Partial Reconfiguration (PR) is the most important function for FME. It allows reconfiguration for given Port/Accelerated Function Unit (AFU). It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges, and invokes fpga-region's interface (fpga_region_program_fpga) for PR operation once PR request received via ioctl. Below user space interface is exposed by this sub feature. Ioctl interface: * DFL_FPGA_FME_PORT_PR Do partial reconfiguration per information from userspace, including target port(AFU), buffer size and address info. It returns error code to userspace if failed. For detailed PR error information, user needs to read fpga-mgr's status sysfs interface.
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| @@ -14,6 +14,7 @@ · 13 unmodified lines | ||
| 14 | 14 | #ifndef _UAPI_LINUX_FPGA_DFL_H |
| 15 | 15 | #define _UAPI_LINUX_FPGA_DFL_H |
| 16 | 16 | |
| 17 | +#include <linux/types.h> | |
| 17 | 18 | #include <linux/ioctl.h> |
| 18 | 19 | |
| 19 | 20 | #define DFL_FPGA_API_VERSION 0 |
| @@ -28,6 +29,7 @@ · 8 unmodified lines | ||
| 28 | 29 | #define DFL_FPGA_MAGIC 0xB6 |
| 29 | 30 | |
| 30 | 31 | #define DFL_FPGA_BASE 0 |
| 32 | +#define DFL_FME_BASE 0x80 | |
| 31 | 33 | |
| 32 | 34 | /** |
| 33 | 35 | * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) |
| @@ -47,4 +49,29 @@ · 13 unmodified lines | ||
| 47 | 49 | |
| 48 | 50 | #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) |
| 49 | 51 | |
| 52 | +/* IOCTLs for FME file descriptor */ | |
| 53 | + | |
| 54 | +/** | |
| 55 | + * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0, | |
| 56 | + * struct dfl_fpga_fme_port_pr) | |
| 57 | + * | |
| 58 | + * Driver does Partial Reconfiguration based on Port ID and Buffer (Image) | |
| 59 | + * provided by caller. | |
| 60 | + * Return: 0 on success, -errno on failure. | |
| 61 | + * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected | |
| 62 | + * some errors during PR, under this case, the user can fetch HW error info | |
| 63 | + * from the status of FME's fpga manager. | |
| 64 | + */ | |
| 65 | + | |
| 66 | +struct dfl_fpga_fme_port_pr { | |
| 67 | + /* Input */ | |
| 68 | + __u32 argsz; /* Structure length */ | |
| 69 | + __u32 flags; /* Zero for now */ | |
| 70 | + __u32 port_id; | |
| 71 | + __u32 buffer_size; | |
| 72 | + __u64 buffer_address; /* Userspace address to the buffer for PR */ | |
| 73 | +}; | |
| 74 | + | |
| 75 | +#define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) | |
| 76 | + | |
| 50 | 77 | #endif /* _UAPI_LINUX_FPGA_DFL_H */ |