Unified · Split
| @@ -30,7 +30,7 @@ · 29 unmodified lines | ||
| 30 | 30 | /* Please note that modifications to all structs defined here are |
| 31 | 31 | * subject to backwards-compatibility constraints. |
| 32 | 32 | * |
| 33 | − * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel | |
| 33 | + * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel | |
| 34 | 34 | * compatibility Keep fields aligned to their size |
| 35 | 35 | */ |
| 36 | 36 | |
| @@ -45,88 +45,88 @@ · 8 unmodified lines | ||
| 45 | 45 | #define DRM_VIRTGPU_GET_CAPS 0x09 |
| 46 | 46 | |
| 47 | 47 | struct drm_virtgpu_map { |
| 48 | − uint64_t offset; /* use for mmap system call */ | |
| 49 | − uint32_t handle; | |
| 50 | − uint32_t pad; | |
| 48 | + __u64 offset; /* use for mmap system call */ | |
| 49 | + __u32 handle; | |
| 50 | + __u32 pad; | |
| 51 | 51 | }; |
| 52 | 52 | |
| 53 | 53 | struct drm_virtgpu_execbuffer { |
| 54 | − uint32_t flags; /* for future use */ | |
| 55 | − uint32_t size; | |
| 56 | − uint64_t command; /* void* */ | |
| 57 | − uint64_t bo_handles; | |
| 58 | − uint32_t num_bo_handles; | |
| 59 | − uint32_t pad; | |
| 54 | + __u32 flags; /* for future use */ | |
| 55 | + __u32 size; | |
| 56 | + __u64 command; /* void* */ | |
| 57 | + __u64 bo_handles; | |
| 58 | + __u32 num_bo_handles; | |
| 59 | + __u32 pad; | |
| 60 | 60 | }; |
| 61 | 61 | |
| 62 | 62 | #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ |
| 63 | 63 | |
| 64 | 64 | struct drm_virtgpu_getparam { |
| 65 | − uint64_t param; | |
| 66 | − uint64_t value; | |
| 65 | + __u64 param; | |
| 66 | + __u64 value; | |
| 67 | 67 | }; |
| 68 | 68 | |
| 69 | 69 | /* NO_BO flags? NO resource flag? */ |
| 70 | 70 | /* resource flag for y_0_top */ |
| 71 | 71 | struct drm_virtgpu_resource_create { |
| 72 | − uint32_t target; | |
| 73 | − uint32_t format; | |
| 74 | − uint32_t bind; | |
| 75 | − uint32_t width; | |
| 76 | − uint32_t height; | |
| 77 | − uint32_t depth; | |
| 78 | − uint32_t array_size; | |
| 79 | − uint32_t last_level; | |
| 80 | − uint32_t nr_samples; | |
| 81 | − uint32_t flags; | |
| 82 | − uint32_t bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ | |
| 83 | − uint32_t res_handle; /* returned by kernel */ | |
| 84 | − uint32_t size; /* validate transfer in the host */ | |
| 85 | − uint32_t stride; /* validate transfer in the host */ | |
| 72 | + __u32 target; | |
| 73 | + __u32 format; | |
| 74 | + __u32 bind; | |
| 75 | + __u32 width; | |
| 76 | + __u32 height; | |
| 77 | + __u32 depth; | |
| 78 | + __u32 array_size; | |
| 79 | + __u32 last_level; | |
| 80 | + __u32 nr_samples; | |
| 81 | + __u32 flags; | |
| 82 | + __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ | |
| 83 | + __u32 res_handle; /* returned by kernel */ | |
| 84 | + __u32 size; /* validate transfer in the host */ | |
| 85 | + __u32 stride; /* validate transfer in the host */ | |
| 86 | 86 | }; |
| 87 | 87 | |
| 88 | 88 | struct drm_virtgpu_resource_info { |
| 89 | − uint32_t bo_handle; | |
| 90 | − uint32_t res_handle; | |
| 91 | − uint32_t size; | |
| 92 | − uint32_t stride; | |
| 89 | + __u32 bo_handle; | |
| 90 | + __u32 res_handle; | |
| 91 | + __u32 size; | |
| 92 | + __u32 stride; | |
| 93 | 93 | }; |
| 94 | 94 | |
| 95 | 95 | struct drm_virtgpu_3d_box { |
| 96 | − uint32_t x; | |
| 97 | − uint32_t y; | |
| 98 | − uint32_t z; | |
| 99 | − uint32_t w; | |
| 100 | − uint32_t h; | |
| 101 | − uint32_t d; | |
| 96 | + __u32 x; | |
| 97 | + __u32 y; | |
| 98 | + __u32 z; | |
| 99 | + __u32 w; | |
| 100 | + __u32 h; | |
| 101 | + __u32 d; | |
| 102 | 102 | }; |
| 103 | 103 | |
| 104 | 104 | struct drm_virtgpu_3d_transfer_to_host { |
| 105 | − uint32_t bo_handle; | |
| 105 | + __u32 bo_handle; | |
| 106 | 106 | struct drm_virtgpu_3d_box box; |
| 107 | − uint32_t level; | |
| 108 | − uint32_t offset; | |
| 107 | + __u32 level; | |
| 108 | + __u32 offset; | |
| 109 | 109 | }; |
| 110 | 110 | |
| 111 | 111 | struct drm_virtgpu_3d_transfer_from_host { |
| 112 | − uint32_t bo_handle; | |
| 112 | + __u32 bo_handle; | |
| 113 | 113 | struct drm_virtgpu_3d_box box; |
| 114 | − uint32_t level; | |
| 115 | − uint32_t offset; | |
| 114 | + __u32 level; | |
| 115 | + __u32 offset; | |
| 116 | 116 | }; |
| 117 | 117 | |
| 118 | 118 | #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ |
| 119 | 119 | struct drm_virtgpu_3d_wait { |
| 120 | − uint32_t handle; /* 0 is an invalid handle */ | |
| 121 | − uint32_t flags; | |
| 120 | + __u32 handle; /* 0 is an invalid handle */ | |
| 121 | + __u32 flags; | |
| 122 | 122 | }; |
| 123 | 123 | |
| 124 | 124 | struct drm_virtgpu_get_caps { |
| 125 | − uint32_t cap_set_id; | |
| 126 | − uint32_t cap_set_ver; | |
| 127 | − uint64_t addr; | |
| 128 | − uint32_t size; | |
| 129 | − uint32_t pad; | |
| 125 | + __u32 cap_set_id; | |
| 126 | + __u32 cap_set_ver; | |
| 127 | + __u64 addr; | |
| 128 | + __u32 size; | |
| 129 | + __u32 pad; | |
| 130 | 130 | }; |
| 131 | 131 | |
| 132 | 132 | #define DRM_IOCTL_VIRTGPU_MAP \ |