[PATCH] ppc32: board-specific part of fs_enet update

This contains board-specific portion to respect driver changes (for 8272ads , 885ads and 866ads). Altered platform_data structures as well as initial setup routines relevant to fs_enet. Changes to the mpc8560ads ppc/ code are also introduced, but mainly as reference, since the entire board support is going to appear in arch/powerpc.

Vitaly Bordug committed 20 years ago

Commit 2ca2d5e1 parent 5b4b84515 files · +578 −391Browse files

Unified · Split

15 files

arch/ppc/platforms/85xx/mpc8560_ads.c +89 −0
arch/ppc/platforms/85xx/mpc85xx_ads_common.h +19 −0
arch/ppc/platforms/mpc8272ads_setup.c +85 −69
arch/ppc/platforms/mpc866ads_setup.c +96 −96
arch/ppc/platforms/mpc885ads_setup.c +66 −109
arch/ppc/platforms/pq2ads_pd.h +0 −82
arch/ppc/syslib/mpc85xx_devices.c +86 −3
arch/ppc/syslib/mpc8xx_devices.c +8 −0
arch/ppc/syslib/mpc8xx_sys.c +4 −2
arch/ppc/syslib/pq2_devices.c +5 −0
arch/ppc/syslib/pq2_sys.c +2 −1
include/asm-ppc/cpm2.h +95 −0
include/asm-ppc/mpc8260.h +1 −0
include/asm-ppc/mpc8xx.h +1 −0
include/linux/fs_enet_pd.h +21 −29

arch/ppc/platforms/85xx/mpc8560_ads.c+89−0

@@ -29,6 +29,7 @@ · 28 unmodified lines
29	29	#include <linux/initrd.h>
30	30	#include <linux/module.h>
31	31	#include <linux/fsl_devices.h>
	32	+#include <linux/fs_enet_pd.h>
32	33
33	34	#include <asm/system.h>
34	35	#include <asm/pgtable.h>
@@ -58,6 +59,71 @@ · 23 unmodified lines
58	59	* Setup the architecture
59	60	*
60	61	*/
	62	+static void init_fcc_ioports(void)
	63	+{
	64	+ struct immap *immap;
	65	+ struct io_port *io;
	66	+ u32 tempval;
	67	+
	68	+ immap = cpm2_immr;
	69	+
	70	+ io = &immap->im_ioport;
	71	+ /* FCC2/3 are on the ports B/C. */
	72	+ tempval = in_be32(&io->iop_pdirb);
	73	+ tempval &= ~PB2_DIRB0;
	74	+ tempval \|= PB2_DIRB1;
	75	+ out_be32(&io->iop_pdirb, tempval);
	76	+
	77	+ tempval = in_be32(&io->iop_psorb);
	78	+ tempval &= ~PB2_PSORB0;
	79	+ tempval \|= PB2_PSORB1;
	80	+ out_be32(&io->iop_psorb, tempval);
	81	+
	82	+ tempval = in_be32(&io->iop_pparb);
	83	+ tempval \|= (PB2_DIRB0 \| PB2_DIRB1);
	84	+ out_be32(&io->iop_pparb, tempval);
	85	+
	86	+ tempval = in_be32(&io->iop_pdirb);
	87	+ tempval &= ~PB3_DIRB0;
	88	+ tempval \|= PB3_DIRB1;
	89	+ out_be32(&io->iop_pdirb, tempval);
	90	+
	91	+ tempval = in_be32(&io->iop_psorb);
	92	+ tempval &= ~PB3_PSORB0;
	93	+ tempval \|= PB3_PSORB1;
	94	+ out_be32(&io->iop_psorb, tempval);
	95	+
	96	+ tempval = in_be32(&io->iop_pparb);
	97	+ tempval \|= (PB3_DIRB0 \| PB3_DIRB1);
	98	+ out_be32(&io->iop_pparb, tempval);
	99	+
	100	+ tempval = in_be32(&io->iop_pdirc);
	101	+ tempval \|= PC3_DIRC1;
	102	+ out_be32(&io->iop_pdirc, tempval);
	103	+
	104	+ tempval = in_be32(&io->iop_pparc);
	105	+ tempval \|= PC3_DIRC1;
	106	+ out_be32(&io->iop_pparc, tempval);
	107	+
	108	+ /* Port C has clocks...... */
	109	+ tempval = in_be32(&io->iop_psorc);
	110	+ tempval &= ~(CLK_TRX);
	111	+ out_be32(&io->iop_psorc, tempval);
	112	+
	113	+ tempval = in_be32(&io->iop_pdirc);
	114	+ tempval &= ~(CLK_TRX);
	115	+ out_be32(&io->iop_pdirc, tempval);
	116	+ tempval = in_be32(&io->iop_pparc);
	117	+ tempval \|= (CLK_TRX);
	118	+ out_be32(&io->iop_pparc, tempval);
	119	+
	120	+ /* Configure Serial Interface clock routing.
	121	+ * First, clear all FCC bits to zero,
	122	+ * then set the ones we want.
	123	+ */
	124	+ immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
	125	+ immap->im_cpmux.cmx_fcr \|= CPMUX_CLK_ROUTE;
	126	+}
61	127
62	128	static void __init
63	129	mpc8560ads_setup_arch(void)
@@ -66,6 +132,7 @@ mpc8560ads_setup_arch(void) · 2 unmodified lines
66	132	unsigned int freq;
67	133	struct gianfar_platform_data *pdata;
68	134	struct gianfar_mdio_data *mdata;
	135	+ struct fs_platform_info *fpi;
69	136
70	137	cpm2_reset();
71	138
@@ -110,6 +177,28 @@ mpc8560ads_setup_arch(void) · 38 unmodified lines
110	177	memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
111	178	}
112	179
	180	+ init_fcc_ioports();
	181	+ ppc_sys_device_remove(MPC85xx_CPM_FCC1);
	182	+
	183	+ fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);
	184	+ if (fpi) {
	185	+ memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
	186	+ fpi->bus_id = "0:02";
	187	+ fpi->phy_addr = 2;
	188	+ fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
	189	+ fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];
	190	+ }
	191	+
	192	+ fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);
	193	+ if (fpi) {
	194	+ memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
	195	+ fpi->macaddr[5] += 1;
	196	+ fpi->bus_id = "0:03";
	197	+ fpi->phy_addr = 3;
	198	+ fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
	199	+ fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];
	200	+ }
	201	+
113	202	#ifdef CONFIG_BLK_DEV_INITRD
114	203	if (initrd_start)
115	204	ROOT_DEV = Root_RAM0;

arch/ppc/platforms/85xx/mpc85xx_ads_common.h+19−0

@@ -45,4 +45,23 @@ extern void mpc85xx_ads_map_io(void) __init; · 44 unmodified lines
45	45
46	46	#define MPC85XX_PCI1_IO_SIZE 0x01000000
47	47
	48	+/* FCC1 Clock Source Configuration. These can be
	49	+ * redefined in the board specific file.
	50	+ * Can only choose from CLK9-12 */
	51	+#define F1_RXCLK 12
	52	+#define F1_TXCLK 11
	53	+
	54	+/* FCC2 Clock Source Configuration. These can be
	55	+ * redefined in the board specific file.
	56	+ * Can only choose from CLK13-16 */
	57	+#define F2_RXCLK 13
	58	+#define F2_TXCLK 14
	59	+
	60	+/* FCC3 Clock Source Configuration. These can be
	61	+ * redefined in the board specific file.
	62	+ * Can only choose from CLK13-16 */
	63	+#define F3_RXCLK 15
	64	+#define F3_TXCLK 16
	65	+
	66	+
48	67	#endif /* __MACH_MPC85XX_ADS_H__ */

arch/ppc/platforms/mpc8272ads_setup.c+85−69

@@ -56,64 +56,51 @@ static struct fs_uart_platform_info mpc8272_uart_pdata[] = { · 55 unmodified lines
56	56	},
57	57	};
58	58
59		−static struct fs_mii_bus_info mii_bus_info = {
60		− .method = fsmii_bitbang,
61		− .id = 0,
62		− .i.bitbang = {
63		− .mdio_port = fsiop_portc,
64		− .mdio_bit = 18,
65		− .mdc_port = fsiop_portc,
66		− .mdc_bit = 19,
67		− .delay = 1,
68		− },
69		−};
70		−
71		−static struct fs_platform_info mpc82xx_fcc1_pdata = {
72		− .fs_no = fsid_fcc1,
73		− .cp_page = CPM_CR_FCC1_PAGE,
74		− .cp_block = CPM_CR_FCC1_SBLOCK,
75		− .clk_trx = (PC_F1RXCLK \| PC_F1TXCLK),
76		− .clk_route = CMX1_CLK_ROUTE,
77		− .clk_mask = CMX1_CLK_MASK,
78		− .init_ioports = init_fcc1_ioports,
79		−
80		− .phy_addr = 0,
81		−#ifdef PHY_INTERRUPT
82		− .phy_irq = PHY_INTERRUPT,
83		−#else
84		− .phy_irq = -1;
85		−#endif
86		− .mem_offset = FCC1_MEM_OFFSET,
87		− .bus_info = &mii_bus_info,
88		− .rx_ring = 32,
89		− .tx_ring = 32,
90		− .rx_copybreak = 240,
91		− .use_napi = 0,
92		− .napi_weight = 17,
	59	+static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = {
	60	+ .mdio_dat.bit = 18,
	61	+ .mdio_dir.bit = 18,
	62	+ .mdc_dat.bit = 19,
	63	+ .delay = 1,
93	64	};
94	65
95		−static struct fs_platform_info mpc82xx_fcc2_pdata = {
96		− .fs_no = fsid_fcc2,
97		− .cp_page = CPM_CR_FCC2_PAGE,
98		− .cp_block = CPM_CR_FCC2_SBLOCK,
99		− .clk_trx = (PC_F2RXCLK \| PC_F2TXCLK),
100		− .clk_route = CMX2_CLK_ROUTE,
101		− .clk_mask = CMX2_CLK_MASK,
102		− .init_ioports = init_fcc2_ioports,
103		−
104		− .phy_addr = 3,
105		−#ifdef PHY_INTERRUPT
106		− .phy_irq = PHY_INTERRUPT,
107		−#else
108		− .phy_irq = -1;
109		−#endif
110		− .mem_offset = FCC2_MEM_OFFSET,
111		− .bus_info = &mii_bus_info,
112		− .rx_ring = 32,
113		− .tx_ring = 32,
114		− .rx_copybreak = 240,
115		− .use_napi = 0,
116		− .napi_weight = 17,
	66	+static struct fs_platform_info mpc82xx_enet_pdata[] = {
	67	+ [fsid_fcc1] = {
	68	+ .fs_no = fsid_fcc1,
	69	+ .cp_page = CPM_CR_FCC1_PAGE,
	70	+ .cp_block = CPM_CR_FCC1_SBLOCK,
	71	+
	72	+ .clk_trx = (PC_F1RXCLK \| PC_F1TXCLK),
	73	+ .clk_route = CMX1_CLK_ROUTE,
	74	+ .clk_mask = CMX1_CLK_MASK,
	75	+ .init_ioports = init_fcc1_ioports,
	76	+
	77	+ .mem_offset = FCC1_MEM_OFFSET,
	78	+
	79	+ .rx_ring = 32,
	80	+ .tx_ring = 32,
	81	+ .rx_copybreak = 240,
	82	+ .use_napi = 0,
	83	+ .napi_weight = 17,
	84	+ .bus_id = "0:00",
	85	+ },
	86	+ [fsid_fcc2] = {
	87	+ .fs_no = fsid_fcc2,
	88	+ .cp_page = CPM_CR_FCC2_PAGE,
	89	+ .cp_block = CPM_CR_FCC2_SBLOCK,
	90	+ .clk_trx = (PC_F2RXCLK \| PC_F2TXCLK),
	91	+ .clk_route = CMX2_CLK_ROUTE,
	92	+ .clk_mask = CMX2_CLK_MASK,
	93	+ .init_ioports = init_fcc2_ioports,
	94	+
	95	+ .mem_offset = FCC2_MEM_OFFSET,
	96	+
	97	+ .rx_ring = 32,
	98	+ .tx_ring = 32,
	99	+ .rx_copybreak = 240,
	100	+ .use_napi = 0,
	101	+ .napi_weight = 17,
	102	+ .bus_id = "0:03",
	103	+ },
117	104	};
118	105
119	106	static void init_fcc1_ioports(void)
@@ -209,20 +196,21 @@ static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev, · 89 unmodified lines
209	196	bd_t* bi = (void*)__res;
210	197	int fs_no = fsid_fcc1+pdev->id-1;
211	198
212		− mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;
213		− mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c;
214		−
215		− switch(fs_no) {
216		− case fsid_fcc1:
217		− memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
218		− pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
219		− break;
220		− case fsid_fcc2:
221		− memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
222		− mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
223		− pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
224		− break;
	199	+ if(fs_no > ARRAY_SIZE(mpc82xx_enet_pdata)) {
	200	+ return;
225	201	}
	202	+
	203	+ mpc82xx_enet_pdata[fs_no].dpram_offset=
	204	+ (u32)cpm2_immr->im_dprambase;
	205	+ mpc82xx_enet_pdata[fs_no].fcc_regs_c =
	206	+ (u32)cpm2_immr->im_fcc_c;
	207	+ memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6);
	208	+
	209	+ /* prevent dup mac */
	210	+ if(fs_no == fsid_fcc2)
	211	+ mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1;
	212	+
	213	+ pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no];
226	214	}
227	215
228	216	static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
@@ -274,6 +262,29 @@ static void init_scc4_uart_ioports(void) · 45 unmodified lines
274	262	iounmap(immap);
275	263	}
276	264
	265	+static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev,
	266	+ int idx)
	267	+{
	268	+ m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT;
	269	+ m82xx_mii_bb_pdata.irq[1] = -1;
	270	+ m82xx_mii_bb_pdata.irq[2] = -1;
	271	+ m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT;
	272	+ m82xx_mii_bb_pdata.irq[31] = -1;
	273	+
	274	+
	275	+ m82xx_mii_bb_pdata.mdio_dat.offset =
	276	+ (u32)&cpm2_immr->im_ioport.iop_pdatc;
	277	+
	278	+ m82xx_mii_bb_pdata.mdio_dir.offset =
	279	+ (u32)&cpm2_immr->im_ioport.iop_pdirc;
	280	+
	281	+ m82xx_mii_bb_pdata.mdc_dat.offset =
	282	+ (u32)&cpm2_immr->im_ioport.iop_pdatc;
	283	+
	284	+
	285	+ pdev->dev.platform_data = &m82xx_mii_bb_pdata;
	286	+}
	287	+
277	288	static int mpc8272ads_platform_notify(struct device *dev)
278	289	{
279	290	static const struct platform_notify_dev_map dev_map[] = {
@@ -285,6 +296,10 @@ static int mpc8272ads_platform_notify(struct device *dev) · 5 unmodified lines
285	296	.bus_id = "fsl-cpm-scc:uart",
286	297	.rtn = mpc8272ads_fixup_uart_pdata,
287	298	},
	299	+ {
	300	+ .bus_id = "fsl-bb-mdio",
	301	+ .rtn = mpc8272ads_fixup_mdio_pdata,
	302	+ },
288	303	{
289	304	.bus_id = NULL
290	305	}
@@ -319,6 +334,7 @@ int __init mpc8272ads_init(void) · 28 unmodified lines
319	334	ppc_sys_device_enable(MPC82xx_CPM_SCC4);
320	335	#endif
321	336
	337	+ ppc_sys_device_enable(MPC82xx_MDIO_BB);
322	338
323	339	return 0;
324	340	}

arch/ppc/platforms/mpc866ads_setup.c+96−96

@@ -1,10 +1,10 @@
1		−/*arch/ppc/platforms/mpc885ads-setup.c
	1	+/*arch/ppc/platforms/mpc866ads-setup.c
2	2	*
3		− * Platform setup for the Freescale mpc885ads board
	3	+ * Platform setup for the Freescale mpc866ads board
4	4	*
5	5	* Vitaly Bordug <vbordug@ru.mvista.com>
6	6	*
7		− * Copyright 2005 MontaVista Software Inc.
	7	+ * Copyright 2005-2006 MontaVista Software Inc.
8	8	*
9	9	* This file is licensed under the terms of the GNU General Public License
10	10	* version 2. This program is licensed "as is" without any warranty of any
@@ -42,49 +42,36 @@ static void setup_scc1_ioports(void); · 31 unmodified lines
42	42	static void setup_smc1_ioports(void);
43	43	static void setup_smc2_ioports(void);
44	44
45		−static struct fs_mii_bus_info fec_mii_bus_info = {
46		− .method = fsmii_fec,
47		− .id = 0,
48		−};
49		−
50		−static struct fs_mii_bus_info scc_mii_bus_info = {
51		− .method = fsmii_fixed,
52		− .id = 0,
53		− .i.fixed.speed = 10,
54		− .i.fixed.duplex = 0,
55		−};
	45	+static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
56	46
57		−static struct fs_platform_info mpc8xx_fec_pdata[] = {
58		− {
59		− .rx_ring = 128,
60		− .tx_ring = 16,
61		− .rx_copybreak = 240,
	47	+static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
62	48
63		− .use_napi = 1,
64		− .napi_weight = 17,
	49	+static struct fs_platform_info mpc8xx_enet_pdata[] = {
	50	+ [fsid_fec1] = {
	51	+ .rx_ring = 128,
	52	+ .tx_ring = 16,
	53	+ .rx_copybreak = 240,
65	54
66		− .phy_addr = 15,
67		− .phy_irq = -1,
	55	+ .use_napi = 1,
	56	+ .napi_weight = 17,
68	57
69		− .use_rmii = 0,
	58	+ .init_ioports = setup_fec1_ioports,
70	59
71		− .bus_info = &fec_mii_bus_info,
72		− }
73		−};
	60	+ .bus_id = "0:0f",
	61	+ .has_phy = 1,
	62	+ },
	63	+ [fsid_scc1] = {
	64	+ .rx_ring = 64,
	65	+ .tx_ring = 8,
	66	+ .rx_copybreak = 240,
	67	+ .use_napi = 1,
	68	+ .napi_weight = 17,
74	69
75		−static struct fs_platform_info mpc8xx_scc_pdata = {
76		− .rx_ring = 64,
77		− .tx_ring = 8,
78		− .rx_copybreak = 240,
79	70
80		− .use_napi = 1,
81		− .napi_weight = 17,
82		−
83		− .phy_addr = -1,
84		− .phy_irq = -1,
85		−
86		− .bus_info = &scc_mii_bus_info,
	71	+ .init_ioports = setup_scc1_ioports,
87	72
	73	+ .bus_id = "fixed@100:1",
	74	+ },
88	75	};
89	76
90	77	static struct fs_uart_platform_info mpc866_uart_pdata[] = {
@@ -207,63 +194,6 @@ static void setup_scc1_ioports(void) · 116 unmodified lines
207	194
208	195	}
209	196
210		−static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
211		−{
212		− struct fs_platform_info *fpi = pdev->dev.platform_data;
213		−
214		− volatile cpm8xx_t *cp;
215		− bd_t bd = (bd_t ) __res;
216		− char *e;
217		− int i;
218		−
219		− /* Get pointer to Communication Processor */
220		− cp = cpmp;
221		− switch (fs_no) {
222		− case fsid_fec1:
223		− fpi = &mpc8xx_fec_pdata[0];
224		− fpi->init_ioports = &setup_fec1_ioports;
225		−
226		− break;
227		− case fsid_scc1:
228		− fpi = &mpc8xx_scc_pdata;
229		− fpi->init_ioports = &setup_scc1_ioports;
230		−
231		− break;
232		− default:
233		− printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
234		− return;
235		− }
236		−
237		− pdev->dev.platform_data = fpi;
238		− fpi->fs_no = fs_no;
239		−
240		− e = (unsigned char *)&bd->bi_enetaddr;
241		− for (i = 0; i < 6; i++)
242		− fpi->macaddr[i] = *e++;
243		−
244		− fpi->macaddr[5 - pdev->id]++;
245		−
246		−}
247		−
248		−static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
249		− int idx)
250		−{
251		− /* This is for FEC devices only */
252		− if (!pdev \|\| !pdev->name \|\| (!strstr(pdev->name, "fsl-cpm-fec")))
253		− return;
254		− mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
255		−}
256		−
257		−static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
258		− int idx)
259		−{
260		− /* This is for SCC devices only */
261		− if (!pdev \|\| !pdev->name \|\| (!strstr(pdev->name, "fsl-cpm-scc")))
262		− return;
263		−
264		− mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
265		−}
266		−
267	197	static void setup_smc1_ioports(void)
268	198	{
269	199	immap_t immap = (immap_t ) IMAP_ADDR;
@@ -315,6 +245,56 @@ static void setup_smc2_ioports(void) · 45 unmodified lines
315	245
316	246	}
317	247
	248	+static int ma_count = 0;
	249	+
	250	+static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
	251	+{
	252	+ struct fs_platform_info *fpi;
	253	+
	254	+ volatile cpm8xx_t *cp;
	255	+ bd_t bd = (bd_t ) __res;
	256	+ char *e;
	257	+ int i;
	258	+
	259	+ /* Get pointer to Communication Processor */
	260	+ cp = cpmp;
	261	+
	262	+ if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {
	263	+ printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
	264	+ return;
	265	+ }
	266	+
	267	+
	268	+ fpi = &mpc8xx_enet_pdata[fs_no];
	269	+ fpi->fs_no = fs_no;
	270	+ pdev->dev.platform_data = fpi;
	271	+
	272	+ e = (unsigned char *)&bd->bi_enetaddr;
	273	+ for (i = 0; i < 6; i++)
	274	+ fpi->macaddr[i] = *e++;
	275	+
	276	+ fpi->macaddr[5] += ma_count++;
	277	+}
	278	+
	279	+static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
	280	+ int idx)
	281	+{
	282	+ /* This is for FEC devices only */
	283	+ if (!pdev \|\| !pdev->name \|\| (!strstr(pdev->name, "fsl-cpm-fec")))
	284	+ return;
	285	+ mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
	286	+}
	287	+
	288	+static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
	289	+ int idx)
	290	+{
	291	+ /* This is for SCC devices only */
	292	+ if (!pdev \|\| !pdev->name \|\| (!strstr(pdev->name, "fsl-cpm-scc")))
	293	+ return;
	294	+
	295	+ mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
	296	+}
	297	+
318	298	static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev,
319	299	int idx)
320	300	{
@@ -359,6 +339,9 @@ static int mpc866ads_platform_notify(struct device *dev) · 38 unmodified lines
359	339
360	340	int __init mpc866ads_init(void)
361	341	{
	342	+ bd_t bd = (bd_t ) __res;
	343	+ struct fs_mii_fec_platform_info* fmpi;
	344	+
362	345	printk(KERN_NOTICE "mpc866ads: Init\n");
363	346
364	347	platform_notify = mpc866ads_platform_notify;
@@ -366,11 +349,20 @@ int __init mpc866ads_init(void) · 1 unmodified line
366	349	ppc_sys_device_initfunc();
367	350	ppc_sys_device_disable_all();
368	351
369		−#ifdef MPC8xx_SECOND_ETH_SCC1
	352	+#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1
370	353	ppc_sys_device_enable(MPC8xx_CPM_SCC1);
371	354	#endif
372	355	ppc_sys_device_enable(MPC8xx_CPM_FEC1);
373	356
	357	+ ppc_sys_device_enable(MPC8xx_MDIO_FEC);
	358	+
	359	+ fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
	360	+ &mpc8xx_mdio_fec_pdata;
	361	+
	362	+ fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
	363	+ /* No PHY interrupt line here */
	364	+ fmpi->irq[0xf] = -1;
	365	+
374	366	/* Since either of the uarts could be used as console, they need to ready */
375	367	#ifdef CONFIG_SERIAL_CPM_SMC1
376	368	ppc_sys_device_enable(MPC8xx_CPM_SMC1);
@@ -381,6 +373,14 @@ int __init mpc866ads_init(void) · 4 unmodified lines
381	373	ppc_sys_device_enable(MPC8xx_CPM_SMC2);
382	374	ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
383	375	#endif
	376	+ ppc_sys_device_enable(MPC8xx_MDIO_FEC);
	377	+
	378	+ fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
	379	+ &mpc8xx_mdio_fec_pdata;
	380	+
	381	+ fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
	382	+ /* No PHY interrupt line here */
	383	+ fmpi->irq[0xf] = -1;
384	384
385	385	return 0;
386	386	}

arch/ppc/platforms/mpc885ads_setup.c+66−109

@@ -38,7 +38,10 @@ extern unsigned char __res[]; · 37 unmodified lines
38	38	static void setup_smc1_ioports(void);
39	39	static void setup_smc2_ioports(void);
40	40
41		−static void __init mpc885ads_scc_phy_init(char);
	41	+static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
	42	+static void setup_fec1_ioports(void);
	43	+static void setup_fec2_ioports(void);
	44	+static void setup_scc3_ioports(void);
42	45
43	46	static struct fs_uart_platform_info mpc885_uart_pdata[] = {
44	47	[fsid_smc1_uart] = {
@@ -61,23 +64,8 @@ static struct fs_uart_platform_info mpc885_uart_pdata[] = { · 16 unmodified lines
61	64	},
62	65	};
63	66
64		−static struct fs_mii_bus_info fec_mii_bus_info = {
65		− .method = fsmii_fec,
66		− .id = 0,
67		−};
68		−
69		−static struct fs_mii_bus_info scc_mii_bus_info = {
70		−#ifdef CONFIG_SCC_ENET_8xx_FIXED
71		− .method = fsmii_fixed,
72		−#else
73		− .method = fsmii_fec,
74		−#endif
75		−
76		− .id = 0,
77		−};
78		−
79		−static struct fs_platform_info mpc8xx_fec_pdata[] = {
80		− {
	67	+static struct fs_platform_info mpc8xx_enet_pdata[] = {
	68	+ [fsid_fec1] = {
81	69	.rx_ring = 128,
82	70	.tx_ring = 16,
83	71	.rx_copybreak = 240,
@@ -85,11 +73,12 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = { · 1 unmodified line
85	73	.use_napi = 1,
86	74	.napi_weight = 17,
87	75
88		− .phy_addr = 0,
89		− .phy_irq = SIU_IRQ7,
	76	+ .init_ioports = setup_fec1_ioports,
90	77
91		− .bus_info = &fec_mii_bus_info,
92		− }, {
	78	+ .bus_id = "0:00",
	79	+ .has_phy = 1,
	80	+ },
	81	+ [fsid_fec2] = {
93	82	.rx_ring = 128,
94	83	.tx_ring = 16,
95	84	.rx_copybreak = 240,
@@ -97,35 +86,32 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = { · 1 unmodified line
97	86	.use_napi = 1,
98	87	.napi_weight = 17,
99	88
100		− .phy_addr = 1,
101		− .phy_irq = SIU_IRQ7,
102		−
103		− .bus_info = &fec_mii_bus_info,
104		− }
105		−};
	89	+ .init_ioports = setup_fec2_ioports,
106	90
107		−static struct fs_platform_info mpc8xx_scc_pdata = {
108		− .rx_ring = 64,
109		− .tx_ring = 8,
110		− .rx_copybreak = 240,
	91	+ .bus_id = "0:01",
	92	+ .has_phy = 1,
	93	+ },
	94	+ [fsid_scc3] = {
	95	+ .rx_ring = 64,
	96	+ .tx_ring = 8,
	97	+ .rx_copybreak = 240,
111	98
112		− .use_napi = 1,
113		− .napi_weight = 17,
	99	+ .use_napi = 1,
	100	+ .napi_weight = 17,
114	101
115		− .phy_addr = 2,
116		−#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED
117		− .phy_irq = -1,
	102	+ .init_ioports = setup_scc3_ioports,
	103	+#ifdef CONFIG_FIXED_MII_10_FDX
	104	+ .bus_id = "fixed@100:1",
118	105	#else
119		− .phy_irq = SIU_IRQ7,
120		−#endif
121		−
122		− .bus_info = &scc_mii_bus_info,
	106	+ .bus_id = "0:02",
	107	+ #endif
	108	+ },
123	109	};
124	110
125	111	void __init board_init(void)
126	112	{
127		− volatile cpm8xx_t *cp = cpmp;
128		− unsigned int *bcsr_io;
	113	+ cpm8xx_t *cp = cpmp;
	114	+ unsigned int *bcsr_io;
129	115
130	116	#ifdef CONFIG_FS_ENET
131	117	immap_t immap = (immap_t ) IMAP_ADDR;
@@ -164,6 +150,14 @@ void __init board_init(void) · 32 unmodified lines
164	150	/* use MDC for MII (common) */
165	151	setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
166	152	clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
	153	+ bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
	154	+ clrbits32(bcsr_io,BCSR5_MII1_EN);
	155	+ clrbits32(bcsr_io,BCSR5_MII1_RST);
	156	+#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
	157	+ clrbits32(bcsr_io,BCSR5_MII2_EN);
	158	+ clrbits32(bcsr_io,BCSR5_MII2_RST);
	159	+#endif
	160	+ iounmap(bcsr_io);
167	161	#endif
168	162	}
169	163
@@ -194,8 +188,8 @@ static void setup_fec2_ioports(void) · 24 unmodified lines
194	188	/* configure FEC2 pins */
195	189	setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
196	190	setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
197		− setbits32(&immap->im_cpm.cp_peso, 0x00037800);
198	191	clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
	192	+ setbits32(&immap->im_cpm.cp_peso, 0x00037800);
199	193	clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
200	194	}
201	195
@@ -213,6 +207,8 @@ static void setup_scc3_ioports(void) · 11 unmodified lines
213	207
214	208	/* Enable the PHY.
215	209	*/
	210	+ clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
	211	+ udelay(1000);
216	212	setbits32(bcsr_io+4, BCSR4_ETH10_RST);
217	213	/* Configure port A pins for Txd and Rxd.
218	214	*/
@@ -254,37 +250,38 @@ static void setup_scc3_ioports(void) · 35 unmodified lines
254	250	clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
255	251	setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
256	252
257		− setbits32(bcsr_io+1, BCSR1_ETHEN);
	253	+ setbits32(bcsr_io+4, BCSR1_ETHEN);
258	254	iounmap(bcsr_io);
259	255	}
260	256
	257	+static int mac_count = 0;
	258	+
261	259	static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
262	260	{
263		− struct fs_platform_info *fpi = pdev->dev.platform_data;
264		−
265		− volatile cpm8xx_t *cp;
	261	+ struct fs_platform_info *fpi;
266	262	bd_t bd = (bd_t ) __res;
267	263	char *e;
268	264	int i;
269	265
270		− /* Get pointer to Communication Processor */
271		− cp = cpmp;
	266	+ if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {
	267	+ printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
	268	+ return;
	269	+ }
	270	+
	271	+ fpi = &mpc8xx_enet_pdata[fs_no];
	272	+
272	273	switch (fs_no) {
273	274	case fsid_fec1:
274		− fpi = &mpc8xx_fec_pdata[0];
275	275	fpi->init_ioports = &setup_fec1_ioports;
276	276	break;
277	277	case fsid_fec2:
278		− fpi = &mpc8xx_fec_pdata[1];
279	278	fpi->init_ioports = &setup_fec2_ioports;
280	279	break;
281	280	case fsid_scc3:
282		− fpi = &mpc8xx_scc_pdata;
283	281	fpi->init_ioports = &setup_scc3_ioports;
284		− mpc885ads_scc_phy_init(fpi->phy_addr);
285	282	break;
286	283	default:
287		− printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
	284	+ printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
288	285	return;
289	286	}
290	287
@@ -295,7 +292,7 @@ static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) · 4 unmodified lines
295	292	for (i = 0; i < 6; i++)
296	293	fpi->macaddr[i] = *e++;
297	294
298		− fpi->macaddr[5 - pdev->id]++;
	295	+ fpi->macaddr[5] += mac_count++;
299	296
300	297	}
301	298
@@ -318,58 +315,6 @@ static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev, · 16 unmodified lines
318	315	mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
319	316	}
320	317
321		−/* SCC ethernet controller does not have MII management channel. FEC1 MII
322		− * channel is used to communicate with the 10Mbit PHY.
323		− */
324		−
325		−#define MII_ECNTRL_PINMUX 0x4
326		−#define FEC_ECNTRL_PINMUX 0x00000004
327		−#define FEC_RCNTRL_MII_MODE 0x00000004
328		−
329		−/* Make MII read/write commands.
330		− */
331		−#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 \| (((REG) & 0x1f) << 18) \| \
332		− ((VAL) & 0xffff) \| ((PHY_ADDR) << 23))
333		−
334		−static void mpc885ads_scc_phy_init(char phy_addr)
335		−{
336		− volatile immap_t *immap;
337		− volatile fec_t *fecp;
338		− bd_t *bd;
339		−
340		− bd = (bd_t *) __res;
341		− immap = (immap_t ) IMAP_ADDR; / pointer to internal registers */
342		− fecp = &(immap->im_cpm.cp_fec);
343		−
344		− /* Enable MII pins of the FEC1
345		− */
346		− setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
347		− clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
348		− /* Set MII speed to 2.5 MHz
349		− */
350		− out_be32(&fecp->fec_mii_speed,
351		− ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1);
352		−
353		− /* Enable FEC pin MUX
354		− */
355		− setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
356		− setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
357		−
358		− out_be32(&fecp->fec_mii_data,
359		− mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr));
360		− udelay(100);
361		− out_be32(&fecp->fec_mii_data,
362		− mk_mii_write(MII_ADVERTISE,
363		− ADVERTISE_10HALF \| ADVERTISE_CSMA, phy_addr));
364		− udelay(100);
365		−
366		− /* Disable FEC MII settings
367		− */
368		− clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
369		− clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
370		− out_be32(&fecp->fec_mii_speed, 0);
371		−}
372		−
373	318	static void setup_smc1_ioports(void)
374	319	{
375	320	immap_t immap = (immap_t ) IMAP_ADDR;
@@ -462,6 +407,9 @@ static int mpc885ads_platform_notify(struct device *dev) · 86 unmodified lines
462	407
463	408	int __init mpc885ads_init(void)
464	409	{
	410	+ struct fs_mii_fec_platform_info* fmpi;
	411	+ bd_t bd = (bd_t ) __res;
	412	+
465	413	printk(KERN_NOTICE "mpc885ads: Init\n");
466	414
467	415	platform_notify = mpc885ads_platform_notify;
@@ -471,8 +419,17 @@ int __init mpc885ads_init(void) · 3 unmodified lines
471	419
472	420	ppc_sys_device_enable(MPC8xx_CPM_FEC1);
473	421
	422	+ ppc_sys_device_enable(MPC8xx_MDIO_FEC);
	423	+ fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
	424	+ &mpc8xx_mdio_fec_pdata;
	425	+
	426	+ fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
	427	+
	428	+ /* No PHY interrupt line here */
	429	+ fmpi->irq[0xf] = SIU_IRQ7;
	430	+
474	431	#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
475		− ppc_sys_device_enable(MPC8xx_CPM_SCC1);
	432	+ ppc_sys_device_enable(MPC8xx_CPM_SCC3);
476	433
477	434	#endif
478	435	#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2

arch/ppc/platforms/pq2ads_pd.h+0−82

@@ -29,86 +29,4 @@ · 28 unmodified lines
29	29	#define F3_RXCLK 13
30	30	#define F3_TXCLK 14
31	31
32		−/* Automatically generates register configurations */
33		−#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
34		−
35		−#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
36		−#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
37		−#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
38		−#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
39		−#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
40		−#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
41		−
42		−#define PC_F1RXCLK PC_CLK(F1_RXCLK)
43		−#define PC_F1TXCLK PC_CLK(F1_TXCLK)
44		−#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) \| CMXFCR_TF1CS(F1_TXCLK))
45		−#define CMX1_CLK_MASK ((uint)0xff000000)
46		−
47		−#define PC_F2RXCLK PC_CLK(F2_RXCLK)
48		−#define PC_F2TXCLK PC_CLK(F2_TXCLK)
49		−#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) \| CMXFCR_TF2CS(F2_TXCLK))
50		−#define CMX2_CLK_MASK ((uint)0x00ff0000)
51		−
52		−#define PC_F3RXCLK PC_CLK(F3_RXCLK)
53		−#define PC_F3TXCLK PC_CLK(F3_TXCLK)
54		−#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) \| CMXFCR_TF3CS(F3_TXCLK))
55		−#define CMX3_CLK_MASK ((uint)0x0000ff00)
56		−
57		−/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
58		− * but there is little variation among the choices.
59		− */
60		−#define PA1_COL 0x00000001U
61		−#define PA1_CRS 0x00000002U
62		−#define PA1_TXER 0x00000004U
63		−#define PA1_TXEN 0x00000008U
64		−#define PA1_RXDV 0x00000010U
65		−#define PA1_RXER 0x00000020U
66		−#define PA1_TXDAT 0x00003c00U
67		−#define PA1_RXDAT 0x0003c000U
68		−#define PA1_PSORA0 (PA1_RXDAT \| PA1_TXDAT)
69		−#define PA1_PSORA1 (PA1_COL \| PA1_CRS \| PA1_TXER \| PA1_TXEN \| \
70		− PA1_RXDV \| PA1_RXER)
71		−#define PA1_DIRA0 (PA1_RXDAT \| PA1_CRS \| PA1_COL \| PA1_RXER \| PA1_RXDV)
72		−#define PA1_DIRA1 (PA1_TXDAT \| PA1_TXEN \| PA1_TXER)
73		−
74		−
75		−/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
76		− * but there is little variation among the choices.
77		− */
78		−#define PB2_TXER 0x00000001U
79		−#define PB2_RXDV 0x00000002U
80		−#define PB2_TXEN 0x00000004U
81		−#define PB2_RXER 0x00000008U
82		−#define PB2_COL 0x00000010U
83		−#define PB2_CRS 0x00000020U
84		−#define PB2_TXDAT 0x000003c0U
85		−#define PB2_RXDAT 0x00003c00U
86		−#define PB2_PSORB0 (PB2_RXDAT \| PB2_TXDAT \| PB2_CRS \| PB2_COL \| \
87		− PB2_RXER \| PB2_RXDV \| PB2_TXER)
88		−#define PB2_PSORB1 (PB2_TXEN)
89		−#define PB2_DIRB0 (PB2_RXDAT \| PB2_CRS \| PB2_COL \| PB2_RXER \| PB2_RXDV)
90		−#define PB2_DIRB1 (PB2_TXDAT \| PB2_TXEN \| PB2_TXER)
91		−
92		−
93		−/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
94		− * but there is little variation among the choices.
95		− */
96		−#define PB3_RXDV 0x00004000U
97		−#define PB3_RXER 0x00008000U
98		−#define PB3_TXER 0x00010000U
99		−#define PB3_TXEN 0x00020000U
100		−#define PB3_COL 0x00040000U
101		−#define PB3_CRS 0x00080000U
102		−#define PB3_TXDAT 0x0f000000U
103		−#define PB3_RXDAT 0x00f00000U
104		−#define PB3_PSORB0 (PB3_RXDAT \| PB3_TXDAT \| PB3_CRS \| PB3_COL \| \
105		− PB3_RXER \| PB3_RXDV \| PB3_TXER \| PB3_TXEN)
106		−#define PB3_PSORB1 0
107		−#define PB3_DIRB0 (PB3_RXDAT \| PB3_CRS \| PB3_COL \| PB3_RXER \| PB3_RXDV)
108		−#define PB3_DIRB1 (PB3_TXDAT \| PB3_TXEN \| PB3_TXER)
109		−
110		−#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
111		−#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
112		−#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
113		−
114	32	#endif

arch/ppc/syslib/mpc85xx_devices.c+86−3

@@ -16,9 +16,11 @@ · 15 unmodified lines
16	16	#include <linux/device.h>
17	17	#include <linux/serial_8250.h>
18	18	#include <linux/fsl_devices.h>
	19	+#include <linux/fs_enet_pd.h>
19	20	#include <asm/mpc85xx.h>
20	21	#include <asm/irq.h>
21	22	#include <asm/ppc_sys.h>
	23	+#include <asm/cpm2.h>
22	24
23	25	/* We use offsets for IORESOURCE_MEM since we do not know at compile time
24	26	* what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
@@ -82,6 +84,60 @@ static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = { · 57 unmodified lines
82	84	.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
83	85	};
84	86
	87	+static struct fs_platform_info mpc85xx_fcc1_pdata = {
	88	+ .fs_no = fsid_fcc1,
	89	+ .cp_page = CPM_CR_FCC1_PAGE,
	90	+ .cp_block = CPM_CR_FCC1_SBLOCK,
	91	+
	92	+ .rx_ring = 32,
	93	+ .tx_ring = 32,
	94	+ .rx_copybreak = 240,
	95	+ .use_napi = 0,
	96	+ .napi_weight = 17,
	97	+
	98	+ .clk_mask = CMX1_CLK_MASK,
	99	+ .clk_route = CMX1_CLK_ROUTE,
	100	+ .clk_trx = (PC_F1RXCLK \| PC_F1TXCLK),
	101	+
	102	+ .mem_offset = FCC1_MEM_OFFSET,
	103	+};
	104	+
	105	+static struct fs_platform_info mpc85xx_fcc2_pdata = {
	106	+ .fs_no = fsid_fcc2,
	107	+ .cp_page = CPM_CR_FCC2_PAGE,
	108	+ .cp_block = CPM_CR_FCC2_SBLOCK,
	109	+
	110	+ .rx_ring = 32,
	111	+ .tx_ring = 32,
	112	+ .rx_copybreak = 240,
	113	+ .use_napi = 0,
	114	+ .napi_weight = 17,
	115	+
	116	+ .clk_mask = CMX2_CLK_MASK,
	117	+ .clk_route = CMX2_CLK_ROUTE,
	118	+ .clk_trx = (PC_F2RXCLK \| PC_F2TXCLK),
	119	+
	120	+ .mem_offset = FCC2_MEM_OFFSET,
	121	+};
	122	+
	123	+static struct fs_platform_info mpc85xx_fcc3_pdata = {
	124	+ .fs_no = fsid_fcc3,
	125	+ .cp_page = CPM_CR_FCC3_PAGE,
	126	+ .cp_block = CPM_CR_FCC3_SBLOCK,
	127	+
	128	+ .rx_ring = 32,
	129	+ .tx_ring = 32,
	130	+ .rx_copybreak = 240,
	131	+ .use_napi = 0,
	132	+ .napi_weight = 17,
	133	+
	134	+ .clk_mask = CMX3_CLK_MASK,
	135	+ .clk_route = CMX3_CLK_ROUTE,
	136	+ .clk_trx = (PC_F3RXCLK \| PC_F3TXCLK),
	137	+
	138	+ .mem_offset = FCC3_MEM_OFFSET,
	139	+};
	140	+
85	141	static struct plat_serial8250_port serial_platform_data[] = {
86	142	[0] = {
87	143	.mapbase = 0x4500,
@@ -318,18 +374,27 @@ struct platform_device ppc_sys_platform_devices[] = { · 230 unmodified lines
318	374	[MPC85xx_CPM_FCC1] = {
319	375	.name = "fsl-cpm-fcc",
320	376	.id = 1,
321		− .num_resources = 3,
	377	+ .num_resources = 4,
	378	+ .dev.platform_data = &mpc85xx_fcc1_pdata,
322	379	.resource = (struct resource[]) {
323	380	{
	381	+ .name = "fcc_regs",
324	382	.start = 0x91300,
325	383	.end = 0x9131F,
326	384	.flags = IORESOURCE_MEM,
327	385	},
328	386	{
	387	+ .name = "fcc_regs_c",
329	388	.start = 0x91380,
330	389	.end = 0x9139F,
331	390	.flags = IORESOURCE_MEM,
332	391	},
	392	+ {
	393	+ .name = "fcc_pram",
	394	+ .start = 0x88400,
	395	+ .end = 0x884ff,
	396	+ .flags = IORESOURCE_MEM,
	397	+ },
333	398	{
334	399	.start = SIU_INT_FCC1,
335	400	.end = SIU_INT_FCC1,
@@ -340,18 +405,27 @@ struct platform_device ppc_sys_platform_devices[] = { · 4 unmodified lines
340	405	[MPC85xx_CPM_FCC2] = {
341	406	.name = "fsl-cpm-fcc",
342	407	.id = 2,
343		− .num_resources = 3,
	408	+ .num_resources = 4,
	409	+ .dev.platform_data = &mpc85xx_fcc2_pdata,
344	410	.resource = (struct resource[]) {
345	411	{
	412	+ .name = "fcc_regs",
346	413	.start = 0x91320,
347	414	.end = 0x9133F,
348	415	.flags = IORESOURCE_MEM,
349	416	},
350	417	{
	418	+ .name = "fcc_regs_c",
351	419	.start = 0x913A0,
352	420	.end = 0x913CF,
353	421	.flags = IORESOURCE_MEM,
354	422	},
	423	+ {
	424	+ .name = "fcc_pram",
	425	+ .start = 0x88500,
	426	+ .end = 0x885ff,
	427	+ .flags = IORESOURCE_MEM,
	428	+ },
355	429	{
356	430	.start = SIU_INT_FCC2,
357	431	.end = SIU_INT_FCC2,
@@ -362,18 +436,27 @@ struct platform_device ppc_sys_platform_devices[] = { · 4 unmodified lines
362	436	[MPC85xx_CPM_FCC3] = {
363	437	.name = "fsl-cpm-fcc",
364	438	.id = 3,
365		− .num_resources = 3,
	439	+ .num_resources = 4,
	440	+ .dev.platform_data = &mpc85xx_fcc3_pdata,
366	441	.resource = (struct resource[]) {
367	442	{
	443	+ .name = "fcc_regs",
368	444	.start = 0x91340,
369	445	.end = 0x9135F,
370	446	.flags = IORESOURCE_MEM,
371	447	},
372	448	{
	449	+ .name = "fcc_regs_c",
373	450	.start = 0x913D0,
374	451	.end = 0x913FF,
375	452	.flags = IORESOURCE_MEM,
376	453	},
	454	+ {
	455	+ .name = "fcc_pram",
	456	+ .start = 0x88600,
	457	+ .end = 0x886ff,
	458	+ .flags = IORESOURCE_MEM,
	459	+ },
377	460	{
378	461	.start = SIU_INT_FCC3,
379	462	.end = SIU_INT_FCC3,

arch/ppc/syslib/mpc8xx_devices.c+8−0

@@ -218,6 +218,14 @@ struct platform_device ppc_sys_platform_devices[] = { · 217 unmodified lines
218	218	},
219	219	},
220	220	},
	221	+
	222	+ [MPC8xx_MDIO_FEC] = {
	223	+ .name = "fsl-cpm-fec-mdio",
	224	+ .id = 0,
	225	+ .num_resources = 0,
	226	+
	227	+ },
	228	+
221	229	};
222	230
223	231	static int __init mach_mpc8xx_fixup(struct platform_device *pdev)

arch/ppc/syslib/mpc8xx_sys.c+4−2

@@ -22,7 +22,7 @@ struct ppc_sys_spec ppc_sys_specs[] = { · 21 unmodified lines
22	22	.ppc_sys_name = "MPC86X",
23	23	.mask = 0xFFFFFFFF,
24	24	.value = 0x00000000,
25		− .num_devices = 7,
	25	+ .num_devices = 8,
26	26	.device_list = (enum ppc_sys_devices[])
27	27	{
28	28	MPC8xx_CPM_FEC1,
@@ -32,13 +32,14 @@ struct ppc_sys_spec ppc_sys_specs[] = { · 3 unmodified lines
32	32	MPC8xx_CPM_SCC4,
33	33	MPC8xx_CPM_SMC1,
34	34	MPC8xx_CPM_SMC2,
	35	+ MPC8xx_MDIO_FEC,
35	36	},
36	37	},
37	38	{
38	39	.ppc_sys_name = "MPC885",
39	40	.mask = 0xFFFFFFFF,
40	41	.value = 0x00000000,
41		− .num_devices = 8,
	42	+ .num_devices = 9,
42	43	.device_list = (enum ppc_sys_devices[])
43	44	{
44	45	MPC8xx_CPM_FEC1,
@@ -49,6 +50,7 @@ struct ppc_sys_spec ppc_sys_specs[] = { · 4 unmodified lines
49	50	MPC8xx_CPM_SCC4,
50	51	MPC8xx_CPM_SMC1,
51	52	MPC8xx_CPM_SMC2,
	53	+ MPC8xx_MDIO_FEC,
52	54	},
53	55	},
54	56	{ /* default match */

arch/ppc/syslib/pq2_devices.c+5−0

@@ -369,6 +369,11 @@ struct platform_device ppc_sys_platform_devices[] = { · 368 unmodified lines
369	369	},
370	370	},
371	371	},
	372	+ [MPC82xx_MDIO_BB] = {
	373	+ .name = "fsl-bb-mdio",
	374	+ .id = 0,
	375	+ .num_resources = 0,
	376	+ },
372	377	};
373	378
374	379	static int __init mach_mpc82xx_fixup(struct platform_device *pdev)

arch/ppc/syslib/pq2_sys.c+2−1

@@ -139,13 +139,14 @@ struct ppc_sys_spec ppc_sys_specs[] = { · 138 unmodified lines
139	139	.ppc_sys_name = "8272",
140	140	.mask = 0x0000ff00,
141	141	.value = 0x00000c00,
142		− .num_devices = 12,
	142	+ .num_devices = 13,
143	143	.device_list = (enum ppc_sys_devices[])
144	144	{
145	145	MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
146	146	MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4,
147	147	MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
148	148	MPC82xx_CPM_I2C, MPC82xx_CPM_USB, MPC82xx_SEC1,
	149	+ MPC82xx_MDIO_BB,
149	150	},
150	151	},
151	152	/* below is a list of the 8280 family of processors */

include/asm-ppc/cpm2.h+95−0

@@ -1093,5 +1093,100 @@ typedef struct im_idma { · 1092 unmodified lines
1093	1093
1094	1094	#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1095	1095
	1096	+/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
	1097	+ * in order to use clock-computing stuff below for the FCC x
	1098	+ */
	1099	+
	1100	+/* Automatically generates register configurations */
	1101	+#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
	1102	+
	1103	+#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
	1104	+#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
	1105	+#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
	1106	+#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
	1107	+#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
	1108	+#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
	1109	+
	1110	+#define PC_F1RXCLK PC_CLK(F1_RXCLK)
	1111	+#define PC_F1TXCLK PC_CLK(F1_TXCLK)
	1112	+#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) \| CMXFCR_TF1CS(F1_TXCLK))
	1113	+#define CMX1_CLK_MASK ((uint)0xff000000)
	1114	+
	1115	+#define PC_F2RXCLK PC_CLK(F2_RXCLK)
	1116	+#define PC_F2TXCLK PC_CLK(F2_TXCLK)
	1117	+#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) \| CMXFCR_TF2CS(F2_TXCLK))
	1118	+#define CMX2_CLK_MASK ((uint)0x00ff0000)
	1119	+
	1120	+#define PC_F3RXCLK PC_CLK(F3_RXCLK)
	1121	+#define PC_F3TXCLK PC_CLK(F3_TXCLK)
	1122	+#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) \| CMXFCR_TF3CS(F3_TXCLK))
	1123	+#define CMX3_CLK_MASK ((uint)0x0000ff00)
	1124	+
	1125	+#define CPMUX_CLK_MASK (CMX3_CLK_MASK \| CMX2_CLK_MASK)
	1126	+#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE \| CMX2_CLK_ROUTE)
	1127	+
	1128	+#define CLK_TRX (PC_F3TXCLK \| PC_F3RXCLK \| PC_F2TXCLK \| PC_F2RXCLK)
	1129	+
	1130	+/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
	1131	+ * but there is little variation among the choices.
	1132	+ */
	1133	+#define PA1_COL 0x00000001U
	1134	+#define PA1_CRS 0x00000002U
	1135	+#define PA1_TXER 0x00000004U
	1136	+#define PA1_TXEN 0x00000008U
	1137	+#define PA1_RXDV 0x00000010U
	1138	+#define PA1_RXER 0x00000020U
	1139	+#define PA1_TXDAT 0x00003c00U
	1140	+#define PA1_RXDAT 0x0003c000U
	1141	+#define PA1_PSORA0 (PA1_RXDAT \| PA1_TXDAT)
	1142	+#define PA1_PSORA1 (PA1_COL \| PA1_CRS \| PA1_TXER \| PA1_TXEN \| \
	1143	+ PA1_RXDV \| PA1_RXER)
	1144	+#define PA1_DIRA0 (PA1_RXDAT \| PA1_CRS \| PA1_COL \| PA1_RXER \| PA1_RXDV)
	1145	+#define PA1_DIRA1 (PA1_TXDAT \| PA1_TXEN \| PA1_TXER)
	1146	+
	1147	+
	1148	+/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
	1149	+ * but there is little variation among the choices.
	1150	+ */
	1151	+#define PB2_TXER 0x00000001U
	1152	+#define PB2_RXDV 0x00000002U
	1153	+#define PB2_TXEN 0x00000004U
	1154	+#define PB2_RXER 0x00000008U
	1155	+#define PB2_COL 0x00000010U
	1156	+#define PB2_CRS 0x00000020U
	1157	+#define PB2_TXDAT 0x000003c0U
	1158	+#define PB2_RXDAT 0x00003c00U
	1159	+#define PB2_PSORB0 (PB2_RXDAT \| PB2_TXDAT \| PB2_CRS \| PB2_COL \| \
	1160	+ PB2_RXER \| PB2_RXDV \| PB2_TXER)
	1161	+#define PB2_PSORB1 (PB2_TXEN)
	1162	+#define PB2_DIRB0 (PB2_RXDAT \| PB2_CRS \| PB2_COL \| PB2_RXER \| PB2_RXDV)
	1163	+#define PB2_DIRB1 (PB2_TXDAT \| PB2_TXEN \| PB2_TXER)
	1164	+
	1165	+
	1166	+/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
	1167	+ * but there is little variation among the choices.
	1168	+ */
	1169	+#define PB3_RXDV 0x00004000U
	1170	+#define PB3_RXER 0x00008000U
	1171	+#define PB3_TXER 0x00010000U
	1172	+#define PB3_TXEN 0x00020000U
	1173	+#define PB3_COL 0x00040000U
	1174	+#define PB3_CRS 0x00080000U
	1175	+#define PB3_TXDAT 0x0f000000U
	1176	+#define PC3_TXDAT 0x00000010U
	1177	+#define PB3_RXDAT 0x00f00000U
	1178	+#define PB3_PSORB0 (PB3_RXDAT \| PB3_TXDAT \| PB3_CRS \| PB3_COL \| \
	1179	+ PB3_RXER \| PB3_RXDV \| PB3_TXER \| PB3_TXEN)
	1180	+#define PB3_PSORB1 0
	1181	+#define PB3_DIRB0 (PB3_RXDAT \| PB3_CRS \| PB3_COL \| PB3_RXER \| PB3_RXDV)
	1182	+#define PB3_DIRB1 (PB3_TXDAT \| PB3_TXEN \| PB3_TXER)
	1183	+#define PC3_DIRC1 (PC3_TXDAT)
	1184	+
	1185	+/* Handy macro to specify mem for FCCs*/
	1186	+#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
	1187	+#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
	1188	+#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
	1189	+#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(2)
	1190	+
1096	1191	#endif /* __CPM2__ */
1097	1192	#endif /* __KERNEL__ */

include/asm-ppc/mpc8260.h+1−0

@@ -82,6 +82,7 @@ enum ppc_sys_devices { · 81 unmodified lines
82	82	MPC82xx_CPM_SMC2,
83	83	MPC82xx_CPM_USB,
84	84	MPC82xx_SEC1,
	85	+ MPC82xx_MDIO_BB,
85	86	NUM_PPC_SYS_DEVS,
86	87	};
87	88

include/asm-ppc/mpc8xx.h+1−0

@@ -110,6 +110,7 @@ enum ppc_sys_devices { · 109 unmodified lines
110	110	MPC8xx_CPM_SMC1,
111	111	MPC8xx_CPM_SMC2,
112	112	MPC8xx_CPM_USB,
	113	+ MPC8xx_MDIO_FEC,
113	114	NUM_PPC_SYS_DEVS,
114	115	};
115	116

include/linux/fs_enet_pd.h+21−29

@@ -69,34 +69,21 @@ enum fs_ioport { · 68 unmodified lines
69	69	fsiop_porte,
70	70	};
71	71
72		−struct fs_mii_bus_info {
73		− int method; /* mii method */
74		− int id; /* the id of the mii_bus */
75		− int disable_aneg; /* if the controller needs to negothiate speed & duplex */
76		− int lpa; /* the default board-specific vallues will be applied otherwise */
77		−
78		− union {
79		− struct {
80		− int duplex;
81		− int speed;
82		− } fixed;
83		−
84		− struct {
85		− /* nothing */
86		− } fec;
87		−
88		− struct {
89		− /* nothing */
90		− } scc;
91		−
92		− struct {
93		− int mdio_port; /* port & bit for MDIO */
94		− int mdio_bit;
95		− int mdc_port; /* port & bit for MDC */
96		− int mdc_bit;
97		− int delay; /* delay in us */
98		− } bitbang;
99		− } i;
	72	+struct fs_mii_bit {
	73	+ u32 offset;
	74	+ u8 bit;
	75	+ u8 polarity;
	76	+};
	77	+struct fs_mii_bb_platform_info {
	78	+ struct fs_mii_bit mdio_dir;
	79	+ struct fs_mii_bit mdio_dat;
	80	+ struct fs_mii_bit mdc_dat;
	81	+ int mdio_port; /* port & bit for MDIO */
	82	+ int mdio_bit;
	83	+ int mdc_port; /* port & bit for MDC */
	84	+ int mdc_bit;
	85	+ int delay; /* delay in us */
	86	+ int irq[32]; /* irqs per phy's */
100	87	};
101	88
102	89	struct fs_platform_info {
@@ -119,6 +106,7 @@ struct fs_platform_info { · 16 unmodified lines
119	106	u32 device_flags;
120	107
121	108	int phy_addr; /* the phy address (-1 no phy) */
	109	+ const char* bus_id;
122	110	int phy_irq; /* the phy irq (if it exists) */
123	111
124	112	const struct fs_mii_bus_info *bus_info;
@@ -130,6 +118,10 @@ struct fs_platform_info { · 5 unmodified lines
130	118	int napi_weight; /* NAPI weight */
131	119
132	120	int use_rmii; /* use RMII mode */
	121	+ int has_phy; /* if the network is phy container as well...*/
	122	+};
	123	+struct fs_mii_fec_platform_info {
	124	+ u32 irq[32];
	125	+ u32 mii_speed;
133	126	};
134		−
135	127	#endif

[PATCH] ppc32: board-specific part of fs_enet update

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