amd-drm-next-5.13-2021-03-23: amdgpu: - Debugfs cleanup - Various cleanups and spelling fixes - Flexible array cleanups - Initial AMD Freesync HDMI - Display fixes - 10bpc dithering improvements - Display ASSR support - Clean up and unify powerplay and swsmu interfaces - Vangogh fixes - Add SMU gfx busy queues for RV/PCO - PCIE DPM fixes - S0ix fixes - GPU metrics data fixes - DCN secure display support - Backlight type override - Add initial support for Aldebaran - RAS fixes - Prime fixes for A+A systems - Reset fixes - Initial resource cursor support - Drop legacy IO BAR requirements - Various power fixes amdkfd: - MMU notifier fixes - APU fixes radeon: - Debugfs cleanups - Flexible array cleanups UAPI: - amdgpu: Add a new INFO ioctl interface to query video capabilities rather than hardcoding them in userspace. This allows us to provide fine grained asic capabilities (e.g., if a particular part is bandwidth limited, we can limit the capabilities). Proposed userspace: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps - amdkfd: bump the driver version. There was a problem with reporting some RAS features on older versions of the driver. Proposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/7cdd63475c36bb9f49bb960f90f9a8cdb7e80a21 Danvet: A bunch of conflicts all over, but it seems to compile ... I did put the call to dc_allow_idle_optimizations() on a single line since it looked a bit too jarring to be left alone.
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| @@ -782,6 +782,12 @@ struct drm_amdgpu_cs_chunk_data { · 781 unmodified lines | |||
| 782 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F | 782 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F |
| 783 | /* query ras mask of enabled features*/ | 783 | /* query ras mask of enabled features*/ |
| 784 | #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 | 784 | #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 |
| 785 | /* query video encode/decode caps */ | ||
| 786 | #define AMDGPU_INFO_VIDEO_CAPS 0x21 | ||
| 787 | /* Subquery id: Decode */ | ||
| 788 | #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 | ||
| 789 | /* Subquery id: Encode */ | ||
| 790 | #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 | ||
| 785 | 791 | ||
| 786 | /* RAS MASK: UMC (VRAM) */ | 792 | /* RAS MASK: UMC (VRAM) */ |
| 787 | #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) | 793 | #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) |
| @@ -878,6 +884,10 @@ struct drm_amdgpu_info { · 90 unmodified lines | |||
| 878 | struct { | 884 | struct { |
| 879 | __u32 type; | 885 | __u32 type; |
| 880 | } sensor_info; | 886 | } sensor_info; |
| 887 | |||
| 888 | struct { | ||
| 889 | __u32 type; | ||
| 890 | } video_cap; | ||
| 881 | }; | 891 | }; |
| 882 | }; | 892 | }; |
| 883 | 893 | ||
| @@ -1074,6 +1084,30 @@ struct drm_amdgpu_info_vce_clock_table { · 190 unmodified lines | |||
| 1074 | __u32 pad; | 1084 | __u32 pad; |
| 1075 | }; | 1085 | }; |
| 1076 | 1086 | ||
| 1087 | /* query video encode/decode caps */ | ||
| 1088 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 | ||
| 1089 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 | ||
| 1090 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 | ||
| 1091 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 | ||
| 1092 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 | ||
| 1093 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 | ||
| 1094 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 | ||
| 1095 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 | ||
| 1096 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 | ||
| 1097 | |||
| 1098 | struct drm_amdgpu_info_video_codec_info { | ||
| 1099 | __u32 valid; | ||
| 1100 | __u32 max_width; | ||
| 1101 | __u32 max_height; | ||
| 1102 | __u32 max_pixels_per_frame; | ||
| 1103 | __u32 max_level; | ||
| 1104 | __u32 pad; | ||
| 1105 | }; | ||
| 1106 | |||
| 1107 | struct drm_amdgpu_info_video_caps { | ||
| 1108 | struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; | ||
| 1109 | }; | ||
| 1110 | |||
| 1077 | /* | 1111 | /* |
| 1078 | * Supported GPU families | 1112 | * Supported GPU families |
| 1079 | */ | 1113 | */ |
| @@ -29,9 +29,10 @@ · 28 unmodified lines | |||
| 29 | /* | 29 | /* |
| 30 | * - 1.1 - initial version | 30 | * - 1.1 - initial version |
| 31 | * - 1.3 - Add SMI events support | 31 | * - 1.3 - Add SMI events support |
| 32 | * - 1.4 - Indicate new SRAM EDC bit in device properties | ||
| 32 | */ | 33 | */ |
| 33 | #define KFD_IOCTL_MAJOR_VERSION 1 | 34 | #define KFD_IOCTL_MAJOR_VERSION 1 |
| 34 | #define KFD_IOCTL_MINOR_VERSION 3 | 35 | #define KFD_IOCTL_MINOR_VERSION 4 |
| 35 | 36 | ||
| 36 | struct kfd_ioctl_get_version_args { | 37 | struct kfd_ioctl_get_version_args { |
| 37 | __u32 major_version; /* from KFD */ | 38 | __u32 major_version; /* from KFD */ |
| @@ -351,6 +352,7 @@ struct kfd_ioctl_acquire_vm_args { · 313 unmodified lines | |||
| 351 | #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) | 352 | #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) |
| 352 | #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) | 353 | #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) |
| 353 | #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) | 354 | #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) |
| 355 | #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) | ||
| 354 | 356 | ||
| 355 | /* Allocate memory for later SVM (shared virtual memory) mapping. | 357 | /* Allocate memory for later SVM (shared virtual memory) mapping. |
| 356 | * | 358 | * |