Pull rdma updates from Jason Gunthorpe: "A new Pensando ionic driver, a new Gen 3 HW support for Intel irdma, and lots of small bnxt_re improvements. - Small bug fixes and improves to hfi1, efa, mlx5, erdma, rdmarvt, siw - Allow userspace access to IB service records through the rdmacm - Optimize dma mapping for erdma - Fix shutdown of the GSI QP in mana - Support relaxed ordering MR and fix a corruption bug with mlx5 DMA Data Direct - Many improvement to bnxt_re: - Debugging features and counters - Improve performance of some commands - Change flow_label reporting in completions - Mirror vnic - RDMA flow support - New RDMA driver for Pensando Ethernet devices: ionic - Gen 3 hardware support for the Intel irdma driver - Fix rdma routing resolution with VRFs" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (85 commits) RDMA/ionic: Fix memory leak of admin q_wr RDMA/siw: Always report immediate post SQ errors RDMA/bnxt_re: improve clarity in ALLOC_PAGE handler RDMA/irdma: Remove unused struct irdma_cq fields RDMA/irdma: Fix positive vs negative error codes in irdma_post_send() RDMA/bnxt_re: Remove non-statistics counters from hw_counters RDMA/bnxt_re: Add debugfs info entry for device and resource information RDMA/bnxt_re: Fix incorrect errno used in function comments RDMA: Use %pe format specifier for error pointers RDMA/ionic: Use ether_addr_copy instead of memcpy RDMA/ionic: Fix build failure on SPARC due to xchg() operand size RDMA/rxe: Fix race in do_task() when draining IB/sa: Fix sa_local_svc_timeout_ms read race IB/ipoib: Ignore L3 master device RDMA/core: Use route entry flag to decide on loopback traffic RDMA/core: Resolve MAC of next-hop device without ARP support RDMA/core: Squash a single user static function RDMA/irdma: Update Kconfig RDMA/irdma: Extend CQE Error and Flush Handling for GEN3 Devices RDMA/irdma: Add Atomic Operations support ...
Showing the changes to include/uapi (5 of 128 files). Show all
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| @@ -255,6 +255,7 @@ enum rdma_driver_id { · 254 unmodified lines | ||
| 255 | 255 | RDMA_DRIVER_SIW, |
| 256 | 256 | RDMA_DRIVER_ERDMA, |
| 257 | 257 | RDMA_DRIVER_MANA, |
| 258 | + RDMA_DRIVER_IONIC, | |
| 258 | 259 | }; |
| 259 | 260 | |
| 260 | 261 | enum ib_uverbs_gid_type { |
| @@ -74,4 +74,18 @@ struct ib_user_path_rec { · 73 unmodified lines | ||
| 74 | 74 | __u8 preference; |
| 75 | 75 | }; |
| 76 | 76 | |
| 77 | +struct ib_user_service_rec { | |
| 78 | + __be64 id; | |
| 79 | + __u8 gid[16]; | |
| 80 | + __be16 pkey; | |
| 81 | + __u8 reserved[2]; | |
| 82 | + __be32 lease; | |
| 83 | + __u8 key[16]; | |
| 84 | + __u8 name[64]; | |
| 85 | + __u8 data_8[16]; | |
| 86 | + __be16 data_16[8]; | |
| 87 | + __be32 data_32[4]; | |
| 88 | + __be64 data_64[2]; | |
| 89 | +}; | |
| 90 | + | |
| 77 | 91 | #endif /* IB_USER_SA_H */ |
| @@ -0,0 +1,115 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | +/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc */ | |
| 3 | + | |
| 4 | +#ifndef IONIC_ABI_H | |
| 5 | +#define IONIC_ABI_H | |
| 6 | + | |
| 7 | +#include <linux/types.h> | |
| 8 | + | |
| 9 | +#define IONIC_ABI_VERSION 1 | |
| 10 | + | |
| 11 | +#define IONIC_EXPDB_64 1 | |
| 12 | +#define IONIC_EXPDB_128 2 | |
| 13 | +#define IONIC_EXPDB_256 4 | |
| 14 | +#define IONIC_EXPDB_512 8 | |
| 15 | + | |
| 16 | +#define IONIC_EXPDB_SQ 1 | |
| 17 | +#define IONIC_EXPDB_RQ 2 | |
| 18 | + | |
| 19 | +#define IONIC_CMB_ENABLE 1 | |
| 20 | +#define IONIC_CMB_REQUIRE 2 | |
| 21 | +#define IONIC_CMB_EXPDB 4 | |
| 22 | +#define IONIC_CMB_WC 8 | |
| 23 | +#define IONIC_CMB_UC 16 | |
| 24 | + | |
| 25 | +struct ionic_ctx_req { | |
| 26 | + __u32 rsvd[2]; | |
| 27 | +}; | |
| 28 | + | |
| 29 | +struct ionic_ctx_resp { | |
| 30 | + __u32 rsvd; | |
| 31 | + __u32 page_shift; | |
| 32 | + | |
| 33 | + __aligned_u64 dbell_offset; | |
| 34 | + | |
| 35 | + __u16 version; | |
| 36 | + __u8 qp_opcodes; | |
| 37 | + __u8 admin_opcodes; | |
| 38 | + | |
| 39 | + __u8 sq_qtype; | |
| 40 | + __u8 rq_qtype; | |
| 41 | + __u8 cq_qtype; | |
| 42 | + __u8 admin_qtype; | |
| 43 | + | |
| 44 | + __u8 max_stride; | |
| 45 | + __u8 max_spec; | |
| 46 | + __u8 udma_count; | |
| 47 | + __u8 expdb_mask; | |
| 48 | + __u8 expdb_qtypes; | |
| 49 | + | |
| 50 | + __u8 rsvd2[3]; | |
| 51 | +}; | |
| 52 | + | |
| 53 | +struct ionic_qdesc { | |
| 54 | + __aligned_u64 addr; | |
| 55 | + __u32 size; | |
| 56 | + __u16 mask; | |
| 57 | + __u8 depth_log2; | |
| 58 | + __u8 stride_log2; | |
| 59 | +}; | |
| 60 | + | |
| 61 | +struct ionic_ah_resp { | |
| 62 | + __u32 ahid; | |
| 63 | + __u32 pad; | |
| 64 | +}; | |
| 65 | + | |
| 66 | +struct ionic_cq_req { | |
| 67 | + struct ionic_qdesc cq[2]; | |
| 68 | + __u8 udma_mask; | |
| 69 | + __u8 rsvd[7]; | |
| 70 | +}; | |
| 71 | + | |
| 72 | +struct ionic_cq_resp { | |
| 73 | + __u32 cqid[2]; | |
| 74 | + __u8 udma_mask; | |
| 75 | + __u8 rsvd[7]; | |
| 76 | +}; | |
| 77 | + | |
| 78 | +struct ionic_qp_req { | |
| 79 | + struct ionic_qdesc sq; | |
| 80 | + struct ionic_qdesc rq; | |
| 81 | + __u8 sq_spec; | |
| 82 | + __u8 rq_spec; | |
| 83 | + __u8 sq_cmb; | |
| 84 | + __u8 rq_cmb; | |
| 85 | + __u8 udma_mask; | |
| 86 | + __u8 rsvd[3]; | |
| 87 | +}; | |
| 88 | + | |
| 89 | +struct ionic_qp_resp { | |
| 90 | + __u32 qpid; | |
| 91 | + __u8 sq_cmb; | |
| 92 | + __u8 rq_cmb; | |
| 93 | + __u8 udma_idx; | |
| 94 | + __u8 rsvd[1]; | |
| 95 | + __aligned_u64 sq_cmb_offset; | |
| 96 | + __aligned_u64 rq_cmb_offset; | |
| 97 | +}; | |
| 98 | + | |
| 99 | +struct ionic_srq_req { | |
| 100 | + struct ionic_qdesc rq; | |
| 101 | + __u8 rq_spec; | |
| 102 | + __u8 rq_cmb; | |
| 103 | + __u8 udma_mask; | |
| 104 | + __u8 rsvd[5]; | |
| 105 | +}; | |
| 106 | + | |
| 107 | +struct ionic_srq_resp { | |
| 108 | + __u32 qpid; | |
| 109 | + __u8 rq_cmb; | |
| 110 | + __u8 udma_idx; | |
| 111 | + __u8 rsvd[2]; | |
| 112 | + __aligned_u64 rq_cmb_offset; | |
| 113 | +}; | |
| 114 | + | |
| 115 | +#endif /* IONIC_ABI_H */ | |
| @@ -20,11 +20,14 @@ enum irdma_memreg_type { · 19 unmodified lines | ||
| 20 | 20 | IRDMA_MEMREG_TYPE_MEM = 0, |
| 21 | 21 | IRDMA_MEMREG_TYPE_QP = 1, |
| 22 | 22 | IRDMA_MEMREG_TYPE_CQ = 2, |
| 23 | + IRDMA_MEMREG_TYPE_SRQ = 3, | |
| 23 | 24 | }; |
| 24 | 25 | |
| 25 | 26 | enum { |
| 26 | 27 | IRDMA_ALLOC_UCTX_USE_RAW_ATTR = 1 << 0, |
| 27 | 28 | IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE = 1 << 1, |
| 29 | + IRDMA_ALLOC_UCTX_MAX_HW_SRQ_QUANTA = 1 << 2, | |
| 30 | + IRDMA_SUPPORT_WQE_FORMAT_V2 = 1 << 3, | |
| 28 | 31 | }; |
| 29 | 32 | |
| 30 | 33 | struct irdma_alloc_ucontext_req { |
| @@ -54,7 +57,8 @@ struct irdma_alloc_ucontext_resp { · 23 unmodified lines | ||
| 54 | 57 | __u8 rsvd2; |
| 55 | 58 | __aligned_u64 comp_mask; |
| 56 | 59 | __u16 min_hw_wq_size; |
| 57 | − __u8 rsvd3[6]; | |
| 60 | + __u32 max_hw_srq_quanta; | |
| 61 | + __u8 rsvd3[2]; | |
| 58 | 62 | }; |
| 59 | 63 | |
| 60 | 64 | struct irdma_alloc_pd_resp { |
| @@ -71,6 +75,16 @@ struct irdma_create_cq_req { · 10 unmodified lines | ||
| 71 | 75 | __aligned_u64 user_shadow_area; |
| 72 | 76 | }; |
| 73 | 77 | |
| 78 | +struct irdma_create_srq_req { | |
| 79 | + __aligned_u64 user_srq_buf; | |
| 80 | + __aligned_u64 user_shadow_area; | |
| 81 | +}; | |
| 82 | + | |
| 83 | +struct irdma_create_srq_resp { | |
| 84 | + __u32 srq_id; | |
| 85 | + __u32 srq_size; | |
| 86 | +}; | |
| 87 | + | |
| 74 | 88 | struct irdma_create_qp_req { |
| 75 | 89 | __aligned_u64 user_wqe_bufs; |
| 76 | 90 | __aligned_u64 user_compl_ctx; |
| @@ -67,7 +67,9 @@ enum { · 66 unmodified lines | ||
| 67 | 67 | RDMA_USER_CM_CMD_QUERY, |
| 68 | 68 | RDMA_USER_CM_CMD_BIND, |
| 69 | 69 | RDMA_USER_CM_CMD_RESOLVE_ADDR, |
| 70 | − RDMA_USER_CM_CMD_JOIN_MCAST | |
| 70 | + RDMA_USER_CM_CMD_JOIN_MCAST, | |
| 71 | + RDMA_USER_CM_CMD_RESOLVE_IB_SERVICE, | |
| 72 | + RDMA_USER_CM_CMD_WRITE_CM_EVENT, | |
| 71 | 73 | }; |
| 72 | 74 | |
| 73 | 75 | /* See IBTA Annex A11, servies ID bytes 4 & 5 */ |
| @@ -147,7 +149,8 @@ struct rdma_ucm_resolve_route { · 73 unmodified lines | ||
| 147 | 149 | enum { |
| 148 | 150 | RDMA_USER_CM_QUERY_ADDR, |
| 149 | 151 | RDMA_USER_CM_QUERY_PATH, |
| 150 | − RDMA_USER_CM_QUERY_GID | |
| 152 | + RDMA_USER_CM_QUERY_GID, | |
| 153 | + RDMA_USER_CM_QUERY_IB_SERVICE | |
| 151 | 154 | }; |
| 152 | 155 | |
| 153 | 156 | struct rdma_ucm_query { |
| @@ -187,6 +190,11 @@ struct rdma_ucm_query_path_resp { · 33 unmodified lines | ||
| 187 | 190 | struct ib_path_rec_data path_data[]; |
| 188 | 191 | }; |
| 189 | 192 | |
| 193 | +struct rdma_ucm_query_ib_service_resp { | |
| 194 | + __u32 num_service_recs; | |
| 195 | + struct ib_user_service_rec recs[]; | |
| 196 | +}; | |
| 197 | + | |
| 190 | 198 | struct rdma_ucm_conn_param { |
| 191 | 199 | __u32 qp_num; |
| 192 | 200 | __u32 qkey; |
| @@ -297,6 +305,7 @@ struct rdma_ucm_event_resp { · 104 unmodified lines | ||
| 297 | 305 | union { |
| 298 | 306 | struct rdma_ucm_conn_param conn; |
| 299 | 307 | struct rdma_ucm_ud_param ud; |
| 308 | + __u32 arg32[2]; | |
| 300 | 309 | } param; |
| 301 | 310 | __u32 reserved; |
| 302 | 311 | struct rdma_ucm_ece ece; |
| @@ -338,4 +347,33 @@ struct rdma_ucm_migrate_resp { · 35 unmodified lines | ||
| 338 | 347 | __u32 events_reported; |
| 339 | 348 | }; |
| 340 | 349 | |
| 350 | +enum { | |
| 351 | + RDMA_USER_CM_IB_SERVICE_FLAG_ID = 1 << 0, | |
| 352 | + RDMA_USER_CM_IB_SERVICE_FLAG_NAME = 1 << 1, | |
| 353 | +}; | |
| 354 | + | |
| 355 | +#define RDMA_USER_CM_IB_SERVICE_NAME_SIZE 64 | |
| 356 | +struct rdma_ucm_ib_service { | |
| 357 | + __u64 service_id; | |
| 358 | + __u8 service_name[RDMA_USER_CM_IB_SERVICE_NAME_SIZE]; | |
| 359 | + __u32 flags; | |
| 360 | + __u32 reserved; | |
| 361 | +}; | |
| 362 | + | |
| 363 | +struct rdma_ucm_resolve_ib_service { | |
| 364 | + __u32 id; | |
| 365 | + struct rdma_ucm_ib_service ibs; | |
| 366 | +}; | |
| 367 | + | |
| 368 | +struct rdma_ucm_write_cm_event { | |
| 369 | + __u32 id; | |
| 370 | + __u32 reserved; | |
| 371 | + __u32 event; | |
| 372 | + __u32 status; | |
| 373 | + union { | |
| 374 | + struct rdma_ucm_conn_param conn; | |
| 375 | + struct rdma_ucm_ud_param ud; | |
| 376 | + __u64 arg; | |
| 377 | + } param; | |
| 378 | +}; | |
| 341 | 379 | #endif /* RDMA_USER_CM_H */ |