History

Merge tag 'iommu-fixes-v6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

Pull iommu fixes from Joerg Roedel: - Intel VT-d fixes from Lu Baolu: - Boot kdump kernels with VT-d scalable mode on - Calculate the right page table levels - Fix two recursive locking issues - Fix a lockdep splat issue - AMD IOMMU fixes: - Fix for completion-wait command to use full 64 bits of data - Fix PASID related issue where GPU sound devices failed to initialize - Fix for Virtio-IOMMU to report correct caching behavior, needed for use with VFIO * tag 'iommu-fixes-v6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu: Fix false ownership failure on AMD systems with PASID activated iommu/vt-d: Fix possible recursive locking in intel_iommu_init() iommu/virtio: Fix interaction with VFIO iommu/vt-d: Fix lockdep splat due to klist iteration in atomic context iommu/vt-d: Fix recursive lock issue in iommu_flush_dev_iotlb() iommu/vt-d: Correctly calculate sagaw value of IOMMU iommu/vt-d: Fix kdump kernels boot failure with scalable mode iommu/amd: use full 64-bit value in build_completion_wait()

Linus Torvalds committed 4 years ago

Commit 2ccd4502 parents 134984d 2380f1e8 files · +163 −135Browse files

Unified · Split

8 files
  1. drivers/iommu/amd/iommu.c +2 −1
  2. drivers/iommu/amd/iommu_v2.c +2 −0
  3. drivers/iommu/intel/dmar.c +7 −0
  4. drivers/iommu/intel/iommu.c +113 −128
  5. drivers/iommu/intel/iommu.h +6 −3
  6. drivers/iommu/iommu.c +19 −2
  7. drivers/iommu/virtio-iommu.c +11 −0
  8. include/linux/dmar.h +3 −1
drivers/iommu/amd/iommu.c+2−1
@@ -939,7 +939,8 @@ static void build_completion_wait(struct iommu_cmd *cmd, · 938 unmodified lines
939939 memset(cmd, 0, sizeof(*cmd));
940940 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
941941 cmd->data[1] = upper_32_bits(paddr);
942− cmd->data[2] = data;
942+ cmd->data[2] = lower_32_bits(data);
943+ cmd->data[3] = upper_32_bits(data);
943944 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
944945 }
945946
drivers/iommu/amd/iommu_v2.c+2−0
@@ -777,6 +777,8 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids) · 776 unmodified lines
777777 if (dev_state->domain == NULL)
778778 goto out_free_states;
779779
780+ /* See iommu_is_default_domain() */
781+ dev_state->domain->type = IOMMU_DOMAIN_IDENTITY;
780782 amd_iommu_domain_direct_map(dev_state->domain);
781783
782784 ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
drivers/iommu/intel/dmar.c+7−0
@@ -2349,6 +2349,13 @@ static int dmar_device_hotplug(acpi_handle handle, bool insert) · 2348 unmodified lines
23492349 if (!dmar_in_use())
23502350 return 0;
23512351
2352+ /*
2353+ * It's unlikely that any I/O board is hot added before the IOMMU
2354+ * subsystem is initialized.
2355+ */
2356+ if (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled)
2357+ return -EOPNOTSUPP;
2358+
23522359 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
23532360 tmp = handle;
23542361 } else {
drivers/iommu/intel/iommu.c+113−128
@@ -163,38 +163,6 @@ static phys_addr_t root_entry_uctp(struct root_entry *re) · 162 unmodified lines
163163 return re->hi & VTD_PAGE_MASK;
164164 }
165165
166−static inline void context_clear_pasid_enable(struct context_entry *context)
167−{
168− context->lo &= ~(1ULL << 11);
169−}
170−
171−static inline bool context_pasid_enabled(struct context_entry *context)
172−{
173− return !!(context->lo & (1ULL << 11));
174−}
175−
176−static inline void context_set_copied(struct context_entry *context)
177−{
178− context->hi |= (1ull << 3);
179−}
180−
181−static inline bool context_copied(struct context_entry *context)
182−{
183− return !!(context->hi & (1ULL << 3));
184−}
185−
186−static inline bool __context_present(struct context_entry *context)
187−{
188− return (context->lo & 1);
189−}
190−
191−bool context_present(struct context_entry *context)
192−{
193− return context_pasid_enabled(context) ?
194− __context_present(context) :
195− __context_present(context) && !context_copied(context);
196−}
197−
198166 static inline void context_set_present(struct context_entry *context)
199167 {
200168 context->lo |= 1;
@@ -242,6 +210,26 @@ static inline void context_clear_entry(struct context_entry *context) · 41 unmodified lines
242210 context->hi = 0;
243211 }
244212
213+static inline bool context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)
214+{
215+ if (!iommu->copied_tables)
216+ return false;
217+
218+ return test_bit(((long)bus << 8) | devfn, iommu->copied_tables);
219+}
220+
221+static inline void
222+set_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)
223+{
224+ set_bit(((long)bus << 8) | devfn, iommu->copied_tables);
225+}
226+
227+static inline void
228+clear_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)
229+{
230+ clear_bit(((long)bus << 8) | devfn, iommu->copied_tables);
231+}
232+
245233 /*
246234 * This domain is a statically identity mapping domain.
247235 * 1. This domain creats a static 1:1 mapping to all usable memory.
@@ -402,14 +390,36 @@ static inline int domain_pfn_supported(struct dmar_domain *domain, · 154 unmodified lines
402390 return !(addr_width < BITS_PER_LONG && pfn >> addr_width);
403391 }
404392
393+/*
394+ * Calculate the Supported Adjusted Guest Address Widths of an IOMMU.
395+ * Refer to 11.4.2 of the VT-d spec for the encoding of each bit of
396+ * the returned SAGAW.
397+ */
398+static unsigned long __iommu_calculate_sagaw(struct intel_iommu *iommu)
399+{
400+ unsigned long fl_sagaw, sl_sagaw;
401+
402+ fl_sagaw = BIT(2) | (cap_fl1gp_support(iommu->cap) ? BIT(3) : 0);
403+ sl_sagaw = cap_sagaw(iommu->cap);
404+
405+ /* Second level only. */
406+ if (!sm_supported(iommu) || !ecap_flts(iommu->ecap))
407+ return sl_sagaw;
408+
409+ /* First level only. */
410+ if (!ecap_slts(iommu->ecap))
411+ return fl_sagaw;
412+
413+ return fl_sagaw & sl_sagaw;
414+}
415+
405416 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
406417 {
407418 unsigned long sagaw;
408419 int agaw;
409420
410− sagaw = cap_sagaw(iommu->cap);
411− for (agaw = width_to_agaw(max_gaw);
412− agaw >= 0; agaw--) {
421+ sagaw = __iommu_calculate_sagaw(iommu);
422+ for (agaw = width_to_agaw(max_gaw); agaw >= 0; agaw--) {
413423 if (test_bit(agaw, &sagaw))
414424 break;
415425 }
@@ -505,8 +515,9 @@ static int domain_update_device_node(struct dmar_domain *domain) · 89 unmodified lines
505515 {
506516 struct device_domain_info *info;
507517 int nid = NUMA_NO_NODE;
518+ unsigned long flags;
508519
509− spin_lock(&domain->lock);
520+ spin_lock_irqsave(&domain->lock, flags);
510521 list_for_each_entry(info, &domain->devices, link) {
511522 /*
512523 * There could possibly be multiple device numa nodes as devices
@@ -518,7 +529,7 @@ static int domain_update_device_node(struct dmar_domain *domain) · 5 unmodified lines
518529 if (nid != NUMA_NO_NODE)
519530 break;
520531 }
521− spin_unlock(&domain->lock);
532+ spin_unlock_irqrestore(&domain->lock, flags);
522533
523534 return nid;
524535 }
@@ -578,6 +589,13 @@ struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, · 53 unmodified lines
578589 struct context_entry *context;
579590 u64 *entry;
580591
592+ /*
593+ * Except that the caller requested to allocate a new entry,
594+ * returning a copied context entry makes no sense.
595+ */
596+ if (!alloc && context_copied(iommu, bus, devfn))
597+ return NULL;
598+
581599 entry = &root->lo;
582600 if (sm_supported(iommu)) {
583601 if (devfn >= 0x80) {
@@ -795,32 +813,11 @@ static void free_context_table(struct intel_iommu *iommu) · 211 unmodified lines
795813 }
796814
797815 #ifdef CONFIG_DMAR_DEBUG
798−static void pgtable_walk(struct intel_iommu *iommu, unsigned long pfn, u8 bus, u8 devfn)
816+static void pgtable_walk(struct intel_iommu *iommu, unsigned long pfn,
817+ u8 bus, u8 devfn, struct dma_pte *parent, int level)
799818 {
800− struct device_domain_info *info;
801− struct dma_pte *parent, *pte;
802− struct dmar_domain *domain;
803− struct pci_dev *pdev;
804− int offset, level;
805−
806− pdev = pci_get_domain_bus_and_slot(iommu->segment, bus, devfn);
807− if (!pdev)
808− return;
809−
810− info = dev_iommu_priv_get(&pdev->dev);
811− if (!info || !info->domain) {
812− pr_info("device [%02x:%02x.%d] not probed\n",
813− bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
814− return;
815− }
816−
817− domain = info->domain;
818− level = agaw_to_level(domain->agaw);
819− parent = domain->pgd;
820− if (!parent) {
821− pr_info("no page table setup\n");
822− return;
823− }
819+ struct dma_pte *pte;
820+ int offset;
824821
825822 while (1) {
826823 offset = pfn_level_offset(pfn, level);
@@ -847,9 +844,10 @@ void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, · 20 unmodified lines
847844 struct pasid_entry *entries, *pte;
848845 struct context_entry *ctx_entry;
849846 struct root_entry *rt_entry;
847+ int i, dir_index, index, level;
850848 u8 devfn = source_id & 0xff;
851849 u8 bus = source_id >> 8;
852− int i, dir_index, index;
850+ struct dma_pte *pgtable;
853851
854852 pr_info("Dump %s table entries for IOVA 0x%llx\n", iommu->name, addr);
855853
@@ -877,8 +875,11 @@ void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, · 21 unmodified lines
877875 ctx_entry->hi, ctx_entry->lo);
878876
879877 /* legacy mode does not require PASID entries */
880− if (!sm_supported(iommu))
878+ if (!sm_supported(iommu)) {
879+ level = agaw_to_level(ctx_entry->hi & 7);
880+ pgtable = phys_to_virt(ctx_entry->lo & VTD_PAGE_MASK);
881881 goto pgtable_walk;
882+ }
882883
883884 /* get the pointer to pasid directory entry */
884885 dir = phys_to_virt(ctx_entry->lo & VTD_PAGE_MASK);
@@ -905,8 +906,16 @@ void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, · 20 unmodified lines
905906 for (i = 0; i < ARRAY_SIZE(pte->val); i++)
906907 pr_info("pasid table entry[%d]: 0x%016llx\n", i, pte->val[i]);
907908
909+ if (pasid_pte_get_pgtt(pte) == PASID_ENTRY_PGTT_FL_ONLY) {
910+ level = pte->val[2] & BIT_ULL(2) ? 5 : 4;
911+ pgtable = phys_to_virt(pte->val[2] & VTD_PAGE_MASK);
912+ } else {
913+ level = agaw_to_level((pte->val[0] >> 2) & 0x7);
914+ pgtable = phys_to_virt(pte->val[0] & VTD_PAGE_MASK);
915+ }
916+
908917 pgtable_walk:
909− pgtable_walk(iommu, addr >> VTD_PAGE_SHIFT, bus, devfn);
918+ pgtable_walk(iommu, addr >> VTD_PAGE_SHIFT, bus, devfn, pgtable, level);
910919 }
911920 #endif
912921
@@ -1345,19 +1354,20 @@ iommu_support_dev_iotlb(struct dmar_domain *domain, struct intel_iommu *iommu, · 432 unmodified lines
13451354 u8 bus, u8 devfn)
13461355 {
13471356 struct device_domain_info *info;
1357+ unsigned long flags;
13481358
13491359 if (!iommu->qi)
13501360 return NULL;
13511361
1352− spin_lock(&domain->lock);
1362+ spin_lock_irqsave(&domain->lock, flags);
13531363 list_for_each_entry(info, &domain->devices, link) {
13541364 if (info->iommu == iommu && info->bus == bus &&
13551365 info->devfn == devfn) {
1356− spin_unlock(&domain->lock);
1366+ spin_unlock_irqrestore(&domain->lock, flags);
13571367 return info->ats_supported ? info : NULL;
13581368 }
13591369 }
1360− spin_unlock(&domain->lock);
1370+ spin_unlock_irqrestore(&domain->lock, flags);
13611371
13621372 return NULL;
13631373 }
@@ -1366,8 +1376,9 @@ static void domain_update_iotlb(struct dmar_domain *domain) · 2 unmodified lines
13661376 {
13671377 struct device_domain_info *info;
13681378 bool has_iotlb_device = false;
1379+ unsigned long flags;
13691380
1370− spin_lock(&domain->lock);
1381+ spin_lock_irqsave(&domain->lock, flags);
13711382 list_for_each_entry(info, &domain->devices, link) {
13721383 if (info->ats_enabled) {
13731384 has_iotlb_device = true;
@@ -1375,7 +1386,7 @@ static void domain_update_iotlb(struct dmar_domain *domain) · 1 unmodified line
13751386 }
13761387 }
13771388 domain->has_iotlb_device = has_iotlb_device;
1378− spin_unlock(&domain->lock);
1389+ spin_unlock_irqrestore(&domain->lock, flags);
13791390 }
13801391
13811392 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
@@ -1467,14 +1478,15 @@ static void iommu_flush_dev_iotlb(struct dmar_domain *domain, · 85 unmodified lines
14671478 u64 addr, unsigned mask)
14681479 {
14691480 struct device_domain_info *info;
1481+ unsigned long flags;
14701482
14711483 if (!domain->has_iotlb_device)
14721484 return;
14731485
1474− spin_lock(&domain->lock);
1486+ spin_lock_irqsave(&domain->lock, flags);
14751487 list_for_each_entry(info, &domain->devices, link)
14761488 __iommu_flush_dev_iotlb(info, addr, mask);
1477− spin_unlock(&domain->lock);
1489+ spin_unlock_irqrestore(&domain->lock, flags);
14781490 }
14791491
14801492 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,
@@ -1688,6 +1700,11 @@ static void free_dmar_iommu(struct intel_iommu *iommu) · 207 unmodified lines
16881700 iommu->domain_ids = NULL;
16891701 }
16901702
1703+ if (iommu->copied_tables) {
1704+ bitmap_free(iommu->copied_tables);
1705+ iommu->copied_tables = NULL;
1706+ }
1707+
16911708 /* free context mapping */
16921709 free_context_table(iommu);
16931710
@@ -1913,7 +1930,7 @@ static int domain_context_mapping_one(struct dmar_domain *domain, · 219 unmodified lines
19131930 goto out_unlock;
19141931
19151932 ret = 0;
1916− if (context_present(context))
1933+ if (context_present(context) && !context_copied(iommu, bus, devfn))
19171934 goto out_unlock;
19181935
19191936 /*
@@ -1925,7 +1942,7 @@ static int domain_context_mapping_one(struct dmar_domain *domain, · 5 unmodified lines
19251942 * in-flight DMA will exist, and we don't need to worry anymore
19261943 * hereafter.
19271944 */
1928− if (context_copied(context)) {
1945+ if (context_copied(iommu, bus, devfn)) {
19291946 u16 did_old = context_domain_id(context);
19301947
19311948 if (did_old < cap_ndoms(iommu->cap)) {
@@ -1936,6 +1953,8 @@ static int domain_context_mapping_one(struct dmar_domain *domain, · 4 unmodified lines
19361953 iommu->flush.flush_iotlb(iommu, did_old, 0, 0,
19371954 DMA_TLB_DSI_FLUSH);
19381955 }
1956+
1957+ clear_context_copied(iommu, bus, devfn);
19391958 }
19401959
19411960 context_clear_entry(context);
@@ -2429,6 +2448,7 @@ static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev) · 487 unmodified lines
24292448 {
24302449 struct device_domain_info *info = dev_iommu_priv_get(dev);
24312450 struct intel_iommu *iommu;
2451+ unsigned long flags;
24322452 u8 bus, devfn;
24332453 int ret;
24342454
@@ -2440,9 +2460,9 @@ static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev) · 5 unmodified lines
24402460 if (ret)
24412461 return ret;
24422462 info->domain = domain;
2443− spin_lock(&domain->lock);
2463+ spin_lock_irqsave(&domain->lock, flags);
24442464 list_add(&info->link, &domain->devices);
2445− spin_unlock(&domain->lock);
2465+ spin_unlock_irqrestore(&domain->lock, flags);
24462466
24472467 /* PASID table is mandatory for a PCI device in scalable mode. */
24482468 if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) {
@@ -2684,32 +2704,14 @@ static int copy_context_table(struct intel_iommu *iommu, · 235 unmodified lines
26842704 /* Now copy the context entry */
26852705 memcpy(&ce, old_ce + idx, sizeof(ce));
26862706
2687− if (!__context_present(&ce))
2707+ if (!context_present(&ce))
26882708 continue;
26892709
26902710 did = context_domain_id(&ce);
26912711 if (did >= 0 && did < cap_ndoms(iommu->cap))
26922712 set_bit(did, iommu->domain_ids);
26932713
2694− /*
2695− * We need a marker for copied context entries. This
2696− * marker needs to work for the old format as well as
2697− * for extended context entries.
2698− *
2699− * Bit 67 of the context entry is used. In the old
2700− * format this bit is available to software, in the
2701− * extended format it is the PGE bit, but PGE is ignored
2702− * by HW if PASIDs are disabled (and thus still
2703− * available).
2704− *
2705− * So disable PASIDs first and then mark the entry
2706− * copied. This means that we don't copy PASID
2707− * translations from the old kernel, but this is fine as
2708− * faults there are not fatal.
2709− */
2710− context_clear_pasid_enable(&ce);
2711− context_set_copied(&ce);
2712−
2714+ set_context_copied(iommu, bus, devfn);
27132715 new_ce[idx] = ce;
27142716 }
27152717
@@ -2735,8 +2737,8 @@ static int copy_translation_tables(struct intel_iommu *iommu) · 19 unmodified lines
27352737 bool new_ext, ext;
27362738
27372739 rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG);
2738− ext = !!(rtaddr_reg & DMA_RTADDR_RTT);
2739− new_ext = !!ecap_ecs(iommu->ecap);
2740+ ext = !!(rtaddr_reg & DMA_RTADDR_SMT);
2741+ new_ext = !!sm_supported(iommu);
27402742
27412743 /*
27422744 * The RTT bit can only be changed when translation is disabled,
@@ -2747,6 +2749,10 @@ static int copy_translation_tables(struct intel_iommu *iommu) · 4 unmodified lines
27472749 if (new_ext != ext)
27482750 return -EINVAL;
27492751
2752+ iommu->copied_tables = bitmap_zalloc(BIT_ULL(16), GFP_KERNEL);
2753+ if (!iommu->copied_tables)
2754+ return -ENOMEM;
2755+
27502756 old_rt_phys = rtaddr_reg & VTD_PAGE_MASK;
27512757 if (!old_rt_phys)
27522758 return -EINVAL;
@@ -3013,13 +3019,7 @@ static int __init init_dmars(void) · 260 unmodified lines
30133019
30143020 #ifdef CONFIG_INTEL_IOMMU_SVM
30153021 if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) {
3016− /*
3017− * Call dmar_alloc_hwirq() with dmar_global_lock held,
3018− * could cause possible lock race condition.
3019− */
3020− up_write(&dmar_global_lock);
30213022 ret = intel_svm_enable_prq(iommu);
3022− down_write(&dmar_global_lock);
30233023 if (ret)
30243024 goto free_iommu;
30253025 }
@@ -3932,7 +3932,6 @@ int __init intel_iommu_init(void) · 906 unmodified lines
39323932 force_on = (!intel_iommu_tboot_noforce && tboot_force_iommu()) ||
39333933 platform_optin_force_iommu();
39343934
3935− down_write(&dmar_global_lock);
39363935 if (dmar_table_init()) {
39373936 if (force_on)
39383937 panic("tboot: Failed to initialize DMAR table\n");
@@ -3945,16 +3944,6 @@ int __init intel_iommu_init(void) · 6 unmodified lines
39453944 goto out_free_dmar;
39463945 }
39473946
3948− up_write(&dmar_global_lock);
3949−
3950− /*
3951− * The bus notifier takes the dmar_global_lock, so lockdep will
3952− * complain later when we register it under the lock.
3953− */
3954− dmar_register_bus_notifier();
3955−
3956− down_write(&dmar_global_lock);
3957−
39583947 if (!no_iommu)
39593948 intel_iommu_debugfs_init();
39603949
@@ -3999,11 +3988,9 @@ int __init intel_iommu_init(void) · 38 unmodified lines
39993988 pr_err("Initialization failed\n");
40003989 goto out_free_dmar;
40013990 }
4002− up_write(&dmar_global_lock);
40033991
40043992 init_iommu_pm_ops();
40053993
4006− down_read(&dmar_global_lock);
40073994 for_each_active_iommu(iommu, drhd) {
40083995 /*
40093996 * The flush queue implementation does not perform
@@ -4021,13 +4008,11 @@ int __init intel_iommu_init(void) · 11 unmodified lines
40214008 "%s", iommu->name);
40224009 iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL);
40234010 }
4024− up_read(&dmar_global_lock);
40254011
40264012 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
40274013 if (si_domain && !hw_pass_through)
40284014 register_memory_notifier(&intel_iommu_memory_nb);
40294015
4030− down_read(&dmar_global_lock);
40314016 if (probe_acpi_namespace_devices())
40324017 pr_warn("ACPI name space devices didn't probe correctly\n");
40334018
@@ -4038,17 +4023,15 @@ int __init intel_iommu_init(void) · 4 unmodified lines
40384023
40394024 iommu_disable_protect_mem_regions(iommu);
40404025 }
4041− up_read(&dmar_global_lock);
4042−
4043− pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
40444026
40454027 intel_iommu_enabled = 1;
4028+ dmar_register_bus_notifier();
4029+ pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
40464030
40474031 return 0;
40484032
40494033 out_free_dmar:
40504034 intel_iommu_free_dmars();
4051− up_write(&dmar_global_lock);
40524035 return ret;
40534036 }
40544037
@@ -4080,6 +4063,7 @@ static void dmar_remove_one_dev_info(struct device *dev) · 25 unmodified lines
40804063 struct device_domain_info *info = dev_iommu_priv_get(dev);
40814064 struct dmar_domain *domain = info->domain;
40824065 struct intel_iommu *iommu = info->iommu;
4066+ unsigned long flags;
40834067
40844068 if (!dev_is_real_dma_subdevice(info->dev)) {
40854069 if (dev_is_pci(info->dev) && sm_supported(iommu))
@@ -4091,9 +4075,9 @@ static void dmar_remove_one_dev_info(struct device *dev) · 5 unmodified lines
40914075 intel_pasid_free_table(info->dev);
40924076 }
40934077
4094− spin_lock(&domain->lock);
4078+ spin_lock_irqsave(&domain->lock, flags);
40954079 list_del(&info->link);
4096− spin_unlock(&domain->lock);
4080+ spin_unlock_irqrestore(&domain->lock, flags);
40974081
40984082 domain_detach_iommu(domain, iommu);
40994083 info->domain = NULL;
@@ -4412,19 +4396,20 @@ static void domain_set_force_snooping(struct dmar_domain *domain) · 312 unmodified lines
44124396 static bool intel_iommu_enforce_cache_coherency(struct iommu_domain *domain)
44134397 {
44144398 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4399+ unsigned long flags;
44154400
44164401 if (dmar_domain->force_snooping)
44174402 return true;
44184403
4419− spin_lock(&dmar_domain->lock);
4404+ spin_lock_irqsave(&dmar_domain->lock, flags);
44204405 if (!domain_support_force_snooping(dmar_domain)) {
4421− spin_unlock(&dmar_domain->lock);
4406+ spin_unlock_irqrestore(&dmar_domain->lock, flags);
44224407 return false;
44234408 }
44244409
44254410 domain_set_force_snooping(dmar_domain);
44264411 dmar_domain->force_snooping = true;
4427− spin_unlock(&dmar_domain->lock);
4412+ spin_unlock_irqrestore(&dmar_domain->lock, flags);
44284413
44294414 return true;
44304415 }
drivers/iommu/intel/iommu.h+6−3
@@ -197,7 +197,6 @@ · 196 unmodified lines
197197 #define ecap_dis(e) (((e) >> 27) & 0x1)
198198 #define ecap_nest(e) (((e) >> 26) & 0x1)
199199 #define ecap_mts(e) (((e) >> 25) & 0x1)
200−#define ecap_ecs(e) (((e) >> 24) & 0x1)
201200 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
202201 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
203202 #define ecap_coherent(e) ((e) & 0x1)
@@ -265,7 +264,6 @@ · 61 unmodified lines
265264 #define DMA_GSTS_CFIS (((u32)1) << 23)
266265
267266 /* DMA_RTADDR_REG */
268−#define DMA_RTADDR_RTT (((u64)1) << 11)
269267 #define DMA_RTADDR_SMT (((u64)1) << 10)
270268
271269 /* CCMD_REG */
@@ -579,6 +577,7 @@ struct intel_iommu { · 307 unmodified lines
579577
580578 #ifdef CONFIG_INTEL_IOMMU
581579 unsigned long *domain_ids; /* bitmap of domains */
580+ unsigned long *copied_tables; /* bitmap of copied tables */
582581 spinlock_t lock; /* protect context, domain ids */
583582 struct root_entry *root_entry; /* virtual address */
584583
@@ -701,6 +700,11 @@ static inline int nr_pte_to_next_page(struct dma_pte *pte) · 116 unmodified lines
701700 (struct dma_pte *)ALIGN((unsigned long)pte, VTD_PAGE_SIZE) - pte;
702701 }
703702
703+static inline bool context_present(struct context_entry *context)
704+{
705+ return (context->lo & 1);
706+}
707+
704708 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
705709
706710 extern int dmar_enable_qi(struct intel_iommu *iommu);
@@ -784,7 +788,6 @@ static inline void intel_iommu_debugfs_init(void) {} · 77 unmodified lines
784788 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
785789
786790 extern const struct attribute_group *intel_iommu_groups[];
787−bool context_present(struct context_entry *context);
788791 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
789792 u8 devfn, int alloc);
790793
drivers/iommu/iommu.c+19−2
@@ -3076,6 +3076,24 @@ out: · 3075 unmodified lines
30763076 return ret;
30773077 }
30783078
3079+static bool iommu_is_default_domain(struct iommu_group *group)
3080+{
3081+ if (group->domain == group->default_domain)
3082+ return true;
3083+
3084+ /*
3085+ * If the default domain was set to identity and it is still an identity
3086+ * domain then we consider this a pass. This happens because of
3087+ * amd_iommu_init_device() replacing the default idenytity domain with an
3088+ * identity domain that has a different configuration for AMDGPU.
3089+ */
3090+ if (group->default_domain &&
3091+ group->default_domain->type == IOMMU_DOMAIN_IDENTITY &&
3092+ group->domain && group->domain->type == IOMMU_DOMAIN_IDENTITY)
3093+ return true;
3094+ return false;
3095+}
3096+
30793097 /**
30803098 * iommu_device_use_default_domain() - Device driver wants to handle device
30813099 * DMA through the kernel DMA API.
@@ -3094,8 +3112,7 @@ int iommu_device_use_default_domain(struct device *dev) · 12 unmodified lines
30943112
30953113 mutex_lock(&group->mutex);
30963114 if (group->owner_cnt) {
3097− if (group->domain != group->default_domain ||
3098− group->owner) {
3115+ if (group->owner || !iommu_is_default_domain(group)) {
30993116 ret = -EBUSY;
31003117 goto unlock_out;
31013118 }
drivers/iommu/virtio-iommu.c+11−0
@@ -1006,7 +1006,18 @@ static int viommu_of_xlate(struct device *dev, struct of_phandle_args *args) · 1005 unmodified lines
10061006 return iommu_fwspec_add_ids(dev, args->args, 1);
10071007 }
10081008
1009+static bool viommu_capable(enum iommu_cap cap)
1010+{
1011+ switch (cap) {
1012+ case IOMMU_CAP_CACHE_COHERENCY:
1013+ return true;
1014+ default:
1015+ return false;
1016+ }
1017+}
1018+
10091019 static struct iommu_ops viommu_ops = {
1020+ .capable = viommu_capable,
10101021 .domain_alloc = viommu_domain_alloc,
10111022 .probe_device = viommu_probe_device,
10121023 .probe_finalize = viommu_probe_finalize,
include/linux/dmar.h+3−1
@@ -65,6 +65,7 @@ struct dmar_pci_notify_info { · 64 unmodified lines
6565
6666 extern struct rw_semaphore dmar_global_lock;
6767 extern struct list_head dmar_drhd_units;
68+extern int intel_iommu_enabled;
6869
6970 #define for_each_drhd_unit(drhd) \
7071 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
@@ -88,7 +89,8 @@ extern struct list_head dmar_drhd_units; · 17 unmodified lines
8889 static inline bool dmar_rcu_check(void)
8990 {
9091 return rwsem_is_locked(&dmar_global_lock) ||
91− system_state == SYSTEM_BOOTING;
92+ system_state == SYSTEM_BOOTING ||
93+ (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled);
9294 }
9395
9496 #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())

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