Since 5bfa685e62e9 ("KVM: arm64: vgic: Read HW interrupt pending state from the HW"), we're able to source the pending bit for an interrupt that is stored either on the physical distributor or on a device. However, this state is only available when the vcpu is loaded, and is not intended to be accessed from userspace. Unfortunately, the GICv2 emulation doesn't provide specific userspace accessors, and we fallback with the ones that are intended for the guest, with fatal consequences. Add a new vgic_uaccess_read_pending() accessor for userspace to use, build on top of the existing vgic_mmio_read_pending().
Unified · Split
| @@ -429,11 +429,11 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { · 428 unmodified lines | ||
| 429 | 429 | VGIC_ACCESS_32bit), |
| 430 | 430 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET, |
| 431 | 431 | vgic_mmio_read_pending, vgic_mmio_write_spending, |
| 432 | − NULL, vgic_uaccess_write_spending, 1, | |
| 432 | + vgic_uaccess_read_pending, vgic_uaccess_write_spending, 1, | |
| 433 | 433 | VGIC_ACCESS_32bit), |
| 434 | 434 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR, |
| 435 | 435 | vgic_mmio_read_pending, vgic_mmio_write_cpending, |
| 436 | − NULL, vgic_uaccess_write_cpending, 1, | |
| 436 | + vgic_uaccess_read_pending, vgic_uaccess_write_cpending, 1, | |
| 437 | 437 | VGIC_ACCESS_32bit), |
| 438 | 438 | REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET, |
| 439 | 439 | vgic_mmio_read_active, vgic_mmio_write_sactive, |
| @@ -226,8 +226,9 @@ int vgic_uaccess_write_cenable(struct kvm_vcpu *vcpu, · 225 unmodified lines | ||
| 226 | 226 | return 0; |
| 227 | 227 | } |
| 228 | 228 | |
| 229 | −unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, | |
| 230 | − gpa_t addr, unsigned int len) | |
| 229 | +static unsigned long __read_pending(struct kvm_vcpu *vcpu, | |
| 230 | + gpa_t addr, unsigned int len, | |
| 231 | + bool is_user) | |
| 231 | 232 | { |
| 232 | 233 | u32 intid = VGIC_ADDR_TO_INTID(addr, 1); |
| 233 | 234 | u32 value = 0; |
| @@ -248,7 +249,7 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, · 14 unmodified lines | ||
| 248 | 249 | IRQCHIP_STATE_PENDING, |
| 249 | 250 | &val); |
| 250 | 251 | WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); |
| 251 | − } else if (vgic_irq_is_mapped_level(irq)) { | |
| 252 | + } else if (!is_user && vgic_irq_is_mapped_level(irq)) { | |
| 252 | 253 | val = vgic_get_phys_line_level(irq); |
| 253 | 254 | } else { |
| 254 | 255 | val = irq_is_pending(irq); |
| @@ -263,6 +264,18 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, · 8 unmodified lines | ||
| 263 | 264 | return value; |
| 264 | 265 | } |
| 265 | 266 | |
| 267 | +unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, | |
| 268 | + gpa_t addr, unsigned int len) | |
| 269 | +{ | |
| 270 | + return __read_pending(vcpu, addr, len, false); | |
| 271 | +} | |
| 272 | + | |
| 273 | +unsigned long vgic_uaccess_read_pending(struct kvm_vcpu *vcpu, | |
| 274 | + gpa_t addr, unsigned int len) | |
| 275 | +{ | |
| 276 | + return __read_pending(vcpu, addr, len, true); | |
| 277 | +} | |
| 278 | + | |
| 266 | 279 | static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq) |
| 267 | 280 | { |
| 268 | 281 | return (vgic_irq_is_sgi(irq->intid) && |
| @@ -149,6 +149,9 @@ int vgic_uaccess_write_cenable(struct kvm_vcpu *vcpu, · 148 unmodified lines | ||
| 149 | 149 | unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, |
| 150 | 150 | gpa_t addr, unsigned int len); |
| 151 | 151 | |
| 152 | +unsigned long vgic_uaccess_read_pending(struct kvm_vcpu *vcpu, | |
| 153 | + gpa_t addr, unsigned int len); | |
| 154 | + | |
| 152 | 155 | void vgic_mmio_write_spending(struct kvm_vcpu *vcpu, |
| 153 | 156 | gpa_t addr, unsigned int len, |
| 154 | 157 | unsigned long val); |