qed: FW 8.42.2.0 debug features

Add to debug dump more information on the platform it was collected from (pci func, path id). Provide human readable reg fifo erros. Removed static debug arrays from HSI Functions, and move them to the hwfn. Some structures were slightly changed (removing reserved chip id for example) which lead to many long initializations being modified with one parameter less during initialization. This leads to some long diffs that don't really change anything.

Michal Kalderon committed 6 years ago

Commit 2d22bc81 parent 6bc82d96 files · +1530 −2538Browse files

Unified · Split

6 files

drivers/net/ethernet/qlogic/qed/qed.h +2 −0
drivers/net/ethernet/qlogic/qed/qed_debug.c +1344 −2048
drivers/net/ethernet/qlogic/qed/qed_dev.c +1 −1
drivers/net/ethernet/qlogic/qed/qed_hsi.h +173 −488
drivers/net/ethernet/qlogic/qed/qed_main.c +1 −1
include/linux/qed/qed_if.h +9 −0

drivers/net/ethernet/qlogic/qed/qed.h+2−0

@@ -666,6 +666,7 @@ struct qed_hwfn { · 665 unmodified lines
666	666
667	667	struct dbg_tools_data dbg_info;
668	668	void *dbg_user_info;
	669	+ struct virt_mem_desc dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
669	670
670	671	/* PWM region specific data */
671	672	u16 wid_count;
@@ -877,6 +878,7 @@ struct qed_dev { · 205 unmodified lines
877	878	struct qed_cb_ll2_info *ll2;
878	879	u8 ll2_mac_address[ETH_ALEN];
879	880	#endif
	881	+ struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM];
880	882	bool disable_ilt_dump;
881	883	DECLARE_HASHTABLE(connections, 10);
882	884	const struct firmware *firmware;

drivers/net/ethernet/qlogic/qed/qed_debug.c+1344−2048

@@ -23,27 +23,28 @@ enum mem_groups { · 22 unmodified lines
23	23	MEM_GROUP_BRB_RAM,
24	24	MEM_GROUP_BRB_MEM,
25	25	MEM_GROUP_PRS_MEM,
	26	+ MEM_GROUP_SDM_MEM,
	27	+ MEM_GROUP_PBUF,
26	28	MEM_GROUP_IOR,
	29	+ MEM_GROUP_RAM,
27	30	MEM_GROUP_BTB_RAM,
	31	+ MEM_GROUP_RDIF_CTX,
	32	+ MEM_GROUP_TDIF_CTX,
	33	+ MEM_GROUP_CFC_MEM,
28	34	MEM_GROUP_CONN_CFC_MEM,
29		− MEM_GROUP_TASK_CFC_MEM,
30	35	MEM_GROUP_CAU_PI,
31	36	MEM_GROUP_CAU_MEM,
	37	+ MEM_GROUP_CAU_MEM_EXT,
32	38	MEM_GROUP_PXP_ILT,
33		− MEM_GROUP_TM_MEM,
34		− MEM_GROUP_SDM_MEM,
35		− MEM_GROUP_PBUF,
36		− MEM_GROUP_RAM,
37	39	MEM_GROUP_MULD_MEM,
38	40	MEM_GROUP_BTB_MEM,
39		− MEM_GROUP_RDIF_CTX,
40		− MEM_GROUP_TDIF_CTX,
41		− MEM_GROUP_CFC_MEM,
42	41	MEM_GROUP_IGU_MEM,
43	42	MEM_GROUP_IGU_MSIX,
44	43	MEM_GROUP_CAU_SB,
45	44	MEM_GROUP_BMB_RAM,
46	45	MEM_GROUP_BMB_MEM,
	46	+ MEM_GROUP_TM_MEM,
	47	+ MEM_GROUP_TASK_CFC_MEM,
47	48	MEM_GROUPS_NUM
48	49	};
49	50
@@ -57,27 +58,28 @@ static const char * const s_mem_group_names[] = { · 7 unmodified lines
57	58	"BRB_RAM",
58	59	"BRB_MEM",
59	60	"PRS_MEM",
	61	+ "SDM_MEM",
	62	+ "PBUF",
60	63	"IOR",
	64	+ "RAM",
61	65	"BTB_RAM",
	66	+ "RDIF_CTX",
	67	+ "TDIF_CTX",
	68	+ "CFC_MEM",
62	69	"CONN_CFC_MEM",
63		− "TASK_CFC_MEM",
64	70	"CAU_PI",
65	71	"CAU_MEM",
	72	+ "CAU_MEM_EXT",
66	73	"PXP_ILT",
67		− "TM_MEM",
68		− "SDM_MEM",
69		− "PBUF",
70		− "RAM",
71	74	"MULD_MEM",
72	75	"BTB_MEM",
73		− "RDIF_CTX",
74		− "TDIF_CTX",
75		− "CFC_MEM",
76	76	"IGU_MEM",
77	77	"IGU_MSIX",
78	78	"CAU_SB",
79	79	"BMB_RAM",
80	80	"BMB_MEM",
	81	+ "TM_MEM",
	82	+ "TASK_CFC_MEM",
81	83	};
82	84
83	85	/* Idle check conditions */
@@ -171,14 +173,38 @@ static u32(cond_arr[]) (const u32 r, const u32 *imm) = { · 87 unmodified lines
171	173	cond13,
172	174	};
173	175
	176	+#define NUM_PHYS_BLOCKS 84
	177	+
	178	+#define NUM_DBG_RESET_REGS 8
	179	+
174	180	/***************************** Data Types ********************************/
175	181
176		−enum platform_ids {
177		− PLATFORM_ASIC,
	182	+enum hw_types {
	183	+ HW_TYPE_ASIC,
178	184	PLATFORM_RESERVED,
179	185	PLATFORM_RESERVED2,
180	186	PLATFORM_RESERVED3,
181		− MAX_PLATFORM_IDS
	187	+ PLATFORM_RESERVED4,
	188	+ MAX_HW_TYPES
	189	+};
	190	+
	191	+/* CM context types */
	192	+enum cm_ctx_types {
	193	+ CM_CTX_CONN_AG,
	194	+ CM_CTX_CONN_ST,
	195	+ CM_CTX_TASK_AG,
	196	+ CM_CTX_TASK_ST,
	197	+ NUM_CM_CTX_TYPES
	198	+};
	199	+
	200	+/* Debug bus frame modes */
	201	+enum dbg_bus_frame_modes {
	202	+ DBG_BUS_FRAME_MODE_4ST = 0, /* 4 Storm dwords (no HW) */
	203	+ DBG_BUS_FRAME_MODE_2ST_2HW = 1, /* 2 Storm dwords, 2 HW dwords */
	204	+ DBG_BUS_FRAME_MODE_1ST_3HW = 2, /* 1 Storm dwords, 3 HW dwords */
	205	+ DBG_BUS_FRAME_MODE_4HW = 3, /* 4 HW dwords (no Storms) */
	206	+ DBG_BUS_FRAME_MODE_8HW = 4, /* 8 HW dwords (no Storms) */
	207	+ DBG_BUS_NUM_FRAME_MODES
182	208	};
183	209
184	210	/* Chip constant definitions */
@@ -187,20 +213,26 @@ struct chip_defs { · 2 unmodified lines
187	213	u32 num_ilt_pages;
188	214	};
189	215
190		−/* Platform constant definitions */
191		−struct platform_defs {
	216	+/* HW type constant definitions */
	217	+struct hw_type_defs {
192	218	const char *name;
193	219	u32 delay_factor;
194	220	u32 dmae_thresh;
195	221	u32 log_thresh;
196	222	};
197	223
	224	+/* RBC reset definitions */
	225	+struct rbc_reset_defs {
	226	+ u32 reset_reg_addr;
	227	+ u32 reset_val[MAX_CHIP_IDS];
	228	+};
	229	+
198	230	/* Storm constant definitions.
199	231	* Addresses are in bytes, sizes are in quad-regs.
200	232	*/
201	233	struct storm_defs {
202	234	char letter;
203		− enum block_id block_id;
	235	+ enum block_id sem_block_id;
204	236	enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
205	237	bool has_vfc;
206	238	u32 sem_fast_mem_addr;
@@ -209,47 +241,26 @@ struct storm_defs { · 2 unmodified lines
209	241	u32 sem_slow_mode_addr;
210	242	u32 sem_slow_mode1_conf_addr;
211	243	u32 sem_sync_dbg_empty_addr;
212		− u32 sem_slow_dbg_empty_addr;
	244	+ u32 sem_gpre_vect_addr;
213	245	u32 cm_ctx_wr_addr;
214		− u32 cm_conn_ag_ctx_lid_size;
215		− u32 cm_conn_ag_ctx_rd_addr;
216		− u32 cm_conn_st_ctx_lid_size;
217		− u32 cm_conn_st_ctx_rd_addr;
218		− u32 cm_task_ag_ctx_lid_size;
219		− u32 cm_task_ag_ctx_rd_addr;
220		− u32 cm_task_st_ctx_lid_size;
221		− u32 cm_task_st_ctx_rd_addr;
	246	+ u32 cm_ctx_rd_addr[NUM_CM_CTX_TYPES];
	247	+ u32 cm_ctx_lid_sizes[MAX_CHIP_IDS][NUM_CM_CTX_TYPES];
222	248	};
223	249
224		−/* Block constant definitions */
225		−struct block_defs {
226		− const char *name;
227		− bool exists[MAX_CHIP_IDS];
228		− bool associated_to_storm;
229		−
230		− /* Valid only if associated_to_storm is true */
231		− u32 storm_id;
232		− enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
233		− u32 dbg_select_addr;
234		− u32 dbg_enable_addr;
235		− u32 dbg_shift_addr;
236		− u32 dbg_force_valid_addr;
237		− u32 dbg_force_frame_addr;
238		− bool has_reset_bit;
239		−
240		− /* If true, block is taken out of reset before dump */
241		− bool unreset;
242		− enum dbg_reset_regs reset_reg;
243		−
244		− /* Bit offset in reset register */
245		− u8 reset_bit_offset;
	250	+/* Debug Bus Constraint operation constant definitions */
	251	+struct dbg_bus_constraint_op_defs {
	252	+ u8 hw_op_val;
	253	+ bool is_cyclic;
246	254	};
247	255
248		−/* Reset register definitions */
249		−struct reset_reg_defs {
250		− u32 addr;
	256	+/* Storm Mode definitions */
	257	+struct storm_mode_defs {
	258	+ const char *name;
	259	+ bool is_fast_dbg;
	260	+ u8 id_in_hw;
	261	+ u32 src_disable_reg_addr;
	262	+ u32 src_enable_val;
251	263	bool exists[MAX_CHIP_IDS];
252		− u32 unreset_val[MAX_CHIP_IDS];
253	264	};
254	265
255	266	struct grc_param_defs {
@@ -259,7 +270,7 @@ struct grc_param_defs { · 3 unmodified lines
259	270	bool is_preset;
260	271	bool is_persistent;
261	272	u32 exclude_all_preset_val;
262		− u32 crash_preset_val;
	273	+ u32 crash_preset_val[MAX_CHIP_IDS];
263	274	};
264	275
265	276	/* Address is in 128b units. Width is in bits. */
@@ -316,15 +327,7 @@ struct split_type_defs { · 50 unmodified lines
316	327
317	328	/****************************** Constants ********************************/
318	329
319		−#define MAX_LCIDS 320
320		−#define MAX_LTIDS 320
321		−
322		−#define NUM_IOR_SETS 2
323		−#define IORS_PER_SET 176
324		−#define IOR_SET_OFFSET(set_id) ((set_id) * 256)
325		−
326	330	#define BYTES_IN_DWORD sizeof(u32)
327		−
328	331	/* In the macros below, size and offset are specified in bits */
329	332	#define CEIL_DWORDS(size) DIV_ROUND_UP(size, 32)
330	333	#define FIELD_BIT_OFFSET(type, field) type ## _ ## field ## _ ## OFFSET
@@ -350,20 +353,17 @@ struct split_type_defs { · 19 unmodified lines
350	353	qed_wr(dev, ptt, addr, (arr)[i]); \
351	354	} while (0)
352	355
353		−#define ARR_REG_RD(dev, ptt, addr, arr, arr_size) \
354		− do { \
355		− for (i = 0; i < (arr_size); i++) \
356		− (arr)[i] = qed_rd(dev, ptt, addr); \
357		− } while (0)
358		−
359	356	#define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD)
360	357	#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD)
361	358
362		−/* Extra lines include a signature line + optional latency events line */
363		−#define NUM_EXTRA_DBG_LINES(block_desc) \
364		− (1 + ((block_desc)->has_latency_events ? 1 : 0))
365		−#define NUM_DBG_LINES(block_desc) \
366		− ((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
	359	+/* extra lines include a signature line + optional latency events line */
	360	+#define NUM_EXTRA_DBG_LINES(block) \
	361	+ (GET_FIELD((block)->flags, DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS) ? 2 : 1)
	362	+#define NUM_DBG_LINES(block) \
	363	+ ((block)->num_of_dbg_bus_lines + NUM_EXTRA_DBG_LINES(block))
	364	+
	365	+#define USE_DMAE true
	366	+#define PROTECT_WIDE_BUS true
367	367
368	368	#define RAM_LINES_TO_DWORDS(lines) ((lines) * 2)
369	369	#define RAM_LINES_TO_BYTES(lines) \
@@ -430,7 +430,9 @@ struct split_type_defs { · 60 unmodified lines
430	430
431	431	#define STATIC_DEBUG_LINE_DWORDS 9
432	432
433		−#define NUM_COMMON_GLOBAL_PARAMS 8
	433	+#define NUM_COMMON_GLOBAL_PARAMS 9
	434	+
	435	+#define MAX_RECURSION_DEPTH 10
434	436
435	437	#define FW_IMG_MAIN 1
436	438
@@ -454,19 +456,13 @@ struct split_type_defs { · 17 unmodified lines
454	456	(MCP_REG_SCRATCH + \
455	457	offsetof(struct static_init, sections[SPAD_SECTION_TRACE]))
456	458
	459	+#define MAX_SW_PLTAFORM_STR_SIZE 64
	460	+
457	461	#define EMPTY_FW_VERSION_STR "???_???_???_???"
458	462	#define EMPTY_FW_IMAGE_STR "???????????????"
459	463
460	464	/*************************** Constant Arrays *****************************/
461	465
462		−struct dbg_array {
463		− const u32 *ptr;
464		− u32 size_in_dwords;
465		−};
466		−
467		−/* Debug arrays */
468		−static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} };
469		−
470	466	/* Chip constant definitions array */
471	467	static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = {
472	468	{"bb", PSWRQ2_REG_ILT_MEMORY_SIZE_BB / 2},
@@ -477,1030 +473,104 @@ static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = { · 4 unmodified lines
477	473	static struct storm_defs s_storm_defs[] = {
478	474	/* Tstorm */
479	475	{'T', BLOCK_TSEM,
480		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT,
481		− DBG_BUS_CLIENT_RBCT}, true,
482		− TSEM_REG_FAST_MEMORY,
483		− TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
484		− TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
485		− TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
486		− TCM_REG_CTX_RBC_ACCS,
487		− 4, TCM_REG_AGG_CON_CTX,
488		− 16, TCM_REG_SM_CON_CTX,
489		− 2, TCM_REG_AGG_TASK_CTX,
490		− 4, TCM_REG_SM_TASK_CTX},
	476	+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
	477	+ true,
	478	+ TSEM_REG_FAST_MEMORY,
	479	+ TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
	480	+ TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
	481	+ TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_DBG_GPRE_VECT,
	482	+ TCM_REG_CTX_RBC_ACCS,
	483	+ {TCM_REG_AGG_CON_CTX, TCM_REG_SM_CON_CTX, TCM_REG_AGG_TASK_CTX,
	484	+ TCM_REG_SM_TASK_CTX},
	485	+ {{4, 16, 2, 4}, {4, 16, 2, 4}} /* {bb} {k2} */
	486	+ },
491	487
492	488	/* Mstorm */
493	489	{'M', BLOCK_MSEM,
494		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM,
495		− DBG_BUS_CLIENT_RBCM}, false,
496		− MSEM_REG_FAST_MEMORY,
497		− MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
498		− MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2,
499		− MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2,
500		− MCM_REG_CTX_RBC_ACCS,
501		− 1, MCM_REG_AGG_CON_CTX,
502		− 10, MCM_REG_SM_CON_CTX,
503		− 2, MCM_REG_AGG_TASK_CTX,
504		− 7, MCM_REG_SM_TASK_CTX},
	490	+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
	491	+ false,
	492	+ MSEM_REG_FAST_MEMORY,
	493	+ MSEM_REG_DBG_FRAME_MODE_BB_K2,
	494	+ MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
	495	+ MSEM_REG_SLOW_DBG_MODE_BB_K2,
	496	+ MSEM_REG_DBG_MODE1_CFG_BB_K2,
	497	+ MSEM_REG_SYNC_DBG_EMPTY,
	498	+ MSEM_REG_DBG_GPRE_VECT,
	499	+ MCM_REG_CTX_RBC_ACCS,
	500	+ {MCM_REG_AGG_CON_CTX, MCM_REG_SM_CON_CTX, MCM_REG_AGG_TASK_CTX,
	501	+ MCM_REG_SM_TASK_CTX },
	502	+ {{1, 10, 2, 7}, {1, 10, 2, 7}} /* {bb} {k2}*/
	503	+ },
505	504
506	505	/* Ustorm */
507	506	{'U', BLOCK_USEM,
508		− {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU,
509		− DBG_BUS_CLIENT_RBCU}, false,
510		− USEM_REG_FAST_MEMORY,
511		− USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
512		− USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2,
513		− USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2,
514		− UCM_REG_CTX_RBC_ACCS,
515		− 2, UCM_REG_AGG_CON_CTX,
516		− 13, UCM_REG_SM_CON_CTX,
517		− 3, UCM_REG_AGG_TASK_CTX,
518		− 3, UCM_REG_SM_TASK_CTX},
	507	+ {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
	508	+ false,
	509	+ USEM_REG_FAST_MEMORY,
	510	+ USEM_REG_DBG_FRAME_MODE_BB_K2,
	511	+ USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
	512	+ USEM_REG_SLOW_DBG_MODE_BB_K2,
	513	+ USEM_REG_DBG_MODE1_CFG_BB_K2,
	514	+ USEM_REG_SYNC_DBG_EMPTY,
	515	+ USEM_REG_DBG_GPRE_VECT,
	516	+ UCM_REG_CTX_RBC_ACCS,
	517	+ {UCM_REG_AGG_CON_CTX, UCM_REG_SM_CON_CTX, UCM_REG_AGG_TASK_CTX,
	518	+ UCM_REG_SM_TASK_CTX},
	519	+ {{2, 13, 3, 3}, {2, 13, 3, 3}} /* {bb} {k2} */
	520	+ },
519	521
520	522	/* Xstorm */
521	523	{'X', BLOCK_XSEM,
522		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX,
523		− DBG_BUS_CLIENT_RBCX}, false,
524		− XSEM_REG_FAST_MEMORY,
525		− XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
526		− XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2,
527		− XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2,
528		− XCM_REG_CTX_RBC_ACCS,
529		− 9, XCM_REG_AGG_CON_CTX,
530		− 15, XCM_REG_SM_CON_CTX,
531		− 0, 0,
532		− 0, 0},
	524	+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
	525	+ false,
	526	+ XSEM_REG_FAST_MEMORY,
	527	+ XSEM_REG_DBG_FRAME_MODE_BB_K2,
	528	+ XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
	529	+ XSEM_REG_SLOW_DBG_MODE_BB_K2,
	530	+ XSEM_REG_DBG_MODE1_CFG_BB_K2,
	531	+ XSEM_REG_SYNC_DBG_EMPTY,
	532	+ XSEM_REG_DBG_GPRE_VECT,
	533	+ XCM_REG_CTX_RBC_ACCS,
	534	+ {XCM_REG_AGG_CON_CTX, XCM_REG_SM_CON_CTX, 0, 0},
	535	+ {{9, 15, 0, 0}, {9, 15, 0, 0}} /* {bb} {k2} */
	536	+ },
533	537
534	538	/* Ystorm */
535	539	{'Y', BLOCK_YSEM,
536		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY,
537		− DBG_BUS_CLIENT_RBCY}, false,
538		− YSEM_REG_FAST_MEMORY,
539		− YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
540		− YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2,
541		− YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
542		− YCM_REG_CTX_RBC_ACCS,
543		− 2, YCM_REG_AGG_CON_CTX,
544		− 3, YCM_REG_SM_CON_CTX,
545		− 2, YCM_REG_AGG_TASK_CTX,
546		− 12, YCM_REG_SM_TASK_CTX},
	540	+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY},
	541	+ false,
	542	+ YSEM_REG_FAST_MEMORY,
	543	+ YSEM_REG_DBG_FRAME_MODE_BB_K2,
	544	+ YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
	545	+ YSEM_REG_SLOW_DBG_MODE_BB_K2,
	546	+ YSEM_REG_DBG_MODE1_CFG_BB_K2,
	547	+ YSEM_REG_SYNC_DBG_EMPTY,
	548	+ YSEM_REG_DBG_GPRE_VECT,
	549	+ YCM_REG_CTX_RBC_ACCS,
	550	+ {YCM_REG_AGG_CON_CTX, YCM_REG_SM_CON_CTX, YCM_REG_AGG_TASK_CTX,
	551	+ YCM_REG_SM_TASK_CTX},
	552	+ {{2, 3, 2, 12}, {2, 3, 2, 12}} /* {bb} {k2} */
	553	+ },
547	554
548	555	/* Pstorm */
549	556	{'P', BLOCK_PSEM,
550		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS,
551		− DBG_BUS_CLIENT_RBCS}, true,
552		− PSEM_REG_FAST_MEMORY,
553		− PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
554		− PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2,
555		− PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2,
556		− PCM_REG_CTX_RBC_ACCS,
557		− 0, 0,
558		− 10, PCM_REG_SM_CON_CTX,
559		− 0, 0,
560		− 0, 0}
561		−};
562		−
563		−/* Block definitions array */
564		−
565		−static struct block_defs block_grc_defs = {
566		− "grc",
567		− {true, true, true}, false, 0,
568		− {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
569		− GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE,
570		− GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID,
571		− GRC_REG_DBG_FORCE_FRAME,
572		− true, false, DBG_RESET_REG_MISC_PL_UA, 1
573		−};
574		−
575		−static struct block_defs block_miscs_defs = {
576		− "miscs", {true, true, true}, false, 0,
577		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
578		− 0, 0, 0, 0, 0,
579		− false, false, MAX_DBG_RESET_REGS, 0
580		−};
581		−
582		−static struct block_defs block_misc_defs = {
583		− "misc", {true, true, true}, false, 0,
584		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
585		− 0, 0, 0, 0, 0,
586		− false, false, MAX_DBG_RESET_REGS, 0
587		−};
588		−
589		−static struct block_defs block_dbu_defs = {
590		− "dbu", {true, true, true}, false, 0,
591		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
592		− 0, 0, 0, 0, 0,
593		− false, false, MAX_DBG_RESET_REGS, 0
594		−};
595		−
596		−static struct block_defs block_pglue_b_defs = {
597		− "pglue_b",
598		− {true, true, true}, false, 0,
599		− {DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH},
600		− PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE,
601		− PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID,
602		− PGLUE_B_REG_DBG_FORCE_FRAME,
603		− true, false, DBG_RESET_REG_MISCS_PL_HV, 1
604		−};
605		−
606		−static struct block_defs block_cnig_defs = {
607		− "cnig",
608		− {true, true, true}, false, 0,
609		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW,
610		− DBG_BUS_CLIENT_RBCW},
611		− CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
612		− CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
613		− CNIG_REG_DBG_FORCE_FRAME_K2_E5,
614		− true, false, DBG_RESET_REG_MISCS_PL_HV, 0
615		−};
616		−
617		−static struct block_defs block_cpmu_defs = {
618		− "cpmu", {true, true, true}, false, 0,
619		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
620		− 0, 0, 0, 0, 0,
621		− true, false, DBG_RESET_REG_MISCS_PL_HV, 8
622		−};
623		−
624		−static struct block_defs block_ncsi_defs = {
625		− "ncsi",
626		− {true, true, true}, false, 0,
627		− {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
628		− NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE,
629		− NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID,
630		− NCSI_REG_DBG_FORCE_FRAME,
631		− true, false, DBG_RESET_REG_MISCS_PL_HV, 5
632		−};
633		−
634		−static struct block_defs block_opte_defs = {
635		− "opte", {true, true, false}, false, 0,
636		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
637		− 0, 0, 0, 0, 0,
638		− true, false, DBG_RESET_REG_MISCS_PL_HV, 4
639		−};
640		−
641		−static struct block_defs block_bmb_defs = {
642		− "bmb",
643		− {true, true, true}, false, 0,
644		− {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB},
645		− BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE,
646		− BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID,
647		− BMB_REG_DBG_FORCE_FRAME,
648		− true, false, DBG_RESET_REG_MISCS_PL_UA, 7
649		−};
650		−
651		−static struct block_defs block_pcie_defs = {
652		− "pcie",
653		− {true, true, true}, false, 0,
654		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
655		− DBG_BUS_CLIENT_RBCH},
656		− PCIE_REG_DBG_COMMON_SELECT_K2_E5,
657		− PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
658		− PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
659		− PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
660		− PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
661		− false, false, MAX_DBG_RESET_REGS, 0
662		−};
663		−
664		−static struct block_defs block_mcp_defs = {
665		− "mcp", {true, true, true}, false, 0,
666		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
667		− 0, 0, 0, 0, 0,
668		− false, false, MAX_DBG_RESET_REGS, 0
669		−};
670		−
671		−static struct block_defs block_mcp2_defs = {
672		− "mcp2",
673		− {true, true, true}, false, 0,
674		− {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
675		− MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE,
676		− MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID,
677		− MCP2_REG_DBG_FORCE_FRAME,
678		− false, false, MAX_DBG_RESET_REGS, 0
679		−};
680		−
681		−static struct block_defs block_pswhst_defs = {
682		− "pswhst",
683		− {true, true, true}, false, 0,
684		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
685		− PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE,
686		− PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID,
687		− PSWHST_REG_DBG_FORCE_FRAME,
688		− true, false, DBG_RESET_REG_MISC_PL_HV, 0
689		−};
690		−
691		−static struct block_defs block_pswhst2_defs = {
692		− "pswhst2",
693		− {true, true, true}, false, 0,
694		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
695		− PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE,
696		− PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID,
697		− PSWHST2_REG_DBG_FORCE_FRAME,
698		− true, false, DBG_RESET_REG_MISC_PL_HV, 0
699		−};
700		−
701		−static struct block_defs block_pswrd_defs = {
702		− "pswrd",
703		− {true, true, true}, false, 0,
704		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
705		− PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE,
706		− PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID,
707		− PSWRD_REG_DBG_FORCE_FRAME,
708		− true, false, DBG_RESET_REG_MISC_PL_HV, 2
709		−};
710		−
711		−static struct block_defs block_pswrd2_defs = {
712		− "pswrd2",
713		− {true, true, true}, false, 0,
714		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
715		− PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE,
716		− PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID,
717		− PSWRD2_REG_DBG_FORCE_FRAME,
718		− true, false, DBG_RESET_REG_MISC_PL_HV, 2
719		−};
720		−
721		−static struct block_defs block_pswwr_defs = {
722		− "pswwr",
723		− {true, true, true}, false, 0,
724		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
725		− PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE,
726		− PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID,
727		− PSWWR_REG_DBG_FORCE_FRAME,
728		− true, false, DBG_RESET_REG_MISC_PL_HV, 3
729		−};
730		−
731		−static struct block_defs block_pswwr2_defs = {
732		− "pswwr2", {true, true, true}, false, 0,
733		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
734		− 0, 0, 0, 0, 0,
735		− true, false, DBG_RESET_REG_MISC_PL_HV, 3
736		−};
737		−
738		−static struct block_defs block_pswrq_defs = {
739		− "pswrq",
740		− {true, true, true}, false, 0,
741		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
742		− PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE,
743		− PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID,
744		− PSWRQ_REG_DBG_FORCE_FRAME,
745		− true, false, DBG_RESET_REG_MISC_PL_HV, 1
746		−};
747		−
748		−static struct block_defs block_pswrq2_defs = {
749		− "pswrq2",
750		− {true, true, true}, false, 0,
751		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
752		− PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE,
753		− PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID,
754		− PSWRQ2_REG_DBG_FORCE_FRAME,
755		− true, false, DBG_RESET_REG_MISC_PL_HV, 1
756		−};
757		−
758		−static struct block_defs block_pglcs_defs = {
759		− "pglcs",
760		− {true, true, true}, false, 0,
761		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
762		− DBG_BUS_CLIENT_RBCH},
763		− PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5,
764		− PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5,
765		− PGLCS_REG_DBG_FORCE_FRAME_K2_E5,
766		− true, false, DBG_RESET_REG_MISCS_PL_HV, 2
767		−};
768		−
769		−static struct block_defs block_ptu_defs = {
770		− "ptu",
771		− {true, true, true}, false, 0,
772		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
773		− PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE,
774		− PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID,
775		− PTU_REG_DBG_FORCE_FRAME,
776		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20
777		−};
778		−
779		−static struct block_defs block_dmae_defs = {
780		− "dmae",
781		− {true, true, true}, false, 0,
782		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
783		− DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE,
784		− DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID,
785		− DMAE_REG_DBG_FORCE_FRAME,
786		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28
787		−};
788		−
789		−static struct block_defs block_tcm_defs = {
790		− "tcm",
791		− {true, true, true}, true, DBG_TSTORM_ID,
792		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
793		− TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE,
794		− TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID,
795		− TCM_REG_DBG_FORCE_FRAME,
796		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5
797		−};
798		−
799		−static struct block_defs block_mcm_defs = {
800		− "mcm",
801		− {true, true, true}, true, DBG_MSTORM_ID,
802		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
803		− MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE,
804		− MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID,
805		− MCM_REG_DBG_FORCE_FRAME,
806		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3
807		−};
808		−
809		−static struct block_defs block_ucm_defs = {
810		− "ucm",
811		− {true, true, true}, true, DBG_USTORM_ID,
812		− {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
813		− UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE,
814		− UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID,
815		− UCM_REG_DBG_FORCE_FRAME,
816		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8
817		−};
818		−
819		−static struct block_defs block_xcm_defs = {
820		− "xcm",
821		− {true, true, true}, true, DBG_XSTORM_ID,
822		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
823		− XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE,
824		− XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID,
825		− XCM_REG_DBG_FORCE_FRAME,
826		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19
827		−};
828		−
829		−static struct block_defs block_ycm_defs = {
830		− "ycm",
831		− {true, true, true}, true, DBG_YSTORM_ID,
832		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
833		− YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE,
834		− YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID,
835		− YCM_REG_DBG_FORCE_FRAME,
836		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5
837		−};
838		−
839		−static struct block_defs block_pcm_defs = {
840		− "pcm",
841		− {true, true, true}, true, DBG_PSTORM_ID,
842		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
843		− PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE,
844		− PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID,
845		− PCM_REG_DBG_FORCE_FRAME,
846		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4
847		−};
848		−
849		−static struct block_defs block_qm_defs = {
850		− "qm",
851		− {true, true, true}, false, 0,
852		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ, DBG_BUS_CLIENT_RBCQ},
853		− QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE,
854		− QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID,
855		− QM_REG_DBG_FORCE_FRAME,
856		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16
857		−};
858		−
859		−static struct block_defs block_tm_defs = {
860		− "tm",
861		− {true, true, true}, false, 0,
862		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
863		− TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE,
864		− TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID,
865		− TM_REG_DBG_FORCE_FRAME,
866		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17
867		−};
868		−
869		−static struct block_defs block_dorq_defs = {
870		− "dorq",
871		− {true, true, true}, false, 0,
872		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
873		− DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE,
874		− DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID,
875		− DORQ_REG_DBG_FORCE_FRAME,
876		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18
877		−};
878		−
879		−static struct block_defs block_brb_defs = {
880		− "brb",
881		− {true, true, true}, false, 0,
882		− {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
883		− BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE,
884		− BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID,
885		− BRB_REG_DBG_FORCE_FRAME,
886		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0
887		−};
888		−
889		−static struct block_defs block_src_defs = {
890		− "src",
891		− {true, true, true}, false, 0,
892		− {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
893		− SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE,
894		− SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID,
895		− SRC_REG_DBG_FORCE_FRAME,
896		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2
897		−};
898		−
899		−static struct block_defs block_prs_defs = {
900		− "prs",
901		− {true, true, true}, false, 0,
902		− {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
903		− PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE,
904		− PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID,
905		− PRS_REG_DBG_FORCE_FRAME,
906		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1
907		−};
908		−
909		−static struct block_defs block_tsdm_defs = {
910		− "tsdm",
911		− {true, true, true}, true, DBG_TSTORM_ID,
912		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
913		− TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE,
914		− TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID,
915		− TSDM_REG_DBG_FORCE_FRAME,
916		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3
917		−};
918		−
919		−static struct block_defs block_msdm_defs = {
920		− "msdm",
921		− {true, true, true}, true, DBG_MSTORM_ID,
922		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
923		− MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE,
924		− MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID,
925		− MSDM_REG_DBG_FORCE_FRAME,
926		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6
927		−};
928		−
929		−static struct block_defs block_usdm_defs = {
930		− "usdm",
931		− {true, true, true}, true, DBG_USTORM_ID,
932		− {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
933		− USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE,
934		− USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID,
935		− USDM_REG_DBG_FORCE_FRAME,
936		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7
937		−};
938		−
939		−static struct block_defs block_xsdm_defs = {
940		− "xsdm",
941		− {true, true, true}, true, DBG_XSTORM_ID,
942		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
943		− XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE,
944		− XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID,
945		− XSDM_REG_DBG_FORCE_FRAME,
946		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20
947		−};
948		−
949		−static struct block_defs block_ysdm_defs = {
950		− "ysdm",
951		− {true, true, true}, true, DBG_YSTORM_ID,
952		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
953		− YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE,
954		− YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID,
955		− YSDM_REG_DBG_FORCE_FRAME,
956		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8
957		−};
958		−
959		−static struct block_defs block_psdm_defs = {
960		− "psdm",
961		− {true, true, true}, true, DBG_PSTORM_ID,
962		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
963		− PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE,
964		− PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID,
965		− PSDM_REG_DBG_FORCE_FRAME,
966		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7
967		−};
968		−
969		−static struct block_defs block_tsem_defs = {
970		− "tsem",
971		− {true, true, true}, true, DBG_TSTORM_ID,
972		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
973		− TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE,
974		− TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID,
975		− TSEM_REG_DBG_FORCE_FRAME,
976		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4
977		−};
978		−
979		−static struct block_defs block_msem_defs = {
980		− "msem",
981		− {true, true, true}, true, DBG_MSTORM_ID,
982		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
983		− MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE,
984		− MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID,
985		− MSEM_REG_DBG_FORCE_FRAME,
986		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9
987		−};
988		−
989		−static struct block_defs block_usem_defs = {
990		− "usem",
991		− {true, true, true}, true, DBG_USTORM_ID,
992		− {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
993		− USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE,
994		− USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID,
995		− USEM_REG_DBG_FORCE_FRAME,
996		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9
997		−};
998		−
999		−static struct block_defs block_xsem_defs = {
1000		− "xsem",
1001		− {true, true, true}, true, DBG_XSTORM_ID,
1002		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
1003		− XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE,
1004		− XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID,
1005		− XSEM_REG_DBG_FORCE_FRAME,
1006		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21
1007		−};
1008		−
1009		−static struct block_defs block_ysem_defs = {
1010		− "ysem",
1011		− {true, true, true}, true, DBG_YSTORM_ID,
1012		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
1013		− YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE,
1014		− YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID,
1015		− YSEM_REG_DBG_FORCE_FRAME,
1016		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11
1017		−};
1018		−
1019		−static struct block_defs block_psem_defs = {
1020		− "psem",
1021		− {true, true, true}, true, DBG_PSTORM_ID,
1022		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
1023		− PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE,
1024		− PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID,
1025		− PSEM_REG_DBG_FORCE_FRAME,
1026		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10
1027		−};
1028		−
1029		−static struct block_defs block_rss_defs = {
1030		− "rss",
1031		− {true, true, true}, false, 0,
1032		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
1033		− RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE,
1034		− RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID,
1035		− RSS_REG_DBG_FORCE_FRAME,
1036		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18
1037		−};
1038		−
1039		−static struct block_defs block_tmld_defs = {
1040		− "tmld",
1041		− {true, true, true}, false, 0,
1042		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
1043		− TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE,
1044		− TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID,
1045		− TMLD_REG_DBG_FORCE_FRAME,
1046		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13
1047		−};
1048		−
1049		−static struct block_defs block_muld_defs = {
1050		− "muld",
1051		− {true, true, true}, false, 0,
1052		− {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
1053		− MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE,
1054		− MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID,
1055		− MULD_REG_DBG_FORCE_FRAME,
1056		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14
1057		−};
1058		−
1059		−static struct block_defs block_yuld_defs = {
1060		− "yuld",
1061		− {true, true, false}, false, 0,
1062		− {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU,
1063		− MAX_DBG_BUS_CLIENTS},
1064		− YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2,
1065		− YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2,
1066		− YULD_REG_DBG_FORCE_FRAME_BB_K2,
1067		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
1068		− 15
1069		−};
1070		−
1071		−static struct block_defs block_xyld_defs = {
1072		− "xyld",
1073		− {true, true, true}, false, 0,
1074		− {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
1075		− XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE,
1076		− XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID,
1077		− XYLD_REG_DBG_FORCE_FRAME,
1078		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12
1079		−};
1080		−
1081		−static struct block_defs block_ptld_defs = {
1082		− "ptld",
1083		− {false, false, true}, false, 0,
1084		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCT},
1085		− PTLD_REG_DBG_SELECT_E5, PTLD_REG_DBG_DWORD_ENABLE_E5,
1086		− PTLD_REG_DBG_SHIFT_E5, PTLD_REG_DBG_FORCE_VALID_E5,
1087		− PTLD_REG_DBG_FORCE_FRAME_E5,
1088		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
1089		− 28
1090		−};
1091		−
1092		−static struct block_defs block_ypld_defs = {
1093		− "ypld",
1094		− {false, false, true}, false, 0,
1095		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCS},
1096		− YPLD_REG_DBG_SELECT_E5, YPLD_REG_DBG_DWORD_ENABLE_E5,
1097		− YPLD_REG_DBG_SHIFT_E5, YPLD_REG_DBG_FORCE_VALID_E5,
1098		− YPLD_REG_DBG_FORCE_FRAME_E5,
1099		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
1100		− 27
1101		−};
1102		−
1103		−static struct block_defs block_prm_defs = {
1104		− "prm",
1105		− {true, true, true}, false, 0,
1106		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
1107		− PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE,
1108		− PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID,
1109		− PRM_REG_DBG_FORCE_FRAME,
1110		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21
1111		−};
1112		−
1113		−static struct block_defs block_pbf_pb1_defs = {
1114		− "pbf_pb1",
1115		− {true, true, true}, false, 0,
1116		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
1117		− PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE,
1118		− PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID,
1119		− PBF_PB1_REG_DBG_FORCE_FRAME,
1120		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
1121		− 11
1122		−};
1123		−
1124		−static struct block_defs block_pbf_pb2_defs = {
1125		− "pbf_pb2",
1126		− {true, true, true}, false, 0,
1127		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
1128		− PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE,
1129		− PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID,
1130		− PBF_PB2_REG_DBG_FORCE_FRAME,
1131		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
1132		− 12
1133		−};
1134		−
1135		−static struct block_defs block_rpb_defs = {
1136		− "rpb",
1137		− {true, true, true}, false, 0,
1138		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
1139		− RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE,
1140		− RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID,
1141		− RPB_REG_DBG_FORCE_FRAME,
1142		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13
1143		−};
1144		−
1145		−static struct block_defs block_btb_defs = {
1146		− "btb",
1147		− {true, true, true}, false, 0,
1148		− {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
1149		− BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE,
1150		− BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID,
1151		− BTB_REG_DBG_FORCE_FRAME,
1152		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10
1153		−};
1154		−
1155		−static struct block_defs block_pbf_defs = {
1156		− "pbf",
1157		− {true, true, true}, false, 0,
1158		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
1159		− PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE,
1160		− PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID,
1161		− PBF_REG_DBG_FORCE_FRAME,
1162		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15
1163		−};
1164		−
1165		−static struct block_defs block_rdif_defs = {
1166		− "rdif",
1167		− {true, true, true}, false, 0,
1168		− {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
1169		− RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE,
1170		− RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID,
1171		− RDIF_REG_DBG_FORCE_FRAME,
1172		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16
1173		−};
1174		−
1175		−static struct block_defs block_tdif_defs = {
1176		− "tdif",
1177		− {true, true, true}, false, 0,
1178		− {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
1179		− TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE,
1180		− TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID,
1181		− TDIF_REG_DBG_FORCE_FRAME,
1182		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17
1183		−};
1184		−
1185		−static struct block_defs block_cdu_defs = {
1186		− "cdu",
1187		− {true, true, true}, false, 0,
1188		− {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
1189		− CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE,
1190		− CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID,
1191		− CDU_REG_DBG_FORCE_FRAME,
1192		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23
1193		−};
1194		−
1195		−static struct block_defs block_ccfc_defs = {
1196		− "ccfc",
1197		− {true, true, true}, false, 0,
1198		− {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
1199		− CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE,
1200		− CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID,
1201		− CCFC_REG_DBG_FORCE_FRAME,
1202		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24
1203		−};
1204		−
1205		−static struct block_defs block_tcfc_defs = {
1206		− "tcfc",
1207		− {true, true, true}, false, 0,
1208		− {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
1209		− TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE,
1210		− TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID,
1211		− TCFC_REG_DBG_FORCE_FRAME,
1212		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25
1213		−};
1214		−
1215		−static struct block_defs block_igu_defs = {
1216		− "igu",
1217		− {true, true, true}, false, 0,
1218		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
1219		− IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE,
1220		− IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID,
1221		− IGU_REG_DBG_FORCE_FRAME,
1222		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27
1223		−};
1224		−
1225		−static struct block_defs block_cau_defs = {
1226		− "cau",
1227		− {true, true, true}, false, 0,
1228		− {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
1229		− CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE,
1230		− CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID,
1231		− CAU_REG_DBG_FORCE_FRAME,
1232		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19
1233		−};
1234		−
1235		−static struct block_defs block_rgfs_defs = {
1236		− "rgfs", {false, false, true}, false, 0,
1237		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1238		− 0, 0, 0, 0, 0,
1239		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 29
1240		−};
1241		−
1242		−static struct block_defs block_rgsrc_defs = {
1243		− "rgsrc",
1244		− {false, false, true}, false, 0,
1245		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
1246		− RGSRC_REG_DBG_SELECT_E5, RGSRC_REG_DBG_DWORD_ENABLE_E5,
1247		− RGSRC_REG_DBG_SHIFT_E5, RGSRC_REG_DBG_FORCE_VALID_E5,
1248		− RGSRC_REG_DBG_FORCE_FRAME_E5,
1249		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
1250		− 30
1251		−};
1252		−
1253		−static struct block_defs block_tgfs_defs = {
1254		− "tgfs", {false, false, true}, false, 0,
1255		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1256		− 0, 0, 0, 0, 0,
1257		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 30
1258		−};
1259		−
1260		−static struct block_defs block_tgsrc_defs = {
1261		− "tgsrc",
1262		− {false, false, true}, false, 0,
1263		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCV},
1264		− TGSRC_REG_DBG_SELECT_E5, TGSRC_REG_DBG_DWORD_ENABLE_E5,
1265		− TGSRC_REG_DBG_SHIFT_E5, TGSRC_REG_DBG_FORCE_VALID_E5,
1266		− TGSRC_REG_DBG_FORCE_FRAME_E5,
1267		− true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
1268		− 31
1269		−};
1270		−
1271		−static struct block_defs block_umac_defs = {
1272		− "umac",
1273		− {true, true, true}, false, 0,
1274		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ,
1275		− DBG_BUS_CLIENT_RBCZ},
1276		− UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5,
1277		− UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5,
1278		− UMAC_REG_DBG_FORCE_FRAME_K2_E5,
1279		− true, false, DBG_RESET_REG_MISCS_PL_HV, 6
1280		−};
1281		−
1282		−static struct block_defs block_xmac_defs = {
1283		− "xmac", {true, false, false}, false, 0,
1284		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1285		− 0, 0, 0, 0, 0,
1286		− false, false, MAX_DBG_RESET_REGS, 0
1287		−};
1288		−
1289		−static struct block_defs block_dbg_defs = {
1290		− "dbg", {true, true, true}, false, 0,
1291		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1292		− 0, 0, 0, 0, 0,
1293		− true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3
1294		−};
1295		−
1296		−static struct block_defs block_nig_defs = {
1297		− "nig",
1298		− {true, true, true}, false, 0,
1299		− {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
1300		− NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE,
1301		− NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID,
1302		− NIG_REG_DBG_FORCE_FRAME,
1303		− true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0
1304		−};
1305		−
1306		−static struct block_defs block_wol_defs = {
1307		− "wol",
1308		− {false, true, true}, false, 0,
1309		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
1310		− WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5,
1311		− WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5,
1312		− WOL_REG_DBG_FORCE_FRAME_K2_E5,
1313		− true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7
1314		−};
1315		−
1316		−static struct block_defs block_bmbn_defs = {
1317		− "bmbn",
1318		− {false, true, true}, false, 0,
1319		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB,
1320		− DBG_BUS_CLIENT_RBCB},
1321		− BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5,
1322		− BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5,
1323		− BMBN_REG_DBG_FORCE_FRAME_K2_E5,
1324		− false, false, MAX_DBG_RESET_REGS, 0
1325		−};
1326		−
1327		−static struct block_defs block_ipc_defs = {
1328		− "ipc", {true, true, true}, false, 0,
1329		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1330		− 0, 0, 0, 0, 0,
1331		− true, false, DBG_RESET_REG_MISCS_PL_UA, 8
1332		−};
1333		−
1334		−static struct block_defs block_nwm_defs = {
1335		− "nwm",
1336		− {false, true, true}, false, 0,
1337		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW},
1338		− NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5,
1339		− NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5,
1340		− NWM_REG_DBG_FORCE_FRAME_K2_E5,
1341		− true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0
1342		−};
1343		−
1344		−static struct block_defs block_nws_defs = {
1345		− "nws",
1346		− {false, true, true}, false, 0,
1347		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW},
1348		− NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5,
1349		− NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5,
1350		− NWS_REG_DBG_FORCE_FRAME_K2_E5,
1351		− true, false, DBG_RESET_REG_MISCS_PL_HV, 12
1352		−};
1353		−
1354		−static struct block_defs block_ms_defs = {
1355		− "ms",
1356		− {false, true, true}, false, 0,
1357		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
1358		− MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5,
1359		− MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5,
1360		− MS_REG_DBG_FORCE_FRAME_K2_E5,
1361		− true, false, DBG_RESET_REG_MISCS_PL_HV, 13
1362		−};
1363		−
1364		−static struct block_defs block_phy_pcie_defs = {
1365		− "phy_pcie",
1366		− {false, true, true}, false, 0,
1367		− {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
1368		− DBG_BUS_CLIENT_RBCH},
1369		− PCIE_REG_DBG_COMMON_SELECT_K2_E5,
1370		− PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
1371		− PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
1372		− PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
1373		− PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
1374		− false, false, MAX_DBG_RESET_REGS, 0
1375		−};
1376		−
1377		−static struct block_defs block_led_defs = {
1378		− "led", {false, true, true}, false, 0,
1379		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1380		− 0, 0, 0, 0, 0,
1381		− true, false, DBG_RESET_REG_MISCS_PL_HV, 14
1382		−};
1383		−
1384		−static struct block_defs block_avs_wrap_defs = {
1385		− "avs_wrap", {false, true, false}, false, 0,
1386		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1387		− 0, 0, 0, 0, 0,
1388		− true, false, DBG_RESET_REG_MISCS_PL_UA, 11
1389		−};
1390		−
1391		−static struct block_defs block_pxpreqbus_defs = {
1392		− "pxpreqbus", {false, false, false}, false, 0,
1393		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1394		− 0, 0, 0, 0, 0,
1395		− false, false, MAX_DBG_RESET_REGS, 0
1396		−};
1397		−
1398		−static struct block_defs block_misc_aeu_defs = {
1399		− "misc_aeu", {true, true, true}, false, 0,
1400		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1401		− 0, 0, 0, 0, 0,
1402		− false, false, MAX_DBG_RESET_REGS, 0
1403		−};
1404		−
1405		−static struct block_defs block_bar0_map_defs = {
1406		− "bar0_map", {true, true, true}, false, 0,
1407		− {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1408		− 0, 0, 0, 0, 0,
1409		− false, false, MAX_DBG_RESET_REGS, 0
1410		−};
1411		−
1412		−static struct block_defs *s_block_defs[MAX_BLOCK_ID] = {
1413		− &block_grc_defs,
1414		− &block_miscs_defs,
1415		− &block_misc_defs,
1416		− &block_dbu_defs,
1417		− &block_pglue_b_defs,
1418		− &block_cnig_defs,
1419		− &block_cpmu_defs,
1420		− &block_ncsi_defs,
1421		− &block_opte_defs,
1422		− &block_bmb_defs,
1423		− &block_pcie_defs,
1424		− &block_mcp_defs,
1425		− &block_mcp2_defs,
1426		− &block_pswhst_defs,
1427		− &block_pswhst2_defs,
1428		− &block_pswrd_defs,
1429		− &block_pswrd2_defs,
1430		− &block_pswwr_defs,
1431		− &block_pswwr2_defs,
1432		− &block_pswrq_defs,
1433		− &block_pswrq2_defs,
1434		− &block_pglcs_defs,
1435		− &block_dmae_defs,
1436		− &block_ptu_defs,
1437		− &block_tcm_defs,
1438		− &block_mcm_defs,
1439		− &block_ucm_defs,
1440		− &block_xcm_defs,
1441		− &block_ycm_defs,
1442		− &block_pcm_defs,
1443		− &block_qm_defs,
1444		− &block_tm_defs,
1445		− &block_dorq_defs,
1446		− &block_brb_defs,
1447		− &block_src_defs,
1448		− &block_prs_defs,
1449		− &block_tsdm_defs,
1450		− &block_msdm_defs,
1451		− &block_usdm_defs,
1452		− &block_xsdm_defs,
1453		− &block_ysdm_defs,
1454		− &block_psdm_defs,
1455		− &block_tsem_defs,
1456		− &block_msem_defs,
1457		− &block_usem_defs,
1458		− &block_xsem_defs,
1459		− &block_ysem_defs,
1460		− &block_psem_defs,
1461		− &block_rss_defs,
1462		− &block_tmld_defs,
1463		− &block_muld_defs,
1464		− &block_yuld_defs,
1465		− &block_xyld_defs,
1466		− &block_ptld_defs,
1467		− &block_ypld_defs,
1468		− &block_prm_defs,
1469		− &block_pbf_pb1_defs,
1470		− &block_pbf_pb2_defs,
1471		− &block_rpb_defs,
1472		− &block_btb_defs,
1473		− &block_pbf_defs,
1474		− &block_rdif_defs,
1475		− &block_tdif_defs,
1476		− &block_cdu_defs,
1477		− &block_ccfc_defs,
1478		− &block_tcfc_defs,
1479		− &block_igu_defs,
1480		− &block_cau_defs,
1481		− &block_rgfs_defs,
1482		− &block_rgsrc_defs,
1483		− &block_tgfs_defs,
1484		− &block_tgsrc_defs,
1485		− &block_umac_defs,
1486		− &block_xmac_defs,
1487		− &block_dbg_defs,
1488		− &block_nig_defs,
1489		− &block_wol_defs,
1490		− &block_bmbn_defs,
1491		− &block_ipc_defs,
1492		− &block_nwm_defs,
1493		− &block_nws_defs,
1494		− &block_ms_defs,
1495		− &block_phy_pcie_defs,
1496		− &block_led_defs,
1497		− &block_avs_wrap_defs,
1498		− &block_pxpreqbus_defs,
1499		− &block_misc_aeu_defs,
1500		− &block_bar0_map_defs,
1501		−};
1502		−
1503		−static struct platform_defs s_platform_defs[] = {
	557	+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
	558	+ true,
	559	+ PSEM_REG_FAST_MEMORY,
	560	+ PSEM_REG_DBG_FRAME_MODE_BB_K2,
	561	+ PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
	562	+ PSEM_REG_SLOW_DBG_MODE_BB_K2,
	563	+ PSEM_REG_DBG_MODE1_CFG_BB_K2,
	564	+ PSEM_REG_SYNC_DBG_EMPTY,
	565	+ PSEM_REG_DBG_GPRE_VECT,
	566	+ PCM_REG_CTX_RBC_ACCS,
	567	+ {0, PCM_REG_SM_CON_CTX, 0, 0},
	568	+ {{0, 10, 0, 0}, {0, 10, 0, 0}} /* {bb} {k2} */
	569	+ },
	570	+};
	571	+
	572	+static struct hw_type_defs s_hw_type_defs[] = {
	573	+ /* HW_TYPE_ASIC */
1504	574	{"asic", 1, 256, 32768},
1505	575	{"reserved", 0, 0, 0},
1506	576	{"reserved2", 0, 0, 0},
@@ -1509,161 +579,159 @@ static struct platform_defs s_platform_defs[] = { · 2 unmodified lines
1509	579
1510	580	static struct grc_param_defs s_grc_param_defs[] = {
1511	581	/* DBG_GRC_PARAM_DUMP_TSTORM */
1512		− {{1, 1, 1}, 0, 1, false, false, 1, 1},
	582	+ {{1, 1}, 0, 1, false, false, 1, {1, 1}},
1513	583
1514	584	/* DBG_GRC_PARAM_DUMP_MSTORM */
1515		− {{1, 1, 1}, 0, 1, false, false, 1, 1},
	585	+ {{1, 1}, 0, 1, false, false, 1, {1, 1}},
1516	586
1517	587	/* DBG_GRC_PARAM_DUMP_USTORM */
1518		− {{1, 1, 1}, 0, 1, false, false, 1, 1},
	588	+ {{1, 1}, 0, 1, false, false, 1, {1, 1}},
1519	589
1520	590	/* DBG_GRC_PARAM_DUMP_XSTORM */
1521		− {{1, 1, 1}, 0, 1, false, false, 1, 1},
	591	+ {{1, 1}, 0, 1, false, false, 1, {1, 1}},
1522	592
1523	593	/* DBG_GRC_PARAM_DUMP_YSTORM */
1524		− {{1, 1, 1}, 0, 1, false, false, 1, 1},
	594	+ {{1, 1}, 0, 1, false, false, 1, {1, 1}},
1525	595
1526	596	/* DBG_GRC_PARAM_DUMP_PSTORM */
1527		− {{1, 1, 1}, 0, 1, false, false, 1, 1},
	597	+ {{1, 1}, 0, 1, false, false, 1, {1, 1}},
1528	598
1529	599	/* DBG_GRC_PARAM_DUMP_REGS */
1530		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	600	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1531	601
1532	602	/* DBG_GRC_PARAM_DUMP_RAM */
1533		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	603	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1534	604
1535	605	/* DBG_GRC_PARAM_DUMP_PBUF */
1536		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	606	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1537	607
1538	608	/* DBG_GRC_PARAM_DUMP_IOR */
1539		− {{0, 0, 0}, 0, 1, false, false, 0, 1},
	609	+ {{0, 0}, 0, 1, false, false, 0, {1, 1}},
1540	610
1541	611	/* DBG_GRC_PARAM_DUMP_VFC */
1542		− {{0, 0, 0}, 0, 1, false, false, 0, 1},
	612	+ {{0, 0}, 0, 1, false, false, 0, {1, 1}},
1543	613
1544	614	/* DBG_GRC_PARAM_DUMP_CM_CTX */
1545		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	615	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1546	616
1547	617	/* DBG_GRC_PARAM_DUMP_ILT */
1548		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	618	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1549	619
1550	620	/* DBG_GRC_PARAM_DUMP_RSS */
1551		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	621	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1552	622
1553	623	/* DBG_GRC_PARAM_DUMP_CAU */
1554		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	624	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1555	625
1556	626	/* DBG_GRC_PARAM_DUMP_QM */
1557		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	627	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1558	628
1559	629	/* DBG_GRC_PARAM_DUMP_MCP */
1560		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	630	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1561	631
1562		− /* DBG_GRC_PARAM_MCP_TRACE_META_SIZE */
1563		− {{1, 1, 1}, 1, 0xffffffff, false, true, 0, 1},
	632	+ /* DBG_GRC_PARAM_DUMP_DORQ */
	633	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1564	634
1565	635	/* DBG_GRC_PARAM_DUMP_CFC */
1566		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	636	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1567	637
1568	638	/* DBG_GRC_PARAM_DUMP_IGU */
1569		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	639	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1570	640
1571	641	/* DBG_GRC_PARAM_DUMP_BRB */
1572		− {{0, 0, 0}, 0, 1, false, false, 0, 1},
	642	+ {{0, 0}, 0, 1, false, false, 0, {1, 1}},
1573	643
1574	644	/* DBG_GRC_PARAM_DUMP_BTB */
1575		− {{0, 0, 0}, 0, 1, false, false, 0, 1},
	645	+ {{0, 0}, 0, 1, false, false, 0, {1, 1}},
1576	646
1577	647	/* DBG_GRC_PARAM_DUMP_BMB */
1578		− {{0, 0, 0}, 0, 1, false, false, 0, 0},
	648	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1579	649
1580		− /* DBG_GRC_PARAM_DUMP_NIG */
1581		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	650	+ /* DBG_GRC_PARAM_RESERVED1 */
	651	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1582	652
1583	653	/* DBG_GRC_PARAM_DUMP_MULD */
1584		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	654	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1585	655
1586	656	/* DBG_GRC_PARAM_DUMP_PRS */
1587		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	657	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1588	658
1589	659	/* DBG_GRC_PARAM_DUMP_DMAE */
1590		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	660	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1591	661
1592	662	/* DBG_GRC_PARAM_DUMP_TM */
1593		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	663	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1594	664
1595	665	/* DBG_GRC_PARAM_DUMP_SDM */
1596		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	666	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1597	667
1598	668	/* DBG_GRC_PARAM_DUMP_DIF */
1599		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	669	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1600	670
1601	671	/* DBG_GRC_PARAM_DUMP_STATIC */
1602		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	672	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1603	673
1604	674	/* DBG_GRC_PARAM_UNSTALL */
1605		− {{0, 0, 0}, 0, 1, false, false, 0, 0},
	675	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1606	676
1607		− /* DBG_GRC_PARAM_NUM_LCIDS */
1608		− {{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, false,
1609		− MAX_LCIDS, MAX_LCIDS},
	677	+ /* DBG_GRC_PARAM_RESERVED2 */
	678	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1610	679
1611		− /* DBG_GRC_PARAM_NUM_LTIDS */
1612		− {{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, false,
1613		− MAX_LTIDS, MAX_LTIDS},
	680	+ /* DBG_GRC_PARAM_MCP_TRACE_META_SIZE */
	681	+ {{0, 0}, 1, 0xffffffff, false, true, 0, {0, 0}},
1614	682
1615	683	/* DBG_GRC_PARAM_EXCLUDE_ALL */
1616		− {{0, 0, 0}, 0, 1, true, false, 0, 0},
	684	+ {{0, 0}, 0, 1, true, false, 0, {0, 0}},
1617	685
1618	686	/* DBG_GRC_PARAM_CRASH */
1619		− {{0, 0, 0}, 0, 1, true, false, 0, 0},
	687	+ {{0, 0}, 0, 1, true, false, 0, {0, 0}},
1620	688
1621	689	/* DBG_GRC_PARAM_PARITY_SAFE */
1622		− {{0, 0, 0}, 0, 1, false, false, 1, 0},
	690	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1623	691
1624	692	/* DBG_GRC_PARAM_DUMP_CM */
1625		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	693	+ {{1, 1}, 0, 1, false, false, 0, {1, 1}},
1626	694
1627	695	/* DBG_GRC_PARAM_DUMP_PHY */
1628		− {{1, 1, 1}, 0, 1, false, false, 0, 1},
	696	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1629	697
1630	698	/* DBG_GRC_PARAM_NO_MCP */
1631		− {{0, 0, 0}, 0, 1, false, false, 0, 0},
	699	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1632	700
1633	701	/* DBG_GRC_PARAM_NO_FW_VER */
1634		− {{0, 0, 0}, 0, 1, false, false, 0, 0},
	702	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1635	703
1636	704	/* DBG_GRC_PARAM_RESERVED3 */
1637		− {{0, 0, 0}, 0, 1, false, false, 0, 0},
	705	+ {{0, 0}, 0, 1, false, false, 0, {0, 0}},
1638	706
1639	707	/* DBG_GRC_PARAM_DUMP_MCP_HW_DUMP */
1640		− {{0, 1, 1}, 0, 1, false, false, 0, 0},
	708	+ {{0, 1}, 0, 1, false, false, 0, {0, 1}},
1641	709
1642	710	/* DBG_GRC_PARAM_DUMP_ILT_CDUC */
1643		− {{1, 1, 1}, 0, 1, false, false, 0, 0},
	711	+ {{1, 1}, 0, 1, false, false, 0, {0, 0}},
1644	712
1645	713	/* DBG_GRC_PARAM_DUMP_ILT_CDUT */
1646		− {{1, 1, 1}, 0, 1, false, false, 0, 0},
	714	+ {{1, 1}, 0, 1, false, false, 0, {0, 0}},
1647	715
1648	716	/* DBG_GRC_PARAM_DUMP_CAU_EXT */
1649		− {{0, 0, 0}, 0, 1, false, false, 0, 1}
	717	+ {{0, 0}, 0, 1, false, false, 0, {1, 1}}
1650	718	};
1651	719
1652	720	static struct rss_mem_defs s_rss_mem_defs[] = {
1653		− { "rss_mem_cid", "rss_cid", 0, 32,
1654		− {256, 320, 512} },
	721	+ {"rss_mem_cid", "rss_cid", 0, 32,
	722	+ {256, 320}},
1655	723
1656		− { "rss_mem_key_msb", "rss_key", 1024, 256,
1657		− {128, 208, 257} },
	724	+ {"rss_mem_key_msb", "rss_key", 1024, 256,
	725	+ {128, 208}},
1658	726
1659		− { "rss_mem_key_lsb", "rss_key", 2048, 64,
1660		− {128, 208, 257} },
	727	+ {"rss_mem_key_lsb", "rss_key", 2048, 64,
	728	+ {128, 208}},
1661	729
1662		− { "rss_mem_info", "rss_info", 3072, 16,
1663		− {128, 208, 256} },
	730	+ {"rss_mem_info", "rss_info", 3072, 16,
	731	+ {128, 208}},
1664	732
1665		− { "rss_mem_ind", "rss_ind", 4096, 16,
1666		− {16384, 26624, 32768} }
	733	+ {"rss_mem_ind", "rss_ind", 4096, 16,
	734	+ {16384, 26624}}
1667	735	};
1668	736
1669	737	static struct vfc_ram_defs s_vfc_ram_defs[] = {
@@ -1674,54 +742,31 @@ static struct vfc_ram_defs s_vfc_ram_defs[] = { · 4 unmodified lines
1674	742	};
1675	743
1676	744	static struct big_ram_defs s_big_ram_defs[] = {
1677		− { "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB,
1678		− BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA,
1679		− MISC_REG_BLOCK_256B_EN, {0, 0, 0},
1680		− {153600, 180224, 282624} },
1681		−
1682		− { "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB,
1683		− BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA,
1684		− MISC_REG_BLOCK_256B_EN, {0, 1, 1},
1685		− {92160, 117760, 168960} },
1686		−
1687		− { "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB,
1688		− BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA,
1689		− MISCS_REG_BLOCK_256B_EN, {0, 0, 0},
1690		− {36864, 36864, 36864} }
1691		−};
1692		−
1693		−static struct reset_reg_defs s_reset_regs_defs[] = {
1694		− /* DBG_RESET_REG_MISCS_PL_UA */
1695		− { MISCS_REG_RESET_PL_UA,
1696		− {true, true, true}, {0x0, 0x0, 0x0} },
1697		−
1698		− /* DBG_RESET_REG_MISCS_PL_HV */
1699		− { MISCS_REG_RESET_PL_HV,
1700		− {true, true, true}, {0x0, 0x400, 0x600} },
	745	+ {"BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB,
	746	+ BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA,
	747	+ MISC_REG_BLOCK_256B_EN, {0, 0},
	748	+ {153600, 180224}},
1701	749
1702		− /* DBG_RESET_REG_MISCS_PL_HV_2 */
1703		− { MISCS_REG_RESET_PL_HV_2_K2_E5,
1704		− {false, true, true}, {0x0, 0x0, 0x0} },
	750	+ {"BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB,
	751	+ BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA,
	752	+ MISC_REG_BLOCK_256B_EN, {0, 1},
	753	+ {92160, 117760}},
1705	754
1706		− /* DBG_RESET_REG_MISC_PL_UA */
1707		− { MISC_REG_RESET_PL_UA,
1708		− {true, true, true}, {0x0, 0x0, 0x0} },
1709		−
1710		− /* DBG_RESET_REG_MISC_PL_HV */
1711		− { MISC_REG_RESET_PL_HV,
1712		− {true, true, true}, {0x0, 0x0, 0x0} },
1713		−
1714		− /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */
1715		− { MISC_REG_RESET_PL_PDA_VMAIN_1,
1716		− {true, true, true}, {0x4404040, 0x4404040, 0x404040} },
1717		−
1718		− /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */
1719		− { MISC_REG_RESET_PL_PDA_VMAIN_2,
1720		− {true, true, true}, {0x7, 0x7c00007, 0x5c08007} },
	755	+ {"BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB,
	756	+ BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA,
	757	+ MISCS_REG_BLOCK_256B_EN, {0, 0},
	758	+ {36864, 36864}}
	759	+};
1721	760
1722		− /* DBG_RESET_REG_MISC_PL_PDA_VAUX */
1723		− { MISC_REG_RESET_PL_PDA_VAUX,
1724		− {true, true, true}, {0x2, 0x2, 0x2} },
	761	+static struct rbc_reset_defs s_rbc_reset_defs[] = {
	762	+ {MISCS_REG_RESET_PL_HV,
	763	+ {0x0, 0x400}},
	764	+ {MISC_REG_RESET_PL_PDA_VMAIN_1,
	765	+ {0x4404040, 0x4404040}},
	766	+ {MISC_REG_RESET_PL_PDA_VMAIN_2,
	767	+ {0x7, 0x7c00007}},
	768	+ {MISC_REG_RESET_PL_PDA_VAUX,
	769	+ {0x2, 0x2}},
1725	770	};
1726	771
1727	772	static struct phy_defs s_phy_defs[] = {
@@ -1804,9 +849,19 @@ static void qed_dbg_grc_init_params(struct qed_hwfn *p_hwfn) · 76 unmodified lines
1804	849	}
1805	850	}
1806	851
	852	+/* Sets pointer and size for the specified binary buffer type */
	853	+static void qed_set_dbg_bin_buf(struct qed_hwfn *p_hwfn,
	854	+ enum bin_dbg_buffer_type buf_type,
	855	+ const u32 *ptr, u32 size)
	856	+{
	857	+ struct virt_mem_desc *buf = &p_hwfn->dbg_arrays[buf_type];
	858	+
	859	+ buf->ptr = (void *)ptr;
	860	+ buf->size = size;
	861	+}
	862	+
1807	863	/* Initializes debug data for the specified device */
1808		−static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn,
1809		− struct qed_ptt *p_ptt)
	864	+static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn)
1810	865	{
1811	866	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1812	867	u8 num_pfs = 0, max_pfs_per_port = 0;
@@ -1831,26 +886,25 @@ static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn, · 18 unmodified lines
1831	886	return DBG_STATUS_UNKNOWN_CHIP;
1832	887	}
1833	888
1834		− /* Set platofrm */
1835		− dev_data->platform_id = PLATFORM_ASIC;
	889	+ /* Set HW type */
	890	+ dev_data->hw_type = HW_TYPE_ASIC;
1836	891	dev_data->mode_enable[MODE_ASIC] = 1;
1837	892
1838	893	/* Set port mode */
1839		− switch (qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE)) {
1840		− case 0:
	894	+ switch (p_hwfn->cdev->num_ports_in_engine) {
	895	+ case 1:
1841	896	dev_data->mode_enable[MODE_PORTS_PER_ENG_1] = 1;
1842	897	break;
1843		− case 1:
	898	+ case 2:
1844	899	dev_data->mode_enable[MODE_PORTS_PER_ENG_2] = 1;
1845	900	break;
1846		− case 2:
	901	+ case 4:
1847	902	dev_data->mode_enable[MODE_PORTS_PER_ENG_4] = 1;
1848	903	break;
1849	904	}
1850	905
1851	906	/* Set 100G mode */
1852		− if (dev_data->chip_id == CHIP_BB &&
1853		− qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB) == 2)
	907	+ if (QED_IS_CMT(p_hwfn->cdev))
1854	908	dev_data->mode_enable[MODE_100G] = 1;
1855	909
1856	910	/* Set number of ports */
@@ -1876,14 +930,36 @@ static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn, · 19 unmodified lines
1876	930	return DBG_STATUS_OK;
1877	931	}
1878	932
1879		−static struct dbg_bus_block get_dbg_bus_block_desc(struct qed_hwfn p_hwfn,
1880		− enum block_id block_id)
	933	+static const struct dbg_block get_dbg_block(struct qed_hwfn p_hwfn,
	934	+ enum block_id block_id)
	935	+{
	936	+ const struct dbg_block *dbg_block;
	937	+
	938	+ dbg_block = p_hwfn->dbg_arrays[BIN_BUF_DBG_BLOCKS].ptr;
	939	+ return dbg_block + block_id;
	940	+}
	941	+
	942	+static const struct dbg_block_chip *qed_get_dbg_block_per_chip(struct qed_hwfn
	943	+ *p_hwfn,
	944	+ enum block_id
	945	+ block_id)
	946	+{
	947	+ struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	948	+
	949	+ return (const struct dbg_block_chip *)
	950	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_BLOCKS_CHIP_DATA].ptr +
	951	+ block_id * MAX_CHIP_IDS + dev_data->chip_id;
	952	+}
	953	+
	954	+static const struct dbg_reset_reg *qed_get_dbg_reset_reg(struct qed_hwfn
	955	+ *p_hwfn,
	956	+ u8 reset_reg_id)
1881	957	{
1882	958	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1883	959
1884		− return (struct dbg_bus_block )&dbg_bus_blocks[block_id
1885		− MAX_CHIP_IDS +
1886		− dev_data->chip_id];
	960	+ return (const struct dbg_reset_reg *)
	961	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_RESET_REGS].ptr +
	962	+ reset_reg_id * MAX_CHIP_IDS + dev_data->chip_id;
1887	963	}
1888	964
1889	965	/* Reads the FW info structure for the specified Storm from the chip,
@@ -1904,8 +980,9 @@ static void qed_read_storm_fw_info(struct qed_hwfn *p_hwfn, · 14 unmodified lines
1904	980	* The address is located in the last line of the Storm RAM.
1905	981	*/
1906	982	addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM +
1907		− DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) -
1908		− sizeof(fw_info_location);
	983	+ DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE) -
	984	+ sizeof(fw_info_location);
	985	+
1909	986	dest = (u32 *)&fw_info_location;
1910	987
1911	988	for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location));
@@ -2100,6 +1177,29 @@ static u32 qed_dump_mfw_ver_param(struct qed_hwfn *p_hwfn, · 188 unmodified lines
2100	1177	return qed_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str);
2101	1178	}
2102	1179
	1180	+/* Reads the chip revision from the chip and writes it as a param to the
	1181	+ * specified buffer. Returns the dumped size in dwords.
	1182	+ */
	1183	+static u32 qed_dump_chip_revision_param(struct qed_hwfn *p_hwfn,
	1184	+ struct qed_ptt *p_ptt,
	1185	+ u32 *dump_buf, bool dump)
	1186	+{
	1187	+ struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	1188	+ char param_str[3] = "??";
	1189	+
	1190	+ if (dev_data->hw_type == HW_TYPE_ASIC) {
	1191	+ u32 chip_rev, chip_metal;
	1192	+
	1193	+ chip_rev = qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
	1194	+ chip_metal = qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
	1195	+
	1196	+ param_str[0] = 'a' + (u8)chip_rev;
	1197	+ param_str[1] = '0' + (u8)chip_metal;
	1198	+ }
	1199	+
	1200	+ return qed_dump_str_param(dump_buf, dump, "chip-revision", param_str);
	1201	+}
	1202	+
2103	1203	/* Writes a section header to the specified buffer.
2104	1204	* Returns the dumped size in dwords.
2105	1205	*/
@@ -2123,7 +1223,8 @@ static u32 qed_dump_common_global_params(struct qed_hwfn *p_hwfn, · 17 unmodified lines
2123	1223	u8 num_params;
2124	1224
2125	1225	/* Dump global params section header */
2126		− num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params;
	1226	+ num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params +
	1227	+ (dev_data->chip_id == CHIP_BB ? 1 : 0);
2127	1228	offset += qed_dump_section_hdr(dump_buf + offset,
2128	1229	dump, "global_params", num_params);
2129	1230
@@ -2131,6 +1232,8 @@ static u32 qed_dump_common_global_params(struct qed_hwfn *p_hwfn, · 1 unmodified line
2131	1232	offset += qed_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump);
2132	1233	offset += qed_dump_mfw_ver_param(p_hwfn,
2133	1234	p_ptt, dump_buf + offset, dump);
	1235	+ offset += qed_dump_chip_revision_param(p_hwfn,
	1236	+ p_ptt, dump_buf + offset, dump);
2134	1237	offset += qed_dump_num_param(dump_buf + offset,
2135	1238	dump, "tools-version", TOOLS_VERSION);
2136	1239	offset += qed_dump_str_param(dump_buf + offset,
@@ -2140,11 +1243,12 @@ static u32 qed_dump_common_global_params(struct qed_hwfn *p_hwfn, · 3 unmodified lines
2140	1243	offset += qed_dump_str_param(dump_buf + offset,
2141	1244	dump,
2142	1245	"platform",
2143		− s_platform_defs[dev_data->platform_id].
2144		− name);
2145		− offset +=
2146		− qed_dump_num_param(dump_buf + offset, dump, "pci-func",
2147		− p_hwfn->abs_pf_id);
	1246	+ s_hw_type_defs[dev_data->hw_type].name);
	1247	+ offset += qed_dump_num_param(dump_buf + offset,
	1248	+ dump, "pci-func", p_hwfn->abs_pf_id);
	1249	+ if (dev_data->chip_id == CHIP_BB)
	1250	+ offset += qed_dump_num_param(dump_buf + offset,
	1251	+ dump, "path", QED_PATH_ID(p_hwfn));
2148	1252
2149	1253	return offset;
2150	1254	}
@@ -2175,24 +1279,87 @@ static void qed_update_blocks_reset_state(struct qed_hwfn *p_hwfn, · 24 unmodified lines
2175	1279	struct qed_ptt *p_ptt)
2176	1280	{
2177	1281	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2178		− u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
2179		− u32 i;
	1282	+ u32 reg_val[NUM_DBG_RESET_REGS] = { 0 };
	1283	+ u8 rst_reg_id;
	1284	+ u32 blk_id;
2180	1285
2181	1286	/* Read reset registers */
2182		− for (i = 0; i < MAX_DBG_RESET_REGS; i++)
2183		− if (s_reset_regs_defs[i].exists[dev_data->chip_id])
2184		− reg_val[i] = qed_rd(p_hwfn,
2185		− p_ptt, s_reset_regs_defs[i].addr);
	1287	+ for (rst_reg_id = 0; rst_reg_id < NUM_DBG_RESET_REGS; rst_reg_id++) {
	1288	+ const struct dbg_reset_reg *rst_reg;
	1289	+ bool rst_reg_removed;
	1290	+ u32 rst_reg_addr;
	1291	+
	1292	+ rst_reg = qed_get_dbg_reset_reg(p_hwfn, rst_reg_id);
	1293	+ rst_reg_removed = GET_FIELD(rst_reg->data,
	1294	+ DBG_RESET_REG_IS_REMOVED);
	1295	+ rst_reg_addr = DWORDS_TO_BYTES(GET_FIELD(rst_reg->data,
	1296	+ DBG_RESET_REG_ADDR));
	1297	+
	1298	+ if (!rst_reg_removed)
	1299	+ reg_val[rst_reg_id] = qed_rd(p_hwfn, p_ptt,
	1300	+ rst_reg_addr);
	1301	+ }
2186	1302
2187	1303	/* Check if blocks are in reset */
2188		− for (i = 0; i < MAX_BLOCK_ID; i++) {
2189		− struct block_defs *block = s_block_defs[i];
	1304	+ for (blk_id = 0; blk_id < NUM_PHYS_BLOCKS; blk_id++) {
	1305	+ const struct dbg_block_chip *blk;
	1306	+ bool has_rst_reg;
	1307	+ bool is_removed;
	1308	+
	1309	+ blk = qed_get_dbg_block_per_chip(p_hwfn, (enum block_id)blk_id);
	1310	+ is_removed = GET_FIELD(blk->flags, DBG_BLOCK_CHIP_IS_REMOVED);
	1311	+ has_rst_reg = GET_FIELD(blk->flags,
	1312	+ DBG_BLOCK_CHIP_HAS_RESET_REG);
	1313	+
	1314	+ if (!is_removed && has_rst_reg)
	1315	+ dev_data->block_in_reset[blk_id] =
	1316	+ !(reg_val[blk->reset_reg_id] &
	1317	+ BIT(blk->reset_reg_bit_offset));
	1318	+ }
	1319	+}
	1320	+
	1321	+/* is_mode_match recursive function */
	1322	+static bool qed_is_mode_match_rec(struct qed_hwfn *p_hwfn,
	1323	+ u16 *modes_buf_offset, u8 rec_depth)
	1324	+{
	1325	+ struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	1326	+ u8 *dbg_array;
	1327	+ bool arg1, arg2;
	1328	+ u8 tree_val;
	1329	+
	1330	+ if (rec_depth > MAX_RECURSION_DEPTH) {
	1331	+ DP_NOTICE(p_hwfn,
	1332	+ "Unexpected error: is_mode_match_rec exceeded the max recursion depth. This is probably due to a corrupt init/debug buffer.\n");
	1333	+ return false;
	1334	+ }
	1335	+
	1336	+ /* Get next element from modes tree buffer */
	1337	+ dbg_array = p_hwfn->dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr;
	1338	+ tree_val = dbg_array[(*modes_buf_offset)++];
2190	1339
2191		− dev_data->block_in_reset[i] = block->has_reset_bit &&
2192		− !(reg_val[block->reset_reg] & BIT(block->reset_bit_offset));
	1340	+ switch (tree_val) {
	1341	+ case INIT_MODE_OP_NOT:
	1342	+ return !qed_is_mode_match_rec(p_hwfn,
	1343	+ modes_buf_offset, rec_depth + 1);
	1344	+ case INIT_MODE_OP_OR:
	1345	+ case INIT_MODE_OP_AND:
	1346	+ arg1 = qed_is_mode_match_rec(p_hwfn,
	1347	+ modes_buf_offset, rec_depth + 1);
	1348	+ arg2 = qed_is_mode_match_rec(p_hwfn,
	1349	+ modes_buf_offset, rec_depth + 1);
	1350	+ return (tree_val == INIT_MODE_OP_OR) ? (arg1 \|\|
	1351	+ arg2) : (arg1 && arg2);
	1352	+ default:
	1353	+ return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0;
2193	1354	}
2194	1355	}
2195	1356
	1357	+/* Returns true if the mode (specified using modes_buf_offset) is enabled */
	1358	+static bool qed_is_mode_match(struct qed_hwfn p_hwfn, u16 modes_buf_offset)
	1359	+{
	1360	+ return qed_is_mode_match_rec(p_hwfn, modes_buf_offset, 0);
	1361	+}
	1362	+
2196	1363	/* Enable / disable the Debug block */
2197	1364	static void qed_bus_enable_dbg_block(struct qed_hwfn *p_hwfn,
2198	1365	struct qed_ptt *p_ptt, bool enable)
@@ -2204,23 +1371,21 @@ static void qed_bus_enable_dbg_block(struct qed_hwfn *p_hwfn, · 5 unmodified lines
2204	1371	static void qed_bus_reset_dbg_block(struct qed_hwfn *p_hwfn,
2205	1372	struct qed_ptt *p_ptt)
2206	1373	{
2207		− u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val;
2208		− struct block_defs *dbg_block = s_block_defs[BLOCK_DBG];
	1374	+ u32 reset_reg_addr, old_reset_reg_val, new_reset_reg_val;
	1375	+ const struct dbg_reset_reg *reset_reg;
	1376	+ const struct dbg_block_chip *block;
2209	1377
2210		− dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr;
2211		− old_reset_reg_val = qed_rd(p_hwfn, p_ptt, dbg_reset_reg_addr);
2212		− new_reset_reg_val =
2213		− old_reset_reg_val & ~BIT(dbg_block->reset_bit_offset);
	1378	+ block = qed_get_dbg_block_per_chip(p_hwfn, BLOCK_DBG);
	1379	+ reset_reg = qed_get_dbg_reset_reg(p_hwfn, block->reset_reg_id);
	1380	+ reset_reg_addr =
	1381	+ DWORDS_TO_BYTES(GET_FIELD(reset_reg->data, DBG_RESET_REG_ADDR));
2214	1382
2215		− qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val);
2216		− qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val);
2217		−}
	1383	+ old_reset_reg_val = qed_rd(p_hwfn, p_ptt, reset_reg_addr);
	1384	+ new_reset_reg_val =
	1385	+ old_reset_reg_val & ~BIT(block->reset_reg_bit_offset);
2218	1386
2219		−static void qed_bus_set_framing_mode(struct qed_hwfn *p_hwfn,
2220		− struct qed_ptt *p_ptt,
2221		− enum dbg_bus_frame_modes mode)
2222		−{
2223		− qed_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode);
	1387	+ qed_wr(p_hwfn, p_ptt, reset_reg_addr, new_reset_reg_val);
	1388	+ qed_wr(p_hwfn, p_ptt, reset_reg_addr, old_reset_reg_val);
2224	1389	}
2225	1390
2226	1391	/* Enable / disable Debug Bus clients according to the specified mask
@@ -2232,28 +1397,65 @@ static void qed_bus_enable_clients(struct qed_hwfn *p_hwfn, · 5 unmodified lines
2232	1397	qed_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask);
2233	1398	}
2234	1399
2235		−static bool qed_is_mode_match(struct qed_hwfn p_hwfn, u16 modes_buf_offset)
	1400	+static void qed_bus_config_dbg_line(struct qed_hwfn *p_hwfn,
	1401	+ struct qed_ptt *p_ptt,
	1402	+ enum block_id block_id,
	1403	+ u8 line_id,
	1404	+ u8 enable_mask,
	1405	+ u8 right_shift,
	1406	+ u8 force_valid_mask, u8 force_frame_mask)
	1407	+{
	1408	+ const struct dbg_block_chip *block =
	1409	+ qed_get_dbg_block_per_chip(p_hwfn, block_id);
	1410	+
	1411	+ qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_select_reg_addr),
	1412	+ line_id);
	1413	+ qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_dword_enable_reg_addr),
	1414	+ enable_mask);
	1415	+ qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_shift_reg_addr),
	1416	+ right_shift);
	1417	+ qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_force_valid_reg_addr),
	1418	+ force_valid_mask);
	1419	+ qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_force_frame_reg_addr),
	1420	+ force_frame_mask);
	1421	+}
	1422	+
	1423	+/* Disable debug bus in all blocks */
	1424	+static void qed_bus_disable_blocks(struct qed_hwfn *p_hwfn,
	1425	+ struct qed_ptt *p_ptt)
2236	1426	{
2237	1427	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2238		− bool arg1, arg2;
2239		− const u32 *ptr;
2240		− u8 tree_val;
	1428	+ u32 block_id;
2241	1429
2242		− /* Get next element from modes tree buffer */
2243		− ptr = s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr;
2244		− tree_val = ((u8 )ptr)[(modes_buf_offset)++];
	1430	+ /* Disable all blocks */
	1431	+ for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
	1432	+ const struct dbg_block_chip *block_per_chip =
	1433	+ qed_get_dbg_block_per_chip(p_hwfn,
	1434	+ (enum block_id)block_id);
2245	1435
2246		− switch (tree_val) {
2247		− case INIT_MODE_OP_NOT:
2248		− return !qed_is_mode_match(p_hwfn, modes_buf_offset);
2249		− case INIT_MODE_OP_OR:
2250		− case INIT_MODE_OP_AND:
2251		− arg1 = qed_is_mode_match(p_hwfn, modes_buf_offset);
2252		− arg2 = qed_is_mode_match(p_hwfn, modes_buf_offset);
2253		− return (tree_val == INIT_MODE_OP_OR) ? (arg1 \|\|
2254		− arg2) : (arg1 && arg2);
2255		− default:
2256		− return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0;
	1436	+ if (GET_FIELD(block_per_chip->flags,
	1437	+ DBG_BLOCK_CHIP_IS_REMOVED) \|\|
	1438	+ dev_data->block_in_reset[block_id])
	1439	+ continue;
	1440	+
	1441	+ /* Disable debug bus */
	1442	+ if (GET_FIELD(block_per_chip->flags,
	1443	+ DBG_BLOCK_CHIP_HAS_DBG_BUS)) {
	1444	+ u32 dbg_en_addr =
	1445	+ block_per_chip->dbg_dword_enable_reg_addr;
	1446	+ u16 modes_buf_offset =
	1447	+ GET_FIELD(block_per_chip->dbg_bus_mode.data,
	1448	+ DBG_MODE_HDR_MODES_BUF_OFFSET);
	1449	+ bool eval_mode =
	1450	+ GET_FIELD(block_per_chip->dbg_bus_mode.data,
	1451	+ DBG_MODE_HDR_EVAL_MODE) > 0;
	1452	+
	1453	+ if (!eval_mode \|\|
	1454	+ qed_is_mode_match(p_hwfn, &modes_buf_offset))
	1455	+ qed_wr(p_hwfn, p_ptt,
	1456	+ DWORDS_TO_BYTES(dbg_en_addr),
	1457	+ 0);
	1458	+ }
2257	1459	}
2258	1460	}
2259	1461
@@ -2266,6 +1468,20 @@ static bool qed_grc_is_included(struct qed_hwfn *p_hwfn, · 6 unmodified lines
2266	1468	return qed_grc_get_param(p_hwfn, grc_param) > 0;
2267	1469	}
2268	1470
	1471	+/* Returns the storm_id that matches the specified Storm letter,
	1472	+ * or MAX_DBG_STORMS if invalid storm letter.
	1473	+ */
	1474	+static enum dbg_storms qed_get_id_from_letter(char storm_letter)
	1475	+{
	1476	+ u8 storm_id;
	1477	+
	1478	+ for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++)
	1479	+ if (s_storm_defs[storm_id].letter == storm_letter)
	1480	+ return (enum dbg_storms)storm_id;
	1481	+
	1482	+ return MAX_DBG_STORMS;
	1483	+}
	1484	+
2269	1485	/* Returns true of the specified Storm should be included in the dump, false
2270	1486	* otherwise.
2271	1487	*/
@@ -2281,14 +1497,20 @@ static bool qed_grc_is_storm_included(struct qed_hwfn *p_hwfn, · 9 unmodified lines
2281	1497	static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn,
2282	1498	enum block_id block_id, u8 mem_group_id)
2283	1499	{
2284		− struct block_defs *block = s_block_defs[block_id];
	1500	+ const struct dbg_block *block;
2285	1501	u8 i;
2286	1502
2287		− /* Check Storm match */
2288		− if (block->associated_to_storm &&
2289		− !qed_grc_is_storm_included(p_hwfn,
2290		− (enum dbg_storms)block->storm_id))
2291		− return false;
	1503	+ block = get_dbg_block(p_hwfn, block_id);
	1504	+
	1505	+ /* If the block is associated with a Storm, check Storm match */
	1506	+ if (block->associated_storm_letter) {
	1507	+ enum dbg_storms associated_storm_id =
	1508	+ qed_get_id_from_letter(block->associated_storm_letter);
	1509	+
	1510	+ if (associated_storm_id == MAX_DBG_STORMS \|\|
	1511	+ !qed_grc_is_storm_included(p_hwfn, associated_storm_id))
	1512	+ return false;
	1513	+ }
2292	1514
2293	1515	for (i = 0; i < NUM_BIG_RAM_TYPES; i++) {
2294	1516	struct big_ram_defs *big_ram = &s_big_ram_defs[i];
@@ -2310,6 +1532,8 @@ static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn, · 15 unmodified lines
2310	1532	case MEM_GROUP_CAU_SB:
2311	1533	case MEM_GROUP_CAU_PI:
2312	1534	return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU);
	1535	+ case MEM_GROUP_CAU_MEM_EXT:
	1536	+ return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU_EXT);
2313	1537	case MEM_GROUP_QM_MEM:
2314	1538	return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_QM);
2315	1539	case MEM_GROUP_CFC_MEM:
@@ -2317,6 +1541,8 @@ static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn, · 1 unmodified line
2317	1541	case MEM_GROUP_TASK_CFC_MEM:
2318	1542	return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC) \|\|
2319	1543	qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX);
	1544	+ case MEM_GROUP_DORQ_MEM:
	1545	+ return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DORQ);
2320	1546	case MEM_GROUP_IGU_MEM:
2321	1547	case MEM_GROUP_IGU_MSIX:
2322	1548	return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU);
@@ -2362,64 +1588,104 @@ static void qed_grc_stall_storms(struct qed_hwfn *p_hwfn, · 39 unmodified lines
2362	1588	msleep(STALL_DELAY_MS);
2363	1589	}
2364	1590
2365		−/* Takes all blocks out of reset */
	1591	+/* Takes all blocks out of reset. If rbc_only is true, only RBC clients are
	1592	+ * taken out of reset.
	1593	+ */
2366	1594	static void qed_grc_unreset_blocks(struct qed_hwfn *p_hwfn,
2367		− struct qed_ptt *p_ptt)
	1595	+ struct qed_ptt *p_ptt, bool rbc_only)
2368	1596	{
2369	1597	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2370		− u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
2371		− u32 block_id, i;
	1598	+ u8 chip_id = dev_data->chip_id;
	1599	+ u32 i;
2372	1600
2373		− /* Fill reset regs values */
2374		− for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
2375		− struct block_defs *block = s_block_defs[block_id];
	1601	+ /* Take RBCs out of reset */
	1602	+ for (i = 0; i < ARRAY_SIZE(s_rbc_reset_defs); i++)
	1603	+ if (s_rbc_reset_defs[i].reset_val[dev_data->chip_id])
	1604	+ qed_wr(p_hwfn,
	1605	+ p_ptt,
	1606	+ s_rbc_reset_defs[i].reset_reg_addr +
	1607	+ RESET_REG_UNRESET_OFFSET,
	1608	+ s_rbc_reset_defs[i].reset_val[chip_id]);
2376	1609
2377		− if (block->exists[dev_data->chip_id] && block->has_reset_bit &&
2378		− block->unreset)
2379		− reg_val[block->reset_reg] \|=
2380		− BIT(block->reset_bit_offset);
2381		− }
	1610	+ if (!rbc_only) {
	1611	+ u32 reg_val[NUM_DBG_RESET_REGS] = { 0 };
	1612	+ u8 reset_reg_id;
	1613	+ u32 block_id;
2382	1614
2383		− /* Write reset registers */
2384		− for (i = 0; i < MAX_DBG_RESET_REGS; i++) {
2385		− if (!s_reset_regs_defs[i].exists[dev_data->chip_id])
2386		− continue;
	1615	+ /* Fill reset regs values */
	1616	+ for (block_id = 0; block_id < NUM_PHYS_BLOCKS; block_id++) {
	1617	+ bool is_removed, has_reset_reg, unreset_before_dump;
	1618	+ const struct dbg_block_chip *block;
	1619	+
	1620	+ block = qed_get_dbg_block_per_chip(p_hwfn,
	1621	+ (enum block_id)
	1622	+ block_id);
	1623	+ is_removed =
	1624	+ GET_FIELD(block->flags, DBG_BLOCK_CHIP_IS_REMOVED);
	1625	+ has_reset_reg =
	1626	+ GET_FIELD(block->flags,
	1627	+ DBG_BLOCK_CHIP_HAS_RESET_REG);
	1628	+ unreset_before_dump =
	1629	+ GET_FIELD(block->flags,
	1630	+ DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP);
	1631	+
	1632	+ if (!is_removed && has_reset_reg && unreset_before_dump)
	1633	+ reg_val[block->reset_reg_id] \|=
	1634	+ BIT(block->reset_reg_bit_offset);
	1635	+ }
2387	1636
2388		− reg_val[i] \|=
2389		− s_reset_regs_defs[i].unreset_val[dev_data->chip_id];
	1637	+ /* Write reset registers */
	1638	+ for (reset_reg_id = 0; reset_reg_id < NUM_DBG_RESET_REGS;
	1639	+ reset_reg_id++) {
	1640	+ const struct dbg_reset_reg *reset_reg;
	1641	+ u32 reset_reg_addr;
2390	1642
2391		− if (reg_val[i])
2392		− qed_wr(p_hwfn,
2393		− p_ptt,
2394		− s_reset_regs_defs[i].addr +
2395		− RESET_REG_UNRESET_OFFSET, reg_val[i]);
	1643	+ reset_reg = qed_get_dbg_reset_reg(p_hwfn, reset_reg_id);
	1644	+
	1645	+ if (GET_FIELD
	1646	+ (reset_reg->data, DBG_RESET_REG_IS_REMOVED))
	1647	+ continue;
	1648	+
	1649	+ if (reg_val[reset_reg_id]) {
	1650	+ reset_reg_addr =
	1651	+ GET_FIELD(reset_reg->data,
	1652	+ DBG_RESET_REG_ADDR);
	1653	+ qed_wr(p_hwfn,
	1654	+ p_ptt,
	1655	+ DWORDS_TO_BYTES(reset_reg_addr) +
	1656	+ RESET_REG_UNRESET_OFFSET,
	1657	+ reg_val[reset_reg_id]);
	1658	+ }
	1659	+ }
2396	1660	}
2397	1661	}
2398	1662
2399	1663	/* Returns the attention block data of the specified block */
2400	1664	static const struct dbg_attn_block_type_data *
2401		−qed_get_block_attn_data(enum block_id block_id, enum dbg_attn_type attn_type)
	1665	+qed_get_block_attn_data(struct qed_hwfn *p_hwfn,
	1666	+ enum block_id block_id, enum dbg_attn_type attn_type)
2402	1667	{
2403	1668	const struct dbg_attn_block *base_attn_block_arr =
2404		− (const struct dbg_attn_block *)
2405		− s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr;
	1669	+ (const struct dbg_attn_block *)
	1670	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr;
2406	1671
2407	1672	return &base_attn_block_arr[block_id].per_type_data[attn_type];
2408	1673	}
2409	1674
2410	1675	/* Returns the attention registers of the specified block */
2411	1676	static const struct dbg_attn_reg *
2412		−qed_get_block_attn_regs(enum block_id block_id, enum dbg_attn_type attn_type,
	1677	+qed_get_block_attn_regs(struct qed_hwfn *p_hwfn,
	1678	+ enum block_id block_id, enum dbg_attn_type attn_type,
2413	1679	u8 *num_attn_regs)
2414	1680	{
2415	1681	const struct dbg_attn_block_type_data *block_type_data =
2416		− qed_get_block_attn_data(block_id, attn_type);
	1682	+ qed_get_block_attn_data(p_hwfn, block_id, attn_type);
2417	1683
2418	1684	*num_attn_regs = block_type_data->num_regs;
2419	1685
2420		− return &((const struct dbg_attn_reg *)
2421		− s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)[block_type_data->
2422		− regs_offset];
	1686	+ return (const struct dbg_attn_reg *)
	1687	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr +
	1688	+ block_type_data->regs_offset;
2423	1689	}
2424	1690
2425	1691	/* For each block, clear the status of all parities */
@@ -2431,11 +1697,12 @@ static void qed_grc_clear_all_prty(struct qed_hwfn *p_hwfn, · 5 unmodified lines
2431	1697	u8 reg_idx, num_attn_regs;
2432	1698	u32 block_id;
2433	1699
2434		− for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
	1700	+ for (block_id = 0; block_id < NUM_PHYS_BLOCKS; block_id++) {
2435	1701	if (dev_data->block_in_reset[block_id])
2436	1702	continue;
2437	1703
2438		− attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id,
	1704	+ attn_reg_arr = qed_get_block_attn_regs(p_hwfn,
	1705	+ (enum block_id)block_id,
2439	1706	ATTN_TYPE_PARITY,
2440	1707	&num_attn_regs);
2441	1708
@@ -2463,22 +1730,20 @@ static void qed_grc_clear_all_prty(struct qed_hwfn *p_hwfn, · 21 unmodified lines
2463	1730	}
2464	1731
2465	1732	/* Dumps GRC registers section header. Returns the dumped size in dwords.
2466		− * The following parameters are dumped:
	1733	+ * the following parameters are dumped:
2467	1734	* - count: no. of dumped entries
2468	1735	* - split_type: split type
2469	1736	* - split_id: split ID (dumped only if split_id != SPLIT_TYPE_NONE)
2470		− * - param_name: user parameter value (dumped only if param_name != NULL
2471		− * and param_val != NULL).
	1737	+ * - reg_type_name: register type name (dumped only if reg_type_name != NULL)
2472	1738	*/
2473	1739	static u32 qed_grc_dump_regs_hdr(u32 *dump_buf,
2474	1740	bool dump,
2475	1741	u32 num_reg_entries,
2476	1742	enum init_split_types split_type,
2477		− u8 split_id,
2478		− const char param_name, const char param_val)
	1743	+ u8 split_id, const char *reg_type_name)
2479	1744	{
2480	1745	u8 num_params = 2 +
2481		− (split_type != SPLIT_TYPE_NONE ? 1 : 0) + (param_name ? 1 : 0);
	1746	+ (split_type != SPLIT_TYPE_NONE ? 1 : 0) + (reg_type_name ? 1 : 0);
2482	1747	u32 offset = 0;
2483	1748
2484	1749	offset += qed_dump_section_hdr(dump_buf + offset,
@@ -2491,9 +1756,9 @@ static u32 qed_grc_dump_regs_hdr(u32 *dump_buf, · 6 unmodified lines
2491	1756	if (split_type != SPLIT_TYPE_NONE)
2492	1757	offset += qed_dump_num_param(dump_buf + offset,
2493	1758	dump, "id", split_id);
2494		− if (param_name && param_val)
	1759	+ if (reg_type_name)
2495	1760	offset += qed_dump_str_param(dump_buf + offset,
2496		− dump, param_name, param_val);
	1761	+ dump, "type", reg_type_name);
2497	1762
2498	1763	return offset;
2499	1764	}
@@ -2523,20 +1788,11 @@ static u32 qed_grc_dump_addr_range(struct qed_hwfn *p_hwfn, · 23 unmodified lines
2523	1788	{
2524	1789	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2525	1790	u8 port_id = 0, pf_id = 0, vf_id = 0, fid = 0;
	1791	+ bool read_using_dmae = false;
	1792	+ u32 thresh;
2526	1793
2527		− if (!dump)
2528		− return len;
2529		−
2530		− /* Print log if needed */
2531		− dev_data->num_regs_read += len;
2532		− if (dev_data->num_regs_read >=
2533		− s_platform_defs[dev_data->platform_id].log_thresh) {
2534		− DP_VERBOSE(p_hwfn,
2535		− QED_MSG_DEBUG,
2536		− "Dumping %d registers...\n",
2537		− dev_data->num_regs_read);
2538		− dev_data->num_regs_read = 0;
2539		− }
	1794	+ if (!dump)
	1795	+ return len;
2540	1796
2541	1797	switch (split_type) {
2542	1798	case SPLIT_TYPE_PORT:
@@ -2558,38 +1814,77 @@ static u32 qed_grc_dump_addr_range(struct qed_hwfn *p_hwfn, · 15 unmodified lines
2558	1814	}
2559	1815
2560	1816	/* Try reading using DMAE */
2561		− if (dev_data->use_dmae && split_type == SPLIT_TYPE_NONE &&
2562		− (len >= s_platform_defs[dev_data->platform_id].dmae_thresh \|\|
2563		− wide_bus)) {
2564		− if (!qed_dmae_grc2host(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr),
2565		− (u64)(uintptr_t)(dump_buf), len, NULL))
2566		− return len;
2567		− dev_data->use_dmae = 0;
2568		− DP_VERBOSE(p_hwfn,
2569		− QED_MSG_DEBUG,
2570		− "Failed reading from chip using DMAE, using GRC instead\n");
	1817	+ if (dev_data->use_dmae && split_type != SPLIT_TYPE_VF &&
	1818	+ (len >= s_hw_type_defs[dev_data->hw_type].dmae_thresh \|\|
	1819	+ (PROTECT_WIDE_BUS && wide_bus))) {
	1820	+ struct qed_dmae_params dmae_params;
	1821	+
	1822	+ /* Set DMAE params */
	1823	+ memset(&dmae_params, 0, sizeof(dmae_params));
	1824	+ SET_FIELD(dmae_params.flags, QED_DMAE_PARAMS_COMPLETION_DST, 1);
	1825	+ switch (split_type) {
	1826	+ case SPLIT_TYPE_PORT:
	1827	+ SET_FIELD(dmae_params.flags, QED_DMAE_PARAMS_PORT_VALID,
	1828	+ 1);
	1829	+ dmae_params.port_id = port_id;
	1830	+ break;
	1831	+ case SPLIT_TYPE_PF:
	1832	+ SET_FIELD(dmae_params.flags,
	1833	+ QED_DMAE_PARAMS_SRC_PF_VALID, 1);
	1834	+ dmae_params.src_pfid = pf_id;
	1835	+ break;
	1836	+ case SPLIT_TYPE_PORT_PF:
	1837	+ SET_FIELD(dmae_params.flags, QED_DMAE_PARAMS_PORT_VALID,
	1838	+ 1);
	1839	+ SET_FIELD(dmae_params.flags,
	1840	+ QED_DMAE_PARAMS_SRC_PF_VALID, 1);
	1841	+ dmae_params.port_id = port_id;
	1842	+ dmae_params.src_pfid = pf_id;
	1843	+ break;
	1844	+ default:
	1845	+ break;
	1846	+ }
	1847	+
	1848	+ /* Execute DMAE command */
	1849	+ read_using_dmae = !qed_dmae_grc2host(p_hwfn,
	1850	+ p_ptt,
	1851	+ DWORDS_TO_BYTES(addr),
	1852	+ (u64)(uintptr_t)(dump_buf),
	1853	+ len, &dmae_params);
	1854	+ if (!read_using_dmae) {
	1855	+ dev_data->use_dmae = 0;
	1856	+ DP_VERBOSE(p_hwfn,
	1857	+ QED_MSG_DEBUG,
	1858	+ "Failed reading from chip using DMAE, using GRC instead\n");
	1859	+ }
2571	1860	}
2572	1861
	1862	+ if (read_using_dmae)
	1863	+ goto print_log;
	1864	+
2573	1865	/* If not read using DMAE, read using GRC */
2574	1866
2575	1867	/* Set pretend */
2576		− if (split_type != dev_data->pretend.split_type \|\| split_id !=
2577		− dev_data->pretend.split_id) {
	1868	+ if (split_type != dev_data->pretend.split_type \|\|
	1869	+ split_id != dev_data->pretend.split_id) {
2578	1870	switch (split_type) {
2579	1871	case SPLIT_TYPE_PORT:
2580	1872	qed_port_pretend(p_hwfn, p_ptt, port_id);
2581	1873	break;
2582	1874	case SPLIT_TYPE_PF:
2583		− fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
	1875	+ fid = FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_PFID,
	1876	+ pf_id);
2584	1877	qed_fid_pretend(p_hwfn, p_ptt, fid);
2585	1878	break;
2586	1879	case SPLIT_TYPE_PORT_PF:
2587		− fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
	1880	+ fid = FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_PFID,
	1881	+ pf_id);
2588	1882	qed_port_fid_pretend(p_hwfn, p_ptt, port_id, fid);
2589	1883	break;
2590	1884	case SPLIT_TYPE_VF:
2591		− fid = BIT(PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT) \|
2592		− (vf_id << PXP_PRETEND_CONCRETE_FID_VFID_SHIFT);
	1885	+ fid = FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_VFVALID, 1)
	1886	+ \| FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_VFID,
	1887	+ vf_id);
2593	1888	qed_fid_pretend(p_hwfn, p_ptt, fid);
2594	1889	break;
2595	1890	default:
@@ -2603,6 +1898,16 @@ static u32 qed_grc_dump_addr_range(struct qed_hwfn *p_hwfn, · 7 unmodified lines
2603	1898	/* Read registers using GRC */
2604	1899	qed_read_regs(p_hwfn, p_ptt, dump_buf, addr, len);
2605	1900
	1901	+print_log:
	1902	+ /* Print log */
	1903	+ dev_data->num_regs_read += len;
	1904	+ thresh = s_hw_type_defs[dev_data->hw_type].log_thresh;
	1905	+ if ((dev_data->num_regs_read / thresh) >
	1906	+ ((dev_data->num_regs_read - len) / thresh))
	1907	+ DP_VERBOSE(p_hwfn,
	1908	+ QED_MSG_DEBUG,
	1909	+ "Dumped %d registers...\n", dev_data->num_regs_read);
	1910	+
2606	1911	return len;
2607	1912	}
2608	1913
@@ -2687,7 +1992,7 @@ static u32 qed_grc_dump_reg_entry_skip(struct qed_hwfn *p_hwfn, · 78 unmodified lines
2687	1992	/* Dumps GRC registers entries. Returns the dumped size in dwords. */
2688	1993	static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn,
2689	1994	struct qed_ptt *p_ptt,
2690		− struct dbg_array input_regs_arr,
	1995	+ struct virt_mem_desc input_regs_arr,
2691	1996	u32 *dump_buf,
2692	1997	bool dump,
2693	1998	enum init_split_types split_type,
@@ -2700,10 +2005,10 @@ static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn, · 6 unmodified lines
2700	2005
2701	2006	*num_dumped_reg_entries = 0;
2702	2007
2703		− while (input_offset < input_regs_arr.size_in_dwords) {
	2008	+ while (input_offset < BYTES_TO_DWORDS(input_regs_arr.size)) {
2704	2009	const struct dbg_dump_cond_hdr *cond_hdr =
2705	2010	(const struct dbg_dump_cond_hdr *)
2706		− &input_regs_arr.ptr[input_offset++];
	2011	+ input_regs_arr.ptr + input_offset++;
2707	2012	u16 modes_buf_offset;
2708	2013	bool eval_mode;
2709	2014
@@ -2726,7 +2031,7 @@ static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn, · 16 unmodified lines
2726	2031	for (i = 0; i < cond_hdr->data_size; i++, input_offset++) {
2727	2032	const struct dbg_dump_reg *reg =
2728	2033	(const struct dbg_dump_reg *)
2729		− &input_regs_arr.ptr[input_offset];
	2034	+ input_regs_arr.ptr + input_offset;
2730	2035	u32 addr, len;
2731	2036	bool wide_bus;
2732	2037
@@ -2751,14 +2056,12 @@ static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn, · 18 unmodified lines
2751	2056	/* Dumps GRC registers entries. Returns the dumped size in dwords. */
2752	2057	static u32 qed_grc_dump_split_data(struct qed_hwfn *p_hwfn,
2753	2058	struct qed_ptt *p_ptt,
2754		− struct dbg_array input_regs_arr,
	2059	+ struct virt_mem_desc input_regs_arr,
2755	2060	u32 *dump_buf,
2756	2061	bool dump,
2757	2062	bool block_enable[MAX_BLOCK_ID],
2758	2063	enum init_split_types split_type,
2759		− u8 split_id,
2760		− const char *param_name,
2761		− const char *param_val)
	2064	+ u8 split_id, const char *reg_type_name)
2762	2065	{
2763	2066	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2764	2067	enum init_split_types hdr_split_type = split_type;
@@ -2776,7 +2079,7 @@ static u32 qed_grc_dump_split_data(struct qed_hwfn *p_hwfn, · 11 unmodified lines
2776	2079	false,
2777	2080	0,
2778	2081	hdr_split_type,
2779		− hdr_split_id, param_name, param_val);
	2082	+ hdr_split_id, reg_type_name);
2780	2083
2781	2084	/* Dump registers */
2782	2085	offset += qed_grc_dump_regs_entries(p_hwfn,
@@ -2795,7 +2098,7 @@ static u32 qed_grc_dump_split_data(struct qed_hwfn *p_hwfn, · 12 unmodified lines
2795	2098	dump,
2796	2099	num_dumped_reg_entries,
2797	2100	hdr_split_type,
2798		− hdr_split_id, param_name, param_val);
	2101	+ hdr_split_id, reg_type_name);
2799	2102
2800	2103	return num_dumped_reg_entries > 0 ? offset : 0;
2801	2104	}
@@ -2808,32 +2111,33 @@ static u32 qed_grc_dump_registers(struct qed_hwfn *p_hwfn, · 6 unmodified lines
2808	2111	u32 *dump_buf,
2809	2112	bool dump,
2810	2113	bool block_enable[MAX_BLOCK_ID],
2811		− const char param_name, const char param_val)
	2114	+ const char *reg_type_name)
2812	2115	{
	2116	+ struct virt_mem_desc *dbg_buf =
	2117	+ &p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_REG];
2813	2118	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2814	2119	u32 offset = 0, input_offset = 0;
2815		− u16 fid;
2816		− while (input_offset <
2817		− s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) {
	2120	+
	2121	+ while (input_offset < BYTES_TO_DWORDS(dbg_buf->size)) {
2818	2122	const struct dbg_dump_split_hdr *split_hdr;
2819		− struct dbg_array curr_input_regs_arr;
	2123	+ struct virt_mem_desc curr_input_regs_arr;
2820	2124	enum init_split_types split_type;
2821	2125	u16 split_count = 0;
2822	2126	u32 split_data_size;
2823	2127	u8 split_id;
2824	2128
2825	2129	split_hdr =
2826		− (const struct dbg_dump_split_hdr *)
2827		− &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset++];
	2130	+ (const struct dbg_dump_split_hdr *)
	2131	+ dbg_buf->ptr + input_offset++;
2828	2132	split_type =
2829		− GET_FIELD(split_hdr->hdr,
2830		− DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
2831		− split_data_size =
2832		− GET_FIELD(split_hdr->hdr,
2833		− DBG_DUMP_SPLIT_HDR_DATA_SIZE);
	2133	+ GET_FIELD(split_hdr->hdr,
	2134	+ DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
	2135	+ split_data_size = GET_FIELD(split_hdr->hdr,
	2136	+ DBG_DUMP_SPLIT_HDR_DATA_SIZE);
2834	2137	curr_input_regs_arr.ptr =
2835		− &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset];
2836		− curr_input_regs_arr.size_in_dwords = split_data_size;
	2138	+ (u32 *)p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr +
	2139	+ input_offset;
	2140	+ curr_input_regs_arr.size = DWORDS_TO_BYTES(split_data_size);
2837	2141
2838	2142	switch (split_type) {
2839	2143	case SPLIT_TYPE_NONE:
@@ -2861,16 +2165,16 @@ static u32 qed_grc_dump_registers(struct qed_hwfn *p_hwfn, · 21 unmodified lines
2861	2165	dump, block_enable,
2862	2166	split_type,
2863	2167	split_id,
2864		− param_name,
2865		− param_val);
	2168	+ reg_type_name);
2866	2169
2867	2170	input_offset += split_data_size;
2868	2171	}
2869	2172
2870	2173	/* Cancel pretends (pretend to original PF) */
2871	2174	if (dump) {
2872		− fid = p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
2873		− qed_fid_pretend(p_hwfn, p_ptt, fid);
	2175	+ qed_fid_pretend(p_hwfn, p_ptt,
	2176	+ FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_PFID,
	2177	+ p_hwfn->rel_pf_id));
2874	2178	dev_data->pretend.split_type = SPLIT_TYPE_NONE;
2875	2179	dev_data->pretend.split_id = 0;
2876	2180	}
@@ -2883,26 +2187,32 @@ static u32 qed_grc_dump_reset_regs(struct qed_hwfn *p_hwfn, · 6 unmodified lines
2883	2187	struct qed_ptt *p_ptt,
2884	2188	u32 *dump_buf, bool dump)
2885	2189	{
2886		− struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2887		− u32 i, offset = 0, num_regs = 0;
	2190	+ u32 offset = 0, num_regs = 0;
	2191	+ u8 reset_reg_id;
2888	2192
2889	2193	/* Calculate header size */
2890	2194	offset += qed_grc_dump_regs_hdr(dump_buf,
2891		− false, 0,
2892		− SPLIT_TYPE_NONE, 0, NULL, NULL);
	2195	+ false,
	2196	+ 0, SPLIT_TYPE_NONE, 0, "RESET_REGS");
2893	2197
2894	2198	/* Write reset registers */
2895		− for (i = 0; i < MAX_DBG_RESET_REGS; i++) {
2896		− if (!s_reset_regs_defs[i].exists[dev_data->chip_id])
	2199	+ for (reset_reg_id = 0; reset_reg_id < NUM_DBG_RESET_REGS;
	2200	+ reset_reg_id++) {
	2201	+ const struct dbg_reset_reg *reset_reg;
	2202	+ u32 reset_reg_addr;
	2203	+
	2204	+ reset_reg = qed_get_dbg_reset_reg(p_hwfn, reset_reg_id);
	2205	+
	2206	+ if (GET_FIELD(reset_reg->data, DBG_RESET_REG_IS_REMOVED))
2897	2207	continue;
2898	2208
	2209	+ reset_reg_addr = GET_FIELD(reset_reg->data, DBG_RESET_REG_ADDR);
2899	2210	offset += qed_grc_dump_reg_entry(p_hwfn,
2900	2211	p_ptt,
2901	2212	dump_buf + offset,
2902	2213	dump,
2903		− BYTES_TO_DWORDS
2904		− (s_reset_regs_defs[i].addr), 1,
2905		− false, SPLIT_TYPE_NONE, 0);
	2214	+ reset_reg_addr,
	2215	+ 1, false, SPLIT_TYPE_NONE, 0);
2906	2216	num_regs++;
2907	2217	}
2908	2218
@@ -2910,7 +2220,7 @@ static u32 qed_grc_dump_reset_regs(struct qed_hwfn *p_hwfn, · 1 unmodified line
2910	2220	if (dump)
2911	2221	qed_grc_dump_regs_hdr(dump_buf,
2912	2222	true, num_regs, SPLIT_TYPE_NONE,
2913		− 0, NULL, NULL);
	2223	+ 0, "RESET_REGS");
2914	2224
2915	2225	return offset;
2916	2226	}
@@ -2923,21 +2233,23 @@ static u32 qed_grc_dump_modified_regs(struct qed_hwfn *p_hwfn, · 6 unmodified lines
2923	2233	u32 *dump_buf, bool dump)
2924	2234	{
2925	2235	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2926		− u32 block_id, offset = 0, num_reg_entries = 0;
	2236	+ u32 block_id, offset = 0, stall_regs_offset;
2927	2237	const struct dbg_attn_reg *attn_reg_arr;
2928	2238	u8 storm_id, reg_idx, num_attn_regs;
	2239	+ u32 num_reg_entries = 0;
2929	2240
2930		− /* Calculate header size */
	2241	+ /* Write empty header for attention registers */
2931	2242	offset += qed_grc_dump_regs_hdr(dump_buf,
2932		− false, 0, SPLIT_TYPE_NONE,
2933		− 0, NULL, NULL);
	2243	+ false,
	2244	+ 0, SPLIT_TYPE_NONE, 0, "ATTN_REGS");
2934	2245
2935	2246	/* Write parity registers */
2936		− for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
	2247	+ for (block_id = 0; block_id < NUM_PHYS_BLOCKS; block_id++) {
2937	2248	if (dev_data->block_in_reset[block_id] && dump)
2938	2249	continue;
2939	2250
2940		− attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id,
	2251	+ attn_reg_arr = qed_get_block_attn_regs(p_hwfn,
	2252	+ (enum block_id)block_id,
2941	2253	ATTN_TYPE_PARITY,
2942	2254	&num_attn_regs);
2943	2255
@@ -2980,16 +2292,29 @@ static u32 qed_grc_dump_modified_regs(struct qed_hwfn *p_hwfn, · 36 unmodified lines
2980	2292	}
2981	2293	}
2982	2294
	2295	+ /* Overwrite header for attention registers */
	2296	+ if (dump)
	2297	+ qed_grc_dump_regs_hdr(dump_buf,
	2298	+ true,
	2299	+ num_reg_entries,
	2300	+ SPLIT_TYPE_NONE, 0, "ATTN_REGS");
	2301	+
	2302	+ /* Write empty header for stall registers */
	2303	+ stall_regs_offset = offset;
	2304	+ offset += qed_grc_dump_regs_hdr(dump_buf,
	2305	+ false, 0, SPLIT_TYPE_NONE, 0, "REGS");
	2306	+
2983	2307	/* Write Storm stall status registers */
2984		− for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
	2308	+ for (storm_id = 0, num_reg_entries = 0; storm_id < MAX_DBG_STORMS;
	2309	+ storm_id++) {
2985	2310	struct storm_defs *storm = &s_storm_defs[storm_id];
2986	2311	u32 addr;
2987	2312
2988		− if (dev_data->block_in_reset[storm->block_id] && dump)
	2313	+ if (dev_data->block_in_reset[storm->sem_block_id] && dump)
2989	2314	continue;
2990	2315
2991	2316	addr =
2992		− BYTES_TO_DWORDS(s_storm_defs[storm_id].sem_fast_mem_addr +
	2317	+ BYTES_TO_DWORDS(storm->sem_fast_mem_addr +
2993	2318	SEM_FAST_REG_STALLED);
2994	2319	offset += qed_grc_dump_reg_entry(p_hwfn,
2995	2320	p_ptt,
@@ -3001,12 +2326,12 @@ static u32 qed_grc_dump_modified_regs(struct qed_hwfn *p_hwfn, · 5 unmodified lines
3001	2326	num_reg_entries++;
3002	2327	}
3003	2328
3004		− /* Write header */
	2329	+ /* Overwrite header for stall registers */
3005	2330	if (dump)
3006		− qed_grc_dump_regs_hdr(dump_buf,
	2331	+ qed_grc_dump_regs_hdr(dump_buf + stall_regs_offset,
3007	2332	true,
3008		− num_reg_entries, SPLIT_TYPE_NONE,
3009		− 0, NULL, NULL);
	2333	+ num_reg_entries,
	2334	+ SPLIT_TYPE_NONE, 0, "REGS");
3010	2335
3011	2336	return offset;
3012	2337	}
@@ -3019,8 +2344,7 @@ static u32 qed_grc_dump_special_regs(struct qed_hwfn *p_hwfn, · 6 unmodified lines
3019	2344	u32 offset = 0, addr;
3020	2345
3021	2346	offset += qed_grc_dump_regs_hdr(dump_buf,
3022		− dump, 2, SPLIT_TYPE_NONE, 0,
3023		− NULL, NULL);
	2347	+ dump, 2, SPLIT_TYPE_NONE, 0, "REGS");
3024	2348
3025	2349	/* Dump R/TDIF_REG_DEBUG_ERROR_INFO_SIZE (every 8'th register should be
3026	2350	* skipped).
@@ -3068,8 +2392,7 @@ static u32 qed_grc_dump_mem_hdr(struct qed_hwfn *p_hwfn, · 41 unmodified lines
3068	2392	u32 len,
3069	2393	u32 bit_width,
3070	2394	bool packed,
3071		− const char *mem_group,
3072		− bool is_storm, char storm_letter)
	2395	+ const char *mem_group, char storm_letter)
3073	2396	{
3074	2397	u8 num_params = 3;
3075	2398	u32 offset = 0;
@@ -3090,7 +2413,7 @@ static u32 qed_grc_dump_mem_hdr(struct qed_hwfn *p_hwfn, · 14 unmodified lines
3090	2413
3091	2414	if (name) {
3092	2415	/* Dump name */
3093		− if (is_storm) {
	2416	+ if (storm_letter) {
3094	2417	strcpy(buf, "?STORM_");
3095	2418	buf[0] = storm_letter;
3096	2419	strcpy(buf + strlen(buf), name);
@@ -3122,7 +2445,7 @@ static u32 qed_grc_dump_mem_hdr(struct qed_hwfn *p_hwfn, · 25 unmodified lines
3122	2445	dump, "packed", 1);
3123	2446
3124	2447	/* Dump reg type */
3125		− if (is_storm) {
	2448	+ if (storm_letter) {
3126	2449	strcpy(buf, "?STORM_");
3127	2450	buf[0] = storm_letter;
3128	2451	strcpy(buf + strlen(buf), mem_group);
@@ -3149,8 +2472,7 @@ static u32 qed_grc_dump_mem(struct qed_hwfn *p_hwfn, · 20 unmodified lines
3149	2472	bool wide_bus,
3150	2473	u32 bit_width,
3151	2474	bool packed,
3152		− const char *mem_group,
3153		− bool is_storm, char storm_letter)
	2475	+ const char *mem_group, char storm_letter)
3154	2476	{
3155	2477	u32 offset = 0;
3156	2478
@@ -3161,8 +2483,7 @@ static u32 qed_grc_dump_mem(struct qed_hwfn *p_hwfn, · 4 unmodified lines
3161	2483	addr,
3162	2484	len,
3163	2485	bit_width,
3164		− packed,
3165		− mem_group, is_storm, storm_letter);
	2486	+ packed, mem_group, storm_letter);
3166	2487	offset += qed_grc_dump_addr_range(p_hwfn,
3167	2488	p_ptt,
3168	2489	dump_buf + offset,
@@ -3175,20 +2496,21 @@ static u32 qed_grc_dump_mem(struct qed_hwfn *p_hwfn, · 6 unmodified lines
3175	2496	/* Dumps GRC memories entries. Returns the dumped size in dwords. */
3176	2497	static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn,
3177	2498	struct qed_ptt *p_ptt,
3178		− struct dbg_array input_mems_arr,
	2499	+ struct virt_mem_desc input_mems_arr,
3179	2500	u32 *dump_buf, bool dump)
3180	2501	{
3181	2502	u32 i, offset = 0, input_offset = 0;
3182	2503	bool mode_match = true;
3183	2504
3184		− while (input_offset < input_mems_arr.size_in_dwords) {
	2505	+ while (input_offset < BYTES_TO_DWORDS(input_mems_arr.size)) {
3185	2506	const struct dbg_dump_cond_hdr *cond_hdr;
3186	2507	u16 modes_buf_offset;
3187	2508	u32 num_entries;
3188	2509	bool eval_mode;
3189	2510
3190		− cond_hdr = (const struct dbg_dump_cond_hdr *)
3191		− &input_mems_arr.ptr[input_offset++];
	2511	+ cond_hdr =
	2512	+ (const struct dbg_dump_cond_hdr *)input_mems_arr.ptr +
	2513	+ input_offset++;
3192	2514	num_entries = cond_hdr->data_size / MEM_DUMP_ENTRY_SIZE_DWORDS;
3193	2515
3194	2516	/* Check required mode */
@@ -3210,24 +2532,25 @@ static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn, · 15 unmodified lines
3210	2532	for (i = 0; i < num_entries;
3211	2533	i++, input_offset += MEM_DUMP_ENTRY_SIZE_DWORDS) {
3212	2534	const struct dbg_dump_mem *mem =
3213		− (const struct dbg_dump_mem *)
3214		− &input_mems_arr.ptr[input_offset];
3215		− u8 mem_group_id = GET_FIELD(mem->dword0,
3216		− DBG_DUMP_MEM_MEM_GROUP_ID);
3217		− bool is_storm = false, mem_wide_bus;
3218		− enum dbg_grc_params grc_param;
3219		− char storm_letter = 'a';
3220		− enum block_id block_id;
	2535	+ (const struct dbg_dump_mem )((u32 )
	2536	+ input_mems_arr.ptr
	2537	+ + input_offset);
	2538	+ const struct dbg_block *block;
	2539	+ char storm_letter = 0;
3221	2540	u32 mem_addr, mem_len;
	2541	+ bool mem_wide_bus;
	2542	+ u8 mem_group_id;
3222	2543
	2544	+ mem_group_id = GET_FIELD(mem->dword0,
	2545	+ DBG_DUMP_MEM_MEM_GROUP_ID);
3223	2546	if (mem_group_id >= MEM_GROUPS_NUM) {
3224	2547	DP_NOTICE(p_hwfn, "Invalid mem_group_id\n");
3225	2548	return 0;
3226	2549	}
3227	2550
3228		− block_id = (enum block_id)cond_hdr->block_id;
3229	2551	if (!qed_grc_is_mem_included(p_hwfn,
3230		− block_id,
	2552	+ (enum block_id)
	2553	+ cond_hdr->block_id,
3231	2554	mem_group_id))
3232	2555	continue;
3233	2556
@@ -3236,42 +2559,14 @@ static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn, · 2 unmodified lines
3236	2559	mem_wide_bus = GET_FIELD(mem->dword1,
3237	2560	DBG_DUMP_MEM_WIDE_BUS);
3238	2561
3239		− /* Update memory length for CCFC/TCFC memories
3240		− * according to number of LCIDs/LTIDs.
3241		− */
3242		− if (mem_group_id == MEM_GROUP_CONN_CFC_MEM) {
3243		− if (mem_len % MAX_LCIDS) {
3244		− DP_NOTICE(p_hwfn,
3245		− "Invalid CCFC connection memory size\n");
3246		− return 0;
3247		− }
3248		−
3249		− grc_param = DBG_GRC_PARAM_NUM_LCIDS;
3250		− mem_len = qed_grc_get_param(p_hwfn, grc_param) *
3251		− (mem_len / MAX_LCIDS);
3252		− } else if (mem_group_id == MEM_GROUP_TASK_CFC_MEM) {
3253		− if (mem_len % MAX_LTIDS) {
3254		− DP_NOTICE(p_hwfn,
3255		− "Invalid TCFC task memory size\n");
3256		− return 0;
3257		− }
3258		−
3259		− grc_param = DBG_GRC_PARAM_NUM_LTIDS;
3260		− mem_len = qed_grc_get_param(p_hwfn, grc_param) *
3261		− (mem_len / MAX_LTIDS);
3262		− }
	2562	+ block = get_dbg_block(p_hwfn,
	2563	+ cond_hdr->block_id);
3263	2564
3264		− /* If memory is associated with Storm, update Storm
3265		− * details.
	2565	+ /* If memory is associated with Storm,
	2566	+ * update storm details
3266	2567	*/
3267		− if (s_block_defs
3268		− [cond_hdr->block_id]->associated_to_storm) {
3269		− is_storm = true;
3270		− storm_letter =
3271		− s_storm_defs[s_block_defs
3272		− [cond_hdr->block_id]->
3273		− storm_id].letter;
3274		− }
	2568	+ if (block->associated_storm_letter)
	2569	+ storm_letter = block->associated_storm_letter;
3275	2570
3276	2571	/* Dump memory */
3277	2572	offset += qed_grc_dump_mem(p_hwfn,
@@ -3285,7 +2580,6 @@ static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn, · 7 unmodified lines
3285	2580	0,
3286	2581	false,
3287	2582	s_mem_group_names[mem_group_id],
3288		− is_storm,
3289	2583	storm_letter);
3290	2584	}
3291	2585	}
@@ -3300,26 +2594,25 @@ static u32 qed_grc_dump_memories(struct qed_hwfn *p_hwfn, · 8 unmodified lines
3300	2594	struct qed_ptt *p_ptt,
3301	2595	u32 *dump_buf, bool dump)
3302	2596	{
	2597	+ struct virt_mem_desc *dbg_buf =
	2598	+ &p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_MEM];
3303	2599	u32 offset = 0, input_offset = 0;
3304	2600
3305		− while (input_offset <
3306		− s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].size_in_dwords) {
	2601	+ while (input_offset < BYTES_TO_DWORDS(dbg_buf->size)) {
3307	2602	const struct dbg_dump_split_hdr *split_hdr;
3308		− struct dbg_array curr_input_mems_arr;
	2603	+ struct virt_mem_desc curr_input_mems_arr;
3309	2604	enum init_split_types split_type;
3310	2605	u32 split_data_size;
3311	2606
3312		− split_hdr = (const struct dbg_dump_split_hdr *)
3313		− &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset++];
3314		− split_type =
3315		− GET_FIELD(split_hdr->hdr,
3316		− DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
3317		− split_data_size =
3318		− GET_FIELD(split_hdr->hdr,
3319		− DBG_DUMP_SPLIT_HDR_DATA_SIZE);
3320		− curr_input_mems_arr.ptr =
3321		− &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset];
3322		− curr_input_mems_arr.size_in_dwords = split_data_size;
	2607	+ split_hdr =
	2608	+ (const struct dbg_dump_split_hdr *)dbg_buf->ptr +
	2609	+ input_offset++;
	2610	+ split_type = GET_FIELD(split_hdr->hdr,
	2611	+ DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
	2612	+ split_data_size = GET_FIELD(split_hdr->hdr,
	2613	+ DBG_DUMP_SPLIT_HDR_DATA_SIZE);
	2614	+ curr_input_mems_arr.ptr = (u32 *)dbg_buf->ptr + input_offset;
	2615	+ curr_input_mems_arr.size = DWORDS_TO_BYTES(split_data_size);
3323	2616
3324	2617	if (split_type == SPLIT_TYPE_NONE)
3325	2618	offset += qed_grc_dump_mem_entries(p_hwfn,
@@ -3347,17 +2640,19 @@ static u32 qed_grc_dump_ctx_data(struct qed_hwfn *p_hwfn, · 21 unmodified lines
3347	2640	bool dump,
3348	2641	const char *name,
3349	2642	u32 num_lids,
3350		− u32 lid_size,
3351		− u32 rd_reg_addr,
3352		− u8 storm_id)
	2643	+ enum cm_ctx_types ctx_type, u8 storm_id)
3353	2644	{
	2645	+ struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
3354	2646	struct storm_defs *storm = &s_storm_defs[storm_id];
3355		− u32 i, lid, total_size, offset = 0;
	2647	+ u32 i, lid, lid_size, total_size;
	2648	+ u32 rd_reg_addr, offset = 0;
	2649	+
	2650	+ /* Convert quad-regs to dwords */
	2651	+ lid_size = storm->cm_ctx_lid_sizes[dev_data->chip_id][ctx_type] * 4;
3356	2652
3357	2653	if (!lid_size)
3358	2654	return 0;
3359	2655
3360		− lid_size *= BYTES_IN_DWORD;
3361	2656	total_size = num_lids * lid_size;
3362	2657
3363	2658	offset += qed_grc_dump_mem_hdr(p_hwfn,
@@ -3367,18 +2662,26 @@ static u32 qed_grc_dump_ctx_data(struct qed_hwfn *p_hwfn, · 3 unmodified lines
3367	2662	0,
3368	2663	total_size,
3369	2664	lid_size * 32,
3370		− false, name, true, storm->letter);
	2665	+ false, name, storm->letter);
3371	2666
3372	2667	if (!dump)
3373	2668	return offset + total_size;
3374	2669
	2670	+ rd_reg_addr = BYTES_TO_DWORDS(storm->cm_ctx_rd_addr[ctx_type]);
	2671	+
3375	2672	/* Dump context data */
3376	2673	for (lid = 0; lid < num_lids; lid++) {
3377		− for (i = 0; i < lid_size; i++, offset++) {
	2674	+ for (i = 0; i < lid_size; i++) {
3378	2675	qed_wr(p_hwfn,
3379	2676	p_ptt, storm->cm_ctx_wr_addr, (i << 9) \| lid);
3380		− *(dump_buf + offset) = qed_rd(p_hwfn,
3381		− p_ptt, rd_reg_addr);
	2677	+ offset += qed_grc_dump_addr_range(p_hwfn,
	2678	+ p_ptt,
	2679	+ dump_buf + offset,
	2680	+ dump,
	2681	+ rd_reg_addr,
	2682	+ 1,
	2683	+ false,
	2684	+ SPLIT_TYPE_NONE, 0);
3382	2685	}
3383	2686	}
3384	2687
@@ -3389,115 +2692,126 @@ static u32 qed_grc_dump_ctx_data(struct qed_hwfn *p_hwfn, · 4 unmodified lines
3389	2692	static u32 qed_grc_dump_ctx(struct qed_hwfn *p_hwfn,
3390	2693	struct qed_ptt p_ptt, u32 dump_buf, bool dump)
3391	2694	{
3392		− enum dbg_grc_params grc_param;
3393	2695	u32 offset = 0;
3394	2696	u8 storm_id;
3395	2697
3396	2698	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
3397		− struct storm_defs *storm = &s_storm_defs[storm_id];
3398		−
3399	2699	if (!qed_grc_is_storm_included(p_hwfn,
3400	2700	(enum dbg_storms)storm_id))
3401	2701	continue;
3402	2702
3403	2703	/* Dump Conn AG context size */
3404		− grc_param = DBG_GRC_PARAM_NUM_LCIDS;
3405		− offset +=
3406		− qed_grc_dump_ctx_data(p_hwfn,
3407		− p_ptt,
3408		− dump_buf + offset,
3409		− dump,
3410		− "CONN_AG_CTX",
3411		− qed_grc_get_param(p_hwfn,
3412		− grc_param),
3413		− storm->cm_conn_ag_ctx_lid_size,
3414		− storm->cm_conn_ag_ctx_rd_addr,
3415		− storm_id);
	2704	+ offset += qed_grc_dump_ctx_data(p_hwfn,
	2705	+ p_ptt,
	2706	+ dump_buf + offset,
	2707	+ dump,
	2708	+ "CONN_AG_CTX",
	2709	+ NUM_OF_LCIDS,
	2710	+ CM_CTX_CONN_AG, storm_id);
3416	2711
3417	2712	/* Dump Conn ST context size */
3418		− grc_param = DBG_GRC_PARAM_NUM_LCIDS;
3419		− offset +=
3420		− qed_grc_dump_ctx_data(p_hwfn,
3421		− p_ptt,
3422		− dump_buf + offset,
3423		− dump,
3424		− "CONN_ST_CTX",
3425		− qed_grc_get_param(p_hwfn,
3426		− grc_param),
3427		− storm->cm_conn_st_ctx_lid_size,
3428		− storm->cm_conn_st_ctx_rd_addr,
3429		− storm_id);
	2713	+ offset += qed_grc_dump_ctx_data(p_hwfn,
	2714	+ p_ptt,
	2715	+ dump_buf + offset,
	2716	+ dump,
	2717	+ "CONN_ST_CTX",
	2718	+ NUM_OF_LCIDS,
	2719	+ CM_CTX_CONN_ST, storm_id);
3430	2720
3431	2721	/* Dump Task AG context size */
3432		− grc_param = DBG_GRC_PARAM_NUM_LTIDS;
3433		− offset +=
3434		− qed_grc_dump_ctx_data(p_hwfn,
3435		− p_ptt,
3436		− dump_buf + offset,
3437		− dump,
3438		− "TASK_AG_CTX",
3439		− qed_grc_get_param(p_hwfn,
3440		− grc_param),
3441		− storm->cm_task_ag_ctx_lid_size,
3442		− storm->cm_task_ag_ctx_rd_addr,
3443		− storm_id);
	2722	+ offset += qed_grc_dump_ctx_data(p_hwfn,
	2723	+ p_ptt,
	2724	+ dump_buf + offset,
	2725	+ dump,
	2726	+ "TASK_AG_CTX",
	2727	+ NUM_OF_LTIDS,
	2728	+ CM_CTX_TASK_AG, storm_id);
3444	2729
3445	2730	/* Dump Task ST context size */
3446		− grc_param = DBG_GRC_PARAM_NUM_LTIDS;
3447		− offset +=
3448		− qed_grc_dump_ctx_data(p_hwfn,
3449		− p_ptt,
3450		− dump_buf + offset,
3451		− dump,
3452		− "TASK_ST_CTX",
3453		− qed_grc_get_param(p_hwfn,
3454		− grc_param),
3455		− storm->cm_task_st_ctx_lid_size,
3456		− storm->cm_task_st_ctx_rd_addr,
3457		− storm_id);
	2731	+ offset += qed_grc_dump_ctx_data(p_hwfn,
	2732	+ p_ptt,
	2733	+ dump_buf + offset,
	2734	+ dump,
	2735	+ "TASK_ST_CTX",
	2736	+ NUM_OF_LTIDS,
	2737	+ CM_CTX_TASK_ST, storm_id);
3458	2738	}
3459	2739
3460	2740	return offset;
3461	2741	}
3462	2742
3463		−/* Dumps GRC IORs data. Returns the dumped size in dwords. */
3464		−static u32 qed_grc_dump_iors(struct qed_hwfn *p_hwfn,
3465		− struct qed_ptt p_ptt, u32 dump_buf, bool dump)
3466		−{
3467		− char buf[10] = "IOR_SET_?";
3468		− u32 addr, offset = 0;
3469		− u8 storm_id, set_id;
	2743	+#define VFC_STATUS_RESP_READY_BIT 0
	2744	+#define VFC_STATUS_BUSY_BIT 1
	2745	+#define VFC_STATUS_SENDING_CMD_BIT 2
3470	2746
3471		− for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
3472		− struct storm_defs *storm = &s_storm_defs[storm_id];
	2747	+#define VFC_POLLING_DELAY_MS 1
	2748	+#define VFC_POLLING_COUNT 20
3473	2749
3474		− if (!qed_grc_is_storm_included(p_hwfn,
3475		− (enum dbg_storms)storm_id))
3476		− continue;
	2750	+/* Reads data from VFC. Returns the number of dwords read (0 on error).
	2751	+ * Sizes are specified in dwords.
	2752	+ */
	2753	+static u32 qed_grc_dump_read_from_vfc(struct qed_hwfn *p_hwfn,
	2754	+ struct qed_ptt *p_ptt,
	2755	+ struct storm_defs *storm,
	2756	+ u32 *cmd_data,
	2757	+ u32 cmd_size,
	2758	+ u32 *addr_data,
	2759	+ u32 addr_size,
	2760	+ u32 resp_size, u32 *dump_buf)
	2761	+{
	2762	+ struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	2763	+ u32 vfc_status, polling_ms, polling_count = 0, i;
	2764	+ u32 reg_addr, sem_base;
	2765	+ bool is_ready = false;
	2766	+
	2767	+ sem_base = storm->sem_fast_mem_addr;
	2768	+ polling_ms = VFC_POLLING_DELAY_MS *
	2769	+ s_hw_type_defs[dev_data->hw_type].delay_factor;
	2770	+
	2771	+ /* Write VFC command */
	2772	+ ARR_REG_WR(p_hwfn,
	2773	+ p_ptt,
	2774	+ sem_base + SEM_FAST_REG_VFC_DATA_WR,
	2775	+ cmd_data, cmd_size);
	2776	+
	2777	+ /* Write VFC address */
	2778	+ ARR_REG_WR(p_hwfn,
	2779	+ p_ptt,
	2780	+ sem_base + SEM_FAST_REG_VFC_ADDR,
	2781	+ addr_data, addr_size);
	2782	+
	2783	+ /* Read response */
	2784	+ for (i = 0; i < resp_size; i++) {
	2785	+ /* Poll until ready */
	2786	+ do {
	2787	+ reg_addr = sem_base + SEM_FAST_REG_VFC_STATUS;
	2788	+ qed_grc_dump_addr_range(p_hwfn,
	2789	+ p_ptt,
	2790	+ &vfc_status,
	2791	+ true,
	2792	+ BYTES_TO_DWORDS(reg_addr),
	2793	+ 1,
	2794	+ false, SPLIT_TYPE_NONE, 0);
	2795	+ is_ready = vfc_status & BIT(VFC_STATUS_RESP_READY_BIT);
	2796	+
	2797	+ if (!is_ready) {
	2798	+ if (polling_count++ == VFC_POLLING_COUNT)
	2799	+ return 0;
3477	2800
3478		− for (set_id = 0; set_id < NUM_IOR_SETS; set_id++) {
3479		− addr = BYTES_TO_DWORDS(storm->sem_fast_mem_addr +
3480		− SEM_FAST_REG_STORM_REG_FILE) +
3481		− IOR_SET_OFFSET(set_id);
3482		− if (strlen(buf) > 0)
3483		− buf[strlen(buf) - 1] = '0' + set_id;
3484		− offset += qed_grc_dump_mem(p_hwfn,
3485		− p_ptt,
3486		− dump_buf + offset,
3487		− dump,
3488		− buf,
3489		− addr,
3490		− IORS_PER_SET,
3491		− false,
3492		− 32,
3493		− false,
3494		− "ior",
3495		− true,
3496		− storm->letter);
3497		− }
	2801	+ msleep(polling_ms);
	2802	+ }
	2803	+ } while (!is_ready);
	2804	+
	2805	+ reg_addr = sem_base + SEM_FAST_REG_VFC_DATA_RD;
	2806	+ qed_grc_dump_addr_range(p_hwfn,
	2807	+ p_ptt,
	2808	+ dump_buf + i,
	2809	+ true,
	2810	+ BYTES_TO_DWORDS(reg_addr),
	2811	+ 1, false, SPLIT_TYPE_NONE, 0);
3498	2812	}
3499	2813
3500		− return offset;
	2814	+ return resp_size;
3501	2815	}
3502	2816
3503	2817	/* Dump VFC CAM. Returns the dumped size in dwords. */
@@ -3509,7 +2823,7 @@ static u32 qed_grc_dump_vfc_cam(struct qed_hwfn *p_hwfn, · 5 unmodified lines
3509	2823	struct storm_defs *storm = &s_storm_defs[storm_id];
3510	2824	u32 cam_addr[VFC_CAM_ADDR_DWORDS] = { 0 };
3511	2825	u32 cam_cmd[VFC_CAM_CMD_DWORDS] = { 0 };
3512		− u32 row, i, offset = 0;
	2826	+ u32 row, offset = 0;
3513	2827
3514	2828	offset += qed_grc_dump_mem_hdr(p_hwfn,
3515	2829	dump_buf + offset,
@@ -3518,7 +2832,7 @@ static u32 qed_grc_dump_vfc_cam(struct qed_hwfn *p_hwfn, · 2 unmodified lines
3518	2832	0,
3519	2833	total_size,
3520	2834	256,
3521		− false, "vfc_cam", true, storm->letter);
	2835	+ false, "vfc_cam", storm->letter);
3522	2836
3523	2837	if (!dump)
3524	2838	return offset + total_size;
@@ -3526,26 +2840,18 @@ static u32 qed_grc_dump_vfc_cam(struct qed_hwfn *p_hwfn, · 1 unmodified line
3526	2840	/* Prepare CAM address */
3527	2841	SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD);
3528	2842
3529		− for (row = 0; row < VFC_CAM_NUM_ROWS;
3530		− row++, offset += VFC_CAM_RESP_DWORDS) {
3531		− /* Write VFC CAM command */
	2843	+ /* Read VFC CAM data */
	2844	+ for (row = 0; row < VFC_CAM_NUM_ROWS; row++) {
3532	2845	SET_VAR_FIELD(cam_cmd, VFC_CAM_CMD, ROW, row);
3533		− ARR_REG_WR(p_hwfn,
3534		− p_ptt,
3535		− storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR,
3536		− cam_cmd, VFC_CAM_CMD_DWORDS);
3537		−
3538		− /* Write VFC CAM address */
3539		− ARR_REG_WR(p_hwfn,
3540		− p_ptt,
3541		− storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR,
3542		− cam_addr, VFC_CAM_ADDR_DWORDS);
3543		−
3544		− /* Read VFC CAM read response */
3545		− ARR_REG_RD(p_hwfn,
3546		− p_ptt,
3547		− storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD,
3548		− dump_buf + offset, VFC_CAM_RESP_DWORDS);
	2846	+ offset += qed_grc_dump_read_from_vfc(p_hwfn,
	2847	+ p_ptt,
	2848	+ storm,
	2849	+ cam_cmd,
	2850	+ VFC_CAM_CMD_DWORDS,
	2851	+ cam_addr,
	2852	+ VFC_CAM_ADDR_DWORDS,
	2853	+ VFC_CAM_RESP_DWORDS,
	2854	+ dump_buf + offset);
3549	2855	}
3550	2856
3551	2857	return offset;
@@ -3562,7 +2868,7 @@ static u32 qed_grc_dump_vfc_ram(struct qed_hwfn *p_hwfn, · 10 unmodified lines
3562	2868	struct storm_defs *storm = &s_storm_defs[storm_id];
3563	2869	u32 ram_addr[VFC_RAM_ADDR_DWORDS] = { 0 };
3564	2870	u32 ram_cmd[VFC_RAM_CMD_DWORDS] = { 0 };
3565		− u32 row, i, offset = 0;
	2871	+ u32 row, offset = 0;
3566	2872
3567	2873	offset += qed_grc_dump_mem_hdr(p_hwfn,
3568	2874	dump_buf + offset,
@@ -3573,35 +2879,27 @@ static u32 qed_grc_dump_vfc_ram(struct qed_hwfn *p_hwfn, · 4 unmodified lines
3573	2879	256,
3574	2880	false,
3575	2881	ram_defs->type_name,
3576		− true, storm->letter);
3577		−
3578		− /* Prepare RAM address */
3579		− SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD);
	2882	+ storm->letter);
3580	2883
3581	2884	if (!dump)
3582	2885	return offset + total_size;
3583	2886
	2887	+ /* Prepare RAM address */
	2888	+ SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD);
	2889	+
	2890	+ /* Read VFC RAM data */
3584	2891	for (row = ram_defs->base_row;
3585		− row < ram_defs->base_row + ram_defs->num_rows;
3586		− row++, offset += VFC_RAM_RESP_DWORDS) {
3587		− /* Write VFC RAM command */
3588		− ARR_REG_WR(p_hwfn,
3589		− p_ptt,
3590		− storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR,
3591		− ram_cmd, VFC_RAM_CMD_DWORDS);
3592		−
3593		− /* Write VFC RAM address */
	2892	+ row < ram_defs->base_row + ram_defs->num_rows; row++) {
3594	2893	SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, ROW, row);
3595		− ARR_REG_WR(p_hwfn,
3596		− p_ptt,
3597		− storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR,
3598		− ram_addr, VFC_RAM_ADDR_DWORDS);
3599		−
3600		− /* Read VFC RAM read response */
3601		− ARR_REG_RD(p_hwfn,
3602		− p_ptt,
3603		− storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD,
3604		− dump_buf + offset, VFC_RAM_RESP_DWORDS);
	2894	+ offset += qed_grc_dump_read_from_vfc(p_hwfn,
	2895	+ p_ptt,
	2896	+ storm,
	2897	+ ram_cmd,
	2898	+ VFC_RAM_CMD_DWORDS,
	2899	+ ram_addr,
	2900	+ VFC_RAM_ADDR_DWORDS,
	2901	+ VFC_RAM_RESP_DWORDS,
	2902	+ dump_buf + offset);
3605	2903	}
3606	2904
3607	2905	return offset;
@@ -3611,16 +2909,13 @@ static u32 qed_grc_dump_vfc_ram(struct qed_hwfn *p_hwfn, · 3 unmodified lines
3611	2909	static u32 qed_grc_dump_vfc(struct qed_hwfn *p_hwfn,
3612	2910	struct qed_ptt p_ptt, u32 dump_buf, bool dump)
3613	2911	{
3614		− struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
3615	2912	u8 storm_id, i;
3616	2913	u32 offset = 0;
3617	2914
3618	2915	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
3619	2916	if (!qed_grc_is_storm_included(p_hwfn,
3620	2917	(enum dbg_storms)storm_id) \|\|
3621		− !s_storm_defs[storm_id].has_vfc \|\|
3622		− (storm_id == DBG_PSTORM_ID && dev_data->platform_id !=
3623		− PLATFORM_ASIC))
	2918	+ !s_storm_defs[storm_id].has_vfc)
3624	2919	continue;
3625	2920
3626	2921	/* Read CAM */
@@ -3670,7 +2965,7 @@ static u32 qed_grc_dump_rss(struct qed_hwfn *p_hwfn, · 43 unmodified lines
3670	2965	total_dwords,
3671	2966	rss_defs->entry_width,
3672	2967	packed,
3673		− rss_defs->type_name, false, 0);
	2968	+ rss_defs->type_name, 0);
3674	2969
3675	2970	/* Dump RSS data */
3676	2971	if (!dump) {
@@ -3730,7 +3025,7 @@ static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn, · 53 unmodified lines
3730	3025	0,
3731	3026	ram_size,
3732	3027	block_size * 8,
3733		− false, type_name, false, 0);
	3028	+ false, type_name, 0);
3734	3029
3735	3030	/* Read and dump Big RAM data */
3736	3031	if (!dump)
@@ -3756,6 +3051,7 @@ static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn, · 19 unmodified lines
3756	3051	return offset;
3757	3052	}
3758	3053
	3054	+/* Dumps MCP scratchpad. Returns the dumped size in dwords. */
3759	3055	static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn,
3760	3056	struct qed_ptt p_ptt, u32 dump_buf, bool dump)
3761	3057	{
@@ -3777,8 +3073,8 @@ static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn, · 15 unmodified lines
3777	3073	dump,
3778	3074	NULL,
3779	3075	BYTES_TO_DWORDS(MCP_REG_SCRATCH),
3780		− MCP_REG_SCRATCH_SIZE_BB_K2,
3781		− false, 0, false, "MCP", false, 0);
	3076	+ MCP_REG_SCRATCH_SIZE,
	3077	+ false, 0, false, "MCP", 0);
3782	3078
3783	3079	/* Dump MCP cpu_reg_file */
3784	3080	offset += qed_grc_dump_mem(p_hwfn,
@@ -3788,19 +3084,19 @@ static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn, · 3 unmodified lines
3788	3084	NULL,
3789	3085	BYTES_TO_DWORDS(MCP_REG_CPU_REG_FILE),
3790	3086	MCP_REG_CPU_REG_FILE_SIZE,
3791		− false, 0, false, "MCP", false, 0);
	3087	+ false, 0, false, "MCP", 0);
3792	3088
3793	3089	/* Dump MCP registers */
3794	3090	block_enable[BLOCK_MCP] = true;
3795	3091	offset += qed_grc_dump_registers(p_hwfn,
3796	3092	p_ptt,
3797	3093	dump_buf + offset,
3798		− dump, block_enable, "block", "MCP");
	3094	+ dump, block_enable, "MCP");
3799	3095
3800	3096	/* Dump required non-MCP registers */
3801	3097	offset += qed_grc_dump_regs_hdr(dump_buf + offset,
3802	3098	dump, 1, SPLIT_TYPE_NONE, 0,
3803		− "block", "MCP");
	3099	+ "MCP");
3804	3100	addr = BYTES_TO_DWORDS(MISC_REG_SHARED_MEM_ADDR);
3805	3101	offset += qed_grc_dump_reg_entry(p_hwfn,
3806	3102	p_ptt,
@@ -3817,7 +3113,9 @@ static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn, · 10 unmodified lines
3817	3113	return offset;
3818	3114	}
3819	3115
3820		−/* Dumps the tbus indirect memory for all PHYs. */
	3116	+/* Dumps the tbus indirect memory for all PHYs.
	3117	+ * Returns the dumped size in dwords.
	3118	+ */
3821	3119	static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn,
3822	3120	struct qed_ptt p_ptt, u32 dump_buf, bool dump)
3823	3121	{
@@ -3851,7 +3149,7 @@ static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn, · 27 unmodified lines
3851	3149	mem_name,
3852	3150	0,
3853	3151	PHY_DUMP_SIZE_DWORDS,
3854		− 16, true, mem_name, false, 0);
	3152	+ 16, true, mem_name, 0);
3855	3153
3856	3154	if (!dump) {
3857	3155	offset += PHY_DUMP_SIZE_DWORDS;
@@ -3882,21 +3180,58 @@ static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn, · 24 unmodified lines
3882	3180	return offset;
3883	3181	}
3884	3182
3885		−static void qed_config_dbg_line(struct qed_hwfn *p_hwfn,
3886		− struct qed_ptt *p_ptt,
3887		− enum block_id block_id,
3888		− u8 line_id,
3889		− u8 enable_mask,
3890		− u8 right_shift,
3891		− u8 force_valid_mask, u8 force_frame_mask)
	3183	+static enum dbg_status qed_find_nvram_image(struct qed_hwfn *p_hwfn,
	3184	+ struct qed_ptt *p_ptt,
	3185	+ u32 image_type,
	3186	+ u32 *nvram_offset_bytes,
	3187	+ u32 *nvram_size_bytes);
	3188	+
	3189	+static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn,
	3190	+ struct qed_ptt *p_ptt,
	3191	+ u32 nvram_offset_bytes,
	3192	+ u32 nvram_size_bytes, u32 *ret_buf);
	3193	+
	3194	+/* Dumps the MCP HW dump from NVRAM. Returns the dumped size in dwords. */
	3195	+static u32 qed_grc_dump_mcp_hw_dump(struct qed_hwfn *p_hwfn,
	3196	+ struct qed_ptt *p_ptt,
	3197	+ u32 *dump_buf, bool dump)
3892	3198	{
3893		− struct block_defs *block = s_block_defs[block_id];
	3199	+ u32 hw_dump_offset_bytes = 0, hw_dump_size_bytes = 0;
	3200	+ u32 hw_dump_size_dwords = 0, offset = 0;
	3201	+ enum dbg_status status;
	3202	+
	3203	+ /* Read HW dump image from NVRAM */
	3204	+ status = qed_find_nvram_image(p_hwfn,
	3205	+ p_ptt,
	3206	+ NVM_TYPE_HW_DUMP_OUT,
	3207	+ &hw_dump_offset_bytes,
	3208	+ &hw_dump_size_bytes);
	3209	+ if (status != DBG_STATUS_OK)
	3210	+ return 0;
	3211	+
	3212	+ hw_dump_size_dwords = BYTES_TO_DWORDS(hw_dump_size_bytes);
	3213	+
	3214	+ /* Dump HW dump image section */
	3215	+ offset += qed_dump_section_hdr(dump_buf + offset,
	3216	+ dump, "mcp_hw_dump", 1);
	3217	+ offset += qed_dump_num_param(dump_buf + offset,
	3218	+ dump, "size", hw_dump_size_dwords);
	3219	+
	3220	+ /* Read MCP HW dump image into dump buffer */
	3221	+ if (dump && hw_dump_size_dwords) {
	3222	+ status = qed_nvram_read(p_hwfn,
	3223	+ p_ptt,
	3224	+ hw_dump_offset_bytes,
	3225	+ hw_dump_size_bytes, dump_buf + offset);
	3226	+ if (status != DBG_STATUS_OK) {
	3227	+ DP_NOTICE(p_hwfn,
	3228	+ "Failed to read MCP HW Dump image from NVRAM\n");
	3229	+ return 0;
	3230	+ }
	3231	+ }
	3232	+ offset += hw_dump_size_dwords;
3894	3233
3895		− qed_wr(p_hwfn, p_ptt, block->dbg_select_addr, line_id);
3896		− qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, enable_mask);
3897		− qed_wr(p_hwfn, p_ptt, block->dbg_shift_addr, right_shift);
3898		− qed_wr(p_hwfn, p_ptt, block->dbg_force_valid_addr, force_valid_mask);
3899		− qed_wr(p_hwfn, p_ptt, block->dbg_force_frame_addr, force_frame_mask);
	3234	+ return offset;
3900	3235	}
3901	3236
3902	3237	/* Dumps Static Debug data. Returns the dumped size in dwords. */
@@ -3905,26 +3240,19 @@ static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn, · 2 unmodified lines
3905	3240	u32 *dump_buf, bool dump)
3906	3241	{
3907	3242	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
3908		− u32 block_id, line_id, offset = 0;
	3243	+ u32 block_id, line_id, offset = 0, addr, len;
3909	3244
3910	3245	/* Don't dump static debug if a debug bus recording is in progress */
3911	3246	if (dump && qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON))
3912	3247	return 0;
3913	3248
3914	3249	if (dump) {
3915		− /* Disable all blocks debug output */
3916		− for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
3917		− struct block_defs *block = s_block_defs[block_id];
3918		−
3919		− if (block->dbg_client_id[dev_data->chip_id] !=
3920		− MAX_DBG_BUS_CLIENTS)
3921		− qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr,
3922		− 0);
3923		− }
	3250	+ /* Disable debug bus in all blocks */
	3251	+ qed_bus_disable_blocks(p_hwfn, p_ptt);
3924	3252
3925	3253	qed_bus_reset_dbg_block(p_hwfn, p_ptt);
3926		− qed_bus_set_framing_mode(p_hwfn,
3927		− p_ptt, DBG_BUS_FRAME_MODE_8HW_0ST);
	3254	+ qed_wr(p_hwfn,
	3255	+ p_ptt, DBG_REG_FRAMING_MODE, DBG_BUS_FRAME_MODE_8HW);
3928	3256	qed_wr(p_hwfn,
3929	3257	p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_INT_BUF);
3930	3258	qed_wr(p_hwfn, p_ptt, DBG_REG_FULL_MODE, 1);
@@ -3933,28 +3261,48 @@ static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn, · 2 unmodified lines
3933	3261
3934	3262	/* Dump all static debug lines for each relevant block */
3935	3263	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
3936		− struct block_defs *block = s_block_defs[block_id];
3937		− struct dbg_bus_block *block_desc;
3938		− u32 block_dwords, addr, len;
3939		− u8 dbg_client_id;
	3264	+ const struct dbg_block_chip *block_per_chip;
	3265	+ const struct dbg_block *block;
	3266	+ bool is_removed, has_dbg_bus;
	3267	+ u16 modes_buf_offset;
	3268	+ u32 block_dwords;
	3269	+
	3270	+ block_per_chip =
	3271	+ qed_get_dbg_block_per_chip(p_hwfn, (enum block_id)block_id);
	3272	+ is_removed = GET_FIELD(block_per_chip->flags,
	3273	+ DBG_BLOCK_CHIP_IS_REMOVED);
	3274	+ has_dbg_bus = GET_FIELD(block_per_chip->flags,
	3275	+ DBG_BLOCK_CHIP_HAS_DBG_BUS);
	3276	+
	3277	+ /* read+clear for NWS parity is not working, skip NWS block */
	3278	+ if (block_id == BLOCK_NWS)
	3279	+ continue;
	3280	+
	3281	+ if (!is_removed && has_dbg_bus &&
	3282	+ GET_FIELD(block_per_chip->dbg_bus_mode.data,
	3283	+ DBG_MODE_HDR_EVAL_MODE) > 0) {
	3284	+ modes_buf_offset =
	3285	+ GET_FIELD(block_per_chip->dbg_bus_mode.data,
	3286	+ DBG_MODE_HDR_MODES_BUF_OFFSET);
	3287	+ if (!qed_is_mode_match(p_hwfn, &modes_buf_offset))
	3288	+ has_dbg_bus = false;
	3289	+ }
3940	3290
3941		− if (block->dbg_client_id[dev_data->chip_id] ==
3942		− MAX_DBG_BUS_CLIENTS)
	3291	+ if (is_removed \|\| !has_dbg_bus)
3943	3292	continue;
3944	3293
3945		− block_desc = get_dbg_bus_block_desc(p_hwfn,
3946		− (enum block_id)block_id);
3947		− block_dwords = NUM_DBG_LINES(block_desc) *
	3294	+ block_dwords = NUM_DBG_LINES(block_per_chip) *
3948	3295	STATIC_DEBUG_LINE_DWORDS;
3949	3296
3950	3297	/* Dump static section params */
	3298	+ block = get_dbg_block(p_hwfn, (enum block_id)block_id);
3951	3299	offset += qed_grc_dump_mem_hdr(p_hwfn,
3952	3300	dump_buf + offset,
3953	3301	dump,
3954	3302	block->name,
3955	3303	0,
3956	3304	block_dwords,
3957		− 32, false, "STATIC", false, 0);
	3305	+ 32, false, "STATIC", 0);
3958	3306
3959	3307	if (!dump) {
3960	3308	offset += block_dwords;
@@ -3970,20 +3318,19 @@ static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn, · 9 unmodified lines
3970	3318	}
3971	3319
3972	3320	/* Enable block's client */
3973		− dbg_client_id = block->dbg_client_id[dev_data->chip_id];
3974	3321	qed_bus_enable_clients(p_hwfn,
3975	3322	p_ptt,
3976		− BIT(dbg_client_id));
	3323	+ BIT(block_per_chip->dbg_client_id));
3977	3324
3978	3325	addr = BYTES_TO_DWORDS(DBG_REG_CALENDAR_OUT_DATA);
3979	3326	len = STATIC_DEBUG_LINE_DWORDS;
3980		− for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_desc);
	3327	+ for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_per_chip);
3981	3328	line_id++) {
3982	3329	/* Configure debug line ID */
3983		− qed_config_dbg_line(p_hwfn,
3984		− p_ptt,
3985		− (enum block_id)block_id,
3986		− (u8)line_id, 0xf, 0, 0, 0);
	3330	+ qed_bus_config_dbg_line(p_hwfn,
	3331	+ p_ptt,
	3332	+ (enum block_id)block_id,
	3333	+ (u8)line_id, 0xf, 0, 0, 0);
3987	3334
3988	3335	/* Read debug line info */
3989	3336	offset += qed_grc_dump_addr_range(p_hwfn,
@@ -3998,7 +3345,8 @@ static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn, · 8 unmodified lines
3998	3345
3999	3346	/* Disable block's client and debug output */
4000	3347	qed_bus_enable_clients(p_hwfn, p_ptt, 0);
4001		− qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0);
	3348	+ qed_bus_config_dbg_line(p_hwfn, p_ptt,
	3349	+ (enum block_id)block_id, 0, 0, 0, 0, 0);
4002	3350	}
4003	3351
4004	3352	if (dump) {
@@ -4018,8 +3366,8 @@ static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn, · 13 unmodified lines
4018	3366	bool dump, u32 *num_dumped_dwords)
4019	3367	{
4020	3368	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	3369	+ u32 dwords_read, offset = 0;
4021	3370	bool parities_masked = false;
4022		− u32 offset = 0;
4023	3371	u8 i;
4024	3372
4025	3373	*num_dumped_dwords = 0;
@@ -4038,13 +3386,11 @@ static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn, · 12 unmodified lines
4038	3386	offset += qed_dump_num_param(dump_buf + offset,
4039	3387	dump,
4040	3388	"num-lcids",
4041		− qed_grc_get_param(p_hwfn,
4042		− DBG_GRC_PARAM_NUM_LCIDS));
	3389	+ NUM_OF_LCIDS);
4043	3390	offset += qed_dump_num_param(dump_buf + offset,
4044	3391	dump,
4045	3392	"num-ltids",
4046		− qed_grc_get_param(p_hwfn,
4047		− DBG_GRC_PARAM_NUM_LTIDS));
	3393	+ NUM_OF_LTIDS);
4048	3394	offset += qed_dump_num_param(dump_buf + offset,
4049	3395	dump, "num-ports", dev_data->num_ports);
4050	3396
@@ -4056,7 +3402,7 @@ static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn, · 5 unmodified lines
4056	3402
4057	3403	/* Take all blocks out of reset (using reset registers) */
4058	3404	if (dump) {
4059		− qed_grc_unreset_blocks(p_hwfn, p_ptt);
	3405	+ qed_grc_unreset_blocks(p_hwfn, p_ptt, false);
4060	3406	qed_update_blocks_reset_state(p_hwfn, p_ptt);
4061	3407	}
4062	3408
@@ -4099,7 +3445,7 @@ static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn, · 36 unmodified lines
4099	3445	dump_buf +
4100	3446	offset,
4101	3447	dump,
4102		− block_enable, NULL, NULL);
	3448	+ block_enable, NULL);
4103	3449
4104	3450	/* Dump special registers */
4105	3451	offset += qed_grc_dump_special_regs(p_hwfn,
@@ -4133,23 +3479,29 @@ static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn, · 27 unmodified lines
4133	3479	dump_buf + offset,
4134	3480	dump, i);
4135	3481
4136		− /* Dump IORs */
4137		− if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR))
4138		− offset += qed_grc_dump_iors(p_hwfn,
4139		− p_ptt, dump_buf + offset, dump);
4140		−
4141	3482	/* Dump VFC */
4142		− if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC))
4143		− offset += qed_grc_dump_vfc(p_hwfn,
4144		− p_ptt, dump_buf + offset, dump);
	3483	+ if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)) {
	3484	+ dwords_read = qed_grc_dump_vfc(p_hwfn,
	3485	+ p_ptt, dump_buf + offset, dump);
	3486	+ offset += dwords_read;
	3487	+ if (!dwords_read)
	3488	+ return DBG_STATUS_VFC_READ_ERROR;
	3489	+ }
4145	3490
4146	3491	/* Dump PHY tbus */
4147	3492	if (qed_grc_is_included(p_hwfn,
4148	3493	DBG_GRC_PARAM_DUMP_PHY) && dev_data->chip_id ==
4149		− CHIP_K2 && dev_data->platform_id == PLATFORM_ASIC)
	3494	+ CHIP_K2 && dev_data->hw_type == HW_TYPE_ASIC)
4150	3495	offset += qed_grc_dump_phy(p_hwfn,
4151	3496	p_ptt, dump_buf + offset, dump);
4152	3497
	3498	+ /* Dump MCP HW Dump */
	3499	+ if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP_HW_DUMP) &&
	3500	+ !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP) && 1)
	3501	+ offset += qed_grc_dump_mcp_hw_dump(p_hwfn,
	3502	+ p_ptt,
	3503	+ dump_buf + offset, dump);
	3504	+
4153	3505	/* Dump static debug data (only if not during debug bus recording) */
4154	3506	if (qed_grc_is_included(p_hwfn,
4155	3507	DBG_GRC_PARAM_DUMP_STATIC) &&
@@ -4200,8 +3552,9 @@ static u32 qed_idle_chk_dump_failure(struct qed_hwfn *p_hwfn, · 44 unmodified lines
4200	3552	u8 reg_id;
4201	3553
4202	3554	hdr = (struct dbg_idle_chk_result_hdr *)dump_buf;
4203		− regs = &((const union dbg_idle_chk_reg *)
4204		− s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)[rule->reg_offset];
	3555	+ regs = (const union dbg_idle_chk_reg *)
	3556	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr +
	3557	+ rule->reg_offset;
4205	3558	cond_regs = &regs[0].cond_reg;
4206	3559	info_regs = &regs[rule->num_cond_regs].info_reg;
4207	3560
@@ -4221,8 +3574,8 @@ static u32 qed_idle_chk_dump_failure(struct qed_hwfn *p_hwfn, · 13 unmodified lines
4221	3574	const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id];
4222	3575	struct dbg_idle_chk_result_reg_hdr *reg_hdr;
4223	3576
4224		− reg_hdr = (struct dbg_idle_chk_result_reg_hdr *)
4225		− (dump_buf + offset);
	3577	+ reg_hdr =
	3578	+ (struct dbg_idle_chk_result_reg_hdr *)(dump_buf + offset);
4226	3579
4227	3580	/* Write register header */
4228	3581	if (!dump) {
@@ -4339,12 +3692,13 @@ qed_idle_chk_dump_rule_entries(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt, · 110 unmodified lines
4339	3692	const u32 *imm_values;
4340	3693
4341	3694	rule = &input_rules[i];
4342		− regs = &((const union dbg_idle_chk_reg *)
4343		− s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)
4344		− [rule->reg_offset];
	3695	+ regs = (const union dbg_idle_chk_reg *)
	3696	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr +
	3697	+ rule->reg_offset;
4345	3698	cond_regs = &regs[0].cond_reg;
4346		− imm_values = &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr
4347		− [rule->imm_offset];
	3699	+ imm_values =
	3700	+ (u32 *)p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr +
	3701	+ rule->imm_offset;
4348	3702
4349	3703	/* Check if all condition register blocks are out of reset, and
4350	3704	* find maximal number of entries (all condition registers that
@@ -4462,10 +3816,12 @@ qed_idle_chk_dump_rule_entries(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt, · 111 unmodified lines
4462	3816	static u32 qed_idle_chk_dump(struct qed_hwfn *p_hwfn,
4463	3817	struct qed_ptt p_ptt, u32 dump_buf, bool dump)
4464	3818	{
4465		− u32 num_failing_rules_offset, offset = 0, input_offset = 0;
4466		− u32 num_failing_rules = 0;
	3819	+ struct virt_mem_desc *dbg_buf =
	3820	+ &p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES];
	3821	+ u32 num_failing_rules_offset, offset = 0,
	3822	+ input_offset = 0, num_failing_rules = 0;
4467	3823
4468		− /* Dump global params */
	3824	+ /* Dump global params - 1 must match below amount of params */
4469	3825	offset += qed_dump_common_global_params(p_hwfn,
4470	3826	p_ptt,
4471	3827	dump_buf + offset, dump, 1);
@@ -4477,12 +3833,10 @@ static u32 qed_idle_chk_dump(struct qed_hwfn *p_hwfn, · 5 unmodified lines
4477	3833	num_failing_rules_offset = offset;
4478	3834	offset += qed_dump_num_param(dump_buf + offset, dump, "num_rules", 0);
4479	3835
4480		− while (input_offset <
4481		− s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].size_in_dwords) {
	3836	+ while (input_offset < BYTES_TO_DWORDS(dbg_buf->size)) {
4482	3837	const struct dbg_idle_chk_cond_hdr *cond_hdr =
4483		− (const struct dbg_idle_chk_cond_hdr *)
4484		− &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr
4485		− [input_offset++];
	3838	+ (const struct dbg_idle_chk_cond_hdr *)dbg_buf->ptr +
	3839	+ input_offset++;
4486	3840	bool eval_mode, mode_match = true;
4487	3841	u32 curr_failing_rules;
4488	3842	u16 modes_buf_offset;
@@ -4499,16 +3853,21 @@ static u32 qed_idle_chk_dump(struct qed_hwfn *p_hwfn, · 10 unmodified lines
4499	3853	}
4500	3854
4501	3855	if (mode_match) {
	3856	+ const struct dbg_idle_chk_rule *rule =
	3857	+ (const struct dbg_idle_chk_rule )((u32 )
	3858	+ dbg_buf->ptr
	3859	+ + input_offset);
	3860	+ u32 num_input_rules =
	3861	+ cond_hdr->data_size / IDLE_CHK_RULE_SIZE_DWORDS;
4502	3862	offset +=
4503	3863	qed_idle_chk_dump_rule_entries(p_hwfn,
4504		− p_ptt,
4505		− dump_buf + offset,
4506		− dump,
4507		− (const struct dbg_idle_chk_rule *)
4508		− &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].
4509		− ptr[input_offset],
4510		− cond_hdr->data_size / IDLE_CHK_RULE_SIZE_DWORDS,
4511		− &curr_failing_rules);
	3864	+ p_ptt,
	3865	+ dump_buf +
	3866	+ offset,
	3867	+ dump,
	3868	+ rule,
	3869	+ num_input_rules,
	3870	+ &curr_failing_rules);
4512	3871	num_failing_rules += curr_failing_rules;
4513	3872	}
4514	3873
@@ -4575,7 +3934,7 @@ static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn, · 60 unmodified lines
4575	3934	{
4576	3935	u32 ret_mcp_resp, ret_mcp_param, ret_read_size, bytes_to_copy;
4577	3936	s32 bytes_left = nvram_size_bytes;
4578		− u32 read_offset = 0;
	3937	+ u32 read_offset = 0, param = 0;
4579	3938
4580	3939	DP_VERBOSE(p_hwfn,
4581	3940	QED_MSG_DEBUG,
@@ -4588,14 +3947,14 @@ static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn, · 6 unmodified lines
4588	3947	MCP_DRV_NVM_BUF_LEN) ? MCP_DRV_NVM_BUF_LEN : bytes_left;
4589	3948
4590	3949	/* Call NVRAM read command */
	3950	+ SET_MFW_FIELD(param,
	3951	+ DRV_MB_PARAM_NVM_OFFSET,
	3952	+ nvram_offset_bytes + read_offset);
	3953	+ SET_MFW_FIELD(param, DRV_MB_PARAM_NVM_LEN, bytes_to_copy);
4591	3954	if (qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
4592		− DRV_MSG_CODE_NVM_READ_NVRAM,
4593		− (nvram_offset_bytes +
4594		− read_offset) \|
4595		− (bytes_to_copy <<
4596		− DRV_MB_PARAM_NVM_LEN_OFFSET),
4597		− &ret_mcp_resp, &ret_mcp_param,
4598		− &ret_read_size,
	3955	+ DRV_MSG_CODE_NVM_READ_NVRAM, param,
	3956	+ &ret_mcp_resp,
	3957	+ &ret_mcp_param, &ret_read_size,
4599	3958	(u32 )((u8 )ret_buf + read_offset)))
4600	3959	return DBG_STATUS_NVRAM_READ_FAILED;
4601	3960
@@ -4733,12 +4092,12 @@ static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn, · 131 unmodified lines
4733	4092	u32 trace_meta_size_dwords = 0, running_bundle_id, offset = 0;
4734	4093	u32 trace_meta_offset_bytes = 0, trace_meta_size_bytes = 0;
4735	4094	enum dbg_status status;
4736		− bool mcp_access;
4737	4095	int halted = 0;
	4096	+ bool use_mfw;
4738	4097
4739	4098	*num_dumped_dwords = 0;
4740	4099
4741		− mcp_access = !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP);
	4100	+ use_mfw = !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP);
4742	4101
4743	4102	/* Get trace data info */
4744	4103	status = qed_mcp_trace_get_data_info(p_hwfn,
@@ -4759,7 +4118,7 @@ static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn, · 14 unmodified lines
4759	4118	* consistent. if halt fails, MCP trace is taken anyway, with a small
4760	4119	* risk that it may be corrupt.
4761	4120	*/
4762		− if (dump && mcp_access) {
	4121	+ if (dump && use_mfw) {
4763	4122	halted = !qed_mcp_halt(p_hwfn, p_ptt);
4764	4123	if (!halted)
4765	4124	DP_NOTICE(p_hwfn, "MCP halt failed!\n");
@@ -4799,17 +4158,15 @@ static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn, · 33 unmodified lines
4799	4158	*/
4800	4159	trace_meta_size_bytes =
4801	4160	qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_MCP_TRACE_META_SIZE);
4802		− if ((!trace_meta_size_bytes \|\| dump) && mcp_access) {
	4161	+ if ((!trace_meta_size_bytes \|\| dump) && use_mfw)
4803	4162	status = qed_mcp_trace_get_meta_info(p_hwfn,
4804	4163	p_ptt,
4805	4164	trace_data_size_bytes,
4806	4165	&running_bundle_id,
4807	4166	&trace_meta_offset_bytes,
4808	4167	&trace_meta_size_bytes);
4809		− if (status == DBG_STATUS_OK)
4810		− trace_meta_size_dwords =
4811		− BYTES_TO_DWORDS(trace_meta_size_bytes);
4812		− }
	4168	+ if (status == DBG_STATUS_OK)
	4169	+ trace_meta_size_dwords = BYTES_TO_DWORDS(trace_meta_size_bytes);
4813	4170
4814	4171	/* Dump trace meta size param */
4815	4172	offset += qed_dump_num_param(dump_buf + offset,
@@ -4833,7 +4190,7 @@ static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn, · 17 unmodified lines
4833	4190	/* If no mcp access, indicate that the dump doesn't contain the meta
4834	4191	* data from NVRAM.
4835	4192	*/
4836		− return mcp_access ? status : DBG_STATUS_NVRAM_GET_IMAGE_FAILED;
	4193	+ return use_mfw ? status : DBG_STATUS_NVRAM_GET_IMAGE_FAILED;
4837	4194	}
4838	4195
4839	4196	/* Dump GRC FIFO */
@@ -5058,7 +4415,7 @@ static u32 qed_fw_asserts_dump(struct qed_hwfn *p_hwfn, · 218 unmodified lines
5058	4415	struct storm_defs *storm = &s_storm_defs[storm_id];
5059	4416	u32 last_list_idx, addr;
5060	4417
5061		− if (dev_data->block_in_reset[storm->block_id])
	4418	+ if (dev_data->block_in_reset[storm->sem_block_id])
5062	4419	continue;
5063	4420
5064	4421	/* Read FW info for the current Storm */
@@ -5453,18 +4810,18 @@ static u32 qed_ilt_dump(struct qed_hwfn *p_hwfn, · 388 unmodified lines
5453	4810
5454	4811	/*************************** Public Functions *****************************/
5455	4812
5456		−enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr)
	4813	+enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn,
	4814	+ const u8 * const bin_ptr)
5457	4815	{
5458		− struct bin_buffer_hdr buf_array = (struct bin_buffer_hdr )bin_ptr;
	4816	+ struct bin_buffer_hdr buf_hdrs = (struct bin_buffer_hdr )bin_ptr;
5459	4817	u8 buf_id;
5460	4818
5461		− /* convert binary data to debug arrays */
5462		− for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) {
5463		− s_dbg_arrays[buf_id].ptr =
5464		− (u32 *)(bin_ptr + buf_array[buf_id].offset);
5465		− s_dbg_arrays[buf_id].size_in_dwords =
5466		− BYTES_TO_DWORDS(buf_array[buf_id].length);
5467		− }
	4819	+ /* Convert binary data to debug arrays */
	4820	+ for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++)
	4821	+ qed_set_dbg_bin_buf(p_hwfn,
	4822	+ buf_id,
	4823	+ (u32 *)(bin_ptr + buf_hdrs[buf_id].offset),
	4824	+ buf_hdrs[buf_id].length);
5468	4825
5469	4826	return DBG_STATUS_OK;
5470	4827	}
@@ -5479,7 +4836,7 @@ bool qed_read_fw_info(struct qed_hwfn *p_hwfn, · 8 unmodified lines
5479	4836	struct storm_defs *storm = &s_storm_defs[storm_id];
5480	4837
5481	4838	/* Skip Storm if it's in reset */
5482		− if (dev_data->block_in_reset[storm->block_id])
	4839	+ if (dev_data->block_in_reset[storm->sem_block_id])
5483	4840	continue;
5484	4841
5485	4842	/* Read FW info for the current Storm */
@@ -5492,16 +4849,17 @@ bool qed_read_fw_info(struct qed_hwfn *p_hwfn, · 6 unmodified lines
5492	4849	}
5493	4850
5494	4851	enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
5495		− struct qed_ptt *p_ptt,
5496	4852	enum dbg_grc_params grc_param, u32 val)
5497	4853	{
	4854	+ struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
5498	4855	enum dbg_status status;
5499	4856	int i;
5500	4857
5501		− DP_VERBOSE(p_hwfn, QED_MSG_DEBUG,
	4858	+ DP_VERBOSE(p_hwfn,
	4859	+ QED_MSG_DEBUG,
5502	4860	"dbg_grc_config: paramId = %d, val = %d\n", grc_param, val);
5503	4861
5504		− status = qed_dbg_dev_init(p_hwfn, p_ptt);
	4862	+ status = qed_dbg_dev_init(p_hwfn);
5505	4863	if (status != DBG_STATUS_OK)
5506	4864	return status;
5507	4865
@@ -5527,24 +4885,23 @@ enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn, · 19 unmodified lines
5527	4885
5528	4886	/* Update all params with the preset values */
5529	4887	for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) {
	4888	+ struct grc_param_defs *defs = &s_grc_param_defs[i];
5530	4889	u32 preset_val;
5531		−
5532	4890	/* Skip persistent params */
5533		− if (s_grc_param_defs[i].is_persistent)
	4891	+ if (defs->is_persistent)
5534	4892	continue;
5535	4893
5536	4894	/* Find preset value */
5537	4895	if (grc_param == DBG_GRC_PARAM_EXCLUDE_ALL)
5538	4896	preset_val =
5539		− s_grc_param_defs[i].exclude_all_preset_val;
	4897	+ defs->exclude_all_preset_val;
5540	4898	else if (grc_param == DBG_GRC_PARAM_CRASH)
5541	4899	preset_val =
5542		− s_grc_param_defs[i].crash_preset_val;
	4900	+ defs->crash_preset_val[dev_data->chip_id];
5543	4901	else
5544	4902	return DBG_STATUS_INVALID_ARGS;
5545	4903
5546		− qed_grc_set_param(p_hwfn,
5547		− (enum dbg_grc_params)i, preset_val);
	4904	+ qed_grc_set_param(p_hwfn, i, preset_val);
5548	4905	}
5549	4906	} else {
5550	4907	/* Regular param - set its value */
@@ -5570,18 +4927,18 @@ enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, · 19 unmodified lines
5570	4927	struct qed_ptt *p_ptt,
5571	4928	u32 *buf_size)
5572	4929	{
5573		− enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
	4930	+ enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5574	4931
5575	4932	*buf_size = 0;
5576	4933
5577	4934	if (status != DBG_STATUS_OK)
5578	4935	return status;
5579	4936
5580		− if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr \|\|
5581		− !s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr \|\|
5582		− !s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr \|\|
5583		− !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr \|\|
5584		− !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)
	4937	+ if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr \|\|
	4938	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr \|\|
	4939	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr \|\|
	4940	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr \|\|
	4941	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)
5585	4942	return DBG_STATUS_DBG_ARRAY_NOT_SET;
5586	4943
5587	4944	return qed_grc_dump(p_hwfn, p_ptt, NULL, false, buf_size);
@@ -5621,20 +4978,19 @@ enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, · 33 unmodified lines
5621	4978	u32 *buf_size)
5622	4979	{
5623	4980	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
5624		− struct idle_chk_data *idle_chk;
	4981	+ struct idle_chk_data *idle_chk = &dev_data->idle_chk;
5625	4982	enum dbg_status status;
5626	4983
5627		− idle_chk = &dev_data->idle_chk;
5628	4984	*buf_size = 0;
5629	4985
5630		− status = qed_dbg_dev_init(p_hwfn, p_ptt);
	4986	+ status = qed_dbg_dev_init(p_hwfn);
5631	4987	if (status != DBG_STATUS_OK)
5632	4988	return status;
5633	4989
5634		− if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr \|\|
5635		− !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr \|\|
5636		− !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr \|\|
5637		− !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr)
	4990	+ if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr \|\|
	4991	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr \|\|
	4992	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr \|\|
	4993	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr)
5638	4994	return DBG_STATUS_DBG_ARRAY_NOT_SET;
5639	4995
5640	4996	if (!idle_chk->buf_size_set) {
@@ -5669,6 +5025,7 @@ enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, · 28 unmodified lines
5669	5025	return DBG_STATUS_DUMP_BUF_TOO_SMALL;
5670	5026
5671	5027	/* Update reset state */
	5028	+ qed_grc_unreset_blocks(p_hwfn, p_ptt, true);
5672	5029	qed_update_blocks_reset_state(p_hwfn, p_ptt);
5673	5030
5674	5031	/* Idle Check Dump */
@@ -5684,7 +5041,7 @@ enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, · 9 unmodified lines
5684	5041	struct qed_ptt *p_ptt,
5685	5042	u32 *buf_size)
5686	5043	{
5687		− enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
	5044	+ enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5688	5045
5689	5046	*buf_size = 0;
5690	5047
@@ -5731,7 +5088,7 @@ enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, · 40 unmodified lines
5731	5088	struct qed_ptt *p_ptt,
5732	5089	u32 *buf_size)
5733	5090	{
5734		− enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
	5091	+ enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5735	5092
5736	5093	*buf_size = 0;
5737	5094
@@ -5777,7 +5134,7 @@ enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, · 39 unmodified lines
5777	5134	struct qed_ptt *p_ptt,
5778	5135	u32 *buf_size)
5779	5136	{
5780		− enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
	5137	+ enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5781	5138
5782	5139	*buf_size = 0;
5783	5140
@@ -5823,7 +5180,7 @@ qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, · 39 unmodified lines
5823	5180	struct qed_ptt *p_ptt,
5824	5181	u32 *buf_size)
5825	5182	{
5826		− enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
	5183	+ enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5827	5184
5828	5185	*buf_size = 0;
5829	5186
@@ -5873,7 +5230,7 @@ enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, · 43 unmodified lines
5873	5230	struct qed_ptt *p_ptt,
5874	5231	u32 *buf_size)
5875	5232	{
5876		− enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
	5233	+ enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5877	5234
5878	5235	*buf_size = 0;
5879	5236
@@ -5921,7 +5278,7 @@ static enum dbg_status qed_dbg_ilt_get_dump_buf_size(struct qed_hwfn *p_hwfn, · 41 unmodified lines
5921	5278	struct qed_ptt *p_ptt,
5922	5279	u32 *buf_size)
5923	5280	{
5924		− enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
	5281	+ enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5925	5282
5926	5283	*buf_size = 0;
5927	5284
@@ -5968,19 +5325,20 @@ enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, · 40 unmodified lines
5968	5325	bool clear_status,
5969	5326	struct dbg_attn_block_result *results)
5970	5327	{
5971		− enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
	5328	+ enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5972	5329	u8 reg_idx, num_attn_regs, num_result_regs = 0;
5973	5330	const struct dbg_attn_reg *attn_reg_arr;
5974	5331
5975	5332	if (status != DBG_STATUS_OK)
5976	5333	return status;
5977	5334
5978		− if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr \|\|
5979		− !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr \|\|
5980		− !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)
	5335	+ if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr \|\|
	5336	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr \|\|
	5337	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)
5981	5338	return DBG_STATUS_DBG_ARRAY_NOT_SET;
5982	5339
5983		− attn_reg_arr = qed_get_block_attn_regs(block_id,
	5340	+ attn_reg_arr = qed_get_block_attn_regs(p_hwfn,
	5341	+ block_id,
5984	5342	attn_type, &num_attn_regs);
5985	5343
5986	5344	for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) {
@@ -6025,7 +5383,7 @@ enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, · 38 unmodified lines
6025	5383
6026	5384	results->block_id = (u8)block_id;
6027	5385	results->names_offset =
6028		− qed_get_block_attn_data(block_id, attn_type)->names_offset;
	5386	+ qed_get_block_attn_data(p_hwfn, block_id, attn_type)->names_offset;
6029	5387	SET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE, attn_type);
6030	5388	SET_FIELD(results->data,
6031	5389	DBG_ATTN_BLOCK_RESULT_NUM_REGS, num_result_regs);
@@ -6035,11 +5393,6 @@ enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, · 3 unmodified lines
6035	5393
6036	5394	/***************************** Data Types ********************************/
6037	5395
6038		−struct block_info {
6039		− const char *name;
6040		− enum block_id id;
6041		−};
6042		−
6043	5396	/* REG fifo element */
6044	5397	struct reg_fifo_element {
6045	5398	u64 data;
@@ -6063,6 +5416,12 @@ struct reg_fifo_element { · 17 unmodified lines
6063	5416	#define REG_FIFO_ELEMENT_ERROR_MASK 0x1f
6064	5417	};
6065	5418
	5419	+/* REG fifo error element */
	5420	+struct reg_fifo_err {
	5421	+ u32 err_code;
	5422	+ const char *err_msg;
	5423	+};
	5424	+
6066	5425	/* IGU fifo element */
6067	5426	struct igu_fifo_element {
6068	5427	u32 dword0;
@@ -6162,20 +5521,6 @@ struct igu_fifo_addr_data { · 93 unmodified lines
6162	5521	enum igu_fifo_addr_types type;
6163	5522	};
6164	5523
6165		−struct mcp_trace_meta {
6166		− u32 modules_num;
6167		− char **modules;
6168		− u32 formats_num;
6169		− struct mcp_trace_format *formats;
6170		− bool is_allocated;
6171		−};
6172		−
6173		−/* Debug Tools user data */
6174		−struct dbg_tools_user_data {
6175		− struct mcp_trace_meta mcp_trace_meta;
6176		− const u32 *mcp_trace_user_meta_buf;
6177		−};
6178		−
6179	5524	/****************************** Constants ********************************/
6180	5525
6181	5526	#define MAX_MSG_LEN 1024
@@ -6183,7 +5528,7 @@ struct dbg_tools_user_data { · 1 unmodified line
6183	5528	#define MCP_TRACE_MAX_MODULE_LEN 8
6184	5529	#define MCP_TRACE_FORMAT_MAX_PARAMS 3
6185	5530	#define MCP_TRACE_FORMAT_PARAM_WIDTH \
6186		− (MCP_TRACE_FORMAT_P2_SIZE_SHIFT - MCP_TRACE_FORMAT_P1_SIZE_SHIFT)
	5531	+ (MCP_TRACE_FORMAT_P2_SIZE_OFFSET - MCP_TRACE_FORMAT_P1_SIZE_OFFSET)
6187	5532
6188	5533	#define REG_FIFO_ELEMENT_ADDR_FACTOR 4
6189	5534	#define REG_FIFO_ELEMENT_IS_PF_VF_VAL 127
@@ -6192,107 +5537,6 @@ struct dbg_tools_user_data { · 2 unmodified lines
6192	5537
6193	5538	/*************************** Constant Arrays *****************************/
6194	5539
6195		−struct user_dbg_array {
6196		− const u32 *ptr;
6197		− u32 size_in_dwords;
6198		−};
6199		−
6200		−/* Debug arrays */
6201		−static struct user_dbg_array
6202		−s_user_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} };
6203		−
6204		−/* Block names array */
6205		−static struct block_info s_block_info_arr[] = {
6206		− {"grc", BLOCK_GRC},
6207		− {"miscs", BLOCK_MISCS},
6208		− {"misc", BLOCK_MISC},
6209		− {"dbu", BLOCK_DBU},
6210		− {"pglue_b", BLOCK_PGLUE_B},
6211		− {"cnig", BLOCK_CNIG},
6212		− {"cpmu", BLOCK_CPMU},
6213		− {"ncsi", BLOCK_NCSI},
6214		− {"opte", BLOCK_OPTE},
6215		− {"bmb", BLOCK_BMB},
6216		− {"pcie", BLOCK_PCIE},
6217		− {"mcp", BLOCK_MCP},
6218		− {"mcp2", BLOCK_MCP2},
6219		− {"pswhst", BLOCK_PSWHST},
6220		− {"pswhst2", BLOCK_PSWHST2},
6221		− {"pswrd", BLOCK_PSWRD},
6222		− {"pswrd2", BLOCK_PSWRD2},
6223		− {"pswwr", BLOCK_PSWWR},
6224		− {"pswwr2", BLOCK_PSWWR2},
6225		− {"pswrq", BLOCK_PSWRQ},
6226		− {"pswrq2", BLOCK_PSWRQ2},
6227		− {"pglcs", BLOCK_PGLCS},
6228		− {"ptu", BLOCK_PTU},
6229		− {"dmae", BLOCK_DMAE},
6230		− {"tcm", BLOCK_TCM},
6231		− {"mcm", BLOCK_MCM},
6232		− {"ucm", BLOCK_UCM},
6233		− {"xcm", BLOCK_XCM},
6234		− {"ycm", BLOCK_YCM},
6235		− {"pcm", BLOCK_PCM},
6236		− {"qm", BLOCK_QM},
6237		− {"tm", BLOCK_TM},
6238		− {"dorq", BLOCK_DORQ},
6239		− {"brb", BLOCK_BRB},
6240		− {"src", BLOCK_SRC},
6241		− {"prs", BLOCK_PRS},
6242		− {"tsdm", BLOCK_TSDM},
6243		− {"msdm", BLOCK_MSDM},
6244		− {"usdm", BLOCK_USDM},
6245		− {"xsdm", BLOCK_XSDM},
6246		− {"ysdm", BLOCK_YSDM},
6247		− {"psdm", BLOCK_PSDM},
6248		− {"tsem", BLOCK_TSEM},
6249		− {"msem", BLOCK_MSEM},
6250		− {"usem", BLOCK_USEM},
6251		− {"xsem", BLOCK_XSEM},
6252		− {"ysem", BLOCK_YSEM},
6253		− {"psem", BLOCK_PSEM},
6254		− {"rss", BLOCK_RSS},
6255		− {"tmld", BLOCK_TMLD},
6256		− {"muld", BLOCK_MULD},
6257		− {"yuld", BLOCK_YULD},
6258		− {"xyld", BLOCK_XYLD},
6259		− {"ptld", BLOCK_PTLD},
6260		− {"ypld", BLOCK_YPLD},
6261		− {"prm", BLOCK_PRM},
6262		− {"pbf_pb1", BLOCK_PBF_PB1},
6263		− {"pbf_pb2", BLOCK_PBF_PB2},
6264		− {"rpb", BLOCK_RPB},
6265		− {"btb", BLOCK_BTB},
6266		− {"pbf", BLOCK_PBF},
6267		− {"rdif", BLOCK_RDIF},
6268		− {"tdif", BLOCK_TDIF},
6269		− {"cdu", BLOCK_CDU},
6270		− {"ccfc", BLOCK_CCFC},
6271		− {"tcfc", BLOCK_TCFC},
6272		− {"igu", BLOCK_IGU},
6273		− {"cau", BLOCK_CAU},
6274		− {"rgfs", BLOCK_RGFS},
6275		− {"rgsrc", BLOCK_RGSRC},
6276		− {"tgfs", BLOCK_TGFS},
6277		− {"tgsrc", BLOCK_TGSRC},
6278		− {"umac", BLOCK_UMAC},
6279		− {"xmac", BLOCK_XMAC},
6280		− {"dbg", BLOCK_DBG},
6281		− {"nig", BLOCK_NIG},
6282		− {"wol", BLOCK_WOL},
6283		− {"bmbn", BLOCK_BMBN},
6284		− {"ipc", BLOCK_IPC},
6285		− {"nwm", BLOCK_NWM},
6286		− {"nws", BLOCK_NWS},
6287		− {"ms", BLOCK_MS},
6288		− {"phy_pcie", BLOCK_PHY_PCIE},
6289		− {"led", BLOCK_LED},
6290		− {"avs_wrap", BLOCK_AVS_WRAP},
6291		− {"pxpreqbus", BLOCK_PXPREQBUS},
6292		− {"misc_aeu", BLOCK_MISC_AEU},
6293		− {"bar0_map", BLOCK_BAR0_MAP}
6294		−};
6295		−
6296	5540	/* Status string array */
6297	5541	static const char * const s_status_str[] = {
6298	5542	/* DBG_STATUS_OK */
@@ -6322,14 +5566,12 @@ static const char * const s_status_str[] = { · 23 unmodified lines
6322	5566	/* DBG_STATUS_PCI_BUF_NOT_ALLOCATED */
6323	5567	"A PCI buffer wasn't allocated",
6324	5568
6325		− /* DBG_STATUS_TOO_MANY_INPUTS */
6326		− "Too many inputs were enabled. Enabled less inputs, or set 'unifyInputs' to true",
	5569	+ /* DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS */
	5570	+ "The filter/trigger constraint dword offsets are not enabled for recording",
6327	5571
6328		− /* DBG_STATUS_INPUT_OVERLAP */
6329		− "Overlapping debug bus inputs",
6330	5572
6331		− /* DBG_STATUS_HW_ONLY_RECORDING */
6332		− "Cannot record Storm data since the entire recording cycle is used by HW",
	5573	+ /* DBG_STATUS_VFC_READ_ERROR */
	5574	+ "Error reading from VFC",
6333	5575
6334	5576	/* DBG_STATUS_STORM_ALREADY_ENABLED */
6335	5577	"The Storm was already enabled",
@@ -6346,8 +5588,8 @@ static const char * const s_status_str[] = { · 10 unmodified lines
6346	5588	/* DBG_STATUS_NO_INPUT_ENABLED */
6347	5589	"No input was enabled for recording",
6348	5590
6349		− /* DBG_STATUS_NO_FILTER_TRIGGER_64B */
6350		− "Filters and triggers are not allowed when recording in 64b units",
	5591	+ /* DBG_STATUS_NO_FILTER_TRIGGER_256B */
	5592	+ "Filters and triggers are not allowed in E4 256-bit mode",
6351	5593
6352	5594	/* DBG_STATUS_FILTER_ALREADY_ENABLED */
6353	5595	"The filter was already enabled",
@@ -6421,8 +5663,8 @@ static const char * const s_status_str[] = { · 67 unmodified lines
6421	5663	/* DBG_STATUS_MCP_COULD_NOT_RESUME */
6422	5664	"Failed to resume MCP after halt",
6423	5665
6424		− /* DBG_STATUS_RESERVED2 */
6425		− "Reserved debug status - shouldn't be returned",
	5666	+ /* DBG_STATUS_RESERVED0 */
	5667	+ "",
6426	5668
6427	5669	/* DBG_STATUS_SEMI_FIFO_NOT_EMPTY */
6428	5670	"Failed to empty SEMI sync FIFO",
@@ -6445,17 +5687,32 @@ static const char * const s_status_str[] = { · 16 unmodified lines
6445	5687	/* DBG_STATUS_DBG_ARRAY_NOT_SET */
6446	5688	"Debug arrays were not set (when using binary files, dbg_set_bin_ptr must be called)",
6447	5689
6448		− /* DBG_STATUS_FILTER_BUG */
6449		− "Debug Bus filtering requires the -unifyInputs option (due to a HW bug)",
	5690	+ /* DBG_STATUS_RESERVED1 */
	5691	+ "",
6450	5692
6451	5693	/* DBG_STATUS_NON_MATCHING_LINES */
6452		− "Non-matching debug lines - all lines must be of the same type (either 128b or 256b)",
	5694	+ "Non-matching debug lines - in E4, all lines must be of the same type (either 128b or 256b)",
6453	5695
6454		− /* DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET */
6455		− "The selected trigger dword offset wasn't enabled in the recorded HW block",
	5696	+ /* DBG_STATUS_INSUFFICIENT_HW_IDS */
	5697	+ "Insufficient HW IDs. Try to record less Storms/blocks",
6456	5698
6457	5699	/* DBG_STATUS_DBG_BUS_IN_USE */
6458		− "The debug bus is in use"
	5700	+ "The debug bus is in use",
	5701	+
	5702	+ /* DBG_STATUS_INVALID_STORM_DBG_MODE */
	5703	+ "The storm debug mode is not supported in the current chip",
	5704	+
	5705	+ /* DBG_STATUS_OTHER_ENGINE_BB_ONLY */
	5706	+ "Other engine is supported only in BB",
	5707	+
	5708	+ /* DBG_STATUS_FILTER_SINGLE_HW_ID */
	5709	+ "The configured filter mode requires a single Storm/block input",
	5710	+
	5711	+ /* DBG_STATUS_TRIGGER_SINGLE_HW_ID */
	5712	+ "The configured filter mode requires that all the constraints of a single trigger state will be defined on a single Storm/block input",
	5713	+
	5714	+ /* DBG_STATUS_MISSING_TRIGGER_STATE_STORM */
	5715	+ "When triggering on Storm data, the Storm to trigger on must be specified"
6459	5716	};
6460	5717
6461	5718	/* Idle check severity names array */
@@ -6511,7 +5768,7 @@ static const char * const s_master_strs[] = { · 49 unmodified lines
6511	5768	"xsdm",
6512	5769	"dbu",
6513	5770	"dmae",
6514		− "???",
	5771	+ "jdap",
6515	5772	"???",
6516	5773	"???",
6517	5774	"???",
@@ -6519,12 +5776,13 @@ static const char * const s_master_strs[] = { · 1 unmodified line
6519	5776	};
6520	5777
6521	5778	/* REG FIFO error messages array */
6522		−static const char * const s_reg_fifo_error_strs[] = {
6523		− "grc timeout",
6524		− "address doesn't belong to any block",
6525		− "reserved address in block or write to read-only address",
6526		− "privilege/protection mismatch",
6527		− "path isolation error"
	5779	+static struct reg_fifo_err s_reg_fifo_errors[] = {
	5780	+ {1, "grc timeout"},
	5781	+ {2, "address doesn't belong to any block"},
	5782	+ {4, "reserved address in block or write to read-only address"},
	5783	+ {8, "privilege/protection mismatch"},
	5784	+ {16, "path isolation error"},
	5785	+ {17, "RSL error"}
6528	5786	};
6529	5787
6530	5788	/* IGU FIFO sources array */
@@ -6764,8 +6022,21 @@ static u32 qed_print_section_params(u32 *dump_buf, · 233 unmodified lines
6764	6022	return dump_offset;
6765	6023	}
6766	6024
6767		−static struct dbg_tools_user_data *
6768		−qed_dbg_get_user_data(struct qed_hwfn *p_hwfn)
	6025	+/* Returns the block name that matches the specified block ID,
	6026	+ * or NULL if not found.
	6027	+ */
	6028	+static const char qed_dbg_get_block_name(struct qed_hwfn p_hwfn,
	6029	+ enum block_id block_id)
	6030	+{
	6031	+ const struct dbg_block_user *block =
	6032	+ (const struct dbg_block_user *)
	6033	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_BLOCKS_USER_DATA].ptr + block_id;
	6034	+
	6035	+ return (const char *)block->name;
	6036	+}
	6037	+
	6038	+static struct dbg_tools_user_data *qed_dbg_get_user_data(struct qed_hwfn
	6039	+ *p_hwfn)
6769	6040	{
6770	6041	return (struct dbg_tools_user_data *)p_hwfn->dbg_user_info;
6771	6042	}
@@ -6773,7 +6044,8 @@ qed_dbg_get_user_data(struct qed_hwfn *p_hwfn) · 1 unmodified line
6773	6044	/* Parses the idle check rules and returns the number of characters printed.
6774	6045	* In case of parsing error, returns 0.
6775	6046	*/
6776		−static u32 qed_parse_idle_chk_dump_rules(u32 *dump_buf,
	6047	+static u32 qed_parse_idle_chk_dump_rules(struct qed_hwfn *p_hwfn,
	6048	+ u32 *dump_buf,
6777	6049	u32 *dump_buf_end,
6778	6050	u32 num_rules,
6779	6051	bool print_fw_idle_chk,
@@ -6801,19 +6073,18 @@ static u32 qed_parse_idle_chk_dump_rules(u32 *dump_buf, · 21 unmodified lines
6801	6073
6802	6074	hdr = (struct dbg_idle_chk_result_hdr *)dump_buf;
6803	6075	rule_parsing_data =
6804		− (const struct dbg_idle_chk_rule_parsing_data *)
6805		− &s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].
6806		− ptr[hdr->rule_id];
	6076	+ (const struct dbg_idle_chk_rule_parsing_data *)
	6077	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr +
	6078	+ hdr->rule_id;
6807	6079	parsing_str_offset =
6808		− GET_FIELD(rule_parsing_data->data,
6809		− DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET);
	6080	+ GET_FIELD(rule_parsing_data->data,
	6081	+ DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET);
6810	6082	has_fw_msg =
6811		− GET_FIELD(rule_parsing_data->data,
6812		− DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG) > 0;
6813		− parsing_str =
6814		− &((const char *)
6815		− s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr)
6816		− [parsing_str_offset];
	6083	+ GET_FIELD(rule_parsing_data->data,
	6084	+ DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG) > 0;
	6085	+ parsing_str = (const char *)
	6086	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr +
	6087	+ parsing_str_offset;
6817	6088	lsi_msg = parsing_str;
6818	6089	curr_reg_id = 0;
6819	6090
@@ -6917,7 +6188,8 @@ static u32 qed_parse_idle_chk_dump_rules(u32 *dump_buf, · 97 unmodified lines
6917	6188	* parsed_results_bytes.
6918	6189	* The parsing status is returned.
6919	6190	*/
6920		−static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf,
	6191	+static enum dbg_status qed_parse_idle_chk_dump(struct qed_hwfn *p_hwfn,
	6192	+ u32 *dump_buf,
6921	6193	u32 num_dumped_dwords,
6922	6194	char *results_buf,
6923	6195	u32 *parsed_results_bytes,
@@ -6935,8 +6207,8 @@ static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf, · 11 unmodified lines
6935	6207	*num_errors = 0;
6936	6208	*num_warnings = 0;
6937	6209
6938		− if (!s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr \|\|
6939		− !s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr)
	6210	+ if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr \|\|
	6211	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr)
6940	6212	return DBG_STATUS_DBG_ARRAY_NOT_SET;
6941	6213
6942	6214	/* Read global_params section */
@@ -6969,7 +6241,8 @@ static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf, · 26 unmodified lines
6969	6241	results_offset),
6970	6242	"FW_IDLE_CHECK:\n");
6971	6243	rules_print_size =
6972		− qed_parse_idle_chk_dump_rules(dump_buf,
	6244	+ qed_parse_idle_chk_dump_rules(p_hwfn,
	6245	+ dump_buf,
6973	6246	dump_buf_end,
6974	6247	num_rules,
6975	6248	true,
@@ -6989,7 +6262,8 @@ static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf, · 13 unmodified lines
6989	6262	results_offset),
6990	6263	"\nLSI_IDLE_CHECK:\n");
6991	6264	rules_print_size =
6992		− qed_parse_idle_chk_dump_rules(dump_buf,
	6265	+ qed_parse_idle_chk_dump_rules(p_hwfn,
	6266	+ dump_buf,
6993	6267	dump_buf_end,
6994	6268	num_rules,
6995	6269	false,
@@ -7101,9 +6375,8 @@ qed_mcp_trace_alloc_meta_data(struct qed_hwfn *p_hwfn, · 105 unmodified lines
7101	6375
7102	6376	format_ptr->data = qed_read_dword_from_buf(meta_buf_bytes,
7103	6377	&offset);
7104		− format_len =
7105		− (format_ptr->data &
7106		− MCP_TRACE_FORMAT_LEN_MASK) >> MCP_TRACE_FORMAT_LEN_SHIFT;
	6378	+ format_len = GET_MFW_FIELD(format_ptr->data,
	6379	+ MCP_TRACE_FORMAT_LEN);
7107	6380	format_ptr->format_str = kzalloc(format_len, GFP_KERNEL);
7108	6381	if (!format_ptr->format_str) {
7109	6382	/* Update number of modules to be released */
@@ -7126,7 +6399,7 @@ qed_mcp_trace_alloc_meta_data(struct qed_hwfn *p_hwfn, · 16 unmodified lines
7126	6399	* trace_buf - MCP trace cyclic buffer
7127	6400	* trace_buf_size - MCP trace cyclic buffer size in bytes
7128	6401	* data_offset - offset in bytes of the data to parse in the MCP trace cyclic
7129		− * buffer.
	6402	+ * buffer.
7130	6403	* data_size - size in bytes of data to parse.
7131	6404	* parsed_buf - destination buffer for parsed data.
7132	6405	* parsed_results_bytes - size of parsed data in bytes.
@@ -7171,9 +6444,8 @@ static enum dbg_status qed_parse_mcp_trace_buf(struct qed_hwfn *p_hwfn, · 38 unmodified lines
7171	6444
7172	6445	/* Skip message if its index doesn't exist in the meta data */
7173	6446	if (format_idx >= meta->formats_num) {
7174		− u8 format_size =
7175		− (u8)((header & MFW_TRACE_PRM_SIZE_MASK) >>
7176		− MFW_TRACE_PRM_SIZE_SHIFT);
	6447	+ u8 format_size = (u8)GET_MFW_FIELD(header,
	6448	+ MFW_TRACE_PRM_SIZE);
7177	6449
7178	6450	if (data_size < format_size)
7179	6451	return DBG_STATUS_MCP_TRACE_BAD_DATA;
@@ -7188,11 +6460,10 @@ static enum dbg_status qed_parse_mcp_trace_buf(struct qed_hwfn *p_hwfn, · 8 unmodified lines
7188	6460	format_ptr = &meta->formats[format_idx];
7189	6461
7190	6462	for (i = 0,
7191		− param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK,
7192		− param_shift = MCP_TRACE_FORMAT_P1_SIZE_SHIFT;
	6463	+ param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK, param_shift =
	6464	+ MCP_TRACE_FORMAT_P1_SIZE_OFFSET;
7193	6465	i < MCP_TRACE_FORMAT_MAX_PARAMS;
7194		− i++,
7195		− param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH,
	6466	+ i++, param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH,
7196	6467	param_shift += MCP_TRACE_FORMAT_PARAM_WIDTH) {
7197	6468	/* Extract param size (0..3) */
7198	6469	u8 param_size = (u8)((format_ptr->data & param_mask) >>
@@ -7220,12 +6491,10 @@ static enum dbg_status qed_parse_mcp_trace_buf(struct qed_hwfn *p_hwfn, · 21 unmodified lines
7220	6491	data_size -= param_size;
7221	6492	}
7222	6493
7223		− format_level = (u8)((format_ptr->data &
7224		− MCP_TRACE_FORMAT_LEVEL_MASK) >>
7225		− MCP_TRACE_FORMAT_LEVEL_SHIFT);
7226		− format_module = (u8)((format_ptr->data &
7227		− MCP_TRACE_FORMAT_MODULE_MASK) >>
7228		− MCP_TRACE_FORMAT_MODULE_SHIFT);
	6494	+ format_level = (u8)GET_MFW_FIELD(format_ptr->data,
	6495	+ MCP_TRACE_FORMAT_LEVEL);
	6496	+ format_module = (u8)GET_MFW_FIELD(format_ptr->data,
	6497	+ MCP_TRACE_FORMAT_MODULE);
7229	6498	if (format_level >= ARRAY_SIZE(s_mcp_trace_level_str))
7230	6499	return DBG_STATUS_MCP_TRACE_BAD_DATA;
7231	6500
@@ -7367,7 +6636,7 @@ static enum dbg_status qed_parse_reg_fifo_dump(u32 *dump_buf, · 135 unmodified lines
7367	6636	const char section_name, param_name, *param_str_val;
7368	6637	u32 param_num_val, num_section_params, num_elements;
7369	6638	struct reg_fifo_element *elements;
7370		− u8 i, j, err_val, vf_val;
	6639	+ u8 i, j, err_code, vf_val;
7371	6640	u32 results_offset = 0;
7372	6641	char vf_str[4];
7373	6642
@@ -7398,7 +6667,7 @@ static enum dbg_status qed_parse_reg_fifo_dump(u32 *dump_buf, · 24 unmodified lines
7398	6667
7399	6668	/* Decode elements */
7400	6669	for (i = 0; i < num_elements; i++) {
7401		− bool err_printed = false;
	6670	+ const char *err_msg = NULL;
7402	6671
7403	6672	/* Discover if element belongs to a VF or a PF */
7404	6673	vf_val = GET_FIELD(elements[i].data, REG_FIFO_ELEMENT_VF);
@@ -7407,11 +6676,17 @@ static enum dbg_status qed_parse_reg_fifo_dump(u32 *dump_buf, · 2 unmodified lines
7407	6676	else
7408	6677	sprintf(vf_str, "%d", vf_val);
7409	6678
	6679	+ /* Find error message */
	6680	+ err_code = GET_FIELD(elements[i].data, REG_FIFO_ELEMENT_ERROR);
	6681	+ for (j = 0; j < ARRAY_SIZE(s_reg_fifo_errors) && !err_msg; j++)
	6682	+ if (err_code == s_reg_fifo_errors[j].err_code)
	6683	+ err_msg = s_reg_fifo_errors[j].err_msg;
	6684	+
7410	6685	/* Add parsed element to parsed buffer */
7411	6686	results_offset +=
7412	6687	sprintf(qed_get_buf_ptr(results_buf,
7413	6688	results_offset),
7414		− "raw: 0x%016llx, address: 0x%07x, access: %-5s, pf: %2d, vf: %s, port: %d, privilege: %-3s, protection: %-12s, master: %-4s, errors: ",
	6689	+ "raw: 0x%016llx, address: 0x%07x, access: %-5s, pf: %2d, vf: %s, port: %d, privilege: %-3s, protection: %-12s, master: %-4s, error: %s\n",
7415	6690	elements[i].data,
7416	6691	(u32)GET_FIELD(elements[i].data,
7417	6692	REG_FIFO_ELEMENT_ADDRESS) *
@@ -7428,30 +6703,8 @@ static enum dbg_status qed_parse_reg_fifo_dump(u32 *dump_buf, · 10 unmodified lines
7428	6703	s_protection_strs[GET_FIELD(elements[i].data,
7429	6704	REG_FIFO_ELEMENT_PROTECTION)],
7430	6705	s_master_strs[GET_FIELD(elements[i].data,
7431		− REG_FIFO_ELEMENT_MASTER)]);
7432		−
7433		− /* Print errors */
7434		− for (j = 0,
7435		− err_val = GET_FIELD(elements[i].data,
7436		− REG_FIFO_ELEMENT_ERROR);
7437		− j < ARRAY_SIZE(s_reg_fifo_error_strs);
7438		− j++, err_val >>= 1) {
7439		− if (err_val & 0x1) {
7440		− if (err_printed)
7441		− results_offset +=
7442		− sprintf(qed_get_buf_ptr
7443		− (results_buf,
7444		− results_offset), ", ");
7445		− results_offset +=
7446		− sprintf(qed_get_buf_ptr
7447		− (results_buf, results_offset), "%s",
7448		− s_reg_fifo_error_strs[j]);
7449		− err_printed = true;
7450		− }
7451		− }
7452		−
7453		− results_offset +=
7454		− sprintf(qed_get_buf_ptr(results_buf, results_offset), "\n");
	6706	+ REG_FIFO_ELEMENT_MASTER)],
	6707	+ err_msg ? err_msg : "unknown error code");
7455	6708	}
7456	6709
7457	6710	results_offset += sprintf(qed_get_buf_ptr(results_buf,
@@ -7805,27 +7058,28 @@ static enum dbg_status qed_parse_fw_asserts_dump(u32 *dump_buf, · 347 unmodified lines
7805	7058
7806	7059	/*************************** Public Functions *****************************/
7807	7060
7808		−enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr)
	7061	+enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn,
	7062	+ const u8 * const bin_ptr)
7809	7063	{
7810		− struct bin_buffer_hdr buf_array = (struct bin_buffer_hdr )bin_ptr;
	7064	+ struct bin_buffer_hdr buf_hdrs = (struct bin_buffer_hdr )bin_ptr;
7811	7065	u8 buf_id;
7812	7066
7813	7067	/* Convert binary data to debug arrays */
7814		− for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) {
7815		− s_user_dbg_arrays[buf_id].ptr =
7816		− (u32 *)(bin_ptr + buf_array[buf_id].offset);
7817		− s_user_dbg_arrays[buf_id].size_in_dwords =
7818		− BYTES_TO_DWORDS(buf_array[buf_id].length);
7819		− }
	7068	+ for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++)
	7069	+ qed_set_dbg_bin_buf(p_hwfn,
	7070	+ (enum bin_dbg_buffer_type)buf_id,
	7071	+ (u32 *)(bin_ptr + buf_hdrs[buf_id].offset),
	7072	+ buf_hdrs[buf_id].length);
7820	7073
7821	7074	return DBG_STATUS_OK;
7822	7075	}
7823	7076
7824		−enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn)
	7077	+enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn,
	7078	+ void **user_data_ptr)
7825	7079	{
7826		− p_hwfn->dbg_user_info = kzalloc(sizeof(struct dbg_tools_user_data),
7827		− GFP_KERNEL);
7828		− if (!p_hwfn->dbg_user_info)
	7080	+ *user_data_ptr = kzalloc(sizeof(struct dbg_tools_user_data),
	7081	+ GFP_KERNEL);
	7082	+ if (!(*user_data_ptr))
7829	7083	return DBG_STATUS_VIRT_MEM_ALLOC_FAILED;
7830	7084
7831	7085	return DBG_STATUS_OK;
@@ -7844,7 +7098,8 @@ enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, · 12 unmodified lines
7844	7098	{
7845	7099	u32 num_errors, num_warnings;
7846	7100
7847		− return qed_parse_idle_chk_dump(dump_buf,
	7101	+ return qed_parse_idle_chk_dump(p_hwfn,
	7102	+ dump_buf,
7848	7103	num_dumped_dwords,
7849	7104	NULL,
7850	7105	results_buf_size,
@@ -7860,7 +7115,8 @@ enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, · 9 unmodified lines
7860	7115	{
7861	7116	u32 parsed_buf_size;
7862	7117
7863		− return qed_parse_idle_chk_dump(dump_buf,
	7118	+ return qed_parse_idle_chk_dump(p_hwfn,
	7119	+ dump_buf,
7864	7120	num_dumped_dwords,
7865	7121	results_buf,
7866	7122	&parsed_buf_size,
@@ -8031,25 +7287,28 @@ enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, · 164 unmodified lines
8031	7287	enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
8032	7288	struct dbg_attn_block_result *results)
8033	7289	{
8034		− struct user_dbg_array block_attn, pstrings;
8035	7290	const u32 *block_attn_name_offsets;
8036		− enum dbg_attn_type attn_type;
	7291	+ const char *attn_name_base;
8037	7292	const char *block_name;
	7293	+ enum dbg_attn_type attn_type;
8038	7294	u8 num_regs, i, j;
8039	7295
8040	7296	num_regs = GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_NUM_REGS);
8041		− attn_type = (enum dbg_attn_type)
8042		− GET_FIELD(results->data,
8043		− DBG_ATTN_BLOCK_RESULT_ATTN_TYPE);
8044		− block_name = s_block_info_arr[results->block_id].name;
8045		−
8046		− if (!s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr \|\|
8047		− !s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr \|\|
8048		− !s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr)
	7297	+ attn_type = GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE);
	7298	+ block_name = qed_dbg_get_block_name(p_hwfn, results->block_id);
	7299	+ if (!block_name)
	7300	+ return DBG_STATUS_INVALID_ARGS;
	7301	+
	7302	+ if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr \|\|
	7303	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr \|\|
	7304	+ !p_hwfn->dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr)
8049	7305	return DBG_STATUS_DBG_ARRAY_NOT_SET;
8050	7306
8051		− block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS];
8052		− block_attn_name_offsets = &block_attn->ptr[results->names_offset];
	7307	+ block_attn_name_offsets =
	7308	+ (u32 *)p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr +
	7309	+ results->names_offset;
	7310	+
	7311	+ attn_name_base = p_hwfn->dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr;
8053	7312
8054	7313	/* Go over registers with a non-zero attention status */
8055	7314	for (i = 0; i < num_regs; i++) {
@@ -8060,18 +7319,17 @@ enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, · 4 unmodified lines
8060	7319	reg_result = &results->reg_results[i];
8061	7320	num_reg_attn = GET_FIELD(reg_result->data,
8062	7321	DBG_ATTN_REG_RESULT_NUM_REG_ATTN);
8063		− block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES];
8064		− bit_mapping = &((struct dbg_attn_bit_mapping *)
8065		− block_attn->ptr)[reg_result->block_attn_offset];
8066		−
8067		− pstrings = &s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS];
	7322	+ bit_mapping = (struct dbg_attn_bit_mapping *)
	7323	+ p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr +
	7324	+ reg_result->block_attn_offset;
8068	7325
8069	7326	/* Go over attention status bits */
8070		− for (j = 0; j < num_reg_attn; j++) {
	7327	+ for (j = 0; j < num_reg_attn; j++, bit_idx++) {
8071	7328	u16 attn_idx_val = GET_FIELD(bit_mapping[j].data,
8072	7329	DBG_ATTN_BIT_MAPPING_VAL);
8073	7330	const char attn_name, attn_type_str, *masked_str;
8074		− u32 attn_name_offset, sts_addr;
	7331	+ u32 attn_name_offset;
	7332	+ u32 sts_addr;
8075	7333
8076	7334	/* Check if bit mask should be advanced (due to unused
8077	7335	* bits).
@@ -8083,18 +7341,19 @@ enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, · 5 unmodified lines
8083	7341	}
8084	7342
8085	7343	/* Check current bit index */
8086		− if (!(reg_result->sts_val & BIT(bit_idx))) {
8087		− bit_idx++;
	7344	+ if (!(reg_result->sts_val & BIT(bit_idx)))
8088	7345	continue;
8089		− }
8090	7346
8091		− /* Find attention name */
	7347	+ /* An attention bit with value=1 was found
	7348	+ * Find attention name
	7349	+ */
8092	7350	attn_name_offset =
8093	7351	block_attn_name_offsets[attn_idx_val];
8094		− attn_name = &((const char *)
8095		− pstrings->ptr)[attn_name_offset];
8096		− attn_type_str = attn_type == ATTN_TYPE_INTERRUPT ?
8097		− "Interrupt" : "Parity";
	7352	+ attn_name = attn_name_base + attn_name_offset;
	7353	+ attn_type_str =
	7354	+ (attn_type ==
	7355	+ ATTN_TYPE_INTERRUPT ? "Interrupt" :
	7356	+ "Parity");
8098	7357	masked_str = reg_result->mask_val & BIT(bit_idx) ?
8099	7358	" [masked]" : "";
8100	7359	sts_addr = GET_FIELD(reg_result->data,
@@ -8102,15 +7361,15 @@ enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, · 1 unmodified line
8102	7361	DP_NOTICE(p_hwfn,
8103	7362	"%s (%s) : %s [address 0x%08x, bit %d]%s\n",
8104	7363	block_name, attn_type_str, attn_name,
8105		− sts_addr, bit_idx, masked_str);
8106		−
8107		− bit_idx++;
	7364	+ sts_addr * 4, bit_idx, masked_str);
8108	7365	}
8109	7366	}
8110	7367
8111	7368	return DBG_STATUS_OK;
8112	7369	}
8113	7370
	7371	+static DEFINE_MUTEX(qed_dbg_lock);
	7372	+
8114	7373	/* Wrapper for unifying the idle_chk and mcp_trace api */
8115	7374	static enum dbg_status
8116	7375	qed_print_idle_chk_results_wrapper(struct qed_hwfn *p_hwfn,
@@ -8287,6 +7546,17 @@ static enum dbg_status qed_dbg_dump(struct qed_hwfn *p_hwfn, · 170 unmodified lines
8287	7546	&buf_size_dwords);
8288	7547	if (rc != DBG_STATUS_OK && rc != DBG_STATUS_NVRAM_GET_IMAGE_FAILED)
8289	7548	return rc;
	7549	+
	7550	+ if (buf_size_dwords > MAX_DBG_FEATURE_SIZE_DWORDS) {
	7551	+ feature->buf_size = 0;
	7552	+ DP_NOTICE(p_hwfn->cdev,
	7553	+ "Debug feature [\"%s\"] size (0x%x dwords) exceeds maximum size (0x%x dwords)\n",
	7554	+ qed_features_lookup[feature_idx].name,
	7555	+ buf_size_dwords, MAX_DBG_FEATURE_SIZE_DWORDS);
	7556	+
	7557	+ return DBG_STATUS_OK;
	7558	+ }
	7559	+
8290	7560	feature->buf_size = buf_size_dwords * sizeof(u32);
8291	7561	feature->dump_buf = vmalloc(feature->buf_size);
8292	7562	if (!feature->dump_buf)
@@ -8487,15 +7757,23 @@ enum debug_print_features { · 194 unmodified lines
8487	7757	ILT_DUMP = 13,
8488	7758	};
8489	7759
8490		−static u32 qed_calc_regdump_header(enum debug_print_features feature,
	7760	+static u32 qed_calc_regdump_header(struct qed_dev *cdev,
	7761	+ enum debug_print_features feature,
8491	7762	int engine, u32 feature_size, u8 omit_engine)
8492	7763	{
8493		− /* Insert the engine, feature and mode inside the header and combine it
8494		− * with feature size.
8495		− */
8496		− return feature_size \| (feature << REGDUMP_HEADER_FEATURE_SHIFT) \|
8497		− (omit_engine << REGDUMP_HEADER_OMIT_ENGINE_SHIFT) \|
8498		− (engine << REGDUMP_HEADER_ENGINE_SHIFT);
	7764	+ u32 res = 0;
	7765	+
	7766	+ SET_FIELD(res, REGDUMP_HEADER_SIZE, feature_size);
	7767	+ if (res != feature_size)
	7768	+ DP_NOTICE(cdev,
	7769	+ "Feature %d is too large (size 0x%x) and will corrupt the dump\n",
	7770	+ feature, feature_size);
	7771	+
	7772	+ SET_FIELD(res, REGDUMP_HEADER_FEATURE, feature);
	7773	+ SET_FIELD(res, REGDUMP_HEADER_OMIT_ENGINE, omit_engine);
	7774	+ SET_FIELD(res, REGDUMP_HEADER_ENGINE, engine);
	7775	+
	7776	+ return res;
8499	7777	}
8500	7778
8501	7779	int qed_dbg_all_data(struct qed_dev cdev, void buffer)
@@ -8511,9 +7789,11 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 9 unmodified lines
8511	7789	for (i = 0; i < MAX_DBG_GRC_PARAMS; i++)
8512	7790	grc_params[i] = dev_data->grc.param_val[i];
8513	7791
8514		− if (cdev->num_hwfns == 1)
	7792	+ if (!QED_IS_CMT(cdev))
8515	7793	omit_engine = 1;
8516	7794
	7795	+ mutex_lock(&qed_dbg_lock);
	7796	+
8517	7797	org_engine = qed_get_debug_engine(cdev);
8518	7798	for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) {
8519	7799	/* Collect idle_chks and grcDump for each hw function */
@@ -8526,7 +7806,7 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 6 unmodified lines
8526	7806	REGDUMP_HEADER_SIZE, &feature_size);
8527	7807	if (!rc) {
8528	7808	(u32 )((u8 *)buffer + offset) =
8529		− qed_calc_regdump_header(IDLE_CHK, cur_engine,
	7809	+ qed_calc_regdump_header(cdev, IDLE_CHK, cur_engine,
8530	7810	feature_size, omit_engine);
8531	7811	offset += (feature_size + REGDUMP_HEADER_SIZE);
8532	7812	} else {
@@ -8538,7 +7818,7 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 5 unmodified lines
8538	7818	REGDUMP_HEADER_SIZE, &feature_size);
8539	7819	if (!rc) {
8540	7820	(u32 )((u8 *)buffer + offset) =
8541		− qed_calc_regdump_header(IDLE_CHK, cur_engine,
	7821	+ qed_calc_regdump_header(cdev, IDLE_CHK, cur_engine,
8542	7822	feature_size, omit_engine);
8543	7823	offset += (feature_size + REGDUMP_HEADER_SIZE);
8544	7824	} else {
@@ -8550,7 +7830,7 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 5 unmodified lines
8550	7830	REGDUMP_HEADER_SIZE, &feature_size);
8551	7831	if (!rc) {
8552	7832	(u32 )((u8 *)buffer + offset) =
8553		− qed_calc_regdump_header(REG_FIFO, cur_engine,
	7833	+ qed_calc_regdump_header(cdev, REG_FIFO, cur_engine,
8554	7834	feature_size, omit_engine);
8555	7835	offset += (feature_size + REGDUMP_HEADER_SIZE);
8556	7836	} else {
@@ -8562,7 +7842,7 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 5 unmodified lines
8562	7842	REGDUMP_HEADER_SIZE, &feature_size);
8563	7843	if (!rc) {
8564	7844	(u32 )((u8 *)buffer + offset) =
8565		− qed_calc_regdump_header(IGU_FIFO, cur_engine,
	7845	+ qed_calc_regdump_header(cdev, IGU_FIFO, cur_engine,
8566	7846	feature_size, omit_engine);
8567	7847	offset += (feature_size + REGDUMP_HEADER_SIZE);
8568	7848	} else {
@@ -8575,7 +7855,7 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 6 unmodified lines
8575	7855	&feature_size);
8576	7856	if (!rc) {
8577	7857	(u32 )((u8 *)buffer + offset) =
8578		− qed_calc_regdump_header(PROTECTION_OVERRIDE,
	7858	+ qed_calc_regdump_header(cdev, PROTECTION_OVERRIDE,
8579	7859	cur_engine,
8580	7860	feature_size, omit_engine);
8581	7861	offset += (feature_size + REGDUMP_HEADER_SIZE);
@@ -8590,8 +7870,9 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 8 unmodified lines
8590	7870	REGDUMP_HEADER_SIZE, &feature_size);
8591	7871	if (!rc) {
8592	7872	(u32 )((u8 *)buffer + offset) =
8593		− qed_calc_regdump_header(FW_ASSERTS, cur_engine,
8594		− feature_size, omit_engine);
	7873	+ qed_calc_regdump_header(cdev, FW_ASSERTS,
	7874	+ cur_engine, feature_size,
	7875	+ omit_engine);
8595	7876	offset += (feature_size + REGDUMP_HEADER_SIZE);
8596	7877	} else {
8597	7878	DP_ERR(cdev, "qed_dbg_fw_asserts failed. rc = %d\n",
@@ -8605,7 +7886,7 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 7 unmodified lines
8605	7886	REGDUMP_HEADER_SIZE, &feature_size);
8606	7887	if (!rc) {
8607	7888	(u32 )((u8 *)buffer + offset) =
8608		− qed_calc_regdump_header(ILT_DUMP,
	7889	+ qed_calc_regdump_header(cdev, ILT_DUMP,
8609	7890	cur_engine,
8610	7891	feature_size,
8611	7892	omit_engine);
@@ -8619,11 +7900,15 @@ int qed_dbg_all_data(struct qed_dev cdev, void buffer) · 7 unmodified lines
8619	7900	/* GRC dump - must be last because when mcp stuck it will
8620	7901	* clutter idle_chk, reg_fifo, ...
8621	7902	*/
	7903	+ for (i = 0; i < MAX_DBG_GRC_PARAMS; i++)
	7904	+ dev_data->grc.param_val[i] = grc_params[i];
	7905	+
8622	7906	rc = qed_dbg_grc(cdev, (u8 *)buffer + offset +
8623	7907	REGDUMP_HEADER_SIZE, &feature_size);

136 more lines aren’t shown here.

drivers/net/ethernet/qlogic/qed/qed_dev.c+1−1

@@ -2346,7 +2346,7 @@ int qed_resc_alloc(struct qed_dev *cdev) · 2345 unmodified lines
2346	2346	if (rc)
2347	2347	goto alloc_err;
2348	2348
2349		− rc = qed_dbg_alloc_user_data(p_hwfn);
	2349	+ rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info);
2350	2350	if (rc)
2351	2351	goto alloc_err;
2352	2352	}

drivers/net/ethernet/qlogic/qed/qed_hsi.h+173−488

@@ -1860,98 +1860,6 @@ struct virt_mem_desc { · 1859 unmodified lines
1860	1860	/* Debug Tools HSI constants and macros */
1861	1861	/****************************************/
1862	1862
1863		−enum block_addr {
1864		− GRCBASE_GRC = 0x50000,
1865		− GRCBASE_MISCS = 0x9000,
1866		− GRCBASE_MISC = 0x8000,
1867		− GRCBASE_DBU = 0xa000,
1868		− GRCBASE_PGLUE_B = 0x2a8000,
1869		− GRCBASE_CNIG = 0x218000,
1870		− GRCBASE_CPMU = 0x30000,
1871		− GRCBASE_NCSI = 0x40000,
1872		− GRCBASE_OPTE = 0x53000,
1873		− GRCBASE_BMB = 0x540000,
1874		− GRCBASE_PCIE = 0x54000,
1875		− GRCBASE_MCP = 0xe00000,
1876		− GRCBASE_MCP2 = 0x52000,
1877		− GRCBASE_PSWHST = 0x2a0000,
1878		− GRCBASE_PSWHST2 = 0x29e000,
1879		− GRCBASE_PSWRD = 0x29c000,
1880		− GRCBASE_PSWRD2 = 0x29d000,
1881		− GRCBASE_PSWWR = 0x29a000,
1882		− GRCBASE_PSWWR2 = 0x29b000,
1883		− GRCBASE_PSWRQ = 0x280000,
1884		− GRCBASE_PSWRQ2 = 0x240000,
1885		− GRCBASE_PGLCS = 0x0,
1886		− GRCBASE_DMAE = 0xc000,
1887		− GRCBASE_PTU = 0x560000,
1888		− GRCBASE_TCM = 0x1180000,
1889		− GRCBASE_MCM = 0x1200000,
1890		− GRCBASE_UCM = 0x1280000,
1891		− GRCBASE_XCM = 0x1000000,
1892		− GRCBASE_YCM = 0x1080000,
1893		− GRCBASE_PCM = 0x1100000,
1894		− GRCBASE_QM = 0x2f0000,
1895		− GRCBASE_TM = 0x2c0000,
1896		− GRCBASE_DORQ = 0x100000,
1897		− GRCBASE_BRB = 0x340000,
1898		− GRCBASE_SRC = 0x238000,
1899		− GRCBASE_PRS = 0x1f0000,
1900		− GRCBASE_TSDM = 0xfb0000,
1901		− GRCBASE_MSDM = 0xfc0000,
1902		− GRCBASE_USDM = 0xfd0000,
1903		− GRCBASE_XSDM = 0xf80000,
1904		− GRCBASE_YSDM = 0xf90000,
1905		− GRCBASE_PSDM = 0xfa0000,
1906		− GRCBASE_TSEM = 0x1700000,
1907		− GRCBASE_MSEM = 0x1800000,
1908		− GRCBASE_USEM = 0x1900000,
1909		− GRCBASE_XSEM = 0x1400000,
1910		− GRCBASE_YSEM = 0x1500000,
1911		− GRCBASE_PSEM = 0x1600000,
1912		− GRCBASE_RSS = 0x238800,
1913		− GRCBASE_TMLD = 0x4d0000,
1914		− GRCBASE_MULD = 0x4e0000,
1915		− GRCBASE_YULD = 0x4c8000,
1916		− GRCBASE_XYLD = 0x4c0000,
1917		− GRCBASE_PTLD = 0x5a0000,
1918		− GRCBASE_YPLD = 0x5c0000,
1919		− GRCBASE_PRM = 0x230000,
1920		− GRCBASE_PBF_PB1 = 0xda0000,
1921		− GRCBASE_PBF_PB2 = 0xda4000,
1922		− GRCBASE_RPB = 0x23c000,
1923		− GRCBASE_BTB = 0xdb0000,
1924		− GRCBASE_PBF = 0xd80000,
1925		− GRCBASE_RDIF = 0x300000,
1926		− GRCBASE_TDIF = 0x310000,
1927		− GRCBASE_CDU = 0x580000,
1928		− GRCBASE_CCFC = 0x2e0000,
1929		− GRCBASE_TCFC = 0x2d0000,
1930		− GRCBASE_IGU = 0x180000,
1931		− GRCBASE_CAU = 0x1c0000,
1932		− GRCBASE_RGFS = 0xf00000,
1933		− GRCBASE_RGSRC = 0x320000,
1934		− GRCBASE_TGFS = 0xd00000,
1935		− GRCBASE_TGSRC = 0x322000,
1936		− GRCBASE_UMAC = 0x51000,
1937		− GRCBASE_XMAC = 0x210000,
1938		− GRCBASE_DBG = 0x10000,
1939		− GRCBASE_NIG = 0x500000,
1940		− GRCBASE_WOL = 0x600000,
1941		− GRCBASE_BMBN = 0x610000,
1942		− GRCBASE_IPC = 0x20000,
1943		− GRCBASE_NWM = 0x800000,
1944		− GRCBASE_NWS = 0x700000,
1945		− GRCBASE_MS = 0x6a0000,
1946		− GRCBASE_PHY_PCIE = 0x620000,
1947		− GRCBASE_LED = 0x6b8000,
1948		− GRCBASE_AVS_WRAP = 0x6b0000,
1949		− GRCBASE_PXPREQBUS = 0x56000,
1950		− GRCBASE_MISC_AEU = 0x8000,
1951		− GRCBASE_BAR0_MAP = 0x1c00000,
1952		− MAX_BLOCK_ADDR
1953		−};
1954		−
1955	1863	enum block_id {
1956	1864	BLOCK_GRC,
1957	1865	BLOCK_MISCS,
@@ -2006,8 +1914,6 @@ enum block_id { · 48 unmodified lines
2006	1914	BLOCK_MULD,
2007	1915	BLOCK_YULD,
2008	1916	BLOCK_XYLD,
2009		− BLOCK_PTLD,
2010		− BLOCK_YPLD,
2011	1917	BLOCK_PRM,
2012	1918	BLOCK_PBF_PB1,
2013	1919	BLOCK_PBF_PB2,
@@ -2021,12 +1927,9 @@ enum block_id { · 7 unmodified lines
2021	1927	BLOCK_TCFC,
2022	1928	BLOCK_IGU,
2023	1929	BLOCK_CAU,
2024		− BLOCK_RGFS,
2025		− BLOCK_RGSRC,
2026		− BLOCK_TGFS,
2027		− BLOCK_TGSRC,
2028	1930	BLOCK_UMAC,
2029	1931	BLOCK_XMAC,
	1932	+ BLOCK_MSTAT,
2030	1933	BLOCK_DBG,
2031	1934	BLOCK_NIG,
2032	1935	BLOCK_WOL,
@@ -2039,8 +1942,17 @@ enum block_id { · 6 unmodified lines
2039	1942	BLOCK_LED,
2040	1943	BLOCK_AVS_WRAP,
2041	1944	BLOCK_PXPREQBUS,
2042		− BLOCK_MISC_AEU,
2043	1945	BLOCK_BAR0_MAP,
	1946	+ BLOCK_MCP_FIO,
	1947	+ BLOCK_LAST_INIT,
	1948	+ BLOCK_PRS_FC,
	1949	+ BLOCK_PBF_FC,
	1950	+ BLOCK_NIG_LB_FC,
	1951	+ BLOCK_NIG_LB_FC_PLLH,
	1952	+ BLOCK_NIG_TX_FC_PLLH,
	1953	+ BLOCK_NIG_TX_FC,
	1954	+ BLOCK_NIG_RX_FC_PLLH,
	1955	+ BLOCK_NIG_RX_FC,
2044	1956	MAX_BLOCK_ID
2045	1957	};
2046	1958
@@ -2057,10 +1969,13 @@ enum bin_dbg_buffer_type { · 10 unmodified lines
2057	1969	BIN_BUF_DBG_ATTN_REGS,
2058	1970	BIN_BUF_DBG_ATTN_INDEXES,
2059	1971	BIN_BUF_DBG_ATTN_NAME_OFFSETS,
2060		− BIN_BUF_DBG_BUS_BLOCKS,
	1972	+ BIN_BUF_DBG_BLOCKS,
	1973	+ BIN_BUF_DBG_BLOCKS_CHIP_DATA,
2061	1974	BIN_BUF_DBG_BUS_LINES,
2062		− BIN_BUF_DBG_BUS_BLOCKS_USER_DATA,
	1975	+ BIN_BUF_DBG_BLOCKS_USER_DATA,
	1976	+ BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA,
2063	1977	BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
	1978	+ BIN_BUF_DBG_RESET_REGS,
2064	1979	BIN_BUF_DBG_PARSING_STRINGS,
2065	1980	MAX_BIN_DBG_BUFFER_TYPE
2066	1981	};
@@ -2144,20 +2059,54 @@ enum dbg_attn_type { · 77 unmodified lines
2144	2059	MAX_DBG_ATTN_TYPE
2145	2060	};
2146	2061
2147		−/* Debug Bus block data */
2148		−struct dbg_bus_block {
2149		− u8 num_of_lines;
2150		− u8 has_latency_events;
2151		− u16 lines_offset;
	2062	+/* Block debug data */
	2063	+struct dbg_block {
	2064	+ u8 name[15];
	2065	+ u8 associated_storm_letter;
2152	2066	};
2153	2067
2154		−/* Debug Bus block user data */
2155		−struct dbg_bus_block_user_data {
2156		− u8 num_of_lines;
	2068	+/* Chip-specific block debug data */
	2069	+struct dbg_block_chip {
	2070	+ u8 flags;
	2071	+#define DBG_BLOCK_CHIP_IS_REMOVED_MASK 0x1
	2072	+#define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT 0
	2073	+#define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK 0x1
	2074	+#define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT 1
	2075	+#define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK 0x1
	2076	+#define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2
	2077	+#define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK 0x1
	2078	+#define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT 3
	2079	+#define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK 0x1
	2080	+#define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT 4
	2081	+#define DBG_BLOCK_CHIP_RESERVED0_MASK 0x7
	2082	+#define DBG_BLOCK_CHIP_RESERVED0_SHIFT 5
	2083	+ u8 dbg_client_id;
	2084	+ u8 reset_reg_id;
	2085	+ u8 reset_reg_bit_offset;
	2086	+ struct dbg_mode_hdr dbg_bus_mode;
	2087	+ u16 reserved1;
	2088	+ u8 reserved2;
	2089	+ u8 num_of_dbg_bus_lines;
	2090	+ u16 dbg_bus_lines_offset;
	2091	+ u32 dbg_select_reg_addr;
	2092	+ u32 dbg_dword_enable_reg_addr;
	2093	+ u32 dbg_shift_reg_addr;
	2094	+ u32 dbg_force_valid_reg_addr;
	2095	+ u32 dbg_force_frame_reg_addr;
	2096	+};
	2097	+
	2098	+/* Chip-specific block user debug data */
	2099	+struct dbg_block_chip_user {
	2100	+ u8 num_of_dbg_bus_lines;
2157	2101	u8 has_latency_events;
2158	2102	u16 names_offset;
2159	2103	};
2160	2104
	2105	+/* Block user debug data */
	2106	+struct dbg_block_user {
	2107	+ u8 name[16];
	2108	+};
	2109	+
2161	2110	/* Block Debug line data */
2162	2111	struct dbg_bus_line {
2163	2112	u8 data;
@@ -2310,22 +2259,33 @@ enum dbg_idle_chk_severity_types { · 146 unmodified lines
2310	2259	MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2311	2260	};
2312	2261
	2262	+/* Reset register */
	2263	+struct dbg_reset_reg {
	2264	+ u32 data;
	2265	+#define DBG_RESET_REG_ADDR_MASK 0xFFFFFF
	2266	+#define DBG_RESET_REG_ADDR_SHIFT 0
	2267	+#define DBG_RESET_REG_IS_REMOVED_MASK 0x1
	2268	+#define DBG_RESET_REG_IS_REMOVED_SHIFT 24
	2269	+#define DBG_RESET_REG_RESERVED_MASK 0x7F
	2270	+#define DBG_RESET_REG_RESERVED_SHIFT 25
	2271	+};
	2272	+
2313	2273	/* Debug Bus block data */
2314	2274	struct dbg_bus_block_data {
2315		− u16 data;
2316		−#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF
2317		−#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0
2318		−#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF
2319		−#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4
2320		−#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF
2321		−#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8
2322		−#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF
2323		−#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12
	2275	+ u8 enable_mask;
	2276	+ u8 right_shift;
	2277	+ u8 force_valid_mask;
	2278	+ u8 force_frame_mask;
	2279	+ u8 dword_mask;
2324	2280	u8 line_num;
2325	2281	u8 hw_id;
	2282	+ u8 flags;
	2283	+#define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK 0x1
	2284	+#define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
	2285	+#define DBG_BUS_BLOCK_DATA_RESERVED_MASK 0x7F
	2286	+#define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT 1
2326	2287	};
2327	2288
2328		−/* Debug Bus Clients */
2329	2289	enum dbg_bus_clients {
2330	2290	DBG_BUS_CLIENT_RBCN,
2331	2291	DBG_BUS_CLIENT_RBCP,
@@ -2366,11 +2326,10 @@ enum dbg_bus_constraint_ops { · 34 unmodified lines
2366	2326
2367	2327	/* Debug Bus trigger state data */
2368	2328	struct dbg_bus_trigger_state_data {
2369		− u8 data;
2370		−#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF
2371		−#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0
2372		−#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF
2373		−#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4
	2329	+ u8 msg_len;
	2330	+ u8 constraint_dword_mask;
	2331	+ u8 storm_id;
	2332	+ u8 reserved;
2374	2333	};
2375	2334
2376	2335	/* Debug Bus memory address */
@@ -2420,8 +2379,7 @@ struct dbg_bus_storm_data { · 43 unmodified lines
2420	2379	struct dbg_bus_data {
2421	2380	u32 app_version;
2422	2381	u8 state;
2423		− u8 hw_dwords;
2424		− u16 hw_id_mask;
	2382	+ u8 mode_256b_en;
2425	2383	u8 num_enabled_blocks;
2426	2384	u8 num_enabled_storms;
2427	2385	u8 target;
@@ -2432,67 +2390,21 @@ struct dbg_bus_data { · 4 unmodified lines
2432	2390	u8 adding_filter;
2433	2391	u8 filter_pre_trigger;
2434	2392	u8 filter_post_trigger;
2435		− u16 reserved;
2436	2393	u8 trigger_en;
2437		− struct dbg_bus_trigger_state_data trigger_states[3];
	2394	+ u8 filter_constraint_dword_mask;
2438	2395	u8 next_trigger_state;
2439	2396	u8 next_constraint_id;
2440		− u8 unify_inputs;
	2397	+ struct dbg_bus_trigger_state_data trigger_states[3];
	2398	+ u8 filter_msg_len;
2441	2399	u8 rcv_from_other_engine;
	2400	+ u8 blocks_dword_mask;
	2401	+ u8 blocks_dword_overlap;
	2402	+ u32 hw_id_mask;
2442	2403	struct dbg_bus_pci_buf_data pci_buf;
2443		− struct dbg_bus_block_data blocks[88];
	2404	+ struct dbg_bus_block_data blocks[132];
2444	2405	struct dbg_bus_storm_data storms[6];
2445	2406	};
2446	2407
2447		−/* Debug bus filter types */
2448		−enum dbg_bus_filter_types {
2449		− DBG_BUS_FILTER_TYPE_OFF,
2450		− DBG_BUS_FILTER_TYPE_PRE,
2451		− DBG_BUS_FILTER_TYPE_POST,
2452		− DBG_BUS_FILTER_TYPE_ON,
2453		− MAX_DBG_BUS_FILTER_TYPES
2454		−};
2455		−
2456		−/* Debug bus frame modes */
2457		−enum dbg_bus_frame_modes {
2458		− DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2459		− DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2460		− DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2461		− MAX_DBG_BUS_FRAME_MODES
2462		−};
2463		−
2464		−/* Debug bus other engine mode */
2465		−enum dbg_bus_other_engine_modes {
2466		− DBG_BUS_OTHER_ENGINE_MODE_NONE,
2467		− DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2468		− DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2469		− DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2470		− DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2471		− MAX_DBG_BUS_OTHER_ENGINE_MODES
2472		−};
2473		−
2474		−/* Debug bus post-trigger recording types */
2475		−enum dbg_bus_post_trigger_types {
2476		− DBG_BUS_POST_TRIGGER_RECORD,
2477		− DBG_BUS_POST_TRIGGER_DROP,
2478		− MAX_DBG_BUS_POST_TRIGGER_TYPES
2479		−};
2480		−
2481		−/* Debug bus pre-trigger recording types */
2482		−enum dbg_bus_pre_trigger_types {
2483		− DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2484		− DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2485		− DBG_BUS_PRE_TRIGGER_DROP,
2486		− MAX_DBG_BUS_PRE_TRIGGER_TYPES
2487		−};
2488		−
2489		−/* Debug bus SEMI frame modes */
2490		−enum dbg_bus_semi_frame_modes {
2491		− DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2492		− DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2493		− MAX_DBG_BUS_SEMI_FRAME_MODES
2494		−};
2495		−
2496	2408	/* Debug bus states */
2497	2409	enum dbg_bus_states {
2498	2410	DBG_BUS_STATE_IDLE,
@@ -2510,7 +2422,9 @@ enum dbg_bus_storm_modes { · 11 unmodified lines
2510	2422	DBG_BUS_STORM_MODE_DRA_W,
2511	2423	DBG_BUS_STORM_MODE_LD_ST_ADDR,
2512	2424	DBG_BUS_STORM_MODE_DRA_FSM,
	2425	+ DBG_BUS_STORM_MODE_FAST_DBGMUX,
2513	2426	DBG_BUS_STORM_MODE_RH,
	2427	+ DBG_BUS_STORM_MODE_RH_WITH_STORE,
2514	2428	DBG_BUS_STORM_MODE_FOC,
2515	2429	DBG_BUS_STORM_MODE_EXT_STORE,
2516	2430	MAX_DBG_BUS_STORM_MODES
@@ -2551,13 +2465,13 @@ enum dbg_grc_params { · 34 unmodified lines
2551	2465	DBG_GRC_PARAM_DUMP_CAU,
2552	2466	DBG_GRC_PARAM_DUMP_QM,
2553	2467	DBG_GRC_PARAM_DUMP_MCP,
2554		− DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
	2468	+ DBG_GRC_PARAM_DUMP_DORQ,
2555	2469	DBG_GRC_PARAM_DUMP_CFC,
2556	2470	DBG_GRC_PARAM_DUMP_IGU,
2557	2471	DBG_GRC_PARAM_DUMP_BRB,
2558	2472	DBG_GRC_PARAM_DUMP_BTB,
2559	2473	DBG_GRC_PARAM_DUMP_BMB,
2560		− DBG_GRC_PARAM_DUMP_NIG,
	2474	+ DBG_GRC_PARAM_RESERVD1,
2561	2475	DBG_GRC_PARAM_DUMP_MULD,
2562	2476	DBG_GRC_PARAM_DUMP_PRS,
2563	2477	DBG_GRC_PARAM_DUMP_DMAE,
@@ -2566,8 +2480,8 @@ enum dbg_grc_params { · 2 unmodified lines
2566	2480	DBG_GRC_PARAM_DUMP_DIF,
2567	2481	DBG_GRC_PARAM_DUMP_STATIC,
2568	2482	DBG_GRC_PARAM_UNSTALL,
2569		− DBG_GRC_PARAM_NUM_LCIDS,
2570		− DBG_GRC_PARAM_NUM_LTIDS,
	2483	+ DBG_GRC_PARAM_RESERVED2,
	2484	+ DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
2571	2485	DBG_GRC_PARAM_EXCLUDE_ALL,
2572	2486	DBG_GRC_PARAM_CRASH,
2573	2487	DBG_GRC_PARAM_PARITY_SAFE,
@@ -2583,19 +2497,6 @@ enum dbg_grc_params { · 9 unmodified lines
2583	2497	MAX_DBG_GRC_PARAMS
2584	2498	};
2585	2499
2586		−/* Debug reset registers */
2587		−enum dbg_reset_regs {
2588		− DBG_RESET_REG_MISCS_PL_UA,
2589		− DBG_RESET_REG_MISCS_PL_HV,
2590		− DBG_RESET_REG_MISCS_PL_HV_2,
2591		− DBG_RESET_REG_MISC_PL_UA,
2592		− DBG_RESET_REG_MISC_PL_HV,
2593		− DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2594		− DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2595		− DBG_RESET_REG_MISC_PL_PDA_VAUX,
2596		− MAX_DBG_RESET_REGS
2597		−};
2598		−
2599	2500	/* Debug status codes */
2600	2501	enum dbg_status {
2601	2502	DBG_STATUS_OK,
@@ -2607,15 +2508,15 @@ enum dbg_status { · 5 unmodified lines
2607	2508	DBG_STATUS_INVALID_PCI_BUF_SIZE,
2608	2509	DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2609	2510	DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2610		− DBG_STATUS_TOO_MANY_INPUTS,
2611		− DBG_STATUS_INPUT_OVERLAP,
2612		− DBG_STATUS_HW_ONLY_RECORDING,
	2511	+ DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS,
	2512	+ DBG_STATUS_NO_MATCHING_FRAMING_MODE,
	2513	+ DBG_STATUS_VFC_READ_ERROR,
2613	2514	DBG_STATUS_STORM_ALREADY_ENABLED,
2614	2515	DBG_STATUS_STORM_NOT_ENABLED,
2615	2516	DBG_STATUS_BLOCK_ALREADY_ENABLED,
2616	2517	DBG_STATUS_BLOCK_NOT_ENABLED,
2617	2518	DBG_STATUS_NO_INPUT_ENABLED,
2618		− DBG_STATUS_NO_FILTER_TRIGGER_64B,
	2519	+ DBG_STATUS_NO_FILTER_TRIGGER_256B,
2619	2520	DBG_STATUS_FILTER_ALREADY_ENABLED,
2620	2521	DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2621	2522	DBG_STATUS_TRIGGER_NOT_ENABLED,
@@ -2640,7 +2541,7 @@ enum dbg_status { · 18 unmodified lines
2640	2541	DBG_STATUS_MCP_TRACE_NO_META,
2641	2542	DBG_STATUS_MCP_COULD_NOT_HALT,
2642	2543	DBG_STATUS_MCP_COULD_NOT_RESUME,
2643		− DBG_STATUS_RESERVED2,
	2544	+ DBG_STATUS_RESERVED0,
2644	2545	DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2645	2546	DBG_STATUS_IGU_FIFO_BAD_DATA,
2646	2547	DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
@@ -2648,10 +2549,15 @@ enum dbg_status { · 1 unmodified line
2648	2549	DBG_STATUS_REG_FIFO_BAD_DATA,
2649	2550	DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2650	2551	DBG_STATUS_DBG_ARRAY_NOT_SET,
2651		− DBG_STATUS_FILTER_BUG,
	2552	+ DBG_STATUS_RESERVED1,
2652	2553	DBG_STATUS_NON_MATCHING_LINES,
2653		− DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET,
	2554	+ DBG_STATUS_INSUFFICIENT_HW_IDS,
2654	2555	DBG_STATUS_DBG_BUS_IN_USE,
	2556	+ DBG_STATUS_INVALID_STORM_DBG_MODE,
	2557	+ DBG_STATUS_OTHER_ENGINE_BB_ONLY,
	2558	+ DBG_STATUS_FILTER_SINGLE_HW_ID,
	2559	+ DBG_STATUS_TRIGGER_SINGLE_HW_ID,
	2560	+ DBG_STATUS_MISSING_TRIGGER_STATE_STORM,
2655	2561	MAX_DBG_STATUS
2656	2562	};
2657	2563
@@ -2687,9 +2593,9 @@ struct dbg_tools_data { · 29 unmodified lines
2687	2593	struct dbg_bus_data bus;
2688	2594	struct idle_chk_data idle_chk;
2689	2595	u8 mode_enable[40];
2690		− u8 block_in_reset[88];
	2596	+ u8 block_in_reset[132];
2691	2597	u8 chip_id;
2692		− u8 platform_id;
	2598	+ u8 hw_type;
2693	2599	u8 num_ports;
2694	2600	u8 num_pfs_per_port;
2695	2601	u8 num_vfs;
@@ -2808,7 +2714,6 @@ struct init_qm_vport_params { · 112 unmodified lines
2808	2714	enum chip_ids {
2809	2715	CHIP_BB,
2810	2716	CHIP_K2,
2811		− CHIP_RESERVED,
2812	2717	MAX_CHIP_IDS
2813	2718	};
2814	2719
@@ -3135,9 +3040,11 @@ struct iro { · 320 unmodified lines
3135	3040	* @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
3136	3041	* arrays.
3137	3042	*
	3043	+ * @param p_hwfn - HW device data
3138	3044	* @param bin_ptr - a pointer to the binary data with debug arrays.
3139	3045	*/
3140		−enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
	3046	+enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn,
	3047	+ const u8 * const bin_ptr);
3141	3048
3142	3049	/**
3143	3050	* @brief qed_read_regs - Reads registers into a buffer (using GRC).
@@ -3181,7 +3088,6 @@ bool qed_read_fw_info(struct qed_hwfn *p_hwfn, · 37 unmodified lines
3181	3088	* - val is outside the allowed boundaries
3182	3089	*/
3183	3090	enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
3184		− struct qed_ptt *p_ptt,
3185	3091	enum dbg_grc_params grc_param, u32 val);
3186	3092
3187	3093	/**
@@ -3502,20 +3408,36 @@ enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn, · 314 unmodified lines
3502	3408	struct mcp_trace_format {
3503	3409	u32 data;
3504	3410	#define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff
3505		−#define MCP_TRACE_FORMAT_MODULE_SHIFT 0
	3411	+#define MCP_TRACE_FORMAT_MODULE_OFFSET 0
3506	3412	#define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000
3507		−#define MCP_TRACE_FORMAT_LEVEL_SHIFT 16
	3413	+#define MCP_TRACE_FORMAT_LEVEL_OFFSET 16
3508	3414	#define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000
3509		−#define MCP_TRACE_FORMAT_P1_SIZE_SHIFT 18
	3415	+#define MCP_TRACE_FORMAT_P1_SIZE_OFFSET 18
3510	3416	#define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000
3511		−#define MCP_TRACE_FORMAT_P2_SIZE_SHIFT 20
	3417	+#define MCP_TRACE_FORMAT_P2_SIZE_OFFSET 20
3512	3418	#define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000
3513		−#define MCP_TRACE_FORMAT_P3_SIZE_SHIFT 22
	3419	+#define MCP_TRACE_FORMAT_P3_SIZE_OFFSET 22
3514	3420	#define MCP_TRACE_FORMAT_LEN_MASK 0xff000000
3515		−#define MCP_TRACE_FORMAT_LEN_SHIFT 24
	3421	+#define MCP_TRACE_FORMAT_LEN_OFFSET 24
	3422	+
3516	3423	char *format_str;
3517	3424	};
3518	3425
	3426	+/* MCP Trace Meta data structure */
	3427	+struct mcp_trace_meta {
	3428	+ u32 modules_num;
	3429	+ char **modules;
	3430	+ u32 formats_num;
	3431	+ struct mcp_trace_format *formats;
	3432	+ bool is_allocated;
	3433	+};
	3434	+
	3435	+/* Debug Tools user data */
	3436	+struct dbg_tools_user_data {
	3437	+ struct mcp_trace_meta mcp_trace_meta;
	3438	+ const u32 *mcp_trace_user_meta_buf;
	3439	+};
	3440	+
3519	3441	/****************************** Constants ********************************/
3520	3442
3521	3443	#define MAX_NAME_LEN 16
@@ -3526,16 +3448,20 @@ struct mcp_trace_format { · 4 unmodified lines
3526	3448	* @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3527	3449	* debug arrays.
3528	3450	*
	3451	+ * @param p_hwfn - HW device data
3529	3452	* @param bin_ptr - a pointer to the binary data with debug arrays.
3530	3453	*/
3531		−enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
	3454	+enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn,
	3455	+ const u8 * const bin_ptr);
3532	3456
3533	3457	/**
3534	3458	* @brief qed_dbg_alloc_user_data - Allocates user debug data.
3535	3459	*
3536	3460	* @param p_hwfn - HW device data
	3461	+ * @param user_data_ptr - OUT: a pointer to the allocated memory.
3537	3462	*/
3538		−enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn);
	3463	+enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn,
	3464	+ void **user_data_ptr);
3539	3465
3540	3466	/**
3541	3467	* @brief qed_dbg_get_status_str - Returns a string for the specified status.
@@ -3808,271 +3734,6 @@ enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, · 266 unmodified lines
3808	3734	enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3809	3735	struct dbg_attn_block_result *results);
3810	3736
3811		−/* Debug Bus blocks */
3812		−static const u32 dbg_bus_blocks[] = {
3813		− 0x0000000f, /* grc, bb, 15 lines */
3814		− 0x0000000f, /* grc, k2, 15 lines */
3815		− 0x00000000,
3816		− 0x00000000, /* miscs, bb, 0 lines */
3817		− 0x00000000, /* miscs, k2, 0 lines */
3818		− 0x00000000,
3819		− 0x00000000, /* misc, bb, 0 lines */
3820		− 0x00000000, /* misc, k2, 0 lines */
3821		− 0x00000000,
3822		− 0x00000000, /* dbu, bb, 0 lines */
3823		− 0x00000000, /* dbu, k2, 0 lines */
3824		− 0x00000000,
3825		− 0x000f0127, /* pglue_b, bb, 39 lines */
3826		− 0x0036012a, /* pglue_b, k2, 42 lines */
3827		− 0x00000000,
3828		− 0x00000000, /* cnig, bb, 0 lines */
3829		− 0x00120102, /* cnig, k2, 2 lines */
3830		− 0x00000000,
3831		− 0x00000000, /* cpmu, bb, 0 lines */
3832		− 0x00000000, /* cpmu, k2, 0 lines */
3833		− 0x00000000,
3834		− 0x00000001, /* ncsi, bb, 1 lines */
3835		− 0x00000001, /* ncsi, k2, 1 lines */
3836		− 0x00000000,
3837		− 0x00000000, /* opte, bb, 0 lines */
3838		− 0x00000000, /* opte, k2, 0 lines */
3839		− 0x00000000,
3840		− 0x00600085, /* bmb, bb, 133 lines */
3841		− 0x00600085, /* bmb, k2, 133 lines */
3842		− 0x00000000,
3843		− 0x00000000, /* pcie, bb, 0 lines */
3844		− 0x00e50033, /* pcie, k2, 51 lines */
3845		− 0x00000000,
3846		− 0x00000000, /* mcp, bb, 0 lines */
3847		− 0x00000000, /* mcp, k2, 0 lines */
3848		− 0x00000000,
3849		− 0x01180009, /* mcp2, bb, 9 lines */
3850		− 0x01180009, /* mcp2, k2, 9 lines */
3851		− 0x00000000,
3852		− 0x01210104, /* pswhst, bb, 4 lines */
3853		− 0x01210104, /* pswhst, k2, 4 lines */
3854		− 0x00000000,
3855		− 0x01250103, /* pswhst2, bb, 3 lines */
3856		− 0x01250103, /* pswhst2, k2, 3 lines */
3857		− 0x00000000,
3858		− 0x00340101, /* pswrd, bb, 1 lines */
3859		− 0x00340101, /* pswrd, k2, 1 lines */
3860		− 0x00000000,
3861		− 0x01280119, /* pswrd2, bb, 25 lines */
3862		− 0x01280119, /* pswrd2, k2, 25 lines */
3863		− 0x00000000,
3864		− 0x01410109, /* pswwr, bb, 9 lines */
3865		− 0x01410109, /* pswwr, k2, 9 lines */
3866		− 0x00000000,
3867		− 0x00000000, /* pswwr2, bb, 0 lines */
3868		− 0x00000000, /* pswwr2, k2, 0 lines */
3869		− 0x00000000,
3870		− 0x001c0001, /* pswrq, bb, 1 lines */
3871		− 0x001c0001, /* pswrq, k2, 1 lines */
3872		− 0x00000000,
3873		− 0x014a0015, /* pswrq2, bb, 21 lines */
3874		− 0x014a0015, /* pswrq2, k2, 21 lines */
3875		− 0x00000000,
3876		− 0x00000000, /* pglcs, bb, 0 lines */
3877		− 0x00120006, /* pglcs, k2, 6 lines */
3878		− 0x00000000,
3879		− 0x00100001, /* dmae, bb, 1 lines */
3880		− 0x00100001, /* dmae, k2, 1 lines */
3881		− 0x00000000,
3882		− 0x015f0105, /* ptu, bb, 5 lines */
3883		− 0x015f0105, /* ptu, k2, 5 lines */
3884		− 0x00000000,
3885		− 0x01640120, /* tcm, bb, 32 lines */
3886		− 0x01640120, /* tcm, k2, 32 lines */
3887		− 0x00000000,
3888		− 0x01640120, /* mcm, bb, 32 lines */
3889		− 0x01640120, /* mcm, k2, 32 lines */
3890		− 0x00000000,
3891		− 0x01640120, /* ucm, bb, 32 lines */
3892		− 0x01640120, /* ucm, k2, 32 lines */
3893		− 0x00000000,
3894		− 0x01640120, /* xcm, bb, 32 lines */
3895		− 0x01640120, /* xcm, k2, 32 lines */
3896		− 0x00000000,
3897		− 0x01640120, /* ycm, bb, 32 lines */
3898		− 0x01640120, /* ycm, k2, 32 lines */
3899		− 0x00000000,
3900		− 0x01640120, /* pcm, bb, 32 lines */
3901		− 0x01640120, /* pcm, k2, 32 lines */
3902		− 0x00000000,
3903		− 0x01840062, /* qm, bb, 98 lines */
3904		− 0x01840062, /* qm, k2, 98 lines */
3905		− 0x00000000,
3906		− 0x01e60021, /* tm, bb, 33 lines */
3907		− 0x01e60021, /* tm, k2, 33 lines */
3908		− 0x00000000,
3909		− 0x02070107, /* dorq, bb, 7 lines */
3910		− 0x02070107, /* dorq, k2, 7 lines */
3911		− 0x00000000,
3912		− 0x00600185, /* brb, bb, 133 lines */
3913		− 0x00600185, /* brb, k2, 133 lines */
3914		− 0x00000000,
3915		− 0x020e0019, /* src, bb, 25 lines */
3916		− 0x020c001a, /* src, k2, 26 lines */
3917		− 0x00000000,
3918		− 0x02270104, /* prs, bb, 4 lines */
3919		− 0x02270104, /* prs, k2, 4 lines */
3920		− 0x00000000,
3921		− 0x022b0133, /* tsdm, bb, 51 lines */
3922		− 0x022b0133, /* tsdm, k2, 51 lines */
3923		− 0x00000000,
3924		− 0x022b0133, /* msdm, bb, 51 lines */
3925		− 0x022b0133, /* msdm, k2, 51 lines */
3926		− 0x00000000,
3927		− 0x022b0133, /* usdm, bb, 51 lines */
3928		− 0x022b0133, /* usdm, k2, 51 lines */
3929		− 0x00000000,
3930		− 0x022b0133, /* xsdm, bb, 51 lines */
3931		− 0x022b0133, /* xsdm, k2, 51 lines */
3932		− 0x00000000,
3933		− 0x022b0133, /* ysdm, bb, 51 lines */
3934		− 0x022b0133, /* ysdm, k2, 51 lines */
3935		− 0x00000000,
3936		− 0x022b0133, /* psdm, bb, 51 lines */
3937		− 0x022b0133, /* psdm, k2, 51 lines */
3938		− 0x00000000,
3939		− 0x025e010c, /* tsem, bb, 12 lines */
3940		− 0x025e010c, /* tsem, k2, 12 lines */
3941		− 0x00000000,
3942		− 0x025e010c, /* msem, bb, 12 lines */
3943		− 0x025e010c, /* msem, k2, 12 lines */
3944		− 0x00000000,
3945		− 0x025e010c, /* usem, bb, 12 lines */
3946		− 0x025e010c, /* usem, k2, 12 lines */
3947		− 0x00000000,
3948		− 0x025e010c, /* xsem, bb, 12 lines */
3949		− 0x025e010c, /* xsem, k2, 12 lines */
3950		− 0x00000000,
3951		− 0x025e010c, /* ysem, bb, 12 lines */
3952		− 0x025e010c, /* ysem, k2, 12 lines */
3953		− 0x00000000,
3954		− 0x025e010c, /* psem, bb, 12 lines */
3955		− 0x025e010c, /* psem, k2, 12 lines */
3956		− 0x00000000,
3957		− 0x026a000d, /* rss, bb, 13 lines */
3958		− 0x026a000d, /* rss, k2, 13 lines */
3959		− 0x00000000,
3960		− 0x02770106, /* tmld, bb, 6 lines */
3961		− 0x02770106, /* tmld, k2, 6 lines */
3962		− 0x00000000,
3963		− 0x027d0106, /* muld, bb, 6 lines */
3964		− 0x027d0106, /* muld, k2, 6 lines */
3965		− 0x00000000,
3966		− 0x02770005, /* yuld, bb, 5 lines */
3967		− 0x02770005, /* yuld, k2, 5 lines */
3968		− 0x00000000,
3969		− 0x02830107, /* xyld, bb, 7 lines */
3970		− 0x027d0107, /* xyld, k2, 7 lines */
3971		− 0x00000000,
3972		− 0x00000000, /* ptld, bb, 0 lines */
3973		− 0x00000000, /* ptld, k2, 0 lines */
3974		− 0x00000000,
3975		− 0x00000000, /* ypld, bb, 0 lines */
3976		− 0x00000000, /* ypld, k2, 0 lines */
3977		− 0x00000000,
3978		− 0x028a010e, /* prm, bb, 14 lines */
3979		− 0x02980110, /* prm, k2, 16 lines */
3980		− 0x00000000,
3981		− 0x02a8000d, /* pbf_pb1, bb, 13 lines */
3982		− 0x02a8000d, /* pbf_pb1, k2, 13 lines */
3983		− 0x00000000,
3984		− 0x02a8000d, /* pbf_pb2, bb, 13 lines */
3985		− 0x02a8000d, /* pbf_pb2, k2, 13 lines */
3986		− 0x00000000,
3987		− 0x02a8000d, /* rpb, bb, 13 lines */
3988		− 0x02a8000d, /* rpb, k2, 13 lines */
3989		− 0x00000000,
3990		− 0x00600185, /* btb, bb, 133 lines */
3991		− 0x00600185, /* btb, k2, 133 lines */
3992		− 0x00000000,
3993		− 0x02b50117, /* pbf, bb, 23 lines */
3994		− 0x02b50117, /* pbf, k2, 23 lines */
3995		− 0x00000000,
3996		− 0x02cc0006, /* rdif, bb, 6 lines */
3997		− 0x02cc0006, /* rdif, k2, 6 lines */
3998		− 0x00000000,
3999		− 0x02d20006, /* tdif, bb, 6 lines */
4000		− 0x02d20006, /* tdif, k2, 6 lines */
4001		− 0x00000000,
4002		− 0x02d80003, /* cdu, bb, 3 lines */
4003		− 0x02db000e, /* cdu, k2, 14 lines */
4004		− 0x00000000,
4005		− 0x02e9010d, /* ccfc, bb, 13 lines */
4006		− 0x02f60117, /* ccfc, k2, 23 lines */
4007		− 0x00000000,
4008		− 0x02e9010d, /* tcfc, bb, 13 lines */
4009		− 0x02f60117, /* tcfc, k2, 23 lines */
4010		− 0x00000000,
4011		− 0x030d0133, /* igu, bb, 51 lines */
4012		− 0x030d0133, /* igu, k2, 51 lines */
4013		− 0x00000000,
4014		− 0x03400106, /* cau, bb, 6 lines */
4015		− 0x03400106, /* cau, k2, 6 lines */
4016		− 0x00000000,
4017		− 0x00000000, /* rgfs, bb, 0 lines */
4018		− 0x00000000, /* rgfs, k2, 0 lines */
4019		− 0x00000000,
4020		− 0x00000000, /* rgsrc, bb, 0 lines */
4021		− 0x00000000, /* rgsrc, k2, 0 lines */
4022		− 0x00000000,
4023		− 0x00000000, /* tgfs, bb, 0 lines */
4024		− 0x00000000, /* tgfs, k2, 0 lines */
4025		− 0x00000000,
4026		− 0x00000000, /* tgsrc, bb, 0 lines */
4027		− 0x00000000, /* tgsrc, k2, 0 lines */
4028		− 0x00000000,
4029		− 0x00000000, /* umac, bb, 0 lines */
4030		− 0x00120006, /* umac, k2, 6 lines */
4031		− 0x00000000,
4032		− 0x00000000, /* xmac, bb, 0 lines */
4033		− 0x00000000, /* xmac, k2, 0 lines */
4034		− 0x00000000,
4035		− 0x00000000, /* dbg, bb, 0 lines */
4036		− 0x00000000, /* dbg, k2, 0 lines */
4037		− 0x00000000,
4038		− 0x0346012b, /* nig, bb, 43 lines */
4039		− 0x0346011d, /* nig, k2, 29 lines */
4040		− 0x00000000,
4041		− 0x00000000, /* wol, bb, 0 lines */
4042		− 0x001c0002, /* wol, k2, 2 lines */
4043		− 0x00000000,
4044		− 0x00000000, /* bmbn, bb, 0 lines */
4045		− 0x00210008, /* bmbn, k2, 8 lines */
4046		− 0x00000000,
4047		− 0x00000000, /* ipc, bb, 0 lines */
4048		− 0x00000000, /* ipc, k2, 0 lines */
4049		− 0x00000000,
4050		− 0x00000000, /* nwm, bb, 0 lines */
4051		− 0x0371000b, /* nwm, k2, 11 lines */
4052		− 0x00000000,
4053		− 0x00000000, /* nws, bb, 0 lines */
4054		− 0x037c0009, /* nws, k2, 9 lines */
4055		− 0x00000000,
4056		− 0x00000000, /* ms, bb, 0 lines */
4057		− 0x00120004, /* ms, k2, 4 lines */
4058		− 0x00000000,
4059		− 0x00000000, /* phy_pcie, bb, 0 lines */
4060		− 0x00e5001a, /* phy_pcie, k2, 26 lines */
4061		− 0x00000000,
4062		− 0x00000000, /* led, bb, 0 lines */
4063		− 0x00000000, /* led, k2, 0 lines */
4064		− 0x00000000,
4065		− 0x00000000, /* avs_wrap, bb, 0 lines */
4066		− 0x00000000, /* avs_wrap, k2, 0 lines */
4067		− 0x00000000,
4068		− 0x00000000, /* bar0_map, bb, 0 lines */
4069		− 0x00000000, /* bar0_map, k2, 0 lines */
4070		− 0x00000000,
4071		− 0x00000000, /* bar0_map, bb, 0 lines */
4072		− 0x00000000, /* bar0_map, k2, 0 lines */
4073		− 0x00000000,
4074		−};
4075		−
4076	3737	/* Win 2 */
4077	3738	#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
4078	3739
@@ -4086,22 +3747,28 @@ static const u32 dbg_bus_blocks[] = { · 7 unmodified lines
4086	3747	#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
4087	3748
4088	3749	/* Win 6 */
4089		−#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
	3750	+#define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL
4090	3751
4091	3752	/* Win 7 */
4092		−#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
	3753	+#define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL
4093	3754
4094	3755	/* Win 8 */
4095		−#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
	3756	+#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL
4096	3757
4097	3758	/* Win 9 */
4098		−#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
	3759	+#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL
4099	3760
4100	3761	/* Win 10 */
4101		−#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
	3762	+#define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL
4102	3763
4103	3764	/* Win 11 */
4104		−#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
	3765	+#define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL
	3766	+
	3767	+/* Win 12 */
	3768	+#define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL
	3769	+
	3770	+/* Win 13 */
	3771	+#define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL
4105	3772
4106	3773	/**
4107	3774	* @brief qed_qm_pf_mem_size - prepare QM ILT sizes
@@ -11913,7 +11580,7 @@ struct e4_ystorm_iscsi_conn_ag_ctx { · 7805 unmodified lines
11913	11580	/* The trace in the buffer */
11914	11581	#define MFW_TRACE_EVENTID_MASK 0x00ffff
11915	11582	#define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
11916		−#define MFW_TRACE_PRM_SIZE_SHIFT 16
	11583	+#define MFW_TRACE_PRM_SIZE_OFFSET 16
11917	11584	#define MFW_TRACE_ENTRY_SIZE 3
11918	11585
11919	11586	struct mcp_trace {
@@ -12866,7 +12533,10 @@ struct public_drv_mb { · 946 unmodified lines
12866	12533	#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
12867	12534
12868	12535	#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI 0x3
	12536	+#define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
	12537	+#define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
12869	12538	#define DRV_MB_PARAM_NVM_LEN_OFFSET 24
	12539	+#define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
12870	12540
12871	12541	#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
12872	12542	#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
@@ -13627,6 +13297,21 @@ enum nvm_image_type { · 754 unmodified lines
13627	13297	NVM_TYPE_FCOE_CFG = 0x1f,
13628	13298	NVM_TYPE_ETH_PHY_FW1 = 0x20,
13629	13299	NVM_TYPE_ETH_PHY_FW2 = 0x21,
	13300	+ NVM_TYPE_BDN = 0x22,
	13301	+ NVM_TYPE_8485X_PHY_FW = 0x23,
	13302	+ NVM_TYPE_PUB_KEY = 0x24,
	13303	+ NVM_TYPE_RECOVERY = 0x25,
	13304	+ NVM_TYPE_PLDM = 0x26,
	13305	+ NVM_TYPE_UPK1 = 0x27,
	13306	+ NVM_TYPE_UPK2 = 0x28,
	13307	+ NVM_TYPE_MASTER_KC = 0x29,
	13308	+ NVM_TYPE_BACKUP_KC = 0x2a,
	13309	+ NVM_TYPE_HW_DUMP = 0x2b,
	13310	+ NVM_TYPE_HW_DUMP_OUT = 0x2c,
	13311	+ NVM_TYPE_BIN_NVM_META = 0x30,
	13312	+ NVM_TYPE_ROM_TEST = 0xf0,
	13313	+ NVM_TYPE_88X33X0_PHY_FW = 0x31,
	13314	+ NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
13630	13315	NVM_TYPE_MAX,
13631	13316	};
13632	13317

drivers/net/ethernet/qlogic/qed/qed_main.c+1−1

@@ -2637,7 +2637,7 @@ static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val) · 2636 unmodified lines
2637	2637	if (!ptt)
2638	2638	return -EAGAIN;
2639	2639
2640		− rc = qed_dbg_grc_config(hwfn, ptt, cfg_id, val);
	2640	+ rc = qed_dbg_grc_config(hwfn, cfg_id, val);
2641	2641
2642	2642	qed_ptt_release(hwfn, ptt);
2643	2643

include/linux/qed/qed_if.h+9−0

@@ -1178,6 +1178,15 @@ struct qed_common_ops { · 1177 unmodified lines
1178	1178	#define GET_FIELD(value, name) \
1179	1179	(((value) >> (name ## _SHIFT)) & name ## _MASK)
1180	1180
	1181	+#define GET_MFW_FIELD(name, field) \
	1182	+ (((name) & (field ## _MASK)) >> (field ## _OFFSET))
	1183	+
	1184	+#define SET_MFW_FIELD(name, field, value) \
	1185	+ do { \
	1186	+ (name) &= ~(field ## _MASK); \
	1187	+ (name) \|= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
	1188	+ } while (0)
	1189	+
1181	1190	#define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1182	1191
1183	1192	/* Debug print definitions */