History

Merge tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner: "Updates for the interrupt subsystem: Treewide: - Cleanup of setup_irq() which is not longer required because the memory allocator is available early. Most cleanup changes come through the various maintainer trees, so the final removal of setup_irq() is postponed towards the end of the merge window. Core: - Protection against unsafe invocation of interrupt handlers and unsafe interrupt injection including a fixup of the offending PCI/AER error injection mechanism. Invoking interrupt handlers from arbitrary contexts, i.e. outside of an actual interrupt, can cause inconsistent state on the fragile x86 interrupt affinity changing hardware trainwreck. Drivers: - Second wave of support for the new ARM GICv4.1 - Multi-instance support for Xilinx and PLIC interrupt controllers - CPU-Hotplug support for PLIC - The obligatory new driver for X1000 TCU - Enhancements, cleanups and fixes all over the place" * tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (58 commits) unicore32: Replace setup_irq() by request_irq() sh: Replace setup_irq() by request_irq() hexagon: Replace setup_irq() by request_irq() c6x: Replace setup_irq() by request_irq() alpha: Replace setup_irq() by request_irq() irqchip/gic-v4.1: Eagerly vmap vPEs irqchip/gic-v4.1: Add VSGI property setup irqchip/gic-v4.1: Add VSGI allocation/teardown irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer irqchip/gic-v4.1: Plumb set_vcpu_affinity SGI callbacks irqchip/gic-v4.1: Plumb get/set_irqchip_state SGI callbacks irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks irqchip/gic-v4.1: Add initial SGI configuration irqchip/gic-v4.1: Plumb skeletal VSGI irqchip irqchip/stm32: Retrigger both in eoi and unmask callbacks irqchip/gic-v3: Move irq_domain_update_bus_token to after checking for NULL domain irqchip/xilinx: Do not call irq_set_default_host() irqchip/xilinx: Enable generic irq multi handler irqchip/xilinx: Fill error code when irq domain registration fails irqchip/xilinx: Add support for multiple instances ...

Linus Torvalds committed 6 years ago

Commit 2d385332 parents 673b41e 8a13b0264 files · +1185 −420Browse files

Showing the changes to include/linux (6 of 64 files). Show all

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6 files
  1. include/linux/cpuhotplug.h +1 −0
  2. include/linux/interrupt.h +2 −0
  3. include/linux/irq.h +13 −0
  4. include/linux/irqchip/arm-gic-common.h +2 −0
  5. include/linux/irqchip/arm-gic-v3.h +22 −1
  6. include/linux/irqchip/arm-gic-v4.h +23 −2
include/linux/cpuhotplug.h+1−0
@@ -102,6 +102,7 @@ enum cpuhp_state { · 101 unmodified lines
102 CPUHP_AP_IRQ_ARMADA_XP_STARTING,102 CPUHP_AP_IRQ_ARMADA_XP_STARTING,
103 CPUHP_AP_IRQ_BCM2836_STARTING,103 CPUHP_AP_IRQ_BCM2836_STARTING,
104 CPUHP_AP_IRQ_MIPS_GIC_STARTING,104 CPUHP_AP_IRQ_MIPS_GIC_STARTING,
105 CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
105 CPUHP_AP_ARM_MVEBU_COHERENCY,106 CPUHP_AP_ARM_MVEBU_COHERENCY,
106 CPUHP_AP_MICROCODE_LOADER,107 CPUHP_AP_MICROCODE_LOADER,
107 CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,108 CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,
include/linux/interrupt.h+2−0
@@ -248,6 +248,8 @@ extern void enable_percpu_nmi(unsigned int irq, unsigned int type); · 247 unmodified lines
248extern int prepare_percpu_nmi(unsigned int irq);248extern int prepare_percpu_nmi(unsigned int irq);
249extern void teardown_percpu_nmi(unsigned int irq);249extern void teardown_percpu_nmi(unsigned int irq);
250 250
251extern int irq_inject_interrupt(unsigned int irq);
252
251/* The following three functions are for the core kernel use only. */253/* The following three functions are for the core kernel use only. */
252extern void suspend_device_irqs(void);254extern void suspend_device_irqs(void);
253extern void resume_device_irqs(void);255extern void resume_device_irqs(void);
include/linux/irq.h+13−0
@@ -211,6 +211,8 @@ struct irq_data { · 210 unmodified lines
211 * IRQD_CAN_RESERVE - Can use reservation mode211 * IRQD_CAN_RESERVE - Can use reservation mode
212 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change212 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
213 * required213 * required
214 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
215 * from actual interrupt context.
214 */216 */
215enum {217enum {
216 IRQD_TRIGGER_MASK = 0xf,218 IRQD_TRIGGER_MASK = 0xf,
@@ -234,6 +236,7 @@ enum { · 17 unmodified lines
234 IRQD_DEFAULT_TRIGGER_SET = (1 << 25),236 IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
235 IRQD_CAN_RESERVE = (1 << 26),237 IRQD_CAN_RESERVE = (1 << 26),
236 IRQD_MSI_NOMASK_QUIRK = (1 << 27),238 IRQD_MSI_NOMASK_QUIRK = (1 << 27),
239 IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28),
237};240};
238 241
239#define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)242#define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
@@ -303,6 +306,16 @@ static inline bool irqd_is_single_target(struct irq_data *d) · 63 unmodified lines
303 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;306 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
304}307}
305 308
309static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
310{
311 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
312}
313
314static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
315{
316 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
317}
318
306static inline bool irqd_is_wakeup_set(struct irq_data *d)319static inline bool irqd_is_wakeup_set(struct irq_data *d)
307{320{
308 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;321 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
include/linux/irqchip/arm-gic-common.h+2−0
@@ -32,6 +32,8 @@ struct gic_kvm_info { · 31 unmodified lines
32 struct resource vctrl;32 struct resource vctrl;
33 /* vlpi support */33 /* vlpi support */
34 bool has_v4;34 bool has_v4;
35 /* rvpeid support */
36 bool has_v4_1;
35};37};
36 38
37const struct gic_kvm_info *gic_get_kvm_info(void);39const struct gic_kvm_info *gic_get_kvm_info(void);
include/linux/irqchip/arm-gic-v3.h+22−1
@@ -57,6 +57,7 @@ · 56 unmodified lines
57#define GICD_SPENDSGIR 0x0F2057#define GICD_SPENDSGIR 0x0F20
58 58
59#define GICD_CTLR_RWP (1U << 31)59#define GICD_CTLR_RWP (1U << 31)
60#define GICD_CTLR_nASSGIreq (1U << 8)
60#define GICD_CTLR_DS (1U << 6)61#define GICD_CTLR_DS (1U << 6)
61#define GICD_CTLR_ARE_NS (1U << 4)62#define GICD_CTLR_ARE_NS (1U << 4)
62#define GICD_CTLR_ENABLE_G1A (1U << 1)63#define GICD_CTLR_ENABLE_G1A (1U << 1)
@@ -90,6 +91,7 @@ · 27 unmodified lines
90#define GICD_TYPER_ESPIS(typer) \91#define GICD_TYPER_ESPIS(typer) \
91 (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)92 (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
92 93
94#define GICD_TYPER2_nASSGIcap (1U << 8)
93#define GICD_TYPER2_VIL (1U << 7)95#define GICD_TYPER2_VIL (1U << 7)
94#define GICD_TYPER2_VID GENMASK(4, 0)96#define GICD_TYPER2_VID GENMASK(4, 0)
95 97
@@ -320,6 +322,9 @@ · 224 unmodified lines
320#define GICR_VPENDBASER_NonShareable \322#define GICR_VPENDBASER_NonShareable \
321 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)323 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
322 324
325#define GICR_VPENDBASER_InnerShareable \
326 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable)
327
323#define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)328#define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
324#define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)329#define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
325#define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)330#define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
@@ -343,6 +348,15 @@ · 17 unmodified lines
343#define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58)348#define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58)
344#define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0)349#define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0)
345 350
351#define GICR_VSGIR 0x0080
352
353#define GICR_VSGIR_VPEID GENMASK(15, 0)
354
355#define GICR_VSGIPENDR 0x0088
356
357#define GICR_VSGIPENDR_BUSY (1U << 31)
358#define GICR_VSGIPENDR_PENDING GENMASK(15, 0)
359
346/*360/*
347 * ITS registers, offsets from ITS_base361 * ITS registers, offsets from ITS_base
348 */362 */
@@ -366,6 +380,11 @@ · 17 unmodified lines
366 380
367#define GITS_TRANSLATER 0x10040381#define GITS_TRANSLATER 0x10040
368 382
383#define GITS_SGIR 0x20020
384
385#define GITS_SGIR_VPEID GENMASK_ULL(47, 32)
386#define GITS_SGIR_VINTID GENMASK_ULL(3, 0)
387
369#define GITS_CTLR_ENABLE (1U << 0)388#define GITS_CTLR_ENABLE (1U << 0)
370#define GITS_CTLR_ImDe (1U << 1)389#define GITS_CTLR_ImDe (1U << 1)
371#define GITS_CTLR_ITS_NUMBER_SHIFT 4390#define GITS_CTLR_ITS_NUMBER_SHIFT 4
@@ -500,8 +519,9 @@ · 128 unmodified lines
500#define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI)519#define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI)
501#define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI)520#define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI)
502#define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC)521#define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC)
503/* VMOVP and INVDB are the odd ones, as they dont have a physical counterpart */522/* VMOVP, VSGI and INVDB are the odd ones, as they dont have a physical counterpart */
504#define GITS_CMD_VMOVP GITS_CMD_GICv4(2)523#define GITS_CMD_VMOVP GITS_CMD_GICv4(2)
524#define GITS_CMD_VSGI GITS_CMD_GICv4(3)
505#define GITS_CMD_INVDB GITS_CMD_GICv4(0xe)525#define GITS_CMD_INVDB GITS_CMD_GICv4(0xe)
506 526
507/*527/*
@@ -650,6 +670,7 @@ · 142 unmodified lines
650 670
651struct rdists {671struct rdists {
652 struct {672 struct {
673 raw_spinlock_t rd_lock;
653 void __iomem *rd_base;674 void __iomem *rd_base;
654 struct page *pend_page;675 struct page *pend_page;
655 phys_addr_t phys_base;676 phys_addr_t phys_base;
include/linux/irqchip/arm-gic-v4.h+23−2
@@ -49,10 +49,22 @@ struct its_vpe { · 48 unmodified lines
49 };49 };
50 /* GICv4.1 implementations */50 /* GICv4.1 implementations */
51 struct {51 struct {
52 struct fwnode_handle *fwnode;
53 struct irq_domain *sgi_domain;
54 struct {
55 u8 priority;
56 bool enabled;
57 bool group;
58 } sgi_config[16];
52 atomic_t vmapp_count;59 atomic_t vmapp_count;
53 };60 };
54 };61 };
55 62
63 /*
64 * Ensures mutual exclusion between affinity setting of the
65 * vPE and vLPI operations using vpe->col_idx.
66 */
67 raw_spinlock_t vpe_lock;
56 /*68 /*
57 * This collection ID is used to indirect the target69 * This collection ID is used to indirect the target
58 * redistributor for this VPE. The ID itself isn't involved in70 * redistributor for this VPE. The ID itself isn't involved in
@@ -93,6 +105,7 @@ enum its_vcpu_info_cmd_type { · 34 unmodified lines
93 SCHEDULE_VPE,105 SCHEDULE_VPE,
94 DESCHEDULE_VPE,106 DESCHEDULE_VPE,
95 INVALL_VPE,107 INVALL_VPE,
108 PROP_UPDATE_VSGI,
96};109};
97 110
98struct its_cmd_info {111struct its_cmd_info {
@@ -105,19 +118,27 @@ struct its_cmd_info { · 6 unmodified lines
105 bool g0en;118 bool g0en;
106 bool g1en;119 bool g1en;
107 };120 };
121 struct {
122 u8 priority;
123 bool group;
124 };
108 };125 };
109};126};
110 127
111int its_alloc_vcpu_irqs(struct its_vm *vm);128int its_alloc_vcpu_irqs(struct its_vm *vm);
112void its_free_vcpu_irqs(struct its_vm *vm);129void its_free_vcpu_irqs(struct its_vm *vm);
113int its_schedule_vpe(struct its_vpe *vpe, bool on);130int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en);
131int its_make_vpe_non_resident(struct its_vpe *vpe, bool db);
114int its_invall_vpe(struct its_vpe *vpe);132int its_invall_vpe(struct its_vpe *vpe);
115int its_map_vlpi(int irq, struct its_vlpi_map *map);133int its_map_vlpi(int irq, struct its_vlpi_map *map);
116int its_get_vlpi(int irq, struct its_vlpi_map *map);134int its_get_vlpi(int irq, struct its_vlpi_map *map);
117int its_unmap_vlpi(int irq);135int its_unmap_vlpi(int irq);
118int its_prop_update_vlpi(int irq, u8 config, bool inv);136int its_prop_update_vlpi(int irq, u8 config, bool inv);
137int its_prop_update_vsgi(int irq, u8 priority, bool group);
119 138
120struct irq_domain_ops;139struct irq_domain_ops;
121int its_init_v4(struct irq_domain *domain, const struct irq_domain_ops *ops);140int its_init_v4(struct irq_domain *domain,
141 const struct irq_domain_ops *vpe_ops,
142 const struct irq_domain_ops *sgi_ops);
122 143
123#endif144#endif

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