Merge tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner: "Updates for the interrupt subsystem: Treewide: - Cleanup of setup_irq() which is not longer required because the memory allocator is available early. Most cleanup changes come through the various maintainer trees, so the final removal of setup_irq() is postponed towards the end of the merge window. Core: - Protection against unsafe invocation of interrupt handlers and unsafe interrupt injection including a fixup of the offending PCI/AER error injection mechanism. Invoking interrupt handlers from arbitrary contexts, i.e. outside of an actual interrupt, can cause inconsistent state on the fragile x86 interrupt affinity changing hardware trainwreck. Drivers: - Second wave of support for the new ARM GICv4.1 - Multi-instance support for Xilinx and PLIC interrupt controllers - CPU-Hotplug support for PLIC - The obligatory new driver for X1000 TCU - Enhancements, cleanups and fixes all over the place" * tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (58 commits) unicore32: Replace setup_irq() by request_irq() sh: Replace setup_irq() by request_irq() hexagon: Replace setup_irq() by request_irq() c6x: Replace setup_irq() by request_irq() alpha: Replace setup_irq() by request_irq() irqchip/gic-v4.1: Eagerly vmap vPEs irqchip/gic-v4.1: Add VSGI property setup irqchip/gic-v4.1: Add VSGI allocation/teardown irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer irqchip/gic-v4.1: Plumb set_vcpu_affinity SGI callbacks irqchip/gic-v4.1: Plumb get/set_irqchip_state SGI callbacks irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks irqchip/gic-v4.1: Add initial SGI configuration irqchip/gic-v4.1: Plumb skeletal VSGI irqchip irqchip/stm32: Retrigger both in eoi and unmask callbacks irqchip/gic-v3: Move irq_domain_update_bus_token to after checking for NULL domain irqchip/xilinx: Do not call irq_set_default_host() irqchip/xilinx: Enable generic irq multi handler irqchip/xilinx: Fill error code when irq domain registration fails irqchip/xilinx: Add support for multiple instances ...

Linus Torvalds committed 6 years ago

Commit 2d385332 parents 673b41e 8a13b0264 files · +1185 −420Browse files

Showing the changes to include/linux (6 of 64 files). Show all

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6 files

include/linux/cpuhotplug.h +1 −0
include/linux/interrupt.h +2 −0
include/linux/irq.h +13 −0
include/linux/irqchip/arm-gic-common.h +2 −0
include/linux/irqchip/arm-gic-v3.h +22 −1
include/linux/irqchip/arm-gic-v4.h +23 −2

include/linux/cpuhotplug.h+1−0

@@ -102,6 +102,7 @@ enum cpuhp_state { · 101 unmodified lines
102	102	CPUHP_AP_IRQ_ARMADA_XP_STARTING,
103	103	CPUHP_AP_IRQ_BCM2836_STARTING,
104	104	CPUHP_AP_IRQ_MIPS_GIC_STARTING,
	105	+ CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
105	106	CPUHP_AP_ARM_MVEBU_COHERENCY,
106	107	CPUHP_AP_MICROCODE_LOADER,
107	108	CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,

include/linux/interrupt.h+2−0

@@ -248,6 +248,8 @@ extern void enable_percpu_nmi(unsigned int irq, unsigned int type); · 247 unmodified lines
248	248	extern int prepare_percpu_nmi(unsigned int irq);
249	249	extern void teardown_percpu_nmi(unsigned int irq);
250	250
	251	+extern int irq_inject_interrupt(unsigned int irq);
	252	+
251	253	/* The following three functions are for the core kernel use only. */
252	254	extern void suspend_device_irqs(void);
253	255	extern void resume_device_irqs(void);

include/linux/irq.h+13−0

@@ -211,6 +211,8 @@ struct irq_data { · 210 unmodified lines
211	211	* IRQD_CAN_RESERVE - Can use reservation mode
212	212	* IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
213	213	* required
	214	+ * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
	215	+ * from actual interrupt context.
214	216	*/
215	217	enum {
216	218	IRQD_TRIGGER_MASK = 0xf,
@@ -234,6 +236,7 @@ enum { · 17 unmodified lines
234	236	IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
235	237	IRQD_CAN_RESERVE = (1 << 26),
236	238	IRQD_MSI_NOMASK_QUIRK = (1 << 27),
	239	+ IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28),
237	240	};
238	241
239	242	#define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
@@ -303,6 +306,16 @@ static inline bool irqd_is_single_target(struct irq_data *d) · 63 unmodified lines
303	306	return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
304	307	}
305	308
	309	+static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
	310	+{
	311	+ __irqd_to_state(d) \|= IRQD_HANDLE_ENFORCE_IRQCTX;
	312	+}
	313	+
	314	+static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
	315	+{
	316	+ return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
	317	+}
	318	+
306	319	static inline bool irqd_is_wakeup_set(struct irq_data *d)
307	320	{
308	321	return __irqd_to_state(d) & IRQD_WAKEUP_STATE;

include/linux/irqchip/arm-gic-common.h+2−0

@@ -32,6 +32,8 @@ struct gic_kvm_info { · 31 unmodified lines
32	32	struct resource vctrl;
33	33	/* vlpi support */
34	34	bool has_v4;
	35	+ /* rvpeid support */
	36	+ bool has_v4_1;
35	37	};
36	38
37	39	const struct gic_kvm_info *gic_get_kvm_info(void);

include/linux/irqchip/arm-gic-v3.h+22−1

@@ -57,6 +57,7 @@ · 56 unmodified lines
57	57	#define GICD_SPENDSGIR 0x0F20
58	58
59	59	#define GICD_CTLR_RWP (1U << 31)
	60	+#define GICD_CTLR_nASSGIreq (1U << 8)
60	61	#define GICD_CTLR_DS (1U << 6)
61	62	#define GICD_CTLR_ARE_NS (1U << 4)
62	63	#define GICD_CTLR_ENABLE_G1A (1U << 1)
@@ -90,6 +91,7 @@ · 27 unmodified lines
90	91	#define GICD_TYPER_ESPIS(typer) \
91	92	(((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
92	93
	94	+#define GICD_TYPER2_nASSGIcap (1U << 8)
93	95	#define GICD_TYPER2_VIL (1U << 7)
94	96	#define GICD_TYPER2_VID GENMASK(4, 0)
95	97
@@ -320,6 +322,9 @@ · 224 unmodified lines
320	322	#define GICR_VPENDBASER_NonShareable \
321	323	GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
322	324
	325	+#define GICR_VPENDBASER_InnerShareable \
	326	+ GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable)
	327	+
323	328	#define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
324	329	#define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
325	330	#define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
@@ -343,6 +348,15 @@ · 17 unmodified lines
343	348	#define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58)
344	349	#define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0)
345	350
	351	+#define GICR_VSGIR 0x0080
	352	+
	353	+#define GICR_VSGIR_VPEID GENMASK(15, 0)
	354	+
	355	+#define GICR_VSGIPENDR 0x0088
	356	+
	357	+#define GICR_VSGIPENDR_BUSY (1U << 31)
	358	+#define GICR_VSGIPENDR_PENDING GENMASK(15, 0)
	359	+
346	360	/*
347	361	* ITS registers, offsets from ITS_base
348	362	*/
@@ -366,6 +380,11 @@ · 17 unmodified lines
366	380
367	381	#define GITS_TRANSLATER 0x10040
368	382
	383	+#define GITS_SGIR 0x20020
	384	+
	385	+#define GITS_SGIR_VPEID GENMASK_ULL(47, 32)
	386	+#define GITS_SGIR_VINTID GENMASK_ULL(3, 0)
	387	+
369	388	#define GITS_CTLR_ENABLE (1U << 0)
370	389	#define GITS_CTLR_ImDe (1U << 1)
371	390	#define GITS_CTLR_ITS_NUMBER_SHIFT 4
@@ -500,8 +519,9 @@ · 128 unmodified lines
500	519	#define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI)
501	520	#define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI)
502	521	#define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC)
503		−/* VMOVP and INVDB are the odd ones, as they dont have a physical counterpart */
	522	+/* VMOVP, VSGI and INVDB are the odd ones, as they dont have a physical counterpart */
504	523	#define GITS_CMD_VMOVP GITS_CMD_GICv4(2)
	524	+#define GITS_CMD_VSGI GITS_CMD_GICv4(3)
505	525	#define GITS_CMD_INVDB GITS_CMD_GICv4(0xe)
506	526
507	527	/*
@@ -650,6 +670,7 @@ · 142 unmodified lines
650	670
651	671	struct rdists {
652	672	struct {
	673	+ raw_spinlock_t rd_lock;
653	674	void __iomem *rd_base;
654	675	struct page *pend_page;
655	676	phys_addr_t phys_base;

include/linux/irqchip/arm-gic-v4.h+23−2

@@ -49,10 +49,22 @@ struct its_vpe { · 48 unmodified lines
49	49	};
50	50	/* GICv4.1 implementations */
51	51	struct {
	52	+ struct fwnode_handle *fwnode;
	53	+ struct irq_domain *sgi_domain;
	54	+ struct {
	55	+ u8 priority;
	56	+ bool enabled;
	57	+ bool group;
	58	+ } sgi_config[16];
52	59	atomic_t vmapp_count;
53	60	};
54	61	};
55	62
	63	+ /*
	64	+ * Ensures mutual exclusion between affinity setting of the
	65	+ * vPE and vLPI operations using vpe->col_idx.
	66	+ */
	67	+ raw_spinlock_t vpe_lock;
56	68	/*
57	69	* This collection ID is used to indirect the target
58	70	* redistributor for this VPE. The ID itself isn't involved in
@@ -93,6 +105,7 @@ enum its_vcpu_info_cmd_type { · 34 unmodified lines
93	105	SCHEDULE_VPE,
94	106	DESCHEDULE_VPE,
95	107	INVALL_VPE,
	108	+ PROP_UPDATE_VSGI,
96	109	};
97	110
98	111	struct its_cmd_info {
@@ -105,19 +118,27 @@ struct its_cmd_info { · 6 unmodified lines
105	118	bool g0en;
106	119	bool g1en;
107	120	};
	121	+ struct {
	122	+ u8 priority;
	123	+ bool group;
	124	+ };
108	125	};
109	126	};
110	127
111	128	int its_alloc_vcpu_irqs(struct its_vm *vm);
112	129	void its_free_vcpu_irqs(struct its_vm *vm);
113		−int its_schedule_vpe(struct its_vpe *vpe, bool on);
	130	+int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en);
	131	+int its_make_vpe_non_resident(struct its_vpe *vpe, bool db);
114	132	int its_invall_vpe(struct its_vpe *vpe);
115	133	int its_map_vlpi(int irq, struct its_vlpi_map *map);
116	134	int its_get_vlpi(int irq, struct its_vlpi_map *map);
117	135	int its_unmap_vlpi(int irq);
118	136	int its_prop_update_vlpi(int irq, u8 config, bool inv);
	137	+int its_prop_update_vsgi(int irq, u8 priority, bool group);
119	138
120	139	struct irq_domain_ops;
121		−int its_init_v4(struct irq_domain domain, const struct irq_domain_ops ops);
	140	+int its_init_v4(struct irq_domain *domain,
	141	+ const struct irq_domain_ops *vpe_ops,
	142	+ const struct irq_domain_ops *sgi_ops);
122	143
123	144	#endif

Merge tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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