History

Merge tag 'perf-urgent-2023-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Thomas Gleixner: "A small set of perf fixes: - Make the MSR-readout based CHA discovery work around broken discovery tables in some SPR firmwares. - Prevent saving PEBS configuration which has software bits set that cause a crash when restored into the relevant MSR" * tag 'perf-urgent-2023-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/uncore: Correct the number of CHAs on SPR perf/x86/intel: Save/restore cpuc->active_pebs_data_cfg when using guest PEBS

Linus Torvalds committed 3 years ago

Commit 2d5438f2 parents abbf7fa 38776cc2 files · +12 −1Browse files

Unified · Split

2 files
  1. arch/x86/events/intel/core.c +1 −1
  2. arch/x86/events/intel/uncore_snbep.c +11 −0
arch/x86/events/intel/core.c+1−1
@@ -4074,7 +4074,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) · 4073 unmodified lines
4074 if (x86_pmu.intel_cap.pebs_baseline) {4074 if (x86_pmu.intel_cap.pebs_baseline) {
4075 arr[(*nr)++] = (struct perf_guest_switch_msr){4075 arr[(*nr)++] = (struct perf_guest_switch_msr){
4076 .msr = MSR_PEBS_DATA_CFG,4076 .msr = MSR_PEBS_DATA_CFG,
4077 .host = cpuc->pebs_data_cfg,4077 .host = cpuc->active_pebs_data_cfg,
4078 .guest = kvm_pmu->pebs_data_cfg,4078 .guest = kvm_pmu->pebs_data_cfg,
4079 };4079 };
4080 }4080 }
arch/x86/events/intel/uncore_snbep.c+11−0
@@ -6150,6 +6150,7 @@ static struct intel_uncore_type spr_uncore_mdf = { · 6149 unmodified lines
6150};6150};
6151 6151
6152#define UNCORE_SPR_NUM_UNCORE_TYPES 126152#define UNCORE_SPR_NUM_UNCORE_TYPES 12
6153#define UNCORE_SPR_CHA 0
6153#define UNCORE_SPR_IIO 16154#define UNCORE_SPR_IIO 1
6154#define UNCORE_SPR_IMC 66155#define UNCORE_SPR_IMC 6
6155#define UNCORE_SPR_UPI 86156#define UNCORE_SPR_UPI 8
@@ -6460,12 +6461,22 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types, · 304 unmodified lines
6460 return max + 1;6461 return max + 1;
6461}6462}
6462 6463
6464#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE
6465
6463void spr_uncore_cpu_init(void)6466void spr_uncore_cpu_init(void)
6464{6467{
6468 struct intel_uncore_type *type;
6469 u64 num_cbo;
6470
6465 uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,6471 uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
6466 UNCORE_SPR_MSR_EXTRA_UNCORES,6472 UNCORE_SPR_MSR_EXTRA_UNCORES,
6467 spr_msr_uncores);6473 spr_msr_uncores);
6468 6474
6475 type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
6476 if (type) {
6477 rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
6478 type->num_boxes = num_cbo;
6479 }
6469 spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);6480 spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
6470}6481}
6471 6482