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powerpc/powernv: use the generic iommu bypass code

Use the generic iommu bypass code instead of overriding set_dma_mask.

Christoph Hellwig committed 7 years ago

Commit 2d6ad411 parent 6248ac91 file · +25 −70Browse files

Unified · Split

arch/powerpc/platforms/powernv/pci-ioda.c+25−70
@@ -1825,89 +1825,45 @@ err: · 1824 unmodified lines
18251825 return -EIO;
18261826 }
18271827
1828−static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1828+static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1829+ u64 dma_mask)
18291830 {
18301831 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
18311832 struct pnv_phb *phb = hose->private_data;
18321833 struct pci_dn *pdn = pci_get_pdn(pdev);
18331834 struct pnv_ioda_pe *pe;
1834− uint64_t top;
1835− bool bypass = false;
1836− s64 rc;
18371835
18381836 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
18391837 return -ENODEV;
18401838
18411839 pe = &phb->ioda.pe_array[pdn->pe_number];
18421840 if (pe->tce_bypass_enabled) {
1843− top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1844− bypass = (dma_mask >= top);
1841+ u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1842+ if (dma_mask >= top)
1843+ return true;
18451844 }
18461845
1847− if (bypass) {
1848− dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1849− set_dma_ops(&pdev->dev, &dma_nommu_ops);
1850− } else {
1851− /*
1852− * If the device can't set the TCE bypass bit but still wants
1853− * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1854− * bypass the 32-bit region and be usable for 64-bit DMAs.
1855− * The device needs to be able to address all of this space.
1856− */
1857− if (dma_mask >> 32 &&
1858− dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1859− /* pe->pdev should be set if it's a single device, pe->pbus if not */
1860− (pe->device_count == 1 || !pe->pbus) &&
1861− phb->model == PNV_PHB_MODEL_PHB3) {
1862− /* Configure the bypass mode */
1863− rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1864− if (rc)
1865− return rc;
1866− /* 4GB offset bypasses 32-bit space */
1867− set_dma_offset(&pdev->dev, (1ULL << 32));
1868− set_dma_ops(&pdev->dev, &dma_nommu_ops);
1869− } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1870− /*
1871− * Fail the request if a DMA mask between 32 and 64 bits
1872− * was requested but couldn't be fulfilled. Ideally we
1873− * would do this for 64-bits but historically we have
1874− * always fallen back to 32-bits.
1875− */
1876− return -ENOMEM;
1877− } else {
1878− dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1879− set_dma_ops(&pdev->dev, &dma_iommu_ops);
1880− }
1846+ /*
1847+ * If the device can't set the TCE bypass bit but still wants
1848+ * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1849+ * bypass the 32-bit region and be usable for 64-bit DMAs.
1850+ * The device needs to be able to address all of this space.
1851+ */
1852+ if (dma_mask >> 32 &&
1853+ dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1854+ /* pe->pdev should be set if it's a single device, pe->pbus if not */
1855+ (pe->device_count == 1 || !pe->pbus) &&
1856+ phb->model == PNV_PHB_MODEL_PHB3) {
1857+ /* Configure the bypass mode */
1858+ s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1859+ if (rc)
1860+ return rc;
1861+ /* 4GB offset bypasses 32-bit space */
1862+ set_dma_offset(&pdev->dev, (1ULL << 32));
1863+ return true;
18811864 }
1882− *pdev->dev.dma_mask = dma_mask;
1883−
1884− /* Update peer npu devices */
1885− pnv_npu_try_dma_set_bypass(pdev, bypass);
1886−
1887− return 0;
1888−}
1889−
1890−static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1891−{
1892− struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1893− struct pnv_phb *phb = hose->private_data;
1894− struct pci_dn *pdn = pci_get_pdn(pdev);
1895− struct pnv_ioda_pe *pe;
1896− u64 end, mask;
18971865
1898− if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1899− return 0;
1900−
1901− pe = &phb->ioda.pe_array[pdn->pe_number];
1902− if (!pe->tce_bypass_enabled)
1903− return __dma_get_required_mask(&pdev->dev);
1904−
1905−
1906− end = pe->tce_bypass_base + memblock_end_of_DRAM();
1907− mask = 1ULL << (fls64(end) - 1);
1908− mask += mask - 1;
1909−
1910− return mask;
1866+ return false;
19111867 }
19121868
19131869 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
@@ -3634,6 +3590,7 @@ static void pnv_pci_ioda_shutdown(struct pci_controller *hose) · 1720 unmodified lines
36343590 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
36353591 .dma_dev_setup = pnv_pci_dma_dev_setup,
36363592 .dma_bus_setup = pnv_pci_dma_bus_setup,
3593+ .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
36373594 .setup_msi_irqs = pnv_setup_msi_irqs,
36383595 .teardown_msi_irqs = pnv_teardown_msi_irqs,
36393596 .enable_device_hook = pnv_pci_enable_device_hook,
@@ -3641,8 +3598,6 @@ static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { · 1 unmodified line
36413598 .window_alignment = pnv_pci_window_alignment,
36423599 .setup_bridge = pnv_pci_setup_bridge,
36433600 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3644− .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3645− .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
36463601 .shutdown = pnv_pci_ioda_shutdown,
36473602 };
36483603