Unified · Split
| @@ -133,20 +133,13 @@ · 132 unmodified lines | ||
| 133 | 133 | #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) |
| 134 | 134 | #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) |
| 135 | 135 | #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) |
| 136 | − | |
| 137 | −/* Only R2 or newer cores have the XI bit */ | |
| 138 | −#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) | |
| 139 | −#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1) | |
| 140 | −#else | |
| 141 | −#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) | |
| 142 | −#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) | |
| 143 | −#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */ | |
| 144 | − | |
| 145 | 136 | #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
| 146 | 137 | |
| 147 | 138 | #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) |
| 148 | 139 | /* XI - page cannot be executed */ |
| 149 | −#ifndef _PAGE_NO_EXEC_SHIFT | |
| 140 | +#ifdef _PAGE_SPLITTING_SHIFT | |
| 141 | +#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1) | |
| 142 | +#else | |
| 150 | 143 | #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1) |
| 151 | 144 | #endif |
| 152 | 145 | #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0) |
| @@ -156,14 +149,16 @@ · 3 unmodified lines | ||
| 156 | 149 | #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT)) |
| 157 | 150 | #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT |
| 158 | 151 | #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0) |
| 152 | +#endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */ | |
| 159 | 153 | |
| 154 | +#if defined(_PAGE_NO_READ_SHIFT) | |
| 160 | 155 | #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) |
| 161 | −#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) | |
| 162 | − | |
| 163 | −#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */ | |
| 156 | +#elif defined(_PAGE_SPLITTING_SHIFT) | |
| 157 | +#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) | |
| 158 | +#else | |
| 164 | 159 | #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) |
| 160 | +#endif | |
| 165 | 161 | #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) |
| 166 | −#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */ | |
| 167 | 162 | |
| 168 | 163 | #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) |
| 169 | 164 | #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) |
| @@ -16,11 +16,13 @@ · 15 unmodified lines | ||
| 16 | 16 | #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ |
| 17 | 17 | defined(_MIPS_ARCH_LOONGSON3A) |
| 18 | 18 | |
| 19 | −static inline __attribute_const__ __u16 __arch_swab16(__u16 x) | |
| 19 | +static inline __attribute__((nomips16)) __attribute_const__ | |
| 20 | + __u16 __arch_swab16(__u16 x) | |
| 20 | 21 | { |
| 21 | 22 | __asm__( |
| 22 | 23 | " .set push \n" |
| 23 | 24 | " .set arch=mips32r2 \n" |
| 25 | + " .set nomips16 \n" | |
| 24 | 26 | " wsbh %0, %1 \n" |
| 25 | 27 | " .set pop \n" |
| 26 | 28 | : "=r" (x) |
| @@ -30,11 +32,13 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x) · 3 unmodified lines | ||
| 30 | 32 | } |
| 31 | 33 | #define __arch_swab16 __arch_swab16 |
| 32 | 34 | |
| 33 | −static inline __attribute_const__ __u32 __arch_swab32(__u32 x) | |
| 35 | +static inline __attribute__((nomips16)) __attribute_const__ | |
| 36 | + __u32 __arch_swab32(__u32 x) | |
| 34 | 37 | { |
| 35 | 38 | __asm__( |
| 36 | 39 | " .set push \n" |
| 37 | 40 | " .set arch=mips32r2 \n" |
| 41 | + " .set nomips16 \n" | |
| 38 | 42 | " wsbh %0, %1 \n" |
| 39 | 43 | " rotr %0, %0, 16 \n" |
| 40 | 44 | " .set pop \n" |
| @@ -50,11 +54,13 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) · 9 unmodified lines | ||
| 50 | 54 | * 64-bit kernel on r2 CPUs. |
| 51 | 55 | */ |
| 52 | 56 | #ifdef __mips64 |
| 53 | −static inline __attribute_const__ __u64 __arch_swab64(__u64 x) | |
| 57 | +static inline __attribute__((nomips16)) __attribute_const__ | |
| 58 | + __u64 __arch_swab64(__u64 x) | |
| 54 | 59 | { |
| 55 | 60 | __asm__( |
| 56 | 61 | " .set push \n" |
| 57 | 62 | " .set arch=mips64r2 \n" |
| 63 | + " .set nomips16 \n" | |
| 58 | 64 | " dsbh %0, %1 \n" |
| 59 | 65 | " dshd %0, %0 \n" |
| 60 | 66 | " .set pop \n" |
| @@ -152,7 +152,7 @@ dcache_done: · 151 unmodified lines | ||
| 152 | 152 | |
| 153 | 153 | /* Enter the coherent domain */ |
| 154 | 154 | li t0, 0xff |
| 155 | − PTR_S t0, GCR_CL_COHERENCE_OFS(v1) | |
| 155 | + sw t0, GCR_CL_COHERENCE_OFS(v1) | |
| 156 | 156 | ehb |
| 157 | 157 | |
| 158 | 158 | /* Jump to kseg0 */ |
| @@ -302,7 +302,7 @@ LEAF(mips_cps_boot_vpes) · 143 unmodified lines | ||
| 302 | 302 | PTR_L t0, 0(t0) |
| 303 | 303 | |
| 304 | 304 | /* Calculate a pointer to this cores struct core_boot_config */ |
| 305 | − PTR_L t0, GCR_CL_ID_OFS(t0) | |
| 305 | + lw t0, GCR_CL_ID_OFS(t0) | |
| 306 | 306 | li t1, COREBOOTCFG_SIZE |
| 307 | 307 | mul t0, t0, t1 |
| 308 | 308 | PTR_LA t1, mips_cps_core_bootcfg |