The "Enhanced Allocation (EA) for Memory and I/O Resources" ECN, approved 23 October 2014, sec 6.9.1.2, specifies a second DW in the capability for type 1 (bridge) functions to describe fixed secondary and subordinate bus numbers. This ECN was included in the PCIe r4.0 spec, but sec 6.9.1.2 was omitted, presumably by mistake. Read fixed bus numbers from the EA capability for bridges.
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| @@ -372,6 +372,12 @@ · 371 unmodified lines | ||
| 372 | 372 | #define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ |
| 373 | 373 | #define PCI_EA_ES 0x00000007 /* Entry Size */ |
| 374 | 374 | #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ |
| 375 | + | |
| 376 | +/* EA fixed Secondary and Subordinate bus numbers for Bridge */ | |
| 377 | +#define PCI_EA_SEC_BUS_MASK 0xff | |
| 378 | +#define PCI_EA_SUB_BUS_MASK 0xff00 | |
| 379 | +#define PCI_EA_SUB_BUS_SHIFT 8 | |
| 380 | + | |
| 375 | 381 | /* 0-5 map to BARs 0-5 respectively */ |
| 376 | 382 | #define PCI_EA_BEI_BAR0 0 |
| 377 | 383 | #define PCI_EA_BEI_BAR5 5 |