Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150.
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| @@ -241,6 +241,8 @@ · 240 unmodified lines | |||
| 241 | #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 | 241 | #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 |
| 242 | 242 | ||
| 243 | /* GCC GDSCRs */ | 243 | /* GCC GDSCRs */ |
| 244 | #define PCIE_0_GDSC 0 | ||
| 245 | #define PCIE_1_GDSC 1 | ||
| 244 | #define USB30_PRIM_GDSC 4 | 246 | #define USB30_PRIM_GDSC 4 |
| 245 | #define USB30_SEC_GDSC 5 | 247 | #define USB30_SEC_GDSC 5 |
| 246 | 248 | ||