| @@ -143,7 +143,7 @@ struct spi_device { · 142 unmodified lines |
| 143 | u32 max_speed_hz; | 143 | u32 max_speed_hz; |
| 144 | u8 chip_select; | 144 | u8 chip_select; |
| 145 | u8 bits_per_word; | 145 | u8 bits_per_word; |
| 146 | u16 mode; | 146 | u32 mode; |
| 147 | #define SPI_CPHA 0x01 /* clock phase */ | 147 | #define SPI_CPHA 0x01 /* clock phase */ |
| 148 | #define SPI_CPOL 0x02 /* clock polarity */ | 148 | #define SPI_CPOL 0x02 /* clock polarity */ |
| 149 | #define SPI_MODE_0 (0|0) /* (original MicroWire) */ | 149 | #define SPI_MODE_0 (0|0) /* (original MicroWire) */ |
| @@ -330,6 +330,9 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv) · 180 unmodified lines |
| 330 | * must fail if an unrecognized or unsupported mode is requested. | 330 | * must fail if an unrecognized or unsupported mode is requested. |
| 331 | * It's always safe to call this unless transfers are pending on | 331 | * It's always safe to call this unless transfers are pending on |
| 332 | * the device whose settings are being modified. | 332 | * the device whose settings are being modified. |
| | 333 | * @set_cs_timing: optional hook for SPI devices to request SPI master |
| | 334 | * controller for configuring specific CS setup time, hold time and inactive |
| | 335 | * delay interms of clock counts |
| 333 | * @transfer: adds a message to the controller's transfer queue. | 336 | * @transfer: adds a message to the controller's transfer queue. |
| 334 | * @cleanup: frees controller-specific state | 337 | * @cleanup: frees controller-specific state |
| 335 | * @can_dma: determine whether this controller supports DMA | 338 | * @can_dma: determine whether this controller supports DMA |
| @@ -363,6 +366,7 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv) · 27 unmodified lines |
| 363 | * @unprepare_transfer_hardware: there are currently no more messages on the | 366 | * @unprepare_transfer_hardware: there are currently no more messages on the |
| 364 | * queue so the subsystem notifies the driver that it may relax the | 367 | * queue so the subsystem notifies the driver that it may relax the |
| 365 | * hardware by issuing this call | 368 | * hardware by issuing this call |
| | 369 | * |
| 366 | * @set_cs: set the logic level of the chip select line. May be called | 370 | * @set_cs: set the logic level of the chip select line. May be called |
| 367 | * from interrupt context. | 371 | * from interrupt context. |
| 368 | * @prepare_message: set up the controller to transfer a single message, | 372 | * @prepare_message: set up the controller to transfer a single message, |
| @@ -439,13 +443,12 @@ struct spi_controller { · 70 unmodified lines |
| 439 | u16 dma_alignment; | 443 | u16 dma_alignment; |
| 440 | | 444 | |
| 441 | /* spi_device.mode flags understood by this controller driver */ | 445 | /* spi_device.mode flags understood by this controller driver */ |
| 442 | u16 mode_bits; | 446 | u32 mode_bits; |
| 443 | | 447 | |
| 444 | /* bitmask of supported bits_per_word for transfers */ | 448 | /* bitmask of supported bits_per_word for transfers */ |
| 445 | u32 bits_per_word_mask; | 449 | u32 bits_per_word_mask; |
| 446 | #define SPI_BPW_MASK(bits) BIT((bits) - 1) | 450 | #define SPI_BPW_MASK(bits) BIT((bits) - 1) |
| 447 | #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) | 451 | #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) |
| 448 | #define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1)) | | |
| 449 | | 452 | |
| 450 | /* limits on transfer speed */ | 453 | /* limits on transfer speed */ |
| 451 | u32 min_speed_hz; | 454 | u32 min_speed_hz; |
| @@ -489,6 +492,17 @@ struct spi_controller { · 37 unmodified lines |
| 489 | */ | 492 | */ |
| 490 | int (*setup)(struct spi_device *spi); | 493 | int (*setup)(struct spi_device *spi); |
| 491 | | 494 | |
| | 495 | /* |
| | 496 | * set_cs_timing() method is for SPI controllers that supports |
| | 497 | * configuring CS timing. |
| | 498 | * |
| | 499 | * This hook allows SPI client drivers to request SPI controllers |
| | 500 | * to configure specific CS timing through spi_set_cs_timing() after |
| | 501 | * spi_setup(). |
| | 502 | */ |
| | 503 | void (*set_cs_timing)(struct spi_device *spi, u8 setup_clk_cycles, |
| | 504 | u8 hold_clk_cycles, u8 inactive_clk_cycles); |
| | 505 | |
| 492 | /* bidirectional bulk transfers | 506 | /* bidirectional bulk transfers |
| 493 | * | 507 | * |
| 494 | * + The transfer() method may not sleep; its main role is | 508 | * + The transfer() method may not sleep; its main role is |
| @@ -1277,7 +1291,7 @@ struct spi_board_info { · 782 unmodified lines |
| 1277 | /* mode becomes spi_device.mode, and is essential for chips | 1291 | /* mode becomes spi_device.mode, and is essential for chips |
| 1278 | * where the default of SPI_CS_HIGH = 0 is wrong. | 1292 | * where the default of SPI_CS_HIGH = 0 is wrong. |
| 1279 | */ | 1293 | */ |
| 1280 | u16 mode; | 1294 | u32 mode; |
| 1281 | | 1295 | |
| 1282 | /* ... may need additional spi_device chip config data here. | 1296 | /* ... may need additional spi_device chip config data here. |
| 1283 | * avoid stuff protocol drivers can set; but include stuff | 1297 | * avoid stuff protocol drivers can set; but include stuff |