lael-labs/linux

Documentation/devicetree/bindings/mtd/tango-nand.txt+3−3

@@ -5,7 +5,7 @@ Required properties: · 4 unmodified lines
5	- compatible: "sigma,smp8758-nand"	5	- compatible: "sigma,smp8758-nand"
6	- reg: address/size of nfc_reg, nfc_mem, and pbus_reg	6	- reg: address/size of nfc_reg, nfc_mem, and pbus_reg
7	- dmas: reference to the DMA channel used by the controller	7	- dmas: reference to the DMA channel used by the controller
8	- dma-names: "nfc_sbox"	8	- dma-names: "rxtx"
9	- clocks: reference to the system clock	9	- clocks: reference to the system clock
10	- #address-cells: <1>	10	- #address-cells: <1>
11	- #size-cells: <0>	11	- #size-cells: <0>
@@ -17,9 +17,9 @@ Example: · 5 unmodified lines
17		17
18	nandc: nand-controller@2c000 {	18	nandc: nand-controller@2c000 {
19	compatible = "sigma,smp8758-nand";	19	compatible = "sigma,smp8758-nand";
20	reg = <0x2c000 0x30 0x2d000 0x800 0x20000 0x1000>;	20	reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
21	dmas = <&dma0 3>;	21	dmas = <&dma0 3>;
22	dma-names = "nfc_sbox";	22	dma-names = "rxtx";
23	clocks = <&clkgen SYS_CLK>;	23	clocks = <&clkgen SYS_CLK>;
24	#address-cells = <1>;	24	#address-cells = <1>;
25	#size-cells = <0>;	25	#size-cells = <0>;

Documentation/devicetree/bindings/net/ti,dp83867.txt+4−2

 Required properties:
 	- reg - The ID number for the phy, usually a small integer
 	- ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
-		for applicable values
+		for applicable values. Required only if interface type is
+		PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
 	- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
-		for applicable values
+		for applicable values. Required only if interface type is
+		PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
 	- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
 		for applicable values

Documentation/devicetree/bindings/spi/sh-msiof.txt+13−6

 Renesas MSIOF spi controller
 Required properties:
-- compatible           : "renesas,msiof-<soctype>" for SoCs,
+- compatible           : "renesas,msiof-r8a7790" (R-Car H2)
-			 "renesas,sh-msiof" for SuperH, or
-			 "renesas,sh-mobile-msiof" for SH Mobile series.
-			 Examples with soctypes are:
-			 "renesas,msiof-r8a7790" (R-Car H2)
 			 "renesas,msiof-r8a7791" (R-Car M2-W)
 			 "renesas,msiof-r8a7792" (R-Car V2H)
 			 "renesas,msiof-r8a7793" (R-Car M2-N)
 			 "renesas,msiof-r8a7794" (R-Car E2)
 			 "renesas,msiof-r8a7796" (R-Car M3-W)
 			 "renesas,msiof-sh73a0" (SH-Mobile AG5)
+			 "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
+			 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device)
+			 "renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device)
+			 "renesas,sh-msiof"      (deprecated)
+			 When compatible with the generic version, nodes
+			 must list the SoC-specific version corresponding
+			 to the platform first followed by the generic
+			 version.
 - reg                  : A list of offsets and lengths of the register sets for
 			 the device.
 			 If only one register set is present, it is to be used
 Example:
 	msiof0: spi@e6e20000 {
-		compatible = "renesas,msiof-r8a7791";
+		compatible = "renesas,msiof-r8a7791",
+			     "renesas,rcar-gen2-msiof";
 		reg = <0 0xe6e20000 0 0x0064>;
 		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;

Documentation/virtual/kvm/devices/arm-vgic-v3.txt+8−3

     -EBUSY: One or more VCPUs are running
-  KVM_DEV_ARM_VGIC_CPU_SYSREGS
+  KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
   Attributes:
     The attr field of kvm_device_attr encodes two values:
     bits:     | 63      ....       32 | 31  ....  16 | 15  ....  0 |
     All system regs accessed through this API are (rw, 64-bit) and
     kvm_device_attr.addr points to a __u64 value.
-    KVM_DEV_ARM_VGIC_CPU_SYSREGS accesses the CPU interface registers for the
+    KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the
     CPU specified by the mpidr field.
+    CPU interface registers access is not implemented for AArch32 mode.
+    Error -ENXIO is returned when accessed in AArch32 mode.
   Errors:
     -ENXIO: Getting or setting this register is not yet supported
     -EBUSY: VCPU is running
-    -EINVAL: Invalid mpidr supplied
+    -EINVAL: Invalid mpidr or register value supplied
   KVM_DEV_ARM_VGIC_GRP_NR_IRQS
     architecture defined MPIDR, and the field is encoded as follows:
       | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
       |    Aff3    |    Aff2    |    Aff1    |    Aff0    |
+  Errors:
+    -EINVAL: vINTID is not multiple of 32 or
+     info field is not VGIC_LEVEL_INFO_LINE_LEVEL

MAINTAINERS+9−2

 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:	http://www.armlinux.org.uk/
 S:	Maintained
+T:	git git://git.armlinux.org.uk/~rmk/linux-arm.git
 F:	arch/arm/
 ARM SUB-ARCHITECTURES
 M:	Russell King <linux@armlinux.org.uk>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
+T:	git git://git.armlinux.org.uk/~rmk/linux-arm.git clkdev
 F:	arch/arm/include/asm/clkdev.h
 F:	drivers/clk/clkdev.c
 R:	Javier Martinez Canillas <javier@osg.samsung.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:	linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
+Q:	https://patchwork.kernel.org/project/linux-samsung-soc/list/
 S:	Maintained
 F:	arch/arm/boot/dts/s3c*
 F:	arch/arm/boot/dts/s5p*
 F:	Documentation/devicetree/bindings/net/dsa/marvell.txt
 MARVELL ARMADA DRM SUPPORT
-M:	Russell King <rmk+kernel@armlinux.org.uk>
+M:	Russell King <linux@armlinux.org.uk>
 S:	Maintained
+T:	git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-devel
+T:	git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-fixes
 F:	drivers/gpu/drm/armada/
 F:	include/uapi/drm/armada_drm.h
 F:	Documentation/devicetree/bindings/display/armada/
 F:	drivers/nfc/nxp-nci
 NXP TDA998X DRM DRIVER
-M:	Russell King <rmk+kernel@armlinux.org.uk>
+M:	Russell King <linux@armlinux.org.uk>
 S:	Supported
+T:	git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-tda998x-devel
+T:	git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-tda998x-fixes
 F:	drivers/gpu/drm/i2c/tda998x_drv.c
 F:	include/drm/i2c/tda998x.h

Makefile+2−2

@@ -1,8 +1,8 @@
1	VERSION = 4	1	VERSION = 4
2	PATCHLEVEL = 10	2	PATCHLEVEL = 10
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc4	4	EXTRAVERSION = -rc5
5	NAME = Roaring Lionus	5	NAME = Anniversary Edition
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION
8	# To see a list of typical targets execute "make help"	8	# To see a list of typical targets execute "make help"

arch/arc/Kconfig+1−1

@@ -29,7 +29,7 @@ config ARC · 28 unmodified lines
29	select HAVE_KPROBES	29	select HAVE_KPROBES
30	select HAVE_KRETPROBES	30	select HAVE_KRETPROBES
31	select HAVE_MEMBLOCK	31	select HAVE_MEMBLOCK
32	select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND	32	select HAVE_MOD_ARCH_SPECIFIC
33	select HAVE_OPROFILE	33	select HAVE_OPROFILE
34	select HAVE_PERF_EVENTS	34	select HAVE_PERF_EVENTS
35	select HANDLE_DOMAIN_IRQ	35	select HANDLE_DOMAIN_IRQ

arch/arc/include/asm/cache.h+5−4

 #define ARC_REG_IC_PTAG_HI	0x1F
 /* Bit val in IC_CTRL */
-#define IC_CTRL_CACHE_DISABLE   0x1
+#define IC_CTRL_DIS		0x1
 /* Data cache related Auxiliary registers */
 #define ARC_REG_DC_BCR		0x72	/* Build Config reg */
 #define ARC_REG_DC_PTAG_HI	0x5F
 /* Bit val in DC_CTRL */
-#define DC_CTRL_INV_MODE_FLUSH  0x40
+#define DC_CTRL_DIS		0x001
-#define DC_CTRL_FLUSH_STATUS    0x100
+#define DC_CTRL_INV_MODE_FLUSH	0x040
+#define DC_CTRL_FLUSH_STATUS	0x100
 /*System-level cache (L2 cache) related Auxiliary registers */
 #define ARC_REG_SLC_CFG		0x901
 #define ARC_REG_SLC_RGN_END	0x916
 /* Bit val in SLC_CONTROL */
+#define SLC_CTRL_DIS		0x001
 #define SLC_CTRL_IM		0x040
-#define SLC_CTRL_DISABLE	0x001
 #define SLC_CTRL_BUSY		0x100
 #define SLC_CTRL_RGN_OP_INV	0x200

arch/arc/include/asm/entry-arcv2.h+2−0

 	;
 	; Now manually save: r12, sp, fp, gp, r25
+	PUSH	r30
 	PUSH	r12
 	; Saving pt_regs->sp correctly requires some extra work due to the way
 	POPAX	AUX_USER_SP
 1:
 	POP	r12
+	POP	r30
 .endm

arch/arc/include/asm/module.h+2−2

 #include <asm-generic/module.h>
-#ifdef CONFIG_ARC_DW2_UNWIND
 struct mod_arch_specific {
+#ifdef CONFIG_ARC_DW2_UNWIND
 	void *unw_info;
 	int unw_sec_idx;
+#endif
 	const char *secstr;
 };
-#endif
 #define MODULE_PROC_FAMILY "ARC700"

arch/arc/include/asm/ptrace.h+1−1

@@ -84,7 +84,7 @@ struct pt_regs { · 83 unmodified lines
84	unsigned long fp;	84	unsigned long fp;
85	unsigned long sp; /* user/kernel sp depending on where we came from */	85	unsigned long sp; /* user/kernel sp depending on where we came from */
86		86
87	unsigned long r12;	87	unsigned long r12, r30;
88		88
89	/------- Below list auto saved by h/w -----------/	89	/------- Below list auto saved by h/w -----------/
90	unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;	90	unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;

arch/arc/include/asm/setup.h+1−0

@@ -31,6 +31,7 @@ extern int root_mountflags, end_mem; · 30 unmodified lines
31		31
32	void setup_processor(void);	32	void setup_processor(void);
33	void __init setup_arch_memory(void);	33	void __init setup_arch_memory(void);
		34	long __init arc_get_mem_sz(void);
34		35
35	/* Helpers used in arc__mumbojumbo routines /	36	/* Helpers used in arc__mumbojumbo routines /
36	#define IS_AVAIL1(v, s) ((v) ? s : "")	37	#define IS_AVAIL1(v, s) ((v) ? s : "")

arch/arc/kernel/intc-arcv2.c+3−3

@@ -77,20 +77,20 @@ void arc_init_IRQ(void) · 76 unmodified lines
77		77
78	static void arcv2_irq_mask(struct irq_data *data)	78	static void arcv2_irq_mask(struct irq_data *data)
79	{	79	{
80	write_aux_reg(AUX_IRQ_SELECT, data->irq);	80	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
81	write_aux_reg(AUX_IRQ_ENABLE, 0);	81	write_aux_reg(AUX_IRQ_ENABLE, 0);
82	}	82	}
83		83
84	static void arcv2_irq_unmask(struct irq_data *data)	84	static void arcv2_irq_unmask(struct irq_data *data)
85	{	85	{
86	write_aux_reg(AUX_IRQ_SELECT, data->irq);	86	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
87	write_aux_reg(AUX_IRQ_ENABLE, 1);	87	write_aux_reg(AUX_IRQ_ENABLE, 1);
88	}	88	}
89		89
90	void arcv2_irq_enable(struct irq_data *data)	90	void arcv2_irq_enable(struct irq_data *data)
91	{	91	{
92	/* set default priority */	92	/* set default priority */
93	write_aux_reg(AUX_IRQ_SELECT, data->irq);	93	write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
94	write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);	94	write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
95		95
96	/*	96	/*

arch/arc/kernel/intc-compact.c+2−2

@@ -57,7 +57,7 @@ static void arc_irq_mask(struct irq_data *data) · 56 unmodified lines
57	unsigned int ienb;	57	unsigned int ienb;
58		58
59	ienb = read_aux_reg(AUX_IENABLE);	59	ienb = read_aux_reg(AUX_IENABLE);
60	ienb &= ~(1 << data->irq);	60	ienb &= ~(1 << data->hwirq);
61	write_aux_reg(AUX_IENABLE, ienb);	61	write_aux_reg(AUX_IENABLE, ienb);
62	}	62	}
63		63
@@ -66,7 +66,7 @@ static void arc_irq_unmask(struct irq_data *data) · 2 unmodified lines
66	unsigned int ienb;	66	unsigned int ienb;
67		67
68	ienb = read_aux_reg(AUX_IENABLE);	68	ienb = read_aux_reg(AUX_IENABLE);
69	ienb \|= (1 << data->irq);	69	ienb \|= (1 << data->hwirq);
70	write_aux_reg(AUX_IENABLE, ienb);	70	write_aux_reg(AUX_IENABLE, ienb);
71	}	71	}
72		72

arch/arc/kernel/mcip.c+4−0

 #include <linux/smp.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/spinlock.h>
 #include <soc/arc/mcip.h>
 #include <asm/irqflags-arcv2.h>
 static void idu_cascade_isr(struct irq_desc *desc)
 {
 	struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
+	struct irq_chip *core_chip = irq_desc_get_chip(desc);
 	irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
 	irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
+	chained_irq_enter(core_chip, desc);
 	generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
+	chained_irq_exit(core_chip, desc);
 }
 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)

arch/arc/kernel/module.c+3−1

 #ifdef CONFIG_ARC_DW2_UNWIND
 	mod->arch.unw_sec_idx = 0;
 	mod->arch.unw_info = NULL;
-	mod->arch.secstr = secstr;
 #endif
+	mod->arch.secstr = secstr;
 	return 0;
 }
 	}
+#ifdef CONFIG_ARC_DW2_UNWIND
 	if (strcmp(module->arch.secstr+sechdrs[tgtsec].sh_name, ".eh_frame") == 0)
 		module->arch.unw_sec_idx = tgtsec;
+#endif
 	return 0;

arch/arc/mm/cache.c+122−33

@@ -23,7 +23,7 @@ · 22 unmodified lines
23		23
24	static int l2_line_sz;	24	static int l2_line_sz;
25	static int ioc_exists;	25	static int ioc_exists;
26	int slc_enable = 1, ioc_enable = 0;	26	int slc_enable = 1, ioc_enable = 1;
27	unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */	27	unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
28	unsigned long perip_end = 0xFFFFFFFF; /* legacy value */	28	unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
29		29
@@ -271,7 +271,11 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr, · 241 unmodified lines
271		271
272	/*	272	/*
273	* For ARC700 MMUv3 I-cache and D-cache flushes	273	* For ARC700 MMUv3 I-cache and D-cache flushes
274	* Also reused for HS38 aliasing I-cache configuration	274	* - ARC700 programming model requires paddr and vaddr be passed in seperate
		275	* AUX registers (_IVL and *_PTAG respectively) irrespective of whether the
		276	* caches actually alias or not.
		277	* - For HS38, only the aliasing I-cache configuration uses the PTAG reg
		278	* (non aliasing I-cache version doesn't; while D-cache can't possibly alias)
275	*/	279	*/
276	static inline	280	static inline
277	void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,	281	void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
@@ -458,6 +462,21 @@ static inline void __dc_entire_op(const int op) · 180 unmodified lines
458	__after_dc_op(op);	462	__after_dc_op(op);
459	}	463	}
460		464
		465	static inline void __dc_disable(void)
		466	{
		467	const int r = ARC_REG_DC_CTRL;
		468
		469	__dc_entire_op(OP_FLUSH_N_INV);
		470	write_aux_reg(r, read_aux_reg(r) \| DC_CTRL_DIS);
		471	}
		472
		473	static void __dc_enable(void)
		474	{
		475	const int r = ARC_REG_DC_CTRL;
		476
		477	write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
		478	}
		479
461	/* For kernel mappings cache operation: index is same as paddr */	480	/* For kernel mappings cache operation: index is same as paddr */
462	#define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)	481	#define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
463		482
@@ -483,6 +502,8 @@ static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr, · 19 unmodified lines
483	#else	502	#else
484		503
485	#define __dc_entire_op(op)	504	#define __dc_entire_op(op)
		505	#define __dc_disable()
		506	#define __dc_enable()
486	#define __dc_line_op(paddr, vaddr, sz, op)	507	#define __dc_line_op(paddr, vaddr, sz, op)
487	#define __dc_line_op_k(paddr, sz, op)	508	#define __dc_line_op_k(paddr, sz, op)
488		509
@@ -597,6 +618,40 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) · 108 unmodified lines
597	#endif	618	#endif
598	}	619	}
599		620
		621	noinline static void slc_entire_op(const int op)
		622	{
		623	unsigned int ctrl, r = ARC_REG_SLC_CTRL;
		624
		625	ctrl = read_aux_reg(r);
		626
		627	if (!(op & OP_FLUSH)) /* i.e. OP_INV */
		628	ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
		629	else
		630	ctrl \|= SLC_CTRL_IM;
		631
		632	write_aux_reg(r, ctrl);
		633
		634	write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
		635
		636	/* Important to wait for flush to complete */
		637	while (read_aux_reg(r) & SLC_CTRL_BUSY);
		638	}
		639
		640	static inline void arc_slc_disable(void)
		641	{
		642	const int r = ARC_REG_SLC_CTRL;
		643
		644	slc_entire_op(OP_FLUSH_N_INV);
		645	write_aux_reg(r, read_aux_reg(r) \| SLC_CTRL_DIS);
		646	}
		647
		648	static inline void arc_slc_enable(void)
		649	{
		650	const int r = ARC_REG_SLC_CTRL;
		651
		652	write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
		653	}
		654
600	/***********************************************************	655	/***********************************************************
601	* Exported APIs	656	* Exported APIs
602	*/	657	*/
@@ -923,21 +978,54 @@ SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) · 320 unmodified lines
923	return 0;	978	return 0;
924	}	979	}
925		980
926	void arc_cache_init(void)	981	/*
		982	* IO-Coherency (IOC) setup rules:
		983	*
		984	* 1. Needs to be at system level, so only once by Master core
		985	* Non-Masters need not be accessing caches at that time
		986	* - They are either HALT_ON_RESET and kick started much later or
		987	* - if run on reset, need to ensure that arc_platform_smp_wait_to_boot()
		988	* doesn't perturb caches or coherency unit
		989	*
		990	* 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
		991	* otherwise any straggler data might behave strangely post IOC enabling
		992	*
		993	* 3. All Caches need to be disabled when setting up IOC to elide any in-flight
		994	* Coherency transactions
		995	*/
		996	noinline void __init arc_ioc_setup(void)
927	{	997	{
928	unsigned int __maybe_unused cpu = smp_processor_id();	998	unsigned int ap_sz;
929	char str[256];
930		999
931	printk(arc_cache_mumbojumbo(0, str, sizeof(str)));	1000	/* Flush + invalidate + disable L1 dcache */
		1001	__dc_disable();
		1002
		1003	/* Flush + invalidate SLC */
		1004	if (read_aux_reg(ARC_REG_SLC_BCR))
		1005	slc_entire_op(OP_FLUSH_N_INV);
		1006
		1007	/* IOC Aperture start: TDB: handle non default CONFIG_LINUX_LINK_BASE */
		1008	write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
932		1009
933	/*	1010	/*
934	* Only master CPU needs to execute rest of function:	1011	* IOC Aperture size:
935	* - Assume SMP so all cores will have same cache config so	1012	* decoded as 2 ^ (SIZE + 2) KB: so setting 0x11 implies 512M
936	* any geomtry checks will be same for all	1013	* TBD: fix for PGU + 1GB of low mem
937	* - IOC setup / dma callbacks only need to be setup once	1014	* TBD: fix for PAE
938	*/	1015	*/
939	if (cpu)	1016	ap_sz = order_base_2(arc_get_mem_sz()/1024) - 2;
940	return;	1017	write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, ap_sz);
		1018
		1019	write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
		1020	write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
		1021
		1022	/* Re-enable L1 dcache */
		1023	__dc_enable();
		1024	}
		1025
		1026	void __init arc_cache_init_master(void)
		1027	{
		1028	unsigned int __maybe_unused cpu = smp_processor_id();
941		1029
942	if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {	1030	if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
943	struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;	1031	struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
@@ -985,30 +1073,14 @@ void arc_cache_init(void) · 41 unmodified lines
985	}	1073	}
986	}	1074	}
987		1075
988	if (is_isa_arcv2() && l2_line_sz && !slc_enable) {	1076	/* Note that SLC disable not formally supported till HS 3.0 */
989		1077	if (is_isa_arcv2() && l2_line_sz && !slc_enable)
990	/* IM set : flush before invalidate */	1078	arc_slc_disable();
991	write_aux_reg(ARC_REG_SLC_CTRL,
992	read_aux_reg(ARC_REG_SLC_CTRL) \| SLC_CTRL_IM);
993		1079
994	write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);	1080	if (is_isa_arcv2() && ioc_enable)
995		1081	arc_ioc_setup();
996	/* Important to wait for flush to complete */
997	while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
998	write_aux_reg(ARC_REG_SLC_CTRL,
999	read_aux_reg(ARC_REG_SLC_CTRL) \| SLC_CTRL_DISABLE);
1000	}
1001		1082
1002	if (is_isa_arcv2() && ioc_enable) {	1083	if (is_isa_arcv2() && ioc_enable) {
1003	/* IO coherency base - 0x8z */
1004	write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
1005	/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
1006	write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11);
1007	/* Enable partial writes */
1008	write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
1009	/* Enable IO coherency */
1010	write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
1011
1012	__dma_cache_wback_inv = __dma_cache_wback_inv_ioc;	1084	__dma_cache_wback_inv = __dma_cache_wback_inv_ioc;
1013	__dma_cache_inv = __dma_cache_inv_ioc;	1085	__dma_cache_inv = __dma_cache_inv_ioc;
1014	__dma_cache_wback = __dma_cache_wback_ioc;	1086	__dma_cache_wback = __dma_cache_wback_ioc;
@@ -1022,3 +1094,20 @@ void arc_cache_init(void) · 7 unmodified lines
1022	__dma_cache_wback = __dma_cache_wback_l1;	1094	__dma_cache_wback = __dma_cache_wback_l1;
1023	}	1095	}
1024	}	1096	}
		1097
		1098	void __ref arc_cache_init(void)
		1099	{
		1100	unsigned int __maybe_unused cpu = smp_processor_id();
		1101	char str[256];
		1102
		1103	printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
		1104
		1105	/*
		1106	* Only master CPU needs to execute rest of function:
		1107	* - Assume SMP so all cores will have same cache config so
		1108	* any geomtry checks will be same for all
		1109	* - IOC setup / dma callbacks only need to be setup once
		1110	*/
		1111	if (!cpu)
		1112	arc_cache_init_master();
		1113	}

arch/arc/mm/init.c+5−0

 EXPORT_SYMBOL(node_data);
 #endif
+long __init arc_get_mem_sz(void)
+{
+	return low_mem_sz;
+}
 /* User can over-ride above with "mem=nnn[KkMm]" in cmdline */
 static int __init setup_mem_sz(char *str)
 {

arch/arm/boot/dts/Makefile+1−0

@@ -846,6 +846,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ · 845 unmodified lines
846	sun8i-a83t-allwinner-h8homlet-v2.dtb \	846	sun8i-a83t-allwinner-h8homlet-v2.dtb \
847	sun8i-a83t-cubietruck-plus.dtb \	847	sun8i-a83t-cubietruck-plus.dtb \
848	sun8i-h3-bananapi-m2-plus.dtb \	848	sun8i-h3-bananapi-m2-plus.dtb \
		849	sun8i-h3-nanopi-m1.dtb \
849	sun8i-h3-nanopi-neo.dtb \	850	sun8i-h3-nanopi-neo.dtb \
850	sun8i-h3-orangepi-2.dtb \	851	sun8i-h3-orangepi-2.dtb \
851	sun8i-h3-orangepi-lite.dtb \	852	sun8i-h3-orangepi-lite.dtb \

arch/arm/boot/dts/am335x-icev2.dts+0−1

@@ -170,7 +170,6 @@ · 169 unmodified lines
170	AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP \| MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */	170	AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP \| MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
171	AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP \| MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */	171	AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP \| MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
172	AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP \| MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */	172	AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP \| MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
173	AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP \| MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
174	>;	173	>;
175	};	174	};
176		175

arch/arm/boot/dts/bcm-nsp.dtsi+1−1

@@ -160,7 +160,7 @@ · 159 unmodified lines
160		160
161	axi {	161	axi {
162	compatible = "simple-bus";	162	compatible = "simple-bus";
163	ranges = <0x00000000 0x18000000 0x0011c40a>;	163	ranges = <0x00000000 0x18000000 0x0011c40c>;
164	#address-cells = <1>;	164	#address-cells = <1>;
165	#size-cells = <1>;	165	#size-cells = <1>;
166		166

arch/arm/boot/dts/da850-evm.dts+1−0

@@ -99,6 +99,7 @@ · 98 unmodified lines
99	#size-cells = <1>;	99	#size-cells = <1>;
100	compatible = "m25p64";	100	compatible = "m25p64";
101	spi-max-frequency = <30000000>;	101	spi-max-frequency = <30000000>;
		102	m25p,fast-read;
102	reg = <0>;	103	reg = <0>;
103	partition@0 {	104	partition@0 {
104	label = "U-Boot-SPL";	105	label = "U-Boot-SPL";

arch/arm/boot/dts/dra7.dtsi+1−0

@@ -1378,6 +1378,7 @@ · 1377 unmodified lines
1378	phy-names = "sata-phy";	1378	phy-names = "sata-phy";
1379	clocks = <&sata_ref_clk>;	1379	clocks = <&sata_ref_clk>;
1380	ti,hwmods = "sata";	1380	ti,hwmods = "sata";
		1381	ports-implemented = <0x1>;
1381	};	1382	};
1382		1383
1383	rtc: rtc@48838000 {	1384	rtc: rtc@48838000 {

arch/arm/boot/dts/dra72-evm-revc.dts+1−1

@@ -75,6 +75,6 @@ · 74 unmodified lines
75	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;	75	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
76	ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;	76	ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
77	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;	77	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
78	ti,min-output-imepdance;	78	ti,min-output-impedance;
79	};	79	};
80	};	80	};

arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi+2−2

 		compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
 			     "fsl,imx-audio-sgtl5000";
 		model = "imx6q-nitrogen6_max-sgtl5000";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_sgtl5000>;
 		ssi-controller = <&ssi1>;
 		audio-codec = <&codec>;
 		audio-routing =
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sgtl5000>;
 		reg = <0x0a>;
 		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_2p5v>;

arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi+2−2

 		compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
 			     "fsl,imx-audio-sgtl5000";
 		model = "imx6q-nitrogen6_som2-sgtl5000";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_sgtl5000>;
 		ssi-controller = <&ssi1>;
 		audio-codec = <&codec>;
 		audio-routing =
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sgtl5000>;
 		reg = <0x0a>;
 		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_2p5v>;

arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts+3−8

 &mmc1 {
 	interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins &mmc1_cd>;
+	pinctrl-0 = <&mmc1_pins>;
 	wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;		/* gpio_126 */
 	cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>;		/* gpio_110 */
 	vmmc-supply = <&vmmc1>;
 			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
 			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
 			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
-			OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4)	/* cam_strobe.gpio_126 sdmmc1_wp*/
+			OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4)	/* cam_strobe.gpio_126 */
+			OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4)	/* cam_d11.gpio_110 */
 		>;
 	};
 			OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4)       /* sys_boot6.gpio_8 */
 		>;
 	};
-	mmc1_cd: pinmux_mmc1_cd {
-		pinctrl-single,pins = <
-			OMAP3_WKUP_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4)	/* cam_d11.gpio_110 */
-		>;
-	};
 };

arch/arm/boot/dts/omap5.dtsi+1−0

@@ -988,6 +988,7 @@ · 987 unmodified lines
988	phy-names = "sata-phy";	988	phy-names = "sata-phy";
989	clocks = <&sata_ref_clk>;	989	clocks = <&sata_ref_clk>;
990	ti,hwmods = "sata";	990	ti,hwmods = "sata";
		991	ports-implemented = <0x1>;
991	};	992	};
992		993
993	dss: dss@58000000 {	994	dss: dss@58000000 {

arch/arm/boot/dts/qcom-mdm9615.dtsi+1−1

@@ -357,7 +357,7 @@ · 356 unmodified lines
357	};	357	};
358		358
359	amba {	359	amba {
360	compatible = "arm,amba-bus";	360	compatible = "simple-bus";
361	#address-cells = <1>;	361	#address-cells = <1>;
362	#size-cells = <1>;	362	#size-cells = <1>;
363	ranges;	363	ranges;

arch/arm/boot/dts/sun6i-a31-hummingbird.dts+4−0

 	cpu-supply = <&reg_dcdc3>;
 };
+&de {
+	status = "okay";
+};
 &ehci0 {
 	status = "okay";
 };

arch/arm/boot/dts/sun6i-a31.dtsi+1−0

@@ -234,6 +234,7 @@ · 233 unmodified lines
234	de: display-engine {	234	de: display-engine {
235	compatible = "allwinner,sun6i-a31-display-engine";	235	compatible = "allwinner,sun6i-a31-display-engine";
236	allwinner,pipelines = <&fe0>;	236	allwinner,pipelines = <&fe0>;
		237	status = "disabled";
237	};	238	};
238		239
239	soc@01c00000 {	240	soc@01c00000 {

arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts+1−1

@@ -56,7 +56,7 @@ · 55 unmodified lines
56	};	56	};
57		57
58	&pio {	58	&pio {
59	mmc2_pins_nrst: mmc2@0 {	59	mmc2_pins_nrst: mmc2-rst-pin {
60	allwinner,pins = "PC16";	60	allwinner,pins = "PC16";
61	allwinner,function = "gpio_out";	61	allwinner,function = "gpio_out";
62	allwinner,drive = <SUN4I_PINCTRL_10_MA>;	62	allwinner,drive = <SUN4I_PINCTRL_10_MA>;

arch/arm/configs/multi_v7_defconfig+2−2

@@ -471,7 +471,7 @@ CONFIG_MESON_WATCHDOG=y · 470 unmodified lines
471	CONFIG_DW_WATCHDOG=y	471	CONFIG_DW_WATCHDOG=y
472	CONFIG_DIGICOLOR_WATCHDOG=y	472	CONFIG_DIGICOLOR_WATCHDOG=y
473	CONFIG_BCM2835_WDT=y	473	CONFIG_BCM2835_WDT=y
474	CONFIG_BCM47XX_WATCHDOG=y	474	CONFIG_BCM47XX_WDT=y
475	CONFIG_BCM7038_WDT=m	475	CONFIG_BCM7038_WDT=m
476	CONFIG_BCM_KONA_WDT=y	476	CONFIG_BCM_KONA_WDT=y
477	CONFIG_MFD_ACT8945A=y	477	CONFIG_MFD_ACT8945A=y
@@ -893,7 +893,7 @@ CONFIG_BCM2835_MBOX=y · 415 unmodified lines
893	CONFIG_RASPBERRYPI_FIRMWARE=y	893	CONFIG_RASPBERRYPI_FIRMWARE=y
894	CONFIG_EFI_VARS=m	894	CONFIG_EFI_VARS=m
895	CONFIG_EFI_CAPSULE_LOADER=m	895	CONFIG_EFI_CAPSULE_LOADER=m
896	CONFIG_CONFIG_BCM47XX_NVRAM=y	896	CONFIG_BCM47XX_NVRAM=y
897	CONFIG_BCM47XX_SPROM=y	897	CONFIG_BCM47XX_SPROM=y
898	CONFIG_EXT4_FS=y	898	CONFIG_EXT4_FS=y
899	CONFIG_AUTOFS4_FS=y	899	CONFIG_AUTOFS4_FS=y

arch/arm/configs/s3c2410_defconfig+3−3

@@ -86,9 +86,9 @@ CONFIG_IPV6_TUNNEL=m · 85 unmodified lines
86	CONFIG_NETFILTER=y	86	CONFIG_NETFILTER=y
87	CONFIG_NF_CONNTRACK=m	87	CONFIG_NF_CONNTRACK=m
88	CONFIG_NF_CONNTRACK_EVENTS=y	88	CONFIG_NF_CONNTRACK_EVENTS=y
89	CONFIG_NF_CT_PROTO_DCCP=m	89	CONFIG_NF_CT_PROTO_DCCP=y
90	CONFIG_NF_CT_PROTO_SCTP=m	90	CONFIG_NF_CT_PROTO_SCTP=y
91	CONFIG_NF_CT_PROTO_UDPLITE=m	91	CONFIG_NF_CT_PROTO_UDPLITE=y
92	CONFIG_NF_CONNTRACK_AMANDA=m	92	CONFIG_NF_CONNTRACK_AMANDA=m
93	CONFIG_NF_CONNTRACK_FTP=m	93	CONFIG_NF_CONNTRACK_FTP=m
94	CONFIG_NF_CONNTRACK_H323=m	94	CONFIG_NF_CONNTRACK_H323=m

arch/arm/include/asm/cputype.h+3−0

@@ -94,6 +94,9 @@ · 93 unmodified lines
94	#define ARM_CPU_XSCALE_ARCH_V2 0x4000	94	#define ARM_CPU_XSCALE_ARCH_V2 0x4000
95	#define ARM_CPU_XSCALE_ARCH_V3 0x6000	95	#define ARM_CPU_XSCALE_ARCH_V3 0x6000
96		96
		97	/* Qualcomm implemented cores */
		98	#define ARM_CPU_PART_SCORPION 0x510002d0
		99
97	extern unsigned int processor_id;	100	extern unsigned int processor_id;
98		101
99	#ifdef CONFIG_CPU_CP15	102	#ifdef CONFIG_CPU_CP15

arch/arm/include/asm/ftrace.h+18−0

@@ -54,6 +54,24 @@ static inline void *return_address(unsigned int level) · 53 unmodified lines
54		54
55	#define ftrace_return_address(n) return_address(n)	55	#define ftrace_return_address(n) return_address(n)
56		56
		57	#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
		58
		59	static inline bool arch_syscall_match_sym_name(const char *sym,
		60	const char *name)
		61	{
		62	if (!strcmp(sym, "sys_mmap2"))
		63	sym = "sys_mmap_pgoff";
		64	else if (!strcmp(sym, "sys_statfs64_wrapper"))
		65	sym = "sys_statfs64";
		66	else if (!strcmp(sym, "sys_fstatfs64_wrapper"))
		67	sym = "sys_fstatfs64";
		68	else if (!strcmp(sym, "sys_arm_fadvise64_64"))
		69	sym = "sys_fadvise64_64";
		70
		71	/* Ignore case since sym may start with "SyS" instead of "sys" */
		72	return !strcasecmp(sym, name);
		73	}
		74
57	#endif /* ifndef __ASSEMBLY__ */	75	#endif /* ifndef __ASSEMBLY__ */
58		76
59	#endif /* _ASM_ARM_FTRACE */	77	#endif /* _ASM_ARM_FTRACE */

arch/arm/include/asm/kvm_host.h+0−3

@@ -60,9 +60,6 @@ struct kvm_arch { · 59 unmodified lines
60	/* The last vcpu id that ran on each physical CPU */	60	/* The last vcpu id that ran on each physical CPU */
61	int __percpu *last_vcpu_ran;	61	int __percpu *last_vcpu_ran;
62		62
63	/* Timer */
64	struct arch_timer_kvm timer;
65
66	/*	63	/*
67	* Anything that is not used directly from assembly code goes	64	* Anything that is not used directly from assembly code goes
68	* here.	65	* here.

arch/arm/include/asm/kvm_mmu.h+2−10

 static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu,
 					       kvm_pfn_t pfn,
-					       unsigned long size,
+					       unsigned long size)
-					       bool ipa_uncached)
 {
 	/*
 	 * If we are going to insert an instruction page and the icache is
 	 * and iterate over the range.
 	 */
-	bool need_flush = !vcpu_has_cache_enabled(vcpu) || ipa_uncached;
 	VM_BUG_ON(size & ~PAGE_MASK);
-	if (!need_flush && !icache_is_pipt())
-		goto vipt_cache;
 	while (size) {
 		void *va = kmap_atomic_pfn(pfn);
-		if (need_flush)
+		kvm_flush_dcache_to_poc(va, PAGE_SIZE);
-			kvm_flush_dcache_to_poc(va, PAGE_SIZE);
 		if (icache_is_pipt())
 			__cpuc_coherent_user_range((unsigned long)va,
 		kunmap_atomic(va);
 	}
-vipt_cache:
 	if (!icache_is_pipt() && !icache_is_vivt_asid_tagged()) {
 		/* any kind of VIPT cache */
 		__flush_icache_all();

arch/arm/include/asm/virt.h+5−0

 	return false;
 }
+static inline bool has_vhe(void)
+{
+	return false;
+}
 /* The section containing the hypervisor idmap text */
 extern char __hyp_idmap_text_start[];
 extern char __hyp_idmap_text_end[];

arch/arm/include/uapi/asm/kvm.h+13−0

@@ -181,10 +181,23 @@ struct kvm_arch_memory_slot { · 180 unmodified lines
181	#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2	181	#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
182	#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32	182	#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
183	#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)	183	#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
		184	#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
		185	#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
		186	(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
184	#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0	187	#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
185	#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)	188	#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
		189	#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
186	#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3	190	#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
187	#define KVM_DEV_ARM_VGIC_GRP_CTRL 4	191	#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
		192	#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
		193	#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
		194	#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
		195	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
		196	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
		197	(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
		198	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
		199	#define VGIC_LEVEL_INFO_LINE_LEVEL 0
		200
188	#define KVM_DEV_ARM_VGIC_CTRL_INIT 0	201	#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
189		202
190	/* KVM_IRQ_LINE irq field index values */	203	/* KVM_IRQ_LINE irq field index values */

arch/arm/include/uapi/asm/types.hrenamed from arch/arm/include/asm/types.h+3−3

@@ -1,5 +1,5 @@
1	#ifndef _ASM_TYPES_H	1	#ifndef _UAPI_ASM_TYPES_H
2	#define _ASM_TYPES_H	2	#define _UAPI_ASM_TYPES_H
3		3
4	#include <asm-generic/int-ll64.h>	4	#include <asm-generic/int-ll64.h>
5		5
@@ -37,4 +37,4 @@ · 31 unmodified lines
37	#define __UINTPTR_TYPE__ unsigned long	37	#define __UINTPTR_TYPE__ unsigned long
38	#endif	38	#endif
39		39
40	#endif /* _ASM_TYPES_H */	40	#endif /* _UAPI_ASM_TYPES_H */

arch/arm/kernel/hw_breakpoint.c+16−0

@@ -1063,6 +1063,22 @@ static int __init arch_hw_breakpoint_init(void) · 1062 unmodified lines
1063	return 0;	1063	return 0;
1064	}	1064	}
1065		1065
		1066	/*
		1067	* Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD
		1068	* whenever a WFI is issued, even if the core is not powered down, in
		1069	* violation of the architecture. When DBGPRSR.SPD is set, accesses to
		1070	* breakpoint and watchpoint registers are treated as undefined, so
		1071	* this results in boot time and runtime failures when these are
		1072	* accessed and we unexpectedly take a trap.
		1073	*
		1074	* It's not clear if/how this can be worked around, so we blacklist
		1075	* Scorpion CPUs to avoid these issues.
		1076	*/
		1077	if (read_cpuid_part() == ARM_CPU_PART_SCORPION) {
		1078	pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n");
		1079	return 0;
		1080	}
		1081
1066	has_ossr = core_has_os_save_restore();	1082	has_ossr = core_has_os_save_restore();
1067		1083
1068	/* Determine how many BRPs/WRPs are available. */	1084	/* Determine how many BRPs/WRPs are available. */

arch/arm/kernel/smp_tlb.c+7−0

  */
 #include <linux/preempt.h>
 #include <linux/smp.h>
+#include <linux/uaccess.h>
 #include <asm/smp_plat.h>
 #include <asm/tlbflush.h>
 static inline void ipi_flush_tlb_page(void *arg)
 {
 	struct tlb_args *ta = (struct tlb_args *)arg;
+	unsigned int __ua_flags = uaccess_save_and_enable();
 	local_flush_tlb_page(ta->ta_vma, ta->ta_start);
+	uaccess_restore(__ua_flags);
 }
 static inline void ipi_flush_tlb_kernel_page(void *arg)
 static inline void ipi_flush_tlb_range(void *arg)
 {
 	struct tlb_args *ta = (struct tlb_args *)arg;
+	unsigned int __ua_flags = uaccess_save_and_enable();
 	local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
+	uaccess_restore(__ua_flags);
 }
 static inline void ipi_flush_tlb_kernel_range(void *arg)

arch/arm/kvm/Makefile+3−2

 	plus_virt_def := -DREQUIRES_VIRT=1
 endif
-ccflags-y += -Iarch/arm/kvm
+ccflags-y += -Iarch/arm/kvm -Ivirt/kvm/arm/vgic
 CFLAGS_arm.o := -I. $(plus_virt_def)
 CFLAGS_mmu.o := -I.
 obj-$(CONFIG_KVM_ARM_HOST) += hyp/
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
-obj-y += coproc.o coproc_a15.o coproc_a7.o mmio.o psci.o perf.o
+obj-y += coproc.o coproc_a15.o coproc_a7.o mmio.o psci.o perf.o vgic-v3-coproc.o
 obj-y += $(KVM)/arm/aarch32.o
 obj-y += $(KVM)/arm/vgic/vgic.o
 obj-y += $(KVM)/arm/vgic/vgic-mmio-v3.o
 obj-y += $(KVM)/arm/vgic/vgic-kvm-device.o
 obj-y += $(KVM)/arm/vgic/vgic-its.o
+obj-y += $(KVM)/arm/vgic/vgic-debug.o
 obj-y += $(KVM)/irqchip.o
 obj-y += $(KVM)/arm/arch_timer.o

arch/arm/kvm/arm.c+5−2

 		goto out_free_stage2_pgd;
 	kvm_vgic_early_init(kvm);
-	kvm_timer_init(kvm);
 	/* Mark the initial VMID generation invalid */
 	kvm->arch.vmid_gen = 0;
 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
 {
-	return kvm_timer_should_fire(vcpu);
+	return kvm_timer_should_fire(vcpu_vtimer(vcpu)) ||
+	       kvm_timer_should_fire(vcpu_ptimer(vcpu));
 }
 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
 	__cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);
 	__cpu_init_stage2();
+	if (is_kernel_in_hyp_mode())
+		kvm_timer_init_vhe();
 	kvm_arm_init_debug();
 }

arch/arm/kvm/mmu.c+4−16

 }
 static void coherent_cache_guest_page(struct kvm_vcpu *vcpu, kvm_pfn_t pfn,
-				      unsigned long size, bool uncached)
+				      unsigned long size)
 {
-	__coherent_cache_guest_page(vcpu, pfn, size, uncached);
+	__coherent_cache_guest_page(vcpu, pfn, size);
 }
 static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
 	struct vm_area_struct *vma;
 	kvm_pfn_t pfn;
 	pgprot_t mem_type = PAGE_S2;
-	bool fault_ipa_uncached;
 	bool logging_active = memslot_is_logging(memslot);
 	unsigned long flags = 0;
 	if (!hugetlb && !force_pte)
 		hugetlb = transparent_hugepage_adjust(&pfn, &fault_ipa);
-	fault_ipa_uncached = memslot->flags & KVM_MEMSLOT_INCOHERENT;
 	if (hugetlb) {
 		pmd_t new_pmd = pfn_pmd(pfn, mem_type);
 		new_pmd = pmd_mkhuge(new_pmd);
 			new_pmd = kvm_s2pmd_mkwrite(new_pmd);
 			kvm_set_pfn_dirty(pfn);
 		}
-		coherent_cache_guest_page(vcpu, pfn, PMD_SIZE, fault_ipa_uncached);
+		coherent_cache_guest_page(vcpu, pfn, PMD_SIZE);
 		ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);
 	} else {
 		pte_t new_pte = pfn_pte(pfn, mem_type);
 			kvm_set_pfn_dirty(pfn);
 			mark_page_dirty(kvm, gfn);
 		}
-		coherent_cache_guest_page(vcpu, pfn, PAGE_SIZE, fault_ipa_uncached);
+		coherent_cache_guest_page(vcpu, pfn, PAGE_SIZE);
 		ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte, flags);
 	}
 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 			    unsigned long npages)
 {
-	/*
-	 * Readonly memslots are not incoherent with the caches by definition,
-	 * but in practice, they are used mostly to emulate ROMs or NOR flashes
-	 * that the guest may consider devices and hence map as uncached.
-	 * To prevent incoherency issues in these cases, tag all readonly
-	 * regions as incoherent.
-	 */
-	if (slot->flags & KVM_MEM_READONLY)
-		slot->flags |= KVM_MEMSLOT_INCOHERENT;
 	return 0;
 }

arch/arm/kvm/reset.c+8−1

 	.usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
 };
+static const struct kvm_irq_level cortexa_ptimer_irq = {
+	{ .irq = 30 },
+	.level = 1,
+};
 static const struct kvm_irq_level cortexa_vtimer_irq = {
 	{ .irq = 27 },
 	.level = 1,
 {
 	struct kvm_regs *reset_regs;
 	const struct kvm_irq_level *cpu_vtimer_irq;
+	const struct kvm_irq_level *cpu_ptimer_irq;
 	switch (vcpu->arch.target) {
 	case KVM_ARM_TARGET_CORTEX_A7:
 		reset_regs = &cortexa_regs_reset;
 		vcpu->arch.midr = read_cpuid_id();
 		cpu_vtimer_irq = &cortexa_vtimer_irq;
+		cpu_ptimer_irq = &cortexa_ptimer_irq;
 		break;
 	default:
 		return -ENODEV;
 	kvm_reset_coprocs(vcpu);
 	/* Reset arch_timer context */
-	return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+	return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq, cpu_ptimer_irq);
 }

arch/arm/kvm/vgic-v3-coproc.c+35−0

@@ -0,0 +1,35 @@
	1	/*
	2	* VGIC system registers handling functions for AArch32 mode
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/kvm.h>
	15	#include <linux/kvm_host.h>
	16	#include <asm/kvm_emulate.h>
	17	#include "vgic.h"
	18
	19	int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
	20	u64 *reg)
	21	{
	22	/*
	23	* TODO: Implement for AArch32
	24	*/
	25	return -ENXIO;
	26	}
	27
	28	int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write, u64 id,
	29	u64 *reg)
	30	{
	31	/*
	32	* TODO: Implement for AArch32
	33	*/
	34	return -ENXIO;
	35	}

arch/arm/mach-omap1/dma.c+7−9

 #include "soc.h"
 #define OMAP1_DMA_BASE			(0xfffed800)
-#define OMAP1_LOGICAL_DMA_CH_COUNT	17
 static u32 enable_1510_mode;
 		goto exit_iounmap;
 	}
-	d->lch_count		= OMAP1_LOGICAL_DMA_CH_COUNT;
 	/* Valid attributes for omap1 plus processors */
 	if (cpu_is_omap15xx())
 		d->dev_caps = ENABLE_1510_MODE;
 	d->dev_caps		|= CLEAR_CSR_ON_READ;
 	d->dev_caps		|= IS_WORD_16;
-	if (cpu_is_omap15xx())
+	/* available logical channels */
-		d->chan_count = 9;
+	if (cpu_is_omap15xx()) {
-	else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
+		d->lch_count = 9;
-		if (!(d->dev_caps & ENABLE_1510_MODE))
+	} else {
-			d->chan_count = 16;
+		if (d->dev_caps & ENABLE_1510_MODE)
+			d->lch_count = 9;
 		else
-			d->chan_count = 9;
+			d->lch_count = 16;
 	}
 	p = dma_plat_info;

arch/arm/mach-omap2/pdata-quirks.c+1−1

@@ -161,7 +161,7 @@ static struct ti_st_plat_data wilink7_pdata = { · 160 unmodified lines
161	.nshutdown_gpio = 162,	161	.nshutdown_gpio = 162,
162	.dev_name = "/dev/ttyO1",	162	.dev_name = "/dev/ttyO1",
163	.flow_cntrl = 1,	163	.flow_cntrl = 1,
164	.baud_rate = 300000,	164	.baud_rate = 3000000,
165	};	165	};
166		166
167	static struct platform_device wl128x_device = {	167	static struct platform_device wl128x_device = {

arch/arm/mach-ux500/pm.c+2−2

@@ -134,8 +134,8 @@ bool prcmu_pending_irq(void) · 133 unmodified lines
134	*/	134	*/
135	bool prcmu_is_cpu_in_wfi(int cpu)	135	bool prcmu_is_cpu_in_wfi(int cpu)
136	{	136	{
137	return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :	137	return readl(PRCM_ARM_WFI_STANDBY) &
138	PRCM_ARM_WFI_STANDBY_WFI0;	138	(cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : PRCM_ARM_WFI_STANDBY_WFI0);
139	}	139	}
140		140
141	/*	141	/*

arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts+4−0

 	};
 };
+&scpi_clocks {
+	status = "disabled";
+};
 &uart_AO {
 	status = "okay";
 	pinctrl-0 = <&uart_ao_a_pins>;

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi+1−1

@@ -55,7 +55,7 @@ · 54 unmodified lines
55	mboxes = <&mailbox 1 &mailbox 2>;	55	mboxes = <&mailbox 1 &mailbox 2>;
56	shmem = <&cpu_scp_lpri &cpu_scp_hpri>;	56	shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
57		57
58	clocks {	58	scpi_clocks: clocks {
59	compatible = "arm,scpi-clocks";	59	compatible = "arm,scpi-clocks";
60		60
61	scpi_dvfs: scpi_clocks@0 {	61	scpi_dvfs: scpi_clocks@0 {

arch/arm64/boot/dts/exynos/exynos5433.dtsi+1−1

@@ -1367,7 +1367,7 @@ · 1366 unmodified lines
1367	};	1367	};
1368		1368
1369	amba {	1369	amba {
1370	compatible = "arm,amba-bus";	1370	compatible = "simple-bus";
1371	#address-cells = <1>;	1371	#address-cells = <1>;
1372	#size-cells = <1>;	1372	#size-cells = <1>;
1373	ranges;	1373	ranges;

arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts+1−1

@@ -27,7 +27,7 @@ · 26 unmodified lines
27	stdout-path = "serial0:115200n8";	27	stdout-path = "serial0:115200n8";
28	};	28	};
29		29
30	memory {	30	memory@0 {
31	device_type = "memory";	31	device_type = "memory";
32	reg = <0x0 0x0 0x0 0x40000000>;	32	reg = <0x0 0x0 0x0 0x40000000>;
33	};	33	};

arch/arm64/boot/dts/xilinx/zynqmp.dtsi+3−3

@@ -72,7 +72,7 @@ · 71 unmodified lines
72	<1 10 0xf08>;	72	<1 10 0xf08>;
73	};	73	};
74		74
75	amba_apu {	75	amba_apu: amba_apu@0 {
76	compatible = "simple-bus";	76	compatible = "simple-bus";
77	#address-cells = <2>;	77	#address-cells = <2>;
78	#size-cells = <1>;	78	#size-cells = <1>;
@@ -175,7 +175,7 @@ · 96 unmodified lines
175	};	175	};
176		176
177	i2c0: i2c@ff020000 {	177	i2c0: i2c@ff020000 {
178	compatible = "cdns,i2c-r1p10";	178	compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
179	status = "disabled";	179	status = "disabled";
180	interrupt-parent = <&gic>;	180	interrupt-parent = <&gic>;
181	interrupts = <0 17 4>;	181	interrupts = <0 17 4>;
@@ -185,7 +185,7 @@ · 3 unmodified lines
185	};	185	};
186		186
187	i2c1: i2c@ff030000 {	187	i2c1: i2c@ff030000 {
188	compatible = "cdns,i2c-r1p10";	188	compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
189	status = "disabled";	189	status = "disabled";
190	interrupt-parent = <&gic>;	190	interrupt-parent = <&gic>;
191	interrupts = <0 18 4>;	191	interrupts = <0 18 4>;

arch/arm64/include/asm/kvm_host.h+0−3

@@ -70,9 +70,6 @@ struct kvm_arch { · 69 unmodified lines
70		70
71	/* Interrupt controller */	71	/* Interrupt controller */
72	struct vgic_dist vgic;	72	struct vgic_dist vgic;
73
74	/* Timer */
75	struct arch_timer_kvm timer;
76	};	73	};
77		74
78	#define KVM_NR_MEM_OBJS 40	75	#define KVM_NR_MEM_OBJS 40

arch/arm64/include/asm/kvm_mmu.h+2−4

 static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu,
 					       kvm_pfn_t pfn,
-					       unsigned long size,
+					       unsigned long size)
-					       bool ipa_uncached)
 {
 	void *va = page_address(pfn_to_page(pfn));
-	if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)
+	kvm_flush_dcache_to_poc(va, size);
-		kvm_flush_dcache_to_poc(va, size);
 	if (!icache_is_aliasing()) {		/* PIPT */
 		flush_icache_range((unsigned long)va,

arch/arm64/include/asm/memory.h+1−1

@@ -222,7 +222,7 @@ static inline void *phys_to_virt(phys_addr_t x) · 221 unmodified lines
222	#define _virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)	222	#define _virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
223	#else	223	#else
224	#define __virt_to_pgoff(kaddr) (((u64)(kaddr) & ~PAGE_OFFSET) / PAGE_SIZE * sizeof(struct page))	224	#define __virt_to_pgoff(kaddr) (((u64)(kaddr) & ~PAGE_OFFSET) / PAGE_SIZE * sizeof(struct page))
225	#define __page_to_voff(page) (((u64)(page) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page))	225	#define __page_to_voff(kaddr) (((u64)(kaddr) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page))
226		226
227	#define page_to_virt(page) ((void *)((__page_to_voff(page)) \| PAGE_OFFSET))	227	#define page_to_virt(page) ((void *)((__page_to_voff(page)) \| PAGE_OFFSET))
228	#define virt_to_page(vaddr) ((struct page *)((__virt_to_pgoff(vaddr)) \| VMEMMAP_START))	228	#define virt_to_page(vaddr) ((struct page *)((__virt_to_pgoff(vaddr)) \| VMEMMAP_START))

arch/arm64/include/asm/virt.h+9−0

 #include <asm/ptrace.h>
 #include <asm/sections.h>
 #include <asm/sysreg.h>
+#include <asm/cpufeature.h>
 /*
  * __boot_cpu_mode records what mode CPUs were booted in.
 	return read_sysreg(CurrentEL) == CurrentEL_EL2;
 }
+static inline bool has_vhe(void)
+{
+	if (cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN))
+		return true;
+	return false;
+}
 #ifdef CONFIG_ARM64_VHE
 extern void verify_cpu_run_el(void);
 #else

arch/arm64/include/uapi/asm/kvm.h+13−0

@@ -201,10 +201,23 @@ struct kvm_arch_memory_slot { · 200 unmodified lines
201	#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2	201	#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
202	#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32	202	#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
203	#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)	203	#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
		204	#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
		205	#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
		206	(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
204	#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0	207	#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
205	#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)	208	#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
		209	#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
206	#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3	210	#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
207	#define KVM_DEV_ARM_VGIC_GRP_CTRL 4	211	#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
		212	#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
		213	#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
		214	#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
		215	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
		216	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
		217	(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
		218	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
		219	#define VGIC_LEVEL_INFO_LINE_LEVEL 0
		220
208	#define KVM_DEV_ARM_VGIC_CTRL_INIT 0	221	#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
209		222
210	/* Device Control API on vcpu fd */	223	/* Device Control API on vcpu fd */

arch/arm64/include/uapi/asm/ptrace.h+1−0

@@ -77,6 +77,7 @@ struct user_fpsimd_state { · 76 unmodified lines
77	__uint128_t vregs[32];	77	__uint128_t vregs[32];
78	__u32 fpsr;	78	__u32 fpsr;
79	__u32 fpcr;	79	__u32 fpcr;
		80	__u32 __reserved[2];
80	};	81	};
81		82
82	struct user_hwdebug_state {	83	struct user_hwdebug_state {

arch/arm64/kernel/entry.S+1−1

@@ -683,7 +683,7 @@ el0_inv: · 682 unmodified lines
683	mov x0, sp	683	mov x0, sp
684	mov x1, #BAD_SYNC	684	mov x1, #BAD_SYNC
685	mov x2, x25	685	mov x2, x25
686	bl bad_mode	686	bl bad_el0_sync
687	b ret_to_user	687	b ret_to_user
688	ENDPROC(el0_sync)	688	ENDPROC(el0_sync)
689		689

arch/arm64/kernel/ptrace.c+11−5

 	/* (address, ctrl) registers */
 	limit = regset->n * regset->size;
 	while (count && offset < limit) {
+		if (count < PTRACE_HBP_ADDR_SZ)
+			return -EINVAL;
 		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr,
 					 offset, offset + PTRACE_HBP_ADDR_SZ);
 		if (ret)
 			return ret;
 		offset += PTRACE_HBP_ADDR_SZ;
+		if (!count)
+			break;
 		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl,
 					 offset, offset + PTRACE_HBP_CTRL_SZ);
 		if (ret)
 		   const void *kbuf, const void __user *ubuf)
 {
 	int ret;
-	struct user_pt_regs newregs;
+	struct user_pt_regs newregs = task_pt_regs(target)->user_regs;
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1);
 	if (ret)
 		   const void *kbuf, const void __user *ubuf)
 {
 	int ret;
-	struct user_fpsimd_state newstate;
+	struct user_fpsimd_state newstate =
+		target->thread.fpsimd_state.user_fpsimd;
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
 	if (ret)
 		   const void *kbuf, const void __user *ubuf)
 {
 	int ret;
-	unsigned long tls;
+	unsigned long tls = target->thread.tp_value;
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
 	if (ret)
 			   unsigned int pos, unsigned int count,
 			   const void *kbuf, const void __user *ubuf)
 {
-	int syscallno, ret;
+	int syscallno = task_pt_regs(target)->syscallno;
+	int ret;
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1);
 	if (ret)
 			  const void __user *ubuf)
 {
 	int ret;
-	compat_ulong_t tls;
+	compat_ulong_t tls = target->thread.tp_value;
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
 	if (ret)

arch/arm64/kernel/traps.c+24−4

 }
 /*
- * bad_mode handles the impossible case in the exception vector.
+ * bad_mode handles the impossible case in the exception vector. This is always
+ * fatal.
  */
 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
 {
-	siginfo_t info;
-	void __user *pc = (void __user *)instruction_pointer(regs);
 	console_verbose();
 	pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
 		handler[reason], smp_processor_id(), esr,
 		esr_get_class_string(esr));
+	die("Oops - bad mode", regs, 0);
+	local_irq_disable();
+	panic("bad mode");
+}
+/*
+ * bad_el0_sync handles unexpected, but potentially recoverable synchronous
+ * exceptions taken from EL0. Unlike bad_mode, this returns.
+ */
+asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
+{
+	siginfo_t info;
+	void __user *pc = (void __user *)instruction_pointer(regs);
+	console_verbose();
+	pr_crit("Bad EL0 synchronous exception detected on CPU%d, code 0x%08x -- %s\n",
+		smp_processor_id(), esr, esr_get_class_string(esr));
 	__show_regs(regs);
 	info.si_signo = SIGILL;
 	info.si_code  = ILL_ILLOPC;
 	info.si_addr  = pc;
-	arm64_notify_die("Oops - bad mode", regs, &info, 0);
+	current->thread.fault_address = 0;
+	current->thread.fault_code = 0;
+	force_sig_info(info.si_signo, &info, current);
 }
 void __pte_error(const char *file, int line, unsigned long val)

arch/arm64/kvm/Makefile+3−1

 # Makefile for Kernel-based Virtual Machine module
 #
-ccflags-y += -Iarch/arm64/kvm
+ccflags-y += -Iarch/arm64/kvm -Ivirt/kvm/arm/vgic
 CFLAGS_arm.o := -I.
 CFLAGS_mmu.o := -I.
 kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o regmap.o
 kvm-$(CONFIG_KVM_ARM_HOST) += hyp.o hyp-init.o handle_exit.o
 kvm-$(CONFIG_KVM_ARM_HOST) += guest.o debug.o reset.o sys_regs.o sys_regs_generic_v8.o
+kvm-$(CONFIG_KVM_ARM_HOST) += vgic-sys-reg-v3.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/aarch32.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-mmio-v3.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-kvm-device.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-its.o
+kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-debug.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/irqchip.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
 kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o

arch/arm64/kvm/reset.c+8−1

 			COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
 };
+static const struct kvm_irq_level default_ptimer_irq = {
+	.irq	= 30,
+	.level	= 1,
+};
 static const struct kvm_irq_level default_vtimer_irq = {
 	.irq	= 27,
 	.level	= 1,
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 {
 	const struct kvm_irq_level *cpu_vtimer_irq;
+	const struct kvm_irq_level *cpu_ptimer_irq;
 	const struct kvm_regs *cpu_reset;
 	switch (vcpu->arch.target) {
 		}
 		cpu_vtimer_irq = &default_vtimer_irq;
+		cpu_ptimer_irq = &default_ptimer_irq;
 		break;
 	}
 	kvm_pmu_vcpu_reset(vcpu);
 	/* Reset timer */
-	return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+	return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq, cpu_ptimer_irq);
 }

arch/arm64/kvm/sys_regs.c+81−11

@@ -820,6 +820,61 @@ static bool access_pmuserenr(struct kvm_vcpu vcpu, struct sys_reg_params p, · 819 unmodified lines
820	CRm((0b1100 \| (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \	820	CRm((0b1100 \| (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
821	access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }	821	access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
822		822
		823	static bool access_cntp_tval(struct kvm_vcpu *vcpu,
		824	struct sys_reg_params *p,
		825	const struct sys_reg_desc *r)
		826	{
		827	struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
		828	u64 now = kvm_phys_timer_read();
		829
		830	if (p->is_write)
		831	ptimer->cnt_cval = p->regval + now;
		832	else
		833	p->regval = ptimer->cnt_cval - now;
		834
		835	return true;
		836	}
		837
		838	static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
		839	struct sys_reg_params *p,
		840	const struct sys_reg_desc *r)
		841	{
		842	struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
		843
		844	if (p->is_write) {
		845	/* ISTATUS bit is read-only */
		846	ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
		847	} else {
		848	u64 now = kvm_phys_timer_read();
		849
		850	p->regval = ptimer->cnt_ctl;
		851	/*
		852	* Set ISTATUS bit if it's expired.
		853	* Note that according to ARMv8 ARM Issue A.k, ISTATUS bit is
		854	* UNKNOWN when ENABLE bit is 0, so we chose to set ISTATUS bit
		855	* regardless of ENABLE bit for our implementation convenience.
		856	*/
		857	if (ptimer->cnt_cval <= now)
		858	p->regval \|= ARCH_TIMER_CTRL_IT_STAT;
		859	}
		860
		861	return true;
		862	}
		863
		864	static bool access_cntp_cval(struct kvm_vcpu *vcpu,
		865	struct sys_reg_params *p,
		866	const struct sys_reg_desc *r)
		867	{
		868	struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
		869
		870	if (p->is_write)
		871	ptimer->cnt_cval = p->regval;
		872	else
		873	p->regval = ptimer->cnt_cval;
		874
		875	return true;
		876	}
		877
823	/*	878	/*
824	* Architected system registers.	879	* Architected system registers.
825	* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2	880	* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -1029,6 +1084,16 @@ static const struct sys_reg_desc sys_reg_descs[] = { · 203 unmodified lines
1029	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),	1084	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1030	NULL, reset_unknown, TPIDRRO_EL0 },	1085	NULL, reset_unknown, TPIDRRO_EL0 },
1031		1086
		1087	/* CNTP_TVAL_EL0 */
		1088	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b000),
		1089	access_cntp_tval },
		1090	/* CNTP_CTL_EL0 */
		1091	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b001),
		1092	access_cntp_ctl },
		1093	/* CNTP_CVAL_EL0 */
		1094	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b010),
		1095	access_cntp_cval },
		1096
1032	/* PMEVCNTRn_EL0 */	1097	/* PMEVCNTRn_EL0 */
1033	PMU_PMEVCNTR_EL0(0),	1098	PMU_PMEVCNTR_EL0(0),
1034	PMU_PMEVCNTR_EL0(1),	1099	PMU_PMEVCNTR_EL0(1),
@@ -1795,6 +1860,17 @@ static bool index_to_params(u64 id, struct sys_reg_params *params) · 760 unmodified lines
1795	}	1860	}
1796	}	1861	}
1797		1862
		1863	const struct sys_reg_desc *find_reg_by_id(u64 id,
		1864	struct sys_reg_params *params,
		1865	const struct sys_reg_desc table[],
		1866	unsigned int num)
		1867	{
		1868	if (!index_to_params(id, params))
		1869	return NULL;
		1870
		1871	return find_reg(params, table, num);
		1872	}
		1873
1798	/* Decode an index value, and find the sys_reg_desc entry. */	1874	/* Decode an index value, and find the sys_reg_desc entry. */
1799	static const struct sys_reg_desc index_to_sys_reg_desc(struct kvm_vcpu vcpu,	1875	static const struct sys_reg_desc index_to_sys_reg_desc(struct kvm_vcpu vcpu,
1800	u64 id)	1876	u64 id)
@@ -1807,11 +1883,8 @@ static const struct sys_reg_desc index_to_sys_reg_desc(struct kvm_vcpu vcpu, · 6 unmodified lines
1807	if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)	1883	if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1808	return NULL;	1884	return NULL;
1809		1885
1810	if (!index_to_params(id, &params))
1811	return NULL;
1812
1813	table = get_target_table(vcpu->arch.target, true, &num);	1886	table = get_target_table(vcpu->arch.target, true, &num);
1814	r = find_reg(&params, table, num);	1887	r = find_reg_by_id(id, &params, table, num);
1815	if (!r)	1888	if (!r)
1816	r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));	1889	r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1817		1890
@@ -1918,10 +1991,8 @@ static int get_invariant_sys_reg(u64 id, void __user *uaddr) · 100 unmodified lines
1918	struct sys_reg_params params;	1991	struct sys_reg_params params;
1919	const struct sys_reg_desc *r;	1992	const struct sys_reg_desc *r;
1920		1993
1921	if (!index_to_params(id, &params))	1994	r = find_reg_by_id(id, &params, invariant_sys_regs,
1922	return -ENOENT;	1995	ARRAY_SIZE(invariant_sys_regs));
1923
1924	r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1925	if (!r)	1996	if (!r)
1926	return -ENOENT;	1997	return -ENOENT;
1927		1998
@@ -1935,9 +2006,8 @@ static int set_invariant_sys_reg(u64 id, void __user *uaddr) · 7 unmodified lines
1935	int err;	2006	int err;
1936	u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */	2007	u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1937		2008
1938	if (!index_to_params(id, &params))	2009	r = find_reg_by_id(id, &params, invariant_sys_regs,
1939	return -ENOENT;	2010	ARRAY_SIZE(invariant_sys_regs));
1940	r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1941	if (!r)	2011	if (!r)
1942	return -ENOENT;	2012	return -ENOENT;
1943		2013

arch/arm64/kvm/sys_regs.h+4−0

 	return i1->Op2 - i2->Op2;
 }
+const struct sys_reg_desc *find_reg_by_id(u64 id,
+					  struct sys_reg_params *params,
+					  const struct sys_reg_desc table[],
+					  unsigned int num);
 #define Op0(_x) 	.Op0 = _x
 #define Op1(_x) 	.Op1 = _x

arch/arm64/kvm/vgic-sys-reg-v3.c+346−0

@@ -0,0 +1,346 @@
	1	/*
	2	* VGIC system registers handling functions for AArch64 mode
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/irqchip/arm-gic-v3.h>
	15	#include <linux/kvm.h>
	16	#include <linux/kvm_host.h>
	17	#include <asm/kvm_emulate.h>
	18	#include "vgic.h"
	19	#include "sys_regs.h"
	20
	21	static bool access_gic_ctlr(struct kvm_vcpu vcpu, struct sys_reg_params p,
	22	const struct sys_reg_desc *r)
	23	{
	24	u32 host_pri_bits, host_id_bits, host_seis, host_a3v, seis, a3v;
	25	struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu;
	26	struct vgic_vmcr vmcr;
	27	u64 val;
	28
	29	vgic_get_vmcr(vcpu, &vmcr);
	30	if (p->is_write) {
	31	val = p->regval;
	32
	33	/*
	34	* Disallow restoring VM state if not supported by this
	35	* hardware.
	36	*/
	37	host_pri_bits = ((val & ICC_CTLR_EL1_PRI_BITS_MASK) >>
	38	ICC_CTLR_EL1_PRI_BITS_SHIFT) + 1;
	39	if (host_pri_bits > vgic_v3_cpu->num_pri_bits)
	40	return false;
	41
	42	vgic_v3_cpu->num_pri_bits = host_pri_bits;
	43
	44	host_id_bits = (val & ICC_CTLR_EL1_ID_BITS_MASK) >>
	45	ICC_CTLR_EL1_ID_BITS_SHIFT;
	46	if (host_id_bits > vgic_v3_cpu->num_id_bits)
	47	return false;
	48
	49	vgic_v3_cpu->num_id_bits = host_id_bits;
	50
	51	host_seis = ((kvm_vgic_global_state.ich_vtr_el2 &
	52	ICH_VTR_SEIS_MASK) >> ICH_VTR_SEIS_SHIFT);
	53	seis = (val & ICC_CTLR_EL1_SEIS_MASK) >>
	54	ICC_CTLR_EL1_SEIS_SHIFT;
	55	if (host_seis != seis)
	56	return false;
	57
	58	host_a3v = ((kvm_vgic_global_state.ich_vtr_el2 &
	59	ICH_VTR_A3V_MASK) >> ICH_VTR_A3V_SHIFT);
	60	a3v = (val & ICC_CTLR_EL1_A3V_MASK) >> ICC_CTLR_EL1_A3V_SHIFT;
	61	if (host_a3v != a3v)
	62	return false;
	63
	64	/*
	65	* Here set VMCR.CTLR in ICC_CTLR_EL1 layout.
	66	* The vgic_set_vmcr() will convert to ICH_VMCR layout.
	67	*/
	68	vmcr.ctlr = val & ICC_CTLR_EL1_CBPR_MASK;
	69	vmcr.ctlr \|= val & ICC_CTLR_EL1_EOImode_MASK;
	70	vgic_set_vmcr(vcpu, &vmcr);
	71	} else {
	72	val = 0;
	73	val \|= (vgic_v3_cpu->num_pri_bits - 1) <<
	74	ICC_CTLR_EL1_PRI_BITS_SHIFT;
	75	val \|= vgic_v3_cpu->num_id_bits << ICC_CTLR_EL1_ID_BITS_SHIFT;
	76	val \|= ((kvm_vgic_global_state.ich_vtr_el2 &
	77	ICH_VTR_SEIS_MASK) >> ICH_VTR_SEIS_SHIFT) <<
	78	ICC_CTLR_EL1_SEIS_SHIFT;
	79	val \|= ((kvm_vgic_global_state.ich_vtr_el2 &
	80	ICH_VTR_A3V_MASK) >> ICH_VTR_A3V_SHIFT) <<
	81	ICC_CTLR_EL1_A3V_SHIFT;
	82	/*
	83	* The VMCR.CTLR value is in ICC_CTLR_EL1 layout.
	84	* Extract it directly using ICC_CTLR_EL1 reg definitions.
	85	*/
	86	val \|= vmcr.ctlr & ICC_CTLR_EL1_CBPR_MASK;
	87	val \|= vmcr.ctlr & ICC_CTLR_EL1_EOImode_MASK;
	88
	89	p->regval = val;
	90	}
	91
	92	return true;
	93	}
	94
	95	static bool access_gic_pmr(struct kvm_vcpu vcpu, struct sys_reg_params p,
	96	const struct sys_reg_desc *r)
	97	{
	98	struct vgic_vmcr vmcr;
	99
	100	vgic_get_vmcr(vcpu, &vmcr);
	101	if (p->is_write) {
	102	vmcr.pmr = (p->regval & ICC_PMR_EL1_MASK) >> ICC_PMR_EL1_SHIFT;
	103	vgic_set_vmcr(vcpu, &vmcr);
	104	} else {
	105	p->regval = (vmcr.pmr << ICC_PMR_EL1_SHIFT) & ICC_PMR_EL1_MASK;
	106	}
	107
	108	return true;
	109	}
	110
	111	static bool access_gic_bpr0(struct kvm_vcpu vcpu, struct sys_reg_params p,
	112	const struct sys_reg_desc *r)
	113	{
	114	struct vgic_vmcr vmcr;
	115
	116	vgic_get_vmcr(vcpu, &vmcr);
	117	if (p->is_write) {
	118	vmcr.bpr = (p->regval & ICC_BPR0_EL1_MASK) >>
	119	ICC_BPR0_EL1_SHIFT;
	120	vgic_set_vmcr(vcpu, &vmcr);
	121	} else {
	122	p->regval = (vmcr.bpr << ICC_BPR0_EL1_SHIFT) &
	123	ICC_BPR0_EL1_MASK;
	124	}
	125
	126	return true;
	127	}
	128
	129	static bool access_gic_bpr1(struct kvm_vcpu vcpu, struct sys_reg_params p,
	130	const struct sys_reg_desc *r)
	131	{
	132	struct vgic_vmcr vmcr;
	133
	134	if (!p->is_write)
	135	p->regval = 0;
	136
	137	vgic_get_vmcr(vcpu, &vmcr);
	138	if (!((vmcr.ctlr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT)) {
	139	if (p->is_write) {
	140	vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >>
	141	ICC_BPR1_EL1_SHIFT;
	142	vgic_set_vmcr(vcpu, &vmcr);
	143	} else {
	144	p->regval = (vmcr.abpr << ICC_BPR1_EL1_SHIFT) &
	145	ICC_BPR1_EL1_MASK;
	146	}
	147	} else {
	148	if (!p->is_write)
	149	p->regval = min((vmcr.bpr + 1), 7U);
	150	}
	151
	152	return true;
	153	}
	154
	155	static bool access_gic_grpen0(struct kvm_vcpu vcpu, struct sys_reg_params p,
	156	const struct sys_reg_desc *r)
	157	{
	158	struct vgic_vmcr vmcr;
	159
	160	vgic_get_vmcr(vcpu, &vmcr);
	161	if (p->is_write) {
	162	vmcr.grpen0 = (p->regval & ICC_IGRPEN0_EL1_MASK) >>
	163	ICC_IGRPEN0_EL1_SHIFT;
	164	vgic_set_vmcr(vcpu, &vmcr);
	165	} else {
	166	p->regval = (vmcr.grpen0 << ICC_IGRPEN0_EL1_SHIFT) &
	167	ICC_IGRPEN0_EL1_MASK;
	168	}
	169
	170	return true;
	171	}
	172
	173	static bool access_gic_grpen1(struct kvm_vcpu vcpu, struct sys_reg_params p,
	174	const struct sys_reg_desc *r)
	175	{
	176	struct vgic_vmcr vmcr;
	177
	178	vgic_get_vmcr(vcpu, &vmcr);
	179	if (p->is_write) {
	180	vmcr.grpen1 = (p->regval & ICC_IGRPEN1_EL1_MASK) >>
	181	ICC_IGRPEN1_EL1_SHIFT;
	182	vgic_set_vmcr(vcpu, &vmcr);
	183	} else {
	184	p->regval = (vmcr.grpen1 << ICC_IGRPEN1_EL1_SHIFT) &
	185	ICC_IGRPEN1_EL1_MASK;
	186	}
	187
	188	return true;
	189	}
	190
	191	static void vgic_v3_access_apr_reg(struct kvm_vcpu *vcpu,
	192	struct sys_reg_params *p, u8 apr, u8 idx)
	193	{
	194	struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
	195	uint32_t *ap_reg;
	196
	197	if (apr)
	198	ap_reg = &vgicv3->vgic_ap1r[idx];
	199	else
	200	ap_reg = &vgicv3->vgic_ap0r[idx];
	201
	202	if (p->is_write)
	203	*ap_reg = p->regval;
	204	else
	205	p->regval = *ap_reg;
	206	}
	207
	208	static bool access_gic_aprn(struct kvm_vcpu vcpu, struct sys_reg_params p,
	209	const struct sys_reg_desc *r, u8 apr)
	210	{
	211	struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu;
	212	u8 idx = r->Op2 & 3;
	213
	214	/*
	215	* num_pri_bits are initialized with HW supported values.
	216	* We can rely safely on num_pri_bits even if VM has not
	217	* restored ICC_CTLR_EL1 before restoring APnR registers.
	218	*/
	219	switch (vgic_v3_cpu->num_pri_bits) {
	220	case 7:
	221	vgic_v3_access_apr_reg(vcpu, p, apr, idx);
	222	break;
	223	case 6:
	224	if (idx > 1)
	225	goto err;
	226	vgic_v3_access_apr_reg(vcpu, p, apr, idx);
	227	break;
	228	default:
	229	if (idx > 0)
	230	goto err;
	231	vgic_v3_access_apr_reg(vcpu, p, apr, idx);
	232	}
	233
	234	return true;
	235	err:
	236	if (!p->is_write)
	237	p->regval = 0;
	238
	239	return false;
	240	}
	241
	242	static bool access_gic_ap0r(struct kvm_vcpu vcpu, struct sys_reg_params p,
	243	const struct sys_reg_desc *r)
	244
	245	{
	246	return access_gic_aprn(vcpu, p, r, 0);
	247	}
	248
	249	static bool access_gic_ap1r(struct kvm_vcpu vcpu, struct sys_reg_params p,
	250	const struct sys_reg_desc *r)
	251	{
	252	return access_gic_aprn(vcpu, p, r, 1);
	253	}
	254
	255	static bool access_gic_sre(struct kvm_vcpu vcpu, struct sys_reg_params p,
	256	const struct sys_reg_desc *r)
	257	{
	258	struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
	259
	260	/* Validate SRE bit */
	261	if (p->is_write) {
	262	if (!(p->regval & ICC_SRE_EL1_SRE))
	263	return false;
	264	} else {
	265	p->regval = vgicv3->vgic_sre;
	266	}
	267
	268	return true;
	269	}
	270	static const struct sys_reg_desc gic_v3_icc_reg_descs[] = {
	271	/* ICC_PMR_EL1 */
	272	{ Op0(3), Op1(0), CRn(4), CRm(6), Op2(0), access_gic_pmr },
	273	/* ICC_BPR0_EL1 */
	274	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(3), access_gic_bpr0 },
	275	/* ICC_AP0R0_EL1 */
	276	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(4), access_gic_ap0r },
	277	/* ICC_AP0R1_EL1 */
	278	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(5), access_gic_ap0r },
	279	/* ICC_AP0R2_EL1 */
	280	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(6), access_gic_ap0r },
	281	/* ICC_AP0R3_EL1 */
	282	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(7), access_gic_ap0r },
	283	/* ICC_AP1R0_EL1 */
	284	{ Op0(3), Op1(0), CRn(12), CRm(9), Op2(0), access_gic_ap1r },
	285	/* ICC_AP1R1_EL1 */
	286	{ Op0(3), Op1(0), CRn(12), CRm(9), Op2(1), access_gic_ap1r },
	287	/* ICC_AP1R2_EL1 */
	288	{ Op0(3), Op1(0), CRn(12), CRm(9), Op2(2), access_gic_ap1r },
	289	/* ICC_AP1R3_EL1 */
	290	{ Op0(3), Op1(0), CRn(12), CRm(9), Op2(3), access_gic_ap1r },
	291	/* ICC_BPR1_EL1 */
	292	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(3), access_gic_bpr1 },
	293	/* ICC_CTLR_EL1 */
	294	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(4), access_gic_ctlr },
	295	/* ICC_SRE_EL1 */
	296	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(5), access_gic_sre },
	297	/* ICC_IGRPEN0_EL1 */
	298	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(6), access_gic_grpen0 },
	299	/* ICC_GRPEN1_EL1 */
	300	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(7), access_gic_grpen1 },
	301	};
	302
	303	int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
	304	u64 *reg)
	305	{
	306	struct sys_reg_params params;
	307	u64 sysreg = (id & KVM_DEV_ARM_VGIC_SYSREG_MASK) \| KVM_REG_SIZE_U64;
	308
	309	params.regval = *reg;
	310	params.is_write = is_write;
	311	params.is_aarch32 = false;
	312	params.is_32bit = false;
	313
	314	if (find_reg_by_id(sysreg, &params, gic_v3_icc_reg_descs,
	315	ARRAY_SIZE(gic_v3_icc_reg_descs)))
	316	return 0;
	317
	318	return -ENXIO;
	319	}
	320
	321	int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write, u64 id,
	322	u64 *reg)
	323	{
	324	struct sys_reg_params params;
	325	const struct sys_reg_desc *r;
	326	u64 sysreg = (id & KVM_DEV_ARM_VGIC_SYSREG_MASK) \| KVM_REG_SIZE_U64;
	327
	328	if (is_write)
	329	params.regval = *reg;
	330	params.is_write = is_write;
	331	params.is_aarch32 = false;
	332	params.is_32bit = false;
	333
	334	r = find_reg_by_id(sysreg, &params, gic_v3_icc_reg_descs,
	335	ARRAY_SIZE(gic_v3_icc_reg_descs));
	336	if (!r)
	337	return -ENXIO;
	338
	339	if (!r->access(vcpu, &params, r))
	340	return -EINVAL;
	341
	342	if (!is_write)
	343	*reg = params.regval;
	344
	345	return 0;
	346	}

arch/arm64/mm/init.c+2−0

@@ -404,6 +404,8 @@ void __init mem_init(void) · 403 unmodified lines
404	if (swiotlb_force == SWIOTLB_FORCE \|\|	404	if (swiotlb_force == SWIOTLB_FORCE \|\|
405	max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))	405	max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))
406	swiotlb_init(1);	406	swiotlb_init(1);
		407	else
		408	swiotlb_force = SWIOTLB_NO_FORCE;
407		409
408	set_max_mapnr(pfn_to_page(max_pfn) - mem_map);	410	set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
409		411

arch/powerpc/include/asm/book3s/64/hash-4k.h+3−2

 #ifdef CONFIG_HUGETLB_PAGE
 static inline int hash__hugepd_ok(hugepd_t hpd)
 {
+	unsigned long hpdval = hpd_val(hpd);
 	/*
 	 * if it is not a pte and have hugepd shift mask
 	 * set, then it is a hugepd directory pointer
 	 */
-	if (!(hpd.pd & _PAGE_PTE) &&
+	if (!(hpdval & _PAGE_PTE) &&
-	    ((hpd.pd & HUGEPD_SHIFT_MASK) != 0))
+	    ((hpdval & HUGEPD_SHIFT_MASK) != 0))
 		return true;
 	return false;
 }

arch/powerpc/include/asm/book3s/64/hash.h+4−0

 					      unsigned long phys);
 extern void hash__vmemmap_remove_mapping(unsigned long start,
 				     unsigned long page_size);
+int hash__create_section_mapping(unsigned long start, unsigned long end);
+int hash__remove_section_mapping(unsigned long start, unsigned long end);
 #endif /* !__ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */

arch/powerpc/include/asm/hugetlb.h+8−6

 	 * We have only four bits to encode, MMU page size
 	 */
 	BUILD_BUG_ON((MMU_PAGE_COUNT - 1) > 0xf);
-	return __va(hpd.pd & HUGEPD_ADDR_MASK);
+	return __va(hpd_val(hpd) & HUGEPD_ADDR_MASK);
 }
 static inline unsigned int hugepd_mmu_psize(hugepd_t hpd)
 {
-	return (hpd.pd & HUGEPD_SHIFT_MASK) >> 2;
+	return (hpd_val(hpd) & HUGEPD_SHIFT_MASK) >> 2;
 }
 static inline unsigned int hugepd_shift(hugepd_t hpd)
 {
 	BUG_ON(!hugepd_ok(hpd));
 #ifdef CONFIG_PPC_8xx
-	return (pte_t *)__va(hpd.pd & ~(_PMD_PAGE_MASK | _PMD_PRESENT_MASK));
+	return (pte_t *)__va(hpd_val(hpd) &
+			     ~(_PMD_PAGE_MASK | _PMD_PRESENT_MASK));
 #else
-	return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
+	return (pte_t *)((hpd_val(hpd) &
+			  ~HUGEPD_SHIFT_MASK) | PD_HUGE);
 #endif
 }
 static inline unsigned int hugepd_shift(hugepd_t hpd)
 {
 #ifdef CONFIG_PPC_8xx
-	return ((hpd.pd & _PMD_PAGE_MASK) >> 1) + 17;
+	return ((hpd_val(hpd) & _PMD_PAGE_MASK) >> 1) + 17;
 #else
-	return hpd.pd & HUGEPD_SHIFT_MASK;
+	return hpd_val(hpd) & HUGEPD_SHIFT_MASK;
 #endif
 }

arch/powerpc/include/asm/nohash/pgtable.h+3−2

 static inline int hugepd_ok(hugepd_t hpd)
 {
 #ifdef CONFIG_PPC_8xx
-	return ((hpd.pd & 0x4) != 0);
+	return ((hpd_val(hpd) & 0x4) != 0);
 #else
-	return (hpd.pd > 0);
+	/* We clear the top bit to indicate hugepd */
+	return ((hpd_val(hpd) & PD_HUGE) ==  0);
 #endif
 }

arch/powerpc/include/asm/page.h+0−3

 #include <asm/pgtable-types.h>
 #endif
-typedef struct { signed long pd; } hugepd_t;
 #ifndef CONFIG_HUGETLB_PAGE
 #define is_hugepd(pdep)		(0)
 #define pgd_huge(pgd)		(0)
 #endif /* CONFIG_HUGETLB_PAGE */
-#define __hugepd(x) ((hugepd_t) { (x) })
 struct page;
 extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
 extern void copy_user_page(void *to, void *from, unsigned long vaddr,

arch/powerpc/include/asm/perf_event_server.h+1−0

@@ -65,6 +65,7 @@ struct power_pmu { · 64 unmodified lines
65	#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */	65	#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
66	#define PPMU_HAS_SIER 0x00000040 /* Has SIER */	66	#define PPMU_HAS_SIER 0x00000040 /* Has SIER */
67	#define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */	67	#define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */
		68	#define PPMU_NO_SIAR 0x00000100 /* Do not use SIAR */
68		69
69	/*	70	/*
70	* Values for flags to get_alternatives()	71	* Values for flags to get_alternatives()

arch/powerpc/include/asm/pgtable-be-types.h+8−0

@@ -104,4 +104,12 @@ static inline bool pmd_xchg(pmd_t *pmdp, pmd_t old, pmd_t new) · 103 unmodified lines
104	return pmd_raw(old) == prev;	104	return pmd_raw(old) == prev;
105	}	105	}
106		106
		107	typedef struct { __be64 pdbe; } hugepd_t;
		108	#define __hugepd(x) ((hugepd_t) { cpu_to_be64(x) })
		109
		110	static inline unsigned long hpd_val(hugepd_t x)
		111	{
		112	return be64_to_cpu(x.pdbe);
		113	}
		114
107	#endif /* _ASM_POWERPC_PGTABLE_BE_TYPES_H */	115	#endif /* _ASM_POWERPC_PGTABLE_BE_TYPES_H */

arch/powerpc/include/asm/pgtable-types.h+7−0

@@ -66,4 +66,11 @@ static inline bool pte_xchg(pte_t *ptep, pte_t old, pte_t new) · 65 unmodified lines
66	}	66	}
67	#endif	67	#endif
68		68
		69	typedef struct { unsigned long pd; } hugepd_t;
		70	#define __hugepd(x) ((hugepd_t) { (x) })
		71	static inline unsigned long hpd_val(hugepd_t x)
		72	{
		73	return x.pd;
		74	}
		75
69	#endif /* _ASM_POWERPC_PGTABLE_TYPES_H */	76	#endif /* _ASM_POWERPC_PGTABLE_TYPES_H */

arch/powerpc/include/asm/ppc-opcode.h+5−5

arch/powerpc/kernel/eeh.c+9−1

 	 *
 	 * For pHyp, we have to enable IO for log retrieval. Otherwise,
 	 * 0xFF's is always returned from PCI config space.
+	 *
+	 * When the @severity is EEH_LOG_PERM, the PE is going to be
+	 * removed. Prior to that, the drivers for devices included in
+	 * the PE will be closed. The drivers rely on working IO path
+	 * to bring the devices to quiet state. Otherwise, PCI traffic
+	 * from those devices after they are removed is like to cause
+	 * another unexpected EEH error.
 	 */
 	if (!(pe->type & EEH_PE_PHB)) {
-		if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG))
+		if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
+		    severity == EEH_LOG_PERM)
 			eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
 		/*

arch/powerpc/kernel/ptrace.c+14−0

 	flush_fp_to_thread(target);
+	for (i = 0; i < 32 ; i++)
+		buf[i] = target->thread.TS_FPR(i);
+	buf[32] = target->thread.fp_state.fpscr;
 	/* copy to local buffer then write that out */
 	i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
 	if (i)
 	flush_altivec_to_thread(target);
 	flush_vsx_to_thread(target);
+	for (i = 0; i < 32 ; i++)
+		buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 				 buf, 0, 32 * sizeof(double));
 	if (!ret)
 	flush_fp_to_thread(target);
 	flush_altivec_to_thread(target);
+	for (i = 0; i < 32; i++)
+		buf[i] = target->thread.TS_CKFPR(i);
+	buf[32] = target->thread.ckfp_state.fpscr;
 	/* copy to local buffer then write that out */
 	i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
 	if (i)
 	flush_altivec_to_thread(target);
 	flush_vsx_to_thread(target);
+	for (i = 0; i < 32 ; i++)
+		buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 				 buf, 0, 32 * sizeof(double));
 	if (!ret)

arch/powerpc/mm/hash_utils_64.c+2−2

@@ -747,7 +747,7 @@ static unsigned long __init htab_get_table_size(void) · 746 unmodified lines
747	}	747	}
748		748
749	#ifdef CONFIG_MEMORY_HOTPLUG	749	#ifdef CONFIG_MEMORY_HOTPLUG
750	int create_section_mapping(unsigned long start, unsigned long end)	750	int hash__create_section_mapping(unsigned long start, unsigned long end)
751	{	751	{
752	int rc = htab_bolt_mapping(start, end, __pa(start),	752	int rc = htab_bolt_mapping(start, end, __pa(start),
753	pgprot_val(PAGE_KERNEL), mmu_linear_psize,	753	pgprot_val(PAGE_KERNEL), mmu_linear_psize,
@@ -761,7 +761,7 @@ int create_section_mapping(unsigned long start, unsigned long end) · 7 unmodified lines
761	return rc;	761	return rc;
762	}	762	}
763		763
764	int remove_section_mapping(unsigned long start, unsigned long end)	764	int hash__remove_section_mapping(unsigned long start, unsigned long end)
765	{	765	{
766	int rc = htab_remove_mapping(start, end, mmu_linear_psize,	766	int rc = htab_remove_mapping(start, end, mmu_linear_psize,
767	mmu_kernel_ssize);	767	mmu_kernel_ssize);

arch/powerpc/mm/hugetlbpage-hash64.c+4−1

 int hugepd_ok(hugepd_t hpd)
 {
 	bool is_hugepd;
+	unsigned long hpdval;
+	hpdval = hpd_val(hpd);
 	/*
 	 * We should not find this format in page directory, warn otherwise.
 	 */
-	is_hugepd = (((hpd.pd & 0x3) == 0x0) && ((hpd.pd & HUGEPD_SHIFT_MASK) != 0));
+	is_hugepd = (((hpdval & 0x3) == 0x0) && ((hpdval & HUGEPD_SHIFT_MASK) != 0));
 	WARN(is_hugepd, "Found wrong page directory format\n");
 	return 0;
 }

arch/powerpc/mm/hugetlbpage.c+12−19

 static unsigned nr_gpages;
 #endif
-#define hugepd_none(hpd)	((hpd).pd == 0)
+#define hugepd_none(hpd)	(hpd_val(hpd) == 0)
 pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
 {
 	for (i = 0; i < num_hugepd; i++, hpdp++) {
 		if (unlikely(!hugepd_none(*hpdp)))
 			break;
-		else
+		else {
 #ifdef CONFIG_PPC_BOOK3S_64
-			hpdp->pd = __pa(new) |
+			*hpdp = __hugepd(__pa(new) |
-				   (shift_to_mmu_psize(pshift) << 2);
+					 (shift_to_mmu_psize(pshift) << 2));
 #elif defined(CONFIG_PPC_8xx)
-			hpdp->pd = __pa(new) |
+			*hpdp = __hugepd(__pa(new) |
-				   (pshift == PAGE_SHIFT_8M ? _PMD_PAGE_8M :
+					 (pshift == PAGE_SHIFT_8M ? _PMD_PAGE_8M :
-							      _PMD_PAGE_512K) |
+					  _PMD_PAGE_512K) | _PMD_PRESENT);
-				   _PMD_PRESENT;
 #else
 			/* We use the old format for PPC_FSL_BOOK3E */
-			hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
+			*hpdp = __hugepd(((unsigned long)new & ~PD_HUGE) | pshift);
 #endif
+		}
 	}
 	/* If we bailed from the for loop early, an error occurred, clean up */
 	if (i < num_hugepd) {
 		for (i = i - 1 ; i >= 0; i--, hpdp--)
-			hpdp->pd = 0;
+			*hpdp = __hugepd(0);
 		kmem_cache_free(cachep, new);
 	}
 	spin_unlock(&mm->page_table_lock);
 		return;
 	for (i = 0; i < num_hugepd; i++, hpdp++)
-		hpdp->pd = 0;
+		*hpdp = __hugepd(0);
 	if (shift >= pdshift)
 		hugepd_free(tlb, hugepte);
 		 * if we have pdshift and shift value same, we don't
 		 * use pgt cache for hugepd.
 		 */
-		if (pdshift > shift) {
+		if (pdshift > shift)
 			pgtable_cache_add(pdshift - shift, NULL);
-			if (!PGT_CACHE(pdshift - shift))
-				panic("hugetlbpage_init(): could not create "
-				      "pgtable cache for %d bit pagesize\n", shift);
-		}
 #if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx)
 		else if (!hugepte_cache) {
 			/*
 	else if (mmu_psize_defs[MMU_PAGE_2M].shift)
 		HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_2M].shift;
 #endif
-	else
-		panic("%s: Unable to set default huge page size\n", __func__);
 	return 0;
 }

arch/powerpc/mm/init-common.c+5−8

 	align = max_t(unsigned long, align, minalign);
 	name = kasprintf(GFP_KERNEL, "pgtable-2^%d", shift);
 	new = kmem_cache_create(name, table_size, align, 0, ctor);
+	if (!new)
+		panic("Could not allocate pgtable cache for order %d", shift);
 	kfree(name);
 	pgtable_cache[shift - 1] = new;
 	pr_debug("Allocated pgtable cache for order %d\n", shift);
 }
 EXPORT_SYMBOL_GPL(pgtable_cache_add);	/* used by kvm_hv module */
 {
 	pgtable_cache_add(PGD_INDEX_SIZE, pgd_ctor);
-	if (PMD_INDEX_SIZE && !PGT_CACHE(PMD_INDEX_SIZE))
+	if (PMD_CACHE_INDEX && !PGT_CACHE(PMD_CACHE_INDEX))
 		pgtable_cache_add(PMD_CACHE_INDEX, pmd_ctor);
 	/*
 	 * In all current configs, when the PUD index exists it's the
 	 */
 	if (PUD_INDEX_SIZE && !PGT_CACHE(PUD_INDEX_SIZE))
 		pgtable_cache_add(PUD_INDEX_SIZE, pud_ctor);
-	if (!PGT_CACHE(PGD_INDEX_SIZE))
-		panic("Couldn't allocate pgd cache");
-	if (PMD_INDEX_SIZE && !PGT_CACHE(PMD_INDEX_SIZE))
-		panic("Couldn't allocate pmd pgtable caches");
-	if (PUD_INDEX_SIZE && !PGT_CACHE(PUD_INDEX_SIZE))
-		panic("Couldn't allocate pud pgtable caches");
 }

arch/powerpc/mm/pgtable-book3s64.c+18−0

@@ -126,3 +126,21 @@ void mmu_cleanup_all(void) · 125 unmodified lines
126	else if (mmu_hash_ops.hpte_clear_all)	126	else if (mmu_hash_ops.hpte_clear_all)
127	mmu_hash_ops.hpte_clear_all();	127	mmu_hash_ops.hpte_clear_all();
128	}	128	}
		129
		130	#ifdef CONFIG_MEMORY_HOTPLUG
		131	int create_section_mapping(unsigned long start, unsigned long end)
		132	{
		133	if (radix_enabled())
		134	return -ENODEV;
		135
		136	return hash__create_section_mapping(start, end);
		137	}
		138
		139	int remove_section_mapping(unsigned long start, unsigned long end)
		140	{
		141	if (radix_enabled())
		142	return -ENODEV;
		143
		144	return hash__remove_section_mapping(start, end);
		145	}
		146	#endif /* CONFIG_MEMORY_HOTPLUG */

arch/powerpc/perf/core-book3s.c+2−0

 	 */
 	if (TRAP(regs) != 0xf00)
 		use_siar = 0;
+	else if ((ppmu->flags & PPMU_NO_SIAR))
+		use_siar = 0;
 	else if (marked)
 		use_siar = 1;
 	else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))

arch/powerpc/perf/power9-events-list.h+1−1

@@ -16,7 +16,7 @@ EVENT(PM_CYC, 0x0001e) · 15 unmodified lines
16	EVENT(PM_ICT_NOSLOT_CYC, 0x100f8)	16	EVENT(PM_ICT_NOSLOT_CYC, 0x100f8)
17	EVENT(PM_CMPLU_STALL, 0x1e054)	17	EVENT(PM_CMPLU_STALL, 0x1e054)
18	EVENT(PM_INST_CMPL, 0x00002)	18	EVENT(PM_INST_CMPL, 0x00002)
19	EVENT(PM_BRU_CMPL, 0x40060)	19	EVENT(PM_BRU_CMPL, 0x10012)
20	EVENT(PM_BR_MPRED_CMPL, 0x400f6)	20	EVENT(PM_BR_MPRED_CMPL, 0x400f6)
21		21
22	/* All L1 D cache load references counted at finish, gated by reject */	22	/* All L1 D cache load references counted at finish, gated by reject */

arch/powerpc/perf/power9-pmu.c+1−1

@@ -384,7 +384,7 @@ static struct power_pmu power9_isa207_pmu = { · 383 unmodified lines
384	.bhrb_filter_map = power9_bhrb_filter_map,	384	.bhrb_filter_map = power9_bhrb_filter_map,
385	.get_constraint = isa207_get_constraint,	385	.get_constraint = isa207_get_constraint,
386	.disable_pmc = isa207_disable_pmc,	386	.disable_pmc = isa207_disable_pmc,
387	.flags = PPMU_HAS_SIER \| PPMU_ARCH_207S,	387	.flags = PPMU_NO_SIAR \| PPMU_ARCH_207S,
388	.n_generic = ARRAY_SIZE(power9_generic_events),	388	.n_generic = ARRAY_SIZE(power9_generic_events),
389	.generic_events = power9_generic_events,	389	.generic_events = power9_generic_events,
390	.cache_events = &power9_cache_events,	390	.cache_events = &power9_cache_events,

arch/powerpc/sysdev/xics/icp-opal.c+24−7

 #include <asm/xics.h>
 #include <asm/io.h>
 #include <asm/opal.h>
+#include <asm/kvm_ppc.h>
 static void icp_opal_teardown_cpu(void)
 {
 	 * Should we be flagging idle loop instead?
 	 * Or creating some task to be scheduled?
 	 */
-	opal_int_eoi((0x00 << 24) | XICS_IPI);
+	if (opal_int_eoi((0x00 << 24) | XICS_IPI) > 0)
+		force_external_irq_replay();
+}
+static unsigned int icp_opal_get_xirr(void)
+{
+	unsigned int kvm_xirr;
+	__be32 hw_xirr;
+	int64_t rc;
+	/* Handle an interrupt latched by KVM first */
+	kvm_xirr = kvmppc_get_xics_latch();
+	if (kvm_xirr)
+		return kvm_xirr;
+	/* Then ask OPAL */
+	rc = opal_int_get_xirr(&hw_xirr, false);
+	if (rc < 0)
+		return 0;
+	return be32_to_cpu(hw_xirr);
 }
 static unsigned int icp_opal_get_irq(void)
 	unsigned int xirr;
 	unsigned int vec;
 	unsigned int irq;
-	int64_t rc;
-	rc = opal_int_get_xirr(&xirr, false);
+	xirr = icp_opal_get_xirr();
-	if (rc < 0)
-		return 0;
-	xirr = be32_to_cpu(xirr);
 	vec = xirr & 0x00ffffff;
 	if (vec == XICS_IRQ_SPURIOUS)
 		return 0;
 	xics_mask_unknown_vec(vec);
 	/* We might learn about it later, so EOI it */
-	opal_int_eoi(xirr);
+	if (opal_int_eoi(xirr) > 0)
+		force_external_irq_replay();
 	return 0;
 }

arch/s390/configs/default_defconfig+13−14

 CONFIG_CMA_DEBUG=y
 CONFIG_CMA_DEBUGFS=y
 CONFIG_MEM_SOFT_DIRTY=y
-CONFIG_ZPOOL=m
+CONFIG_ZSWAP=y
 CONFIG_ZBUD=m
 CONFIG_ZSMALLOC=m
 CONFIG_ZSMALLOC_STAT=y
 CONFIG_NF_CONNTRACK_EVENTS=y
 CONFIG_NF_CONNTRACK_TIMEOUT=y
 CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CT_PROTO_DCCP=m
-CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
 CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NFT_EXTHDR=m
 CONFIG_NFT_META=m
 CONFIG_NFT_CT=m
-CONFIG_NFT_RBTREE=m
-CONFIG_NFT_HASH=m
 CONFIG_NFT_COUNTER=m
 CONFIG_NFT_LOG=m
 CONFIG_NFT_LIMIT=m
 CONFIG_NFT_NAT=m
 CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
 CONFIG_NETFILTER_XT_SET=m
 CONFIG_NETFILTER_XT_TARGET_AUDIT=m
 CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_MATCH_RATEEST=m
 CONFIG_NETFILTER_XT_MATCH_REALM=m
 CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
 CONFIG_NETFILTER_XT_MATCH_STATE=m
 CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_IP_VS_FTP=m
 CONFIG_IP_VS_PE_SIP=m
 CONFIG_NF_CONNTRACK_IPV4=m
-# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
 CONFIG_NF_TABLES_IPV4=m
 CONFIG_NFT_CHAIN_ROUTE_IPV4=m
 CONFIG_NF_TABLES_ARP=m
 CONFIG_IFB=m
 CONFIG_MACVLAN=m
 CONFIG_MACVTAP=m
-CONFIG_IPVLAN=m
 CONFIG_VXLAN=m
 CONFIG_TUN=m
 CONFIG_VETH=m
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
 CONFIG_JBD2_DEBUG=y
 CONFIG_JFS_FS=m
 CONFIG_JFS_POSIX_ACL=y
 CONFIG_DEBUG_LOCKDEP=y
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 CONFIG_DEBUG_LOCKING_API_SELFTESTS=y
-CONFIG_DEBUG_LIST=y
 CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_NOTIFIERS=y
 CONFIG_DEBUG_CREDENTIALS=y
 CONFIG_RCU_TORTURE_TEST=m
 CONFIG_RCU_CPU_STALL_TIMEOUT=300
 CONFIG_NOTIFIER_ERROR_INJECTION=m
-CONFIG_CPU_NOTIFIER_ERROR_INJECT=m
 CONFIG_PM_NOTIFIER_ERROR_INJECT=m
 CONFIG_FAULT_INJECTION=y
 CONFIG_FAILSLAB=y
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_UPROBE_EVENT=y
 CONFIG_FUNCTION_PROFILER=y
+CONFIG_HIST_TRIGGERS=y
 CONFIG_TRACE_ENUM_MAP_FILE=y
 CONFIG_LKDTM=m
 CONFIG_TEST_LIST_SORT=y
 CONFIG_TEST_KSTRTOX=y
 CONFIG_DMA_API_DEBUG=y
 CONFIG_TEST_BPF=m
+CONFIG_BUG_ON_DATA_CORRUPTION=y
 CONFIG_S390_PTDUMP=y
 CONFIG_ENCRYPTED_KEYS=m
 CONFIG_SECURITY=y
 CONFIG_SECURITY_SELINUX_DISABLE=y
 CONFIG_IMA=y
 CONFIG_IMA_APPRAISE=y
+CONFIG_CRYPTO_RSA=m
+CONFIG_CRYPTO_DH=m
+CONFIG_CRYPTO_ECDH=m
 CONFIG_CRYPTO_USER=m
-# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_CCM=m
 CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_KEYWRAP=m
 CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_LZO=m
+CONFIG_CRYPTO_842=m
 CONFIG_CRYPTO_LZ4=m
 CONFIG_CRYPTO_LZ4HC=m
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_AEAD=m
 CONFIG_ZCRYPT=m
 CONFIG_CRYPTO_SHA1_S390=m
 CONFIG_CRYPTO_SHA256_S390=m

arch/s390/configs/gcov_defconfig+30−20

 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_NUMA_BALANCING=y
+# CONFIG_NUMA_BALANCING_DEFAULT_ENABLED is not set
 CONFIG_MEMCG=y
 CONFIG_MEMCG_SWAP=y
 CONFIG_BLK_CGROUP=y
 CONFIG_UNIXWARE_DISKLABEL=y
 CONFIG_CFQ_GROUP_IOSCHED=y
 CONFIG_DEFAULT_DEADLINE=y
+CONFIG_LIVEPATCH=y
 CONFIG_TUNE_ZEC12=y
-CONFIG_NR_CPUS=256
+CONFIG_NR_CPUS=512
 CONFIG_NUMA=y
 CONFIG_HZ_100=y
 CONFIG_MEMORY_HOTPLUG=y
 CONFIG_CLEANCACHE=y
 CONFIG_FRONTSWAP=y
 CONFIG_CMA=y
+CONFIG_MEM_SOFT_DIRTY=y
 CONFIG_ZSWAP=y
 CONFIG_ZBUD=m
 CONFIG_ZSMALLOC=m
 CONFIG_NF_CONNTRACK_EVENTS=y
 CONFIG_NF_CONNTRACK_TIMEOUT=y
 CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CT_PROTO_DCCP=m
-CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
 CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NFT_EXTHDR=m
 CONFIG_NFT_META=m
 CONFIG_NFT_CT=m
-CONFIG_NFT_RBTREE=m
-CONFIG_NFT_HASH=m
 CONFIG_NFT_COUNTER=m
 CONFIG_NFT_LOG=m
 CONFIG_NFT_LIMIT=m
 CONFIG_NFT_NAT=m
 CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
 CONFIG_NETFILTER_XT_SET=m
 CONFIG_NETFILTER_XT_TARGET_AUDIT=m
 CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_MATCH_RATEEST=m
 CONFIG_NETFILTER_XT_MATCH_REALM=m
 CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
 CONFIG_NETFILTER_XT_MATCH_STATE=m
 CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_IP_VS_FTP=m
 CONFIG_IP_VS_PE_SIP=m
 CONFIG_NF_CONNTRACK_IPV4=m
-# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
 CONFIG_NF_TABLES_IPV4=m
 CONFIG_NFT_CHAIN_ROUTE_IPV4=m
 CONFIG_NF_TABLES_ARP=m
 CONFIG_IFB=m
 CONFIG_MACVLAN=m
 CONFIG_MACVTAP=m
-CONFIG_IPVLAN=m
 CONFIG_VXLAN=m
 CONFIG_TUN=m
 CONFIG_VETH=m
 CONFIG_RAW_DRIVER=m
 CONFIG_HANGCHECK_TIMER=m
 CONFIG_TN3270_FS=y
+# CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_SOFT_WATCHDOG=m
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
 CONFIG_JBD2_DEBUG=y
 CONFIG_JFS_FS=m
 CONFIG_JFS_POSIX_ACL=y
 CONFIG_FUSE_FS=y
 CONFIG_CUSE=m
 CONFIG_OVERLAY_FS=m
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
 CONFIG_FSCACHE=m
 CONFIG_CACHEFILES=m
 CONFIG_ISO9660_FS=y
 CONFIG_UNUSED_SYMBOLS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m
 CONFIG_PANIC_ON_OOPS=y
 CONFIG_TIMER_STATS=y
 CONFIG_RCU_TORTURE_TEST=m
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
-CONFIG_NOTIFIER_ERROR_INJECTION=m
-CONFIG_CPU_NOTIFIER_ERROR_INJECT=m
-CONFIG_PM_NOTIFIER_ERROR_INJECT=m
 CONFIG_LATENCYTOP=y
+CONFIG_SCHED_TRACER=y
+CONFIG_FTRACE_SYSCALLS=y
+CONFIG_STACK_TRACER=y
 CONFIG_BLK_DEV_IO_TRACE=y
-# CONFIG_KPROBE_EVENT is not set
+CONFIG_UPROBE_EVENT=y
+CONFIG_FUNCTION_PROFILER=y
+CONFIG_HIST_TRIGGERS=y
 CONFIG_TRACE_ENUM_MAP_FILE=y
 CONFIG_LKDTM=m
-CONFIG_RBTREE_TEST=m
-CONFIG_INTERVAL_TREE_TEST=m
 CONFIG_PERCPU_TEST=m
 CONFIG_ATOMIC64_SELFTEST=y
 CONFIG_TEST_BPF=m
+CONFIG_BUG_ON_DATA_CORRUPTION=y
 CONFIG_S390_PTDUMP=y
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_BIG_KEYS=y
 CONFIG_ENCRYPTED_KEYS=m
 CONFIG_SECURITY=y
 CONFIG_SECURITY_NETWORK=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
 CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_INTEGRITY_SIGNATURE=y
+CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
 CONFIG_IMA=y
+CONFIG_IMA_WRITE_POLICY=y
 CONFIG_IMA_APPRAISE=y
+CONFIG_CRYPTO_DH=m
+CONFIG_CRYPTO_ECDH=m
 CONFIG_CRYPTO_USER=m
 # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_PCRYPT=m
 CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_MCRYPTD=m
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_CCM=m
 CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_KEYWRAP=m
 CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_SHA3=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_842=m
 CONFIG_CRYPTO_LZ4=m
 CONFIG_CRYPTO_LZ4HC=m
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_AEAD=m
 CONFIG_ZCRYPT=m
 CONFIG_CRYPTO_SHA1_S390=m
 CONFIG_CRYPTO_SHA256_S390=m
 CONFIG_CRYPTO_AES_S390=m
 CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_CRC32_S390=y
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=m
 CONFIG_CRC7=m
 CONFIG_CRC8=m
 CONFIG_CORDIC=m

arch/s390/configs/performance_defconfig+21−12

 CONFIG_CLEANCACHE=y
 CONFIG_FRONTSWAP=y
 CONFIG_CMA=y
+CONFIG_MEM_SOFT_DIRTY=y
 CONFIG_ZSWAP=y
 CONFIG_ZBUD=m
 CONFIG_ZSMALLOC=m
 CONFIG_NF_CONNTRACK_EVENTS=y
 CONFIG_NF_CONNTRACK_TIMEOUT=y
 CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CT_PROTO_DCCP=m
-CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
 CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NFT_EXTHDR=m
 CONFIG_NFT_META=m
 CONFIG_NFT_CT=m
-CONFIG_NFT_RBTREE=m
-CONFIG_NFT_HASH=m
 CONFIG_NFT_COUNTER=m
 CONFIG_NFT_LOG=m
 CONFIG_NFT_LIMIT=m
 CONFIG_NFT_NAT=m
 CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
 CONFIG_NETFILTER_XT_SET=m
 CONFIG_NETFILTER_XT_TARGET_AUDIT=m
 CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_MATCH_RATEEST=m
 CONFIG_NETFILTER_XT_MATCH_REALM=m
 CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
 CONFIG_NETFILTER_XT_MATCH_STATE=m
 CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_IP_VS_FTP=m
 CONFIG_IP_VS_PE_SIP=m
 CONFIG_NF_CONNTRACK_IPV4=m
-# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
 CONFIG_NF_TABLES_IPV4=m
 CONFIG_NFT_CHAIN_ROUTE_IPV4=m
 CONFIG_NF_TABLES_ARP=m
 CONFIG_IFB=m
 CONFIG_MACVLAN=m
 CONFIG_MACVTAP=m
-CONFIG_IPVLAN=m
 CONFIG_VXLAN=m
 CONFIG_TUN=m
 CONFIG_VETH=m
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
 CONFIG_JBD2_DEBUG=y
 CONFIG_JFS_FS=m
 CONFIG_JFS_POSIX_ACL=y
 CONFIG_FUSE_FS=y
 CONFIG_CUSE=m
 CONFIG_OVERLAY_FS=m
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
 CONFIG_FSCACHE=m
 CONFIG_CACHEFILES=m
 CONFIG_ISO9660_FS=y
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_UPROBE_EVENT=y
 CONFIG_FUNCTION_PROFILER=y
+CONFIG_HIST_TRIGGERS=y
 CONFIG_TRACE_ENUM_MAP_FILE=y
 CONFIG_LKDTM=m
 CONFIG_PERCPU_TEST=m
 CONFIG_ATOMIC64_SELFTEST=y
 CONFIG_TEST_BPF=m
+CONFIG_BUG_ON_DATA_CORRUPTION=y
 CONFIG_S390_PTDUMP=y
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_BIG_KEYS=y
 CONFIG_ENCRYPTED_KEYS=m
 CONFIG_SECURITY=y
 CONFIG_SECURITY_NETWORK=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
 CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_INTEGRITY_SIGNATURE=y
+CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
 CONFIG_IMA=y
+CONFIG_IMA_WRITE_POLICY=y
 CONFIG_IMA_APPRAISE=y
+CONFIG_CRYPTO_DH=m
+CONFIG_CRYPTO_ECDH=m
 CONFIG_CRYPTO_USER=m
 # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_PCRYPT=m
 CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_MCRYPTD=m
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_CCM=m
 CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_KEYWRAP=m
 CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_SHA3=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_842=m
 CONFIG_CRYPTO_LZ4=m
 CONFIG_CRYPTO_LZ4HC=m
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_AEAD=m
 CONFIG_ZCRYPT=m
 CONFIG_CRYPTO_SHA1_S390=m
 CONFIG_CRYPTO_SHA256_S390=m
 CONFIG_CRYPTO_AES_S390=m
 CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_CRC32_S390=y
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=m
 CONFIG_CRC7=m
 CONFIG_CRC8=m
 CONFIG_CORDIC=m

arch/s390/defconfig+3−2

 CONFIG_STATIC_KEYS_SELFTEST=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
 CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_IBM_PARTITION=y
 CONFIG_EQUALIZER=m
 CONFIG_TUN=m
 CONFIG_VIRTIO_NET=y
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
+CONFIG_DEVKMEM=y
 CONFIG_RAW_DRIVER=m
 CONFIG_VIRTIO_BALLOON=y
 CONFIG_EXT4_FS=y
 CONFIG_KPROBES_SANITY_TEST=y
 CONFIG_S390_PTDUMP=y
 CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_CCM=m
 CONFIG_CRYPTO_GCM=m

arch/s390/include/asm/ctl_reg.h+3−1

 	BUILD_BUG_ON(sizeof(addrtype) != (high - low + 1) * sizeof(long));\
 	asm volatile(							\
 		"	lctlg	%1,%2,%0\n"				\
-		: : "Q" (*(addrtype *)(&array)), "i" (low), "i" (high));\
+		:							\
+		: "Q" (*(addrtype *)(&array)), "i" (low), "i" (high)	\
+		: "memory");						\
 }
 #define __ctl_store(array, low, high) {					\

arch/x86/events/amd/ibs.c+1−1

@@ -1010,7 +1010,7 @@ static __init int amd_ibs_init(void) · 1009 unmodified lines
1010	* all online cpus.	1010	* all online cpus.
1011	*/	1011	*/
1012	cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,	1012	cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
1013	"perf/x86/amd/ibs:STARTING",	1013	"perf/x86/amd/ibs:starting",
1014	x86_pmu_amd_ibs_starting_cpu,	1014	x86_pmu_amd_ibs_starting_cpu,
1015	x86_pmu_amd_ibs_dying_cpu);	1015	x86_pmu_amd_ibs_dying_cpu);
1016		1016

arch/x86/events/intel/core.c+5−2

 	if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
 		for_each_cpu(i, topology_sibling_cpumask(cpu)) {
+			struct cpu_hw_events *sibling;
 			struct intel_excl_cntrs *c;
-			c = per_cpu(cpu_hw_events, i).excl_cntrs;
+			sibling = &per_cpu(cpu_hw_events, i);
+			c = sibling->excl_cntrs;
 			if (c && c->core_id == core_id) {
 				cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
 				cpuc->excl_cntrs = c;
-				cpuc->excl_thread_id = 1;
+				if (!sibling->excl_thread_id)
+					cpuc->excl_thread_id = 1;
 				break;
 			}
 		}

arch/x86/kernel/apic/io_apic.c+2−0

 	.irq_ack		= irq_chip_ack_parent,
 	.irq_eoi		= ioapic_ack_level,
 	.irq_set_affinity	= ioapic_set_affinity,
+	.irq_retrigger		= irq_chip_retrigger_hierarchy,
 	.flags			= IRQCHIP_SKIP_SET_WAKE,
 };
 	.irq_ack		= irq_chip_ack_parent,
 	.irq_eoi		= ioapic_ir_ack_level,
 	.irq_set_affinity	= ioapic_set_affinity,
+	.irq_retrigger		= irq_chip_retrigger_hierarchy,
 	.flags			= IRQCHIP_SKIP_SET_WAKE,
 };

arch/x86/kvm/x86.c+2−1

@@ -6263,7 +6263,8 @@ static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) · 6262 unmodified lines
6263		6263
6264	kvm_x86_ops->patch_hypercall(vcpu, instruction);	6264	kvm_x86_ops->patch_hypercall(vcpu, instruction);
6265		6265
6266	return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);	6266	return emulator_write_emulated(ctxt, rip, instruction, 3,
		6267	&ctxt->exception);
6267	}	6268	}
6268		6269
6269	static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)	6270	static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)

arch/x86/pci/acpi.c+10−0

@@ -114,6 +114,16 @@ static const struct dmi_system_id pci_crs_quirks[] __initconst = { · 113 unmodified lines
114	DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),	114	DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),
115	},	115	},
116	},	116	},
		117	/* https://bugzilla.kernel.org/show_bug.cgi?id=42606 */
		118	{
		119	.callback = set_nouse_crs,
		120	.ident = "Supermicro X8DTH",
		121	.matches = {
		122	DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
		123	DMI_MATCH(DMI_PRODUCT_NAME, "X8DTH-i/6/iF/6F"),
		124	DMI_MATCH(DMI_BIOS_VERSION, "2.0a"),
		125	},
		126	},
117		127
118	/* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */	128	/* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */
119	{	129	{

block/blk-mq.c+0−1

@@ -912,7 +912,6 @@ bool blk_mq_dispatch_rq_list(struct blk_mq_hw_ctx hctx, struct list_head list) · 911 unmodified lines
912	static void blk_mq_process_rq_list(struct blk_mq_hw_ctx *hctx)	912	static void blk_mq_process_rq_list(struct blk_mq_hw_ctx *hctx)
913	{	913	{
914	LIST_HEAD(rq_list);	914	LIST_HEAD(rq_list);
915	LIST_HEAD(driver_list);
916		915
917	if (unlikely(blk_mq_hctx_stopped(hctx)))	916	if (unlikely(blk_mq_hctx_stopped(hctx)))
918	return;	917	return;

drivers/block/nbd.c+2−4

 static int nbd_send_cmd(struct nbd_device *nbd, struct nbd_cmd *cmd, int index)
 {
 	struct request *req = blk_mq_rq_from_pdu(cmd);
-	int result, flags;
+	int result;
 	struct nbd_request request;
 	unsigned long size = blk_rq_bytes(req);
 	struct bio *bio;
 	if (type != NBD_CMD_WRITE)
 		return 0;
-	flags = 0;
 	bio = req->bio;
 	while (bio) {
 		struct bio *next = bio->bi_next;
 		bio_for_each_segment(bvec, bio, iter) {
 			bool is_last = !next && bio_iter_last(bvec, iter);
+			int flags = is_last ? 0 : MSG_MORE;
-			if (is_last)
-				flags = MSG_MORE;
 			dev_dbg(nbd_to_dev(nbd), "request %p: sending %d bytes data\n",
 				cmd, bvec.bv_len);
 			result = sock_send_bvec(nbd, index, &bvec, flags);

drivers/char/virtio_console.c+1−1

@@ -1862,7 +1862,7 @@ static void config_work_handler(struct work_struct *work) · 1861 unmodified lines
1862	{	1862	{
1863	struct ports_device *portdev;	1863	struct ports_device *portdev;
1864		1864
1865	portdev = container_of(work, struct ports_device, control_work);	1865	portdev = container_of(work, struct ports_device, config_work);
1866	if (!use_multiport(portdev)) {	1866	if (!use_multiport(portdev)) {
1867	struct virtio_device *vdev;	1867	struct virtio_device *vdev;
1868	struct port *port;	1868	struct port *port;

drivers/clk/samsung/clk-exynos5420.c+7−7

drivers/clocksource/exynos_mct.c+1−0

@@ -495,6 +495,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) · 494 unmodified lines
495	if (mct_int_type == MCT_INT_SPI) {	495	if (mct_int_type == MCT_INT_SPI) {
496	if (evt->irq != -1)	496	if (evt->irq != -1)
497	disable_irq_nosync(evt->irq);	497	disable_irq_nosync(evt->irq);
		498	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
498	} else {	499	} else {
499	disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);	500	disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
500	}	501	}

drivers/hid/hid-corsair.c+45−15

 	struct usb_interface *usbif = to_usb_interface(dev->parent);
 	struct usb_device *usbdev = interface_to_usbdev(usbif);
 	int brightness;
-	char data[8];
+	char *data;
+	data = kmalloc(8, GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
 	ret = usb_control_msg(usbdev, usb_rcvctrlpipe(usbdev, 0),
 			      K90_REQUEST_STATUS,
 			      USB_DIR_IN | USB_TYPE_VENDOR |
 			      USB_RECIP_DEVICE, 0, 0, data, 8,
 			      USB_CTRL_SET_TIMEOUT);
-	if (ret < 0) {
+	if (ret < 5) {
 		dev_warn(dev, "Failed to get K90 initial state (error %d).\n",
 			 ret);
-		return -EIO;
+		ret = -EIO;
+		goto out;
 	}
 	brightness = data[4];
 	if (brightness < 0 || brightness > 3) {
 		dev_warn(dev,
 			 "Read invalid backlight brightness: %02hhx.\n",
 			 data[4]);
-		return -EIO;
+		ret = -EIO;
+		goto out;
 	}
-	return brightness;
+	ret = brightness;
+out:
+	kfree(data);
+	return ret;
 }
 static enum led_brightness k90_record_led_get(struct led_classdev *led_cdev)
 	struct usb_interface *usbif = to_usb_interface(dev->parent);
 	struct usb_device *usbdev = interface_to_usbdev(usbif);
 	const char *macro_mode;
-	char data[8];
+	char *data;
+	data = kmalloc(2, GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
 	ret = usb_control_msg(usbdev, usb_rcvctrlpipe(usbdev, 0),
 			      K90_REQUEST_GET_MODE,
 			      USB_DIR_IN | USB_TYPE_VENDOR |
 			      USB_RECIP_DEVICE, 0, 0, data, 2,
 			      USB_CTRL_SET_TIMEOUT);
-	if (ret < 0) {
+	if (ret < 1) {
 		dev_warn(dev, "Failed to get K90 initial mode (error %d).\n",
 			 ret);
-		return -EIO;
+		ret = -EIO;
+		goto out;
 	}
 	switch (data[0]) {
 	default:
 		dev_warn(dev, "K90 in unknown mode: %02hhx.\n",
 			 data[0]);
-		return -EIO;
+		ret = -EIO;
+		goto out;
 	}
-	return snprintf(buf, PAGE_SIZE, "%s\n", macro_mode);
+	ret = snprintf(buf, PAGE_SIZE, "%s\n", macro_mode);
+out:
+	kfree(data);
+	return ret;
 }
 static ssize_t k90_store_macro_mode(struct device *dev,
 	struct usb_interface *usbif = to_usb_interface(dev->parent);
 	struct usb_device *usbdev = interface_to_usbdev(usbif);
 	int current_profile;
-	char data[8];
+	char *data;
+	data = kmalloc(8, GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
 	ret = usb_control_msg(usbdev, usb_rcvctrlpipe(usbdev, 0),
 			      K90_REQUEST_STATUS,
 			      USB_DIR_IN | USB_TYPE_VENDOR |
 			      USB_RECIP_DEVICE, 0, 0, data, 8,
 			      USB_CTRL_SET_TIMEOUT);
-	if (ret < 0) {
+	if (ret < 8) {
 		dev_warn(dev, "Failed to get K90 initial state (error %d).\n",
 			 ret);
-		return -EIO;
+		ret = -EIO;
+		goto out;
 	}
 	current_profile = data[7];
 	if (current_profile < 1 || current_profile > 3) {
 		dev_warn(dev, "Read invalid current profile: %02hhx.\n",
 			 data[7]);
-		return -EIO;
+		ret = -EIO;
+		goto out;
 	}
-	return snprintf(buf, PAGE_SIZE, "%d\n", current_profile);
+	ret = snprintf(buf, PAGE_SIZE, "%d\n", current_profile);
+out:
+	kfree(data);
+	return ret;
 }
 static ssize_t k90_store_current_profile(struct device *dev,

drivers/hid/wacom_sys.c+8−8

 		return retval;
 	}
+	if (wacom_wac->features.device_type & WACOM_DEVICETYPE_TOUCH)
+		wacom_wac->shared->touch = hdev;
+	else if (wacom_wac->features.device_type & WACOM_DEVICETYPE_PEN)
+		wacom_wac->shared->pen = hdev;
 out:
 	mutex_unlock(&wacom_udev_list_lock);
 	return retval;
 	if (error)
 		goto fail;
-	error = wacom_add_shared_data(hdev);
-	if (error)
-		goto fail;
 	/*
 	 * Bamboo Pad has a generic hid handling for the Pen, and we switch it
 	 * into debug mode for the touch part.
 	wacom_update_name(wacom, wireless ? " (WL)" : "");
-	if (wacom_wac->features.device_type & WACOM_DEVICETYPE_TOUCH)
+	error = wacom_add_shared_data(hdev);
-		wacom_wac->shared->touch = hdev;
+	if (error)
-	else if (wacom_wac->features.device_type & WACOM_DEVICETYPE_PEN)
+		goto fail;
-		wacom_wac->shared->pen = hdev;
 	if (!(features->device_type & WACOM_DEVICETYPE_WL_MONITOR) &&
 	     (features->quirks & WACOM_QUIRK_BATTERY)) {

drivers/hid/wacom_wac.c+10−0

@@ -2187,6 +2187,16 @@ void wacom_wac_report(struct hid_device hdev, struct hid_report report) · 2186 unmodified lines
2187		2187
2188	wacom_report_events(hdev, report);	2188	wacom_report_events(hdev, report);
2189		2189
		2190	/*
		2191	* Non-input reports may be sent prior to the device being
		2192	* completely initialized. Since only their events need
		2193	* to be processed, exit after 'wacom_report_events' has
		2194	* been called to prevent potential crashes in the report-
		2195	* processing functions.
		2196	*/
		2197	if (report->type != HID_INPUT_REPORT)
		2198	return;
		2199
2190	if (WACOM_PAD_FIELD(field)) {	2200	if (WACOM_PAD_FIELD(field)) {
2191	wacom_wac_pad_battery_report(hdev, report);	2201	wacom_wac_pad_battery_report(hdev, report);
2192	if (wacom->wacom_wac.pad_input)	2202	if (wacom->wacom_wac.pad_input)

drivers/mmc/core/mmc_ops.c+12−13

 		}
 	} while (busy);
-	if (host->ops->card_busy && send_status)
-		return mmc_switch_status(card);
 	return 0;
 }
 	if (!use_busy_signal)
 		goto out;
-	/* Switch to new timing before poll and check switch status. */
-	if (timing)
-		mmc_set_timing(host, timing);
 	/*If SPI or used HW busy detection above, then we don't need to poll. */
 	if (((host->caps & MMC_CAP_WAIT_WHILE_BUSY) && use_r1b_resp) ||
-		mmc_host_is_spi(host)) {
+		mmc_host_is_spi(host))
-		if (send_status)
-			err = mmc_switch_status(card);
 		goto out_tim;
-	}
 	/* Let's try to poll to find out when the command is completed. */
 	err = mmc_poll_for_busy(card, timeout_ms, send_status, retry_crc_err);
+	if (err)
+		goto out;
 out_tim:
-	if (err && timing)
+	/* Switch to new timing before check switch status. */
-		mmc_set_timing(host, old_timing);
+	if (timing)
+		mmc_set_timing(host, timing);
+	if (send_status) {
+		err = mmc_switch_status(card);
+		if (err && timing)
+			mmc_set_timing(host, old_timing);
+	}
 out:
 	mmc_retune_release(host);

drivers/mmc/host/meson-gx-mmc.c+5−3

 {
 	struct meson_host *host = dev_id;
 	struct mmc_request *mrq;
-	struct mmc_command *cmd = host->cmd;
+	struct mmc_command *cmd;
 	u32 irq_en, status, raw_status;
 	irqreturn_t ret = IRQ_HANDLED;
 	if (WARN_ON(!host))
 		return IRQ_NONE;
+	cmd = host->cmd;
 	mrq = host->mrq;
 	if (WARN_ON(!mrq))
 	int ret = IRQ_HANDLED;
 	if (WARN_ON(!mrq))
-		ret = IRQ_NONE;
+		return IRQ_NONE;
 	if (WARN_ON(!cmd))
-		ret = IRQ_NONE;
+		return IRQ_NONE;
 	data = cmd->data;
 	if (data) {

drivers/mmc/host/mxs-mmc.c+4−2

 	cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
 	cmd1 = cmd->arg;
+	if (cmd->opcode == MMC_STOP_TRANSMISSION)
+		cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
 	if (host->sdio_irq_en) {
 		ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
 		cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
 		       ssp->base + HW_SSP_BLOCK_SIZE);
 	}
-	if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
+	if (cmd->opcode == SD_IO_RW_EXTENDED)
-	    (cmd->opcode == SD_IO_RW_EXTENDED))
 		cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
 	cmd1 = cmd->arg;

drivers/mmc/host/sdhci-acpi.c+2−1

@@ -395,7 +395,8 @@ static int sdhci_acpi_probe(struct platform_device *pdev) · 394 unmodified lines
395	/* Power on the SDHCI controller and its children */	395	/* Power on the SDHCI controller and its children */
396	acpi_device_fix_up_power(device);	396	acpi_device_fix_up_power(device);
397	list_for_each_entry(child, &device->children, node)	397	list_for_each_entry(child, &device->children, node)
398	acpi_device_fix_up_power(child);	398	if (child->status.present && child->status.enabled)
		399	acpi_device_fix_up_power(child);
399		400
400	if (acpi_bus_get_status(device) \|\| !device->status.present)	401	if (acpi_bus_get_status(device) \|\| !device->status.present)
401	return -ENODEV;	402	return -ENODEV;

drivers/mtd/nand/Kconfig+2−1

 config MTD_NAND_OXNAS
 	tristate "NAND Flash support for Oxford Semiconductor SoC"
+	depends on HAS_IOMEM
 	help
 	  This enables the NAND flash controller on Oxford Semiconductor SoCs.
 	  Flexible Static Memory Controller (FSMC)
 config MTD_NAND_XWAY
-	tristate "Support for NAND on Lantiq XWAY SoC"
+	bool "Support for NAND on Lantiq XWAY SoC"
 	depends on LANTIQ && SOC_TYPE_XWAY
 	help
 	  Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached

drivers/mtd/nand/lpc32xx_mlc.c+1−1

@@ -775,7 +775,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev) · 774 unmodified lines
775	init_completion(&host->comp_controller);	775	init_completion(&host->comp_controller);
776		776
777	host->irq = platform_get_irq(pdev, 0);	777	host->irq = platform_get_irq(pdev, 0);
778	if ((host->irq < 0) \|\| (host->irq >= NR_IRQS)) {	778	if (host->irq < 0) {
779	dev_err(&pdev->dev, "failed to get platform irq\n");	779	dev_err(&pdev->dev, "failed to get platform irq\n");
780	res = -EINVAL;	780	res = -EINVAL;
781	goto err_exit3;	781	goto err_exit3;

drivers/mtd/nand/tango_nand.c+3−1

 	if (IS_ERR(nfc->pbus_base))
 		return PTR_ERR(nfc->pbus_base);
+	writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
 	clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
-	nfc->chan = dma_request_chan(&pdev->dev, "nfc_sbox");
+	nfc->chan = dma_request_chan(&pdev->dev, "rxtx");
 	if (IS_ERR(nfc->chan))
 		return PTR_ERR(nfc->chan);

drivers/mtd/nand/xway_nand.c+1−4

 	{ .compatible = "lantiq,nand-xway" },
 	{},
 };
-MODULE_DEVICE_TABLE(of, xway_nand_match);
 static struct platform_driver xway_nand_driver = {
 	.probe	= xway_nand_probe,
 	},
 };
-module_platform_driver(xway_nand_driver);
+builtin_platform_driver(xway_nand_driver);
-MODULE_LICENSE("GPL");

drivers/net/ethernet/broadcom/bcmsysport.c+18−7

 	unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs;
 	unsigned int pkts_compl = 0, bytes_compl = 0;
 	struct bcm_sysport_cb *cb;
-	struct netdev_queue *txq;
 	u32 hw_ind;
-	txq = netdev_get_tx_queue(ndev, ring->index);
 	/* Compute how many descriptors have been processed since last call */
 	hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
 	c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
 	ring->c_index = c_index;
-	if (netif_tx_queue_stopped(txq) && pkts_compl)
-		netif_tx_wake_queue(txq);
 	netif_dbg(priv, tx_done, ndev,
 		  "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
 		  ring->index, ring->c_index, pkts_compl, bytes_compl);
 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
 					   struct bcm_sysport_tx_ring *ring)
 {
+	struct netdev_queue *txq;
 	unsigned int released;
 	unsigned long flags;
+	txq = netdev_get_tx_queue(priv->netdev, ring->index);
 	spin_lock_irqsave(&ring->lock, flags);
 	released = __bcm_sysport_tx_reclaim(priv, ring);
+	if (released)
+		netif_tx_wake_queue(txq);
 	spin_unlock_irqrestore(&ring->lock, flags);
 	return released;
 }
+/* Locked version of the per-ring TX reclaim, but does not wake the queue */
+static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv,
+				 struct bcm_sysport_tx_ring *ring)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&ring->lock, flags);
+	__bcm_sysport_tx_reclaim(priv, ring);
+	spin_unlock_irqrestore(&ring->lock, flags);
+}
 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
 {
 	struct bcm_sysport_tx_ring *ring =
 	napi_disable(&ring->napi);
 	netif_napi_del(&ring->napi);
-	bcm_sysport_tx_reclaim(priv, ring);
+	bcm_sysport_tx_clean(priv, ring);
 	kfree(ring->cbs);
 	ring->cbs = NULL;

drivers/net/ethernet/cavium/thunder/thunder_bgx.c+6−5

 struct bgx {
 	u8			bgx_id;
 	struct	lmac		lmac[MAX_LMAC_PER_BGX];
-	int			lmac_count;
+	u8			lmac_count;
 	u8			max_lmac;
+	u8                      acpi_lmac_idx;
 	void __iomem		*reg_base;
 	struct pci_dev		*pdev;
 	bool                    is_dlm;
 	if (acpi_bus_get_device(handle, &adev))
 		goto out;
-	acpi_get_mac_address(dev, adev, bgx->lmac[bgx->lmac_count].mac);
+	acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
-	SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, dev);
+	SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
-	bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
+	bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
+	bgx->acpi_lmac_idx++; /* move to next LMAC */
 out:
-	bgx->lmac_count++;
 	return AE_OK;
 }

drivers/net/ethernet/emulex/benet/be_cmds.c+1−1

@@ -1118,7 +1118,7 @@ int be_cmd_pmac_add(struct be_adapter adapter, u8 mac_addr, · 1117 unmodified lines
1118	err:	1118	err:
1119	mutex_unlock(&adapter->mcc_lock);	1119	mutex_unlock(&adapter->mcc_lock);
1120		1120
1121	if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)	1121	if (base_status(status) == MCC_STATUS_UNAUTHORIZED_REQUEST)
1122	status = -EPERM;	1122	status = -EPERM;
1123		1123
1124	return status;	1124	return status;

drivers/net/ethernet/emulex/benet/be_main.c+15−3

 	if (ether_addr_equal(addr->sa_data, adapter->dev_mac))
 		return 0;
+	/* BE3 VFs without FILTMGMT privilege are not allowed to set its MAC
+	 * address
+	 */
+	if (BEx_chip(adapter) && be_virtfn(adapter) &&
+	    !check_privilege(adapter, BE_PRIV_FILTMGMT))
+		return -EPERM;
 	/* if device is not running, copy MAC to netdev->dev_addr */
 	if (!netif_running(netdev))
 		goto done;
 static void be_disable_if_filters(struct be_adapter *adapter)
 {
-	be_dev_mac_del(adapter, adapter->pmac_id[0]);
+	/* Don't delete MAC on BE3 VFs without FILTMGMT privilege  */
+	if (!BEx_chip(adapter) || !be_virtfn(adapter) ||
+	    check_privilege(adapter, BE_PRIV_FILTMGMT))
+		be_dev_mac_del(adapter, adapter->pmac_id[0]);
 	be_clear_uc_list(adapter);
 	be_clear_mc_list(adapter);
 	if (status)
 		return status;
-	/* For BE3 VFs, the PF programs the initial MAC address */
+	/* Don't add MAC on BE3 VFs without FILTMGMT privilege */
-	if (!(BEx_chip(adapter) && be_virtfn(adapter))) {
+	if (!BEx_chip(adapter) || !be_virtfn(adapter) ||
+	    check_privilege(adapter, BE_PRIV_FILTMGMT)) {
 		status = be_dev_mac_add(adapter, adapter->netdev->dev_addr);
 		if (status)
 			return status;

drivers/net/ethernet/mellanox/mlx4/cq.c+20−18

 {
 	struct mlx4_cq *cq;
+	rcu_read_lock();
 	cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
 			       cqn & (dev->caps.num_cqs - 1));
+	rcu_read_unlock();
 	if (!cq) {
 		mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
 		return;
 	}
+	/* Acessing the CQ outside of rcu_read_lock is safe, because
+	 * the CQ is freed only after interrupt handling is completed.
+	 */
 	++cq->arm_sn;
 	cq->comp(cq);
 	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
 	struct mlx4_cq *cq;
-	spin_lock(&cq_table->lock);
+	rcu_read_lock();
 	cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
-	if (cq)
+	rcu_read_unlock();
-		atomic_inc(&cq->refcount);
-	spin_unlock(&cq_table->lock);
 	if (!cq) {
-		mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
+		mlx4_dbg(dev, "Async event for bogus CQ %08x\n", cqn);
 		return;
 	}
+	/* Acessing the CQ outside of rcu_read_lock is safe, because
+	 * the CQ is freed only after interrupt handling is completed.
+	 */
 	cq->event(cq, event_type);
-	if (atomic_dec_and_test(&cq->refcount))
-		complete(&cq->free);
 }
 static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 	if (err)
 		return err;
-	spin_lock_irq(&cq_table->lock);
+	spin_lock(&cq_table->lock);
 	err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
-	spin_unlock_irq(&cq_table->lock);
+	spin_unlock(&cq_table->lock);
 	if (err)
 		goto err_icm;
 	return 0;
 err_radix:
-	spin_lock_irq(&cq_table->lock);
+	spin_lock(&cq_table->lock);
 	radix_tree_delete(&cq_table->tree, cq->cqn);
-	spin_unlock_irq(&cq_table->lock);
+	spin_unlock(&cq_table->lock);
 err_icm:
 	mlx4_cq_free_icm(dev, cq->cqn);
 	if (err)
 		mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
+	spin_lock(&cq_table->lock);
+	radix_tree_delete(&cq_table->tree, cq->cqn);
+	spin_unlock(&cq_table->lock);
 	synchronize_irq(priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq);
 	if (priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq !=
 	    priv->eq_table.eq[MLX4_EQ_ASYNC].irq)
 		synchronize_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
-	spin_lock_irq(&cq_table->lock);
-	radix_tree_delete(&cq_table->tree, cq->cqn);
-	spin_unlock_irq(&cq_table->lock);
 	if (atomic_dec_and_test(&cq->refcount))
 		complete(&cq->free);
 	wait_for_completion(&cq->free);

drivers/net/ethernet/mellanox/mlx4/en_netdev.c+4−1

 	/* Process all completions if exist to prevent
 	 * the queues freezing if they are full
 	 */
-	for (i = 0; i < priv->rx_ring_num; i++)
+	for (i = 0; i < priv->rx_ring_num; i++) {
+		local_bh_disable();
 		napi_schedule(&priv->rx_cq[i]->napi);
+		local_bh_enable();
+	}
 	netif_tx_start_all_queues(dev);
 	netif_device_attach(dev);

drivers/net/ethernet/mellanox/mlx4/eq.c+14−9

 			break;
 		case MLX4_EVENT_TYPE_SRQ_LIMIT:
-			mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
+			mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT. srq_no=0x%x, eq 0x%x\n",
-				 __func__);
+				 __func__, be32_to_cpu(eqe->event.srq.srqn),
+				 eq->eqn);
 		case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
 			if (mlx4_is_master(dev)) {
 				/* forward only to slave owning the SRQ */
 						  eq->eqn, eq->cons_index, ret);
 					break;
 				}
-				mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
+				if (eqe->type ==
-					  __func__, slave,
+				    MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
-					  be32_to_cpu(eqe->event.srq.srqn),
+					mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
-					  eqe->type, eqe->subtype);
+						  __func__, slave,
+						  be32_to_cpu(eqe->event.srq.srqn),
+						  eqe->type, eqe->subtype);
 				if (!ret && slave != dev->caps.function) {
-					mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
+					if (eqe->type ==
-						  __func__, eqe->type,
+					    MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
-						  eqe->subtype, slave);
+						mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
+							  __func__, eqe->type,
+							  eqe->subtype, slave);
 					mlx4_slave_event(dev, slave, eqe);
 					break;
 				}

drivers/net/ethernet/mellanox/mlx4/resource_tracker.c+3−2

 		put_res(dev, slave, srqn, RES_SRQ);
 		qp->srq = srq;
 	}
+	/* Save param3 for dynamic changes from VST back to VGT */
+	qp->param3 = qpc->param3;
 	put_res(dev, slave, rcqn, RES_CQ);
 	put_res(dev, slave, mtt_base, RES_MTT);
 	res_end_move(dev, slave, RES_QP, qpn);
 	int qpn = vhcr->in_modifier & 0x7fffff;
 	struct res_qp *qp;
 	u8 orig_sched_queue;
-	__be32	orig_param3 = qpc->param3;
 	u8 orig_vlan_control = qpc->pri_path.vlan_control;
 	u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
 	u8 orig_pri_path_fl = qpc->pri_path.fl;
 	 */
 	if (!err) {
 		qp->sched_queue = orig_sched_queue;
-		qp->param3	= orig_param3;
 		qp->vlan_control = orig_vlan_control;
 		qp->fvl_rx	=  orig_fvl_rx;
 		qp->pri_path_fl = orig_pri_path_fl;

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+7−4

 	int ttl;
 #if IS_ENABLED(CONFIG_INET)
+	int ret;
 	rt = ip_route_output_key(dev_net(mirred_dev), fl4);
-	if (IS_ERR(rt))
+	ret = PTR_ERR_OR_ZERO(rt);
-		return PTR_ERR(rt);
+	if (ret)
+		return ret;
 #else
 	return -EOPNOTSUPP;
 #endif
 	struct flowi4 fl4 = {};
 	char *encap_header;
 	int encap_size;
-	__be32 saddr = 0;
+	__be32 saddr;
-	int ttl = 0;
+	int ttl;
 	int err;
 	encap_header = kzalloc(max_encap_size, GFP_KERNEL);

drivers/net/ethernet/mellanox/mlxsw/pci_hw.h+4−4

@@ -209,21 +209,21 @@ MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1); · 208 unmodified lines
209	/* pci_eqe_cmd_token	209	/* pci_eqe_cmd_token
210	* Command completion event - token	210	* Command completion event - token
211	*/	211	*/
212	MLXSW_ITEM32(pci, eqe, cmd_token, 0x08, 16, 16);	212	MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
213		213
214	/* pci_eqe_cmd_status	214	/* pci_eqe_cmd_status
215	* Command completion event - status	215	* Command completion event - status
216	*/	216	*/
217	MLXSW_ITEM32(pci, eqe, cmd_status, 0x08, 0, 8);	217	MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
218		218
219	/* pci_eqe_cmd_out_param_h	219	/* pci_eqe_cmd_out_param_h
220	* Command completion event - output parameter - higher part	220	* Command completion event - output parameter - higher part
221	*/	221	*/
222	MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x0C, 0, 32);	222	MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
223		223
224	/* pci_eqe_cmd_out_param_l	224	/* pci_eqe_cmd_out_param_l
225	* Command completion event - output parameter - lower part	225	* Command completion event - output parameter - lower part
226	*/	226	*/
227	MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x10, 0, 32);	227	MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
228		228
229	#endif	229	#endif

drivers/net/ethernet/mellanox/mlxsw/spectrum.c+1−0

@@ -684,6 +684,7 @@ static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, · 683 unmodified lines
684	dev_kfree_skb_any(skb_orig);	684	dev_kfree_skb_any(skb_orig);
685	return NETDEV_TX_OK;	685	return NETDEV_TX_OK;
686	}	686	}
		687	dev_consume_skb_any(skb_orig);
687	}	688	}
688		689
689	if (eth_skb_pad(skb)) {	690	if (eth_skb_pad(skb)) {

drivers/net/ethernet/mellanox/mlxsw/switchx2.c+1−0

@@ -345,6 +345,7 @@ static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb, · 344 unmodified lines
345	dev_kfree_skb_any(skb_orig);	345	dev_kfree_skb_any(skb_orig);
346	return NETDEV_TX_OK;	346	return NETDEV_TX_OK;
347	}	347	}
		348	dev_consume_skb_any(skb_orig);
348	}	349	}
349	mlxsw_sx_txhdr_construct(skb, &tx_info);	350	mlxsw_sx_txhdr_construct(skb, &tx_info);
350	/* TX header is consumed by HW on the way so we shouldn't count its	351	/* TX header is consumed by HW on the way so we shouldn't count its

drivers/net/ethernet/qualcomm/emac/emac-phy.c+7−0

@@ -201,6 +201,13 @@ int emac_phy_config(struct platform_device pdev, struct emac_adapter adpt) · 200 unmodified lines
201	else	201	else
202	adpt->phydev = mdiobus_get_phy(mii_bus, phy_addr);	202	adpt->phydev = mdiobus_get_phy(mii_bus, phy_addr);
203		203
		204	/* of_phy_find_device() claims a reference to the phydev,
		205	* so we do that here manually as well. When the driver
		206	* later unloads, it can unilaterally drop the reference
		207	* without worrying about ACPI vs DT.
		208	*/
		209	if (adpt->phydev)
		210	get_device(&adpt->phydev->mdio.dev);
204	} else {	211	} else {
205	struct device_node *phy_np;	212	struct device_node *phy_np;
206		213

drivers/net/ethernet/qualcomm/emac/emac.c+2−4

 err_undo_napi:
 	netif_napi_del(&adpt->rx_q.napi);
 err_undo_mdiobus:
-	if (!has_acpi_companion(&pdev->dev))
+	put_device(&adpt->phydev->mdio.dev);
-		put_device(&adpt->phydev->mdio.dev);
 	mdiobus_unregister(adpt->mii_bus);
 err_undo_clocks:
 	emac_clks_teardown(adpt);
 	emac_clks_teardown(adpt);
-	if (!has_acpi_companion(&pdev->dev))
+	put_device(&adpt->phydev->mdio.dev);
-		put_device(&adpt->phydev->mdio.dev);
 	mdiobus_unregister(adpt->mii_bus);
 	free_netdev(netdev);

drivers/net/ethernet/renesas/ravb_main.c+15−6

 	/* Receive error message handling */
 	priv->rx_over_errors =  priv->stats[RAVB_BE].rx_over_errors;
 	priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
-	if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
+	if (priv->rx_over_errors != ndev->stats.rx_over_errors)
 		ndev->stats.rx_over_errors = priv->rx_over_errors;
-		netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
+	if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
-	}
-	if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
 		ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
-		netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
-	}
 out:
 	return budget - quota;
 }
 	buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
 		 entry / NUM_TX_DESC * DPTR_ALIGN;
 	len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
+	/* Zero length DMA descriptors are problematic as they seem to
+	 * terminate DMA transfers. Avoid them by simply using a length of
+	 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
+	 *
+	 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
+	 * data by the call to skb_put_padto() above this is safe with
+	 * respect to both the length of the first DMA descriptor (len)
+	 * overflowing the available data and the length of the second DMA
+	 * descriptor (skb->len - len) being negative.
+	 */
+	if (len == 0)
+		len = DPTR_ALIGN;
 	memcpy(buffer, skb->data, len);
 	dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
 	if (dma_mapping_error(ndev->dev.parent, dma_addr))

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+10−9

 	    (priv->plat->maxmtu >= ndev->min_mtu))
 		ndev->max_mtu = priv->plat->maxmtu;
 	else if (priv->plat->maxmtu < ndev->min_mtu)
-		netdev_warn(priv->dev,
+		dev_warn(priv->device,
-			    "%s: warning: maxmtu having invalid value (%d)\n",
+			 "%s: warning: maxmtu having invalid value (%d)\n",
-			    __func__, priv->plat->maxmtu);
+			 __func__, priv->plat->maxmtu);
 	if (flow_ctrl)
 		priv->flow_ctrl = FLOW_AUTO;	/* RX/TX pause on */
 	 */
 	if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
 		priv->use_riwt = 1;
-		netdev_info(priv->dev, "Enable RX Mitigation via HW Watchdog Timer\n");
+		dev_info(priv->device,
+			 "Enable RX Mitigation via HW Watchdog Timer\n");
 	}
 	netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
 		/* MDIO bus Registration */
 		ret = stmmac_mdio_register(ndev);
 		if (ret < 0) {
-			netdev_err(priv->dev,
+			dev_err(priv->device,
-				   "%s: MDIO bus (id: %d) registration failed",
+				"%s: MDIO bus (id: %d) registration failed",
-				   __func__, priv->plat->bus_id);
+				__func__, priv->plat->bus_id);
 			goto error_mdio_register;
 		}
 	}
 	ret = register_netdev(ndev);
 	if (ret) {
-		netdev_err(priv->dev, "%s: ERROR %i registering the device\n",
+		dev_err(priv->device, "%s: ERROR %i registering the device\n",
-			   __func__, ret);
+			__func__, ret);
 		goto error_netdev_register;
 	}

drivers/net/ethernet/ti/cpmac.c+1−1

@@ -1210,7 +1210,7 @@ int cpmac_init(void) · 1209 unmodified lines
1210	goto fail_alloc;	1210	goto fail_alloc;
1211	}	1211	}
1212		1212
1213	#warning FIXME: unhardcode gpio&reset bits	1213	/* FIXME: unhardcode gpio&reset bits */
1214	ar7_gpio_disable(26);	1214	ar7_gpio_disable(26);
1215	ar7_gpio_disable(27);	1215	ar7_gpio_disable(27);
1216	ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);	1216	ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);

drivers/net/hyperv/netvsc_drv.c+3−0

 	 * policy filters on the host). Deliver these via the VF
 	 * interface in the guest.
 	 */
+	rcu_read_lock();
 	vf_netdev = rcu_dereference(net_device_ctx->vf_netdev);
 	if (vf_netdev && (vf_netdev->flags & IFF_UP))
 		net = vf_netdev;
 	skb = netvsc_alloc_recv_skb(net, packet, csum_info, *data, vlan_tci);
 	if (unlikely(!skb)) {
 		++net->stats.rx_dropped;
+		rcu_read_unlock();
 		return NVSP_STAT_FAIL;
 	}
 	 * TODO - use NAPI?
 	 */
 	netif_rx(skb);
+	rcu_read_unlock();
 	return 0;
 }

drivers/net/ieee802154/at86rf230.c+2−2

@@ -1715,9 +1715,9 @@ static int at86rf230_probe(struct spi_device *spi) · 1714 unmodified lines
1715	/* Reset */	1715	/* Reset */
1716	if (gpio_is_valid(rstn)) {	1716	if (gpio_is_valid(rstn)) {
1717	udelay(1);	1717	udelay(1);
1718	gpio_set_value(rstn, 0);	1718	gpio_set_value_cansleep(rstn, 0);
1719	udelay(1);	1719	udelay(1);
1720	gpio_set_value(rstn, 1);	1720	gpio_set_value_cansleep(rstn, 1);
1721	usleep_range(120, 240);	1721	usleep_range(120, 240);
1722	}	1722	}
1723		1723

drivers/net/ieee802154/atusb.c+43−16

@@ -117,13 +117,26 @@ static int atusb_read_reg(struct atusb *atusb, uint8_t reg) · 116 unmodified lines
117	{	117	{
118	struct usb_device *usb_dev = atusb->usb_dev;	118	struct usb_device *usb_dev = atusb->usb_dev;
119	int ret;	119	int ret;
		120	uint8_t *buffer;
120	uint8_t value;	121	uint8_t value;
121		122
		123	buffer = kmalloc(1, GFP_KERNEL);
		124	if (!buffer)
		125	return -ENOMEM;
		126
122	dev_dbg(&usb_dev->dev, "atusb: reg = 0x%x\n", reg);	127	dev_dbg(&usb_dev->dev, "atusb: reg = 0x%x\n", reg);
123	ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0),	128	ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0),
124	ATUSB_REG_READ, ATUSB_REQ_FROM_DEV,	129	ATUSB_REG_READ, ATUSB_REQ_FROM_DEV,
125	0, reg, &value, 1, 1000);	130	0, reg, buffer, 1, 1000);
126	return ret >= 0 ? value : ret;	131
		132	if (ret >= 0) {
		133	value = buffer[0];
		134	kfree(buffer);
		135	return value;
		136	} else {
		137	kfree(buffer);
		138	return ret;
		139	}
127	}	140	}
128		141
129	static int atusb_write_subreg(struct atusb *atusb, uint8_t reg, uint8_t mask,	142	static int atusb_write_subreg(struct atusb *atusb, uint8_t reg, uint8_t mask,
@@ -549,13 +562,6 @@ static int · 419 unmodified lines
549	atusb_set_frame_retries(struct ieee802154_hw *hw, s8 retries)	562	atusb_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
550	{	563	{
551	struct atusb *atusb = hw->priv;	564	struct atusb *atusb = hw->priv;
552	struct device *dev = &atusb->usb_dev->dev;
553
554	if (atusb->fw_ver_maj == 0 && atusb->fw_ver_min < 3) {
555	dev_info(dev, "Automatic frame retransmission is only available from "
556	"firmware version 0.3. Please update if you want this feature.");
557	return -EINVAL;
558	}
559		565
560	return atusb_write_subreg(atusb, SR_MAX_FRAME_RETRIES, retries);	566	return atusb_write_subreg(atusb, SR_MAX_FRAME_RETRIES, retries);
561	}	567	}
@@ -608,9 +614,13 @@ static const struct ieee802154_ops atusb_ops = { · 46 unmodified lines
608	static int atusb_get_and_show_revision(struct atusb *atusb)	614	static int atusb_get_and_show_revision(struct atusb *atusb)
609	{	615	{
610	struct usb_device *usb_dev = atusb->usb_dev;	616	struct usb_device *usb_dev = atusb->usb_dev;
611	unsigned char buffer[3];	617	unsigned char *buffer;
612	int ret;	618	int ret;
613		619
		620	buffer = kmalloc(3, GFP_KERNEL);
		621	if (!buffer)
		622	return -ENOMEM;
		623
614	/* Get a couple of the ATMega Firmware values */	624	/* Get a couple of the ATMega Firmware values */
615	ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0),	625	ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0),
616	ATUSB_ID, ATUSB_REQ_FROM_DEV, 0, 0,	626	ATUSB_ID, ATUSB_REQ_FROM_DEV, 0, 0,
@@ -631,15 +641,20 @@ static int atusb_get_and_show_revision(struct atusb *atusb) · 14 unmodified lines
631	dev_info(&usb_dev->dev, "Please update to version 0.2 or newer");	641	dev_info(&usb_dev->dev, "Please update to version 0.2 or newer");
632	}	642	}
633		643
		644	kfree(buffer);
634	return ret;	645	return ret;
635	}	646	}
636		647
637	static int atusb_get_and_show_build(struct atusb *atusb)	648	static int atusb_get_and_show_build(struct atusb *atusb)
638	{	649	{
639	struct usb_device *usb_dev = atusb->usb_dev;	650	struct usb_device *usb_dev = atusb->usb_dev;
640	char build[ATUSB_BUILD_SIZE + 1];	651	char *build;
641	int ret;	652	int ret;
642		653
		654	build = kmalloc(ATUSB_BUILD_SIZE + 1, GFP_KERNEL);
		655	if (!build)
		656	return -ENOMEM;
		657
643	ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0),	658	ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0),
644	ATUSB_BUILD, ATUSB_REQ_FROM_DEV, 0, 0,	659	ATUSB_BUILD, ATUSB_REQ_FROM_DEV, 0, 0,
645	build, ATUSB_BUILD_SIZE, 1000);	660	build, ATUSB_BUILD_SIZE, 1000);
@@ -648,6 +663,7 @@ static int atusb_get_and_show_build(struct atusb *atusb) · 2 unmodified lines
648	dev_info(&usb_dev->dev, "Firmware: build %s\n", build);	663	dev_info(&usb_dev->dev, "Firmware: build %s\n", build);
649	}	664	}
650		665
		666	kfree(build);
651	return ret;	667	return ret;
652	}	668	}
653		669
@@ -698,7 +714,7 @@ fail: · 44 unmodified lines
698	static int atusb_set_extended_addr(struct atusb *atusb)	714	static int atusb_set_extended_addr(struct atusb *atusb)
699	{	715	{
700	struct usb_device *usb_dev = atusb->usb_dev;	716	struct usb_device *usb_dev = atusb->usb_dev;
701	unsigned char buffer[IEEE802154_EXTENDED_ADDR_LEN];	717	unsigned char *buffer;
702	__le64 extended_addr;	718	__le64 extended_addr;
703	u64 addr;	719	u64 addr;
704	int ret;	720	int ret;
@@ -710,12 +726,20 @@ static int atusb_set_extended_addr(struct atusb *atusb) · 5 unmodified lines
710	return 0;	726	return 0;
711	}	727	}
712		728
		729	buffer = kmalloc(IEEE802154_EXTENDED_ADDR_LEN, GFP_KERNEL);
		730	if (!buffer)
		731	return -ENOMEM;
		732
713	/* Firmware is new enough so we fetch the address from EEPROM */	733	/* Firmware is new enough so we fetch the address from EEPROM */
714	ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0),	734	ret = atusb_control_msg(atusb, usb_rcvctrlpipe(usb_dev, 0),
715	ATUSB_EUI64_READ, ATUSB_REQ_FROM_DEV, 0, 0,	735	ATUSB_EUI64_READ, ATUSB_REQ_FROM_DEV, 0, 0,
716	buffer, IEEE802154_EXTENDED_ADDR_LEN, 1000);	736	buffer, IEEE802154_EXTENDED_ADDR_LEN, 1000);
717	if (ret < 0)	737	if (ret < 0) {
718	dev_err(&usb_dev->dev, "failed to fetch extended address\n");	738	dev_err(&usb_dev->dev, "failed to fetch extended address, random address set\n");
		739	ieee802154_random_extended_addr(&atusb->hw->phy->perm_extended_addr);
		740	kfree(buffer);
		741	return ret;
		742	}
719		743
720	memcpy(&extended_addr, buffer, IEEE802154_EXTENDED_ADDR_LEN);	744	memcpy(&extended_addr, buffer, IEEE802154_EXTENDED_ADDR_LEN);
721	/* Check if read address is not empty and the unicast bit is set correctly */	745	/* Check if read address is not empty and the unicast bit is set correctly */
@@ -729,6 +753,7 @@ static int atusb_set_extended_addr(struct atusb *atusb) · 7 unmodified lines
729	&addr);	753	&addr);
730	}	754	}
731		755
		756	kfree(buffer);
732	return ret;	757	return ret;
733	}	758	}
734		759
@@ -770,8 +795,7 @@ static int atusb_probe(struct usb_interface *interface, · 35 unmodified lines
770		795
771	hw->parent = &usb_dev->dev;	796	hw->parent = &usb_dev->dev;
772	hw->flags = IEEE802154_HW_TX_OMIT_CKSUM \| IEEE802154_HW_AFILT \|	797	hw->flags = IEEE802154_HW_TX_OMIT_CKSUM \| IEEE802154_HW_AFILT \|
773	IEEE802154_HW_PROMISCUOUS \| IEEE802154_HW_CSMA_PARAMS \|	798	IEEE802154_HW_PROMISCUOUS \| IEEE802154_HW_CSMA_PARAMS;
774	IEEE802154_HW_FRAME_RETRIES;
775		799
776	hw->phy->flags = WPAN_PHY_FLAG_TXPOWER \| WPAN_PHY_FLAG_CCA_ED_LEVEL \|	800	hw->phy->flags = WPAN_PHY_FLAG_TXPOWER \| WPAN_PHY_FLAG_CCA_ED_LEVEL \|
777	WPAN_PHY_FLAG_CCA_MODE;	801	WPAN_PHY_FLAG_CCA_MODE;
@@ -800,6 +824,9 @@ static int atusb_probe(struct usb_interface *interface, · 22 unmodified lines
800	atusb_get_and_show_build(atusb);	824	atusb_get_and_show_build(atusb);
801	atusb_set_extended_addr(atusb);	825	atusb_set_extended_addr(atusb);
802		826
		827	if (atusb->fw_ver_maj >= 0 && atusb->fw_ver_min >= 3)
		828	hw->flags \|= IEEE802154_HW_FRAME_RETRIES;
		829
803	ret = atusb_get_and_clear_error(atusb);	830	ret = atusb_get_and_clear_error(atusb);
804	if (ret) {	831	if (ret) {
805	dev_err(&atusb->usb_dev->dev,	832	dev_err(&atusb->usb_dev->dev,

drivers/net/phy/dp83867.c+6−2

 	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 				   &dp83867->rx_id_delay);
-	if (ret)
+	if (ret &&
+	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	     phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 		return ret;
 	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 				   &dp83867->tx_id_delay);
-	if (ret)
+	if (ret &&
+	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	     phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 		return ret;
 	return of_property_read_u32(of_node, "ti,fifo-depth",

drivers/net/usb/r8152.c+6−1

 	u8 checksum = CHECKSUM_NONE;
 	u32 opts2, opts3;
-	if (tp->version == RTL_VER_01 || tp->version == RTL_VER_02)
+	if (!(tp->netdev->features & NETIF_F_RXCSUM))
 		goto return_result;
 	opts2 = le32_to_cpu(rx_desc->opts2);
 				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
 				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
+	if (tp->version == RTL_VER_01) {
+		netdev->features &= ~NETIF_F_RXCSUM;
+		netdev->hw_features &= ~NETIF_F_RXCSUM;
+	}
 	netdev->ethtool_ops = &ops;
 	netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);

drivers/net/vxlan.c+10−3

 static struct rtable *vxlan_get_route(struct vxlan_dev *vxlan, struct net_device *dev,
 				      struct vxlan_sock *sock4,
 				      struct sk_buff *skb, int oif, u8 tos,
-				      __be32 daddr, __be32 *saddr,
+				      __be32 daddr, __be32 *saddr, __be16 dport, __be16 sport,
 				      struct dst_cache *dst_cache,
 				      const struct ip_tunnel_info *info)
 {
 	fl4.flowi4_proto = IPPROTO_UDP;
 	fl4.daddr = daddr;
 	fl4.saddr = *saddr;
+	fl4.fl4_dport = dport;
+	fl4.fl4_sport = sport;
 	rt = ip_route_output_key(vxlan->net, &fl4);
 	if (likely(!IS_ERR(rt))) {
 					  __be32 label,
 					  const struct in6_addr *daddr,
 					  struct in6_addr *saddr,
+					  __be16 dport, __be16 sport,
 					  struct dst_cache *dst_cache,
 					  const struct ip_tunnel_info *info)
 {
 	fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tos), label);
 	fl6.flowi6_mark = skb->mark;
 	fl6.flowi6_proto = IPPROTO_UDP;
+	fl6.fl6_dport = dport;
+	fl6.fl6_sport = sport;
 	err = ipv6_stub->ipv6_dst_lookup(vxlan->net,
 					 sock6->sock->sk,
 				     rdst ? rdst->remote_ifindex : 0, tos,
 				     dst->sin.sin_addr.s_addr,
 				     &src->sin.sin_addr.s_addr,
+				     dst_port, src_port,
 				     dst_cache, info);
 		if (IS_ERR(rt)) {
 			err = PTR_ERR(rt);
 					rdst ? rdst->remote_ifindex : 0, tos,
 					label, &dst->sin6.sin6_addr,
 					&src->sin6.sin6_addr,
+					dst_port, src_port,
 					dst_cache, info);
 		if (IS_ERR(ndst)) {
 			err = PTR_ERR(ndst);
 		rt = vxlan_get_route(vxlan, dev, sock4, skb, 0, info->key.tos,
 				     info->key.u.ipv4.dst,
-				     &info->key.u.ipv4.src, NULL, info);
+				     &info->key.u.ipv4.src, dport, sport, NULL, info);
 		if (IS_ERR(rt))
 			return PTR_ERR(rt);
 		ip_rt_put(rt);
 		ndst = vxlan6_get_route(vxlan, dev, sock6, skb, 0, info->key.tos,
 					info->key.label, &info->key.u.ipv6.dst,
-					&info->key.u.ipv6.src, NULL, info);
+					&info->key.u.ipv6.src, dport, sport, NULL, info);
 		if (IS_ERR(ndst))
 			return PTR_ERR(ndst);
 		dst_release(ndst);

drivers/nvdimm/namespace_devs.c+10−13

 {
 	resource_size_t allocated = 0, available = 0;
 	struct nd_region *nd_region = to_nd_region(dev->parent);
+	struct nd_namespace_common *ndns = to_ndns(dev);
 	struct nd_mapping *nd_mapping;
 	struct nvdimm_drvdata *ndd;
 	struct nd_label_id label_id;
 	u8 *uuid = NULL;
 	int rc, i;
-	if (dev->driver || to_ndns(dev)->claim)
+	if (dev->driver || ndns->claim)
 		return -EBUSY;
 	if (is_namespace_pmem(dev)) {
 		nd_namespace_pmem_set_resource(nd_region, nspm,
 				val * nd_region->ndr_mappings);
-	} else if (is_namespace_blk(dev)) {
-		struct nd_namespace_blk *nsblk = to_nd_namespace_blk(dev);
-		/*
-		 * Try to delete the namespace if we deleted all of its
-		 * allocation, this is not the seed device for the
-		 * region, and it is not actively claimed by a btt
-		 * instance.
-		 */
-		if (val == 0 && nd_region->ns_seed != dev
-				&& !nsblk->common.claim)
-			nd_device_unregister(dev, ND_ASYNC);
 	}
+	/*
+	 * Try to delete the namespace if we deleted all of its
+	 * allocation, this is not the seed device for the region, and
+	 * it is not actively claimed by a btt instance.
+	 */
+	if (val == 0 && nd_region->ns_seed != dev && !ndns->claim)
+		nd_device_unregister(dev, ND_ASYNC);
 	return rc;
 }

drivers/nvdimm/pmem.c+3−1

@@ -90,7 +90,9 @@ static int read_pmem(struct page *page, unsigned int off, · 89 unmodified lines
90		90
91	rc = memcpy_from_pmem(mem + off, pmem_addr, len);	91	rc = memcpy_from_pmem(mem + off, pmem_addr, len);
92	kunmap_atomic(mem);	92	kunmap_atomic(mem);
93	return rc;	93	if (rc)
		94	return -EIO;
		95	return 0;
94	}	96	}
95		97
96	static int pmem_do_bvec(struct pmem_device pmem, struct page page,	98	static int pmem_do_bvec(struct pmem_device pmem, struct page page,

drivers/pci/host/pci-xgene-msi.c+1−1

@@ -517,7 +517,7 @@ static int xgene_msi_probe(struct platform_device *pdev) · 516 unmodified lines
517		517
518	rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online",	518	rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online",
519	xgene_msi_hwirq_alloc, NULL);	519	xgene_msi_hwirq_alloc, NULL);
520	if (rc)	520	if (rc < 0)
521	goto err_cpuhp;	521	goto err_cpuhp;
522	pci_xgene_online = rc;	522	pci_xgene_online = rc;
523	rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL,	523	rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL,

drivers/pci/host/pcie-designware.c+5−5

 {
 	u32 val;
-	/* get iATU unroll support */
-	pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
-	dev_dbg(pp->dev, "iATU unroll: %s\n",
-		pp->iatu_unroll_enabled ? "enabled" : "disabled");
 	/* set the number of lanes */
 	val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
 	val &= ~PORT_LINK_MODE_MASK;
 	 * we should not program the ATU here.
 	 */
 	if (!pp->ops->rd_other_conf) {
+		/* get iATU unroll support */
+		pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
+		dev_dbg(pp->dev, "iATU unroll: %s\n",
+			pp->iatu_unroll_enabled ? "enabled" : "disabled");
 		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
 					  PCIE_ATU_TYPE_MEM, pp->mem_base,
 					  pp->mem_bus_addr, pp->mem_size);

drivers/pci/probe.c+7−5

 	pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 	if (!pos)
 		return;
 	pdev->pcie_cap = pos;
 	pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
 	pdev->pcie_flags_reg = reg16;
 	pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
 	/*
-	 * A Root Port is always the upstream end of a Link.  No PCIe
+	 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
-	 * component has two Links.  Two Links are connected by a Switch
+	 * of a Link.  No PCIe component has two Links.  Two Links are
-	 * that has a Port on each Link and internal logic to connect the
+	 * connected by a Switch that has a Port on each Link and internal
-	 * two Ports.
+	 * logic to connect the two Ports.
 	 */
 	type = pci_pcie_type(pdev);
-	if (type == PCI_EXP_TYPE_ROOT_PORT)
+	if (type == PCI_EXP_TYPE_ROOT_PORT ||
+	    type == PCI_EXP_TYPE_PCIE_BRIDGE)
 		pdev->has_secondary_link = 1;
 	else if (type == PCI_EXP_TYPE_UPSTREAM ||
 		 type == PCI_EXP_TYPE_DOWNSTREAM) {

drivers/s390/virtio/virtio_ccw.c+27−2

 #define CCW_CMD_WRITE_CONF 0x21
 #define CCW_CMD_WRITE_STATUS 0x31
 #define CCW_CMD_READ_VQ_CONF 0x32
+#define CCW_CMD_READ_STATUS 0x72
 #define CCW_CMD_SET_IND_ADAPTER 0x73
 #define CCW_CMD_SET_VIRTIO_REV 0x83
 #define VIRTIO_CCW_DOING_SET_CONF_IND 0x04000000
 #define VIRTIO_CCW_DOING_SET_IND_ADAPTER 0x08000000
 #define VIRTIO_CCW_DOING_SET_VIRTIO_REV 0x10000000
+#define VIRTIO_CCW_DOING_READ_STATUS 0x20000000
 #define VIRTIO_CCW_INTPARM_MASK 0xffff0000
 static struct virtio_ccw_device *to_vc_device(struct virtio_device *vdev)
 	 * This may happen on device detach.
 	 */
 	if (ret && (ret != -ENODEV))
-		dev_warn(&vq->vdev->dev, "Error %d while deleting queue %d",
+		dev_warn(&vq->vdev->dev, "Error %d while deleting queue %d\n",
 			 ret, index);
 	vring_del_virtqueue(vq);
 static u8 virtio_ccw_get_status(struct virtio_device *vdev)
 {
 	struct virtio_ccw_device *vcdev = to_vc_device(vdev);
+	u8 old_status = *vcdev->status;
+	struct ccw1 *ccw;
+	if (vcdev->revision < 1)
+		return *vcdev->status;
+	ccw = kzalloc(sizeof(*ccw), GFP_DMA | GFP_KERNEL);
+	if (!ccw)
+		return old_status;
+	ccw->cmd_code = CCW_CMD_READ_STATUS;
+	ccw->flags = 0;
+	ccw->count = sizeof(*vcdev->status);
+	ccw->cda = (__u32)(unsigned long)vcdev->status;
+	ccw_io_helper(vcdev, ccw, VIRTIO_CCW_DOING_READ_STATUS);
+/*
+ * If the channel program failed (should only happen if the device
+ * was hotunplugged, and then we clean up via the machine check
+ * handler anyway), vcdev->status was not overwritten and we just
+ * return the old status, which is fine.
+*/
+	kfree(ccw);
 	return *vcdev->status;
 }
 	kfree(ccw);
 }
-static struct virtio_config_ops virtio_ccw_config_ops = {
+static const struct virtio_config_ops virtio_ccw_config_ops = {
 	.get_features = virtio_ccw_get_features,
 	.finalize_features = virtio_ccw_finalize_features,
 	.get = virtio_ccw_get_config,
 		case VIRTIO_CCW_DOING_READ_CONFIG:
 		case VIRTIO_CCW_DOING_WRITE_CONFIG:
 		case VIRTIO_CCW_DOING_WRITE_STATUS:
+		case VIRTIO_CCW_DOING_READ_STATUS:
 		case VIRTIO_CCW_DOING_SET_VQ:
 		case VIRTIO_CCW_DOING_SET_IND:
 		case VIRTIO_CCW_DOING_SET_CONF_IND:

drivers/scsi/bfa/bfad_bsg.c+1−1

@@ -3363,7 +3363,7 @@ bfad_im_bsg_els_ct_request(struct bsg_job *job) · 3362 unmodified lines
3363	struct bfad_fcxp *drv_fcxp;	3363	struct bfad_fcxp *drv_fcxp;
3364	struct bfa_fcs_lport_s *fcs_port;	3364	struct bfa_fcs_lport_s *fcs_port;
3365	struct bfa_fcs_rport_s *fcs_rport;	3365	struct bfa_fcs_rport_s *fcs_rport;
3366	struct fc_bsg_request *bsg_request = bsg_request;	3366	struct fc_bsg_request *bsg_request = job->request;
3367	struct fc_bsg_reply *bsg_reply = job->reply;	3367	struct fc_bsg_reply *bsg_reply = job->reply;
3368	uint32_t command_type = bsg_request->msgcode;	3368	uint32_t command_type = bsg_request->msgcode;
3369	unsigned long flags;	3369	unsigned long flags;

drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c+4−3

 #define	INITIAL_SRP_LIMIT	800
 #define	DEFAULT_MAX_SECTORS	256
+#define MAX_TXU			1024 * 1024
 static uint max_vdma_size = MAX_H_COPY_RDMA;
 	}
 	info = dma_alloc_coherent(&vscsi->dma_dev->dev, sizeof(*info), &token,
-				  GFP_KERNEL);
+				  GFP_ATOMIC);
 	if (!info) {
 		dev_err(&vscsi->dev, "bad dma_alloc_coherent %p\n",
 			iue->target);
 	info->mad_version = cpu_to_be32(MAD_VERSION_1);
 	info->os_type = cpu_to_be32(LINUX);
 	memset(&info->port_max_txu[0], 0, sizeof(info->port_max_txu));
-	info->port_max_txu[0] = cpu_to_be32(128 * PAGE_SIZE);
+	info->port_max_txu[0] = cpu_to_be32(MAX_TXU);
 	dma_wmb();
 	rc = h_copy_rdma(sizeof(*info), vscsi->dds.window[LOCAL].liobn,
 	}
 	cap = dma_alloc_coherent(&vscsi->dma_dev->dev, olen, &token,
-				 GFP_KERNEL);
+				 GFP_ATOMIC);
 	if (!cap) {
 		dev_err(&vscsi->dev, "bad dma_alloc_coherent %p\n",
 			iue->target);

drivers/scsi/lpfc/lpfc_els.c+2−0

 		} else {
 			buf_ptr1 = (struct lpfc_dmabuf *) elsiocb->context2;
 			lpfc_els_free_data(phba, buf_ptr1);
+			elsiocb->context2 = NULL;
 		}
 	}
 	if (elsiocb->context3) {
 		buf_ptr = (struct lpfc_dmabuf *) elsiocb->context3;
 		lpfc_els_free_bpl(phba, buf_ptr);
+		elsiocb->context3 = NULL;
 	}
 	lpfc_sli_release_iocbq(phba, elsiocb);
 	return 0;

drivers/scsi/lpfc/lpfc_sli.c+7−0

  free_vfi_bmask:
 	kfree(phba->sli4_hba.vfi_bmask);
+	phba->sli4_hba.vfi_bmask = NULL;
  free_xri_ids:
 	kfree(phba->sli4_hba.xri_ids);
+	phba->sli4_hba.xri_ids = NULL;
  free_xri_bmask:
 	kfree(phba->sli4_hba.xri_bmask);
+	phba->sli4_hba.xri_bmask = NULL;
  free_vpi_ids:
 	kfree(phba->vpi_ids);
+	phba->vpi_ids = NULL;
  free_vpi_bmask:
 	kfree(phba->vpi_bmask);
+	phba->vpi_bmask = NULL;
  free_rpi_ids:
 	kfree(phba->sli4_hba.rpi_ids);
+	phba->sli4_hba.rpi_ids = NULL;
  free_rpi_bmask:
 	kfree(phba->sli4_hba.rpi_bmask);
+	phba->sli4_hba.rpi_bmask = NULL;
  err_exit:
 	return rc;
 }

drivers/scsi/mpt3sas/mpt3sas_base.h+12−0

  * @eedp_enable: eedp support enable bit
  * @eedp_type: 0(type_1), 1(type_2), 2(type_3)
  * @eedp_block_length: block size
+ * @ata_command_pending: SATL passthrough outstanding for device
  */
 struct MPT3SAS_DEVICE {
 	struct MPT3SAS_TARGET *sas_target;
 	u8	ignore_delay_remove;
 	/* Iopriority Command Handling */
 	u8	ncq_prio_enable;
+	/*
+	 * Bug workaround for SATL handling: the mpt2/3sas firmware
+	 * doesn't return BUSY or TASK_SET_FULL for subsequent
+	 * commands while a SATL pass through is in operation as the
+	 * spec requires, it simply does nothing with them until the
+	 * pass through completes, causing them possibly to timeout if
+	 * the passthrough is a long executing command (like format or
+	 * secure erase).  This variable allows us to do the right
+	 * thing while a SATL command is pending.
+	 */
+	unsigned long ata_command_pending;
 };

drivers/scsi/mpt3sas/mpt3sas_scsih.c+26−14

 	}
 }
-static inline bool ata_12_16_cmd(struct scsi_cmnd *scmd)
+static int _scsih_set_satl_pending(struct scsi_cmnd *scmd, bool pending)
 {
-	return (scmd->cmnd[0] == ATA_12 || scmd->cmnd[0] == ATA_16);
+	struct MPT3SAS_DEVICE *priv = scmd->device->hostdata;
+	if (scmd->cmnd[0] != ATA_12 && scmd->cmnd[0] != ATA_16)
+		return 0;
+	if (pending)
+		return test_and_set_bit(0, &priv->ata_command_pending);
+	clear_bit(0, &priv->ata_command_pending);
+	return 0;
 }
 /**
 		if (!scmd)
 			continue;
 		count++;
-		if (ata_12_16_cmd(scmd))
+		_scsih_set_satl_pending(scmd, false);
-			scsi_internal_device_unblock(scmd->device,
-							SDEV_RUNNING);
 		mpt3sas_base_free_smid(ioc, smid);
 		scsi_dma_unmap(scmd);
 		if (ioc->pci_error_recovery)
 	if (ioc->logging_level & MPT_DEBUG_SCSI)
 		scsi_print_command(scmd);
-	/*
-	 * Lock the device for any subsequent command until command is
-	 * done.
-	 */
-	if (ata_12_16_cmd(scmd))
-		scsi_internal_device_block(scmd->device);
 	sas_device_priv_data = scmd->device->hostdata;
 	if (!sas_device_priv_data || !sas_device_priv_data->sas_target) {
 		scmd->result = DID_NO_CONNECT << 16;
 		return 0;
 	}
+	/*
+	 * Bug work around for firmware SATL handling.  The loop
+	 * is based on atomic operations and ensures consistency
+	 * since we're lockless at this point
+	 */
+	do {
+		if (test_bit(0, &sas_device_priv_data->ata_command_pending)) {
+			scmd->result = SAM_STAT_BUSY;
+			scmd->scsi_done(scmd);
+			return 0;
+		}
+	} while (_scsih_set_satl_pending(scmd, true));
 	sas_target_priv_data = sas_device_priv_data->sas_target;
 	/* invalid device handle */
 	if (scmd == NULL)
 		return 1;
-	if (ata_12_16_cmd(scmd))
+	_scsih_set_satl_pending(scmd, false);
-		scsi_internal_device_unblock(scmd->device, SDEV_RUNNING);
 	mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);

drivers/scsi/qla2xxx/qla_attr.c+14−7

 	struct qla_hw_data *ha = vha->hw;
 	ssize_t rval = 0;
+	mutex_lock(&ha->optrom_mutex);
 	if (ha->optrom_state != QLA_SREADING)
-		return 0;
+		goto out;
-	mutex_lock(&ha->optrom_mutex);
 	rval = memory_read_from_buffer(buf, count, &off, ha->optrom_buffer,
 	    ha->optrom_region_size);
+out:
 	mutex_unlock(&ha->optrom_mutex);
 	return rval;
 	    struct device, kobj)));
 	struct qla_hw_data *ha = vha->hw;
-	if (ha->optrom_state != QLA_SWRITING)
+	mutex_lock(&ha->optrom_mutex);
+	if (ha->optrom_state != QLA_SWRITING) {
+		mutex_unlock(&ha->optrom_mutex);
 		return -EINVAL;
-	if (off > ha->optrom_region_size)
+	}
+	if (off > ha->optrom_region_size) {
+		mutex_unlock(&ha->optrom_mutex);
 		return -ERANGE;
+	}
 	if (off + count > ha->optrom_region_size)
 		count = ha->optrom_region_size - off;
-	mutex_lock(&ha->optrom_mutex);
 	memcpy(&ha->optrom_buffer[off], buf, count);
 	mutex_unlock(&ha->optrom_mutex);
 	struct scsi_qla_host *vha = shost_priv(dev_to_shost(container_of(kobj,
 	    struct device, kobj)));
 	int type;
-	int rval = 0;
 	port_id_t did;
 	type = simple_strtol(buf, NULL, 10);
 	ql_log(ql_log_info, vha, 0x70e4, "%s: %d\n", __func__, type);
-	rval = qla24xx_els_dcmd_iocb(vha, ELS_DCMD_LOGO, did);
+	qla24xx_els_dcmd_iocb(vha, ELS_DCMD_LOGO, did);
 	return count;
 }

drivers/scsi/qla2xxx/qla_def.h+3−3

 struct atio {
 	uint8_t		entry_type;		/* Entry type. */
 	uint8_t		entry_count;		/* Entry count. */
-	uint8_t		data[58];
+	__le16		attr_n_length;
+	uint8_t		data[56];
 	uint32_t	signature;
 #define ATIO_PROCESSED 0xDEADDEAD		/* Signature */
 };
 #define QLA_MSIX_FW_MODE(m)	(((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
 #define QLA_MSIX_FW_MODE_1(m)	(QLA_MSIX_FW_MODE(m) == 1)
-#define QLA_MSIX_DEFAULT		0x00
+#define QLA_BASE_VECTORS	2 /* default + RSP */
 #define QLA_MSIX_RSP_Q			0x01
 #define QLA_ATIO_VECTOR		0x02
 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q	0x03
 	uint16_t entry;
 	char name[30];
 	void *handle;
-	struct irq_affinity_notify irq_notify;
 	int cpuid;
 };

drivers/scsi/qla2xxx/qla_init.c+2−2

@@ -1191,7 +1191,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha) · 1190 unmodified lines
1191		1191
1192	/* Wait for soft-reset to complete. */	1192	/* Wait for soft-reset to complete. */
1193	RD_REG_DWORD(&reg->ctrl_status);	1193	RD_REG_DWORD(&reg->ctrl_status);
1194	for (cnt = 0; cnt < 6000000; cnt++) {	1194	for (cnt = 0; cnt < 60; cnt++) {
1195	barrier();	1195	barrier();
1196	if ((RD_REG_DWORD(&reg->ctrl_status) &	1196	if ((RD_REG_DWORD(&reg->ctrl_status) &
1197	CSRX_ISP_SOFT_RESET) == 0)	1197	CSRX_ISP_SOFT_RESET) == 0)
@@ -1234,7 +1234,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha) · 36 unmodified lines
1234	RD_REG_DWORD(&reg->hccr);	1234	RD_REG_DWORD(&reg->hccr);
1235		1235
1236	RD_REG_WORD(&reg->mailbox0);	1236	RD_REG_WORD(&reg->mailbox0);
1237	for (cnt = 6000000; RD_REG_WORD(&reg->mailbox0) != 0 &&	1237	for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
1238	rval == QLA_SUCCESS; cnt--) {	1238	rval == QLA_SUCCESS; cnt--) {
1239	barrier();	1239	barrier();
1240	if (cnt)	1240	if (cnt)

drivers/scsi/qla2xxx/qla_isr.c+15−77

@@ -19,10 +19,6 @@ static void qla2x00_status_entry(scsi_qla_host_t , struct rsp_que , void *); · 18 unmodified lines
19	static void qla2x00_status_cont_entry(struct rsp_que , sts_cont_entry_t );	19	static void qla2x00_status_cont_entry(struct rsp_que , sts_cont_entry_t );
20	static void qla2x00_error_entry(scsi_qla_host_t , struct rsp_que ,	20	static void qla2x00_error_entry(scsi_qla_host_t , struct rsp_que ,
21	sts_entry_t *);	21	sts_entry_t *);
22	static void qla_irq_affinity_notify(struct irq_affinity_notify *,
23	const cpumask_t *);
24	static void qla_irq_affinity_release(struct kref *);
25
26		22
27	/**	23	/**
28	* qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.	24	* qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
@@ -2496,6 +2492,10 @@ qla2x00_error_entry(scsi_qla_host_t vha, struct rsp_que rsp, sts_entry_t *pkt) · 2467 unmodified lines
2496	if (pkt->entry_status & RF_BUSY)	2492	if (pkt->entry_status & RF_BUSY)
2497	res = DID_BUS_BUSY << 16;	2493	res = DID_BUS_BUSY << 16;
2498		2494
		2495	if (pkt->entry_type == NOTIFY_ACK_TYPE &&
		2496	pkt->handle == QLA_TGT_SKIP_HANDLE)
		2497	return;
		2498
2499	sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);	2499	sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2500	if (sp) {	2500	if (sp) {
2501	sp->done(ha, sp, res);	2501	sp->done(ha, sp, res);
@@ -2572,14 +2572,6 @@ void qla24xx_process_response_queue(struct scsi_qla_host *vha, · 70 unmodified lines
2572	if (!vha->flags.online)	2572	if (!vha->flags.online)
2573	return;	2573	return;
2574		2574
2575	if (rsp->msix && rsp->msix->cpuid != smp_processor_id()) {
2576	/* if kernel does not notify qla of IRQ's CPU change,
2577	* then set it here.
2578	*/
2579	rsp->msix->cpuid = smp_processor_id();
2580	ha->tgt.rspq_vector_cpuid = rsp->msix->cpuid;
2581	}
2582
2583	while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {	2575	while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
2584	pkt = (struct sts_entry_24xx *)rsp->ring_ptr;	2576	pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
2585		2577
@@ -3018,13 +3010,20 @@ static struct qla_init_msix_entry qla82xx_msix_entries[] = { · 432 unmodified lines
3018	static int	3010	static int
3019	qla24xx_enable_msix(struct qla_hw_data ha, struct rsp_que rsp)	3011	qla24xx_enable_msix(struct qla_hw_data ha, struct rsp_que rsp)
3020	{	3012	{
3021	#define MIN_MSIX_COUNT 2
3022	int i, ret;	3013	int i, ret;
3023	struct qla_msix_entry *qentry;	3014	struct qla_msix_entry *qentry;
3024	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);	3015	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
		3016	struct irq_affinity desc = {
		3017	.pre_vectors = QLA_BASE_VECTORS,
		3018	};
		3019
		3020	if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha))
		3021	desc.pre_vectors++;
		3022
		3023	ret = pci_alloc_irq_vectors_affinity(ha->pdev, QLA_BASE_VECTORS,
		3024	ha->msix_count, PCI_IRQ_MSIX \| PCI_IRQ_AFFINITY,
		3025	&desc);
3025		3026
3026	ret = pci_alloc_irq_vectors(ha->pdev, MIN_MSIX_COUNT, ha->msix_count,
3027	PCI_IRQ_MSIX \| PCI_IRQ_AFFINITY);
3028	if (ret < 0) {	3027	if (ret < 0) {
3029	ql_log(ql_log_fatal, vha, 0x00c7,	3028	ql_log(ql_log_fatal, vha, 0x00c7,
3030	"MSI-X: Failed to enable support, "	3029	"MSI-X: Failed to enable support, "
@@ -3069,13 +3068,10 @@ qla24xx_enable_msix(struct qla_hw_data ha, struct rsp_que rsp) · 38 unmodified lines
3069	qentry->have_irq = 0;	3068	qentry->have_irq = 0;
3070	qentry->in_use = 0;	3069	qentry->in_use = 0;
3071	qentry->handle = NULL;	3070	qentry->handle = NULL;
3072	qentry->irq_notify.notify = qla_irq_affinity_notify;
3073	qentry->irq_notify.release = qla_irq_affinity_release;
3074	qentry->cpuid = -1;
3075	}	3071	}
3076		3072
3077	/* Enable MSI-X vectors for the base queue */	3073	/* Enable MSI-X vectors for the base queue */
3078	for (i = 0; i < (QLA_MSIX_RSP_Q + 1); i++) {	3074	for (i = 0; i < QLA_BASE_VECTORS; i++) {
3079	qentry = &ha->msix_entries[i];	3075	qentry = &ha->msix_entries[i];
3080	qentry->handle = rsp;	3076	qentry->handle = rsp;
3081	rsp->msix = qentry;	3077	rsp->msix = qentry;
@@ -3093,18 +3089,6 @@ qla24xx_enable_msix(struct qla_hw_data ha, struct rsp_que rsp) · 11 unmodified lines
3093	goto msix_register_fail;	3089	goto msix_register_fail;
3094	qentry->have_irq = 1;	3090	qentry->have_irq = 1;
3095	qentry->in_use = 1;	3091	qentry->in_use = 1;
3096
3097	/* Register for CPU affinity notification. */
3098	irq_set_affinity_notifier(qentry->vector, &qentry->irq_notify);
3099
3100	/* Schedule work (ie. trigger a notification) to read cpu
3101	* mask for this specific irq.
3102	* kref_get is required because
3103	* irq_affinity_notify() will do
3104	* kref_put().
3105	*/
3106	kref_get(&qentry->irq_notify.kref);
3107	schedule_work(&qentry->irq_notify.work);
3108	}	3092	}
3109		3093
3110	/*	3094	/*
@@ -3301,49 +3285,3 @@ int qla25xx_request_irq(struct qla_hw_data ha, struct qla_qpair qpair, · 190 unmodified lines
3301	msix->handle = qpair;	3285	msix->handle = qpair;
3302	return ret;	3286	return ret;
3303	}	3287	}
3304
3305
3306	/* irq_set_affinity/irqbalance will trigger notification of cpu mask update */
3307	static void qla_irq_affinity_notify(struct irq_affinity_notify *notify,
3308	const cpumask_t *mask)
3309	{
3310	struct qla_msix_entry *e =
3311	container_of(notify, struct qla_msix_entry, irq_notify);
3312	struct qla_hw_data *ha;
3313	struct scsi_qla_host *base_vha;
3314	struct rsp_que *rsp = e->handle;
3315
3316	/* user is recommended to set mask to just 1 cpu */
3317	e->cpuid = cpumask_first(mask);
3318
3319	ha = rsp->hw;
3320	base_vha = pci_get_drvdata(ha->pdev);
3321
3322	ql_dbg(ql_dbg_init, base_vha, 0xffff,
3323	"%s: host %ld : vector %d cpu %d \n", __func__,
3324	base_vha->host_no, e->vector, e->cpuid);
3325
3326	if (e->have_irq) {
3327	if ((IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) &&
3328	(e->entry == QLA83XX_RSPQ_MSIX_ENTRY_NUMBER)) {
3329	ha->tgt.rspq_vector_cpuid = e->cpuid;
3330	ql_dbg(ql_dbg_init, base_vha, 0xffff,
3331	"%s: host%ld: rspq vector %d cpu %d runtime change\n",
3332	__func__, base_vha->host_no, e->vector, e->cpuid);
3333	}
3334	}
3335	}
3336
3337	static void qla_irq_affinity_release(struct kref *ref)
3338	{
3339	struct irq_affinity_notify *notify =
3340	container_of(ref, struct irq_affinity_notify, kref);
3341	struct qla_msix_entry *e =
3342	container_of(notify, struct qla_msix_entry, irq_notify);
3343	struct rsp_que *rsp = e->handle;
3344	struct scsi_qla_host *base_vha = pci_get_drvdata(rsp->hw->pdev);
3345
3346	ql_dbg(ql_dbg_init, base_vha, 0xffff,
3347	"%s: host%ld: vector %d cpu %d\n", __func__,
3348	base_vha->host_no, e->vector, e->cpuid);
3349	}

drivers/scsi/qla2xxx/qla_mbx.c+24−13

 #include <linux/delay.h>
 #include <linux/gfp.h>
-struct rom_cmd {
+static struct rom_cmd {
 	uint16_t cmd;
 } rom_cmds[] = {
 	{ MBC_LOAD_RAM },
 		return QLA_FUNCTION_TIMEOUT;
 	}
-	 /* if PCI error, then avoid mbx processing.*/
+	/* if PCI error, then avoid mbx processing.*/
-	 if (test_bit(PCI_ERR, &base_vha->dpc_flags)) {
+	if (test_bit(PCI_ERR, &base_vha->dpc_flags)) {
 		ql_log(ql_log_warn, vha, 0x1191,
 		    "PCI error, exiting.\n");
 		return QLA_FUNCTION_TIMEOUT;
-	 }
+	}
 	reg = ha->iobase;
 	io_lock_on = base_vha->flags.init_done;
 		}
 	} else {
-		uint16_t mb0;
+		uint16_t mb[8];
-		uint32_t ictrl;
+		uint32_t ictrl, host_status, hccr;
 		uint16_t        w;
 		if (IS_FWI2_CAPABLE(ha)) {
-			mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
+			mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
+			mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
+			mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
+			mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
+			mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
 			ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
+			host_status = RD_REG_DWORD(&reg->isp24.host_status);
+			hccr = RD_REG_DWORD(&reg->isp24.hccr);
+			ql_log(ql_log_warn, vha, 0x1119,
+			    "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
+			    "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
+			    command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
+			    mb[7], host_status, hccr);
 		} else {
-			mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
+			mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
 			ictrl = RD_REG_WORD(&reg->isp.ictrl);
+			ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
+			    "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
+			    "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
 		}
-		ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
-		    "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
-		    "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
 		ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
 		/* Capture FW dump only, if PCI device active */
 	mbx_cmd_t	mc;
 	mbx_cmd_t	*mcp = &mc;
 	struct qla_hw_data *ha = vha->hw;
-	int configured_count;
 	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
 	    "Entered %s.\n", __func__);
 		/*EMPTY*/
 		ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
 	} else {
-		configured_count = mcp->mb[11];
 		ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
 		    "Done %s.\n", __func__);
 	}

drivers/scsi/qla2xxx/qla_nx.c+5−0

 	(crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
 	QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
+const int MD_MIU_TEST_AGT_RDDATA[] = {
+	0x410000A8, 0x410000AC,
+	0x410000B8, 0x410000BC
+};
 static void qla82xx_crb_addr_transform_setup(void)
 {
 	qla82xx_crb_addr_transform(XDMA);

drivers/scsi/qla2xxx/qla_nx.h+1−2

@@ -1176,8 +1176,7 @@ struct qla82xx_md_entry_queue { · 1175 unmodified lines
1176	#define MD_MIU_TEST_AGT_ADDR_LO 0x41000094	1176	#define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1177	#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098	1177	#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1178		1178
1179	static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8, 0x410000AC,	1179	extern const int MD_MIU_TEST_AGT_RDDATA[4];
1180	0x410000B8, 0x410000BC };
1181		1180
1182	#define CRB_NIU_XG_PAUSE_CTL_P0 0x1	1181	#define CRB_NIU_XG_PAUSE_CTL_P0 0x1
1183	#define CRB_NIU_XG_PAUSE_CTL_P1 0x8	1182	#define CRB_NIU_XG_PAUSE_CTL_P1 0x8

drivers/scsi/qla2xxx/qla_nx2.c+17−0

@@ -15,6 +15,23 @@ · 14 unmodified lines
15		15
16	#define TIMEOUT_100_MS 100	16	#define TIMEOUT_100_MS 100
17		17
		18	static const uint32_t qla8044_reg_tbl[] = {
		19	QLA8044_PEG_HALT_STATUS1,
		20	QLA8044_PEG_HALT_STATUS2,
		21	QLA8044_PEG_ALIVE_COUNTER,
		22	QLA8044_CRB_DRV_ACTIVE,
		23	QLA8044_CRB_DEV_STATE,
		24	QLA8044_CRB_DRV_STATE,
		25	QLA8044_CRB_DRV_SCRATCH,
		26	QLA8044_CRB_DEV_PART_INFO1,
		27	QLA8044_CRB_IDC_VER_MAJOR,
		28	QLA8044_FW_VER_MAJOR,
		29	QLA8044_FW_VER_MINOR,
		30	QLA8044_FW_VER_SUB,
		31	QLA8044_CMDPEG_STATE,
		32	QLA8044_ASIC_TEMP,
		33	};
		34
18	/* 8044 Flash Read/Write functions */	35	/* 8044 Flash Read/Write functions */
19	uint32_t	36	uint32_t
20	qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)	37	qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)

drivers/scsi/qla2xxx/qla_nx2.h+0−17

@@ -535,23 +535,6 @@ enum qla_regs { · 534 unmodified lines
535	#define CRB_CMDPEG_CHECK_RETRY_COUNT 60	535	#define CRB_CMDPEG_CHECK_RETRY_COUNT 60
536	#define CRB_CMDPEG_CHECK_DELAY 500	536	#define CRB_CMDPEG_CHECK_DELAY 500
537		537
538	static const uint32_t qla8044_reg_tbl[] = {
539	QLA8044_PEG_HALT_STATUS1,
540	QLA8044_PEG_HALT_STATUS2,
541	QLA8044_PEG_ALIVE_COUNTER,
542	QLA8044_CRB_DRV_ACTIVE,
543	QLA8044_CRB_DEV_STATE,
544	QLA8044_CRB_DRV_STATE,
545	QLA8044_CRB_DRV_SCRATCH,
546	QLA8044_CRB_DEV_PART_INFO1,
547	QLA8044_CRB_IDC_VER_MAJOR,
548	QLA8044_FW_VER_MAJOR,
549	QLA8044_FW_VER_MINOR,
550	QLA8044_FW_VER_SUB,
551	QLA8044_CMDPEG_STATE,
552	QLA8044_ASIC_TEMP,
553	};
554
555	/* MiniDump Structures */	538	/* MiniDump Structures */
556		539
557	/* Driver_code is for driver to write some info about the entry	540	/* Driver_code is for driver to write some info about the entry

drivers/scsi/qla2xxx/qla_os.c+13−5

 			continue;
 		rsp = ha->rsp_q_map[cnt];
-		clear_bit(cnt, ha->req_qid_map);
+		clear_bit(cnt, ha->rsp_qid_map);
 		ha->rsp_q_map[cnt] =  NULL;
 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
 		qla2x00_free_rsp_que(ha, rsp);
 				sizeof(struct ct6_dsd), 0,
 				SLAB_HWCACHE_ALIGN, NULL);
 			if (!ctx_cachep)
-				goto fail_free_gid_list;
+				goto fail_free_srb_mempool;
 		}
 		ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
 			ctx_cachep);
 	ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
 	    GFP_KERNEL);
 	if (!ha->loop_id_map)
-		goto fail_async_pd;
+		goto fail_loop_id_map;
 	else {
 		qla2x00_set_reserved_loop_ids(ha);
 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
 	return 0;
+fail_loop_id_map:
+	dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
 fail_async_pd:
 	dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
 fail_ex_init_cb:
 	dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
 	ha->ms_iocb = NULL;
 	ha->ms_iocb_dma = 0;
+	if (ha->sns_cmd)
+		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
+		    ha->sns_cmd, ha->sns_cmd_dma);
 fail_dma_pool:
 	if (IS_QLA82XX(ha) || ql2xenabledif) {
 		dma_pool_destroy(ha->fcp_cmnd_dma_pool);
 	kfree(ha->nvram);
 	ha->nvram = NULL;
 fail_free_ctx_mempool:
-	mempool_destroy(ha->ctx_mempool);
+	if (ha->ctx_mempool)
+		mempool_destroy(ha->ctx_mempool);
 	ha->ctx_mempool = NULL;
 fail_free_srb_mempool:
-	mempool_destroy(ha->srb_mempool);
+	if (ha->srb_mempool)
+		mempool_destroy(ha->srb_mempool);
 	ha->srb_mempool = NULL;
 fail_free_gid_list:
 	dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),

drivers/scsi/qla2xxx/qla_target.c+39−18

 {
 	struct qla_hw_data *ha = vha->hw;
 	struct qla_tgt_sess *sess = NULL;
-	uint32_t unpacked_lun, lun = 0;
 	uint16_t loop_id;
 	int res = 0;
 	struct imm_ntfy_from_isp *n = (struct imm_ntfy_from_isp *)iocb;
-	struct atio_from_isp *a = (struct atio_from_isp *)iocb;
 	unsigned long flags;
 	loop_id = le16_to_cpu(n->u.isp24.nport_handle);
 	    "loop_id %d)\n", vha->host_no, sess, sess->port_name,
 	    mcmd, loop_id);
-	lun = a->u.isp24.fcp_cmnd.lun;
+	return qlt_issue_task_mgmt(sess, 0, mcmd, iocb, QLA24XX_MGMT_SEND_NACK);
-	unpacked_lun = scsilun_to_int((struct scsi_lun *)&lun);
-	return qlt_issue_task_mgmt(sess, unpacked_lun, mcmd,
-	    iocb, QLA24XX_MGMT_SEND_NACK);
 }
 /* ha->tgt.sess_lock supposed to be held on entry */
 	pkt->entry_type = NOTIFY_ACK_TYPE;
 	pkt->entry_count = 1;
-	pkt->handle = QLA_TGT_SKIP_HANDLE | CTIO_COMPLETION_HANDLE_MARK;
+	pkt->handle = QLA_TGT_SKIP_HANDLE;
 	nack = (struct nack_to_isp *)pkt;
 	nack->ox_id = ntfy->ox_id;
 #if 0	/* Todo  */
 		if (rc == -ENOMEM)
 			qlt_alloc_qfull_cmd(vha, imm, 0, 0);
+#else
+		if (rc) {
+		}
 #endif
 		goto done;
 	}
 	if (!vha->flags.online)
 		return;
-	while (ha->tgt.atio_ring_ptr->signature != ATIO_PROCESSED) {
+	while ((ha->tgt.atio_ring_ptr->signature != ATIO_PROCESSED) ||
+	    fcpcmd_is_corrupted(ha->tgt.atio_ring_ptr)) {
 		pkt = (struct atio_from_isp *)ha->tgt.atio_ring_ptr;
 		cnt = pkt->u.raw.entry_count;
-		qlt_24xx_atio_pkt_all_vps(vha, (struct atio_from_isp *)pkt,
+		if (unlikely(fcpcmd_is_corrupted(ha->tgt.atio_ring_ptr))) {
-		    ha_locked);
+			/*
+			 * This packet is corrupted. The header + payload
+			 * can not be trusted. There is no point in passing
+			 * it further up.
+			 */
+			ql_log(ql_log_warn, vha, 0xffff,
+			    "corrupted fcp frame SID[%3phN] OXID[%04x] EXCG[%x] %64phN\n",
+			    pkt->u.isp24.fcp_hdr.s_id,
+			    be16_to_cpu(pkt->u.isp24.fcp_hdr.ox_id),
+			    le32_to_cpu(pkt->u.isp24.exchange_addr), pkt);
+			adjust_corrupted_atio(pkt);
+			qlt_send_term_exchange(vha, NULL, pkt, ha_locked, 0);
+		} else {
+			qlt_24xx_atio_pkt_all_vps(vha,
+			    (struct atio_from_isp *)pkt, ha_locked);
+		}
 		for (i = 0; i < cnt; i++) {
 			ha->tgt.atio_ring_index++;
 		/* Disable Full Login after LIP */
 		nv->host_p &= cpu_to_le32(~BIT_10);
+		/*
+		 * clear BIT 15 explicitly as we have seen at least
+		 * a couple of instances where this was set and this
+		 * was causing the firmware to not be initialized.
+		 */
+		nv->firmware_options_1 &= cpu_to_le32(~BIT_15);
 		/* Enable target PRLI control */
 		nv->firmware_options_2 |= cpu_to_le32(BIT_14);
 	} else {
 		return;
 	}
-	/* out-of-order frames reassembly */
-	nv->firmware_options_3 |= BIT_6|BIT_9;
 	if (ha->tgt.enable_class_2) {
 		if (vha->flags.init_done)
 			fc_host_supported_classes(vha->host) =
 		/* Disable ini mode, if requested */
 		if (!qla_ini_mode_enabled(vha))
 			nv->firmware_options_1 |= cpu_to_le32(BIT_5);
 		/* Disable Full Login after LIP */
 		nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
 		/* Enable initial LIP */
 		nv->firmware_options_1 &= cpu_to_le32(~BIT_9);
+		/*
+		 * clear BIT 15 explicitly as we have seen at
+		 * least a couple of instances where this was set
+		 * and this was causing the firmware to not be
+		 * initialized.
+		 */
+		nv->firmware_options_1 &= cpu_to_le32(~BIT_15);
 		if (ql2xtgt_tape_enable)
 			/* Enable FC tape support */
 			nv->firmware_options_2 |= cpu_to_le32(BIT_12);
 		return;
 	}
-	/* out-of-order frames reassembly */
-	nv->firmware_options_3 |= BIT_6|BIT_9;
 	if (ha->tgt.enable_class_2) {
 		if (vha->flags.init_done)
 			fc_host_supported_classes(vha->host) =

drivers/scsi/qla2xxx/qla_target.h+21−1

@@ -427,13 +427,33 @@ struct atio_from_isp { · 426 unmodified lines
427	struct {	427	struct {
428	uint8_t entry_type; /* Entry type. */	428	uint8_t entry_type; /* Entry type. */
429	uint8_t entry_count; /* Entry count. */	429	uint8_t entry_count; /* Entry count. */
430	uint8_t data[58];	430	__le16 attr_n_length;
		431	#define FCP_CMD_LENGTH_MASK 0x0fff
		432	#define FCP_CMD_LENGTH_MIN 0x38
		433	uint8_t data[56];
431	uint32_t signature;	434	uint32_t signature;
432	#define ATIO_PROCESSED 0xDEADDEAD /* Signature */	435	#define ATIO_PROCESSED 0xDEADDEAD /* Signature */
433	} raw;	436	} raw;
434	} u;	437	} u;
435	} __packed;	438	} __packed;
436		439
		440	static inline int fcpcmd_is_corrupted(struct atio *atio)
		441	{
		442	if (atio->entry_type == ATIO_TYPE7 &&
		443	(le16_to_cpu(atio->attr_n_length & FCP_CMD_LENGTH_MASK) <
		444	FCP_CMD_LENGTH_MIN))
		445	return 1;
		446	else
		447	return 0;
		448	}
		449
		450	/* adjust corrupted atio so we won't trip over the same entry again. */
		451	static inline void adjust_corrupted_atio(struct atio_from_isp *atio)
		452	{
		453	atio->u.raw.attr_n_length = cpu_to_le16(FCP_CMD_LENGTH_MIN);
		454	atio->u.isp24.fcp_cmnd.add_cdb_len = 0;
		455	}
		456
437	#define CTIO_TYPE7 0x12 /* Continue target I/O entry (for 24xx) */	457	#define CTIO_TYPE7 0x12 /* Continue target I/O entry (for 24xx) */
438		458
439	/*	459	/*

drivers/scsi/qla2xxx/qla_tmpl.c+24−0

@@ -433,6 +433,18 @@ qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha, · 432 unmodified lines
433	count++;	433	count++;
434	}	434	}
435	}	435	}
		436	} else if (QLA_TGT_MODE_ENABLED() &&
		437	ent->t263.queue_type == T263_QUEUE_TYPE_ATIO) {
		438	struct qla_hw_data *ha = vha->hw;
		439	struct atio *atr = ha->tgt.atio_ring;
		440
		441	if (atr \|\| !buf) {
		442	length = ha->tgt.atio_q_length;
		443	qla27xx_insert16(0, buf, len);
		444	qla27xx_insert16(length, buf, len);
		445	qla27xx_insertbuf(atr, length * sizeof(*atr), buf, len);
		446	count++;
		447	}
436	} else {	448	} else {
437	ql_dbg(ql_dbg_misc, vha, 0xd026,	449	ql_dbg(ql_dbg_misc, vha, 0xd026,
438	"%s: unknown queue %x\n", __func__, ent->t263.queue_type);	450	"%s: unknown queue %x\n", __func__, ent->t263.queue_type);
@@ -676,6 +688,18 @@ qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha, · 237 unmodified lines
676	count++;	688	count++;
677	}	689	}
678	}	690	}
		691	} else if (QLA_TGT_MODE_ENABLED() &&
		692	ent->t274.queue_type == T274_QUEUE_TYPE_ATIO_SHAD) {
		693	struct qla_hw_data *ha = vha->hw;
		694	struct atio *atr = ha->tgt.atio_ring_ptr;
		695
		696	if (atr \|\| !buf) {
		697	qla27xx_insert16(0, buf, len);
		698	qla27xx_insert16(1, buf, len);
		699	qla27xx_insert32(ha->tgt.atio_q_in ?
		700	readl(ha->tgt.atio_q_in) : 0, buf, len);
		701	count++;
		702	}
679	} else {	703	} else {
680	ql_dbg(ql_dbg_misc, vha, 0xd02f,	704	ql_dbg(ql_dbg_misc, vha, 0xd02f,
681	"%s: unknown queue %x\n", __func__, ent->t274.queue_type);	705	"%s: unknown queue %x\n", __func__, ent->t274.queue_type);

drivers/scsi/qla2xxx/tcm_qla2xxx.c+2−2

@@ -1800,7 +1800,7 @@ static ssize_t tcm_qla2xxx_wwn_version_show(struct config_item *item, · 1799 unmodified lines
1800	{	1800	{
1801	return sprintf(page,	1801	return sprintf(page,
1802	"TCM QLOGIC QLA2XXX NPIV capable fabric module %s on %s/%s on "	1802	"TCM QLOGIC QLA2XXX NPIV capable fabric module %s on %s/%s on "
1803	UTS_RELEASE"\n", TCM_QLA2XXX_VERSION, utsname()->sysname,	1803	UTS_RELEASE"\n", QLA2XXX_VERSION, utsname()->sysname,
1804	utsname()->machine);	1804	utsname()->machine);
1805	}	1805	}
1806		1806
@@ -1906,7 +1906,7 @@ static int tcm_qla2xxx_register_configfs(void) · 99 unmodified lines
1906	int ret;	1906	int ret;
1907		1907
1908	pr_debug("TCM QLOGIC QLA2XXX fabric module %s on %s/%s on "	1908	pr_debug("TCM QLOGIC QLA2XXX fabric module %s on %s/%s on "
1909	UTS_RELEASE"\n", TCM_QLA2XXX_VERSION, utsname()->sysname,	1909	UTS_RELEASE"\n", QLA2XXX_VERSION, utsname()->sysname,
1910	utsname()->machine);	1910	utsname()->machine);
1911		1911
1912	ret = target_register_template(&tcm_qla2xxx_ops);	1912	ret = target_register_template(&tcm_qla2xxx_ops);

drivers/scsi/qla2xxx/tcm_qla2xxx.h+0−1

@@ -1,7 +1,6 @@
1	#include <target/target_core_base.h>	1	#include <target/target_core_base.h>
2	#include <linux/btree.h>	2	#include <linux/btree.h>
3		3
4	#define TCM_QLA2XXX_VERSION "v0.1"
5	/* length of ASCII WWPNs including pad */	4	/* length of ASCII WWPNs including pad */
6	#define TCM_QLA2XXX_NAMELEN 32	5	#define TCM_QLA2XXX_NAMELEN 32
7	/*	6	/*

drivers/scsi/sd.c+16−7

 		if (sdp->broken_fua) {
 			sd_first_printk(KERN_NOTICE, sdkp, "Disabling FUA\n");
 			sdkp->DPOFUA = 0;
-		} else if (sdkp->DPOFUA && !sdkp->device->use_10_for_rw) {
+		} else if (sdkp->DPOFUA && !sdkp->device->use_10_for_rw &&
+			   !sdkp->device->use_16_for_rw) {
 			sd_first_printk(KERN_NOTICE, sdkp,
 				  "Uses READ/WRITE(6), disabling FUA\n");
 			sdkp->DPOFUA = 0;
 		queue_flag_clear_unlocked(QUEUE_FLAG_ADD_RANDOM, q);
 	}
-	sdkp->zoned = (buffer[8] >> 4) & 3;
+	if (sdkp->device->type == TYPE_ZBC) {
-	if (sdkp->zoned == 1)
+		/* Host-managed */
-		q->limits.zoned = BLK_ZONED_HA;
-	else if (sdkp->device->type == TYPE_ZBC)
 		q->limits.zoned = BLK_ZONED_HM;
-	else
+	} else {
-		q->limits.zoned = BLK_ZONED_NONE;
+		sdkp->zoned = (buffer[8] >> 4) & 3;
+		if (sdkp->zoned == 1)
+			/* Host-aware */
+			q->limits.zoned = BLK_ZONED_HA;
+		else
+			/*
+			 * Treat drive-managed devices as
+			 * regular block devices.
+			 */
+			q->limits.zoned = BLK_ZONED_NONE;
+	}
 	if (blk_queue_is_zoned(q) && sdkp->first_scan)
 		sd_printk(KERN_NOTICE, sdkp, "Host-%s zoned block device\n",
 		      q->limits.zoned == BLK_ZONED_HM ? "managed" : "aware");

drivers/scsi/ses.c+1−1

@@ -587,7 +587,7 @@ static void ses_match_to_enclosure(struct enclosure_device *edev, · 586 unmodified lines
587		587
588	ses_enclosure_data_process(edev, to_scsi_device(edev->edev.parent), 0);	588	ses_enclosure_data_process(edev, to_scsi_device(edev->edev.parent), 0);
589		589
590	if (scsi_is_sas_rphy(&sdev->sdev_gendev))	590	if (scsi_is_sas_rphy(sdev->sdev_target->dev.parent))
591	efd.addr = sas_get_address(sdev);	591	efd.addr = sas_get_address(sdev);
592		592
593	if (efd.addr) {	593	if (efd.addr) {

drivers/soc/ti/wkup_m3_ipc.c+1−0

@@ -459,6 +459,7 @@ static int wkup_m3_ipc_probe(struct platform_device *pdev) · 458 unmodified lines
459		459
460	if (IS_ERR(task)) {	460	if (IS_ERR(task)) {
461	dev_err(dev, "can't create rproc_boot thread\n");	461	dev_err(dev, "can't create rproc_boot thread\n");
		462	ret = PTR_ERR(task);
462	goto err_put_rproc;	463	goto err_put_rproc;
463	}	464	}
464		465

drivers/spi/Kconfig+1−0

@@ -378,6 +378,7 @@ config SPI_FSL_SPI · 377 unmodified lines
378	config SPI_FSL_DSPI	378	config SPI_FSL_DSPI
379	tristate "Freescale DSPI controller"	379	tristate "Freescale DSPI controller"
380	select REGMAP_MMIO	380	select REGMAP_MMIO
		381	depends on HAS_DMA
381	depends on SOC_VF610 \|\| SOC_LS1021A \|\| ARCH_LAYERSCAPE \|\| COMPILE_TEST	382	depends on SOC_VF610 \|\| SOC_LS1021A \|\| ARCH_LAYERSCAPE \|\| COMPILE_TEST
382	help	383	help
383	This enables support for the Freescale DSPI controller in master	384	This enables support for the Freescale DSPI controller in master

drivers/spi/spi-armada-3700.c+6−5

 	struct spi_master *master;
 	struct a3700_spi *spi;
 	u32 num_cs = 0;
-	int ret = 0;
+	int irq, ret = 0;
 	master = spi_alloc_master(dev, sizeof(*spi));
 	if (!master) {
 	master->unprepare_message = a3700_spi_unprepare_message;
 	master->set_cs = a3700_spi_set_cs;
 	master->flags = SPI_MASTER_HALF_DUPLEX;
-	master->mode_bits |= (SPI_RX_DUAL | SPI_RX_DUAL |
+	master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL |
 			      SPI_RX_QUAD | SPI_TX_QUAD);
 	platform_set_drvdata(pdev, master);
 		goto error;
 	}
-	spi->irq = platform_get_irq(pdev, 0);
+	irq = platform_get_irq(pdev, 0);
-	if (spi->irq < 0) {
+	if (irq < 0) {
-		dev_err(dev, "could not get irq: %d\n", spi->irq);
+		dev_err(dev, "could not get irq: %d\n", irq);
 		ret = -ENXIO;
 		goto error;
 	}
+	spi->irq = irq;
 	init_completion(&spi->done);

drivers/spi/spi-axi-spi-engine.c+2−1

@@ -494,7 +494,8 @@ static int spi_engine_probe(struct platform_device *pdev) · 493 unmodified lines
494	SPI_ENGINE_VERSION_MAJOR(version),	494	SPI_ENGINE_VERSION_MAJOR(version),
495	SPI_ENGINE_VERSION_MINOR(version),	495	SPI_ENGINE_VERSION_MINOR(version),
496	SPI_ENGINE_VERSION_PATCH(version));	496	SPI_ENGINE_VERSION_PATCH(version));
497	return -ENODEV;	497	ret = -ENODEV;
		498	goto err_put_master;
498	}	499	}
499		500
500	spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");	501	spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");

drivers/spi/spi-davinci.c+2−2

@@ -646,7 +646,7 @@ static int davinci_spi_bufs(struct spi_device spi, struct spi_transfer t) · 645 unmodified lines
646	buf = t->rx_buf;	646	buf = t->rx_buf;
647	t->rx_dma = dma_map_single(&spi->dev, buf,	647	t->rx_dma = dma_map_single(&spi->dev, buf,
648	t->len, DMA_FROM_DEVICE);	648	t->len, DMA_FROM_DEVICE);
649	if (!t->rx_dma) {	649	if (dma_mapping_error(&spi->dev, !t->rx_dma)) {
650	ret = -EFAULT;	650	ret = -EFAULT;
651	goto err_rx_map;	651	goto err_rx_map;
652	}	652	}
@@ -660,7 +660,7 @@ static int davinci_spi_bufs(struct spi_device spi, struct spi_transfer t) · 7 unmodified lines
660	buf = (void *)t->tx_buf;	660	buf = (void *)t->tx_buf;
661	t->tx_dma = dma_map_single(&spi->dev, buf,	661	t->tx_dma = dma_map_single(&spi->dev, buf,
662	t->len, DMA_TO_DEVICE);	662	t->len, DMA_TO_DEVICE);
663	if (!t->tx_dma) {	663	if (dma_mapping_error(&spi->dev, t->tx_dma)) {
664	ret = -EFAULT;	664	ret = -EFAULT;
665	goto err_tx_map;	665	goto err_tx_map;
666	}	666	}

drivers/spi/spi-dw-mid.c+2−2

@@ -274,11 +274,11 @@ static int mid_spi_dma_transfer(struct dw_spi dws, struct spi_transfer xfer) · 273 unmodified lines
274	static void mid_spi_dma_stop(struct dw_spi *dws)	274	static void mid_spi_dma_stop(struct dw_spi *dws)
275	{	275	{
276	if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {	276	if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
277	dmaengine_terminate_all(dws->txchan);	277	dmaengine_terminate_sync(dws->txchan);
278	clear_bit(TX_BUSY, &dws->dma_chan_busy);	278	clear_bit(TX_BUSY, &dws->dma_chan_busy);
279	}	279	}
280	if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {	280	if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
281	dmaengine_terminate_all(dws->rxchan);	281	dmaengine_terminate_sync(dws->rxchan);
282	clear_bit(RX_BUSY, &dws->dma_chan_busy);	282	clear_bit(RX_BUSY, &dws->dma_chan_busy);
283	}	283	}
284	}	284	}

drivers/spi/spi-dw.c+4−1

@@ -107,7 +107,10 @@ static const struct file_operations dw_spi_regs_ops = { · 106 unmodified lines
107		107
108	static int dw_spi_debugfs_init(struct dw_spi *dws)	108	static int dw_spi_debugfs_init(struct dw_spi *dws)
109	{	109	{
110	dws->debugfs = debugfs_create_dir("dw_spi", NULL);	110	char name[128];
		111
		112	snprintf(name, 128, "dw_spi-%s", dev_name(&dws->master->dev));
		113	dws->debugfs = debugfs_create_dir(name, NULL);
111	if (!dws->debugfs)	114	if (!dws->debugfs)
112	return -ENOMEM;	115	return -ENOMEM;
113		116

drivers/spi/spi-pxa2xx.c+1−0

@@ -1690,6 +1690,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) · 1689 unmodified lines
1690	pxa2xx_spi_write(drv_data, SSCR1, tmp);	1690	pxa2xx_spi_write(drv_data, SSCR1, tmp);
1691	tmp = SSCR0_SCR(2) \| SSCR0_Motorola \| SSCR0_DataSize(8);	1691	tmp = SSCR0_SCR(2) \| SSCR0_Motorola \| SSCR0_DataSize(8);
1692	pxa2xx_spi_write(drv_data, SSCR0, tmp);	1692	pxa2xx_spi_write(drv_data, SSCR0, tmp);
		1693	break;
1693	default:	1694	default:
1694	tmp = SSCR1_RxTresh(RX_THRESH_DFLT) \|	1695	tmp = SSCR1_RxTresh(RX_THRESH_DFLT) \|
1695	SSCR1_TxTresh(TX_THRESH_DFLT);	1696	SSCR1_TxTresh(TX_THRESH_DFLT);

drivers/spi/spi-sh-msiof.c+3−1

 };
 static const struct of_device_id sh_msiof_match[] = {
-	{ .compatible = "renesas,sh-msiof",        .data = &sh_data },
 	{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
 	{ .compatible = "renesas,msiof-r8a7790",   .data = &r8a779x_data },
 	{ .compatible = "renesas,msiof-r8a7791",   .data = &r8a779x_data },
 	{ .compatible = "renesas,msiof-r8a7792",   .data = &r8a779x_data },
 	{ .compatible = "renesas,msiof-r8a7793",   .data = &r8a779x_data },
 	{ .compatible = "renesas,msiof-r8a7794",   .data = &r8a779x_data },
+	{ .compatible = "renesas,rcar-gen2-msiof", .data = &r8a779x_data },
 	{ .compatible = "renesas,msiof-r8a7796",   .data = &r8a779x_data },
+	{ .compatible = "renesas,rcar-gen3-msiof", .data = &r8a779x_data },
+	{ .compatible = "renesas,sh-msiof",        .data = &sh_data }, /* Deprecated */
 	{},
 };
 MODULE_DEVICE_TABLE(of, sh_msiof_match);

drivers/thermal/rockchip_thermal.c+100−53

@@ -118,12 +118,12 @@ struct rockchip_tsadc_chip { · 117 unmodified lines
118	void (control)(void __iomem reg, bool on);	118	void (control)(void __iomem reg, bool on);
119		119
120	/* Per-sensor methods */	120	/* Per-sensor methods */
121	int (*get_temp)(struct chip_tsadc_table table,	121	int (get_temp)(const struct chip_tsadc_table table,
122	int chn, void __iomem reg, int temp);	122	int chn, void __iomem reg, int temp);
123	void (*set_alarm_temp)(struct chip_tsadc_table table,	123	int (set_alarm_temp)(const struct chip_tsadc_table table,
124	int chn, void __iomem *reg, int temp);	124	int chn, void __iomem *reg, int temp);
125	void (*set_tshut_temp)(struct chip_tsadc_table table,	125	int (set_tshut_temp)(const struct chip_tsadc_table table,
126	int chn, void __iomem *reg, int temp);	126	int chn, void __iomem *reg, int temp);
127	void (set_tshut_mode)(int chn, void __iomem reg, enum tshut_mode m);	127	void (set_tshut_mode)(int chn, void __iomem reg, enum tshut_mode m);
128		128
129	/* Per-table methods */	129	/* Per-table methods */
@@ -317,6 +317,7 @@ static const struct tsadc_table rk3288_code_table[] = { · 187 unmodified lines
317	{3452, 115000},	317	{3452, 115000},
318	{3437, 120000},	318	{3437, 120000},
319	{3421, 125000},	319	{3421, 125000},
		320	{0, 125000},
320	};	321	};
321		322
322	static const struct tsadc_table rk3368_code_table[] = {	323	static const struct tsadc_table rk3368_code_table[] = {
@@ -397,59 +398,80 @@ static const struct tsadc_table rk3399_code_table[] = { · 74 unmodified lines
397	{TSADCV3_DATA_MASK, 125000},	398	{TSADCV3_DATA_MASK, 125000},
398	};	399	};
399		400
400	static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table,	401	static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
401	int temp)	402	int temp)
402	{	403	{
403	int high, low, mid;	404	int high, low, mid;
404	u32 error = 0;	405	unsigned long num;
		406	unsigned int denom;
		407	u32 error = table->data_mask;
405		408
406	low = 0;	409	low = 0;
407	high = table.length - 1;	410	high = (table->length - 1) - 1; /* ignore the last check for table */
408	mid = (high + low) / 2;	411	mid = (high + low) / 2;
409		412
410	/* Return mask code data when the temp is over table range */	413	/* Return mask code data when the temp is over table range */
411	if (temp < table.id[low].temp \|\| temp > table.id[high].temp) {	414	if (temp < table->id[low].temp \|\| temp > table->id[high].temp)
412	error = table.data_mask;
413	goto exit;	415	goto exit;
414	}
415		416
416	while (low <= high) {	417	while (low <= high) {
417	if (temp == table.id[mid].temp)	418	if (temp == table->id[mid].temp)
418	return table.id[mid].code;	419	return table->id[mid].code;
419	else if (temp < table.id[mid].temp)	420	else if (temp < table->id[mid].temp)
420	high = mid - 1;	421	high = mid - 1;
421	else	422	else
422	low = mid + 1;	423	low = mid + 1;
423	mid = (low + high) / 2;	424	mid = (low + high) / 2;
424	}	425	}
425		426
		427	/*
		428	* The conversion code granularity provided by the table. Let's
		429	* assume that the relationship between temperature and
		430	* analog value between 2 table entries is linear and interpolate
		431	* to produce less granular result.
		432	*/
		433	num = abs(table->id[mid + 1].code - table->id[mid].code);
		434	num *= temp - table->id[mid].temp;
		435	denom = table->id[mid + 1].temp - table->id[mid].temp;
		436
		437	switch (table->mode) {
		438	case ADC_DECREMENT:
		439	return table->id[mid].code - (num / denom);
		440	case ADC_INCREMENT:
		441	return table->id[mid].code + (num / denom);
		442	default:
		443	pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
		444	return error;
		445	}
		446
426	exit:	447	exit:
427	pr_err("Invalid the conversion, error=%d\n", error);	448	pr_err("%s: invalid temperature, temp=%d error=%d\n",
		449	__func__, temp, error);
428	return error;	450	return error;
429	}	451	}
430		452
431	static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code,	453	static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
432	int *temp)	454	u32 code, int *temp)
433	{	455	{
434	unsigned int low = 1;	456	unsigned int low = 1;
435	unsigned int high = table.length - 1;	457	unsigned int high = table->length - 1;
436	unsigned int mid = (low + high) / 2;	458	unsigned int mid = (low + high) / 2;
437	unsigned int num;	459	unsigned int num;
438	unsigned long denom;	460	unsigned long denom;
439		461
440	WARN_ON(table.length < 2);	462	WARN_ON(table->length < 2);
441		463
442	switch (table.mode) {	464	switch (table->mode) {
443	case ADC_DECREMENT:	465	case ADC_DECREMENT:
444	code &= table.data_mask;	466	code &= table->data_mask;
445	if (code < table.id[high].code)	467	if (code <= table->id[high].code)
446	return -EAGAIN; /* Incorrect reading */	468	return -EAGAIN; /* Incorrect reading */
447		469
448	while (low <= high) {	470	while (low <= high) {
449	if (code >= table.id[mid].code &&	471	if (code >= table->id[mid].code &&
450	code < table.id[mid - 1].code)	472	code < table->id[mid - 1].code)
451	break;	473	break;
452	else if (code < table.id[mid].code)	474	else if (code < table->id[mid].code)
453	low = mid + 1;	475	low = mid + 1;
454	else	476	else
455	high = mid - 1;	477	high = mid - 1;
@@ -458,15 +480,15 @@ static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code, · 2 unmodified lines
458	}	480	}
459	break;	481	break;
460	case ADC_INCREMENT:	482	case ADC_INCREMENT:
461	code &= table.data_mask;	483	code &= table->data_mask;
462	if (code < table.id[low].code)	484	if (code < table->id[low].code)
463	return -EAGAIN; /* Incorrect reading */	485	return -EAGAIN; /* Incorrect reading */
464		486
465	while (low <= high) {	487	while (low <= high) {
466	if (code <= table.id[mid].code &&	488	if (code <= table->id[mid].code &&
467	code > table.id[mid - 1].code)	489	code > table->id[mid - 1].code)
468	break;	490	break;
469	else if (code > table.id[mid].code)	491	else if (code > table->id[mid].code)
470	low = mid + 1;	492	low = mid + 1;
471	else	493	else
472	high = mid - 1;	494	high = mid - 1;
@@ -475,7 +497,8 @@ static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code, · 2 unmodified lines
475	}	497	}
476	break;	498	break;
477	default:	499	default:
478	pr_err("Invalid the conversion table\n");	500	pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
		501	return -EINVAL;
479	}	502	}
480		503
481	/*	504	/*
@@ -484,10 +507,10 @@ static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code, · 2 unmodified lines
484	* temperature between 2 table entries is linear and interpolate	507	* temperature between 2 table entries is linear and interpolate
485	* to produce less granular result.	508	* to produce less granular result.
486	*/	509	*/
487	num = table.id[mid].temp - table.id[mid - 1].temp;	510	num = table->id[mid].temp - table->id[mid - 1].temp;
488	num *= abs(table.id[mid - 1].code - code);	511	num *= abs(table->id[mid - 1].code - code);
489	denom = abs(table.id[mid - 1].code - table.id[mid].code);	512	denom = abs(table->id[mid - 1].code - table->id[mid].code);
490	*temp = table.id[mid - 1].temp + (num / denom);	513	*temp = table->id[mid - 1].temp + (num / denom);
491		514
492	return 0;	515	return 0;
493	}	516	}
@@ -638,7 +661,7 @@ static void rk_tsadcv3_control(void __iomem *regs, bool enable) · 144 unmodified lines
638	writel_relaxed(val, regs + TSADCV2_AUTO_CON);	661	writel_relaxed(val, regs + TSADCV2_AUTO_CON);
639	}	662	}
640		663
641	static int rk_tsadcv2_get_temp(struct chip_tsadc_table table,	664	static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
642	int chn, void __iomem regs, int temp)	665	int chn, void __iomem regs, int temp)
643	{	666	{
644	u32 val;	667	u32 val;
@@ -648,39 +671,57 @@ static int rk_tsadcv2_get_temp(struct chip_tsadc_table table, · 3 unmodified lines
648	return rk_tsadcv2_code_to_temp(table, val, temp);	671	return rk_tsadcv2_code_to_temp(table, val, temp);
649	}	672	}
650		673
651	static void rk_tsadcv2_alarm_temp(struct chip_tsadc_table table,	674	static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
652	int chn, void __iomem *regs, int temp)	675	int chn, void __iomem *regs, int temp)
653	{	676	{
654	u32 alarm_value, int_en;	677	u32 alarm_value;
		678	u32 int_en, int_clr;
		679
		680	/*
		681	* In some cases, some sensors didn't need the trip points, the
		682	* set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
		683	* in the end, ignore this case and disable the high temperature
		684	* interrupt.
		685	*/
		686	if (temp == INT_MAX) {
		687	int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
		688	int_clr &= ~TSADCV2_INT_SRC_EN(chn);
		689	writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
		690	return 0;
		691	}
655		692
656	/* Make sure the value is valid */	693	/* Make sure the value is valid */
657	alarm_value = rk_tsadcv2_temp_to_code(table, temp);	694	alarm_value = rk_tsadcv2_temp_to_code(table, temp);
658	if (alarm_value == table.data_mask)	695	if (alarm_value == table->data_mask)
659	return;	696	return -ERANGE;
660		697
661	writel_relaxed(alarm_value & table.data_mask,	698	writel_relaxed(alarm_value & table->data_mask,
662	regs + TSADCV2_COMP_INT(chn));	699	regs + TSADCV2_COMP_INT(chn));
663		700
664	int_en = readl_relaxed(regs + TSADCV2_INT_EN);	701	int_en = readl_relaxed(regs + TSADCV2_INT_EN);
665	int_en \|= TSADCV2_INT_SRC_EN(chn);	702	int_en \|= TSADCV2_INT_SRC_EN(chn);
666	writel_relaxed(int_en, regs + TSADCV2_INT_EN);	703	writel_relaxed(int_en, regs + TSADCV2_INT_EN);
		704
		705	return 0;
667	}	706	}
668		707
669	static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table,	708	static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
670	int chn, void __iomem *regs, int temp)	709	int chn, void __iomem *regs, int temp)
671	{	710	{
672	u32 tshut_value, val;	711	u32 tshut_value, val;
673		712
674	/* Make sure the value is valid */	713	/* Make sure the value is valid */
675	tshut_value = rk_tsadcv2_temp_to_code(table, temp);	714	tshut_value = rk_tsadcv2_temp_to_code(table, temp);
676	if (tshut_value == table.data_mask)	715	if (tshut_value == table->data_mask)
677	return;	716	return -ERANGE;
678		717
679	writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));	718	writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
680		719
681	/* TSHUT will be valid */	720	/* TSHUT will be valid */
682	val = readl_relaxed(regs + TSADCV2_AUTO_CON);	721	val = readl_relaxed(regs + TSADCV2_AUTO_CON);
683	writel_relaxed(val \| TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);	722	writel_relaxed(val \| TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
		723
		724	return 0;
684	}	725	}
685		726
686	static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,	727	static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
@@ -883,10 +924,8 @@ static int rockchip_thermal_set_trips(void *_sensor, int low, int high) · 196 unmodified lines
883	dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",	924	dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
884	__func__, sensor->id, low, high);	925	__func__, sensor->id, low, high);
885		926
886	tsadc->set_alarm_temp(tsadc->table,	927	return tsadc->set_alarm_temp(&tsadc->table,
887	sensor->id, thermal->regs, high);	928	sensor->id, thermal->regs, high);
888
889	return 0;
890	}	929	}
891		930
892	static int rockchip_thermal_get_temp(void _sensor, int out_temp)	931	static int rockchip_thermal_get_temp(void _sensor, int out_temp)
@@ -896,7 +935,7 @@ static int rockchip_thermal_get_temp(void _sensor, int out_temp) · 3 unmodified lines
896	const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;	935	const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
897	int retval;	936	int retval;
898		937
899	retval = tsadc->get_temp(tsadc->table,	938	retval = tsadc->get_temp(&tsadc->table,
900	sensor->id, thermal->regs, out_temp);	939	sensor->id, thermal->regs, out_temp);
901	dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",	940	dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
902	sensor->id, *out_temp, retval);	941	sensor->id, *out_temp, retval);
@@ -982,8 +1021,12 @@ rockchip_thermal_register_sensor(struct platform_device *pdev, · 79 unmodified lines
982	int error;	1021	int error;
983		1022
984	tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);	1023	tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
985	tsadc->set_tshut_temp(tsadc->table, id, thermal->regs,	1024
		1025	error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
986	thermal->tshut_temp);	1026	thermal->tshut_temp);
		1027	if (error)
		1028	dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
		1029	__func__, thermal->tshut_temp, error);
987		1030
988	sensor->thermal = thermal;	1031	sensor->thermal = thermal;
989	sensor->id = id;	1032	sensor->id = id;
@@ -1196,9 +1239,13 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev) · 206 unmodified lines
1196		1239
1197	thermal->chip->set_tshut_mode(id, thermal->regs,	1240	thermal->chip->set_tshut_mode(id, thermal->regs,
1198	thermal->tshut_mode);	1241	thermal->tshut_mode);
1199	thermal->chip->set_tshut_temp(thermal->chip->table,	1242
		1243	error = thermal->chip->set_tshut_temp(&thermal->chip->table,
1200	id, thermal->regs,	1244	id, thermal->regs,
1201	thermal->tshut_temp);	1245	thermal->tshut_temp);
		1246	if (error)
		1247	dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
		1248	__func__, thermal->tshut_temp, error);
1202	}	1249	}
1203		1250
1204	thermal->chip->control(thermal->regs, true);	1251	thermal->chip->control(thermal->regs, true);

drivers/thermal/thermal_core.c+5−5

 	if (!strncmp(dev_name(dev), "thermal_zone",
 		     sizeof("thermal_zone") - 1)) {
 		tz = to_thermal_zone(dev);
+		kfree(tz->trip_type_attrs);
+		kfree(tz->trip_temp_attrs);
+		kfree(tz->trip_hyst_attrs);
+		kfree(tz->trips_attribute_group.attrs);
+		kfree(tz->device.groups);
 		kfree(tz);
 	} else if (!strncmp(dev_name(dev), "cooling_device",
 			    sizeof("cooling_device") - 1)) {
 	thermal_zone_device_set_polling(tz, 0);
-	kfree(tz->trip_type_attrs);
-	kfree(tz->trip_temp_attrs);
-	kfree(tz->trip_hyst_attrs);
-	kfree(tz->trips_attribute_group.attrs);
 	thermal_set_governor(tz, NULL);
 	thermal_remove_hwmon_sysfs(tz);
 	idr_destroy(&tz->idr);
 	mutex_destroy(&tz->lock);
 	device_unregister(&tz->device);
-	kfree(tz->device.groups);
 }
 EXPORT_SYMBOL_GPL(thermal_zone_device_unregister);

drivers/thermal/thermal_hwmon.c+3−17

 static DEFINE_MUTEX(thermal_hwmon_list_lock);
-static ssize_t
-name_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
-	struct thermal_hwmon_device *hwmon = dev_get_drvdata(dev);
-	return sprintf(buf, "%s\n", hwmon->type);
-}
-static DEVICE_ATTR_RO(name);
 static ssize_t
 temp_input_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
 	INIT_LIST_HEAD(&hwmon->tz_list);
 	strlcpy(hwmon->type, tz->type, THERMAL_NAME_LENGTH);
-	hwmon->device = hwmon_device_register(NULL);
+	hwmon->device = hwmon_device_register_with_info(NULL, hwmon->type,
+							hwmon, NULL, NULL);
 	if (IS_ERR(hwmon->device)) {
 		result = PTR_ERR(hwmon->device);
 		goto free_mem;
 	}
-	dev_set_drvdata(hwmon->device, hwmon);
-	result = device_create_file(hwmon->device, &dev_attr_name);
-	if (result)
-		goto free_mem;
  register_sys_interface:
 	temp = kzalloc(sizeof(*temp), GFP_KERNEL);
  free_temp_mem:
 	kfree(temp);
  unregister_name:
-	if (new_hwmon_device) {
+	if (new_hwmon_device)
-		device_remove_file(hwmon->device, &dev_attr_name);
 		hwmon_device_unregister(hwmon->device);
-	}
  free_mem:
 	if (new_hwmon_device)
 		kfree(hwmon);
 	list_del(&hwmon->node);
 	mutex_unlock(&thermal_hwmon_list_lock);
-	device_remove_file(hwmon->device, &dev_attr_name);
 	hwmon_device_unregister(hwmon->device);
 	kfree(hwmon);
 }

drivers/usb/dwc2/core.h+2−2

@@ -513,8 +513,8 @@ struct dwc2_core_params { · 512 unmodified lines
513	/* Gadget parameters */	513	/* Gadget parameters */
514	bool g_dma;	514	bool g_dma;
515	bool g_dma_desc;	515	bool g_dma_desc;
516	u16 g_rx_fifo_size;	516	u32 g_rx_fifo_size;
517	u16 g_np_tx_fifo_size;	517	u32 g_np_tx_fifo_size;
518	u32 g_tx_fifo_size[MAX_EPS_CHANNELS];	518	u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
519	};	519	};
520		520

drivers/usb/dwc2/gadget.c+5−13

 	/* keep other bits untouched (so e.g. forced modes are not lost) */
 	usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 	usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
-		GUSBCFG_HNPCAP);
+		GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
 	if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
 	    (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
 		__func__, epctrl, epctrl_reg);
 	/* Allocate DMA descriptor chain for non-ctrl endpoints */
-	if (using_desc_dma(hsotg)) {
+	if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
-		hs_ep->desc_list = dma_alloc_coherent(hsotg->dev,
+		hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
 			MAX_DMA_DESC_NUM_GENERIC *
 			sizeof(struct dwc2_dma_desc),
 			&hs_ep->desc_list_dma, GFP_ATOMIC);
 error2:
 	if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
-		dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
+		dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
 			sizeof(struct dwc2_dma_desc),
 			hs_ep->desc_list, hs_ep->desc_list_dma);
 		hs_ep->desc_list = NULL;
 		return -EINVAL;
 	}
-	/* Remove DMA memory allocated for non-control Endpoints */
-	if (using_desc_dma(hsotg)) {
-		dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
-				  sizeof(struct dwc2_dma_desc),
-				  hs_ep->desc_list, hs_ep->desc_list_dma);
-		hs_ep->desc_list = NULL;
-	}
 	epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
 	spin_lock_irqsave(&hsotg->lock, flags);
 	/* keep other bits untouched (so e.g. forced modes are not lost) */
 	usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 	usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
-		GUSBCFG_HNPCAP);
+		GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
 	/* set the PLL on, remove the HNP/SRP and set the PHY */
 	trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;

drivers/usb/dwc2/hcd.c+5−2

 	if (!HCD_HW_ACCESSIBLE(hcd))
 		goto unlock;
+	if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
+		goto unlock;
 	if (!hsotg->params.hibernation)
 		goto skip_power_saving;
 {
 #ifdef VERBOSE_DEBUG
 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
-	char *pipetype;
+	char *pipetype = NULL;
-	char *speed;
+	char *speed = NULL;
 	dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
 	dev_vdbg(hsotg->dev, "  Device address: %d\n",

drivers/usb/dwc2/params.c+5−5

@@ -385,16 +385,16 @@ static void dwc2_set_param(struct dwc2_hsotg hsotg, void param, · 384 unmodified lines
385	}	385	}
386		386
387	/**	387	/**
388	* dwc2_set_param_u16() - Set a u16 parameter	388	* dwc2_set_param_u32() - Set a u32 parameter
389	*	389	*
390	* See dwc2_set_param().	390	* See dwc2_set_param().
391	*/	391	*/
392	static void dwc2_set_param_u16(struct dwc2_hsotg hsotg, u16 param,	392	static void dwc2_set_param_u32(struct dwc2_hsotg hsotg, u32 param,
393	bool lookup, char *property, u16 legacy,	393	bool lookup, char *property, u16 legacy,
394	u16 def, u16 min, u16 max)	394	u16 def, u16 min, u16 max)
395	{	395	{
396	dwc2_set_param(hsotg, param, lookup, property,	396	dwc2_set_param(hsotg, param, lookup, property,
397	legacy, def, min, max, 2);	397	legacy, def, min, max, 4);
398	}	398	}
399		399
400	/**	400	/**
@@ -1178,12 +1178,12 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg, · 777 unmodified lines
1178	* auto-detect if the hardware does not support the	1178	* auto-detect if the hardware does not support the
1179	* default.	1179	* default.
1180	*/	1180	*/
1181	dwc2_set_param_u16(hsotg, &p->g_rx_fifo_size,	1181	dwc2_set_param_u32(hsotg, &p->g_rx_fifo_size,
1182	true, "g-rx-fifo-size", 2048,	1182	true, "g-rx-fifo-size", 2048,
1183	hw->rx_fifo_size,	1183	hw->rx_fifo_size,
1184	16, hw->rx_fifo_size);	1184	16, hw->rx_fifo_size);
1185		1185
1186	dwc2_set_param_u16(hsotg, &p->g_np_tx_fifo_size,	1186	dwc2_set_param_u32(hsotg, &p->g_np_tx_fifo_size,
1187	true, "g-np-tx-fifo-size", 1024,	1187	true, "g-np-tx-fifo-size", 1024,
1188	hw->dev_nperio_tx_fifo_size,	1188	hw->dev_nperio_tx_fifo_size,
1189	16, hw->dev_nperio_tx_fifo_size);	1189	16, hw->dev_nperio_tx_fifo_size);

drivers/usb/dwc3/dwc3-exynos.c+3−1

 		exynos->axius_clk = devm_clk_get(dev, "usbdrd30_axius_clk");
 		if (IS_ERR(exynos->axius_clk)) {
 			dev_err(dev, "no AXI UpScaler clk specified\n");
-			return -ENODEV;
+			ret = -ENODEV;
+			goto axius_clk_err;
 		}
 		clk_prepare_enable(exynos->axius_clk);
 	} else {
 	regulator_disable(exynos->vdd33);
 err2:
 	clk_disable_unprepare(exynos->axius_clk);
+axius_clk_err:
 	clk_disable_unprepare(exynos->susp_clk);
 	clk_disable_unprepare(exynos->clk);
 	return ret;

drivers/usb/gadget/composite.c+1−1

@@ -2147,7 +2147,7 @@ int composite_os_desc_req_prepare(struct usb_composite_dev *cdev, · 2146 unmodified lines
2147	cdev->os_desc_req->buf = kmalloc(4096, GFP_KERNEL);	2147	cdev->os_desc_req->buf = kmalloc(4096, GFP_KERNEL);
2148	if (!cdev->os_desc_req->buf) {	2148	if (!cdev->os_desc_req->buf) {
2149	ret = -ENOMEM;	2149	ret = -ENOMEM;
2150	kfree(cdev->os_desc_req);	2150	usb_ep_free_request(ep0, cdev->os_desc_req);
2151	goto end;	2151	goto end;
2152	}	2152	}
2153	cdev->os_desc_req->context = cdev;	2153	cdev->os_desc_req->context = cdev;

drivers/usb/gadget/function/f_fs.c+6−6

@@ -1806,7 +1806,7 @@ static void ffs_func_eps_disable(struct ffs_function *func) · 1805 unmodified lines
1806	unsigned long flags;	1806	unsigned long flags;
1807		1807
1808	spin_lock_irqsave(&func->ffs->eps_lock, flags);	1808	spin_lock_irqsave(&func->ffs->eps_lock, flags);
1809	do {	1809	while (count--) {
1810	/* pending requests get nuked */	1810	/* pending requests get nuked */
1811	if (likely(ep->ep))	1811	if (likely(ep->ep))
1812	usb_ep_disable(ep->ep);	1812	usb_ep_disable(ep->ep);
@@ -1817,7 +1817,7 @@ static void ffs_func_eps_disable(struct ffs_function *func) · 4 unmodified lines
1817	__ffs_epfile_read_buffer_free(epfile);	1817	__ffs_epfile_read_buffer_free(epfile);
1818	++epfile;	1818	++epfile;
1819	}	1819	}
1820	} while (--count);	1820	}
1821	spin_unlock_irqrestore(&func->ffs->eps_lock, flags);	1821	spin_unlock_irqrestore(&func->ffs->eps_lock, flags);
1822	}	1822	}
1823		1823
@@ -1831,7 +1831,7 @@ static int ffs_func_eps_enable(struct ffs_function *func) · 7 unmodified lines
1831	int ret = 0;	1831	int ret = 0;
1832		1832
1833	spin_lock_irqsave(&func->ffs->eps_lock, flags);	1833	spin_lock_irqsave(&func->ffs->eps_lock, flags);
1834	do {	1834	while(count--) {
1835	struct usb_endpoint_descriptor *ds;	1835	struct usb_endpoint_descriptor *ds;
1836	int desc_idx;	1836	int desc_idx;
1837		1837
@@ -1867,7 +1867,7 @@ static int ffs_func_eps_enable(struct ffs_function *func) · 29 unmodified lines
1867		1867
1868	++ep;	1868	++ep;
1869	++epfile;	1869	++epfile;
1870	} while (--count);	1870	}
1871	spin_unlock_irqrestore(&func->ffs->eps_lock, flags);	1871	spin_unlock_irqrestore(&func->ffs->eps_lock, flags);
1872		1872
1873	return ret;	1873	return ret;
@@ -3448,12 +3448,12 @@ static void ffs_func_unbind(struct usb_configuration *c, · 1574 unmodified lines
3448		3448
3449	/* cleanup after autoconfig */	3449	/* cleanup after autoconfig */
3450	spin_lock_irqsave(&func->ffs->eps_lock, flags);	3450	spin_lock_irqsave(&func->ffs->eps_lock, flags);
3451	do {	3451	while (count--) {
3452	if (ep->ep && ep->req)	3452	if (ep->ep && ep->req)
3453	usb_ep_free_request(ep->ep, ep->req);	3453	usb_ep_free_request(ep->ep, ep->req);
3454	ep->req = NULL;	3454	ep->req = NULL;
3455	++ep;	3455	++ep;
3456	} while (--count);	3456	}
3457	spin_unlock_irqrestore(&func->ffs->eps_lock, flags);	3457	spin_unlock_irqrestore(&func->ffs->eps_lock, flags);
3458	kfree(func->eps);	3458	kfree(func->eps);
3459	func->eps = NULL;	3459	func->eps = NULL;

drivers/usb/gadget/udc/atmel_usba_udc.c+2−1

@@ -1978,7 +1978,8 @@ static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev, · 1977 unmodified lines
1978	dev_err(&pdev->dev, "of_probe: name error(%d)\n", ret);	1978	dev_err(&pdev->dev, "of_probe: name error(%d)\n", ret);
1979	goto err;	1979	goto err;
1980	}	1980	}
1981	ep->ep.name = kasprintf(GFP_KERNEL, "ep%d", ep->index);	1981	sprintf(ep->name, "ep%d", ep->index);
		1982	ep->ep.name = ep->name;
1982		1983
1983	ep->ep_regs = udc->regs + USBA_EPT_BASE(i);	1984	ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
1984	ep->dma_regs = udc->regs + USBA_DMA_BASE(i);	1985	ep->dma_regs = udc->regs + USBA_DMA_BASE(i);

drivers/usb/gadget/udc/atmel_usba_udc.h+1−0

@@ -280,6 +280,7 @@ struct usba_ep { · 279 unmodified lines
280	void __iomem *ep_regs;	280	void __iomem *ep_regs;
281	void __iomem *dma_regs;	281	void __iomem *dma_regs;
282	void __iomem *fifo;	282	void __iomem *fifo;
		283	char name[8];
283	struct usb_ep ep;	284	struct usb_ep ep;
284	struct usba_udc *udc;	285	struct usba_udc *udc;
285		286

drivers/usb/host/xhci-plat.c+1−1

@@ -165,7 +165,7 @@ static int xhci_plat_probe(struct platform_device *pdev) · 164 unmodified lines
165	return -ENODEV;	165	return -ENODEV;
166		166
167	/* Try to set 64-bit DMA first */	167	/* Try to set 64-bit DMA first */
168	if (WARN_ON(!pdev->dev.dma_mask))	168	if (!pdev->dev.dma_mask)
169	/* Platform did not initialize dma_mask */	169	/* Platform did not initialize dma_mask */
170	ret = dma_coerce_mask_and_coherent(&pdev->dev,	170	ret = dma_coerce_mask_and_coherent(&pdev->dev,
171	DMA_BIT_MASK(64));	171	DMA_BIT_MASK(64));

drivers/vhost/scsi.c+2−2

@@ -843,7 +843,7 @@ vhost_scsi_handle_vq(struct vhost_scsi vs, struct vhost_virtqueue vq) · 842 unmodified lines
843	struct iov_iter out_iter, in_iter, prot_iter, data_iter;	843	struct iov_iter out_iter, in_iter, prot_iter, data_iter;
844	u64 tag;	844	u64 tag;
845	u32 exp_data_len, data_direction;	845	u32 exp_data_len, data_direction;
846	unsigned out, in;	846	unsigned int out = 0, in = 0;
847	int head, ret, prot_bytes;	847	int head, ret, prot_bytes;
848	size_t req_size, rsp_size = sizeof(struct virtio_scsi_cmd_resp);	848	size_t req_size, rsp_size = sizeof(struct virtio_scsi_cmd_resp);
849	size_t out_size, in_size;	849	size_t out_size, in_size;
@@ -2087,7 +2087,7 @@ static struct configfs_attribute *vhost_scsi_wwn_attrs[] = { · 1237 unmodified lines
2087	NULL,	2087	NULL,
2088	};	2088	};
2089		2089
2090	static struct target_core_fabric_ops vhost_scsi_ops = {	2090	static const struct target_core_fabric_ops vhost_scsi_ops = {
2091	.module = THIS_MODULE,	2091	.module = THIS_MODULE,
2092	.name = "vhost",	2092	.name = "vhost",
2093	.get_fabric_name = vhost_scsi_get_fabric_name,	2093	.get_fabric_name = vhost_scsi_get_fabric_name,

drivers/xen/platform-pci.c+71−0

@@ -42,6 +42,7 @@ · 41 unmodified lines
42	static unsigned long platform_mmio;	42	static unsigned long platform_mmio;
43	static unsigned long platform_mmio_alloc;	43	static unsigned long platform_mmio_alloc;
44	static unsigned long platform_mmiolen;	44	static unsigned long platform_mmiolen;
		45	static uint64_t callback_via;
45		46
46	static unsigned long alloc_xen_mmio(unsigned long len)	47	static unsigned long alloc_xen_mmio(unsigned long len)
47	{	48	{
@@ -54,6 +55,51 @@ static unsigned long alloc_xen_mmio(unsigned long len) · 6 unmodified lines
54	return addr;	55	return addr;
55	}	56	}
56		57
		58	static uint64_t get_callback_via(struct pci_dev *pdev)
		59	{
		60	u8 pin;
		61	int irq;
		62
		63	irq = pdev->irq;
		64	if (irq < 16)
		65	return irq; /* ISA IRQ */
		66
		67	pin = pdev->pin;
		68
		69	/* We don't know the GSI. Specify the PCI INTx line instead. */
		70	return ((uint64_t)0x01 << HVM_CALLBACK_VIA_TYPE_SHIFT) \| /* PCI INTx identifier */
		71	((uint64_t)pci_domain_nr(pdev->bus) << 32) \|
		72	((uint64_t)pdev->bus->number << 16) \|
		73	((uint64_t)(pdev->devfn & 0xff) << 8) \|
		74	((uint64_t)(pin - 1) & 3);
		75	}
		76
		77	static irqreturn_t do_hvm_evtchn_intr(int irq, void *dev_id)
		78	{
		79	xen_hvm_evtchn_do_upcall();
		80	return IRQ_HANDLED;
		81	}
		82
		83	static int xen_allocate_irq(struct pci_dev *pdev)
		84	{
		85	return request_irq(pdev->irq, do_hvm_evtchn_intr,
		86	IRQF_NOBALANCING \| IRQF_TRIGGER_RISING,
		87	"xen-platform-pci", pdev);
		88	}
		89
		90	static int platform_pci_resume(struct pci_dev *pdev)
		91	{
		92	int err;
		93	if (!xen_pv_domain())
		94	return 0;
		95	err = xen_set_callback_via(callback_via);
		96	if (err) {
		97	dev_err(&pdev->dev, "platform_pci_resume failure!\n");
		98	return err;
		99	}
		100	return 0;
		101	}
		102
57	static int platform_pci_probe(struct pci_dev *pdev,	103	static int platform_pci_probe(struct pci_dev *pdev,
58	const struct pci_device_id *ent)	104	const struct pci_device_id *ent)
59	{	105	{
@@ -92,6 +138,28 @@ static int platform_pci_probe(struct pci_dev *pdev, · 32 unmodified lines
92	platform_mmio = mmio_addr;	138	platform_mmio = mmio_addr;
93	platform_mmiolen = mmio_len;	139	platform_mmiolen = mmio_len;
94		140
		141	/*
		142	* Xen HVM guests always use the vector callback mechanism.
		143	* L1 Dom0 in a nested Xen environment is a PV guest inside in an
		144	* HVM environment. It needs the platform-pci driver to get
		145	* notifications from L0 Xen, but it cannot use the vector callback
		146	* as it is not exported by L1 Xen.
		147	*/
		148	if (xen_pv_domain()) {
		149	ret = xen_allocate_irq(pdev);
		150	if (ret) {
		151	dev_warn(&pdev->dev, "request_irq failed err=%d\n", ret);
		152	goto out;
		153	}
		154	callback_via = get_callback_via(pdev);
		155	ret = xen_set_callback_via(callback_via);
		156	if (ret) {
		157	dev_warn(&pdev->dev, "Unable to set the evtchn callback "
		158	"err=%d\n", ret);
		159	goto out;
		160	}
		161	}
		162
95	max_nr_gframes = gnttab_max_grant_frames();	163	max_nr_gframes = gnttab_max_grant_frames();
96	grant_frames = alloc_xen_mmio(PAGE_SIZE * max_nr_gframes);	164	grant_frames = alloc_xen_mmio(PAGE_SIZE * max_nr_gframes);
97	ret = gnttab_setup_auto_xlat_frames(grant_frames);	165	ret = gnttab_setup_auto_xlat_frames(grant_frames);
@@ -123,6 +191,9 @@ static struct pci_driver platform_driver = { · 25 unmodified lines
123	.name = DRV_NAME,	191	.name = DRV_NAME,
124	.probe = platform_pci_probe,	192	.probe = platform_pci_probe,
125	.id_table = platform_pci_tbl,	193	.id_table = platform_pci_tbl,
		194	#ifdef CONFIG_PM
		195	.resume_early = platform_pci_resume,
		196	#endif
126	};	197	};
127		198
128	builtin_pci_driver(platform_driver);	199	builtin_pci_driver(platform_driver);

fs/ceph/caps.c+6−1

 			add_wait_queue(&ci->i_cap_wq, &wait);
 			while (!try_get_cap_refs(ci, need, want, endoff,
-						 true, &_got, &err))
+						 true, &_got, &err)) {
+				if (signal_pending(current)) {
+					ret = -ERESTARTSYS;
+					break;
+				}
 				wait_woken(&wait, TASK_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT);
+			}
 			remove_wait_queue(&ci->i_cap_wq, &wait);

fs/ceph/dir.c+3−2

 		struct ceph_mds_client *mdsc =
 			ceph_sb_to_client(dir->i_sb)->mdsc;
 		struct ceph_mds_request *req;
-		int op, mask, err;
+		int op, err;
+		u32 mask;
 		if (flags & LOOKUP_RCU)
 			return -ECHILD;
 			mask = CEPH_STAT_CAP_INODE | CEPH_CAP_AUTH_SHARED;
 			if (ceph_security_xattr_wanted(dir))
 				mask |= CEPH_CAP_XATTR_SHARED;
-			req->r_args.getattr.mask = mask;
+			req->r_args.getattr.mask = cpu_to_le32(mask);
 			err = ceph_mdsc_do_request(mdsc, NULL, req);
 			switch (err) {

fs/ceph/inode.c+2−1

@@ -305,7 +305,8 @@ static int frag_tree_split_cmp(const void l, const void r) · 304 unmodified lines
305	{	305	{
306	struct ceph_frag_tree_split ls = (struct ceph_frag_tree_split)l;	306	struct ceph_frag_tree_split ls = (struct ceph_frag_tree_split)l;
307	struct ceph_frag_tree_split rs = (struct ceph_frag_tree_split)r;	307	struct ceph_frag_tree_split rs = (struct ceph_frag_tree_split)r;
308	return ceph_frag_compare(ls->frag, rs->frag);	308	return ceph_frag_compare(le32_to_cpu(ls->frag),
		309	le32_to_cpu(rs->frag));
309	}	310	}
310		311
311	static bool is_frag_child(u32 f, struct ceph_inode_frag *frag)	312	static bool is_frag_child(u32 f, struct ceph_inode_frag *frag)

fs/ceph/mds_client.c+5−4

 				  struct ceph_mds_reply_info_parsed *info,
 				  u64 features)
 {
-	if (info->head->op == CEPH_MDS_OP_GETFILELOCK)
+	u32 op = le32_to_cpu(info->head->op);
+	if (op == CEPH_MDS_OP_GETFILELOCK)
 		return parse_reply_info_filelock(p, end, info, features);
-	else if (info->head->op == CEPH_MDS_OP_READDIR ||
+	else if (op == CEPH_MDS_OP_READDIR || op == CEPH_MDS_OP_LSSNAP)
-		 info->head->op == CEPH_MDS_OP_LSSNAP)
 		return parse_reply_info_dir(p, end, info, features);
-	else if (info->head->op == CEPH_MDS_OP_CREATE)
+	else if (op == CEPH_MDS_OP_CREATE)
 		return parse_reply_info_create(p, end, info, features);
 	else
 		return -EIO;

fs/fuse/dev.c+2−1

 		struct fuse_req *req;
 		req = list_entry(head->next, struct fuse_req, list);
 		req->out.h.error = -ECONNABORTED;
-		clear_bit(FR_PENDING, &req->flags);
 		clear_bit(FR_SENT, &req->flags);
 		list_del_init(&req->list);
 		request_end(fc, req);
 		spin_lock(&fiq->waitq.lock);
 		fiq->connected = 0;
 		list_splice_init(&fiq->pending, &to_end2);
+		list_for_each_entry(req, &to_end2, list)
+			clear_bit(FR_PENDING, &req->flags);
 		while (forget_pending(fiq))
 			kfree(dequeue_forget(fiq, 1, NULL));
 		wake_up_all_locked(&fiq->waitq);

fs/fuse/dir.c+1−1

@@ -68,7 +68,7 @@ static u64 time_to_jiffies(u64 sec, u32 nsec) · 67 unmodified lines
68	if (sec \|\| nsec) {	68	if (sec \|\| nsec) {
69	struct timespec64 ts = {	69	struct timespec64 ts = {
70	sec,	70	sec,
71	max_t(u32, nsec, NSEC_PER_SEC - 1)	71	min_t(u32, nsec, NSEC_PER_SEC - 1)
72	};	72	};
73		73
74	return get_jiffies_64() + timespec64_to_jiffies(&ts);	74	return get_jiffies_64() + timespec64_to_jiffies(&ts);

fs/nfs/nfs4proc.c+18−11

 #include <linux/mm.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
-#include <linux/file.h>
 #include <linux/string.h>
 #include <linux/ratelimit.h>
 #include <linux/printk.h>
 	return nfs4_call_sync_sequence(clnt, server, msg, args, res);
 }
-static void update_changeattr(struct inode *dir, struct nfs4_change_info *cinfo)
+static void update_changeattr(struct inode *dir, struct nfs4_change_info *cinfo,
+		unsigned long timestamp)
 {
 	struct nfs_inode *nfsi = NFS_I(dir);
 				NFS_INO_INVALID_ACL;
 	}
 	dir->i_version = cinfo->after;
+	nfsi->read_cache_jiffies = timestamp;
 	nfsi->attr_gencount = nfs_inc_attr_generation_counter();
 	nfs_fscache_invalidate(dir);
 	spin_unlock(&dir->i_lock);
 	nfs_fattr_map_and_free_names(server, &data->f_attr);
 	if (o_arg->open_flags & O_CREAT) {
-		update_changeattr(dir, &o_res->cinfo);
 		if (o_arg->open_flags & O_EXCL)
 			data->file_created = 1;
 		else if (o_res->cinfo.before != o_res->cinfo.after)
 			data->file_created = 1;
+		if (data->file_created || dir->i_version != o_res->cinfo.after)
+			update_changeattr(dir, &o_res->cinfo,
+					o_res->f_attr->time_start);
 	}
 	if ((o_res->rflags & NFS4_OPEN_RESULT_LOCKTYPE_POSIX) == 0)
 		server->caps &= ~NFS_CAP_POSIX_LOCK;
 		.rpc_argp = &args,
 		.rpc_resp = &res,
 	};
+	unsigned long timestamp = jiffies;
 	int status;
 	status = nfs4_call_sync(server->client, server, &msg, &args.seq_args, &res.seq_res, 1);
 	if (status == 0)
-		update_changeattr(dir, &res.cinfo);
+		update_changeattr(dir, &res.cinfo, timestamp);
 	return status;
 }
 	if (nfs4_async_handle_error(task, res->server, NULL,
 				    &data->timeout) == -EAGAIN)
 		return 0;
-	update_changeattr(dir, &res->cinfo);
+	if (task->tk_status == 0)
+		update_changeattr(dir, &res->cinfo, res->dir_attr->time_start);
 	return 1;
 }
 	if (nfs4_async_handle_error(task, res->server, NULL, &data->timeout) == -EAGAIN)
 		return 0;
-	update_changeattr(old_dir, &res->old_cinfo);
+	if (task->tk_status == 0) {
-	update_changeattr(new_dir, &res->new_cinfo);
+		update_changeattr(old_dir, &res->old_cinfo, res->old_fattr->time_start);
+		if (new_dir != old_dir)
+			update_changeattr(new_dir, &res->new_cinfo, res->new_fattr->time_start);
+	}
 	return 1;
 }
 	status = nfs4_call_sync(server->client, server, &msg, &arg.seq_args, &res.seq_res, 1);
 	if (!status) {
-		update_changeattr(dir, &res.cinfo);
+		update_changeattr(dir, &res.cinfo, res.fattr->time_start);
 		status = nfs_post_op_update_inode(inode, res.fattr);
 		if (!status)
 			nfs_setsecurity(inode, res.fattr, res.label);
 	int status = nfs4_call_sync(NFS_SERVER(dir)->client, NFS_SERVER(dir), &data->msg,
 				    &data->arg.seq_args, &data->res.seq_res, 1);
 	if (status == 0) {
-		update_changeattr(dir, &data->res.dir_cinfo);
+		update_changeattr(dir, &data->res.dir_cinfo,
+				data->res.fattr->time_start);
 		status = nfs_instantiate(dentry, data->res.fh, data->res.fattr, data->res.label);
 	}
 	return status;
 	p->server = server;
 	atomic_inc(&lsp->ls_count);
 	p->ctx = get_nfs_open_context(ctx);
-	get_file(fl->fl_file);
 	memcpy(&p->fl, fl, sizeof(p->fl));
 	return p;
 out_free_seqid:
 		nfs_free_seqid(data->arg.lock_seqid);
 	nfs4_put_lock_state(data->lsp);
 	put_nfs_open_context(data->ctx);
-	fput(data->fl.fl_file);
 	kfree(data);
 	dprintk("%s: done!\n", __func__);
 }

fs/nfs/nfs4state.c+0−1

@@ -1729,7 +1729,6 @@ static int nfs4_recovery_handle_error(struct nfs_client *clp, int error) · 1728 unmodified lines
1729	break;	1729	break;
1730	case -NFS4ERR_STALE_CLIENTID:	1730	case -NFS4ERR_STALE_CLIENTID:
1731	set_bit(NFS4CLNT_LEASE_EXPIRED, &clp->cl_state);	1731	set_bit(NFS4CLNT_LEASE_EXPIRED, &clp->cl_state);
1732	nfs4_state_clear_reclaim_reboot(clp);
1733	nfs4_state_start_reclaim_reboot(clp);	1732	nfs4_state_start_reclaim_reboot(clp);
1734	break;	1733	break;
1735	case -NFS4ERR_EXPIRED:	1734	case -NFS4ERR_EXPIRED:

fs/nfsd/nfs4xdr.c+3−1

@@ -2440,7 +2440,9 @@ nfsd4_encode_fattr(struct xdr_stream xdr, struct svc_fh fhp, · 2439 unmodified lines
2440	p++; /* to be backfilled later */	2440	p++; /* to be backfilled later */
2441		2441
2442	if (bmval0 & FATTR4_WORD0_SUPPORTED_ATTRS) {	2442	if (bmval0 & FATTR4_WORD0_SUPPORTED_ATTRS) {
2443	u32 *supp = nfsd_suppattrs[minorversion];	2443	u32 supp[3];
		2444
		2445	memcpy(supp, nfsd_suppattrs[minorversion], sizeof(supp));
2444		2446
2445	if (!IS_POSIXACL(dentry->d_inode))	2447	if (!IS_POSIXACL(dentry->d_inode))
2446	supp[0] &= ~FATTR4_WORD0_ACL;	2448	supp[0] &= ~FATTR4_WORD0_ACL;

fs/overlayfs/namei.c+18−9

 static int ovl_lookup_layer(struct dentry *base, struct ovl_lookup_data *d,
 			    struct dentry **ret)
 {
-	const char *s = d->name.name;
+	/* Counting down from the end, since the prefix can change */
+	size_t rem = d->name.len - 1;
 	struct dentry *dentry = NULL;
 	int err;
-	if (*s != '/')
+	if (d->name.name[0] != '/')
 		return ovl_lookup_single(base, d, d->name.name, d->name.len,
 					 0, "", ret);
-	while (*s++ == '/' && !IS_ERR_OR_NULL(base) && d_can_lookup(base)) {
+	while (!IS_ERR_OR_NULL(base) && d_can_lookup(base)) {
+		const char *s = d->name.name + d->name.len - rem;
 		const char *next = strchrnul(s, '/');
-		size_t slen = strlen(s);
+		size_t thislen = next - s;
+		bool end = !next[0];
-		if (WARN_ON(slen > d->name.len) ||
+		/* Verify we did not go off the rails */
-		    WARN_ON(strcmp(d->name.name + d->name.len - slen, s)))
+		if (WARN_ON(s[-1] != '/'))
 			return -EIO;
-		err = ovl_lookup_single(base, d, s, next - s,
+		err = ovl_lookup_single(base, d, s, thislen,
-					d->name.len - slen, next, &base);
+					d->name.len - rem, next, &base);
 		dput(dentry);
 		if (err)
 			return err;
 		dentry = base;
-		s = next;
+		if (end)
+			break;
+		rem -= thislen + 1;
+		if (WARN_ON(rem >= d->name.len))
+			return -EIO;
 	}
 	*ret = dentry;
 	return 0;

fs/ubifs/Kconfig+1−1

@@ -53,7 +53,7 @@ config UBIFS_ATIME_SUPPORT · 52 unmodified lines
53		53
54	config UBIFS_FS_ENCRYPTION	54	config UBIFS_FS_ENCRYPTION
55	bool "UBIFS Encryption"	55	bool "UBIFS Encryption"
56	depends on UBIFS_FS	56	depends on UBIFS_FS && BLOCK
57	select FS_ENCRYPTION	57	select FS_ENCRYPTION
58	default n	58	default n
59	help	59	help

fs/ubifs/dir.c+3−55

@@ -390,16 +390,6 @@ static int do_tmpfile(struct inode dir, struct dentry dentry, · 389 unmodified lines
390	dbg_gen("dent '%pd', mode %#hx in dir ino %lu",	390	dbg_gen("dent '%pd', mode %#hx in dir ino %lu",
391	dentry, mode, dir->i_ino);	391	dentry, mode, dir->i_ino);
392		392
393	if (ubifs_crypt_is_encrypted(dir)) {
394	err = fscrypt_get_encryption_info(dir);
395	if (err)
396	return err;
397
398	if (!fscrypt_has_encryption_key(dir)) {
399	return -EPERM;
400	}
401	}
402
403	err = fscrypt_setup_filename(dir, &dentry->d_name, 0, &nm);	393	err = fscrypt_setup_filename(dir, &dentry->d_name, 0, &nm);
404	if (err)	394	if (err)
405	return err;	395	return err;
@@ -741,17 +731,9 @@ static int ubifs_link(struct dentry old_dentry, struct inode dir, · 335 unmodified lines
741	ubifs_assert(inode_is_locked(dir));	731	ubifs_assert(inode_is_locked(dir));
742	ubifs_assert(inode_is_locked(inode));	732	ubifs_assert(inode_is_locked(inode));
743		733
744	if (ubifs_crypt_is_encrypted(dir)) {	734	if (ubifs_crypt_is_encrypted(dir) &&
745	if (!fscrypt_has_permitted_context(dir, inode))	735	!fscrypt_has_permitted_context(dir, inode))
746	return -EPERM;	736	return -EPERM;
747
748	err = fscrypt_get_encryption_info(inode);
749	if (err)
750	return err;
751
752	if (!fscrypt_has_encryption_key(inode))
753	return -EPERM;
754	}
755		737
756	err = fscrypt_setup_filename(dir, &dentry->d_name, 0, &nm);	738	err = fscrypt_setup_filename(dir, &dentry->d_name, 0, &nm);
757	if (err)	739	if (err)
@@ -1000,17 +982,6 @@ static int ubifs_mkdir(struct inode dir, struct dentry dentry, umode_t mode) · 242 unmodified lines
1000	if (err)	982	if (err)
1001	return err;	983	return err;
1002		984
1003	if (ubifs_crypt_is_encrypted(dir)) {
1004	err = fscrypt_get_encryption_info(dir);
1005	if (err)
1006	goto out_budg;
1007
1008	if (!fscrypt_has_encryption_key(dir)) {
1009	err = -EPERM;
1010	goto out_budg;
1011	}
1012	}
1013
1014	err = fscrypt_setup_filename(dir, &dentry->d_name, 0, &nm);	985	err = fscrypt_setup_filename(dir, &dentry->d_name, 0, &nm);
1015	if (err)	986	if (err)
1016	goto out_budg;	987	goto out_budg;
@@ -1096,17 +1067,6 @@ static int ubifs_mknod(struct inode dir, struct dentry dentry, · 79 unmodified lines
1096	return err;	1067	return err;
1097	}	1068	}
1098		1069
1099	if (ubifs_crypt_is_encrypted(dir)) {
1100	err = fscrypt_get_encryption_info(dir);
1101	if (err)
1102	goto out_budg;
1103
1104	if (!fscrypt_has_encryption_key(dir)) {
1105	err = -EPERM;
1106	goto out_budg;
1107	}
1108	}
1109
1110	err = fscrypt_setup_filename(dir, &dentry->d_name, 0, &nm);	1070	err = fscrypt_setup_filename(dir, &dentry->d_name, 0, &nm);
1111	if (err)	1071	if (err)
1112	goto out_budg;	1072	goto out_budg;
@@ -1231,18 +1191,6 @@ static int ubifs_symlink(struct inode dir, struct dentry dentry, · 118 unmodified lines
1231	goto out_inode;	1191	goto out_inode;
1232	}	1192	}
1233		1193
1234	err = fscrypt_get_encryption_info(inode);
1235	if (err) {
1236	kfree(sd);
1237	goto out_inode;
1238	}
1239
1240	if (!fscrypt_has_encryption_key(inode)) {
1241	kfree(sd);
1242	err = -EPERM;
1243	goto out_inode;
1244	}
1245
1246	ostr.name = sd->encrypted_path;	1194	ostr.name = sd->encrypted_path;
1247	ostr.len = disk_link.len;	1195	ostr.len = disk_link.len;
1248		1196

fs/ubifs/ioctl.c+3−0

 	case FS_IOC32_SETFLAGS:
 		cmd = FS_IOC_SETFLAGS;
 		break;
+	case FS_IOC_SET_ENCRYPTION_POLICY:
+	case FS_IOC_GET_ENCRYPTION_POLICY:
+		break;
 	default:
 		return -ENOIOCTLCMD;
 	}

fs/ubifs/journal.c+2−0

 	} else {
 		data->compr_size = 0;
+		out_len = compr_len;
 	}
 	dlen = UBIFS_DATA_NODE_SZ + out_len;
 	dn->compr_type = cpu_to_le16(compr_type);
 	dn->size = cpu_to_le32(*new_len);
 	*new_len = UBIFS_DATA_NODE_SZ + out_len;
+	err = 0;
 out:
 	kfree(buf);
 	return err;

fs/ubifs/tnc.c+23−2

@@ -34,6 +34,11 @@ · 33 unmodified lines
34	#include <linux/slab.h>	34	#include <linux/slab.h>
35	#include "ubifs.h"	35	#include "ubifs.h"
36		36
		37	static int try_read_node(const struct ubifs_info c, void buf, int type,
		38	int len, int lnum, int offs);
		39	static int fallible_read_node(struct ubifs_info c, const union ubifs_key key,
		40	struct ubifs_zbranch zbr, void node);
		41
37	/*	42	/*
38	* Returned codes of 'matches_name()' and 'fallible_matches_name()' functions.	43	* Returned codes of 'matches_name()' and 'fallible_matches_name()' functions.
39	* @NAME_LESS: name corresponding to the first argument is less than second	44	* @NAME_LESS: name corresponding to the first argument is less than second
@@ -402,7 +407,19 @@ static int tnc_read_hashed_node(struct ubifs_info c, struct ubifs_zbranch zbr, · 362 unmodified lines
402	return 0;	407	return 0;
403	}	408	}
404		409
405	err = ubifs_tnc_read_node(c, zbr, node);	410	if (c->replaying) {
		411	err = fallible_read_node(c, &zbr->key, zbr, node);
		412	/*
		413	* When the node was not found, return -ENOENT, 0 otherwise.
		414	* Negative return codes stay as-is.
		415	*/
		416	if (err == 0)
		417	err = -ENOENT;
		418	else if (err == 1)
		419	err = 0;
		420	} else {
		421	err = ubifs_tnc_read_node(c, zbr, node);
		422	}
406	if (err)	423	if (err)
407	return err;	424	return err;
408		425
@@ -2857,7 +2874,11 @@ struct ubifs_dent_node ubifs_tnc_next_ent(struct ubifs_info c, · 2448 unmodified lines
2857	if (fname_len(nm) > 0) {	2874	if (fname_len(nm) > 0) {
2858	if (err) {	2875	if (err) {
2859	/* Handle collisions */	2876	/* Handle collisions */
2860	err = resolve_collision(c, key, &znode, &n, nm);	2877	if (c->replaying)
		2878	err = fallible_resolve_collision(c, key, &znode, &n,
		2879	nm, 0);
		2880	else
		2881	err = resolve_collision(c, key, &znode, &n, nm);
2861	dbg_tnc("rc returned %d, znode %p, n %d",	2882	dbg_tnc("rc returned %d, znode %p, n %d",
2862	err, znode, n);	2883	err, znode, n);
2863	if (unlikely(err < 0))	2884	if (unlikely(err < 0))

fs/xfs/libxfs/xfs_dir2.c+24−15

 struct xfs_name xfs_name_dotdot = { (unsigned char *)"..", 2, XFS_DIR3_FT_DIR };
 /*
- * @mode, if set, indicates that the type field needs to be set up.
+ * Convert inode mode to directory entry filetype
- * This uses the transformation from file mode to DT_* as defined in linux/fs.h
- * for file type specification. This will be propagated into the directory
- * structure if appropriate for the given operation and filesystem config.
  */
-const unsigned char xfs_mode_to_ftype[S_IFMT >> S_SHIFT] = {
+unsigned char xfs_mode_to_ftype(int mode)
-	[0]			= XFS_DIR3_FT_UNKNOWN,
+{
-	[S_IFREG >> S_SHIFT]    = XFS_DIR3_FT_REG_FILE,
+	switch (mode & S_IFMT) {
-	[S_IFDIR >> S_SHIFT]    = XFS_DIR3_FT_DIR,
+	case S_IFREG:
-	[S_IFCHR >> S_SHIFT]    = XFS_DIR3_FT_CHRDEV,
+		return XFS_DIR3_FT_REG_FILE;
-	[S_IFBLK >> S_SHIFT]    = XFS_DIR3_FT_BLKDEV,
+	case S_IFDIR:
-	[S_IFIFO >> S_SHIFT]    = XFS_DIR3_FT_FIFO,
+		return XFS_DIR3_FT_DIR;
-	[S_IFSOCK >> S_SHIFT]   = XFS_DIR3_FT_SOCK,
+	case S_IFCHR:
-	[S_IFLNK >> S_SHIFT]    = XFS_DIR3_FT_SYMLINK,
+		return XFS_DIR3_FT_CHRDEV;
-};
+	case S_IFBLK:
+		return XFS_DIR3_FT_BLKDEV;
+	case S_IFIFO:
+		return XFS_DIR3_FT_FIFO;
+	case S_IFSOCK:
+		return XFS_DIR3_FT_SOCK;
+	case S_IFLNK:
+		return XFS_DIR3_FT_SYMLINK;
+	default:
+		return XFS_DIR3_FT_UNKNOWN;
+	}
+}
 /*
  * ASCII case-insensitive (ie. A-Z) support for directories that was
 	if ((rval = xfs_bmap_last_offset(args->dp, &last, XFS_DATA_FORK)))
 		return rval;
 	rval = XFS_FSB_TO_B(args->dp->i_mount, last) == args->geo->blksize;
-	ASSERT(rval == 0 || args->dp->i_d.di_size == args->geo->blksize);
+	if (rval != 0 && args->dp->i_d.di_size != args->geo->blksize)
+		return -EFSCORRUPTED;
 	*vp = rval;
 	return 0;
 }

fs/xfs/libxfs/xfs_dir2.h+5−3

 #ifndef __XFS_DIR2_H__
 #define __XFS_DIR2_H__
+#include "xfs_da_format.h"
+#include "xfs_da_btree.h"
 struct xfs_defer_ops;
 struct xfs_da_args;
 struct xfs_inode;
 extern struct xfs_name	xfs_name_dotdot;
 /*
- * directory filetype conversion tables.
+ * Convert inode mode to directory entry filetype
  */
-#define S_SHIFT 12
+extern unsigned char xfs_mode_to_ftype(int mode);
-extern const unsigned char xfs_mode_to_ftype[];
 /*
  * directory operations vector for encode/decode routines

fs/xfs/libxfs/xfs_inode_buf.c+8−2

 #include "xfs_icache.h"
 #include "xfs_trans.h"
 #include "xfs_ialloc.h"
+#include "xfs_dir2.h"
 /*
  * Check that none of the inode's in the buffer have a next
 	xfs_ino_t		ino,
 	struct xfs_dinode	*dip)
 {
+	uint16_t		mode;
 	uint16_t		flags;
 	uint64_t		flags2;
 	if (be64_to_cpu(dip->di_size) & (1ULL << 63))
 		return false;
-	/* No zero-length symlinks. */
+	mode = be16_to_cpu(dip->di_mode);
-	if (S_ISLNK(be16_to_cpu(dip->di_mode)) && dip->di_size == 0)
+	if (mode && xfs_mode_to_ftype(mode) == XFS_DIR3_FT_UNKNOWN)
+		return false;
+	/* No zero-length symlinks/dirs. */
+	if ((S_ISLNK(mode) || S_ISDIR(mode)) && dip->di_size == 0)
 		return false;
 	/* only version 3 or greater inodes are extensively verified here */

fs/xfs/xfs_dquot.c+4−0

 	/* Simple advance */
 	next_id = *id + 1;
+	/* If we'd wrap past the max ID, stop */
+	if (next_id < *id)
+		return -ENOENT;
 	/* If new ID is within the current chunk, advancing it sufficed */
 	if (next_id % mp->m_quotainfo->qi_dqperchunk) {
 		*id = next_id;

fs/xfs/xfs_iops.c+40−10

 static void
 xfs_dentry_to_name(
+	struct xfs_name	*namep,
+	struct dentry	*dentry)
+{
+	namep->name = dentry->d_name.name;
+	namep->len = dentry->d_name.len;
+	namep->type = XFS_DIR3_FT_UNKNOWN;
+}
+static int
+xfs_dentry_mode_to_name(
 	struct xfs_name	*namep,
 	struct dentry	*dentry,
 	int		mode)
 {
 	namep->name = dentry->d_name.name;
 	namep->len = dentry->d_name.len;
-	namep->type = xfs_mode_to_ftype[(mode & S_IFMT) >> S_SHIFT];
+	namep->type = xfs_mode_to_ftype(mode);
+	if (unlikely(namep->type == XFS_DIR3_FT_UNKNOWN))
+		return -EFSCORRUPTED;
+	return 0;
 }
 STATIC void
 	 * xfs_init_security we must back out.
 	 * ENOSPC can hit here, among other things.
 	 */
-	xfs_dentry_to_name(&teardown, dentry, 0);
+	xfs_dentry_to_name(&teardown, dentry);
 	xfs_remove(XFS_I(dir), &teardown, XFS_I(inode));
 }
 	if (error)
 		return error;
+	/* Verify mode is valid also for tmpfile case */
+	error = xfs_dentry_mode_to_name(&name, dentry, mode);
+	if (unlikely(error))
+		goto out_free_acl;
 	if (!tmpfile) {
-		xfs_dentry_to_name(&name, dentry, mode);
 		error = xfs_create(XFS_I(dir), &name, mode, rdev, &ip);
 	} else {
 		error = xfs_create_tmpfile(XFS_I(dir), dentry, mode, &ip);
 	if (dentry->d_name.len >= MAXNAMELEN)
 		return ERR_PTR(-ENAMETOOLONG);
-	xfs_dentry_to_name(&name, dentry, 0);
+	xfs_dentry_to_name(&name, dentry);
 	error = xfs_lookup(XFS_I(dir), &name, &cip, NULL);
 	if (unlikely(error)) {
 		if (unlikely(error != -ENOENT))
 	if (dentry->d_name.len >= MAXNAMELEN)
 		return ERR_PTR(-ENAMETOOLONG);
-	xfs_dentry_to_name(&xname, dentry, 0);
+	xfs_dentry_to_name(&xname, dentry);
 	error = xfs_lookup(XFS_I(dir), &xname, &ip, &ci_name);
 	if (unlikely(error)) {
 		if (unlikely(error != -ENOENT))
 	struct xfs_name	name;
 	int		error;
-	xfs_dentry_to_name(&name, dentry, inode->i_mode);
+	error = xfs_dentry_mode_to_name(&name, dentry, inode->i_mode);
+	if (unlikely(error))
+		return error;
 	error = xfs_link(XFS_I(dir), XFS_I(inode), &name);
 	if (unlikely(error))
 	struct xfs_name	name;
 	int		error;
-	xfs_dentry_to_name(&name, dentry, 0);
+	xfs_dentry_to_name(&name, dentry);
 	error = xfs_remove(XFS_I(dir), &name, XFS_I(d_inode(dentry)));
 	if (error)
 	mode = S_IFLNK |
 		(irix_symlink_mode ? 0777 & ~current_umask() : S_IRWXUGO);
-	xfs_dentry_to_name(&name, dentry, mode);
+	error = xfs_dentry_mode_to_name(&name, dentry, mode);
+	if (unlikely(error))
+		goto out;
 	error = xfs_symlink(XFS_I(dir), &name, symname, mode, &cip);
 	if (unlikely(error))
 {
 	struct inode	*new_inode = d_inode(ndentry);
 	int		omode = 0;
+	int		error;
 	struct xfs_name	oname;
 	struct xfs_name	nname;
 	if (flags & RENAME_EXCHANGE)
 		omode = d_inode(ndentry)->i_mode;
-	xfs_dentry_to_name(&oname, odentry, omode);
+	error = xfs_dentry_mode_to_name(&oname, odentry, omode);
-	xfs_dentry_to_name(&nname, ndentry, d_inode(odentry)->i_mode);
+	if (omode && unlikely(error))
+		return error;
+	error = xfs_dentry_mode_to_name(&nname, ndentry,
+					d_inode(odentry)->i_mode);
+	if (unlikely(error))
+		return error;
 	return xfs_rename(XFS_I(odir), &oname, XFS_I(d_inode(odentry)),
 			  XFS_I(ndir), &nname,

fs/xfs/xfs_linux.h+3−3

@@ -331,11 +331,11 @@ static inline __uint64_t howmany_64(__uint64_t x, __uint32_t y) · 330 unmodified lines
331	}	331	}
332		332
333	#define ASSERT_ALWAYS(expr) \	333	#define ASSERT_ALWAYS(expr) \
334	(unlikely(expr) ? (void)0 : assfail(#expr, __FILE__, __LINE__))	334	(likely(expr) ? (void)0 : assfail(#expr, __FILE__, __LINE__))
335		335
336	#ifdef DEBUG	336	#ifdef DEBUG
337	#define ASSERT(expr) \	337	#define ASSERT(expr) \
338	(unlikely(expr) ? (void)0 : assfail(#expr, __FILE__, __LINE__))	338	(likely(expr) ? (void)0 : assfail(#expr, __FILE__, __LINE__))
339		339
340	#ifndef STATIC	340	#ifndef STATIC
341	# define STATIC noinline	341	# define STATIC noinline
@@ -346,7 +346,7 @@ static inline __uint64_t howmany_64(__uint64_t x, __uint32_t y) · 4 unmodified lines
346	#ifdef XFS_WARN	346	#ifdef XFS_WARN
347		347
348	#define ASSERT(expr) \	348	#define ASSERT(expr) \
349	(unlikely(expr) ? (void)0 : asswarn(#expr, __FILE__, __LINE__))	349	(likely(expr) ? (void)0 : asswarn(#expr, __FILE__, __LINE__))
350		350
351	#ifndef STATIC	351	#ifndef STATIC
352	# define STATIC static noinline	352	# define STATIC static noinline

include/kvm/arm_arch_timer.h+22−18

 #include <linux/hrtimer.h>
 #include <linux/workqueue.h>
-struct arch_timer_kvm {
+struct arch_timer_context {
+	/* Registers: control register, timer value */
+	u32				cnt_ctl;
+	u64				cnt_cval;
+	/* Timer IRQ */
+	struct kvm_irq_level		irq;
+	/* Active IRQ state caching */
+	bool				active_cleared_last;
 	/* Virtual offset */
 	u64			cntvoff;
 };
 struct arch_timer_cpu {
-	/* Registers: control register, timer value */
+	struct arch_timer_context	vtimer;
-	u32				cntv_ctl;	/* Saved/restored */
+	struct arch_timer_context	ptimer;
-	u64				cntv_cval;	/* Saved/restored */
-	/*
-	 * Anything that is not used directly from assembly code goes
-	 * here.
-	 */
 	/* Background timer used when the guest is not running */
 	struct hrtimer			timer;
 	/* Background timer active */
 	bool				armed;
-	/* Timer IRQ */
-	struct kvm_irq_level		irq;
-	/* Active IRQ state caching */
-	bool				active_cleared_last;
 	/* Is the timer enabled */
 	bool			enabled;
 };
 int kvm_timer_hyp_init(void);
 int kvm_timer_enable(struct kvm_vcpu *vcpu);
-void kvm_timer_init(struct kvm *kvm);
 int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
-			 const struct kvm_irq_level *irq);
+			 const struct kvm_irq_level *virt_irq,
+			 const struct kvm_irq_level *phys_irq);
 void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
 void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
 void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
 u64 kvm_arm_timer_get_reg(struct kvm_vcpu *, u64 regid);
 int kvm_arm_timer_set_reg(struct kvm_vcpu *, u64 regid, u64 value);
-bool kvm_timer_should_fire(struct kvm_vcpu *vcpu);
+bool kvm_timer_should_fire(struct arch_timer_context *timer_ctx);
 void kvm_timer_schedule(struct kvm_vcpu *vcpu);
 void kvm_timer_unschedule(struct kvm_vcpu *vcpu);
+u64 kvm_phys_timer_read(void);
 void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);
+void kvm_timer_init_vhe(void);
+#define vcpu_vtimer(v)	(&(v)->arch.timer_cpu.vtimer)
+#define vcpu_ptimer(v)	(&(v)->arch.timer_cpu.ptimer)
 #endif

include/kvm/arm_vgic.h+16−2

 	/* GIC system register CPU interface */
 	struct static_key_false gicv3_cpuif;
+	u32			ich_vtr_el2;
 };
 extern struct vgic_global kvm_vgic_global_state;
 					 */
 	u32 intid;			/* Guest visible INTID */
-	bool pending;
 	bool line_level;		/* Level only */
-	bool soft_pending;		/* Level only */
+	bool pending_latch;		/* The pending latch state used to calculate
+					 * the pending state for both level
+					 * and edge triggered IRQs. */
 	bool active;			/* not used for LPIs */
 	bool enabled;
 	bool hw;			/* Tied to HW IRQ */
 	struct list_head	collection_list;
 };
+struct vgic_state_iter;
 struct vgic_dist {
 	bool			in_kernel;
 	bool			ready;
 	spinlock_t		lpi_list_lock;
 	struct list_head	lpi_list_head;
 	int			lpi_list_count;
+	/* used by vgic-debug */
+	struct vgic_state_iter *iter;
 };
 struct vgic_v2_cpu_if {
 	u64 pendbaser;
 	bool lpis_enabled;
+	/* Cache guest priority bits */
+	u32 num_pri_bits;
+	/* Cache guest interrupt ID bits */
+	u32 num_id_bits;
 };
 extern struct static_key_false vgic_v2_cpuif_trap;

include/linux/bpf.h+1−1

@@ -216,7 +216,7 @@ u64 bpf_tail_call(u64 ctx, u64 r2, u64 index, u64 r4, u64 r5); · 215 unmodified lines
216	u64 bpf_get_stackid(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5);	216	u64 bpf_get_stackid(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5);
217		217
218	bool bpf_prog_array_compatible(struct bpf_array array, const struct bpf_prog fp);	218	bool bpf_prog_array_compatible(struct bpf_array array, const struct bpf_prog fp);
219	int bpf_prog_calc_digest(struct bpf_prog *fp);	219	int bpf_prog_calc_tag(struct bpf_prog *fp);
220		220
221	const struct bpf_func_proto *bpf_get_trace_printk_proto(void);	221	const struct bpf_func_proto *bpf_get_trace_printk_proto(void);
222		222

include/linux/cpuhotplug.h+2−0

 	CPUHP_ZCOMP_PREPARE,
 	CPUHP_TIMERS_DEAD,
 	CPUHP_MIPS_SOC_PREPARE,
+	CPUHP_BP_PREPARE_DYN,
+	CPUHP_BP_PREPARE_DYN_END		= CPUHP_BP_PREPARE_DYN + 20,
 	CPUHP_BRINGUP_CPU,
 	CPUHP_AP_IDLE_DEAD,
 	CPUHP_AP_OFFLINE,

include/linux/filter.h+4−2

 /* BPF program can access up to 512 bytes of stack space. */
 #define MAX_BPF_STACK	512
+#define BPF_TAG_SIZE	8
 /* Helper macros for filter block array initializers. */
 /* ALU ops on registers, bpf_add|sub|...: dst_reg += src_reg */
 	kmemcheck_bitfield_end(meta);
 	enum bpf_prog_type	type;		/* Type of BPF program */
 	u32			len;		/* Number of filter blocks */
-	u32			digest[SHA_DIGEST_WORDS]; /* Program digest */
+	u8			tag[BPF_TAG_SIZE];
 	struct bpf_prog_aux	*aux;		/* Auxiliary fields */
 	struct sock_fprog_kern	*orig_prog;	/* Original BPF program */
 	unsigned int		(*bpf_func)(const void *ctx,
 	return prog->len * sizeof(struct bpf_insn);
 }
-static inline u32 bpf_prog_digest_scratch_size(const struct bpf_prog *prog)
+static inline u32 bpf_prog_tag_scratch_size(const struct bpf_prog *prog)
 {
 	return round_up(bpf_prog_insn_size(prog) +
 			sizeof(__be64) + 1, SHA_MESSAGE_BYTES);

include/linux/irqchip/arm-gic-v3.h+41−4

@@ -352,8 +352,30 @@ · 351 unmodified lines
352	/*	352	/*
353	* CPU interface registers	353	* CPU interface registers
354	*/	354	*/
355	#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)	355	#define ICC_CTLR_EL1_EOImode_SHIFT (1)
356	#define ICC_CTLR_EL1_EOImode_drop (1U << 1)	356	#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
		357	#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
		358	#define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
		359	#define ICC_CTLR_EL1_CBPR_SHIFT 0
		360	#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
		361	#define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
		362	#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
		363	#define ICC_CTLR_EL1_ID_BITS_SHIFT 11
		364	#define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
		365	#define ICC_CTLR_EL1_SEIS_SHIFT 14
		366	#define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
		367	#define ICC_CTLR_EL1_A3V_SHIFT 15
		368	#define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
		369	#define ICC_PMR_EL1_SHIFT 0
		370	#define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
		371	#define ICC_BPR0_EL1_SHIFT 0
		372	#define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
		373	#define ICC_BPR1_EL1_SHIFT 0
		374	#define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
		375	#define ICC_IGRPEN0_EL1_SHIFT 0
		376	#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
		377	#define ICC_IGRPEN1_EL1_SHIFT 0
		378	#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
357	#define ICC_SRE_EL1_SRE (1U << 0)	379	#define ICC_SRE_EL1_SRE (1U << 0)
358		380
359	/*	381	/*
@@ -382,14 +404,29 @@ · 22 unmodified lines
382	#define ICH_HCR_EN (1 << 0)	404	#define ICH_HCR_EN (1 << 0)
383	#define ICH_HCR_UIE (1 << 1)	405	#define ICH_HCR_UIE (1 << 1)
384		406
385	#define ICH_VMCR_CTLR_SHIFT 0	407	#define ICH_VMCR_CBPR_SHIFT 4
386	#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)	408	#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
		409	#define ICH_VMCR_EOIM_SHIFT 9
		410	#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
387	#define ICH_VMCR_BPR1_SHIFT 18	411	#define ICH_VMCR_BPR1_SHIFT 18
388	#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)	412	#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
389	#define ICH_VMCR_BPR0_SHIFT 21	413	#define ICH_VMCR_BPR0_SHIFT 21
390	#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)	414	#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
391	#define ICH_VMCR_PMR_SHIFT 24	415	#define ICH_VMCR_PMR_SHIFT 24
392	#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)	416	#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
		417	#define ICH_VMCR_ENG0_SHIFT 0
		418	#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
		419	#define ICH_VMCR_ENG1_SHIFT 1
		420	#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
		421
		422	#define ICH_VTR_PRI_BITS_SHIFT 29
		423	#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
		424	#define ICH_VTR_ID_BITS_SHIFT 23
		425	#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
		426	#define ICH_VTR_SEIS_SHIFT 22
		427	#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
		428	#define ICH_VTR_A3V_SHIFT 21
		429	#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
393		430
394	#define ICC_IAR1_EL1_SPURIOUS 0x3ff	431	#define ICC_IAR1_EL1_SPURIOUS 0x3ff
395		432

include/linux/kernel.h+2−2

@@ -514,8 +514,8 @@ extern enum system_states { · 513 unmodified lines
514	#define TAINT_FLAGS_COUNT 16	514	#define TAINT_FLAGS_COUNT 16
515		515
516	struct taint_flag {	516	struct taint_flag {
517	char true; /* character printed when tainted */	517	char c_true; /* character printed when tainted */
518	char false; /* character printed when not tainted */	518	char c_false; /* character printed when not tainted */
519	bool module; /* also show as a per-module taint flag */	519	bool module; /* also show as a per-module taint flag */
520	};	520	};
521		521

include/linux/kvm_host.h+0−1

@@ -45,7 +45,6 @@ · 44 unmodified lines
45	* include/linux/kvm_h.	45	* include/linux/kvm_h.
46	*/	46	*/
47	#define KVM_MEMSLOT_INVALID (1UL << 16)	47	#define KVM_MEMSLOT_INVALID (1UL << 16)
48	#define KVM_MEMSLOT_INCOHERENT (1UL << 17)
49		48
50	/* Two fragments for cross MMIO pages. */	49	/* Two fragments for cross MMIO pages. */
51	#define KVM_MAX_MMIO_FRAGMENTS 2	50	#define KVM_MAX_MMIO_FRAGMENTS 2

include/linux/rcupdate.h+4−0

 #error "Unknown RCU implementation specified to kernel configuration"
 #endif
+#define RCU_SCHEDULER_INACTIVE	0
+#define RCU_SCHEDULER_INIT	1
+#define RCU_SCHEDULER_RUNNING	2
 /*
  * init_rcu_head_on_stack()/destroy_rcu_head_on_stack() are needed for dynamic
  * initialization and destruction of rcu_head on the stack. rcu_head structures

include/linux/sunrpc/svc_xprt.h+1−0

@@ -66,6 +66,7 @@ struct svc_xprt { · 65 unmodified lines
66	#define XPT_LISTENER 10 /* listening endpoint */	66	#define XPT_LISTENER 10 /* listening endpoint */
67	#define XPT_CACHE_AUTH 11 /* cache auth info */	67	#define XPT_CACHE_AUTH 11 /* cache auth info */
68	#define XPT_LOCAL 12 /* connection from loopback interface */	68	#define XPT_LOCAL 12 /* connection from loopback interface */
		69	#define XPT_KILL_TEMP 13 /* call xpo_kill_temp_xprt before closing */
69		70
70	struct svc_serv xpt_server; / service for transport */	71	struct svc_serv xpt_server; / service for transport */
71	atomic_t xpt_reserved; /* space on outq that is rsvd */	72	atomic_t xpt_reserved; /* space on outq that is rsvd */

include/linux/tcp.h+6−1

 /* TCP Fast Open Cookie as stored in memory */
 struct tcp_fastopen_cookie {
+	union {
+		u8	val[TCP_FASTOPEN_COOKIE_MAX];
+#if IS_ENABLED(CONFIG_IPV6)
+		struct in6_addr addr;
+#endif
+	};
 	s8	len;
-	u8	val[TCP_FASTOPEN_COOKIE_MAX];
 	bool	exp;	/* In RFC6994 experimental option format */
 };

include/scsi/libfc.h+3−3

@@ -809,11 +809,11 @@ static inline void fc_set_wwnn(struct fc_lport *lport, u64 wwnn) · 808 unmodified lines
809	/**	809	/**
810	* fc_set_wwpn() - Set the World Wide Port Name of a local port	810	* fc_set_wwpn() - Set the World Wide Port Name of a local port
811	* @lport: The local port whose WWPN is to be set	811	* @lport: The local port whose WWPN is to be set
812	* @wwnn: The new WWPN	812	* @wwpn: The new WWPN
813	*/	813	*/
814	static inline void fc_set_wwpn(struct fc_lport *lport, u64 wwnn)	814	static inline void fc_set_wwpn(struct fc_lport *lport, u64 wwpn)
815	{	815	{
816	lport->wwpn = wwnn;	816	lport->wwpn = wwpn;
817	}	817	}
818		818
819	/**	819	/**

include/uapi/linux/nl80211.h+3−1

  *
  * @NL80211_ATTR_OPMODE_NOTIF: Operating mode field from Operating Mode
  *	Notification Element based on association request when used with
- *	%NL80211_CMD_NEW_STATION; u8 attribute.
+ *	%NL80211_CMD_NEW_STATION or %NL80211_CMD_SET_STATION (only when
+ *	%NL80211_FEATURE_FULL_AP_CLIENT_STATE is supported, or with TDLS);
+ *	u8 attribute.
  *
  * @NL80211_ATTR_VENDOR_ID: The vendor ID, either a 24-bit OUI or, if
  *	%NL80211_VENDOR_ID_IS_LINUX is set, a special Linux ID (not used yet)

include/uapi/linux/pkt_cls.h+1−1

@@ -397,7 +397,7 @@ enum { · 396 unmodified lines
397	TCA_BPF_NAME,	397	TCA_BPF_NAME,
398	TCA_BPF_FLAGS,	398	TCA_BPF_FLAGS,
399	TCA_BPF_FLAGS_GEN,	399	TCA_BPF_FLAGS_GEN,
400	TCA_BPF_DIGEST,	400	TCA_BPF_TAG,
401	__TCA_BPF_MAX,	401	__TCA_BPF_MAX,
402	};	402	};
403		403

include/uapi/linux/tc_act/tc_bpf.h+1−1

@@ -27,7 +27,7 @@ enum { · 26 unmodified lines
27	TCA_ACT_BPF_FD,	27	TCA_ACT_BPF_FD,
28	TCA_ACT_BPF_NAME,	28	TCA_ACT_BPF_NAME,
29	TCA_ACT_BPF_PAD,	29	TCA_ACT_BPF_PAD,
30	TCA_ACT_BPF_DIGEST,	30	TCA_ACT_BPF_TAG,
31	__TCA_ACT_BPF_MAX,	31	__TCA_ACT_BPF_MAX,
32	};	32	};
33	#define TCA_ACT_BPF_MAX (__TCA_ACT_BPF_MAX - 1)	33	#define TCA_ACT_BPF_MAX (__TCA_ACT_BPF_MAX - 1)

kernel/bpf/core.c+8−6

 	vfree(fp);
 }
-int bpf_prog_calc_digest(struct bpf_prog *fp)
+int bpf_prog_calc_tag(struct bpf_prog *fp)
 {
 	const u32 bits_offset = SHA_MESSAGE_BYTES - sizeof(__be64);
-	u32 raw_size = bpf_prog_digest_scratch_size(fp);
+	u32 raw_size = bpf_prog_tag_scratch_size(fp);
+	u32 digest[SHA_DIGEST_WORDS];
 	u32 ws[SHA_WORKSPACE_WORDS];
 	u32 i, bsize, psize, blocks;
 	struct bpf_insn *dst;
 	if (!raw)
 		return -ENOMEM;
-	sha_init(fp->digest);
+	sha_init(digest);
 	memset(ws, 0, sizeof(ws));
 	/* We need to take out the map fd for the digest calculation
 	*bits = cpu_to_be64((psize - 1) << 3);
 	while (blocks--) {
-		sha_transform(fp->digest, todo, ws);
+		sha_transform(digest, todo, ws);
 		todo += SHA_MESSAGE_BYTES;
 	}
-	result = (__force __be32 *)fp->digest;
+	result = (__force __be32 *)digest;
 	for (i = 0; i < SHA_DIGEST_WORDS; i++)
-		result[i] = cpu_to_be32(fp->digest[i]);
+		result[i] = cpu_to_be32(digest[i]);
+	memcpy(fp->tag, result, sizeof(fp->tag));
 	vfree(raw);
 	return 0;

kernel/bpf/syscall.c+4−4

@@ -688,17 +688,17 @@ static int bpf_prog_release(struct inode inode, struct file filp) · 687 unmodified lines
688	static void bpf_prog_show_fdinfo(struct seq_file m, struct file filp)	688	static void bpf_prog_show_fdinfo(struct seq_file m, struct file filp)
689	{	689	{
690	const struct bpf_prog *prog = filp->private_data;	690	const struct bpf_prog *prog = filp->private_data;
691	char prog_digest[sizeof(prog->digest) * 2 + 1] = { };	691	char prog_tag[sizeof(prog->tag) * 2 + 1] = { };
692		692
693	bin2hex(prog_digest, prog->digest, sizeof(prog->digest));	693	bin2hex(prog_tag, prog->tag, sizeof(prog->tag));
694	seq_printf(m,	694	seq_printf(m,
695	"prog_type:\t%u\n"	695	"prog_type:\t%u\n"
696	"prog_jited:\t%u\n"	696	"prog_jited:\t%u\n"
697	"prog_digest:\t%s\n"	697	"prog_tag:\t%s\n"
698	"memlock:\t%llu\n",	698	"memlock:\t%llu\n",
699	prog->type,	699	prog->type,
700	prog->jited,	700	prog->jited,
701	prog_digest,	701	prog_tag,
702	prog->pages * 1ULL << PAGE_SHIFT);	702	prog->pages * 1ULL << PAGE_SHIFT);
703	}	703	}
704	#endif	704	#endif

kernel/bpf/verifier.c+1−1

@@ -2936,7 +2936,7 @@ static int replace_map_fd_with_map_ptr(struct bpf_verifier_env *env) · 2935 unmodified lines
2936	int insn_cnt = env->prog->len;	2936	int insn_cnt = env->prog->len;
2937	int i, j, err;	2937	int i, j, err;
2938		2938
2939	err = bpf_prog_calc_digest(env->prog);	2939	err = bpf_prog_calc_tag(env->prog);
2940	if (err)	2940	if (err)
2941	return err;	2941	return err;
2942		2942

kernel/cpu.c+18−6

 {
 	struct cpuhp_cpu_state *st = per_cpu_ptr(&cpuhp_state, cpu);
 	int prev_state, ret = 0;
-	bool hasdied = false;
 	if (num_online_cpus() == 1)
 		return -EBUSY;
 		cpuhp_kick_ap_work(cpu);
 	}
-	hasdied = prev_state != st->state && st->state == CPUHP_OFFLINE;
 out:
 	cpu_hotplug_done();
 	return ret;
  */
 static int cpuhp_reserve_state(enum cpuhp_state state)
 {
-	enum cpuhp_state i;
+	enum cpuhp_state i, end;
+	struct cpuhp_step *step;
-	for (i = CPUHP_AP_ONLINE_DYN; i <= CPUHP_AP_ONLINE_DYN_END; i++) {
+	switch (state) {
-		if (!cpuhp_ap_states[i].name)
+	case CPUHP_AP_ONLINE_DYN:
+		step = cpuhp_ap_states + CPUHP_AP_ONLINE_DYN;
+		end = CPUHP_AP_ONLINE_DYN_END;
+		break;
+	case CPUHP_BP_PREPARE_DYN:
+		step = cpuhp_bp_states + CPUHP_BP_PREPARE_DYN;
+		end = CPUHP_BP_PREPARE_DYN_END;
+		break;
+	default:
+		return -EINVAL;
+	}
+	for (i = state; i <= end; i++, step++) {
+		if (!step->name)
 			return i;
 	}
 	WARN(1, "No more dynamic states available for CPU hotplug\n");
 	mutex_lock(&cpuhp_state_mutex);
-	if (state == CPUHP_AP_ONLINE_DYN) {
+	if (state == CPUHP_AP_ONLINE_DYN || state == CPUHP_BP_PREPARE_DYN) {
 		ret = cpuhp_reserve_state(state);
 		if (ret < 0)
 			goto out;

kernel/module.c+1−1

@@ -1145,7 +1145,7 @@ static size_t module_flags_taint(struct module mod, char buf) · 1144 unmodified lines
1145		1145
1146	for (i = 0; i < TAINT_FLAGS_COUNT; i++) {	1146	for (i = 0; i < TAINT_FLAGS_COUNT; i++) {
1147	if (taint_flags[i].module && test_bit(i, &mod->taints))	1147	if (taint_flags[i].module && test_bit(i, &mod->taints))
1148	buf[l++] = taint_flags[i].true;	1148	buf[l++] = taint_flags[i].c_true;
1149	}	1149	}
1150		1150
1151	return l;	1151	return l;

kernel/panic.c+1−1

@@ -355,7 +355,7 @@ const char *print_tainted(void) · 354 unmodified lines
355	for (i = 0; i < TAINT_FLAGS_COUNT; i++) {	355	for (i = 0; i < TAINT_FLAGS_COUNT; i++) {
356	const struct taint_flag *t = &taint_flags[i];	356	const struct taint_flag *t = &taint_flags[i];
357	*s++ = test_bit(i, &tainted_mask) ?	357	*s++ = test_bit(i, &tainted_mask) ?
358	t->true : t->false;	358	t->c_true : t->c_false;
359	}	359	}
360	*s = 0;	360	*s = 0;
361	} else	361	} else

kernel/rcu/rcu.h+1−0

@@ -136,6 +136,7 @@ int rcu_jiffies_till_stall_check(void); · 135 unmodified lines
136	#define TPS(x) tracepoint_string(x)	136	#define TPS(x) tracepoint_string(x)
137		137
138	void rcu_early_boot_tests(void);	138	void rcu_early_boot_tests(void);
		139	void rcu_test_sync_prims(void);
139		140
140	/*	141	/*
141	* This function really isn't for public consumption, but RCU is special in	142	* This function really isn't for public consumption, but RCU is special in

kernel/rcu/tiny.c+0−4

  * benefits of doing might_sleep() to reduce latency.)
  *
  * Cool, huh?  (Due to Josh Triplett.)
- *
- * But we want to make this a static inline later.  The cond_resched()
- * currently makes this problematic.
  */
 void synchronize_sched(void)
 {
 			 lock_is_held(&rcu_lock_map) ||
 			 lock_is_held(&rcu_sched_lock_map),
 			 "Illegal synchronize_sched() in RCU read-side critical section");
-	cond_resched();
 }
 EXPORT_SYMBOL_GPL(synchronize_sched);

kernel/rcu/tiny_plugin.h+7−2

 /*
  * During boot, we forgive RCU lockdep issues.  After this function is
- * invoked, we start taking RCU lockdep issues seriously.
+ * invoked, we start taking RCU lockdep issues seriously.  Note that unlike
+ * Tree RCU, Tiny RCU transitions directly from RCU_SCHEDULER_INACTIVE
+ * to RCU_SCHEDULER_RUNNING, skipping the RCU_SCHEDULER_INIT stage.
+ * The reason for this is that Tiny RCU does not need kthreads, so does
+ * not have to care about the fact that the scheduler is half-initialized
+ * at a certain phase of the boot process.
  */
 void __init rcu_scheduler_starting(void)
 {
 	WARN_ON(nr_context_switches() > 0);
-	rcu_scheduler_active = 1;
+	rcu_scheduler_active = RCU_SCHEDULER_RUNNING;
 }
 #endif /* #ifdef CONFIG_DEBUG_LOCK_ALLOC */

kernel/rcu/tree.c+20−13

 int sysctl_panic_on_rcu_stall __read_mostly;
 /*
- * The rcu_scheduler_active variable transitions from zero to one just
+ * The rcu_scheduler_active variable is initialized to the value
- * before the first task is spawned.  So when this variable is zero, RCU
+ * RCU_SCHEDULER_INACTIVE and transitions RCU_SCHEDULER_INIT just before the
- * can assume that there is but one task, allowing RCU to (for example)
+ * first task is spawned.  So when this variable is RCU_SCHEDULER_INACTIVE,
+ * RCU can assume that there is but one task, allowing RCU to (for example)
  * optimize synchronize_rcu() to a simple barrier().  When this variable
- * is one, RCU must actually do all the hard work required to detect real
+ * is RCU_SCHEDULER_INIT, RCU must actually do all the hard work required
- * grace periods.  This variable is also used to suppress boot-time false
+ * to detect real grace periods.  This variable is also used to suppress
- * positives from lockdep-RCU error checking.
+ * boot-time false positives from lockdep-RCU error checking.  Finally, it
+ * transitions from RCU_SCHEDULER_INIT to RCU_SCHEDULER_RUNNING after RCU
+ * is fully initialized, including all of its kthreads having been spawned.
  */
 int rcu_scheduler_active __read_mostly;
 EXPORT_SYMBOL_GPL(rcu_scheduler_active);
 early_initcall(rcu_spawn_gp_kthread);
 /*
- * This function is invoked towards the end of the scheduler's initialization
+ * This function is invoked towards the end of the scheduler's
- * process.  Before this is called, the idle task might contain
+ * initialization process.  Before this is called, the idle task might
- * RCU read-side critical sections (during which time, this idle
+ * contain synchronous grace-period primitives (during which time, this idle
- * task is booting the system).  After this function is called, the
+ * task is booting the system, and such primitives are no-ops).  After this
- * idle tasks are prohibited from containing RCU read-side critical
+ * function is called, any synchronous grace-period primitives are run as
- * sections.  This function also enables RCU lockdep checking.
+ * expedited, with the requesting task driving the grace period forward.
+ * A later core_initcall() rcu_exp_runtime_mode() will switch to full
+ * runtime RCU functionality.
  */
 void rcu_scheduler_starting(void)
 {
 	WARN_ON(num_online_cpus() != 1);
 	WARN_ON(nr_context_switches() > 0);
-	rcu_scheduler_active = 1;
+	rcu_test_sync_prims();
+	rcu_scheduler_active = RCU_SCHEDULER_INIT;
+	rcu_test_sync_prims();
 }
 /*

kernel/rcu/tree_exp.h+41−11

 	struct work_struct rew_work;
 };
+/*
+ * Common code to drive an expedited grace period forward, used by
+ * workqueues and mid-boot-time tasks.
+ */
+static void rcu_exp_sel_wait_wake(struct rcu_state *rsp,
+				  smp_call_func_t func, unsigned long s)
+{
+	/* Initialize the rcu_node tree in preparation for the wait. */
+	sync_rcu_exp_select_cpus(rsp, func);
+	/* Wait and clean up, including waking everyone. */
+	rcu_exp_wait_wake(rsp, s);
+}
 /*
  * Work-queue handler to drive an expedited grace period forward.
  */
 {
 	struct rcu_exp_work *rewp;
-	/* Initialize the rcu_node tree in preparation for the wait. */
 	rewp = container_of(wp, struct rcu_exp_work, rew_work);
-	sync_rcu_exp_select_cpus(rewp->rew_rsp, rewp->rew_func);
+	rcu_exp_sel_wait_wake(rewp->rew_rsp, rewp->rew_func, rewp->rew_s);
-	/* Wait and clean up, including waking everyone. */
-	rcu_exp_wait_wake(rewp->rew_rsp, rewp->rew_s);
 }
 /*
 	if (exp_funnel_lock(rsp, s))
 		return;  /* Someone else did our work for us. */
-	/* Marshall arguments and schedule the expedited grace period. */
+	/* Ensure that load happens before action based on it. */
-	rew.rew_func = func;
+	if (unlikely(rcu_scheduler_active == RCU_SCHEDULER_INIT)) {
-	rew.rew_rsp = rsp;
+		/* Direct call during scheduler init and early_initcalls(). */
-	rew.rew_s = s;
+		rcu_exp_sel_wait_wake(rsp, func, s);
-	INIT_WORK_ONSTACK(&rew.rew_work, wait_rcu_exp_gp);
+	} else {
-	schedule_work(&rew.rew_work);
+		/* Marshall arguments & schedule the expedited grace period. */
+		rew.rew_func = func;
+		rew.rew_rsp = rsp;
+		rew.rew_s = s;
+		INIT_WORK_ONSTACK(&rew.rew_work, wait_rcu_exp_gp);
+		schedule_work(&rew.rew_work);
+	}
 	/* Wait for expedited grace period to complete. */
 	rdp = per_cpu_ptr(rsp->rda, raw_smp_processor_id());
 {
 	struct rcu_state *rsp = rcu_state_p;
+	if (rcu_scheduler_active == RCU_SCHEDULER_INACTIVE)
+		return;
 	_synchronize_rcu_expedited(rsp, sync_rcu_exp_handler);
 }
 EXPORT_SYMBOL_GPL(synchronize_rcu_expedited);
 EXPORT_SYMBOL_GPL(synchronize_rcu_expedited);
 #endif /* #else #ifdef CONFIG_PREEMPT_RCU */
+/*
+ * Switch to run-time mode once Tree RCU has fully initialized.
+ */
+static int __init rcu_exp_runtime_mode(void)
+{
+	rcu_test_sync_prims();
+	rcu_scheduler_active = RCU_SCHEDULER_RUNNING;
+	rcu_test_sync_prims();
+	return 0;
+}
+core_initcall(rcu_exp_runtime_mode);

kernel/rcu/tree_plugin.h+1−1

@@ -670,7 +670,7 @@ void synchronize_rcu(void) · 669 unmodified lines
670	lock_is_held(&rcu_lock_map) \|\|	670	lock_is_held(&rcu_lock_map) \|\|
671	lock_is_held(&rcu_sched_lock_map),	671	lock_is_held(&rcu_sched_lock_map),
672	"Illegal synchronize_rcu() in RCU read-side critical section");	672	"Illegal synchronize_rcu() in RCU read-side critical section");
673	if (!rcu_scheduler_active)	673	if (rcu_scheduler_active == RCU_SCHEDULER_INACTIVE)
674	return;	674	return;
675	if (rcu_gp_is_expedited())	675	if (rcu_gp_is_expedited())
676	synchronize_rcu_expedited();	676	synchronize_rcu_expedited();

kernel/rcu/update.c+30−8

  * Should expedited grace-period primitives always fall back to their
  * non-expedited counterparts?  Intended for use within RCU.  Note
  * that if the user specifies both rcu_expedited and rcu_normal, then
- * rcu_normal wins.
+ * rcu_normal wins.  (Except during the time period during boot from
+ * when the first task is spawned until the rcu_exp_runtime_mode()
+ * core_initcall() is invoked, at which point everything is expedited.)
  */
 bool rcu_gp_is_normal(void)
 {
-	return READ_ONCE(rcu_normal);
+	return READ_ONCE(rcu_normal) &&
+	       rcu_scheduler_active != RCU_SCHEDULER_INIT;
 }
 EXPORT_SYMBOL_GPL(rcu_gp_is_normal);
 /*
  * Should normal grace-period primitives be expedited?  Intended for
  * use within RCU.  Note that this function takes the rcu_expedited
- * sysfs/boot variable into account as well as the rcu_expedite_gp()
+ * sysfs/boot variable and rcu_scheduler_active into account as well
- * nesting.  So looping on rcu_unexpedite_gp() until rcu_gp_is_expedited()
+ * as the rcu_expedite_gp() nesting.  So looping on rcu_unexpedite_gp()
- * returns false is a -really- bad idea.
+ * until rcu_gp_is_expedited() returns false is a -really- bad idea.
  */
 bool rcu_gp_is_expedited(void)
 {
-	return rcu_expedited || atomic_read(&rcu_expedited_nesting);
+	return rcu_expedited || atomic_read(&rcu_expedited_nesting) ||
+	       rcu_scheduler_active == RCU_SCHEDULER_INIT;
 }
 EXPORT_SYMBOL_GPL(rcu_gp_is_expedited);
 int notrace debug_lockdep_rcu_enabled(void)
 {
-	return rcu_scheduler_active && debug_locks &&
+	return rcu_scheduler_active != RCU_SCHEDULER_INACTIVE && debug_locks &&
 	       current->lockdep_recursion == 0;
 }
 EXPORT_SYMBOL_GPL(debug_lockdep_rcu_enabled);
 void synchronize_rcu_tasks(void)
 {
 	/* Complain if the scheduler has not started.  */
-	RCU_LOCKDEP_WARN(!rcu_scheduler_active,
+	RCU_LOCKDEP_WARN(rcu_scheduler_active == RCU_SCHEDULER_INACTIVE,
 			 "synchronize_rcu_tasks called too soon");
 	/* Wait for the grace period. */
 #endif /* #ifdef CONFIG_TASKS_RCU */
+/*
+ * Test each non-SRCU synchronous grace-period wait API.  This is
+ * useful just after a change in mode for these primitives, and
+ * during early boot.
+ */
+void rcu_test_sync_prims(void)
+{
+	if (!IS_ENABLED(CONFIG_PROVE_RCU))
+		return;
+	synchronize_rcu();
+	synchronize_rcu_bh();
+	synchronize_sched();
+	synchronize_rcu_expedited();
+	synchronize_rcu_bh_expedited();
+	synchronize_sched_expedited();
+}
 #ifdef CONFIG_PROVE_RCU
 /*
 		early_boot_test_call_rcu_bh();
 	if (rcu_self_test_sched)
 		early_boot_test_call_rcu_sched();
+	rcu_test_sync_prims();
 }
 static int rcu_verify_early_boot_tests(void)

lib/swiotlb.c+3−3

@@ -483,11 +483,11 @@ phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, · 482 unmodified lines
483	: 1UL << (BITS_PER_LONG - IO_TLB_SHIFT);	483	: 1UL << (BITS_PER_LONG - IO_TLB_SHIFT);
484		484
485	/*	485	/*
486	* For mappings greater than a page, we limit the stride (and	486	* For mappings greater than or equal to a page, we limit the stride
487	* hence alignment) to a page size.	487	* (and hence alignment) to a page size.
488	*/	488	*/
489	nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;	489	nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
490	if (size > PAGE_SIZE)	490	if (size >= PAGE_SIZE)
491	stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT));	491	stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT));
492	else	492	else
493	stride = 1;	493	stride = 1;

net/ax25/ax25_subr.c+1−1

@@ -264,7 +264,7 @@ void ax25_disconnect(ax25_cb *ax25, int reason) · 263 unmodified lines
264	{	264	{
265	ax25_clear_queues(ax25);	265	ax25_clear_queues(ax25);
266		266
267	if (!sock_flag(ax25->sk, SOCK_DESTROY))	267	if (!ax25->sk \|\| !sock_flag(ax25->sk, SOCK_DESTROY))
268	ax25_stop_heartbeat(ax25);	268	ax25_stop_heartbeat(ax25);
269	ax25_stop_t1timer(ax25);	269	ax25_stop_t1timer(ax25);
270	ax25_stop_t2timer(ax25);	270	ax25_stop_t2timer(ax25);

net/ceph/crypto.c+1−1

@@ -214,7 +214,7 @@ static int ceph_aes_crypt(const struct ceph_crypto_key *key, bool encrypt, · 213 unmodified lines
214	SKCIPHER_REQUEST_ON_STACK(req, key->tfm);	214	SKCIPHER_REQUEST_ON_STACK(req, key->tfm);
215	struct sg_table sgt;	215	struct sg_table sgt;
216	struct scatterlist prealloc_sg;	216	struct scatterlist prealloc_sg;
217	char iv[AES_BLOCK_SIZE];	217	char iv[AES_BLOCK_SIZE] __aligned(8);
218	int pad_byte = AES_BLOCK_SIZE - (in_len & (AES_BLOCK_SIZE - 1));	218	int pad_byte = AES_BLOCK_SIZE - (in_len & (AES_BLOCK_SIZE - 1));
219	int crypt_len = encrypt ? in_len + pad_byte : in_len;	219	int crypt_len = encrypt ? in_len + pad_byte : in_len;
220	int ret;	220	int ret;

net/ipv4/fib_semantics.c+7−4

 		    nla_put_u32(skb, RTA_FLOW, fi->fib_nh[0].nh_tclassid))
 			goto nla_put_failure;
 #endif
-		if (fi->fib_nh->nh_lwtstate)
+		if (fi->fib_nh->nh_lwtstate &&
-			lwtunnel_fill_encap(skb, fi->fib_nh->nh_lwtstate);
+		    lwtunnel_fill_encap(skb, fi->fib_nh->nh_lwtstate) < 0)
+			goto nla_put_failure;
 	}
 #ifdef CONFIG_IP_ROUTE_MULTIPATH
 	if (fi->fib_nhs > 1) {
 			    nla_put_u32(skb, RTA_FLOW, nh->nh_tclassid))
 				goto nla_put_failure;
 #endif
-			if (nh->nh_lwtstate)
+			if (nh->nh_lwtstate &&
-				lwtunnel_fill_encap(skb, nh->nh_lwtstate);
+			    lwtunnel_fill_encap(skb, nh->nh_lwtstate) < 0)
+				goto nla_put_failure;
 			/* length of rtnetlink header + attributes */
 			rtnh->rtnh_len = nlmsg_get_pos(skb) - (void *) rtnh;
 		} endfor_nexthops(fi);

net/ipv4/route.c+1−1

@@ -2472,7 +2472,7 @@ static int rt_fill_info(struct net *net, __be32 dst, __be32 src, u32 table_id, · 2471 unmodified lines
2472	r->rtm_dst_len = 32;	2472	r->rtm_dst_len = 32;
2473	r->rtm_src_len = 0;	2473	r->rtm_src_len = 0;
2474	r->rtm_tos = fl4->flowi4_tos;	2474	r->rtm_tos = fl4->flowi4_tos;
2475	r->rtm_table = table_id;	2475	r->rtm_table = table_id < 256 ? table_id : RT_TABLE_COMPAT;
2476	if (nla_put_u32(skb, RTA_TABLE, table_id))	2476	if (nla_put_u32(skb, RTA_TABLE, table_id))
2477	goto nla_put_failure;	2477	goto nla_put_failure;
2478	r->rtm_type = rt->rt_type;	2478	r->rtm_type = rt->rt_type;

net/ipv4/tcp_fastopen.c+1−1

@@ -113,7 +113,7 @@ static bool tcp_fastopen_cookie_gen(struct request_sock *req, · 112 unmodified lines
113	struct tcp_fastopen_cookie tmp;	113	struct tcp_fastopen_cookie tmp;
114		114
115	if (__tcp_fastopen_cookie_gen(&ip6h->saddr, &tmp)) {	115	if (__tcp_fastopen_cookie_gen(&ip6h->saddr, &tmp)) {
116	struct in6_addr buf = (struct in6_addr ) tmp.val;	116	struct in6_addr *buf = &tmp.addr;
117	int i;	117	int i;
118		118
119	for (i = 0; i < 4; i++)	119	for (i = 0; i < 4; i++)

net/ipv6/ip6_tunnel.c+2−2

@@ -1108,7 +1108,7 @@ route_lookup: · 1107 unmodified lines
1108	t->parms.name);	1108	t->parms.name);
1109	goto tx_err_dst_release;	1109	goto tx_err_dst_release;
1110	}	1110	}
1111	mtu = dst_mtu(dst) - psh_hlen;	1111	mtu = dst_mtu(dst) - psh_hlen - t->tun_hlen;
1112	if (encap_limit >= 0) {	1112	if (encap_limit >= 0) {
1113	max_headroom += 8;	1113	max_headroom += 8;
1114	mtu -= 8;	1114	mtu -= 8;
@@ -1117,7 +1117,7 @@ route_lookup: · 2 unmodified lines
1117	mtu = IPV6_MIN_MTU;	1117	mtu = IPV6_MIN_MTU;
1118	if (skb_dst(skb) && !t->parms.collect_md)	1118	if (skb_dst(skb) && !t->parms.collect_md)
1119	skb_dst(skb)->ops->update_pmtu(skb_dst(skb), NULL, skb, mtu);	1119	skb_dst(skb)->ops->update_pmtu(skb_dst(skb), NULL, skb, mtu);
1120	if (skb->len > mtu && !skb_is_gso(skb)) {	1120	if (skb->len - t->tun_hlen > mtu && !skb_is_gso(skb)) {
1121	*pmtu = mtu;	1121	*pmtu = mtu;
1122	err = -EMSGSIZE;	1122	err = -EMSGSIZE;
1123	goto tx_err_dst_release;	1123	goto tx_err_dst_release;

net/ipv6/mcast.c+30−21

 static void mld_ifc_timer_expire(unsigned long data);
 static void mld_ifc_event(struct inet6_dev *idev);
 static void mld_add_delrec(struct inet6_dev *idev, struct ifmcaddr6 *pmc);
-static void mld_del_delrec(struct inet6_dev *idev, const struct in6_addr *addr);
+static void mld_del_delrec(struct inet6_dev *idev, struct ifmcaddr6 *pmc);
 static void mld_clear_delrec(struct inet6_dev *idev);
 static bool mld_in_v1_mode(const struct inet6_dev *idev);
 static int sf_setstate(struct ifmcaddr6 *pmc);
 			dev_mc_del(dev, buf);
 	}
-	if (mc->mca_flags & MAF_NOREPORT)
-		goto done;
 	spin_unlock_bh(&mc->mca_lock);
+	if (mc->mca_flags & MAF_NOREPORT)
+		return;
 	if (!mc->idev->dead)
 		igmp6_leave_group(mc);
 	spin_lock_bh(&mc->mca_lock);
 	if (del_timer(&mc->mca_timer))
 		atomic_dec(&mc->mca_refcnt);
-done:
-	ip6_mc_clear_src(mc);
 	spin_unlock_bh(&mc->mca_lock);
 }
 	spin_unlock_bh(&idev->mc_lock);
 }
-static void mld_del_delrec(struct inet6_dev *idev, const struct in6_addr *pmca)
+static void mld_del_delrec(struct inet6_dev *idev, struct ifmcaddr6 *im)
 {
 	struct ifmcaddr6 *pmc, *pmc_prev;
-	struct ip6_sf_list *psf, *psf_next;
+	struct ip6_sf_list *psf;
+	struct in6_addr *pmca = &im->mca_addr;
 	spin_lock_bh(&idev->mc_lock);
 	pmc_prev = NULL;
 	}
 	spin_unlock_bh(&idev->mc_lock);
+	spin_lock_bh(&im->mca_lock);
 	if (pmc) {
-		for (psf = pmc->mca_tomb; psf; psf = psf_next) {
+		im->idev = pmc->idev;
-			psf_next = psf->sf_next;
+		im->mca_crcount = idev->mc_qrv;
-			kfree(psf);
+		im->mca_sfmode = pmc->mca_sfmode;
+		if (pmc->mca_sfmode == MCAST_INCLUDE) {
+			im->mca_tomb = pmc->mca_tomb;
+			im->mca_sources = pmc->mca_sources;
+			for (psf = im->mca_sources; psf; psf = psf->sf_next)
+				psf->sf_crcount = im->mca_crcount;
 		}
 		in6_dev_put(pmc->idev);
-		kfree(pmc);
 	}
+	spin_unlock_bh(&im->mca_lock);
 }
 static void mld_clear_delrec(struct inet6_dev *idev)
 	mca_get(mc);
 	write_unlock_bh(&idev->lock);
-	mld_del_delrec(idev, &mc->mca_addr);
+	mld_del_delrec(idev, mc);
 	igmp6_group_added(mc);
 	ma_put(mc);
 	return 0;
 				write_unlock_bh(&idev->lock);
 				igmp6_group_dropped(ma);
+				ip6_mc_clear_src(ma);
 				ma_put(ma);
 				return 0;
 	/* Withdraw multicast list */
 	read_lock_bh(&idev->lock);
-	mld_ifc_stop_timer(idev);
-	mld_gq_stop_timer(idev);
-	mld_dad_stop_timer(idev);
 	for (i = idev->mc_list; i; i = i->next)
 		igmp6_group_dropped(i);
-	read_unlock_bh(&idev->lock);
-	mld_clear_delrec(idev);
+	/* Should stop timer after group drop. or we will
+	 * start timer again in mld_ifc_event()
+	 */
+	mld_ifc_stop_timer(idev);
+	mld_gq_stop_timer(idev);
+	mld_dad_stop_timer(idev);
+	read_unlock_bh(&idev->lock);
 }
 static void ipv6_mc_reset(struct inet6_dev *idev)
 	read_lock_bh(&idev->lock);
 	ipv6_mc_reset(idev);
-	for (i = idev->mc_list; i; i = i->next)
+	for (i = idev->mc_list; i; i = i->next) {
+		mld_del_delrec(idev, i);
 		igmp6_group_added(i);
+	}
 	read_unlock_bh(&idev->lock);
 }
 	/* Deactivate timers */
 	ipv6_mc_down(idev);
+	mld_clear_delrec(idev);
 	/* Delete all-nodes address. */
 	/* We cannot call ipv6_dev_mc_dec() directly, our caller in
 	write_lock_bh(&idev->lock);
 	while ((i = idev->mc_list) != NULL) {
 		idev->mc_list = i->next;
-		write_unlock_bh(&idev->lock);
-		igmp6_group_dropped(i);
+		write_unlock_bh(&idev->lock);
 		ma_put(i);
 		write_lock_bh(&idev->lock);
 	}
 	write_unlock_bh(&idev->lock);

net/ipv6/route.c+2−1

@@ -3317,7 +3317,8 @@ static int rt6_fill_node(struct net *net, · 3316 unmodified lines
3317	if (nla_put_u8(skb, RTA_PREF, IPV6_EXTRACT_PREF(rt->rt6i_flags)))	3317	if (nla_put_u8(skb, RTA_PREF, IPV6_EXTRACT_PREF(rt->rt6i_flags)))
3318	goto nla_put_failure;	3318	goto nla_put_failure;
3319		3319
3320	lwtunnel_fill_encap(skb, rt->dst.lwtstate);	3320	if (lwtunnel_fill_encap(skb, rt->dst.lwtstate) < 0)
		3321	goto nla_put_failure;
3321		3322
3322	nlmsg_end(skb, nlh);	3323	nlmsg_end(skb, nlh);
3323	return 0;	3324	return 0;

net/ipv6/seg6_hmac.c+1−1

@@ -400,7 +400,7 @@ static int seg6_hmac_init_algo(void) · 399 unmodified lines
400	*p_tfm = tfm;	400	*p_tfm = tfm;
401	}	401	}
402		402
403	p_tfm = this_cpu_ptr(algo->tfms);	403	p_tfm = raw_cpu_ptr(algo->tfms);
404	tfm = *p_tfm;	404	tfm = *p_tfm;
405		405
406	shsize = sizeof(*shash) + crypto_shash_descsize(tfm);	406	shsize = sizeof(*shash) + crypto_shash_descsize(tfm);

net/ipv6/seg6_iptunnel.c+4−0

 	slwt = seg6_lwt_lwtunnel(orig_dst->lwtstate);
 #ifdef CONFIG_DST_CACHE
+	preempt_disable();
 	dst = dst_cache_get(&slwt->cache);
+	preempt_enable();
 #endif
 	if (unlikely(!dst)) {
 		}
 #ifdef CONFIG_DST_CACHE
+		preempt_disable();
 		dst_cache_set_ip6(&slwt->cache, dst, &fl6.saddr);
+		preempt_enable();
 #endif
 	}

net/mac80211/chan.c+0−3

@@ -231,9 +231,6 @@ ieee80211_get_max_required_bw(struct ieee80211_sub_if_data *sdata) · 230 unmodified lines
231	!(sta->sdata->bss && sta->sdata->bss == sdata->bss))	231	!(sta->sdata->bss && sta->sdata->bss == sdata->bss))
232	continue;	232	continue;
233		233
234	if (!sta->uploaded \|\| !test_sta_flag(sta, WLAN_STA_ASSOC))
235	continue;
236
237	max_bw = max(max_bw, ieee80211_get_sta_bw(&sta->sta));	234	max_bw = max(max_bw, ieee80211_get_sta_bw(&sta->sta));
238	}	235	}
239	rcu_read_unlock();	236	rcu_read_unlock();

net/mac80211/iface.c+21−0

@@ -6,6 +6,7 @@ · 5 unmodified lines
6	* Copyright (c) 2006 Jiri Benc <jbenc@suse.cz>	6	* Copyright (c) 2006 Jiri Benc <jbenc@suse.cz>
7	* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>	7	* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
8	* Copyright 2013-2014 Intel Mobile Communications GmbH	8	* Copyright 2013-2014 Intel Mobile Communications GmbH
		9	* Copyright (c) 2016 Intel Deutschland GmbH
9	*	10	*
10	* This program is free software; you can redistribute it and/or modify	11	* This program is free software; you can redistribute it and/or modify
11	* it under the terms of the GNU General Public License version 2 as	12	* it under the terms of the GNU General Public License version 2 as
@@ -1295,6 +1296,26 @@ static void ieee80211_iface_work(struct work_struct *work) · 1283 unmodified lines
1295	} else if (ieee80211_is_action(mgmt->frame_control) &&	1296	} else if (ieee80211_is_action(mgmt->frame_control) &&
1296	mgmt->u.action.category == WLAN_CATEGORY_VHT) {	1297	mgmt->u.action.category == WLAN_CATEGORY_VHT) {
1297	switch (mgmt->u.action.u.vht_group_notif.action_code) {	1298	switch (mgmt->u.action.u.vht_group_notif.action_code) {
		1299	case WLAN_VHT_ACTION_OPMODE_NOTIF: {
		1300	struct ieee80211_rx_status *status;
		1301	enum nl80211_band band;
		1302	u8 opmode;
		1303
		1304	status = IEEE80211_SKB_RXCB(skb);
		1305	band = status->band;
		1306	opmode = mgmt->u.action.u.vht_opmode_notif.operating_mode;
		1307
		1308	mutex_lock(&local->sta_mtx);
		1309	sta = sta_info_get_bss(sdata, mgmt->sa);
		1310
		1311	if (sta)
		1312	ieee80211_vht_handle_opmode(sdata, sta,
		1313	opmode,
		1314	band);
		1315
		1316	mutex_unlock(&local->sta_mtx);
		1317	break;
		1318	}
1298	case WLAN_VHT_ACTION_GROUPID_MGMT:	1319	case WLAN_VHT_ACTION_GROUPID_MGMT:
1299	ieee80211_process_mu_groups(sdata, mgmt);	1320	ieee80211_process_mu_groups(sdata, mgmt);
1300	break;	1321	break;

net/mac80211/main.c+9−4

 		supp_ht = supp_ht || sband->ht_cap.ht_supported;
 		supp_vht = supp_vht || sband->vht_cap.vht_supported;
-		if (sband->ht_cap.ht_supported)
+		if (!sband->ht_cap.ht_supported)
-			local->rx_chains =
+			continue;
-				max(ieee80211_mcs_to_chains(&sband->ht_cap.mcs),
-				    local->rx_chains);
 		/* TODO: consider VHT for RX chains, hopefully it's the same */
+		local->rx_chains =
+			max(ieee80211_mcs_to_chains(&sband->ht_cap.mcs),
+			    local->rx_chains);
+		/* no need to mask, SM_PS_DISABLED has all bits set */
+		sband->ht_cap.cap |= WLAN_HT_CAP_SM_PS_DISABLED <<
+			             IEEE80211_HT_CAP_SM_PS_SHIFT;
 	}
 	/* if low-level driver supports AP, we also support VLAN */

net/mac80211/rate.c+2−0

@@ -40,6 +40,8 @@ void rate_control_rate_init(struct sta_info *sta) · 39 unmodified lines
40		40
41	ieee80211_sta_set_rx_nss(sta);	41	ieee80211_sta_set_rx_nss(sta);
42		42
		43	ieee80211_recalc_min_chandef(sta->sdata);
		44
43	if (!ref)	45	if (!ref)
44	return;	46	return;
45		47

net/mac80211/rx.c+21−17

@@ -2472,7 +2472,8 @@ ieee80211_rx_h_mesh_fwding(struct ieee80211_rx_data *rx) · 2471 unmodified lines
2472	if (!ifmsh->mshcfg.dot11MeshForwarding)	2472	if (!ifmsh->mshcfg.dot11MeshForwarding)
2473	goto out;	2473	goto out;
2474		2474
2475	fwd_skb = skb_copy_expand(skb, local->tx_headroom, 0, GFP_ATOMIC);	2475	fwd_skb = skb_copy_expand(skb, local->tx_headroom +
		2476	sdata->encrypt_headroom, 0, GFP_ATOMIC);
2476	if (!fwd_skb) {	2477	if (!fwd_skb) {
2477	net_info_ratelimited("%s: failed to clone mesh frame\n",	2478	net_info_ratelimited("%s: failed to clone mesh frame\n",
2478	sdata->name);	2479	sdata->name);
@@ -2880,17 +2881,10 @@ ieee80211_rx_h_action(struct ieee80211_rx_data *rx) · 401 unmodified lines
2880		2881
2881	switch (mgmt->u.action.u.vht_opmode_notif.action_code) {	2882	switch (mgmt->u.action.u.vht_opmode_notif.action_code) {
2882	case WLAN_VHT_ACTION_OPMODE_NOTIF: {	2883	case WLAN_VHT_ACTION_OPMODE_NOTIF: {
2883	u8 opmode;
2884
2885	/* verify opmode is present */	2884	/* verify opmode is present */
2886	if (len < IEEE80211_MIN_ACTION_SIZE + 2)	2885	if (len < IEEE80211_MIN_ACTION_SIZE + 2)
2887	goto invalid;	2886	goto invalid;
2888		2887	goto queue;
2889	opmode = mgmt->u.action.u.vht_opmode_notif.operating_mode;
2890
2891	ieee80211_vht_handle_opmode(rx->sdata, rx->sta,
2892	opmode, status->band);
2893	goto handled;
2894	}	2888	}
2895	case WLAN_VHT_ACTION_GROUPID_MGMT: {	2889	case WLAN_VHT_ACTION_GROUPID_MGMT: {
2896	if (len < IEEE80211_MIN_ACTION_SIZE + 25)	2890	if (len < IEEE80211_MIN_ACTION_SIZE + 25)
@@ -3942,21 +3936,31 @@ static bool ieee80211_invoke_fast_rx(struct ieee80211_rx_data *rx, · 1045 unmodified lines
3942	u64_stats_update_end(&stats->syncp);	3936	u64_stats_update_end(&stats->syncp);
3943		3937
3944	if (fast_rx->internal_forward) {	3938	if (fast_rx->internal_forward) {
3945	struct sta_info *dsta = sta_info_get(rx->sdata, skb->data);	3939	struct sk_buff *xmit_skb = NULL;
		3940	bool multicast = is_multicast_ether_addr(skb->data);
		3941
		3942	if (multicast) {
		3943	xmit_skb = skb_copy(skb, GFP_ATOMIC);
		3944	} else if (sta_info_get(rx->sdata, skb->data)) {
		3945	xmit_skb = skb;
		3946	skb = NULL;
		3947	}
3946		3948
3947	if (dsta) {	3949	if (xmit_skb) {
3948	/*	3950	/*
3949	* Send to wireless media and increase priority by 256	3951	* Send to wireless media and increase priority by 256
3950	* to keep the received priority instead of	3952	* to keep the received priority instead of
3951	* reclassifying the frame (see cfg80211_classify8021d).	3953	* reclassifying the frame (see cfg80211_classify8021d).
3952	*/	3954	*/
3953	skb->priority += 256;	3955	xmit_skb->priority += 256;
3954	skb->protocol = htons(ETH_P_802_3);	3956	xmit_skb->protocol = htons(ETH_P_802_3);
3955	skb_reset_network_header(skb);	3957	skb_reset_network_header(xmit_skb);
3956	skb_reset_mac_header(skb);	3958	skb_reset_mac_header(xmit_skb);
3957	dev_queue_xmit(skb);	3959	dev_queue_xmit(xmit_skb);
3958	return true;
3959	}	3960	}
		3961
		3962	if (!skb)
		3963	return true;
3960	}	3964	}
3961		3965
3962	/* deliver to local stack */	3966	/* deliver to local stack */

net/mac80211/sta_info.c+2−2

@@ -1501,8 +1501,8 @@ ieee80211_sta_ps_deliver_response(struct sta_info *sta, · 1500 unmodified lines
1501		1501
1502	/* This will evaluate to 1, 3, 5 or 7. */	1502	/* This will evaluate to 1, 3, 5 or 7. */
1503	for (ac = IEEE80211_AC_VO; ac < IEEE80211_NUM_ACS; ac++)	1503	for (ac = IEEE80211_AC_VO; ac < IEEE80211_NUM_ACS; ac++)
1504	if (ignored_acs & BIT(ac))	1504	if (!(ignored_acs & ieee80211_ac_to_qos_mask[ac]))
1505	continue;	1505	break;
1506	tid = 7 - 2 * ac;	1506	tid = 7 - 2 * ac;
1507		1507
1508	ieee80211_send_null_response(sta, tid, reason, true, false);	1508	ieee80211_send_null_response(sta, tid, reason, true, false);

net/mac80211/tx.c+7−10

 static struct txq_info *ieee80211_get_txq(struct ieee80211_local *local,
 					  struct ieee80211_vif *vif,
-					  struct ieee80211_sta *pubsta,
+					  struct sta_info *sta,
 					  struct sk_buff *skb)
 {
 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
 	if (!ieee80211_is_data(hdr->frame_control))
 		return NULL;
-	if (pubsta) {
+	if (sta) {
 		u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
-		txq = pubsta->txq[tid];
+		if (!sta->uploaded)
+			return NULL;
+		txq = sta->sta.txq[tid];
 	} else if (vif) {
 		txq = vif->txq;
 	}
 	struct fq *fq = &local->fq;
 	struct ieee80211_vif *vif;
 	struct txq_info *txqi;
-	struct ieee80211_sta *pubsta;
 	if (!local->ops->wake_tx_queue ||
 	    sdata->vif.type == NL80211_IFTYPE_MONITOR)
 		return false;
-	if (sta && sta->uploaded)
-		pubsta = &sta->sta;
-	else
-		pubsta = NULL;
 	if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN)
 		sdata = container_of(sdata->bss,
 				     struct ieee80211_sub_if_data, u.ap);
 	vif = &sdata->vif;
-	txqi = ieee80211_get_txq(local, vif, pubsta, skb);
+	txqi = ieee80211_get_txq(local, vif, sta, skb);
 	if (!txqi)
 		return false;

net/mac80211/vht.c+3−1

@@ -527,8 +527,10 @@ void ieee80211_vht_handle_opmode(struct ieee80211_sub_if_data *sdata, · 526 unmodified lines
527		527
528	u32 changed = __ieee80211_vht_handle_opmode(sdata, sta, opmode, band);	528	u32 changed = __ieee80211_vht_handle_opmode(sdata, sta, opmode, band);
529		529
530	if (changed > 0)	530	if (changed > 0) {
		531	ieee80211_recalc_min_chandef(sdata);
531	rate_control_rate_update(local, sband, sta, changed);	532	rate_control_rate_update(local, sband, sta, changed);
		533	}
532	}	534	}
533		535
534	void ieee80211_get_vht_mask_from_cap(__le16 vht_cap,	536	void ieee80211_get_vht_mask_from_cap(__le16 vht_cap,

net/openvswitch/conntrack.c+4−2

 	int hooknum, nh_off, err = NF_ACCEPT;
 	nh_off = skb_network_offset(skb);
-	skb_pull(skb, nh_off);
+	skb_pull_rcsum(skb, nh_off);
 	/* See HOOK2MANIP(). */
 	if (maniptype == NF_NAT_MANIP_SRC)
 	err = nf_nat_packet(ct, ctinfo, hooknum, skb);
 push:
 	skb_push(skb, nh_off);
+	skb_postpush_rcsum(skb, skb->data, nh_off);
 	return err;
 }
 	/* The conntrack module expects to be working at L3. */
 	nh_ofs = skb_network_offset(skb);
-	skb_pull(skb, nh_ofs);
+	skb_pull_rcsum(skb, nh_ofs);
 	if (key->ip.frag != OVS_FRAG_TYPE_NONE) {
 		err = handle_fragments(net, key, info->zone.id, skb);
 		err = ovs_ct_lookup(net, key, info, skb);
 	skb_push(skb, nh_ofs);
+	skb_postpush_rcsum(skb, skb->data, nh_ofs);
 	if (err)
 		kfree_skb(skb);
 	return err;

net/sched/act_api.c+2−3

 			goto err;
 		}
 		act->order = i;
-		if (event == RTM_GETACTION)
-			act->tcfa_refcnt++;
 		list_add_tail(&act->list, &actions);
 	}
 		return ret;
 	}
 err:
-	tcf_action_destroy(&actions, 0);
+	if (event != RTM_GETACTION)
+		tcf_action_destroy(&actions, 0);
 	return ret;
 }

net/sched/act_bpf.c+2−3

 	    nla_put_string(skb, TCA_ACT_BPF_NAME, prog->bpf_name))
 		return -EMSGSIZE;
-	nla = nla_reserve(skb, TCA_ACT_BPF_DIGEST,
+	nla = nla_reserve(skb, TCA_ACT_BPF_TAG, sizeof(prog->filter->tag));
-			  sizeof(prog->filter->digest));
 	if (nla == NULL)
 		return -EMSGSIZE;
-	memcpy(nla_data(nla), prog->filter->digest, nla_len(nla));
+	memcpy(nla_data(nla), prog->filter->tag, nla_len(nla));
 	return 0;
 }

net/sched/cls_bpf.c+2−2

@@ -555,11 +555,11 @@ static int cls_bpf_dump_ebpf_info(const struct cls_bpf_prog *prog, · 554 unmodified lines
555	nla_put_string(skb, TCA_BPF_NAME, prog->bpf_name))	555	nla_put_string(skb, TCA_BPF_NAME, prog->bpf_name))
556	return -EMSGSIZE;	556	return -EMSGSIZE;
557		557
558	nla = nla_reserve(skb, TCA_BPF_DIGEST, sizeof(prog->filter->digest));	558	nla = nla_reserve(skb, TCA_BPF_TAG, sizeof(prog->filter->tag));
559	if (nla == NULL)	559	if (nla == NULL)
560	return -EMSGSIZE;	560	return -EMSGSIZE;
561		561
562	memcpy(nla_data(nla), prog->filter->digest, nla_len(nla));	562	memcpy(nla_data(nla), prog->filter->tag, nla_len(nla));
563		563
564	return 0;	564	return 0;
565	}	565	}

net/sunrpc/auth_gss/svcauth_gss.c+1−1

@@ -1489,7 +1489,7 @@ svcauth_gss_accept(struct svc_rqst rqstp, __be32 authp) · 1488 unmodified lines
1489	case RPC_GSS_PROC_DESTROY:	1489	case RPC_GSS_PROC_DESTROY:
1490	if (gss_write_verf(rqstp, rsci->mechctx, gc->gc_seq))	1490	if (gss_write_verf(rqstp, rsci->mechctx, gc->gc_seq))
1491	goto auth_err;	1491	goto auth_err;
1492	rsci->h.expiry_time = get_seconds();	1492	rsci->h.expiry_time = seconds_since_boot();
1493	set_bit(CACHE_NEGATIVE, &rsci->h.flags);	1493	set_bit(CACHE_NEGATIVE, &rsci->h.flags);
1494	if (resv->iov_len + 4 > PAGE_SIZE)	1494	if (resv->iov_len + 4 > PAGE_SIZE)
1495	goto drop;	1495	goto drop;

net/sunrpc/svc_xprt.c+7−3

 	if (test_bit(XPT_CLOSE, &xprt->xpt_flags)) {
 		dprintk("svc_recv: found XPT_CLOSE\n");
+		if (test_and_clear_bit(XPT_KILL_TEMP, &xprt->xpt_flags))
+			xprt->xpt_ops->xpo_kill_temp_xprt(xprt);
 		svc_delete_xprt(xprt);
 		/* Leave XPT_BUSY set on the dead xprt: */
 		goto out;
 		le = to_be_closed.next;
 		list_del_init(le);
 		xprt = list_entry(le, struct svc_xprt, xpt_list);
-		dprintk("svc_age_temp_xprts_now: closing %p\n", xprt);
+		set_bit(XPT_CLOSE, &xprt->xpt_flags);
-		xprt->xpt_ops->xpo_kill_temp_xprt(xprt);
+		set_bit(XPT_KILL_TEMP, &xprt->xpt_flags);
-		svc_close_xprt(xprt);
+		dprintk("svc_age_temp_xprts_now: queuing xprt %p for closing\n",
+				xprt);
+		svc_xprt_enqueue(xprt);
 	}
 }
 EXPORT_SYMBOL_GPL(svc_age_temp_xprts_now);

net/sunrpc/xprtrdma/svc_rdma_recvfrom.c+0−2

 	atomic_inc(&rdma_stat_read);
 	return ret;
  err:
-	ib_dma_unmap_sg(xprt->sc_cm_id->device,
-			frmr->sg, frmr->sg_nents, frmr->direction);
 	svc_rdma_put_context(ctxt, 0);
 	svc_rdma_put_frmr(xprt, frmr);
 	return ret;

net/tipc/discover.c+2−2

@@ -169,7 +169,7 @@ void tipc_disc_rcv(struct net net, struct sk_buff skb, · 168 unmodified lines
169		169
170	/* Send response, if necessary */	170	/* Send response, if necessary */
171	if (respond && (mtyp == DSC_REQ_MSG)) {	171	if (respond && (mtyp == DSC_REQ_MSG)) {
172	rskb = tipc_buf_acquire(MAX_H_SIZE);	172	rskb = tipc_buf_acquire(MAX_H_SIZE, GFP_ATOMIC);
173	if (!rskb)	173	if (!rskb)
174	return;	174	return;
175	tipc_disc_init_msg(net, rskb, DSC_RESP_MSG, bearer);	175	tipc_disc_init_msg(net, rskb, DSC_RESP_MSG, bearer);
@@ -278,7 +278,7 @@ int tipc_disc_create(struct net net, struct tipc_bearer b, · 102 unmodified lines
278	req = kmalloc(sizeof(*req), GFP_ATOMIC);	278	req = kmalloc(sizeof(*req), GFP_ATOMIC);
279	if (!req)	279	if (!req)
280	return -ENOMEM;	280	return -ENOMEM;
281	req->buf = tipc_buf_acquire(MAX_H_SIZE);	281	req->buf = tipc_buf_acquire(MAX_H_SIZE, GFP_ATOMIC);
282	if (!req->buf) {	282	if (!req->buf) {
283	kfree(req);	283	kfree(req);
284	return -ENOMEM;	284	return -ENOMEM;

net/tipc/link.c+1−1

@@ -1395,7 +1395,7 @@ tnl: · 1394 unmodified lines
1395	msg_set_seqno(hdr, seqno++);	1395	msg_set_seqno(hdr, seqno++);
1396	pktlen = msg_size(hdr);	1396	pktlen = msg_size(hdr);
1397	msg_set_size(&tnlhdr, pktlen + INT_H_SIZE);	1397	msg_set_size(&tnlhdr, pktlen + INT_H_SIZE);
1398	tnlskb = tipc_buf_acquire(pktlen + INT_H_SIZE);	1398	tnlskb = tipc_buf_acquire(pktlen + INT_H_SIZE, GFP_ATOMIC);
1399	if (!tnlskb) {	1399	if (!tnlskb) {
1400	pr_warn("%sunable to send packet\n", link_co_err);	1400	pr_warn("%sunable to send packet\n", link_co_err);
1401	return;	1401	return;

net/tipc/msg.c+8−8

@@ -58,12 +58,12 @@ static unsigned int align(unsigned int i) · 57 unmodified lines
58	* NOTE: Headroom is reserved to allow prepending of a data link header.	58	* NOTE: Headroom is reserved to allow prepending of a data link header.
59	* There may also be unrequested tailroom present at the buffer's end.	59	* There may also be unrequested tailroom present at the buffer's end.
60	*/	60	*/
61	struct sk_buff *tipc_buf_acquire(u32 size)	61	struct sk_buff *tipc_buf_acquire(u32 size, gfp_t gfp)
62	{	62	{
63	struct sk_buff *skb;	63	struct sk_buff *skb;
64	unsigned int buf_size = (BUF_HEADROOM + size + 3) & ~3u;	64	unsigned int buf_size = (BUF_HEADROOM + size + 3) & ~3u;
65		65
66	skb = alloc_skb_fclone(buf_size, GFP_ATOMIC);	66	skb = alloc_skb_fclone(buf_size, gfp);
67	if (skb) {	67	if (skb) {
68	skb_reserve(skb, BUF_HEADROOM);	68	skb_reserve(skb, BUF_HEADROOM);
69	skb_put(skb, size);	69	skb_put(skb, size);
@@ -95,7 +95,7 @@ struct sk_buff *tipc_msg_create(uint user, uint type, · 25 unmodified lines
95	struct tipc_msg *msg;	95	struct tipc_msg *msg;
96	struct sk_buff *buf;	96	struct sk_buff *buf;
97		97
98	buf = tipc_buf_acquire(hdr_sz + data_sz);	98	buf = tipc_buf_acquire(hdr_sz + data_sz, GFP_ATOMIC);
99	if (unlikely(!buf))	99	if (unlikely(!buf))
100	return NULL;	100	return NULL;
101		101
@@ -261,7 +261,7 @@ int tipc_msg_build(struct tipc_msg mhdr, struct msghdr m, · 159 unmodified lines
261		261
262	/* No fragmentation needed? */	262	/* No fragmentation needed? */
263	if (likely(msz <= pktmax)) {	263	if (likely(msz <= pktmax)) {
264	skb = tipc_buf_acquire(msz);	264	skb = tipc_buf_acquire(msz, GFP_KERNEL);
265	if (unlikely(!skb))	265	if (unlikely(!skb))
266	return -ENOMEM;	266	return -ENOMEM;
267	skb_orphan(skb);	267	skb_orphan(skb);
@@ -282,7 +282,7 @@ int tipc_msg_build(struct tipc_msg mhdr, struct msghdr m, · 14 unmodified lines
282	msg_set_importance(&pkthdr, msg_importance(mhdr));	282	msg_set_importance(&pkthdr, msg_importance(mhdr));
283		283
284	/* Prepare first fragment */	284	/* Prepare first fragment */
285	skb = tipc_buf_acquire(pktmax);	285	skb = tipc_buf_acquire(pktmax, GFP_KERNEL);
286	if (!skb)	286	if (!skb)
287	return -ENOMEM;	287	return -ENOMEM;
288	skb_orphan(skb);	288	skb_orphan(skb);
@@ -313,7 +313,7 @@ int tipc_msg_build(struct tipc_msg mhdr, struct msghdr m, · 24 unmodified lines
313	pktsz = drem + INT_H_SIZE;	313	pktsz = drem + INT_H_SIZE;
314	else	314	else
315	pktsz = pktmax;	315	pktsz = pktmax;
316	skb = tipc_buf_acquire(pktsz);	316	skb = tipc_buf_acquire(pktsz, GFP_KERNEL);
317	if (!skb) {	317	if (!skb) {
318	rc = -ENOMEM;	318	rc = -ENOMEM;
319	goto error;	319	goto error;
@@ -448,7 +448,7 @@ bool tipc_msg_make_bundle(struct sk_buff *skb, struct tipc_msg msg, · 128 unmodified lines
448	if (msz > (max / 2))	448	if (msz > (max / 2))
449	return false;	449	return false;
450		450
451	_skb = tipc_buf_acquire(max);	451	_skb = tipc_buf_acquire(max, GFP_ATOMIC);
452	if (!_skb)	452	if (!_skb)
453	return false;	453	return false;
454		454
@@ -496,7 +496,7 @@ bool tipc_msg_reverse(u32 own_node, struct sk_buff **skb, int err) · 41 unmodified lines
496		496
497	/* Never return SHORT header; expand by replacing buffer if necessary */	497	/* Never return SHORT header; expand by replacing buffer if necessary */
498	if (msg_short(hdr)) {	498	if (msg_short(hdr)) {
499	*skb = tipc_buf_acquire(BASIC_H_SIZE + dlen);	499	*skb = tipc_buf_acquire(BASIC_H_SIZE + dlen, GFP_ATOMIC);
500	if (!*skb)	500	if (!*skb)
501	goto exit;	501	goto exit;
502	memcpy((*skb)->data + BASIC_H_SIZE, msg_data(hdr), dlen);	502	memcpy((*skb)->data + BASIC_H_SIZE, msg_data(hdr), dlen);

net/tipc/msg.h+1−1

@@ -820,7 +820,7 @@ static inline bool msg_is_reset(struct tipc_msg *hdr) · 819 unmodified lines
820	return (msg_user(hdr) == LINK_PROTOCOL) && (msg_type(hdr) == RESET_MSG);	820	return (msg_user(hdr) == LINK_PROTOCOL) && (msg_type(hdr) == RESET_MSG);
821	}	821	}
822		822
823	struct sk_buff *tipc_buf_acquire(u32 size);	823	struct sk_buff *tipc_buf_acquire(u32 size, gfp_t gfp);
824	bool tipc_msg_validate(struct sk_buff *skb);	824	bool tipc_msg_validate(struct sk_buff *skb);
825	bool tipc_msg_reverse(u32 own_addr, struct sk_buff **skb, int err);	825	bool tipc_msg_reverse(u32 own_addr, struct sk_buff **skb, int err);
826	void tipc_msg_init(u32 own_addr, struct tipc_msg *m, u32 user, u32 type,	826	void tipc_msg_init(u32 own_addr, struct tipc_msg *m, u32 user, u32 type,

net/tipc/name_distr.c+1−1

@@ -69,7 +69,7 @@ static struct sk_buff named_prepare_buf(struct net net, u32 type, u32 size, · 68 unmodified lines
69	u32 dest)	69	u32 dest)
70	{	70	{
71	struct tipc_net *tn = net_generic(net, tipc_net_id);	71	struct tipc_net *tn = net_generic(net, tipc_net_id);
72	struct sk_buff *buf = tipc_buf_acquire(INT_H_SIZE + size);	72	struct sk_buff *buf = tipc_buf_acquire(INT_H_SIZE + size, GFP_ATOMIC);
73	struct tipc_msg *msg;	73	struct tipc_msg *msg;
74		74
75	if (buf != NULL) {	75	if (buf != NULL) {

net/wireless/nl80211.c+15−0

@@ -4615,6 +4615,15 @@ int cfg80211_check_station_change(struct wiphy *wiphy, · 4614 unmodified lines
4615	break;	4615	break;
4616	}	4616	}
4617		4617
		4618	/*
		4619	* Older kernel versions ignored this attribute entirely, so don't
		4620	* reject attempts to update it but mark it as unused instead so the
		4621	* driver won't look at the data.
		4622	*/
		4623	if (statype != CFG80211_STA_AP_CLIENT_UNASSOC &&
		4624	statype != CFG80211_STA_TDLS_PEER_SETUP)
		4625	params->opmode_notif_used = false;
		4626
4618	return 0;	4627	return 0;
4619	}	4628	}
4620	EXPORT_SYMBOL(cfg80211_check_station_change);	4629	EXPORT_SYMBOL(cfg80211_check_station_change);
@@ -4854,6 +4863,12 @@ static int nl80211_set_station(struct sk_buff skb, struct genl_info info) · 233 unmodified lines
4854	params.local_pm = pm;	4863	params.local_pm = pm;
4855	}	4864	}
4856		4865
		4866	if (info->attrs[NL80211_ATTR_OPMODE_NOTIF]) {
		4867	params.opmode_notif_used = true;
		4868	params.opmode_notif =
		4869	nla_get_u8(info->attrs[NL80211_ATTR_OPMODE_NOTIF]);
		4870	}
		4871
4857	/* Include parameters for TDLS peer (will check later) */	4872	/* Include parameters for TDLS peer (will check later) */
4858	err = nl80211_set_station_tdls(info, &params);	4873	err = nl80211_set_station_tdls(info, &params);
4859	if (err)	4874	if (err)

tools/perf/util/probe-event.c+62−33

 	return ret ? : -ENOENT;
 }
+/* Adjust symbol name and address */
+static int post_process_probe_trace_point(struct probe_trace_point *tp,
+					   struct map *map, unsigned long offs)
+{
+	struct symbol *sym;
+	u64 addr = tp->address + tp->offset - offs;
+	sym = map__find_symbol(map, addr);
+	if (!sym)
+		return -ENOENT;
+	if (strcmp(sym->name, tp->symbol)) {
+		/* If we have no realname, use symbol for it */
+		if (!tp->realname)
+			tp->realname = tp->symbol;
+		else
+			free(tp->symbol);
+		tp->symbol = strdup(sym->name);
+		if (!tp->symbol)
+			return -ENOMEM;
+	}
+	tp->offset = addr - sym->start;
+	tp->address -= offs;
+	return 0;
+}
 /*
  * Rename DWARF symbols to ELF symbols -- gcc sometimes optimizes functions
  * and generate new symbols with suffixes such as .constprop.N or .isra.N
 post_process_offline_probe_trace_events(struct probe_trace_event *tevs,
 					int ntevs, const char *pathname)
 {
-	struct symbol *sym;
 	struct map *map;
 	unsigned long stext = 0;
-	u64 addr;
+	int i, ret = 0;
-	int i;
 	/* Prepare a map for offline binary */
 	map = dso__new_map(pathname);
 	}
 	for (i = 0; i < ntevs; i++) {
-		addr = tevs[i].point.address + tevs[i].point.offset - stext;
+		ret = post_process_probe_trace_point(&tevs[i].point,
-		sym = map__find_symbol(map, addr);
+						     map, stext);
-		if (!sym)
+		if (ret < 0)
-			continue;
+			break;
-		if (!strcmp(sym->name, tevs[i].point.symbol))
-			continue;
-		/* If we have no realname, use symbol for it */
-		if (!tevs[i].point.realname)
-			tevs[i].point.realname = tevs[i].point.symbol;
-		else
-			free(tevs[i].point.symbol);
-		tevs[i].point.symbol = strdup(sym->name);
-		tevs[i].point.offset = addr - sym->start;
 	}
 	map__put(map);
-	return 0;
+	return ret;
 }
 static int add_exec_to_probe_trace_events(struct probe_trace_event *tevs,
 	return ret;
 }
-static int add_module_to_probe_trace_events(struct probe_trace_event *tevs,
+static int
-					    int ntevs, const char *module)
+post_process_module_probe_trace_events(struct probe_trace_event *tevs,
+				       int ntevs, const char *module,
+				       struct debuginfo *dinfo)
 {
+	Dwarf_Addr text_offs = 0;
 	int i, ret = 0;
 	char *mod_name = NULL;
+	struct map *map;
 	if (!module)
 		return 0;
-	mod_name = find_module_name(module);
+	map = get_target_map(module, false);
+	if (!map || debuginfo__get_text_offset(dinfo, &text_offs, true) < 0) {
+		pr_warning("Failed to get ELF symbols for %s\n", module);
+		return -EINVAL;
+	}
+	mod_name = find_module_name(module);
 	for (i = 0; i < ntevs; i++) {
+		ret = post_process_probe_trace_point(&tevs[i].point,
+						map, (unsigned long)text_offs);
+		if (ret < 0)
+			break;
 		tevs[i].point.module =
 			strdup(mod_name ? mod_name : module);
 		if (!tevs[i].point.module) {
 	}
 	free(mod_name);
+	map__put(map);
 	return ret;
 }
 static int post_process_probe_trace_events(struct perf_probe_event *pev,
 					   struct probe_trace_event *tevs,
 					   int ntevs, const char *module,
-					   bool uprobe)
+					   bool uprobe, struct debuginfo *dinfo)
 {
 	int ret;
 		ret = add_exec_to_probe_trace_events(tevs, ntevs, module);
 	else if (module)
 		/* Currently ref_reloc_sym based probe is not for drivers */
-		ret = add_module_to_probe_trace_events(tevs, ntevs, module);
+		ret = post_process_module_probe_trace_events(tevs, ntevs,
+							     module, dinfo);
 	else
 		ret = post_process_kernel_probe_trace_events(tevs, ntevs);
 		}
 	}
-	debuginfo__delete(dinfo);
 	if (ntevs > 0) {	/* Succeeded to find trace events */
 		pr_debug("Found %d probe_trace_events.\n", ntevs);
 		ret = post_process_probe_trace_events(pev, *tevs, ntevs,
-						pev->target, pev->uprobes);
+					pev->target, pev->uprobes, dinfo);
 		if (ret < 0 || ret == ntevs) {
+			pr_debug("Post processing failed or all events are skipped. (%d)\n", ret);
 			clear_probe_trace_events(*tevs, ntevs);
 			zfree(tevs);
+			ntevs = 0;
 		}
-		if (ret != ntevs)
-			return ret < 0 ? ret : ntevs;
-		ntevs = 0;
-		/* Fall through */
 	}
+	debuginfo__delete(dinfo);
 	if (ntevs == 0)	{	/* No error but failed to find probe point. */
 		pr_warning("Probe point '%s' not found.\n",
 			   synthesize_perf_probe_point(&pev->point));
 		return -ENOENT;
-	}
+	} else if (ntevs < 0) {
-	/* Error path : ntevs < 0 */
+		/* Error path : ntevs < 0 */
-	pr_debug("An error occurred in debuginfo analysis (%d).\n", ntevs);
+		pr_debug("An error occurred in debuginfo analysis (%d).\n", ntevs);
-	if (ntevs < 0) {
 		if (ntevs == -EBADF)
 			pr_warning("Warning: No dwarf info found in the vmlinux - "
 				"please rebuild kernel with CONFIG_DEBUG_INFO=y.\n");

tools/perf/util/probe-finder.c+7−8

 }
 /* For the kernel module, we need a special code to get a DIE */
-static int debuginfo__get_text_offset(struct debuginfo *dbg, Dwarf_Addr *offs)
+int debuginfo__get_text_offset(struct debuginfo *dbg, Dwarf_Addr *offs,
+				bool adjust_offset)
 {
 	int n, i;
 	Elf32_Word shndx;
 			if (!shdr)
 				return -ENOENT;
 			*offs = shdr->sh_addr;
+			if (adjust_offset)
+				*offs -= shdr->sh_offset;
 		}
 	}
 	return 0;
 	Dwarf_Addr _addr = 0, baseaddr = 0;
 	const char *fname = NULL, *func = NULL, *basefunc = NULL, *tmp;
 	int baseline = 0, lineno = 0, ret = 0;
-	bool reloc = false;
-retry:
+	/* We always need to relocate the address for aranges */
+	if (debuginfo__get_text_offset(dbg, &baseaddr, false) == 0)
+		addr += baseaddr;
 	/* Find cu die */
 	if (!dwarf_addrdie(dbg->dbg, (Dwarf_Addr)addr, &cudie)) {
-		if (!reloc && debuginfo__get_text_offset(dbg, &baseaddr) == 0) {
-			addr += baseaddr;
-			reloc = true;
-			goto retry;
-		}
 		pr_warning("Failed to find debug information for address %lx\n",
 			   addr);
 		ret = -EINVAL;

tools/perf/util/probe-finder.h+3−0

@@ -46,6 +46,9 @@ int debuginfo__find_trace_events(struct debuginfo *dbg, · 45 unmodified lines
46	int debuginfo__find_probe_point(struct debuginfo *dbg, unsigned long addr,	46	int debuginfo__find_probe_point(struct debuginfo *dbg, unsigned long addr,
47	struct perf_probe_point *ppt);	47	struct perf_probe_point *ppt);
48		48
		49	int debuginfo__get_text_offset(struct debuginfo dbg, Dwarf_Addr offs,
		50	bool adjust_offset);
		51
49	/* Find a line range */	52	/* Find a line range */
50	int debuginfo__find_line_range(struct debuginfo dbg, struct line_range lr);	53	int debuginfo__find_line_range(struct debuginfo dbg, struct line_range lr);
51		54

tools/testing/selftests/powerpc/pmu/ebb/pmc56_overflow_test.c+1−1

@@ -66,7 +66,7 @@ int pmc56_overflow(void) · 65 unmodified lines
66		66
67	FAIL_IF(ebb_event_enable(&event));	67	FAIL_IF(ebb_event_enable(&event));
68		68
69	mtspr(SPRN_PMC1, pmc_sample_period(sample_period));	69	mtspr(SPRN_PMC2, pmc_sample_period(sample_period));
70	mtspr(SPRN_PMC5, 0);	70	mtspr(SPRN_PMC5, 0);
71	mtspr(SPRN_PMC6, 0);	71	mtspr(SPRN_PMC6, 0);
72		72

tools/virtio/ringtest/main.h+12−0

 #define VMEXIT_CYCLES 500
 #define VMENTRY_CYCLES 500
+#elif defined(__s390x__)
+static inline void wait_cycles(unsigned long long cycles)
+{
+	asm volatile("0: brctg %0,0b" : : "d" (cycles));
+}
+/* tweak me */
+#define VMEXIT_CYCLES 200
+#define VMENTRY_CYCLES 200
 #else
 static inline void wait_cycles(unsigned long long cycles)
 {
 /* Is there a portable way to do this? */
 #if defined(__x86_64__) || defined(__i386__)
 #define cpu_relax() asm ("rep; nop" ::: "memory")
+#elif defined(__s390x__)
+#define cpu_relax() barrier()
 #else
 #define cpu_relax() assert(0)
 #endif

tools/virtio/ringtest/run-on-all.sh+3−2

 #!/bin/sh
+CPUS_ONLINE=$(lscpu --online -p=cpu|grep -v -e '#')
 #use last CPU for host. Why not the first?
 #many devices tend to use cpu0 by default so
 #it tends to be busier
-HOST_AFFINITY=$(lscpu -p=cpu | tail -1)
+HOST_AFFINITY=$(echo "${CPUS_ONLINE}"|tail -n 1)
 #run command on all cpus
-for cpu in $(seq 0 $HOST_AFFINITY)
+for cpu in $CPUS_ONLINE
 do
 	#Don't run guest and host on same CPU
 	#It actually works ok if using signalling

virt/kvm/arm/arch_timer.c+159−62

@@ -24,6 +24,7 @@ · 23 unmodified lines
24		24
25	#include <clocksource/arm_arch_timer.h>	25	#include <clocksource/arm_arch_timer.h>
26	#include <asm/arch_timer.h>	26	#include <asm/arch_timer.h>
		27	#include <asm/kvm_hyp.h>
27		28
28	#include <kvm/arm_vgic.h>	29	#include <kvm/arm_vgic.h>
29	#include <kvm/arm_arch_timer.h>	30	#include <kvm/arm_arch_timer.h>
@@ -36,10 +37,10 @@ static u32 host_vtimer_irq_flags; · 6 unmodified lines
36		37
37	void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu)	38	void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu)
38	{	39	{
39	vcpu->arch.timer_cpu.active_cleared_last = false;	40	vcpu_vtimer(vcpu)->active_cleared_last = false;
40	}	41	}
41		42
42	static u64 kvm_phys_timer_read(void)	43	u64 kvm_phys_timer_read(void)
43	{	44	{
44	return timecounter->cc->read(timecounter->cc);	45	return timecounter->cc->read(timecounter->cc);
45	}	46	}
@@ -89,9 +90,6 @@ static void kvm_timer_inject_irq_work(struct work_struct *work) · 43 unmodified lines
89	struct kvm_vcpu *vcpu;	90	struct kvm_vcpu *vcpu;
90		91
91	vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);	92	vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
92	vcpu->arch.timer_cpu.armed = false;
93
94	WARN_ON(!kvm_timer_should_fire(vcpu));
95		93
96	/*	94	/*
97	* If the vcpu is blocked we want to wake it up so that it will see	95	* If the vcpu is blocked we want to wake it up so that it will see
@@ -100,12 +98,12 @@ static void kvm_timer_inject_irq_work(struct work_struct *work) · 2 unmodified lines
100	kvm_vcpu_kick(vcpu);	98	kvm_vcpu_kick(vcpu);
101	}	99	}
102		100
103	static u64 kvm_timer_compute_delta(struct kvm_vcpu *vcpu)	101	static u64 kvm_timer_compute_delta(struct arch_timer_context *timer_ctx)
104	{	102	{
105	u64 cval, now;	103	u64 cval, now;
106		104
107	cval = vcpu->arch.timer_cpu.cntv_cval;	105	cval = timer_ctx->cnt_cval;
108	now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;	106	now = kvm_phys_timer_read() - timer_ctx->cntvoff;
109		107
110	if (now < cval) {	108	if (now < cval) {
111	u64 ns;	109	u64 ns;
@@ -120,6 +118,35 @@ static u64 kvm_timer_compute_delta(struct kvm_vcpu *vcpu) · 8 unmodified lines
120	return 0;	118	return 0;
121	}	119	}
122		120
		121	static bool kvm_timer_irq_can_fire(struct arch_timer_context *timer_ctx)
		122	{
		123	return !(timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
		124	(timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_ENABLE);
		125	}
		126
		127	/*
		128	* Returns the earliest expiration time in ns among guest timers.
		129	* Note that it will return 0 if none of timers can fire.
		130	*/
		131	static u64 kvm_timer_earliest_exp(struct kvm_vcpu *vcpu)
		132	{
		133	u64 min_virt = ULLONG_MAX, min_phys = ULLONG_MAX;
		134	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
		135	struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
		136
		137	if (kvm_timer_irq_can_fire(vtimer))
		138	min_virt = kvm_timer_compute_delta(vtimer);
		139
		140	if (kvm_timer_irq_can_fire(ptimer))
		141	min_phys = kvm_timer_compute_delta(ptimer);
		142
		143	/* If none of timers can fire, then return 0 */
		144	if ((min_virt == ULLONG_MAX) && (min_phys == ULLONG_MAX))
		145	return 0;
		146
		147	return min(min_virt, min_phys);
		148	}
		149
123	static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)	150	static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)
124	{	151	{
125	struct arch_timer_cpu *timer;	152	struct arch_timer_cpu *timer;
@@ -134,7 +161,7 @@ static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt) · 8 unmodified lines
134	* PoV (NTP on the host may have forced it to expire	161	* PoV (NTP on the host may have forced it to expire
135	* early). If we should have slept longer, restart it.	162	* early). If we should have slept longer, restart it.
136	*/	163	*/
137	ns = kvm_timer_compute_delta(vcpu);	164	ns = kvm_timer_earliest_exp(vcpu);
138	if (unlikely(ns)) {	165	if (unlikely(ns)) {
139	hrtimer_forward_now(hrt, ns_to_ktime(ns));	166	hrtimer_forward_now(hrt, ns_to_ktime(ns));
140	return HRTIMER_RESTART;	167	return HRTIMER_RESTART;
@@ -144,42 +171,33 @@ static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt) · 3 unmodified lines
144	return HRTIMER_NORESTART;	171	return HRTIMER_NORESTART;
145	}	172	}
146		173
147	static bool kvm_timer_irq_can_fire(struct kvm_vcpu *vcpu)	174	bool kvm_timer_should_fire(struct arch_timer_context *timer_ctx)
148	{	175	{
149	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
150
151	return !(timer->cntv_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
152	(timer->cntv_ctl & ARCH_TIMER_CTRL_ENABLE);
153	}
154
155	bool kvm_timer_should_fire(struct kvm_vcpu *vcpu)
156	{
157	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
158	u64 cval, now;	176	u64 cval, now;
159		177
160	if (!kvm_timer_irq_can_fire(vcpu))	178	if (!kvm_timer_irq_can_fire(timer_ctx))
161	return false;	179	return false;
162		180
163	cval = timer->cntv_cval;	181	cval = timer_ctx->cnt_cval;
164	now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;	182	now = kvm_phys_timer_read() - timer_ctx->cntvoff;
165		183
166	return cval <= now;	184	return cval <= now;
167	}	185	}
168		186
169	static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)	187	static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level,
		188	struct arch_timer_context *timer_ctx)
170	{	189	{
171	int ret;	190	int ret;
172	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
173		191
174	BUG_ON(!vgic_initialized(vcpu->kvm));	192	BUG_ON(!vgic_initialized(vcpu->kvm));
175		193
176	timer->active_cleared_last = false;	194	timer_ctx->active_cleared_last = false;
177	timer->irq.level = new_level;	195	timer_ctx->irq.level = new_level;
178	trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->irq.irq,	196	trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq,
179	timer->irq.level);	197	timer_ctx->irq.level);
180	ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,	198
181	timer->irq.irq,	199	ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, timer_ctx->irq.irq,
182	timer->irq.level);	200	timer_ctx->irq.level);
183	WARN_ON(ret);	201	WARN_ON(ret);
184	}	202	}
185		203
@@ -190,22 +208,43 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level) · 4 unmodified lines
190	static int kvm_timer_update_state(struct kvm_vcpu *vcpu)	208	static int kvm_timer_update_state(struct kvm_vcpu *vcpu)
191	{	209	{
192	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	210	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
		211	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
		212	struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
193		213
194	/*	214	/*
195	* If userspace modified the timer registers via SET_ONE_REG before	215	* If userspace modified the timer registers via SET_ONE_REG before
196	* the vgic was initialized, we mustn't set the timer->irq.level value	216	* the vgic was initialized, we mustn't set the vtimer->irq.level value
197	* because the guest would never see the interrupt. Instead wait	217	* because the guest would never see the interrupt. Instead wait
198	* until we call this function from kvm_timer_flush_hwstate.	218	* until we call this function from kvm_timer_flush_hwstate.
199	*/	219	*/
200	if (!vgic_initialized(vcpu->kvm) \|\| !timer->enabled)	220	if (!vgic_initialized(vcpu->kvm) \|\| !timer->enabled)
201	return -ENODEV;	221	return -ENODEV;
202		222
203	if (kvm_timer_should_fire(vcpu) != timer->irq.level)	223	if (kvm_timer_should_fire(vtimer) != vtimer->irq.level)
204	kvm_timer_update_irq(vcpu, !timer->irq.level);	224	kvm_timer_update_irq(vcpu, !vtimer->irq.level, vtimer);
		225
		226	if (kvm_timer_should_fire(ptimer) != ptimer->irq.level)
		227	kvm_timer_update_irq(vcpu, !ptimer->irq.level, ptimer);
205		228
206	return 0;	229	return 0;
207	}	230	}
208		231
		232	/* Schedule the background timer for the emulated timer. */
		233	static void kvm_timer_emulate(struct kvm_vcpu *vcpu,
		234	struct arch_timer_context *timer_ctx)
		235	{
		236	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
		237
		238	if (kvm_timer_should_fire(timer_ctx))
		239	return;
		240
		241	if (!kvm_timer_irq_can_fire(timer_ctx))
		242	return;
		243
		244	/* The timer has not yet expired, schedule a background timer */
		245	timer_arm(timer, kvm_timer_compute_delta(timer_ctx));
		246	}
		247
209	/*	248	/*
210	* Schedule the background timer before calling kvm_vcpu_block, so that this	249	* Schedule the background timer before calling kvm_vcpu_block, so that this
211	* thread is removed from its waitqueue and made runnable when there's a timer	250	* thread is removed from its waitqueue and made runnable when there's a timer
@@ -214,26 +253,31 @@ static int kvm_timer_update_state(struct kvm_vcpu *vcpu) · 2 unmodified lines
214	void kvm_timer_schedule(struct kvm_vcpu *vcpu)	253	void kvm_timer_schedule(struct kvm_vcpu *vcpu)
215	{	254	{
216	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	255	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
		256	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
		257	struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
217		258
218	BUG_ON(timer_is_armed(timer));	259	BUG_ON(timer_is_armed(timer));
219		260
220	/*	261	/*
221	* No need to schedule a background timer if the guest timer has	262	* No need to schedule a background timer if any guest timer has
222	* already expired, because kvm_vcpu_block will return before putting	263	* already expired, because kvm_vcpu_block will return before putting
223	* the thread to sleep.	264	* the thread to sleep.
224	*/	265	*/
225	if (kvm_timer_should_fire(vcpu))	266	if (kvm_timer_should_fire(vtimer) \|\| kvm_timer_should_fire(ptimer))
226	return;	267	return;
227		268
228	/*	269	/*
229	* If the timer is not capable of raising interrupts (disabled or	270	* If both timers are not capable of raising interrupts (disabled or
230	* masked), then there's no more work for us to do.	271	* masked), then there's no more work for us to do.
231	*/	272	*/
232	if (!kvm_timer_irq_can_fire(vcpu))	273	if (!kvm_timer_irq_can_fire(vtimer) && !kvm_timer_irq_can_fire(ptimer))
233	return;	274	return;
234		275
235	/* The timer has not yet expired, schedule a background timer */	276	/*
236	timer_arm(timer, kvm_timer_compute_delta(vcpu));	277	* The guest timers have not yet expired, schedule a background timer.
		278	* Set the earliest expiration time among the guest timers.
		279	*/
		280	timer_arm(timer, kvm_timer_earliest_exp(vcpu));
237	}	281	}
238		282
239	void kvm_timer_unschedule(struct kvm_vcpu *vcpu)	283	void kvm_timer_unschedule(struct kvm_vcpu *vcpu)
@@ -251,13 +295,16 @@ void kvm_timer_unschedule(struct kvm_vcpu *vcpu) · 11 unmodified lines
251	*/	295	*/
252	void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)	296	void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
253	{	297	{
254	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	298	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
255	bool phys_active;	299	bool phys_active;
256	int ret;	300	int ret;
257		301
258	if (kvm_timer_update_state(vcpu))	302	if (kvm_timer_update_state(vcpu))
259	return;	303	return;
260		304
		305	/* Set the background timer for the physical timer emulation. */
		306	kvm_timer_emulate(vcpu, vcpu_ptimer(vcpu));
		307
261	/*	308	/*
262	* If we enter the guest with the virtual input level to the VGIC	309	* If we enter the guest with the virtual input level to the VGIC
263	* asserted, then we have already told the VGIC what we need to, and	310	* asserted, then we have already told the VGIC what we need to, and
@@ -275,8 +322,8 @@ void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) · 11 unmodified lines
275	* to ensure that hardware interrupts from the timer triggers a guest	322	* to ensure that hardware interrupts from the timer triggers a guest
276	* exit.	323	* exit.
277	*/	324	*/
278	phys_active = timer->irq.level \|\|	325	phys_active = vtimer->irq.level \|\|
279	kvm_vgic_map_is_active(vcpu, timer->irq.irq);	326	kvm_vgic_map_is_active(vcpu, vtimer->irq.irq);
280		327
281	/*	328	/*
282	* We want to avoid hitting the (re)distributor as much as	329	* We want to avoid hitting the (re)distributor as much as
@@ -298,7 +345,7 @@ void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) · 15 unmodified lines
298	* - cached value is "active clear"	345	* - cached value is "active clear"
299	* - value to be programmed is "active clear"	346	* - value to be programmed is "active clear"
300	*/	347	*/
301	if (timer->active_cleared_last && !phys_active)	348	if (vtimer->active_cleared_last && !phys_active)
302	return;	349	return;
303		350
304	ret = irq_set_irqchip_state(host_vtimer_irq,	351	ret = irq_set_irqchip_state(host_vtimer_irq,
@@ -306,7 +353,7 @@ void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) · 1 unmodified line
306	phys_active);	353	phys_active);
307	WARN_ON(ret);	354	WARN_ON(ret);
308		355
309	timer->active_cleared_last = !phys_active;	356	vtimer->active_cleared_last = !phys_active;
310	}	357	}
311		358
312	/**	359	/**
@@ -320,7 +367,11 @@ void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) · 7 unmodified lines
320	{	367	{
321	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	368	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
322		369
323	BUG_ON(timer_is_armed(timer));	370	/*
		371	* This is to cancel the background timer for the physical timer
		372	* emulation if it is set.
		373	*/
		374	timer_disarm(timer);
324		375
325	/*	376	/*
326	* The guest could have modified the timer registers or the timer	377	* The guest could have modified the timer registers or the timer
@@ -330,9 +381,11 @@ void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) · 3 unmodified lines
330	}	381	}
331		382
332	int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,	383	int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
333	const struct kvm_irq_level *irq)	384	const struct kvm_irq_level *virt_irq,
		385	const struct kvm_irq_level *phys_irq)
334	{	386	{
335	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	387	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
		388	struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
336		389
337	/*	390	/*
338	* The vcpu timer irq number cannot be determined in	391	* The vcpu timer irq number cannot be determined in
@@ -340,7 +393,8 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu, · 1 unmodified line
340	* kvm_vcpu_set_target(). To handle this, we determine	393	* kvm_vcpu_set_target(). To handle this, we determine
341	* vcpu timer irq number when the vcpu is reset.	394	* vcpu timer irq number when the vcpu is reset.
342	*/	395	*/
343	timer->irq.irq = irq->irq;	396	vtimer->irq.irq = virt_irq->irq;
		397	ptimer->irq.irq = phys_irq->irq;
344		398
345	/*	399	/*
346	* The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8	400	* The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8
@@ -348,16 +402,40 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu, · 1 unmodified line
348	* resets the timer to be disabled and unmasked and is compliant with	402	* resets the timer to be disabled and unmasked and is compliant with
349	* the ARMv7 architecture.	403	* the ARMv7 architecture.
350	*/	404	*/
351	timer->cntv_ctl = 0;	405	vtimer->cnt_ctl = 0;
		406	ptimer->cnt_ctl = 0;
352	kvm_timer_update_state(vcpu);	407	kvm_timer_update_state(vcpu);
353		408
354	return 0;	409	return 0;
355	}	410	}
356		411
		412	/* Make the updates of cntvoff for all vtimer contexts atomic */
		413	static void update_vtimer_cntvoff(struct kvm_vcpu *vcpu, u64 cntvoff)
		414	{
		415	int i;
		416	struct kvm *kvm = vcpu->kvm;
		417	struct kvm_vcpu *tmp;
		418
		419	mutex_lock(&kvm->lock);
		420	kvm_for_each_vcpu(i, tmp, kvm)
		421	vcpu_vtimer(tmp)->cntvoff = cntvoff;
		422
		423	/*
		424	* When called from the vcpu create path, the CPU being created is not
		425	* included in the loop above, so we just set it here as well.
		426	*/
		427	vcpu_vtimer(vcpu)->cntvoff = cntvoff;
		428	mutex_unlock(&kvm->lock);
		429	}
		430
357	void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)	431	void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
358	{	432	{
359	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	433	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
360		434
		435	/* Synchronize cntvoff across all vtimers of a VM. */
		436	update_vtimer_cntvoff(vcpu, kvm_phys_timer_read());
		437	vcpu_ptimer(vcpu)->cntvoff = 0;
		438
361	INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);	439	INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);
362	hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);	440	hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
363	timer->timer.function = kvm_timer_expire;	441	timer->timer.function = kvm_timer_expire;
@@ -370,17 +448,17 @@ static void kvm_timer_init_interrupt(void *info) · 6 unmodified lines
370		448
371	int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value)	449	int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value)
372	{	450	{
373	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	451	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
374		452
375	switch (regid) {	453	switch (regid) {
376	case KVM_REG_ARM_TIMER_CTL:	454	case KVM_REG_ARM_TIMER_CTL:
377	timer->cntv_ctl = value;	455	vtimer->cnt_ctl = value;
378	break;	456	break;
379	case KVM_REG_ARM_TIMER_CNT:	457	case KVM_REG_ARM_TIMER_CNT:
380	vcpu->kvm->arch.timer.cntvoff = kvm_phys_timer_read() - value;	458	update_vtimer_cntvoff(vcpu, kvm_phys_timer_read() - value);
381	break;	459	break;
382	case KVM_REG_ARM_TIMER_CVAL:	460	case KVM_REG_ARM_TIMER_CVAL:
383	timer->cntv_cval = value;	461	vtimer->cnt_cval = value;
384	break;	462	break;
385	default:	463	default:
386	return -1;	464	return -1;
@@ -392,15 +470,15 @@ int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value) · 5 unmodified lines
392		470
393	u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid)	471	u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid)
394	{	472	{
395	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	473	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
396		474
397	switch (regid) {	475	switch (regid) {
398	case KVM_REG_ARM_TIMER_CTL:	476	case KVM_REG_ARM_TIMER_CTL:
399	return timer->cntv_ctl;	477	return vtimer->cnt_ctl;
400	case KVM_REG_ARM_TIMER_CNT:	478	case KVM_REG_ARM_TIMER_CNT:
401	return kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;	479	return kvm_phys_timer_read() - vtimer->cntvoff;
402	case KVM_REG_ARM_TIMER_CVAL:	480	case KVM_REG_ARM_TIMER_CVAL:
403	return timer->cntv_cval;	481	return vtimer->cnt_cval;
404	}	482	}
405	return (u64)-1;	483	return (u64)-1;
406	}	484	}
@@ -464,14 +542,16 @@ int kvm_timer_hyp_init(void) · 57 unmodified lines
464	void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)	542	void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)
465	{	543	{
466	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	544	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
		545	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
467		546
468	timer_disarm(timer);	547	timer_disarm(timer);
469	kvm_vgic_unmap_phys_irq(vcpu, timer->irq.irq);	548	kvm_vgic_unmap_phys_irq(vcpu, vtimer->irq.irq);
470	}	549	}
471		550
472	int kvm_timer_enable(struct kvm_vcpu *vcpu)	551	int kvm_timer_enable(struct kvm_vcpu *vcpu)
473	{	552	{
474	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;	553	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
		554	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
475	struct irq_desc *desc;	555	struct irq_desc *desc;
476	struct irq_data *data;	556	struct irq_data *data;
477	int phys_irq;	557	int phys_irq;
@@ -499,7 +579,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) · 21 unmodified lines
499	* Tell the VGIC that the virtual interrupt is tied to a	579	* Tell the VGIC that the virtual interrupt is tied to a
500	* physical interrupt. We do that once per VCPU.	580	* physical interrupt. We do that once per VCPU.
501	*/	581	*/
502	ret = kvm_vgic_map_phys_irq(vcpu, timer->irq.irq, phys_irq);	582	ret = kvm_vgic_map_phys_irq(vcpu, vtimer->irq.irq, phys_irq);
503	if (ret)	583	if (ret)
504	return ret;	584	return ret;
505		585
@@ -508,7 +588,24 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) · 2 unmodified lines
508	return 0;	588	return 0;
509	}	589	}
510		590
511	void kvm_timer_init(struct kvm *kvm)	591	/*
		592	* On VHE system, we only need to configure trap on physical timer and counter
		593	* accesses in EL0 and EL1 once, not for every world switch.
		594	* The host kernel runs at EL2 with HCR_EL2.TGE == 1,
		595	* and this makes those bits have no effect for the host kernel execution.
		596	*/
		597	void kvm_timer_init_vhe(void)
512	{	598	{
513	kvm->arch.timer.cntvoff = kvm_phys_timer_read();	599	/* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */
		600	u32 cnthctl_shift = 10;
		601	u64 val;
		602
		603	/*
		604	* Disallow physical timer access for the guest.
		605	* Physical counter access is allowed.
		606	*/
		607	val = read_sysreg(cnthctl_el2);
		608	val &= ~(CNTHCTL_EL1PCEN << cnthctl_shift);
		609	val \|= (CNTHCTL_EL1PCTEN << cnthctl_shift);
		610	write_sysreg(val, cnthctl_el2);
514	}	611	}

virt/kvm/arm/hyp/timer-sr.c+28−18

 void __hyp_text __timer_save_state(struct kvm_vcpu *vcpu)
 {
 	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
 	u64 val;
 	if (timer->enabled) {
-		timer->cntv_ctl = read_sysreg_el0(cntv_ctl);
+		vtimer->cnt_ctl = read_sysreg_el0(cntv_ctl);
-		timer->cntv_cval = read_sysreg_el0(cntv_cval);
+		vtimer->cnt_cval = read_sysreg_el0(cntv_cval);
 	}
 	/* Disable the virtual timer */
 	write_sysreg_el0(0, cntv_ctl);
-	/* Allow physical timer/counter access for the host */
+	/*
-	val = read_sysreg(cnthctl_el2);
+	 * We don't need to do this for VHE since the host kernel runs in EL2
-	val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
+	 * with HCR_EL2.TGE ==1, which makes those bits have no impact.
-	write_sysreg(val, cnthctl_el2);
+	 */
+	if (!has_vhe()) {
+		/* Allow physical timer/counter access for the host */
+		val = read_sysreg(cnthctl_el2);
+		val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
+		write_sysreg(val, cnthctl_el2);
+	}
 	/* Clear cntvoff for the host */
 	write_sysreg(0, cntvoff_el2);
 void __hyp_text __timer_restore_state(struct kvm_vcpu *vcpu)
 {
-	struct kvm *kvm = kern_hyp_va(vcpu->kvm);
 	struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+	struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
 	u64 val;
-	/*
+	/* Those bits are already configured at boot on VHE-system */
-	 * Disallow physical timer access for the guest
+	if (!has_vhe()) {
-	 * Physical counter access is allowed
+		/*
-	 */
+		 * Disallow physical timer access for the guest
-	val = read_sysreg(cnthctl_el2);
+		 * Physical counter access is allowed
-	val &= ~CNTHCTL_EL1PCEN;
+		 */
-	val |= CNTHCTL_EL1PCTEN;
+		val = read_sysreg(cnthctl_el2);
-	write_sysreg(val, cnthctl_el2);
+		val &= ~CNTHCTL_EL1PCEN;
+		val |= CNTHCTL_EL1PCTEN;
+		write_sysreg(val, cnthctl_el2);
+	}
 	if (timer->enabled) {
-		write_sysreg(kvm->arch.timer.cntvoff, cntvoff_el2);
+		write_sysreg(vtimer->cntvoff, cntvoff_el2);
-		write_sysreg_el0(timer->cntv_cval, cntv_cval);
+		write_sysreg_el0(vtimer->cnt_cval, cntv_cval);
 		isb();
-		write_sysreg_el0(timer->cntv_ctl, cntv_ctl);
+		write_sysreg_el0(vtimer->cnt_ctl, cntv_ctl);
 	}
 }

virt/kvm/arm/vgic/vgic-debug.c+283−0

@@ -0,0 +1,283 @@
	1	/*
	2	* Copyright (C) 2016 Linaro
	3	* Author: Christoffer Dall <christoffer.dall@linaro.org>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#include <linux/cpu.h>
	19	#include <linux/debugfs.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/kvm_host.h>
	22	#include <linux/seq_file.h>
	23	#include <kvm/arm_vgic.h>
	24	#include <asm/kvm_mmu.h>
	25	#include "vgic.h"
	26
	27	/*
	28	* Structure to control looping through the entire vgic state. We start at
	29	* zero for each field and move upwards. So, if dist_id is 0 we print the
	30	* distributor info. When dist_id is 1, we have already printed it and move
	31	* on.
	32	*
	33	* When vcpu_id < nr_cpus we print the vcpu info until vcpu_id == nr_cpus and
	34	* so on.
	35	*/
	36	struct vgic_state_iter {
	37	int nr_cpus;
	38	int nr_spis;
	39	int dist_id;
	40	int vcpu_id;
	41	int intid;
	42	};
	43
	44	static void iter_next(struct vgic_state_iter *iter)
	45	{
	46	if (iter->dist_id == 0) {
	47	iter->dist_id++;
	48	return;
	49	}
	50
	51	iter->intid++;
	52	if (iter->intid == VGIC_NR_PRIVATE_IRQS &&
	53	++iter->vcpu_id < iter->nr_cpus)
	54	iter->intid = 0;
	55	}
	56
	57	static void iter_init(struct kvm kvm, struct vgic_state_iter iter,
	58	loff_t pos)
	59	{
	60	int nr_cpus = atomic_read(&kvm->online_vcpus);
	61
	62	memset(iter, 0, sizeof(*iter));
	63
	64	iter->nr_cpus = nr_cpus;
	65	iter->nr_spis = kvm->arch.vgic.nr_spis;
	66
	67	/* Fast forward to the right position if needed */
	68	while (pos--)
	69	iter_next(iter);
	70	}
	71
	72	static bool end_of_vgic(struct vgic_state_iter *iter)
	73	{
	74	return iter->dist_id > 0 &&
	75	iter->vcpu_id == iter->nr_cpus &&
	76	(iter->intid - VGIC_NR_PRIVATE_IRQS) == iter->nr_spis;
	77	}
	78
	79	static void vgic_debug_start(struct seq_file s, loff_t *pos)
	80	{
	81	struct kvm kvm = (struct kvm )s->private;
	82	struct vgic_state_iter *iter;
	83
	84	mutex_lock(&kvm->lock);
	85	iter = kvm->arch.vgic.iter;
	86	if (iter) {
	87	iter = ERR_PTR(-EBUSY);
	88	goto out;
	89	}
	90
	91	iter = kmalloc(sizeof(*iter), GFP_KERNEL);
	92	if (!iter) {
	93	iter = ERR_PTR(-ENOMEM);
	94	goto out;
	95	}
	96
	97	iter_init(kvm, iter, *pos);
	98	kvm->arch.vgic.iter = iter;
	99
	100	if (end_of_vgic(iter))
	101	iter = NULL;
	102	out:
	103	mutex_unlock(&kvm->lock);
	104	return iter;
	105	}
	106
	107	static void vgic_debug_next(struct seq_file s, void v, loff_t pos)
	108	{
	109	struct kvm kvm = (struct kvm )s->private;
	110	struct vgic_state_iter *iter = kvm->arch.vgic.iter;
	111
	112	++*pos;
	113	iter_next(iter);
	114	if (end_of_vgic(iter))
	115	iter = NULL;
	116	return iter;
	117	}
	118
	119	static void vgic_debug_stop(struct seq_file s, void v)
	120	{
	121	struct kvm kvm = (struct kvm )s->private;
	122	struct vgic_state_iter *iter;
	123
	124	/*
	125	* If the seq file wasn't properly opened, there's nothing to clearn
	126	* up.
	127	*/
	128	if (IS_ERR(v))
	129	return;
	130
	131	mutex_lock(&kvm->lock);
	132	iter = kvm->arch.vgic.iter;
	133	kfree(iter);
	134	kvm->arch.vgic.iter = NULL;
	135	mutex_unlock(&kvm->lock);
	136	}
	137
	138	static void print_dist_state(struct seq_file s, struct vgic_dist dist)
	139	{
	140	seq_printf(s, "Distributor\n");
	141	seq_printf(s, "===========\n");
	142	seq_printf(s, "vgic_model:\t%s\n",
	143	(dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) ?
	144	"GICv3" : "GICv2");
	145	seq_printf(s, "nr_spis:\t%d\n", dist->nr_spis);
	146	seq_printf(s, "enabled:\t%d\n", dist->enabled);
	147	seq_printf(s, "\n");
	148
	149	seq_printf(s, "P=pending_latch, L=line_level, A=active\n");
	150	seq_printf(s, "E=enabled, H=hw, C=config (level=1, edge=0)\n");
	151	}
	152
	153	static void print_header(struct seq_file s, struct vgic_irq irq,
	154	struct kvm_vcpu *vcpu)
	155	{
	156	int id = 0;
	157	char *hdr = "SPI ";
	158
	159	if (vcpu) {
	160	hdr = "VCPU";
	161	id = vcpu->vcpu_id;
	162	}
	163
	164	seq_printf(s, "\n");
	165	seq_printf(s, "%s%2d TYP ID TGT_ID PLAEHC HWID TARGET SRC PRI VCPU_ID\n", hdr, id);
	166	seq_printf(s, "---------------------------------------------------------------\n");
	167	}
	168
	169	static void print_irq_state(struct seq_file s, struct vgic_irq irq,
	170	struct kvm_vcpu *vcpu)
	171	{
	172	char *type;
	173	if (irq->intid < VGIC_NR_SGIS)
	174	type = "SGI";
	175	else if (irq->intid < VGIC_NR_PRIVATE_IRQS)
	176	type = "PPI";
	177	else
	178	type = "SPI";
	179
	180	if (irq->intid ==0 \|\| irq->intid == VGIC_NR_PRIVATE_IRQS)
	181	print_header(s, irq, vcpu);
	182
	183	seq_printf(s, " %s %4d "
	184	" %2d "
	185	"%d%d%d%d%d%d "
	186	"%8d "
	187	"%8x "
	188	" %2x "
	189	"%3d "
	190	" %2d "
	191	"\n",
	192	type, irq->intid,
	193	(irq->target_vcpu) ? irq->target_vcpu->vcpu_id : -1,
	194	irq->pending_latch,
	195	irq->line_level,
	196	irq->active,
	197	irq->enabled,
	198	irq->hw,
	199	irq->config == VGIC_CONFIG_LEVEL,
	200	irq->hwintid,
	201	irq->mpidr,
	202	irq->source,
	203	irq->priority,
	204	(irq->vcpu) ? irq->vcpu->vcpu_id : -1);
	205
	206	}
	207
	208	static int vgic_debug_show(struct seq_file s, void v)
	209	{
	210	struct kvm kvm = (struct kvm )s->private;
	211	struct vgic_state_iter iter = (struct vgic_state_iter )v;
	212	struct vgic_irq *irq;
	213	struct kvm_vcpu *vcpu = NULL;
	214
	215	if (iter->dist_id == 0) {
	216	print_dist_state(s, &kvm->arch.vgic);
	217	return 0;
	218	}
	219
	220	if (!kvm->arch.vgic.initialized)
	221	return 0;
	222
	223	if (iter->vcpu_id < iter->nr_cpus) {
	224	vcpu = kvm_get_vcpu(kvm, iter->vcpu_id);
	225	irq = &vcpu->arch.vgic_cpu.private_irqs[iter->intid];
	226	} else {
	227	irq = &kvm->arch.vgic.spis[iter->intid - VGIC_NR_PRIVATE_IRQS];
	228	}
	229
	230	spin_lock(&irq->irq_lock);
	231	print_irq_state(s, irq, vcpu);
	232	spin_unlock(&irq->irq_lock);
	233
	234	return 0;
	235	}
	236
	237	static struct seq_operations vgic_debug_seq_ops = {
	238	.start = vgic_debug_start,
	239	.next = vgic_debug_next,
	240	.stop = vgic_debug_stop,
	241	.show = vgic_debug_show
	242	};
	243
	244	static int debug_open(struct inode inode, struct file file)
	245	{
	246	int ret;
	247	ret = seq_open(file, &vgic_debug_seq_ops);
	248	if (!ret) {
	249	struct seq_file *seq;
	250	/* seq_open will have modified file->private_data */
	251	seq = file->private_data;
	252	seq->private = inode->i_private;
	253	}
	254
	255	return ret;
	256	};
	257
	258	static struct file_operations vgic_debug_fops = {
	259	.owner = THIS_MODULE,
	260	.open = debug_open,
	261	.read = seq_read,
	262	.llseek = seq_lseek,
	263	.release = seq_release
	264	};
	265
	266	int vgic_debug_init(struct kvm *kvm)
	267	{
	268	if (!kvm->debugfs_dentry)
	269	return -ENOENT;
	270
	271	if (!debugfs_create_file("vgic-state", 0444,
	272	kvm->debugfs_dentry,
	273	kvm,
	274	&vgic_debug_fops))
	275	return -ENOMEM;
	276
	277	return 0;
	278	}
	279
	280	int vgic_debug_destroy(struct kvm *kvm)
	281	{
	282	return 0;
	283	}

virt/kvm/arm/vgic/vgic-init.c+17−5

 	if (ret)
 		goto out;
+	vgic_debug_init(kvm);
 	dist->initialized = true;
 out:
 	return ret;
 {
 	struct vgic_dist *dist = &kvm->arch.vgic;
-	mutex_lock(&kvm->lock);
 	dist->ready = false;
 	dist->initialized = false;
 	kfree(dist->spis);
 	dist->nr_spis = 0;
-	mutex_unlock(&kvm->lock);
 }
 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
 	INIT_LIST_HEAD(&vgic_cpu->ap_list_head);
 }
-void kvm_vgic_destroy(struct kvm *kvm)
+/* To be called with kvm->lock held */
+static void __kvm_vgic_destroy(struct kvm *kvm)
 {
 	struct kvm_vcpu *vcpu;
 	int i;
+	vgic_debug_destroy(kvm);
 	kvm_vgic_dist_destroy(kvm);
 	kvm_for_each_vcpu(i, vcpu, kvm)
 		kvm_vgic_vcpu_destroy(vcpu);
 }
+void kvm_vgic_destroy(struct kvm *kvm)
+{
+	mutex_lock(&kvm->lock);
+	__kvm_vgic_destroy(kvm);
+	mutex_unlock(&kvm->lock);
+}
 /**
  * vgic_lazy_init: Lazy init is only allowed if the GIC exposed to the guest
  * is a GICv2. A GICv3 must be explicitly initialized by the guest using the
 		ret = vgic_v2_map_resources(kvm);
 	else
 		ret = vgic_v3_map_resources(kvm);
+	if (ret)
+		__kvm_vgic_destroy(kvm);
 out:
 	mutex_unlock(&kvm->lock);
 	return ret;

virt/kvm/arm/vgic/vgic-irqfd.c+3−0

@@ -99,6 +99,9 @@ int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, · 98 unmodified lines
99	if (!vgic_has_its(kvm))	99	if (!vgic_has_its(kvm))
100	return -ENODEV;	100	return -ENODEV;
101		101
		102	if (!level)
		103	return -1;
		104
102	return vgic_its_inject_msi(kvm, &msi);	105	return vgic_its_inject_msi(kvm, &msi);
103	}	106	}
104		107

virt/kvm/arm/vgic/vgic-its.c+3−3

@@ -350,7 +350,7 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu) · 349 unmodified lines
350		350
351	irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);	351	irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
352	spin_lock(&irq->irq_lock);	352	spin_lock(&irq->irq_lock);
353	irq->pending = pendmask & (1U << bit_nr);	353	irq->pending_latch = pendmask & (1U << bit_nr);
354	vgic_queue_irq_unlock(vcpu->kvm, irq);	354	vgic_queue_irq_unlock(vcpu->kvm, irq);
355	vgic_put_irq(vcpu->kvm, irq);	355	vgic_put_irq(vcpu->kvm, irq);
356	}	356	}
@@ -465,7 +465,7 @@ static int vgic_its_trigger_msi(struct kvm kvm, struct vgic_its its, · 108 unmodified lines
465	return -EBUSY;	465	return -EBUSY;
466		466
467	spin_lock(&itte->irq->irq_lock);	467	spin_lock(&itte->irq->irq_lock);
468	itte->irq->pending = true;	468	itte->irq->pending_latch = true;
469	vgic_queue_irq_unlock(kvm, itte->irq);	469	vgic_queue_irq_unlock(kvm, itte->irq);
470		470
471	return 0;	471	return 0;
@@ -913,7 +913,7 @@ static int vgic_its_cmd_handle_clear(struct kvm kvm, struct vgic_its its, · 441 unmodified lines
913	if (!itte)	913	if (!itte)
914	return E_ITS_CLEAR_UNMAPPED_INTERRUPT;	914	return E_ITS_CLEAR_UNMAPPED_INTERRUPT;
915		915
916	itte->irq->pending = false;	916	itte->irq->pending_latch = false;
917		917
918	return 0;	918	return 0;
919	}	919	}

virt/kvm/arm/vgic/vgic-kvm-device.c+216−15

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	#include <kvm/arm_vgic.h>	17	#include <kvm/arm_vgic.h>
18	#include <linux/uaccess.h>	18	#include <linux/uaccess.h>
19	#include <asm/kvm_mmu.h>	19	#include <asm/kvm_mmu.h>
		20	#include <asm/cputype.h>
20	#include "vgic.h"	21	#include "vgic.h"
21		22
22	/* common helpers */	23	/* common helpers */
@@ -230,14 +231,8 @@ int kvm_register_vgic_device(unsigned long type) · 207 unmodified lines
230	return ret;	231	return ret;
231	}	232	}
232		233
233	struct vgic_reg_attr {	234	int vgic_v2_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
234	struct kvm_vcpu *vcpu;	235	struct vgic_reg_attr *reg_attr)
235	gpa_t addr;
236	};
237
238	static int parse_vgic_v2_attr(struct kvm_device *dev,
239	struct kvm_device_attr *attr,
240	struct vgic_reg_attr *reg_attr)
241	{	236	{
242	int cpuid;	237	int cpuid;
243		238
@@ -292,14 +287,14 @@ static bool lock_all_vcpus(struct kvm *kvm) · 48 unmodified lines
292	}	287	}
293		288
294	/**	289	/**
295	* vgic_attr_regs_access_v2 - allows user space to access VGIC v2 state	290	* vgic_v2_attr_regs_access - allows user space to access VGIC v2 state
296	*	291	*
297	* @dev: kvm device handle	292	* @dev: kvm device handle
298	* @attr: kvm device attribute	293	* @attr: kvm device attribute
299	* @reg: address the value is read or written	294	* @reg: address the value is read or written
300	* @is_write: true if userspace is writing a register	295	* @is_write: true if userspace is writing a register
301	*/	296	*/
302	static int vgic_attr_regs_access_v2(struct kvm_device *dev,	297	static int vgic_v2_attr_regs_access(struct kvm_device *dev,
303	struct kvm_device_attr *attr,	298	struct kvm_device_attr *attr,
304	u32 *reg, bool is_write)	299	u32 *reg, bool is_write)
305	{	300	{
@@ -308,7 +303,7 @@ static int vgic_attr_regs_access_v2(struct kvm_device *dev, · 2 unmodified lines
308	struct kvm_vcpu *vcpu;	303	struct kvm_vcpu *vcpu;
309	int ret;	304	int ret;
310		305
311	ret = parse_vgic_v2_attr(dev, attr, &reg_attr);	306	ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
312	if (ret)	307	if (ret)
313	return ret;	308	return ret;
314		309
@@ -362,7 +357,7 @@ static int vgic_v2_set_attr(struct kvm_device *dev, · 47 unmodified lines
362	if (get_user(reg, uaddr))	357	if (get_user(reg, uaddr))
363	return -EFAULT;	358	return -EFAULT;
364		359
365	return vgic_attr_regs_access_v2(dev, attr, &reg, true);	360	return vgic_v2_attr_regs_access(dev, attr, &reg, true);
366	}	361	}
367	}	362	}
368		363
@@ -384,7 +379,7 @@ static int vgic_v2_get_attr(struct kvm_device *dev, · 15 unmodified lines
384	u32 __user uaddr = (u32 __user )(long)attr->addr;	379	u32 __user uaddr = (u32 __user )(long)attr->addr;
385	u32 reg = 0;	380	u32 reg = 0;
386		381
387	ret = vgic_attr_regs_access_v2(dev, attr, &reg, false);	382	ret = vgic_v2_attr_regs_access(dev, attr, &reg, false);
388	if (ret)	383	if (ret)
389	return ret;	384	return ret;
390	return put_user(reg, uaddr);	385	return put_user(reg, uaddr);
@@ -428,16 +423,211 @@ struct kvm_device_ops kvm_arm_vgic_v2_ops = { · 37 unmodified lines
428	.has_attr = vgic_v2_has_attr,	423	.has_attr = vgic_v2_has_attr,
429	};	424	};
430		425
		426	int vgic_v3_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
		427	struct vgic_reg_attr *reg_attr)
		428	{
		429	unsigned long vgic_mpidr, mpidr_reg;
		430
		431	/*
		432	* For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
		433	* attr might not hold MPIDR. Hence assume vcpu0.
		434	*/
		435	if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
		436	vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
		437	KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
		438
		439	mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
		440	reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
		441	} else {
		442	reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
		443	}
		444
		445	if (!reg_attr->vcpu)
		446	return -EINVAL;
		447
		448	reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
		449
		450	return 0;
		451	}
		452
		453	/*
		454	* vgic_v3_attr_regs_access - allows user space to access VGIC v3 state
		455	*
		456	* @dev: kvm device handle
		457	* @attr: kvm device attribute
		458	* @reg: address the value is read or written
		459	* @is_write: true if userspace is writing a register
		460	*/
		461	static int vgic_v3_attr_regs_access(struct kvm_device *dev,
		462	struct kvm_device_attr *attr,
		463	u64 *reg, bool is_write)
		464	{
		465	struct vgic_reg_attr reg_attr;
		466	gpa_t addr;
		467	struct kvm_vcpu *vcpu;
		468	int ret;
		469	u32 tmp32;
		470
		471	ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
		472	if (ret)
		473	return ret;
		474
		475	vcpu = reg_attr.vcpu;
		476	addr = reg_attr.addr;
		477
		478	mutex_lock(&dev->kvm->lock);
		479
		480	if (unlikely(!vgic_initialized(dev->kvm))) {
		481	ret = -EBUSY;
		482	goto out;
		483	}
		484
		485	if (!lock_all_vcpus(dev->kvm)) {
		486	ret = -EBUSY;
		487	goto out;
		488	}
		489
		490	switch (attr->group) {
		491	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
		492	if (is_write)
		493	tmp32 = *reg;
		494
		495	ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &tmp32);
		496	if (!is_write)
		497	*reg = tmp32;
		498	break;
		499	case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
		500	if (is_write)
		501	tmp32 = *reg;
		502
		503	ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &tmp32);
		504	if (!is_write)
		505	*reg = tmp32;
		506	break;
		507	case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
		508	u64 regid;
		509
		510	regid = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
		511	ret = vgic_v3_cpu_sysregs_uaccess(vcpu, is_write,
		512	regid, reg);
		513	break;
		514	}
		515	case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
		516	unsigned int info, intid;
		517
		518	info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
		519	KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
		520	if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
		521	intid = attr->attr &
		522	KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
		523	ret = vgic_v3_line_level_info_uaccess(vcpu, is_write,
		524	intid, reg);
		525	} else {
		526	ret = -EINVAL;
		527	}
		528	break;
		529	}
		530	default:
		531	ret = -EINVAL;
		532	break;
		533	}
		534
		535	unlock_all_vcpus(dev->kvm);
		536	out:
		537	mutex_unlock(&dev->kvm->lock);
		538	return ret;
		539	}
		540
431	static int vgic_v3_set_attr(struct kvm_device *dev,	541	static int vgic_v3_set_attr(struct kvm_device *dev,
432	struct kvm_device_attr *attr)	542	struct kvm_device_attr *attr)
433	{	543	{
434	return vgic_set_common_attr(dev, attr);	544	int ret;
		545
		546	ret = vgic_set_common_attr(dev, attr);
		547	if (ret != -ENXIO)
		548	return ret;
		549
		550	switch (attr->group) {
		551	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
		552	case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
		553	u32 __user uaddr = (u32 __user )(long)attr->addr;
		554	u32 tmp32;
		555	u64 reg;
		556
		557	if (get_user(tmp32, uaddr))
		558	return -EFAULT;
		559
		560	reg = tmp32;
		561	return vgic_v3_attr_regs_access(dev, attr, &reg, true);
		562	}
		563	case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
		564	u64 __user uaddr = (u64 __user )(long)attr->addr;
		565	u64 reg;
		566
		567	if (get_user(reg, uaddr))
		568	return -EFAULT;
		569
		570	return vgic_v3_attr_regs_access(dev, attr, &reg, true);
		571	}
		572	case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
		573	u32 __user uaddr = (u32 __user )(long)attr->addr;
		574	u64 reg;
		575	u32 tmp32;
		576
		577	if (get_user(tmp32, uaddr))
		578	return -EFAULT;
		579
		580	reg = tmp32;
		581	return vgic_v3_attr_regs_access(dev, attr, &reg, true);
		582	}
		583	}
		584	return -ENXIO;
435	}	585	}
436		586
437	static int vgic_v3_get_attr(struct kvm_device *dev,	587	static int vgic_v3_get_attr(struct kvm_device *dev,
438	struct kvm_device_attr *attr)	588	struct kvm_device_attr *attr)
439	{	589	{
440	return vgic_get_common_attr(dev, attr);	590	int ret;
		591
		592	ret = vgic_get_common_attr(dev, attr);
		593	if (ret != -ENXIO)
		594	return ret;
		595
		596	switch (attr->group) {
		597	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
		598	case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
		599	u32 __user uaddr = (u32 __user )(long)attr->addr;
		600	u64 reg;
		601	u32 tmp32;
		602
		603	ret = vgic_v3_attr_regs_access(dev, attr, &reg, false);
		604	if (ret)
		605	return ret;
		606	tmp32 = reg;
		607	return put_user(tmp32, uaddr);
		608	}
		609	case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
		610	u64 __user uaddr = (u64 __user )(long)attr->addr;
		611	u64 reg;
		612
		613	ret = vgic_v3_attr_regs_access(dev, attr, &reg, false);
		614	if (ret)
		615	return ret;
		616	return put_user(reg, uaddr);
		617	}
		618	case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
		619	u32 __user uaddr = (u32 __user )(long)attr->addr;
		620	u64 reg;
		621	u32 tmp32;
		622
		623	ret = vgic_v3_attr_regs_access(dev, attr, &reg, false);
		624	if (ret)
		625	return ret;
		626	tmp32 = reg;
		627	return put_user(tmp32, uaddr);
		628	}
		629	}
		630	return -ENXIO;
441	}	631	}
442		632
443	static int vgic_v3_has_attr(struct kvm_device *dev,	633	static int vgic_v3_has_attr(struct kvm_device *dev,
@@ -451,8 +641,19 @@ static int vgic_v3_has_attr(struct kvm_device *dev, · 7 unmodified lines
451	return 0;	641	return 0;
452	}	642	}
453	break;	643	break;
		644	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
		645	case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
		646	case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
		647	return vgic_v3_has_attr_regs(dev, attr);
454	case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:	648	case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
455	return 0;	649	return 0;
		650	case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
		651	if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
		652	KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
		653	VGIC_LEVEL_INFO_LINE_LEVEL)
		654	return 0;
		655	break;
		656	}
456	case KVM_DEV_ARM_VGIC_GRP_CTRL:	657	case KVM_DEV_ARM_VGIC_GRP_CTRL:
457	switch (attr->attr) {	658	switch (attr->attr) {
458	case KVM_DEV_ARM_VGIC_CTRL_INIT:	659	case KVM_DEV_ARM_VGIC_CTRL_INIT:

virt/kvm/arm/vgic/vgic-mmio-v2.c+24−63

 		irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
 		spin_lock(&irq->irq_lock);
-		irq->pending = true;
+		irq->pending_latch = true;
 		irq->source |= 1U << source_vcpu->vcpu_id;
 		vgic_queue_irq_unlock(source_vcpu->kvm, irq);
 		irq->source &= ~((val >> (i * 8)) & 0xff);
 		if (!irq->source)
-			irq->pending = false;
+			irq->pending_latch = false;
 		spin_unlock(&irq->irq_lock);
 		vgic_put_irq(vcpu->kvm, irq);
 		irq->source |= (val >> (i * 8)) & 0xff;
 		if (irq->source) {
-			irq->pending = true;
+			irq->pending_latch = true;
 			vgic_queue_irq_unlock(vcpu->kvm, irq);
 		} else {
 			spin_unlock(&irq->irq_lock);
 	}
 }
-static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
-{
-	if (kvm_vgic_global_state.type == VGIC_V2)
-		vgic_v2_set_vmcr(vcpu, vmcr);
-	else
-		vgic_v3_set_vmcr(vcpu, vmcr);
-}
-static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
-{
-	if (kvm_vgic_global_state.type == VGIC_V2)
-		vgic_v2_get_vmcr(vcpu, vmcr);
-	else
-		vgic_v3_get_vmcr(vcpu, vmcr);
-}
 #define GICC_ARCH_VERSION_V2	0x2
 /* These are for userland accesses only, there is no guest-facing emulation. */
 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
 {
-	int nr_irqs = dev->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
+	const struct vgic_register_region *region;
-	const struct vgic_register_region *regions;
+	struct vgic_io_device iodev;
+	struct vgic_reg_attr reg_attr;
+	struct kvm_vcpu *vcpu;
 	gpa_t addr;
-	int nr_regions, i, len;
+	int ret;
+	ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
+	if (ret)
+		return ret;
-	addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
+	vcpu = reg_attr.vcpu;
+	addr = reg_attr.addr;
 	switch (attr->group) {
 	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
-		regions = vgic_v2_dist_registers;
+		iodev.regions = vgic_v2_dist_registers;
-		nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
+		iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
+		iodev.base_addr = 0;
 		break;
 	case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
-		regions = vgic_v2_cpu_registers;
+		iodev.regions = vgic_v2_cpu_registers;
-		nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
+		iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
+		iodev.base_addr = 0;
 		break;
 	default:
 		return -ENXIO;
 	if (addr & 3)
 		return -ENXIO;
-	for (i = 0; i < nr_regions; i++) {
+	region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
-		if (regions[i].bits_per_irq)
+	if (!region)
-			len = (regions[i].bits_per_irq * nr_irqs) / 8;
+		return -ENXIO;
-		else
-			len = regions[i].len;
-		if (regions[i].reg_offset <= addr &&
-		    regions[i].reg_offset + len > addr)
-			return 0;
-	}
-	return -ENXIO;
-}
-/*
- * When userland tries to access the VGIC register handlers, we need to
- * create a usable struct vgic_io_device to be passed to the handlers and we
- * have to set up a buffer similar to what would have happened if a guest MMIO
- * access occurred, including doing endian conversions on BE systems.
- */
-static int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
-			bool is_write, int offset, u32 *val)
-{
-	unsigned int len = 4;
-	u8 buf[4];
-	int ret;
-	if (is_write) {
-		vgic_data_host_to_mmio_bus(buf, len, *val);
-		ret = kvm_io_gic_ops.write(vcpu, &dev->dev, offset, len, buf);
-	} else {
-		ret = kvm_io_gic_ops.read(vcpu, &dev->dev, offset, len, buf);
-		if (!ret)
-			*val = vgic_data_mmio_bus_to_host(buf, len);
-	}
-	return ret;
+	return 0;
 }
 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,

virt/kvm/arm/vgic/vgic-mmio-v3.c+184−19

@@ -18,6 +18,8 @@ · 17 unmodified lines
18	#include <kvm/arm_vgic.h>	18	#include <kvm/arm_vgic.h>
19		19
20	#include <asm/kvm_emulate.h>	20	#include <asm/kvm_emulate.h>
		21	#include <asm/kvm_arm.h>
		22	#include <asm/kvm_mmu.h>
21		23
22	#include "vgic.h"	24	#include "vgic.h"
23	#include "vgic-mmio.h"	25	#include "vgic-mmio.h"
@@ -207,6 +209,60 @@ static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, · 183 unmodified lines
207	return 0;	209	return 0;
208	}	210	}
209		211
		212	static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
		213	gpa_t addr, unsigned int len)
		214	{
		215	u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
		216	u32 value = 0;
		217	int i;
		218
		219	/*
		220	* pending state of interrupt is latched in pending_latch variable.
		221	* Userspace will save and restore pending state and line_level
		222	* separately.
		223	* Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
		224	* for handling of ISPENDR and ICPENDR.
		225	*/
		226	for (i = 0; i < len * 8; i++) {
		227	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
		228
		229	if (irq->pending_latch)
		230	value \|= (1U << i);
		231
		232	vgic_put_irq(vcpu->kvm, irq);
		233	}
		234
		235	return value;
		236	}
		237
		238	static void vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
		239	gpa_t addr, unsigned int len,
		240	unsigned long val)
		241	{
		242	u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
		243	int i;
		244
		245	for (i = 0; i < len * 8; i++) {
		246	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
		247
		248	spin_lock(&irq->irq_lock);
		249	if (test_bit(i, &val)) {
		250	/*
		251	* pending_latch is set irrespective of irq type
		252	* (level or edge) to avoid dependency that VM should
		253	* restore irq config before pending info.
		254	*/
		255	irq->pending_latch = true;
		256	vgic_queue_irq_unlock(vcpu->kvm, irq);
		257	} else {
		258	irq->pending_latch = false;
		259	spin_unlock(&irq->irq_lock);
		260	}
		261
		262	vgic_put_irq(vcpu->kvm, irq);
		263	}
		264	}
		265
210	/* We want to avoid outer shareable. */	266	/* We want to avoid outer shareable. */
211	u64 vgic_sanitise_shareability(u64 field)	267	u64 vgic_sanitise_shareability(u64 field)
212	{	268	{
@@ -356,7 +412,7 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, · 143 unmodified lines
356	* We take some special care here to fix the calculation of the register	412	* We take some special care here to fix the calculation of the register
357	* offset.	413	* offset.
358	*/	414	*/
359	#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \	415	#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
360	{ \	416	{ \
361	.reg_offset = off, \	417	.reg_offset = off, \
362	.bits_per_irq = bpi, \	418	.bits_per_irq = bpi, \
@@ -371,47 +427,54 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, · 8 unmodified lines
371	.access_flags = acc, \	427	.access_flags = acc, \
372	.read = rd, \	428	.read = rd, \
373	.write = wr, \	429	.write = wr, \
		430	.uaccess_read = ur, \
		431	.uaccess_write = uw, \
374	}	432	}
375		433
376	static const struct vgic_register_region vgic_v3_dist_registers[] = {	434	static const struct vgic_register_region vgic_v3_dist_registers[] = {
377	REGISTER_DESC_WITH_LENGTH(GICD_CTLR,	435	REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
378	vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,	436	vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
379	VGIC_ACCESS_32bit),	437	VGIC_ACCESS_32bit),
		438	REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
		439	vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
		440	VGIC_ACCESS_32bit),
380	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,	441	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
381	vgic_mmio_read_rao, vgic_mmio_write_wi, 1,	442	vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
382	VGIC_ACCESS_32bit),	443	VGIC_ACCESS_32bit),
383	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,	444	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
384	vgic_mmio_read_enable, vgic_mmio_write_senable, 1,	445	vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
385	VGIC_ACCESS_32bit),	446	VGIC_ACCESS_32bit),
386	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,	447	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
387	vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,	448	vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
388	VGIC_ACCESS_32bit),	449	VGIC_ACCESS_32bit),
389	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,	450	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
390	vgic_mmio_read_pending, vgic_mmio_write_spending, 1,	451	vgic_mmio_read_pending, vgic_mmio_write_spending,
		452	vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
391	VGIC_ACCESS_32bit),	453	VGIC_ACCESS_32bit),
392	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,	454	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
393	vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,	455	vgic_mmio_read_pending, vgic_mmio_write_cpending,
		456	vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
394	VGIC_ACCESS_32bit),	457	VGIC_ACCESS_32bit),
395	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,	458	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
396	vgic_mmio_read_active, vgic_mmio_write_sactive, 1,	459	vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,
397	VGIC_ACCESS_32bit),	460	VGIC_ACCESS_32bit),
398	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,	461	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
399	vgic_mmio_read_active, vgic_mmio_write_cactive, 1,	462	vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,
400	VGIC_ACCESS_32bit),	463	VGIC_ACCESS_32bit),
401	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,	464	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
402	vgic_mmio_read_priority, vgic_mmio_write_priority, 8,	465	vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
403	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),	466	8, VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
404	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,	467	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
405	vgic_mmio_read_raz, vgic_mmio_write_wi, 8,	468	vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
406	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),	469	VGIC_ACCESS_32bit \| VGIC_ACCESS_8bit),
407	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,	470	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
408	vgic_mmio_read_config, vgic_mmio_write_config, 2,	471	vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
409	VGIC_ACCESS_32bit),	472	VGIC_ACCESS_32bit),
410	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,	473	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
411	vgic_mmio_read_raz, vgic_mmio_write_wi, 1,	474	vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
412	VGIC_ACCESS_32bit),	475	VGIC_ACCESS_32bit),
413	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,	476	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
414	vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,	477	vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
415	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),	478	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
416	REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,	479	REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
417	vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,	480	vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
@@ -422,12 +485,18 @@ static const struct vgic_register_region vgic_v3_rdbase_registers[] = { · 4 unmodified lines
422	REGISTER_DESC_WITH_LENGTH(GICR_CTLR,	485	REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
423	vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,	486	vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
424	VGIC_ACCESS_32bit),	487	VGIC_ACCESS_32bit),
		488	REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
		489	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		490	VGIC_ACCESS_32bit),
425	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,	491	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
426	vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,	492	vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
427	VGIC_ACCESS_32bit),	493	VGIC_ACCESS_32bit),
428	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,	494	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
429	vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,	495	vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
430	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),	496	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
		497	REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
		498	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
		499	VGIC_ACCESS_32bit),
431	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,	500	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
432	vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,	501	vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
433	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),	502	VGIC_ACCESS_64bit \| VGIC_ACCESS_32bit),
@@ -449,11 +518,13 @@ static const struct vgic_register_region vgic_v3_sgibase_registers[] = { · 15 unmodified lines
449	REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,	518	REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
450	vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,	519	vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
451	VGIC_ACCESS_32bit),	520	VGIC_ACCESS_32bit),
452	REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,	521	REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
453	vgic_mmio_read_pending, vgic_mmio_write_spending, 4,	522	vgic_mmio_read_pending, vgic_mmio_write_spending,
		523	vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
454	VGIC_ACCESS_32bit),	524	VGIC_ACCESS_32bit),
455	REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,	525	REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
456	vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,	526	vgic_mmio_read_pending, vgic_mmio_write_cpending,
		527	vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
457	VGIC_ACCESS_32bit),	528	VGIC_ACCESS_32bit),
458	REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,	529	REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
459	vgic_mmio_read_active, vgic_mmio_write_sactive, 4,	530	vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
@@ -546,6 +617,54 @@ int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address) · 86 unmodified lines
546	return ret;	617	return ret;
547	}	618	}
548		619
		620	int vgic_v3_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr)
		621	{
		622	const struct vgic_register_region *region;
		623	struct vgic_io_device iodev;
		624	struct vgic_reg_attr reg_attr;
		625	struct kvm_vcpu *vcpu;
		626	gpa_t addr;
		627	int ret;
		628
		629	ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
		630	if (ret)
		631	return ret;
		632
		633	vcpu = reg_attr.vcpu;
		634	addr = reg_attr.addr;
		635
		636	switch (attr->group) {
		637	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
		638	iodev.regions = vgic_v3_dist_registers;
		639	iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
		640	iodev.base_addr = 0;
		641	break;
		642	case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
		643	iodev.regions = vgic_v3_rdbase_registers;
		644	iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
		645	iodev.base_addr = 0;
		646	break;
		647	}
		648	case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
		649	u64 reg, id;
		650
		651	id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
		652	return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, &reg);
		653	}
		654	default:
		655	return -ENXIO;
		656	}
		657
		658	/* We only support aligned 32-bit accesses. */
		659	if (addr & 3)
		660	return -ENXIO;
		661
		662	region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
		663	if (!region)
		664	return -ENXIO;
		665
		666	return 0;
		667	}
549	/*	668	/*
550	* Compare a given affinity (level 1-3 and a level 0 mask, from the SGI	669	* Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
551	* generation register ICC_SGI1R_EL1) with a given VCPU.	670	* generation register ICC_SGI1R_EL1) with a given VCPU.
@@ -646,9 +765,55 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg) · 94 unmodified lines
646	irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);	765	irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
647		766
648	spin_lock(&irq->irq_lock);	767	spin_lock(&irq->irq_lock);
649	irq->pending = true;	768	irq->pending_latch = true;
650		769
651	vgic_queue_irq_unlock(vcpu->kvm, irq);	770	vgic_queue_irq_unlock(vcpu->kvm, irq);
652	vgic_put_irq(vcpu->kvm, irq);	771	vgic_put_irq(vcpu->kvm, irq);
653	}	772	}
654	}	773	}
		774
		775	int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
		776	int offset, u32 *val)
		777	{
		778	struct vgic_io_device dev = {
		779	.regions = vgic_v3_dist_registers,
		780	.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
		781	};
		782
		783	return vgic_uaccess(vcpu, &dev, is_write, offset, val);
		784	}
		785
		786	int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
		787	int offset, u32 *val)
		788	{
		789	struct vgic_io_device rd_dev = {
		790	.regions = vgic_v3_rdbase_registers,
		791	.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers),
		792	};
		793
		794	struct vgic_io_device sgi_dev = {
		795	.regions = vgic_v3_sgibase_registers,
		796	.nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers),
		797	};
		798
		799	/* SGI_base is the next 64K frame after RD_base */
		800	if (offset >= SZ_64K)
		801	return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K,
		802	val);
		803	else
		804	return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
		805	}
		806
		807	int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
		808	u32 intid, u64 *val)
		809	{
		810	if (intid % 32)
		811	return -EINVAL;
		812
		813	if (is_write)
		814	vgic_write_irq_line_level_info(vcpu, intid, *val);
		815	else
		816	*val = vgic_read_irq_line_level_info(vcpu, intid);
		817
		818	return 0;
		819	}

virt/kvm/arm/vgic/vgic-mmio.c+147−20

@@ -111,7 +111,7 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, · 110 unmodified lines
111	for (i = 0; i < len * 8; i++) {	111	for (i = 0; i < len * 8; i++) {
112	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	112	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
113		113
114	if (irq->pending)	114	if (irq_is_pending(irq))
115	value \|= (1U << i);	115	value \|= (1U << i);
116		116
117	vgic_put_irq(vcpu->kvm, irq);	117	vgic_put_irq(vcpu->kvm, irq);
@@ -131,9 +131,7 @@ void vgic_mmio_write_spending(struct kvm_vcpu *vcpu, · 13 unmodified lines
131	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	131	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
132		132
133	spin_lock(&irq->irq_lock);	133	spin_lock(&irq->irq_lock);
134	irq->pending = true;	134	irq->pending_latch = true;
135	if (irq->config == VGIC_CONFIG_LEVEL)
136	irq->soft_pending = true;
137		135
138	vgic_queue_irq_unlock(vcpu->kvm, irq);	136	vgic_queue_irq_unlock(vcpu->kvm, irq);
139	vgic_put_irq(vcpu->kvm, irq);	137	vgic_put_irq(vcpu->kvm, irq);
@@ -152,12 +150,7 @@ void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu, · 12 unmodified lines
152		150
153	spin_lock(&irq->irq_lock);	151	spin_lock(&irq->irq_lock);
154		152
155	if (irq->config == VGIC_CONFIG_LEVEL) {	153	irq->pending_latch = false;
156	irq->soft_pending = false;
157	irq->pending = irq->line_level;
158	} else {
159	irq->pending = false;
160	}
161		154
162	spin_unlock(&irq->irq_lock);	155	spin_unlock(&irq->irq_lock);
163	vgic_put_irq(vcpu->kvm, irq);	156	vgic_put_irq(vcpu->kvm, irq);
@@ -359,18 +352,70 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu, · 195 unmodified lines
359	irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	352	irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
360	spin_lock(&irq->irq_lock);	353	spin_lock(&irq->irq_lock);
361		354
362	if (test_bit(i * 2 + 1, &val)) {	355	if (test_bit(i * 2 + 1, &val))
363	irq->config = VGIC_CONFIG_EDGE;	356	irq->config = VGIC_CONFIG_EDGE;
364	} else {	357	else
365	irq->config = VGIC_CONFIG_LEVEL;	358	irq->config = VGIC_CONFIG_LEVEL;
366	irq->pending = irq->line_level \| irq->soft_pending;
367	}
368		359
369	spin_unlock(&irq->irq_lock);	360	spin_unlock(&irq->irq_lock);
370	vgic_put_irq(vcpu->kvm, irq);	361	vgic_put_irq(vcpu->kvm, irq);
371	}	362	}
372	}	363	}
373		364
		365	u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
		366	{
		367	int i;
		368	u64 val = 0;
		369	int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
		370
		371	for (i = 0; i < 32; i++) {
		372	struct vgic_irq *irq;
		373
		374	if ((intid + i) < VGIC_NR_SGIS \|\| (intid + i) >= nr_irqs)
		375	continue;
		376
		377	irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
		378	if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
		379	val \|= (1U << i);
		380
		381	vgic_put_irq(vcpu->kvm, irq);
		382	}
		383
		384	return val;
		385	}
		386
		387	void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
		388	const u64 val)
		389	{
		390	int i;
		391	int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
		392
		393	for (i = 0; i < 32; i++) {
		394	struct vgic_irq *irq;
		395	bool new_level;
		396
		397	if ((intid + i) < VGIC_NR_SGIS \|\| (intid + i) >= nr_irqs)
		398	continue;
		399
		400	irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
		401
		402	/*
		403	* Line level is set irrespective of irq type
		404	* (level or edge) to avoid dependency that VM should
		405	* restore irq config before line level.
		406	*/
		407	new_level = !!(val & (1U << i));
		408	spin_lock(&irq->irq_lock);
		409	irq->line_level = new_level;
		410	if (new_level)
		411	vgic_queue_irq_unlock(vcpu->kvm, irq);
		412	else
		413	spin_unlock(&irq->irq_lock);
		414
		415	vgic_put_irq(vcpu->kvm, irq);
		416	}
		417	}
		418
374	static int match_region(const void key, const void elt)	419	static int match_region(const void key, const void elt)
375	{	420	{
376	const unsigned int offset = (unsigned long)key;	421	const unsigned int offset = (unsigned long)key;
@@ -394,6 +439,22 @@ vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions, · 17 unmodified lines
394	sizeof(region[0]), match_region);	439	sizeof(region[0]), match_region);
395	}	440	}
396		441
		442	void vgic_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr)
		443	{
		444	if (kvm_vgic_global_state.type == VGIC_V2)
		445	vgic_v2_set_vmcr(vcpu, vmcr);
		446	else
		447	vgic_v3_set_vmcr(vcpu, vmcr);
		448	}
		449
		450	void vgic_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr)
		451	{
		452	if (kvm_vgic_global_state.type == VGIC_V2)
		453	vgic_v2_get_vmcr(vcpu, vmcr);
		454	else
		455	vgic_v3_get_vmcr(vcpu, vmcr);
		456	}
		457
397	/*	458	/*
398	* kvm_mmio_read_buf() returns a value in a format where it can be converted	459	* kvm_mmio_read_buf() returns a value in a format where it can be converted
399	* to a byte array and be directly observed as the guest wanted it to appear	460	* to a byte array and be directly observed as the guest wanted it to appear
@@ -484,6 +545,74 @@ static bool check_region(const struct kvm *kvm, · 84 unmodified lines
484	return false;	545	return false;
485	}	546	}
486		547
		548	const struct vgic_register_region *
		549	vgic_get_mmio_region(struct kvm_vcpu vcpu, struct vgic_io_device iodev,
		550	gpa_t addr, int len)
		551	{
		552	const struct vgic_register_region *region;
		553
		554	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
		555	addr - iodev->base_addr);
		556	if (!region \|\| !check_region(vcpu->kvm, region, addr, len))
		557	return NULL;
		558
		559	return region;
		560	}
		561
		562	static int vgic_uaccess_read(struct kvm_vcpu vcpu, struct kvm_io_device dev,
		563	gpa_t addr, u32 *val)
		564	{
		565	struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
		566	const struct vgic_register_region *region;
		567	struct kvm_vcpu *r_vcpu;
		568
		569	region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
		570	if (!region) {
		571	*val = 0;
		572	return 0;
		573	}
		574
		575	r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
		576	if (region->uaccess_read)
		577	*val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
		578	else
		579	*val = region->read(r_vcpu, addr, sizeof(u32));
		580
		581	return 0;
		582	}
		583
		584	static int vgic_uaccess_write(struct kvm_vcpu vcpu, struct kvm_io_device dev,
		585	gpa_t addr, const u32 *val)
		586	{
		587	struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
		588	const struct vgic_register_region *region;
		589	struct kvm_vcpu *r_vcpu;
		590
		591	region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
		592	if (!region)
		593	return 0;
		594
		595	r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
		596	if (region->uaccess_write)
		597	region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
		598	else
		599	region->write(r_vcpu, addr, sizeof(u32), *val);
		600
		601	return 0;
		602	}
		603
		604	/*
		605	* Userland access to VGIC registers.
		606	*/
		607	int vgic_uaccess(struct kvm_vcpu vcpu, struct vgic_io_device dev,
		608	bool is_write, int offset, u32 *val)
		609	{
		610	if (is_write)
		611	return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
		612	else
		613	return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
		614	}
		615
487	static int dispatch_mmio_read(struct kvm_vcpu vcpu, struct kvm_io_device dev,	616	static int dispatch_mmio_read(struct kvm_vcpu vcpu, struct kvm_io_device dev,
488	gpa_t addr, int len, void *val)	617	gpa_t addr, int len, void *val)
489	{	618	{
@@ -491,9 +620,8 @@ static int dispatch_mmio_read(struct kvm_vcpu vcpu, struct kvm_io_device dev, · 1 unmodified line
491	const struct vgic_register_region *region;	620	const struct vgic_register_region *region;
492	unsigned long data = 0;	621	unsigned long data = 0;
493		622
494	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,	623	region = vgic_get_mmio_region(vcpu, iodev, addr, len);
495	addr - iodev->base_addr);	624	if (!region) {
496	if (!region \|\| !check_region(vcpu->kvm, region, addr, len)) {
497	memset(val, 0, len);	625	memset(val, 0, len);
498	return 0;	626	return 0;
499	}	627	}
@@ -524,9 +652,8 @@ static int dispatch_mmio_write(struct kvm_vcpu vcpu, struct kvm_io_device dev, · 24 unmodified lines
524	const struct vgic_register_region *region;	652	const struct vgic_register_region *region;
525	unsigned long data = vgic_data_mmio_bus_to_host(val, len);	653	unsigned long data = vgic_data_mmio_bus_to_host(val, len);
526		654
527	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,	655	region = vgic_get_mmio_region(vcpu, iodev, addr, len);
528	addr - iodev->base_addr);	656	if (!region)
529	if (!region \|\| !check_region(vcpu->kvm, region, addr, len))
530	return 0;	657	return 0;
531		658
532	switch (iodev->iodev_type) {	659	switch (iodev->iodev_type) {

virt/kvm/arm/vgic/vgic-mmio.h+24−0

@@ -34,6 +34,10 @@ struct vgic_register_region { · 33 unmodified lines
34	gpa_t addr, unsigned int len,	34	gpa_t addr, unsigned int len,
35	unsigned long val);	35	unsigned long val);
36	};	36	};
		37	unsigned long (uaccess_read)(struct kvm_vcpu vcpu, gpa_t addr,
		38	unsigned int len);
		39	void (uaccess_write)(struct kvm_vcpu vcpu, gpa_t addr,
		40	unsigned int len, unsigned long val);
37	};	41	};
38		42
39	extern struct kvm_io_device_ops kvm_io_gic_ops;	43	extern struct kvm_io_device_ops kvm_io_gic_ops;
@@ -86,6 +90,18 @@ extern struct kvm_io_device_ops kvm_io_gic_ops; · 46 unmodified lines
86	.write = wr, \	90	.write = wr, \
87	}	91	}
88		92
		93	#define REGISTER_DESC_WITH_LENGTH_UACCESS(off, rd, wr, urd, uwr, length, acc) \
		94	{ \
		95	.reg_offset = off, \
		96	.bits_per_irq = 0, \
		97	.len = length, \
		98	.access_flags = acc, \
		99	.read = rd, \
		100	.write = wr, \
		101	.uaccess_read = urd, \
		102	.uaccess_write = uwr, \
		103	}
		104
89	int kvm_vgic_register_mmio_region(struct kvm kvm, struct kvm_vcpu vcpu,	105	int kvm_vgic_register_mmio_region(struct kvm kvm, struct kvm_vcpu vcpu,
90	struct vgic_register_region *reg_desc,	106	struct vgic_register_region *reg_desc,
91	struct vgic_io_device *region,	107	struct vgic_io_device *region,
@@ -158,6 +174,14 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu, · 66 unmodified lines
158	gpa_t addr, unsigned int len,	174	gpa_t addr, unsigned int len,
159	unsigned long val);	175	unsigned long val);
160		176
		177	int vgic_uaccess(struct kvm_vcpu vcpu, struct vgic_io_device dev,
		178	bool is_write, int offset, u32 *val);
		179
		180	u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid);
		181
		182	void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
		183	const u64 val);
		184
161	unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);	185	unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
162		186
163	unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);	187	unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);

virt/kvm/arm/vgic/vgic-v2.c+5−9

 		/* Edge is the only case where we preserve the pending bit */
 		if (irq->config == VGIC_CONFIG_EDGE &&
 		    (val & GICH_LR_PENDING_BIT)) {
-			irq->pending = true;
+			irq->pending_latch = true;
 			if (vgic_irq_is_sgi(intid)) {
 				u32 cpuid = val & GICH_LR_PHYSID_CPUID;
 		 */
 		if (irq->config == VGIC_CONFIG_LEVEL) {
 			if (!(val & GICH_LR_PENDING_BIT))
-				irq->soft_pending = false;
+				irq->pending_latch = false;
-			irq->pending = irq->line_level || irq->soft_pending;
 		}
 		spin_unlock(&irq->irq_lock);
 {
 	u32 val = irq->intid;
-	if (irq->pending) {
+	if (irq_is_pending(irq)) {
 		val |= GICH_LR_PENDING_BIT;
 		if (irq->config == VGIC_CONFIG_EDGE)
-			irq->pending = false;
+			irq->pending_latch = false;
 		if (vgic_irq_is_sgi(irq->intid)) {
 			u32 src = ffs(irq->source);
 			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 			irq->source &= ~(1 << (src - 1));
 			if (irq->source)
-				irq->pending = true;
+				irq->pending_latch = true;
 		}
 	}
 	dist->ready = true;
 out:
-	if (ret)
-		kvm_vgic_destroy(kvm);
 	return ret;
 }

virt/kvm/arm/vgic/vgic-v3.c+31−11

 		/* Edge is the only case where we preserve the pending bit */
 		if (irq->config == VGIC_CONFIG_EDGE &&
 		    (val & ICH_LR_PENDING_BIT)) {
-			irq->pending = true;
+			irq->pending_latch = true;
 			if (vgic_irq_is_sgi(intid) &&
 			    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 		 */
 		if (irq->config == VGIC_CONFIG_LEVEL) {
 			if (!(val & ICH_LR_PENDING_BIT))
-				irq->soft_pending = false;
+				irq->pending_latch = false;
-			irq->pending = irq->line_level || irq->soft_pending;
 		}
 		spin_unlock(&irq->irq_lock);
 	u32 model = vcpu->kvm->arch.vgic.vgic_model;
 	u64 val = irq->intid;
-	if (irq->pending) {
+	if (irq_is_pending(irq)) {
 		val |= ICH_LR_PENDING_BIT;
 		if (irq->config == VGIC_CONFIG_EDGE)
-			irq->pending = false;
+			irq->pending_latch = false;
 		if (vgic_irq_is_sgi(irq->intid) &&
 		    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 			irq->source &= ~(1 << (src - 1));
 			if (irq->source)
-				irq->pending = true;
+				irq->pending_latch = true;
 		}
 	}
 {
 	u32 vmcr;
-	vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
+	/*
+	 * Ignore the FIQen bit, because GIC emulation always implies
+	 * SRE=1 which means the vFIQEn bit is also RES1.
+	 */
+	vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
+		 ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
+	vmcr |= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
 	vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 	vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 	vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
+	vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
+	vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
 }
 {
 	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
-	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
+	/*
+	 * Ignore the FIQen bit, because GIC emulation always implies
+	 * SRE=1 which means the vFIQEn bit is also RES1.
+	 */
+	vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
+			ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
+	vmcrp->ctlr |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 	vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 	vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
+	vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
+	vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
 }
 #define INITIAL_PENDBASER_VALUE						  \
 		vgic_v3->vgic_sre = 0;
 	}
+	vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
+					   ICH_VTR_ID_BITS_MASK) >>
+					   ICH_VTR_ID_BITS_SHIFT;
+	vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
+					    ICH_VTR_PRI_BITS_MASK) >>
+					    ICH_VTR_PRI_BITS_SHIFT) + 1;
 	/* Get the show on the road... */
 	vgic_v3->vgic_hcr = ICH_HCR_EN;
 }
 	dist->ready = true;
 out:
-	if (ret)
-		kvm_vgic_destroy(kvm);
 	return ret;
 }
 	 */
 	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 	kvm_vgic_global_state.can_emulate_gicv2 = false;
+	kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 	if (!info->vcpu.start) {
 		kvm_info("GICv3: no GICV resource entry\n");

virt/kvm/arm/vgic/vgic.c+23−43

 	 * If the distributor is disabled, pending interrupts shouldn't be
 	 * forwarded.
 	 */
-	if (irq->enabled && irq->pending) {
+	if (irq->enabled && irq_is_pending(irq)) {
 		if (unlikely(irq->target_vcpu &&
 			     !irq->target_vcpu->kvm->arch.vgic.enabled))
 			return NULL;
 		goto out;
 	}
-	penda = irqa->enabled && irqa->pending;
+	penda = irqa->enabled && irq_is_pending(irqa);
-	pendb = irqb->enabled && irqb->pending;
+	pendb = irqb->enabled && irq_is_pending(irqb);
 	if (!penda || !pendb) {
 		ret = (int)pendb - (int)penda;
 	return true;
 }
-static int vgic_update_irq_pending(struct kvm *kvm, int cpuid,
+/**
-				   unsigned int intid, bool level,
+ * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
-				   bool mapped_irq)
+ * @kvm:     The VM structure pointer
+ * @cpuid:   The CPU for PPIs
+ * @intid:   The INTID to inject a new state to.
+ * @level:   Edge-triggered:  true:  to trigger the interrupt
+ *			      false: to ignore the call
+ *	     Level-sensitive  true:  raise the input signal
+ *			      false: lower the input signal
+ *
+ * The VGIC is not concerned with devices being active-LOW or active-HIGH for
+ * level-sensitive interrupts.  You can think of the level parameter as 1
+ * being HIGH and 0 being LOW and all devices being active-HIGH.
+ */
+int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
+			bool level)
 {
 	struct kvm_vcpu *vcpu;
 	struct vgic_irq *irq;
 	if (!irq)
 		return -EINVAL;
-	if (irq->hw != mapped_irq) {
-		vgic_put_irq(kvm, irq);
-		return -EINVAL;
-	}
 	spin_lock(&irq->irq_lock);
 	if (!vgic_validate_injection(irq, level)) {
 		return 0;
 	}
-	if (irq->config == VGIC_CONFIG_LEVEL) {
+	if (irq->config == VGIC_CONFIG_LEVEL)
 		irq->line_level = level;
-		irq->pending = level || irq->soft_pending;
+	else
-	} else {
+		irq->pending_latch = true;
-		irq->pending = true;
-	}
 	vgic_queue_irq_unlock(kvm, irq);
 	vgic_put_irq(kvm, irq);
 	return 0;
 }
-/**
- * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
- * @kvm:     The VM structure pointer
- * @cpuid:   The CPU for PPIs
- * @intid:   The INTID to inject a new state to.
- * @level:   Edge-triggered:  true:  to trigger the interrupt
- *			      false: to ignore the call
- *	     Level-sensitive  true:  raise the input signal
- *			      false: lower the input signal
- *
- * The VGIC is not concerned with devices being active-LOW or active-HIGH for
- * level-sensitive interrupts.  You can think of the level parameter as 1
- * being HIGH and 0 being LOW and all devices being active-HIGH.
- */
-int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
-			bool level)
-{
-	return vgic_update_irq_pending(kvm, cpuid, intid, level, false);
-}
-int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
-			       bool level)
-{
-	return vgic_update_irq_pending(kvm, cpuid, intid, level, true);
-}
 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq)
 {
 	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, virt_irq);
 	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
 		spin_lock(&irq->irq_lock);
-		pending = irq->pending && irq->enabled;
+		pending = irq_is_pending(irq) && irq->enabled;
 		spin_unlock(&irq->irq_lock);
 		if (pending)

virt/kvm/arm/vgic/vgic.h+82−1

@@ -30,13 +30,79 @@ · 29 unmodified lines
30		30
31	#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)	31	#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
32		32
		33	#define VGIC_AFFINITY_0_SHIFT 0
		34	#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
		35	#define VGIC_AFFINITY_1_SHIFT 8
		36	#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
		37	#define VGIC_AFFINITY_2_SHIFT 16
		38	#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
		39	#define VGIC_AFFINITY_3_SHIFT 24
		40	#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
		41
		42	#define VGIC_AFFINITY_LEVEL(reg, level) \
		43	((((reg) & VGIC_AFFINITY_## level ##_MASK) \
		44	>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
		45
		46	/*
		47	* The Userspace encodes the affinity differently from the MPIDR,
		48	* Below macro converts vgic userspace format to MPIDR reg format.
		49	*/
		50	#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) \| \
		51	VGIC_AFFINITY_LEVEL(val, 1) \| \
		52	VGIC_AFFINITY_LEVEL(val, 2) \| \
		53	VGIC_AFFINITY_LEVEL(val, 3))
		54
		55	/*
		56	* As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
		57	* below macros are defined for CPUREG encoding.
		58	*/
		59	#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
		60	#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
		61	#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
		62	#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
		63	#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
		64	#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
		65	#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
		66	#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
		67	#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
		68	#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
		69
		70	#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK \| \
		71	KVM_REG_ARM_VGIC_SYSREG_OP1_MASK \| \
		72	KVM_REG_ARM_VGIC_SYSREG_CRN_MASK \| \
		73	KVM_REG_ARM_VGIC_SYSREG_CRM_MASK \| \
		74	KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
		75
		76	static inline bool irq_is_pending(struct vgic_irq *irq)
		77	{
		78	if (irq->config == VGIC_CONFIG_EDGE)
		79	return irq->pending_latch;
		80	else
		81	return irq->pending_latch \|\| irq->line_level;
		82	}
		83
33	struct vgic_vmcr {	84	struct vgic_vmcr {
34	u32 ctlr;	85	u32 ctlr;
35	u32 abpr;	86	u32 abpr;
36	u32 bpr;	87	u32 bpr;
37	u32 pmr;	88	u32 pmr;
		89	/* Below member variable are valid only for GICv3 */
		90	u32 grpen0;
		91	u32 grpen1;
		92	};
		93
		94	struct vgic_reg_attr {
		95	struct kvm_vcpu *vcpu;
		96	gpa_t addr;
38	};	97	};
39		98
		99	int vgic_v3_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
		100	struct vgic_reg_attr *reg_attr);
		101	int vgic_v2_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
		102	struct vgic_reg_attr *reg_attr);
		103	const struct vgic_register_region *
		104	vgic_get_mmio_region(struct kvm_vcpu vcpu, struct vgic_io_device iodev,
		105	gpa_t addr, int len);
40	struct vgic_irq vgic_get_irq(struct kvm kvm, struct kvm_vcpu *vcpu,	106	struct vgic_irq vgic_get_irq(struct kvm kvm, struct kvm_vcpu *vcpu,
41	u32 intid);	107	u32 intid);
42	void vgic_put_irq(struct kvm kvm, struct vgic_irq irq);	108	void vgic_put_irq(struct kvm kvm, struct vgic_irq irq);
@@ -89,9 +155,24 @@ bool vgic_has_its(struct kvm *kvm); · 46 unmodified lines
89	int kvm_vgic_register_its_device(void);	155	int kvm_vgic_register_its_device(void);
90	void vgic_enable_lpis(struct kvm_vcpu *vcpu);	156	void vgic_enable_lpis(struct kvm_vcpu *vcpu);
91	int vgic_its_inject_msi(struct kvm kvm, struct kvm_msi msi);	157	int vgic_its_inject_msi(struct kvm kvm, struct kvm_msi msi);
92		158	int vgic_v3_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr);
		159	int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
		160	int offset, u32 *val);
		161	int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
		162	int offset, u32 *val);
		163	int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
		164	u64 id, u64 *val);
		165	int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
		166	u64 *reg);
		167	int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
		168	u32 intid, u64 *val);
93	int kvm_register_vgic_device(unsigned long type);	169	int kvm_register_vgic_device(unsigned long type);
		170	void vgic_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
		171	void vgic_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
94	int vgic_lazy_init(struct kvm *kvm);	172	int vgic_lazy_init(struct kvm *kvm);
95	int vgic_init(struct kvm *kvm);	173	int vgic_init(struct kvm *kvm);
96		174
		175	int vgic_debug_init(struct kvm *kvm);
		176	int vgic_debug_destroy(struct kvm *kvm);
		177
97	#endif	178	#endif

@@ -157,7 +157,7 @@ · 156 unmodified lines
157	#define PPC_INST_MCRXR 0x7c000400	157	#define PPC_INST_MCRXR 0x7c000400
158	#define PPC_INST_MCRXR_MASK 0xfc0007fe	158	#define PPC_INST_MCRXR_MASK 0xfc0007fe
159	#define PPC_INST_MFSPR_PVR 0x7c1f42a6	159	#define PPC_INST_MFSPR_PVR 0x7c1f42a6
160	#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff	160	#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
161	#define PPC_INST_MFTMR 0x7c0002dc	161	#define PPC_INST_MFTMR 0x7c0002dc
162	#define PPC_INST_MSGSND 0x7c00019c	162	#define PPC_INST_MSGSND 0x7c00019c
163	#define PPC_INST_MSGCLR 0x7c0001dc	163	#define PPC_INST_MSGCLR 0x7c0001dc
@@ -174,13 +174,13 @@ · 10 unmodified lines
174	#define PPC_INST_RFDI 0x4c00004e	174	#define PPC_INST_RFDI 0x4c00004e
175	#define PPC_INST_RFMCI 0x4c00004c	175	#define PPC_INST_RFMCI 0x4c00004c
176	#define PPC_INST_MFSPR_DSCR 0x7c1102a6	176	#define PPC_INST_MFSPR_DSCR 0x7c1102a6
177	#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff	177	#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
178	#define PPC_INST_MTSPR_DSCR 0x7c1103a6	178	#define PPC_INST_MTSPR_DSCR 0x7c1103a6
179	#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff	179	#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
180	#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6	180	#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
181	#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1fffff	181	#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
182	#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6	182	#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
183	#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1fffff	183	#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
184	#define PPC_INST_MFVSRD 0x7c000066	184	#define PPC_INST_MFVSRD 0x7c000066
185	#define PPC_INST_MTVSRD 0x7c000166	185	#define PPC_INST_MTVSRD 0x7c000166
186	#define PPC_INST_SLBFEE 0x7c0007a7	186	#define PPC_INST_SLBFEE 0x7c0007a7

@@ -586,7 +586,7 @@ static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { · 585 unmodified lines
586	GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",	586	GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
587	GATE_BUS_TOP, 24, 0, 0),	587	GATE_BUS_TOP, 24, 0, 0),
588	GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",	588	GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
589	GATE_BUS_TOP, 27, 0, 0),	589	GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
590	};	590	};
591		591
592	static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {	592	static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
@@ -956,20 +956,20 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { · 363 unmodified lines
956	GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),	956	GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
957		957
958	GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",	958	GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
959	GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),	959	GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
960	GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",	960	GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
961	GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),	961	GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
962		962
963	GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",	963	GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
964	GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),	964	GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
965	GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",	965	GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
966	GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),	966	GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
967	GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",	967	GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
968	GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),	968	GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
969	GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",	969	GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
970	GATE_BUS_TOP, 5, 0, 0),	970	GATE_BUS_TOP, 5, 0, 0),
971	GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",	971	GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
972	GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),	972	GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
973	GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",	973	GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
974	GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),	974	GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
975	GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",	975	GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
@@ -983,20 +983,20 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { · 7 unmodified lines
983	GATE(0, "aclk166", "mout_user_aclk166",	983	GATE(0, "aclk166", "mout_user_aclk166",
984	GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),	984	GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
985	GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",	985	GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
986	GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),	986	GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
987	GATE(0, "aclk400_isp", "mout_user_aclk400_isp",	987	GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
988	GATE_BUS_TOP, 16, 0, 0),	988	GATE_BUS_TOP, 16, 0, 0),
989	GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",	989	GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
990	GATE_BUS_TOP, 17, 0, 0),	990	GATE_BUS_TOP, 17, 0, 0),
991	GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",	991	GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
992	GATE_BUS_TOP, 18, 0, 0),	992	GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
993	GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",	993	GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
994	GATE_BUS_TOP, 28, 0, 0),	994	GATE_BUS_TOP, 28, 0, 0),
995	GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",	995	GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
996	GATE_BUS_TOP, 29, 0, 0),	996	GATE_BUS_TOP, 29, 0, 0),
997		997
998	GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",	998	GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
999	SRC_MASK_TOP2, 24, 0, 0),	999	SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
1000		1000
1001	GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",	1001	GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
1002	SRC_MASK_TOP7, 20, 0, 0),	1002	SRC_MASK_TOP7, 20, 0, 0),