Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next

- Qualcomm QCS404 CDSP clk support - Qualcomm QCS404 Turing clk support - Mediatek MT8183 clock support - Mediatek MT8516 clock support - Milbeaut M10V clk controller support * clk-renesas: clk: renesas: rcar-gen3: Remove unused variable clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value clk: renesas: r8a77980: Fix RPC-IF module clock's parent clk: renesas: rcar-gen3: Rename DRIF clocks clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC clk: renesas: rcar-gen3: Correct parent clock of HS-USB clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI clk: renesas: r8a774c0: Add Z2 clock clk: renesas: r8a77990: Add Z2 clock clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents math64: New DIV64_U64_ROUND_CLOSEST helper clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r9a06g032: Add missing PCI USB clock clk: renesas: r7s9210: Always use readl() clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() * clk-qcom: clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998 clk: qcom: Add QCS404 TuringCC clk: qcom: branch: Add AON clock ops dt-bindings: clock: Introduce Qualcomm Turing Clock controller clk: qcom: gcc-qcs404: Add CDSP related clocks and resets * clk-mtk: clk: mediatek: add clock driver for MT8516 dt-bindings: mediatek: apmixedsys: add support for MT8516 dt-bindings: mediatek: infracfg: add support for MT8516 dt-bindings: mediatek: topckgen: add support for MT8516 clk: mediatek: Allow changing PLL rate when it is off clk: mediatek: Add MT8183 clock support clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add dt-bindings for MT8183 clocks dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data clk: mediatek: Add new clkmux register API clk: mediatek: Disable tuner_en before change PLL rate * clk-milbeaut: clock: milbeaut: Add Milbeaut M10V clock controller dt-bindings: clock: milbeaut: add Milbeaut clock description * clk-imx: clk: imx: correct pfdv2 gate_bit/vld_bit operations clk: imx: clk-pllv3: mark expected switch fall-throughs clk: imx8mq: Add dsi_ipg_div clk: imx: pllv4: add fractional-N pll support clk: imx: keep uart clock on during system boot clk: imx: correct i.MX7D AV PLL num/denom offset clk: imx6sll: Fix mispelling uart4_serial as serail clk: imx: pll14xx: drop unused variable clk: imx: rename clk-imx51-imx53.c to clk-imx5.c clk: imx5: Fix i.MX50 ESDHC clock registers clk: imx5: Fix i.MX50 mainbus clock registers clk: imx: Remove unused imx_get_clk_hw_fixed dt-bindings: clock: imx7ulp: remove SNVS clock clk: imx7ulp: remove snvs clock

Stephen Boyd committed 7 years ago

Commit 2ed3b916 parents e93c9c9 c2f0705 c0ee0e4 db077fe 6a6ba5b a5a627c72 files · +5451 −204Browse files

Unified · Split

72 files

Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +2 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +1 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt +22 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +1 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +2 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt +43 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt +1 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt +1 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +1 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +2 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt +1 −0
Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt +1 −0
Documentation/devicetree/bindings/clock/milbeaut-clock.yaml +73 −0
Documentation/devicetree/bindings/clock/qcom,turingcc.txt +19 −0
drivers/clk/Makefile +1 −0
drivers/clk/clk-milbeaut.c +663 −0
drivers/clk/imx/Makefile +1 −1
drivers/clk/imx/clk-imx5.c +45 −14
drivers/clk/imx/clk-imx6sll.c +17 −1
drivers/clk/imx/clk-imx7d.c +2 −2
drivers/clk/imx/clk-imx7ulp.c +0 −1
drivers/clk/imx/clk-imx8mq.c +1 −0
drivers/clk/imx/clk-pfdv2.c +5 −5
drivers/clk/imx/clk-pll14xx.c +2 −4
drivers/clk/imx/clk-pllv3.c +23 −8
drivers/clk/imx/clk-pllv4.c +63 −9
drivers/clk/imx/clk.h +1 −5
drivers/clk/mediatek/Kconfig +83 −0
drivers/clk/mediatek/Makefile +15 −1
drivers/clk/mediatek/clk-gate.h +14 −0
drivers/clk/mediatek/clk-mt8183-audio.c +105 −0
drivers/clk/mediatek/clk-mt8183-cam.c +63 −0
drivers/clk/mediatek/clk-mt8183-img.c +63 −0
drivers/clk/mediatek/clk-mt8183-ipu0.c +56 −0
drivers/clk/mediatek/clk-mt8183-ipu1.c +56 −0
drivers/clk/mediatek/clk-mt8183-ipu_adl.c +54 −0
drivers/clk/mediatek/clk-mt8183-ipu_conn.c +123 −0
drivers/clk/mediatek/clk-mt8183-mfgcfg.c +54 −0
drivers/clk/mediatek/clk-mt8183-mm.c +111 −0
drivers/clk/mediatek/clk-mt8183-vdec.c +67 −0
drivers/clk/mediatek/clk-mt8183-venc.c +59 −0
drivers/clk/mediatek/clk-mt8183.c +1284 −0
drivers/clk/mediatek/clk-mt8516.c +815 −0
drivers/clk/mediatek/clk-mtk.h +3 −0
drivers/clk/mediatek/clk-mux.c +223 −0
drivers/clk/mediatek/clk-mux.h +89 −0
drivers/clk/mediatek/clk-pll.c +55 −32
drivers/clk/qcom/Kconfig +6 −0
drivers/clk/qcom/Makefile +1 −0
drivers/clk/qcom/clk-branch.c +6 −0
drivers/clk/qcom/clk-branch.h +1 −0
drivers/clk/qcom/gcc-msm8998.c +1 −1
drivers/clk/qcom/gcc-qcs404.c +90 −0
drivers/clk/qcom/turingcc-qcs404.c +170 −0
drivers/clk/renesas/r7s9210-cpg-mssr.c +2 −1
drivers/clk/renesas/r8a774a1-cpg-mssr.c +9 −9
drivers/clk/renesas/r8a774c0-cpg-mssr.c +4 −3
drivers/clk/renesas/r8a7795-cpg-mssr.c +21 −20
drivers/clk/renesas/r8a7796-cpg-mssr.c +18 −17
drivers/clk/renesas/r8a77965-cpg-mssr.c +17 −16
drivers/clk/renesas/r8a77980-cpg-mssr.c +1 −1
drivers/clk/renesas/r8a77990-cpg-mssr.c +13 −12
drivers/clk/renesas/r8a77995-cpg-mssr.c +1 −1
drivers/clk/renesas/r9a06g032-clocks.c +1 −0
drivers/clk/renesas/rcar-gen3-cpg.c +33 −38
drivers/clk/renesas/rcar-gen3-cpg.h +4 −1
include/dt-bindings/clock/imx7ulp-clock.h +0 −1
include/dt-bindings/clock/mt8183-clk.h +422 −0
include/dt-bindings/clock/mt8516-clk.h +211 −0
include/dt-bindings/clock/qcom,gcc-qcs404.h +5 −0
include/dt-bindings/clock/qcom,turingcc-qcs404.h +15 −0
include/linux/math64.h +13 −0

Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt+2−0

@@ -14,6 +14,8 @@ Required Properties: · 13 unmodified lines
14	14	- "mediatek,mt7629-apmixedsys"
15	15	- "mediatek,mt8135-apmixedsys"
16	16	- "mediatek,mt8173-apmixedsys"
	17	+ - "mediatek,mt8183-apmixedsys", "syscon"
	18	+ - "mediatek,mt8516-apmixedsys"
17	19	- #clock-cells: Must be 1
18	20
19	21	The apmixedsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt+1−0

@@ -9,6 +9,7 @@ Required Properties: · 8 unmodified lines
9	9	- "mediatek,mt2701-audsys", "syscon"
10	10	- "mediatek,mt7622-audsys", "syscon"
11	11	- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
	12	+ - "mediatek,mt8183-audiosys", "syscon"
12	13	- #clock-cells: Must be 1
13	14
14	15	The AUDSYS controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt+22−0

@@ -0,0 +1,22 @@
	1	+MediaTek CAMSYS controller
	2	+============================
	3	+
	4	+The MediaTek camsys controller provides various clocks to the system.
	5	+
	6	+Required Properties:
	7	+
	8	+- compatible: Should be one of:
	9	+ - "mediatek,mt8183-camsys", "syscon"
	10	+- #clock-cells: Must be 1
	11	+
	12	+The camsys controller uses the common clk binding from
	13	+Documentation/devicetree/bindings/clock/clock-bindings.txt
	14	+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
	15	+
	16	+Example:
	17	+
	18	+camsys: camsys@1a000000 {
	19	+ compatible = "mediatek,mt8183-camsys", "syscon";
	20	+ reg = <0 0x1a000000 0 0x1000>;
	21	+ #clock-cells = <1>;
	22	+};

Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt+1−0

@@ -11,6 +11,7 @@ Required Properties: · 10 unmodified lines
11	11	- "mediatek,mt6797-imgsys", "syscon"
12	12	- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
13	13	- "mediatek,mt8173-imgsys", "syscon"
	14	+ - "mediatek,mt8183-imgsys", "syscon"
14	15	- #clock-cells: Must be 1
15	16
16	17	The imgsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt+2−0

@@ -15,6 +15,8 @@ Required Properties: · 14 unmodified lines
15	15	- "mediatek,mt7629-infracfg", "syscon"
16	16	- "mediatek,mt8135-infracfg", "syscon"
17	17	- "mediatek,mt8173-infracfg", "syscon"
	18	+ - "mediatek,mt8183-infracfg", "syscon"
	19	+ - "mediatek,mt8516-infracfg", "syscon"
18	20	- #clock-cells: Must be 1
19	21	- #reset-cells: Must be 1
20	22

Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt+43−0

@@ -0,0 +1,43 @@
	1	+Mediatek IPU controller
	2	+============================
	3	+
	4	+The Mediatek ipu controller provides various clocks to the system.
	5	+
	6	+Required Properties:
	7	+
	8	+- compatible: Should be one of:
	9	+ - "mediatek,mt8183-ipu_conn", "syscon"
	10	+ - "mediatek,mt8183-ipu_adl", "syscon"
	11	+ - "mediatek,mt8183-ipu_core0", "syscon"
	12	+ - "mediatek,mt8183-ipu_core1", "syscon"
	13	+- #clock-cells: Must be 1
	14	+
	15	+The ipu controller uses the common clk binding from
	16	+Documentation/devicetree/bindings/clock/clock-bindings.txt
	17	+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
	18	+
	19	+Example:
	20	+
	21	+ipu_conn: syscon@19000000 {
	22	+ compatible = "mediatek,mt8183-ipu_conn", "syscon";
	23	+ reg = <0 0x19000000 0 0x1000>;
	24	+ #clock-cells = <1>;
	25	+};
	26	+
	27	+ipu_adl: syscon@19010000 {
	28	+ compatible = "mediatek,mt8183-ipu_adl", "syscon";
	29	+ reg = <0 0x19010000 0 0x1000>;
	30	+ #clock-cells = <1>;
	31	+};
	32	+
	33	+ipu_core0: syscon@19180000 {
	34	+ compatible = "mediatek,mt8183-ipu_core0", "syscon";
	35	+ reg = <0 0x19180000 0 0x1000>;
	36	+ #clock-cells = <1>;
	37	+};
	38	+
	39	+ipu_core1: syscon@19280000 {
	40	+ compatible = "mediatek,mt8183-ipu_core1", "syscon";
	41	+ reg = <0 0x19280000 0 0x1000>;
	42	+ #clock-cells = <1>;
	43	+};

Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt+1−0

@@ -7,6 +7,7 @@ Required Properties: · 6 unmodified lines
7	7
8	8	- compatible: Should be one of:
9	9	- "mediatek,mt2712-mcucfg", "syscon"
	10	+ - "mediatek,mt8183-mcucfg", "syscon"
10	11	- #clock-cells: Must be 1
11	12
12	13	The mcucfg controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt+1−0

@@ -7,6 +7,7 @@ Required Properties: · 6 unmodified lines
7	7
8	8	- compatible: Should be one of:
9	9	- "mediatek,mt2712-mfgcfg", "syscon"
	10	+ - "mediatek,mt8183-mfgcfg", "syscon"
10	11	- #clock-cells: Must be 1
11	12
12	13	The mfgcfg controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt+1−0

@@ -11,6 +11,7 @@ Required Properties: · 10 unmodified lines
11	11	- "mediatek,mt6797-mmsys", "syscon"
12	12	- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
13	13	- "mediatek,mt8173-mmsys", "syscon"
	14	+ - "mediatek,mt8183-mmsys", "syscon"
14	15	- #clock-cells: Must be 1
15	16
16	17	The mmsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt+2−0

@@ -14,6 +14,8 @@ Required Properties: · 13 unmodified lines
14	14	- "mediatek,mt7629-topckgen"
15	15	- "mediatek,mt8135-topckgen"
16	16	- "mediatek,mt8173-topckgen"
	17	+ - "mediatek,mt8183-topckgen", "syscon"
	18	+ - "mediatek,mt8516-topckgen"
17	19	- #clock-cells: Must be 1
18	20
19	21	The topckgen controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt+1−0

@@ -11,6 +11,7 @@ Required Properties: · 10 unmodified lines
11	11	- "mediatek,mt6797-vdecsys", "syscon"
12	12	- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
13	13	- "mediatek,mt8173-vdecsys", "syscon"
	14	+ - "mediatek,mt8183-vdecsys", "syscon"
14	15	- #clock-cells: Must be 1
15	16
16	17	The vdecsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt+1−0

@@ -9,6 +9,7 @@ Required Properties: · 8 unmodified lines
9	9	- "mediatek,mt2712-vencsys", "syscon"
10	10	- "mediatek,mt6797-vencsys", "syscon"
11	11	- "mediatek,mt8173-vencsys", "syscon"
	12	+ - "mediatek,mt8183-vencsys", "syscon"
12	13	- #clock-cells: Must be 1
13	14
14	15	The vencsys controller uses the common clk binding from

Documentation/devicetree/bindings/clock/milbeaut-clock.yaml+73−0

@@ -0,0 +1,73 @@
	1	+# SPDX-License-Identifier: GPL-2.0
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Milbeaut SoCs Clock Controller Binding
	8	+
	9	+maintainers:
	10	+ - Taichi Sugaya <sugaya.taichi@socionext.com>
	11	+
	12	+description: \|
	13	+ Milbeaut SoCs Clock controller is an integrated clock controller, which
	14	+ generates and supplies to all modules.
	15	+
	16	+ This binding uses common clock bindings
	17	+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
	18	+
	19	+properties:
	20	+ compatible:
	21	+ oneOf:
	22	+ - items:
	23	+ - enum:
	24	+ - socionext,milbeaut-m10v-ccu
	25	+ clocks:
	26	+ maxItems: 1
	27	+ description: external clock
	28	+
	29	+ '#clock-cells':
	30	+ const: 1
	31	+
	32	+required:
	33	+ - compatible
	34	+ - reg
	35	+ - clocks
	36	+ - '#clock-cells'
	37	+
	38	+examples:
	39	+ # Clock controller node:
	40	+ - \|
	41	+ m10v-clk-ctrl@1d021000 {
	42	+ compatible = "socionext,milbeaut-m10v-clk-ccu";
	43	+ reg = <0x1d021000 0x4000>;
	44	+ #clock-cells = <1>;
	45	+ clocks = <&clki40mhz>;
	46	+ };
	47	+
	48	+ # Required an external clock for Clock controller node:
	49	+ - \|
	50	+ clocks {
	51	+ clki40mhz: clki40mhz {
	52	+ compatible = "fixed-clock";
	53	+ #clock-cells = <0>;
	54	+ clock-frequency = <40000000>;
	55	+ };
	56	+ /* other clocks */
	57	+ };
	58	+
	59	+ # The clock consumer shall specify the desired clock-output of the clock
	60	+ # controller as below by specifying output-id in its "clk" phandle cell.
	61	+ # 2: uart
	62	+ # 4: 32-bit timer
	63	+ # 7: UHS-I/II
	64	+ - \|
	65	+ serial@1e700010 {
	66	+ compatible = "socionext,milbeaut-usio-uart";
	67	+ reg = <0x1e700010 0x10>;
	68	+ interrupts = <0 141 0x4>, <0 149 0x4>;
	69	+ interrupt-names = "rx", "tx";
	70	+ clocks = <&clk 2>;
	71	+ };
	72	+
	73	+...

Documentation/devicetree/bindings/clock/qcom,turingcc.txt+19−0

@@ -0,0 +1,19 @@
	1	+Qualcomm Turing Clock & Reset Controller Binding
	2	+------------------------------------------------
	3	+
	4	+Required properties :
	5	+- compatible: shall contain "qcom,qcs404-turingcc".
	6	+- reg: shall contain base register location and length.
	7	+- clocks: ahb clock for the TuringCC
	8	+- #clock-cells: from common clock binding, shall contain 1.
	9	+- #reset-cells: from common reset binding, shall contain 1.
	10	+
	11	+Example:
	12	+ turingcc: clock-controller@800000 {
	13	+ compatible = "qcom,qcs404-turingcc";
	14	+ reg = <0x00800000 0x30000>;
	15	+ clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
	16	+
	17	+ #clock-cells = <1>;
	18	+ #reset-cells = <1>;
	19	+ };

drivers/clk/Makefile+1−0

@@ -34,6 +34,7 @@ obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o · 33 unmodified lines
34	34	obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
35	35	obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
36	36	obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
	37	+obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o
37	38	obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
38	39	obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
39	40	obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o

drivers/clk/clk-milbeaut.c+663−0

@@ -0,0 +1,663 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright (C) 2018 Socionext Inc.
	4	+ * Copyright (C) 2016 Linaro Ltd.
	5	+ */
	6	+
	7	+#include <linux/clk-provider.h>
	8	+#include <linux/err.h>
	9	+#include <linux/io.h>
	10	+#include <linux/iopoll.h>
	11	+#include <linux/of_address.h>
	12	+#include <linux/platform_device.h>
	13	+#include <linux/slab.h>
	14	+#include <linux/spinlock.h>
	15	+
	16	+#define M10V_CLKSEL1 0x0
	17	+#define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
	18	+
	19	+#define M10V_PLL1 "pll1"
	20	+#define M10V_PLL1DIV2 "pll1-2"
	21	+#define M10V_PLL2 "pll2"
	22	+#define M10V_PLL2DIV2 "pll2-2"
	23	+#define M10V_PLL6 "pll6"
	24	+#define M10V_PLL6DIV2 "pll6-2"
	25	+#define M10V_PLL6DIV3 "pll6-3"
	26	+#define M10V_PLL7 "pll7"
	27	+#define M10V_PLL7DIV2 "pll7-2"
	28	+#define M10V_PLL7DIV5 "pll7-5"
	29	+#define M10V_PLL9 "pll9"
	30	+#define M10V_PLL10 "pll10"
	31	+#define M10V_PLL10DIV2 "pll10-2"
	32	+#define M10V_PLL11 "pll11"
	33	+
	34	+#define M10V_SPI_PARENT0 "spi-parent0"
	35	+#define M10V_SPI_PARENT1 "spi-parent1"
	36	+#define M10V_SPI_PARENT2 "spi-parent2"
	37	+#define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0"
	38	+#define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1"
	39	+#define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2"
	40	+#define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0"
	41	+#define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1"
	42	+#define M10V_NFCLK_PARENT0 "nfclk-parent0"
	43	+#define M10V_NFCLK_PARENT1 "nfclk-parent1"
	44	+#define M10V_NFCLK_PARENT2 "nfclk-parent2"
	45	+#define M10V_NFCLK_PARENT3 "nfclk-parent3"
	46	+#define M10V_NFCLK_PARENT4 "nfclk-parent4"
	47	+#define M10V_NFCLK_PARENT5 "nfclk-parent5"
	48	+
	49	+#define M10V_DCHREQ 1
	50	+#define M10V_UPOLL_RATE 1
	51	+#define M10V_UTIMEOUT 250
	52	+
	53	+#define M10V_EMMCCLK_ID 0
	54	+#define M10V_ACLK_ID 1
	55	+#define M10V_HCLK_ID 2
	56	+#define M10V_PCLK_ID 3
	57	+#define M10V_RCLK_ID 4
	58	+#define M10V_SPICLK_ID 5
	59	+#define M10V_NFCLK_ID 6
	60	+#define M10V_UHS1CLK2_ID 7
	61	+#define M10V_NUM_CLKS 8
	62	+
	63	+#define to_m10v_div(_hw) container_of(_hw, struct m10v_clk_divider, hw)
	64	+
	65	+static struct clk_hw_onecell_data *m10v_clk_data;
	66	+
	67	+static DEFINE_SPINLOCK(m10v_crglock);
	68	+
	69	+struct m10v_clk_div_factors {
	70	+ const char *name;
	71	+ const char *parent_name;
	72	+ u32 offset;
	73	+ u8 shift;
	74	+ u8 width;
	75	+ const struct clk_div_table *table;
	76	+ unsigned long div_flags;
	77	+ int onecell_idx;
	78	+};
	79	+
	80	+struct m10v_clk_div_fixed_data {
	81	+ const char *name;
	82	+ const char *parent_name;
	83	+ u8 div;
	84	+ u8 mult;
	85	+ int onecell_idx;
	86	+};
	87	+
	88	+struct m10v_clk_mux_factors {
	89	+ const char *name;
	90	+ const char * const *parent_names;
	91	+ u8 num_parents;
	92	+ u32 offset;
	93	+ u8 shift;
	94	+ u8 mask;
	95	+ u32 *table;
	96	+ unsigned long mux_flags;
	97	+ int onecell_idx;
	98	+};
	99	+
	100	+static const struct clk_div_table emmcclk_table[] = {
	101	+ { .val = 0, .div = 8 },
	102	+ { .val = 1, .div = 9 },
	103	+ { .val = 2, .div = 10 },
	104	+ { .val = 3, .div = 15 },
	105	+ { .div = 0 },
	106	+};
	107	+
	108	+static const struct clk_div_table mclk400_table[] = {
	109	+ { .val = 1, .div = 2 },
	110	+ { .val = 3, .div = 4 },
	111	+ { .div = 0 },
	112	+};
	113	+
	114	+static const struct clk_div_table mclk200_table[] = {
	115	+ { .val = 3, .div = 4 },
	116	+ { .val = 7, .div = 8 },
	117	+ { .div = 0 },
	118	+};
	119	+
	120	+static const struct clk_div_table aclk400_table[] = {
	121	+ { .val = 1, .div = 2 },
	122	+ { .val = 3, .div = 4 },
	123	+ { .div = 0 },
	124	+};
	125	+
	126	+static const struct clk_div_table aclk300_table[] = {
	127	+ { .val = 0, .div = 2 },
	128	+ { .val = 1, .div = 3 },
	129	+ { .div = 0 },
	130	+};
	131	+
	132	+static const struct clk_div_table aclk_table[] = {
	133	+ { .val = 3, .div = 4 },
	134	+ { .val = 7, .div = 8 },
	135	+ { .div = 0 },
	136	+};
	137	+
	138	+static const struct clk_div_table aclkexs_table[] = {
	139	+ { .val = 3, .div = 4 },
	140	+ { .val = 4, .div = 5 },
	141	+ { .val = 5, .div = 6 },
	142	+ { .val = 7, .div = 8 },
	143	+ { .div = 0 },
	144	+};
	145	+
	146	+static const struct clk_div_table hclk_table[] = {
	147	+ { .val = 7, .div = 8 },
	148	+ { .val = 15, .div = 16 },
	149	+ { .div = 0 },
	150	+};
	151	+
	152	+static const struct clk_div_table hclkbmh_table[] = {
	153	+ { .val = 3, .div = 4 },
	154	+ { .val = 7, .div = 8 },
	155	+ { .div = 0 },
	156	+};
	157	+
	158	+static const struct clk_div_table pclk_table[] = {
	159	+ { .val = 15, .div = 16 },
	160	+ { .val = 31, .div = 32 },
	161	+ { .div = 0 },
	162	+};
	163	+
	164	+static const struct clk_div_table rclk_table[] = {
	165	+ { .val = 0, .div = 8 },
	166	+ { .val = 1, .div = 16 },
	167	+ { .val = 2, .div = 24 },
	168	+ { .val = 3, .div = 32 },
	169	+ { .div = 0 },
	170	+};
	171	+
	172	+static const struct clk_div_table uhs1clk0_table[] = {
	173	+ { .val = 0, .div = 2 },
	174	+ { .val = 1, .div = 3 },
	175	+ { .val = 2, .div = 4 },
	176	+ { .val = 3, .div = 8 },
	177	+ { .val = 4, .div = 16 },
	178	+ { .div = 0 },
	179	+};
	180	+
	181	+static const struct clk_div_table uhs2clk_table[] = {
	182	+ { .val = 0, .div = 9 },
	183	+ { .val = 1, .div = 10 },
	184	+ { .val = 2, .div = 11 },
	185	+ { .val = 3, .div = 12 },
	186	+ { .val = 4, .div = 13 },
	187	+ { .val = 5, .div = 14 },
	188	+ { .val = 6, .div = 16 },
	189	+ { .val = 7, .div = 18 },
	190	+ { .div = 0 },
	191	+};
	192	+
	193	+static u32 spi_mux_table[] = {0, 1, 2};
	194	+static const char * const spi_mux_names[] = {
	195	+ M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2
	196	+};
	197	+
	198	+static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8};
	199	+static const char * const uhs1clk2_mux_names[] = {
	200	+ M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1,
	201	+ M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2
	202	+};
	203	+
	204	+static u32 uhs1clk1_mux_table[] = {3, 4, 8};
	205	+static const char * const uhs1clk1_mux_names[] = {
	206	+ M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2
	207	+};
	208	+
	209	+static u32 nfclk_mux_table[] = {0, 1, 2, 3, 4, 8};
	210	+static const char * const nfclk_mux_names[] = {
	211	+ M10V_NFCLK_PARENT0, M10V_NFCLK_PARENT1, M10V_NFCLK_PARENT2,
	212	+ M10V_NFCLK_PARENT3, M10V_NFCLK_PARENT4, M10V_NFCLK_PARENT5
	213	+};
	214	+
	215	+static const struct m10v_clk_div_fixed_data m10v_pll_fixed_data[] = {
	216	+ {M10V_PLL1, NULL, 1, 40, -1},
	217	+ {M10V_PLL2, NULL, 1, 30, -1},
	218	+ {M10V_PLL6, NULL, 1, 35, -1},
	219	+ {M10V_PLL7, NULL, 1, 40, -1},
	220	+ {M10V_PLL9, NULL, 1, 33, -1},
	221	+ {M10V_PLL10, NULL, 5, 108, -1},
	222	+ {M10V_PLL10DIV2, M10V_PLL10, 2, 1, -1},
	223	+ {M10V_PLL11, NULL, 2, 75, -1},
	224	+};
	225	+
	226	+static const struct m10v_clk_div_fixed_data m10v_div_fixed_data[] = {
	227	+ {"usb2", NULL, 2, 1, -1},
	228	+ {"pcisuppclk", NULL, 20, 1, -1},
	229	+ {M10V_PLL1DIV2, M10V_PLL1, 2, 1, -1},
	230	+ {M10V_PLL2DIV2, M10V_PLL2, 2, 1, -1},
	231	+ {M10V_PLL6DIV2, M10V_PLL6, 2, 1, -1},
	232	+ {M10V_PLL6DIV3, M10V_PLL6, 3, 1, -1},
	233	+ {M10V_PLL7DIV2, M10V_PLL7, 2, 1, -1},
	234	+ {M10V_PLL7DIV5, M10V_PLL7, 5, 1, -1},
	235	+ {"ca7wd", M10V_PLL2DIV2, 12, 1, -1},
	236	+ {"pclkca7wd", M10V_PLL1DIV2, 16, 1, -1},
	237	+ {M10V_SPI_PARENT0, M10V_PLL10DIV2, 2, 1, -1},
	238	+ {M10V_SPI_PARENT1, M10V_PLL10DIV2, 4, 1, -1},
	239	+ {M10V_SPI_PARENT2, M10V_PLL7DIV2, 8, 1, -1},
	240	+ {M10V_UHS1CLK2_PARENT0, M10V_PLL7, 4, 1, -1},
	241	+ {M10V_UHS1CLK2_PARENT1, M10V_PLL7, 8, 1, -1},
	242	+ {M10V_UHS1CLK2_PARENT2, M10V_PLL7, 16, 1, -1},
	243	+ {M10V_UHS1CLK1_PARENT0, M10V_PLL7, 8, 1, -1},
	244	+ {M10V_UHS1CLK1_PARENT1, M10V_PLL7, 16, 1, -1},
	245	+ {M10V_NFCLK_PARENT0, M10V_PLL7DIV2, 8, 1, -1},
	246	+ {M10V_NFCLK_PARENT1, M10V_PLL7DIV2, 10, 1, -1},
	247	+ {M10V_NFCLK_PARENT2, M10V_PLL7DIV2, 13, 1, -1},
	248	+ {M10V_NFCLK_PARENT3, M10V_PLL7DIV2, 16, 1, -1},
	249	+ {M10V_NFCLK_PARENT4, M10V_PLL7DIV2, 40, 1, -1},
	250	+ {M10V_NFCLK_PARENT5, M10V_PLL7DIV5, 10, 1, -1},
	251	+};
	252	+
	253	+static const struct m10v_clk_div_factors m10v_div_factor_data[] = {
	254	+ {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
	255	+ M10V_EMMCCLK_ID},
	256	+ {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
	257	+ {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
	258	+ {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
	259	+ {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
	260	+ {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
	261	+ {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
	262	+ {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
	263	+ {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
	264	+ {"pclk", M10V_PLL1DIV2, CLKSEL(9), 0, 7, pclk_table, 0, M10V_PCLK_ID},
	265	+ {"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1},
	266	+ {"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1},
	267	+};
	268	+
	269	+static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = {
	270	+ {"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names),
	271	+ CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
	272	+ {"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names),
	273	+ CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, M10V_UHS1CLK2_ID},
	274	+ {"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names),
	275	+ CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
	276	+ {"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names),
	277	+ CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
	278	+};
	279	+
	280	+static u8 m10v_mux_get_parent(struct clk_hw *hw)
	281	+{
	282	+ struct clk_mux *mux = to_clk_mux(hw);
	283	+ u32 val;
	284	+
	285	+ val = readl(mux->reg) >> mux->shift;
	286	+ val &= mux->mask;
	287	+
	288	+ return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
	289	+}
	290	+
	291	+static int m10v_mux_set_parent(struct clk_hw *hw, u8 index)
	292	+{
	293	+ struct clk_mux *mux = to_clk_mux(hw);
	294	+ u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
	295	+ unsigned long flags = 0;
	296	+ u32 reg;
	297	+ u32 write_en = BIT(fls(mux->mask) - 1);
	298	+
	299	+ if (mux->lock)
	300	+ spin_lock_irqsave(mux->lock, flags);
	301	+ else
	302	+ __acquire(mux->lock);
	303	+
	304	+ reg = readl(mux->reg);
	305	+ reg &= ~(mux->mask << mux->shift);
	306	+
	307	+ val = (val \| write_en) << mux->shift;
	308	+ reg \|= val;
	309	+ writel(reg, mux->reg);
	310	+
	311	+ if (mux->lock)
	312	+ spin_unlock_irqrestore(mux->lock, flags);
	313	+ else
	314	+ __release(mux->lock);
	315	+
	316	+ return 0;
	317	+}
	318	+
	319	+static const struct clk_ops m10v_mux_ops = {
	320	+ .get_parent = m10v_mux_get_parent,
	321	+ .set_parent = m10v_mux_set_parent,
	322	+ .determine_rate = __clk_mux_determine_rate,
	323	+};
	324	+
	325	+static struct clk_hw m10v_clk_hw_register_mux(struct device dev,
	326	+ const char name, const char const *parent_names,
	327	+ u8 num_parents, unsigned long flags, void __iomem *reg,
	328	+ u8 shift, u32 mask, u8 clk_mux_flags, u32 *table,
	329	+ spinlock_t *lock)
	330	+{
	331	+ struct clk_mux *mux;
	332	+ struct clk_hw *hw;
	333	+ struct clk_init_data init;
	334	+ int ret;
	335	+
	336	+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	337	+ if (!mux)
	338	+ return ERR_PTR(-ENOMEM);
	339	+
	340	+ init.name = name;
	341	+ init.ops = &m10v_mux_ops;
	342	+ init.flags = flags;
	343	+ init.parent_names = parent_names;
	344	+ init.num_parents = num_parents;
	345	+
	346	+ mux->reg = reg;
	347	+ mux->shift = shift;
	348	+ mux->mask = mask;
	349	+ mux->flags = clk_mux_flags;
	350	+ mux->lock = lock;
	351	+ mux->table = table;
	352	+ mux->hw.init = &init;
	353	+
	354	+ hw = &mux->hw;
	355	+ ret = clk_hw_register(dev, hw);
	356	+ if (ret) {
	357	+ kfree(mux);
	358	+ hw = ERR_PTR(ret);
	359	+ }
	360	+
	361	+ return hw;
	362	+
	363	+}
	364	+
	365	+struct m10v_clk_divider {
	366	+ struct clk_hw hw;
	367	+ void __iomem *reg;
	368	+ u8 shift;
	369	+ u8 width;
	370	+ u8 flags;
	371	+ const struct clk_div_table *table;
	372	+ spinlock_t *lock;
	373	+ void __iomem *write_valid_reg;
	374	+};
	375	+
	376	+static unsigned long m10v_clk_divider_recalc_rate(struct clk_hw *hw,
	377	+ unsigned long parent_rate)
	378	+{
	379	+ struct m10v_clk_divider *divider = to_m10v_div(hw);
	380	+ unsigned int val;
	381	+
	382	+ val = readl(divider->reg) >> divider->shift;
	383	+ val &= clk_div_mask(divider->width);
	384	+
	385	+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
	386	+ divider->flags, divider->width);
	387	+}
	388	+
	389	+static long m10v_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
	390	+ unsigned long *prate)
	391	+{
	392	+ struct m10v_clk_divider *divider = to_m10v_div(hw);
	393	+
	394	+ /* if read only, just return current value */
	395	+ if (divider->flags & CLK_DIVIDER_READ_ONLY) {
	396	+ u32 val;
	397	+
	398	+ val = readl(divider->reg) >> divider->shift;
	399	+ val &= clk_div_mask(divider->width);
	400	+
	401	+ return divider_ro_round_rate(hw, rate, prate, divider->table,
	402	+ divider->width, divider->flags,
	403	+ val);
	404	+ }
	405	+
	406	+ return divider_round_rate(hw, rate, prate, divider->table,
	407	+ divider->width, divider->flags);
	408	+}
	409	+
	410	+static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
	411	+ unsigned long parent_rate)
	412	+{
	413	+ struct m10v_clk_divider *divider = to_m10v_div(hw);
	414	+ int value;
	415	+ unsigned long flags = 0;
	416	+ u32 val;
	417	+ u32 write_en = BIT(divider->width - 1);
	418	+
	419	+ value = divider_get_val(rate, parent_rate, divider->table,
	420	+ divider->width, divider->flags);
	421	+ if (value < 0)
	422	+ return value;
	423	+
	424	+ if (divider->lock)
	425	+ spin_lock_irqsave(divider->lock, flags);
	426	+ else
	427	+ __acquire(divider->lock);
	428	+
	429	+ val = readl(divider->reg);
	430	+ val &= ~(clk_div_mask(divider->width) << divider->shift);
	431	+
	432	+ val \|= ((u32)value \| write_en) << divider->shift;
	433	+ writel(val, divider->reg);
	434	+
	435	+ if (divider->write_valid_reg) {
	436	+ writel(M10V_DCHREQ, divider->write_valid_reg);
	437	+ if (readl_poll_timeout(divider->write_valid_reg, val,
	438	+ !val, M10V_UPOLL_RATE, M10V_UTIMEOUT))
	439	+ pr_err("%s:%s couldn't stabilize\n",
	440	+ __func__, divider->hw.init->name);
	441	+ }
	442	+
	443	+ if (divider->lock)
	444	+ spin_unlock_irqrestore(divider->lock, flags);
	445	+ else
	446	+ __release(divider->lock);
	447	+
	448	+ return 0;
	449	+}
	450	+
	451	+static const struct clk_ops m10v_clk_divider_ops = {
	452	+ .recalc_rate = m10v_clk_divider_recalc_rate,
	453	+ .round_rate = m10v_clk_divider_round_rate,
	454	+ .set_rate = m10v_clk_divider_set_rate,
	455	+};
	456	+
	457	+static struct clk_hw m10v_clk_hw_register_divider(struct device dev,
	458	+ const char name, const char parent_name, unsigned long flags,
	459	+ void __iomem *reg, u8 shift, u8 width,
	460	+ u8 clk_divider_flags, const struct clk_div_table *table,
	461	+ spinlock_t lock, void __iomem write_valid_reg)
	462	+{
	463	+ struct m10v_clk_divider *div;
	464	+ struct clk_hw *hw;
	465	+ struct clk_init_data init;
	466	+ int ret;
	467	+
	468	+ div = kzalloc(sizeof(*div), GFP_KERNEL);
	469	+ if (!div)
	470	+ return ERR_PTR(-ENOMEM);
	471	+
	472	+ init.name = name;
	473	+ init.ops = &m10v_clk_divider_ops;
	474	+ init.flags = flags;
	475	+ init.parent_names = &parent_name;
	476	+ init.num_parents = 1;
	477	+
	478	+ div->reg = reg;
	479	+ div->shift = shift;
	480	+ div->width = width;
	481	+ div->flags = clk_divider_flags;
	482	+ div->lock = lock;
	483	+ div->hw.init = &init;
	484	+ div->table = table;
	485	+ div->write_valid_reg = write_valid_reg;
	486	+
	487	+ /* register the clock */
	488	+ hw = &div->hw;
	489	+ ret = clk_hw_register(dev, hw);
	490	+ if (ret) {
	491	+ kfree(div);
	492	+ hw = ERR_PTR(ret);
	493	+ }
	494	+
	495	+ return hw;
	496	+}
	497	+
	498	+static void m10v_reg_div_pre(const struct m10v_clk_div_factors *factors,
	499	+ struct clk_hw_onecell_data *clk_data,
	500	+ void __iomem *base)
	501	+{
	502	+ struct clk_hw *hw;
	503	+ void __iomem *write_valid_reg;
	504	+
	505	+ /*
	506	+ * The registers on CLKSEL(9) or CLKSEL(10) need additional
	507	+ * writing to become valid.
	508	+ */
	509	+ if ((factors->offset == CLKSEL(9)) \|\| (factors->offset == CLKSEL(10)))
	510	+ write_valid_reg = base + CLKSEL(11);
	511	+ else
	512	+ write_valid_reg = NULL;
	513	+
	514	+ hw = m10v_clk_hw_register_divider(NULL, factors->name,
	515	+ factors->parent_name,
	516	+ CLK_SET_RATE_PARENT,
	517	+ base + factors->offset,
	518	+ factors->shift,
	519	+ factors->width, factors->div_flags,
	520	+ factors->table,
	521	+ &m10v_crglock, write_valid_reg);
	522	+
	523	+ if (factors->onecell_idx >= 0)
	524	+ clk_data->hws[factors->onecell_idx] = hw;
	525	+}
	526	+
	527	+static void m10v_reg_fixed_pre(const struct m10v_clk_div_fixed_data *factors,
	528	+ struct clk_hw_onecell_data *clk_data,
	529	+ const char *parent_name)
	530	+{
	531	+ struct clk_hw *hw;
	532	+ const char *pn = factors->parent_name ?
	533	+ factors->parent_name : parent_name;
	534	+
	535	+ hw = clk_hw_register_fixed_factor(NULL, factors->name, pn, 0,
	536	+ factors->mult, factors->div);
	537	+
	538	+ if (factors->onecell_idx >= 0)
	539	+ clk_data->hws[factors->onecell_idx] = hw;
	540	+}
	541	+
	542	+static void m10v_reg_mux_pre(const struct m10v_clk_mux_factors *factors,
	543	+ struct clk_hw_onecell_data *clk_data,
	544	+ void __iomem *base)
	545	+{
	546	+ struct clk_hw *hw;
	547	+
	548	+ hw = m10v_clk_hw_register_mux(NULL, factors->name,
	549	+ factors->parent_names,
	550	+ factors->num_parents,
	551	+ CLK_SET_RATE_PARENT,
	552	+ base + factors->offset, factors->shift,
	553	+ factors->mask, factors->mux_flags,
	554	+ factors->table, &m10v_crglock);
	555	+
	556	+ if (factors->onecell_idx >= 0)
	557	+ clk_data->hws[factors->onecell_idx] = hw;
	558	+}
	559	+
	560	+static int m10v_clk_probe(struct platform_device *pdev)
	561	+{
	562	+ int id;
	563	+ struct resource *res;
	564	+ struct device *dev = &pdev->dev;
	565	+ struct device_node *np = dev->of_node;
	566	+ void __iomem *base;
	567	+ const char *parent_name;
	568	+
	569	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	570	+ base = devm_ioremap_resource(dev, res);
	571	+ if (IS_ERR(base))
	572	+ return PTR_ERR(base);
	573	+
	574	+ parent_name = of_clk_get_parent_name(np, 0);
	575	+
	576	+ for (id = 0; id < ARRAY_SIZE(m10v_div_factor_data); ++id)
	577	+ m10v_reg_div_pre(&m10v_div_factor_data[id],
	578	+ m10v_clk_data, base);
	579	+
	580	+ for (id = 0; id < ARRAY_SIZE(m10v_div_fixed_data); ++id)
	581	+ m10v_reg_fixed_pre(&m10v_div_fixed_data[id],
	582	+ m10v_clk_data, parent_name);
	583	+
	584	+ for (id = 0; id < ARRAY_SIZE(m10v_mux_factor_data); ++id)
	585	+ m10v_reg_mux_pre(&m10v_mux_factor_data[id],
	586	+ m10v_clk_data, base);
	587	+
	588	+ for (id = 0; id < M10V_NUM_CLKS; id++) {
	589	+ if (IS_ERR(m10v_clk_data->hws[id]))
	590	+ return PTR_ERR(m10v_clk_data->hws[id]);
	591	+ }
	592	+
	593	+ return 0;
	594	+}
	595	+
	596	+static const struct of_device_id m10v_clk_dt_ids[] = {
	597	+ { .compatible = "socionext,milbeaut-m10v-ccu", },
	598	+ { }
	599	+};
	600	+
	601	+static struct platform_driver m10v_clk_driver = {
	602	+ .probe = m10v_clk_probe,
	603	+ .driver = {
	604	+ .name = "m10v-ccu",
	605	+ .of_match_table = m10v_clk_dt_ids,
	606	+ },
	607	+};
	608	+builtin_platform_driver(m10v_clk_driver);
	609	+
	610	+static void __init m10v_cc_init(struct device_node *np)
	611	+{
	612	+ int id;
	613	+ void __iomem *base;
	614	+ const char *parent_name;
	615	+ struct clk_hw *hw;
	616	+
	617	+ m10v_clk_data = kzalloc(struct_size(m10v_clk_data, hws,
	618	+ M10V_NUM_CLKS),
	619	+ GFP_KERNEL);
	620	+
	621	+ if (!m10v_clk_data)
	622	+ return;
	623	+
	624	+ base = of_iomap(np, 0);
	625	+ if (!base) {
	626	+ kfree(m10v_clk_data);
	627	+ return;
	628	+ }
	629	+
	630	+ parent_name = of_clk_get_parent_name(np, 0);
	631	+ if (!parent_name) {
	632	+ kfree(m10v_clk_data);
	633	+ iounmap(base);
	634	+ return;
	635	+ }
	636	+
	637	+ /*
	638	+ * This way all clocks fetched before the platform device probes,
	639	+ * except those we assign here for early use, will be deferred.
	640	+ */
	641	+ for (id = 0; id < M10V_NUM_CLKS; id++)
	642	+ m10v_clk_data->hws[id] = ERR_PTR(-EPROBE_DEFER);
	643	+
	644	+ /*
	645	+ * PLLs are set by bootloader so this driver registers them as the
	646	+ * fixed factor.
	647	+ */
	648	+ for (id = 0; id < ARRAY_SIZE(m10v_pll_fixed_data); ++id)
	649	+ m10v_reg_fixed_pre(&m10v_pll_fixed_data[id],
	650	+ m10v_clk_data, parent_name);
	651	+
	652	+ /*
	653	+ * timer consumes "rclk" so it needs to register here.
	654	+ */
	655	+ hw = m10v_clk_hw_register_divider(NULL, "rclk", M10V_PLL10DIV2, 0,
	656	+ base + CLKSEL(1), 0, 3, 0, rclk_table,
	657	+ &m10v_crglock, NULL);
	658	+ m10v_clk_data->hws[M10V_RCLK_ID] = hw;
	659	+
	660	+ m10v_clk_data->num = M10V_NUM_CLKS;
	661	+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data);
	662	+}
	663	+CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);

drivers/clk/imx/Makefile+1−1

@@ -35,7 +35,7 @@ obj-$(CONFIG_SOC_IMX25) += clk-imx25.o · 34 unmodified lines
35	35	obj-$(CONFIG_SOC_IMX27) += clk-imx27.o
36	36	obj-$(CONFIG_SOC_IMX31) += clk-imx31.o
37	37	obj-$(CONFIG_SOC_IMX35) += clk-imx35.o
38		−obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o
	38	+obj-$(CONFIG_SOC_IMX5) += clk-imx5.o
39	39	obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o
40	40	obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
41	41	obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o

drivers/clk/imx/clk-imx5.crenamed from drivers/clk/imx/clk-imx51-imx53.c+45−14

@@ -164,10 +164,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) · 163 unmodified lines
164	164	clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
165	165	clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
166	166
167		− clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
168		− periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
169		− clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
170		− main_bus_sel, ARRAY_SIZE(main_bus_sel));
171	167	clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
172	168	per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
173	169	clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
@@ -191,16 +187,10 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) · 17 unmodified lines
191	187	clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
192	188	clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
193	189
194		− clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
195		− standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
196		− clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
197		− standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
198	190	clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
199	191	clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
200	192	clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
201	193	clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
202		− clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
203		− clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
204	194
205	195	clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
206	196	emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
@@ -311,10 +301,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) · 104 unmodified lines
311	301	clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
312	302	clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
313	303
314		− /* Set SDHC parents to be PLL2 */
315		− clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
316		− clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
317		−
318	304	/* move usb phy clk to 24MHz */
319	305	clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
320	306	}
@@ -342,8 +328,21 @@ static void __init mx50_clocks_init(struct device_node *np) · 21 unmodified lines
342	328
343	329	mx5_clocks_common_init(ccm_base);
344	330
	331	+ /*
	332	+ * This clock is called periph_clk in the i.MX50 Reference Manual, but
	333	+ * it comes closest in scope to the main_bus_clk of i.MX51 and i.MX53
	334	+ */
	335	+ clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 2,
	336	+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
	337	+
345	338	clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
346	339	lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
	340	+ clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 21, 2,
	341	+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
	342	+ clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
	343	+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
	344	+ clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 20, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
	345	+ clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
347	346	clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
348	347	clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
349	348	clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
@@ -372,6 +371,10 @@ static void __init mx50_clocks_init(struct device_node *np) · 22 unmodified lines
372	371	clk_data.clk_num = ARRAY_SIZE(clk);
373	372	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
374	373
	374	+ /* Set SDHC parents to be PLL2 */
	375	+ clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
	376	+ clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
	377	+
375	378	/* set SDHC root clock to 200MHZ*/
376	379	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
377	380	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -410,6 +413,10 @@ static void __init mx51_clocks_init(struct device_node *np) · 32 unmodified lines
410	413
411	414	mx5_clocks_common_init(ccm_base);
412	415
	416	+ clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
	417	+ periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
	418	+ clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
	419	+ main_bus_sel, ARRAY_SIZE(main_bus_sel));
413	420	clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
414	421	lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
415	422	clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
@@ -422,6 +429,12 @@ static void __init mx51_clocks_init(struct device_node *np) · 6 unmodified lines
422	429	mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
423	430	clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
424	431	clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
	432	+ clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
	433	+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
	434	+ clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
	435	+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
	436	+ clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
	437	+ clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
425	438	clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
426	439	clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
427	440	clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
@@ -452,6 +465,10 @@ static void __init mx51_clocks_init(struct device_node *np) · 24 unmodified lines
452	465	/* set the usboh3 parent to pll2_sw */
453	466	clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
454	467
	468	+ /* Set SDHC parents to be PLL2 */
	469	+ clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
	470	+ clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
	471	+
455	472	/* set SDHC root clock to 166.25MHZ*/
456	473	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
457	474	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
@@ -506,6 +523,10 @@ static void __init mx53_clocks_init(struct device_node *np) · 48 unmodified lines
506	523
507	524	mx5_clocks_common_init(ccm_base);
508	525
	526	+ clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
	527	+ periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
	528	+ clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
	529	+ main_bus_sel, ARRAY_SIZE(main_bus_sel));
509	530	clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
510	531	lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
511	532	clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
@@ -527,6 +548,12 @@ static void __init mx53_clocks_init(struct device_node *np) · 15 unmodified lines
527	548	mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
528	549	clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
529	550	clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
	551	+ clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
	552	+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
	553	+ clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
	554	+ standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
	555	+ clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
	556	+ clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
530	557	clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
531	558	clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
532	559	clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
@@ -589,6 +616,10 @@ static void __init mx53_clocks_init(struct device_node *np) · 56 unmodified lines
589	616	clk_data.clk_num = ARRAY_SIZE(clk);
590	617	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
591	618
	619	+ /* Set SDHC parents to be PLL2 */
	620	+ clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
	621	+ clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
	622	+
592	623	/* set SDHC root clock to 200MHZ*/
593	624	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
594	625	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);

drivers/clk/imx/clk-imx6sll.c+17−1

@@ -76,6 +76,20 @@ static u32 share_count_ssi1; · 75 unmodified lines
76	76	static u32 share_count_ssi2;
77	77	static u32 share_count_ssi3;
78	78
	79	+static struct clk ** const uart_clks[] __initconst = {
	80	+ &clks[IMX6SLL_CLK_UART1_IPG],
	81	+ &clks[IMX6SLL_CLK_UART1_SERIAL],
	82	+ &clks[IMX6SLL_CLK_UART2_IPG],
	83	+ &clks[IMX6SLL_CLK_UART2_SERIAL],
	84	+ &clks[IMX6SLL_CLK_UART3_IPG],
	85	+ &clks[IMX6SLL_CLK_UART3_SERIAL],
	86	+ &clks[IMX6SLL_CLK_UART4_IPG],
	87	+ &clks[IMX6SLL_CLK_UART4_SERIAL],
	88	+ &clks[IMX6SLL_CLK_UART5_IPG],
	89	+ &clks[IMX6SLL_CLK_UART5_SERIAL],
	90	+ NULL
	91	+};
	92	+
79	93	static void __init imx6sll_clocks_init(struct device_node *ccm_node)
80	94	{
81	95	struct device_node *np;
@@ -268,7 +282,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) · 186 unmodified lines
268	282	clks[IMX6SLL_CLK_GPT_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20);
269	283	clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
270	284	clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
271		− clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
	285	+ clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
272	286	clks[IMX6SLL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
273	287	clks[IMX6SLL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
274	288
@@ -334,6 +348,8 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) · 59 unmodified lines
334	348	clk_data.clk_num = ARRAY_SIZE(clks);
335	349	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
336	350
	351	+ imx_register_uart_clocks(uart_clks);
	352	+
337	353	/* Lower the AHB clock rate before changing the clock source. */
338	354	clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
339	355

drivers/clk/imx/clk-imx7d.c+2−2

@@ -417,8 +417,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) · 416 unmodified lines
417	417	clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f);
418	418	clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1);
419	419	clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0);
420		− clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f);
421		− clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "osc", base + 0x130, 0x7f);
	420	+ clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0xf0, 0x7f);
	421	+ clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x130, 0x7f);
422	422
423	423	clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT);
424	424	clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT);

drivers/clk/imx/clk-imx7ulp.c+0−1

@@ -151,7 +151,6 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np) · 150 unmodified lines
151	151	clks[IMX7ULP_CLK_DMA1] = imx_clk_hw_gate("dma1", "nic1_clk", base + 0x20, 30);
152	152	clks[IMX7ULP_CLK_RGPIO2P1] = imx_clk_hw_gate("rgpio2p1", "nic1_bus_clk", base + 0x3c, 30);
153	153	clks[IMX7ULP_CLK_DMA_MUX1] = imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30);
154		− clks[IMX7ULP_CLK_SNVS] = imx_clk_hw_gate("snvs", "nic1_bus_clk", base + 0x8c, 30);
155	154	clks[IMX7ULP_CLK_CAAM] = imx_clk_hw_gate("caam", "nic1_clk", base + 0x90, 30);
156	155	clks[IMX7ULP_CLK_LPTPM4] = imx7ulp_clk_composite("lptpm4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
157	156	clks[IMX7ULP_CLK_LPTPM5] = imx7ulp_clk_composite("lptpm5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);

drivers/clk/imx/clk-imx8mq.c+1−0

@@ -458,6 +458,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) · 457 unmodified lines
458	458	clks[IMX8MQ_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00);
459	459	clks[IMX8MQ_CLK_DSI_ESC] = imx8m_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80);
460	460	clks[IMX8MQ_CLK_DSI_AHB] = imx8m_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200);
	461	+ clks[IMX8MQ_CLK_DSI_IPG_DIV] = imx_clk_divider2("dsi_ipg_div", "dsi_ahb", base + 0x9280, 0, 6);
461	462	clks[IMX8MQ_CLK_CSI1_CORE] = imx8m_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00);
462	463	clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80);
463	464	clks[IMX8MQ_CLK_CSI1_ESC] = imx8m_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00);

drivers/clk/imx/clk-pfdv2.c+5−5

@@ -43,7 +43,7 @@ static int clk_pfdv2_wait(struct clk_pfdv2 *pfd) · 42 unmodified lines
43	43	{
44	44	u32 val;
45	45
46		− return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit,
	46	+ return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit),
47	47	0, LOCK_TIMEOUT_US);
48	48	}
49	49
@@ -55,7 +55,7 @@ static int clk_pfdv2_enable(struct clk_hw *hw) · 5 unmodified lines
55	55
56	56	spin_lock_irqsave(&pfd_lock, flags);
57	57	val = readl_relaxed(pfd->reg);
58		− val &= ~pfd->gate_bit;
	58	+ val &= ~(1 << pfd->gate_bit);
59	59	writel_relaxed(val, pfd->reg);
60	60	spin_unlock_irqrestore(&pfd_lock, flags);
61	61
@@ -70,7 +70,7 @@ static void clk_pfdv2_disable(struct clk_hw *hw) · 8 unmodified lines
70	70
71	71	spin_lock_irqsave(&pfd_lock, flags);
72	72	val = readl_relaxed(pfd->reg);
73		− val \|= pfd->gate_bit;
	73	+ val \|= (1 << pfd->gate_bit);
74	74	writel_relaxed(val, pfd->reg);
75	75	spin_unlock_irqrestore(&pfd_lock, flags);
76	76	}
@@ -123,7 +123,7 @@ static int clk_pfdv2_is_enabled(struct clk_hw *hw) · 46 unmodified lines
123	123	{
124	124	struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
125	125
126		− if (readl_relaxed(pfd->reg) & pfd->gate_bit)
	126	+ if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit))
127	127	return 0;
128	128
129	129	return 1;
@@ -180,7 +180,7 @@ struct clk_hw imx_clk_pfdv2(const char name, const char *parent_name, · 50 unmodified lines
180	180	return ERR_PTR(-ENOMEM);
181	181
182	182	pfd->reg = reg;
183		− pfd->gate_bit = 1 << ((idx + 1) * 8 - 1);
	183	+ pfd->gate_bit = (idx + 1) * 8 - 1;
184	184	pfd->vld_bit = pfd->gate_bit - 1;
185	185	pfd->frac_off = idx * 8;
186	186

drivers/clk/imx/clk-pll14xx.c+2−4

@@ -74,10 +74,9 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, · 73 unmodified lines
74	74	unsigned long parent_rate)
75	75	{
76	76	struct clk_pll14xx *pll = to_clk_pll14xx(hw);
77		− u32 mdiv, pdiv, sdiv, pll_gnrl, pll_div;
	77	+ u32 mdiv, pdiv, sdiv, pll_div;
78	78	u64 fvco = parent_rate;
79	79
80		− pll_gnrl = readl_relaxed(pll->base);
81	80	pll_div = readl_relaxed(pll->base + 4);
82	81	mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
83	82	pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
@@ -93,11 +92,10 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, · 9 unmodified lines
93	92	unsigned long parent_rate)
94	93	{
95	94	struct clk_pll14xx *pll = to_clk_pll14xx(hw);
96		− u32 mdiv, pdiv, sdiv, pll_gnrl, pll_div_ctl0, pll_div_ctl1;
	95	+ u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
97	96	short int kdiv;
98	97	u64 fvco = parent_rate;
99	98
100		− pll_gnrl = readl_relaxed(pll->base);
101	99	pll_div_ctl0 = readl_relaxed(pll->base + 4);
102	100	pll_div_ctl1 = readl_relaxed(pll->base + 8);
103	101	mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;

drivers/clk/imx/clk-pllv3.c+23−8

@@ -20,6 +20,8 @@ · 19 unmodified lines
20	20
21	21	#define PLL_NUM_OFFSET 0x10
22	22	#define PLL_DENOM_OFFSET 0x20
	23	+#define PLL_IMX7_NUM_OFFSET 0x20
	24	+#define PLL_IMX7_DENOM_OFFSET 0x30
23	25
24	26	#define PLL_VF610_NUM_OFFSET 0x20
25	27	#define PLL_VF610_DENOM_OFFSET 0x30
@@ -49,6 +51,8 @@ struct clk_pllv3 { · 23 unmodified lines
49	51	u32 div_mask;
50	52	u32 div_shift;
51	53	unsigned long ref_clock;
	54	+ u32 num_offset;
	55	+ u32 denom_offset;
52	56	};
53	57
54	58	#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@@ -219,8 +223,8 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, · 164 unmodified lines
219	223	unsigned long parent_rate)
220	224	{
221	225	struct clk_pllv3 *pll = to_clk_pllv3(hw);
222		− u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
223		− u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
	226	+ u32 mfn = readl_relaxed(pll->base + pll->num_offset);
	227	+ u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
224	228	u32 div = readl_relaxed(pll->base) & pll->div_mask;
225	229	u64 temp64 = (u64)parent_rate;
226	230
@@ -289,8 +293,8 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, · 62 unmodified lines
289	293	val &= ~pll->div_mask;
290	294	val \|= div;
291	295	writel_relaxed(val, pll->base);
292		− writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
293		− writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
	296	+ writel_relaxed(mfn, pll->base + pll->num_offset);
	297	+ writel_relaxed(mfd, pll->base + pll->denom_offset);
294	298
295	299	return clk_pllv3_wait_lock(pll);
296	300	}
@@ -352,8 +356,8 @@ static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw, · 55 unmodified lines
352	356	struct clk_pllv3 *pll = to_clk_pllv3(hw);
353	357	struct clk_pllv3_vf610_mf mf;
354	358
355		− mf.mfn = readl_relaxed(pll->base + PLL_VF610_NUM_OFFSET);
356		− mf.mfd = readl_relaxed(pll->base + PLL_VF610_DENOM_OFFSET);
	359	+ mf.mfn = readl_relaxed(pll->base + pll->num_offset);
	360	+ mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
357	361	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
358	362
359	363	return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
@@ -382,8 +386,8 @@ static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate, · 22 unmodified lines
382	386	val \|= pll->div_mask; /* set bit for mfi=22 */
383	387	writel_relaxed(val, pll->base);
384	388
385		− writel_relaxed(mf.mfn, pll->base + PLL_VF610_NUM_OFFSET);
386		− writel_relaxed(mf.mfd, pll->base + PLL_VF610_DENOM_OFFSET);
	389	+ writel_relaxed(mf.mfn, pll->base + pll->num_offset);
	390	+ writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
387	391
388	392	return clk_pllv3_wait_lock(pll);
389	393	}
@@ -426,6 +430,8 @@ struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name, · 36 unmodified lines
426	430	return ERR_PTR(-ENOMEM);
427	431
428	432	pll->power_bit = BM_PLL_POWER;
	433	+ pll->num_offset = PLL_NUM_OFFSET;
	434	+ pll->denom_offset = PLL_DENOM_OFFSET;
429	435
430	436	switch (type) {
431	437	case IMX_PLLV3_SYS:
@@ -433,13 +439,20 @@ struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name, · 1 unmodified line
433	439	break;
434	440	case IMX_PLLV3_SYS_VF610:
435	441	ops = &clk_pllv3_vf610_ops;
	442	+ pll->num_offset = PLL_VF610_NUM_OFFSET;
	443	+ pll->denom_offset = PLL_VF610_DENOM_OFFSET;
436	444	break;
437	445	case IMX_PLLV3_USB_VF610:
438	446	pll->div_shift = 1;
	447	+ /* fall through */
439	448	case IMX_PLLV3_USB:
440	449	ops = &clk_pllv3_ops;
441	450	pll->powerup_set = true;
442	451	break;
	452	+ case IMX_PLLV3_AV_IMX7:
	453	+ pll->num_offset = PLL_IMX7_NUM_OFFSET;
	454	+ pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
	455	+ /* fall through */
443	456	case IMX_PLLV3_AV:
444	457	ops = &clk_pllv3_av_ops;
445	458	break;
@@ -454,6 +467,8 @@ struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name, · 8 unmodified lines
454	467	break;
455	468	case IMX_PLLV3_DDR_IMX7:
456	469	pll->power_bit = IMX7_DDR_PLL_POWER;
	470	+ pll->num_offset = PLL_IMX7_NUM_OFFSET;
	471	+ pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
457	472	ops = &clk_pllv3_av_ops;
458	473	break;
459	474	default:

drivers/clk/imx/clk-pllv4.c+63−9

@@ -30,6 +30,9 @@ · 29 unmodified lines
30	30	/* PLL Denominator Register (xPLLDENOM) */
31	31	#define PLL_DENOM_OFFSET 0x14
32	32
	33	+#define MAX_MFD 0x3fffffff
	34	+#define DEFAULT_MFD 1000000
	35	+
33	36	struct clk_pllv4 {
34	37	struct clk_hw hw;
35	38	void __iomem *base;
@@ -64,13 +67,20 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw, · 28 unmodified lines
64	67	unsigned long parent_rate)
65	68	{
66	69	struct clk_pllv4 *pll = to_clk_pllv4(hw);
67		− u32 div;
	70	+ u32 mult, mfn, mfd;
	71	+ u64 temp64;
	72	+
	73	+ mult = readl_relaxed(pll->base + PLL_CFG_OFFSET);
	74	+ mult &= BM_PLL_MULT;
	75	+ mult >>= BP_PLL_MULT;
68	76
69		− div = readl_relaxed(pll->base + PLL_CFG_OFFSET);
70		− div &= BM_PLL_MULT;
71		− div >>= BP_PLL_MULT;
	77	+ mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
	78	+ mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
	79	+ temp64 = parent_rate;
	80	+ temp64 *= mfn;
	81	+ do_div(temp64, mfd);
72	82
73		− return parent_rate * div;
	83	+ return (parent_rate * mult) + (u32)temp64;
74	84	}
75	85
76	86	static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -78,14 +88,46 @@ static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, · 1 unmodified line
78	88	{
79	89	unsigned long parent_rate = *prate;
80	90	unsigned long round_rate, i;
	91	+ u32 mfn, mfd = DEFAULT_MFD;
	92	+ bool found = false;
	93	+ u64 temp64;
81	94
82	95	for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
83	96	round_rate = parent_rate * pllv4_mult_table[i];
84		− if (rate >= round_rate)
85		− return round_rate;
	97	+ if (rate >= round_rate) {
	98	+ found = true;
	99	+ break;
	100	+ }
	101	+ }
	102	+
	103	+ if (!found) {
	104	+ pr_warn("%s: unable to round rate %lu, parent rate %lu\n",
	105	+ clk_hw_get_name(hw), rate, parent_rate);
	106	+ return 0;
86	107	}
87	108
88		− return round_rate;
	109	+ if (parent_rate <= MAX_MFD)
	110	+ mfd = parent_rate;
	111	+
	112	+ temp64 = (u64)(rate - round_rate);
	113	+ temp64 *= mfd;
	114	+ do_div(temp64, parent_rate);
	115	+ mfn = temp64;
	116	+
	117	+ /*
	118	+ * NOTE: The value of numerator must always be configured to be
	119	+ * less than the value of the denominator. If we can't get a proper
	120	+ * pair of mfn/mfd, we simply return the round_rate without using
	121	+ * the frac part.
	122	+ */
	123	+ if (mfn >= mfd)
	124	+ return round_rate;
	125	+
	126	+ temp64 = (u64)parent_rate;
	127	+ temp64 *= mfn;
	128	+ do_div(temp64, mfd);
	129	+
	130	+ return round_rate + (u32)temp64;
89	131	}
90	132
91	133	static bool clk_pllv4_is_valid_mult(unsigned int mult)
@@ -105,18 +147,30 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, · 13 unmodified lines
105	147	unsigned long parent_rate)
106	148	{
107	149	struct clk_pllv4 *pll = to_clk_pllv4(hw);
108		− u32 val, mult;
	150	+ u32 val, mult, mfn, mfd = DEFAULT_MFD;
	151	+ u64 temp64;
109	152
110	153	mult = rate / parent_rate;
111	154
112	155	if (!clk_pllv4_is_valid_mult(mult))
113	156	return -EINVAL;
114	157
	158	+ if (parent_rate <= MAX_MFD)
	159	+ mfd = parent_rate;
	160	+
	161	+ temp64 = (u64)(rate - mult * parent_rate);
	162	+ temp64 *= mfd;
	163	+ do_div(temp64, parent_rate);
	164	+ mfn = temp64;
	165	+
115	166	val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
116	167	val &= ~BM_PLL_MULT;
117	168	val \|= mult << BP_PLL_MULT;
118	169	writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
119	170
	171	+ writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
	172	+ writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
	173	+
120	174	return 0;
121	175	}
122	176

drivers/clk/imx/clk.h+1−5

@@ -77,6 +77,7 @@ enum imx_pllv3_type { · 76 unmodified lines
77	77	IMX_PLLV3_ENET_IMX7,
78	78	IMX_PLLV3_SYS_VF610,
79	79	IMX_PLLV3_DDR_IMX7,
	80	+ IMX_PLLV3_AV_IMX7,
80	81	};
81	82
82	83	struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name,
@@ -138,11 +139,6 @@ static inline struct clk_hw imx_clk_hw_fixed(const char name, int rate) · 55 unmodified lines
138	139	return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
139	140	}
140	141
141		−static inline struct clk_hw imx_get_clk_hw_fixed(const char name, int rate)
142		−{
143		− return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
144		−}
145		−
146	142	static inline struct clk imx_clk_mux_ldb(const char name, void __iomem *reg,
147	143	u8 shift, u8 width, const char * const *parents,
148	144	int num_parents)

drivers/clk/mediatek/Kconfig+83−0

@@ -216,4 +216,87 @@ config COMMON_CLK_MT8173 · 215 unmodified lines
216	216	default ARCH_MEDIATEK
217	217	---help---
218	218	This driver supports MediaTek MT8173 clocks.
	219	+
	220	+config COMMON_CLK_MT8183
	221	+ bool "Clock driver for MediaTek MT8183"
	222	+ depends on (ARCH_MEDIATEK && ARM64) \|\| COMPILE_TEST
	223	+ select COMMON_CLK_MEDIATEK
	224	+ default ARCH_MEDIATEK && ARM64
	225	+ help
	226	+ This driver supports MediaTek MT8183 basic clocks.
	227	+
	228	+config COMMON_CLK_MT8183_AUDIOSYS
	229	+ bool "Clock driver for MediaTek MT8183 audiosys"
	230	+ depends on COMMON_CLK_MT8183
	231	+ help
	232	+ This driver supports MediaTek MT8183 audiosys clocks.
	233	+
	234	+config COMMON_CLK_MT8183_CAMSYS
	235	+ bool "Clock driver for MediaTek MT8183 camsys"
	236	+ depends on COMMON_CLK_MT8183
	237	+ help
	238	+ This driver supports MediaTek MT8183 camsys clocks.
	239	+
	240	+config COMMON_CLK_MT8183_IMGSYS
	241	+ bool "Clock driver for MediaTek MT8183 imgsys"
	242	+ depends on COMMON_CLK_MT8183
	243	+ help
	244	+ This driver supports MediaTek MT8183 imgsys clocks.
	245	+
	246	+config COMMON_CLK_MT8183_IPU_CORE0
	247	+ bool "Clock driver for MediaTek MT8183 ipu_core0"
	248	+ depends on COMMON_CLK_MT8183
	249	+ help
	250	+ This driver supports MediaTek MT8183 ipu_core0 clocks.
	251	+
	252	+config COMMON_CLK_MT8183_IPU_CORE1
	253	+ bool "Clock driver for MediaTek MT8183 ipu_core1"
	254	+ depends on COMMON_CLK_MT8183
	255	+ help
	256	+ This driver supports MediaTek MT8183 ipu_core1 clocks.
	257	+
	258	+config COMMON_CLK_MT8183_IPU_ADL
	259	+ bool "Clock driver for MediaTek MT8183 ipu_adl"
	260	+ depends on COMMON_CLK_MT8183
	261	+ help
	262	+ This driver supports MediaTek MT8183 ipu_adl clocks.
	263	+
	264	+config COMMON_CLK_MT8183_IPU_CONN
	265	+ bool "Clock driver for MediaTek MT8183 ipu_conn"
	266	+ depends on COMMON_CLK_MT8183
	267	+ help
	268	+ This driver supports MediaTek MT8183 ipu_conn clocks.
	269	+
	270	+config COMMON_CLK_MT8183_MFGCFG
	271	+ bool "Clock driver for MediaTek MT8183 mfgcfg"
	272	+ depends on COMMON_CLK_MT8183
	273	+ help
	274	+ This driver supports MediaTek MT8183 mfgcfg clocks.
	275	+
	276	+config COMMON_CLK_MT8183_MMSYS
	277	+ bool "Clock driver for MediaTek MT8183 mmsys"
	278	+ depends on COMMON_CLK_MT8183
	279	+ help
	280	+ This driver supports MediaTek MT8183 mmsys clocks.
	281	+
	282	+config COMMON_CLK_MT8183_VDECSYS
	283	+ bool "Clock driver for MediaTek MT8183 vdecsys"
	284	+ depends on COMMON_CLK_MT8183
	285	+ help
	286	+ This driver supports MediaTek MT8183 vdecsys clocks.
	287	+
	288	+config COMMON_CLK_MT8183_VENCSYS
	289	+ bool "Clock driver for MediaTek MT8183 vencsys"
	290	+ depends on COMMON_CLK_MT8183
	291	+ help
	292	+ This driver supports MediaTek MT8183 vencsys clocks.
	293	+
	294	+config COMMON_CLK_MT8516
	295	+ bool "Clock driver for MediaTek MT8516"
	296	+ depends on ARCH_MEDIATEK \|\| COMPILE_TEST
	297	+ select COMMON_CLK_MEDIATEK
	298	+ default ARCH_MEDIATEK
	299	+ help
	300	+ This driver supports MediaTek MT8516 clocks.
	301	+
219	302	endmenu

drivers/clk/mediatek/Makefile+15−1

@@ -1,5 +1,6 @@
1	1	# SPDX-License-Identifier: GPL-2.0
2		−obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o
	2	+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
	3	+
3	4	obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
4	5	obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
5	6	obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
@@ -31,3 +32,16 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o · 25 unmodified lines
31	32	obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
32	33	obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
33	34	obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
	35	+obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
	36	+obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o
	37	+obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o
	38	+obj-$(CONFIG_COMMON_CLK_MT8183_IMGSYS) += clk-mt8183-img.o
	39	+obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE0) += clk-mt8183-ipu0.o
	40	+obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE1) += clk-mt8183-ipu1.o
	41	+obj-$(CONFIG_COMMON_CLK_MT8183_IPU_ADL) += clk-mt8183-ipu_adl.o
	42	+obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CONN) += clk-mt8183-ipu_conn.o
	43	+obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
	44	+obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
	45	+obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
	46	+obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
	47	+obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o

drivers/clk/mediatek/clk-gate.h+14−0

@@ -50,4 +50,18 @@ struct clk *mtk_clk_register_gate( · 49 unmodified lines
50	50	const struct clk_ops *ops,
51	51	unsigned long flags);
52	52
	53	+#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
	54	+ _ops, _flags) { \
	55	+ .id = _id, \
	56	+ .name = _name, \
	57	+ .parent_name = _parent, \
	58	+ .regs = _regs, \
	59	+ .shift = _shift, \
	60	+ .ops = _ops, \
	61	+ .flags = _flags, \
	62	+ }
	63	+
	64	+#define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
	65	+ GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
	66	+
53	67	#endif /* __DRV_CLK_GATE_H */

drivers/clk/mediatek/clk-mt8183-audio.c+105−0

@@ -0,0 +1,105 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/of_platform.h>
	8	+#include <linux/platform_device.h>
	9	+
	10	+#include "clk-mtk.h"
	11	+#include "clk-gate.h"
	12	+
	13	+#include <dt-bindings/clock/mt8183-clk.h>
	14	+
	15	+static const struct mtk_gate_regs audio0_cg_regs = {
	16	+ .set_ofs = 0x0,
	17	+ .clr_ofs = 0x0,
	18	+ .sta_ofs = 0x0,
	19	+};
	20	+
	21	+static const struct mtk_gate_regs audio1_cg_regs = {
	22	+ .set_ofs = 0x4,
	23	+ .clr_ofs = 0x4,
	24	+ .sta_ofs = 0x4,
	25	+};
	26	+
	27	+#define GATE_AUDIO0(_id, _name, _parent, _shift) \
	28	+ GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
	29	+ &mtk_clk_gate_ops_no_setclr)
	30	+
	31	+#define GATE_AUDIO1(_id, _name, _parent, _shift) \
	32	+ GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
	33	+ &mtk_clk_gate_ops_no_setclr)
	34	+
	35	+static const struct mtk_gate audio_clks[] = {
	36	+ /* AUDIO0 */
	37	+ GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
	38	+ 2),
	39	+ GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
	40	+ 8),
	41	+ GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
	42	+ 9),
	43	+ GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
	44	+ 18),
	45	+ GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
	46	+ 19),
	47	+ GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
	48	+ 20),
	49	+ GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
	50	+ 24),
	51	+ GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
	52	+ 25),
	53	+ GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
	54	+ 26),
	55	+ GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
	56	+ 27),
	57	+ /* AUDIO1 */
	58	+ GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
	59	+ 4),
	60	+ GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
	61	+ 5),
	62	+ GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
	63	+ 6),
	64	+ GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
	65	+ 7),
	66	+ GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
	67	+ 20),
	68	+};
	69	+
	70	+static int clk_mt8183_audio_probe(struct platform_device *pdev)
	71	+{
	72	+ struct clk_onecell_data *clk_data;
	73	+ int r;
	74	+ struct device_node *node = pdev->dev.of_node;
	75	+
	76	+ clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
	77	+
	78	+ mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
	79	+ clk_data);
	80	+
	81	+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	82	+ if (r)
	83	+ return r;
	84	+
	85	+ r = devm_of_platform_populate(&pdev->dev);
	86	+ if (r)
	87	+ of_clk_del_provider(node);
	88	+
	89	+ return r;
	90	+}
	91	+
	92	+static const struct of_device_id of_match_clk_mt8183_audio[] = {
	93	+ { .compatible = "mediatek,mt8183-audiosys", },
	94	+ {}
	95	+};
	96	+
	97	+static struct platform_driver clk_mt8183_audio_drv = {
	98	+ .probe = clk_mt8183_audio_probe,
	99	+ .driver = {
	100	+ .name = "clk-mt8183-audio",
	101	+ .of_match_table = of_match_clk_mt8183_audio,
	102	+ },
	103	+};
	104	+
	105	+builtin_platform_driver(clk_mt8183_audio_drv);

drivers/clk/mediatek/clk-mt8183-cam.c+63−0

@@ -0,0 +1,63 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs cam_cg_regs = {
	15	+ .set_ofs = 0x4,
	16	+ .clr_ofs = 0x8,
	17	+ .sta_ofs = 0x0,
	18	+};
	19	+
	20	+#define GATE_CAM(_id, _name, _parent, _shift) \
	21	+ GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
	22	+ &mtk_clk_gate_ops_setclr)
	23	+
	24	+static const struct mtk_gate cam_clks[] = {
	25	+ GATE_CAM(CLK_CAM_LARB6, "cam_larb6", "cam_sel", 0),
	26	+ GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
	27	+ GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "cam_sel", 2),
	28	+ GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
	29	+ GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
	30	+ GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
	31	+ GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
	32	+ GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
	33	+ GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
	34	+ GATE_CAM(CLK_CAM_CCU, "cam_ccu", "cam_sel", 12),
	35	+};
	36	+
	37	+static int clk_mt8183_cam_probe(struct platform_device *pdev)
	38	+{
	39	+ struct clk_onecell_data *clk_data;
	40	+ struct device_node *node = pdev->dev.of_node;
	41	+
	42	+ clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
	43	+
	44	+ mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
	45	+ clk_data);
	46	+
	47	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	48	+}
	49	+
	50	+static const struct of_device_id of_match_clk_mt8183_cam[] = {
	51	+ { .compatible = "mediatek,mt8183-camsys", },
	52	+ {}
	53	+};
	54	+
	55	+static struct platform_driver clk_mt8183_cam_drv = {
	56	+ .probe = clk_mt8183_cam_probe,
	57	+ .driver = {
	58	+ .name = "clk-mt8183-cam",
	59	+ .of_match_table = of_match_clk_mt8183_cam,
	60	+ },
	61	+};
	62	+
	63	+builtin_platform_driver(clk_mt8183_cam_drv);

drivers/clk/mediatek/clk-mt8183-img.c+63−0

@@ -0,0 +1,63 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs img_cg_regs = {
	15	+ .set_ofs = 0x4,
	16	+ .clr_ofs = 0x8,
	17	+ .sta_ofs = 0x0,
	18	+};
	19	+
	20	+#define GATE_IMG(_id, _name, _parent, _shift) \
	21	+ GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
	22	+ &mtk_clk_gate_ops_setclr)
	23	+
	24	+static const struct mtk_gate img_clks[] = {
	25	+ GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
	26	+ GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
	27	+ GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
	28	+ GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
	29	+ GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
	30	+ GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
	31	+ GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
	32	+ GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
	33	+ GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
	34	+ GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
	35	+};
	36	+
	37	+static int clk_mt8183_img_probe(struct platform_device *pdev)
	38	+{
	39	+ struct clk_onecell_data *clk_data;
	40	+ struct device_node *node = pdev->dev.of_node;
	41	+
	42	+ clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
	43	+
	44	+ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
	45	+ clk_data);
	46	+
	47	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	48	+}
	49	+
	50	+static const struct of_device_id of_match_clk_mt8183_img[] = {
	51	+ { .compatible = "mediatek,mt8183-imgsys", },
	52	+ {}
	53	+};
	54	+
	55	+static struct platform_driver clk_mt8183_img_drv = {
	56	+ .probe = clk_mt8183_img_probe,
	57	+ .driver = {
	58	+ .name = "clk-mt8183-img",
	59	+ .of_match_table = of_match_clk_mt8183_img,
	60	+ },
	61	+};
	62	+
	63	+builtin_platform_driver(clk_mt8183_img_drv);

drivers/clk/mediatek/clk-mt8183-ipu0.c+56−0

@@ -0,0 +1,56 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs ipu_core0_cg_regs = {
	15	+ .set_ofs = 0x4,
	16	+ .clr_ofs = 0x8,
	17	+ .sta_ofs = 0x0,
	18	+};
	19	+
	20	+#define GATE_IPU_CORE0(_id, _name, _parent, _shift) \
	21	+ GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift, \
	22	+ &mtk_clk_gate_ops_setclr)
	23	+
	24	+static const struct mtk_gate ipu_core0_clks[] = {
	25	+ GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG, "ipu_core0_jtag", "dsp_sel", 0),
	26	+ GATE_IPU_CORE0(CLK_IPU_CORE0_AXI, "ipu_core0_axi", "dsp_sel", 1),
	27	+ GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
	28	+};
	29	+
	30	+static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
	31	+{
	32	+ struct clk_onecell_data *clk_data;
	33	+ struct device_node *node = pdev->dev.of_node;
	34	+
	35	+ clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
	36	+
	37	+ mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
	38	+ clk_data);
	39	+
	40	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	41	+}
	42	+
	43	+static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
	44	+ { .compatible = "mediatek,mt8183-ipu_core0", },
	45	+ {}
	46	+};
	47	+
	48	+static struct platform_driver clk_mt8183_ipu_core0_drv = {
	49	+ .probe = clk_mt8183_ipu_core0_probe,
	50	+ .driver = {
	51	+ .name = "clk-mt8183-ipu_core0",
	52	+ .of_match_table = of_match_clk_mt8183_ipu_core0,
	53	+ },
	54	+};
	55	+
	56	+builtin_platform_driver(clk_mt8183_ipu_core0_drv);

drivers/clk/mediatek/clk-mt8183-ipu1.c+56−0

@@ -0,0 +1,56 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs ipu_core1_cg_regs = {
	15	+ .set_ofs = 0x4,
	16	+ .clr_ofs = 0x8,
	17	+ .sta_ofs = 0x0,
	18	+};
	19	+
	20	+#define GATE_IPU_CORE1(_id, _name, _parent, _shift) \
	21	+ GATE_MTK(_id, _name, _parent, &ipu_core1_cg_regs, _shift, \
	22	+ &mtk_clk_gate_ops_setclr)
	23	+
	24	+static const struct mtk_gate ipu_core1_clks[] = {
	25	+ GATE_IPU_CORE1(CLK_IPU_CORE1_JTAG, "ipu_core1_jtag", "dsp_sel", 0),
	26	+ GATE_IPU_CORE1(CLK_IPU_CORE1_AXI, "ipu_core1_axi", "dsp_sel", 1),
	27	+ GATE_IPU_CORE1(CLK_IPU_CORE1_IPU, "ipu_core1_ipu", "dsp_sel", 2),
	28	+};
	29	+
	30	+static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
	31	+{
	32	+ struct clk_onecell_data *clk_data;
	33	+ struct device_node *node = pdev->dev.of_node;
	34	+
	35	+ clk_data = mtk_alloc_clk_data(CLK_IPU_CORE1_NR_CLK);
	36	+
	37	+ mtk_clk_register_gates(node, ipu_core1_clks, ARRAY_SIZE(ipu_core1_clks),
	38	+ clk_data);
	39	+
	40	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	41	+}
	42	+
	43	+static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = {
	44	+ { .compatible = "mediatek,mt8183-ipu_core1", },
	45	+ {}
	46	+};
	47	+
	48	+static struct platform_driver clk_mt8183_ipu_core1_drv = {
	49	+ .probe = clk_mt8183_ipu_core1_probe,
	50	+ .driver = {
	51	+ .name = "clk-mt8183-ipu_core1",
	52	+ .of_match_table = of_match_clk_mt8183_ipu_core1,
	53	+ },
	54	+};
	55	+
	56	+builtin_platform_driver(clk_mt8183_ipu_core1_drv);

drivers/clk/mediatek/clk-mt8183-ipu_adl.c+54−0

@@ -0,0 +1,54 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs ipu_adl_cg_regs = {
	15	+ .set_ofs = 0x204,
	16	+ .clr_ofs = 0x204,
	17	+ .sta_ofs = 0x204,
	18	+};
	19	+
	20	+#define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \
	21	+ GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \
	22	+ &mtk_clk_gate_ops_no_setclr_inv)
	23	+
	24	+static const struct mtk_gate ipu_adl_clks[] = {
	25	+ GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
	26	+};
	27	+
	28	+static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
	29	+{
	30	+ struct clk_onecell_data *clk_data;
	31	+ struct device_node *node = pdev->dev.of_node;
	32	+
	33	+ clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
	34	+
	35	+ mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
	36	+ clk_data);
	37	+
	38	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	39	+}
	40	+
	41	+static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
	42	+ { .compatible = "mediatek,mt8183-ipu_adl", },
	43	+ {}
	44	+};
	45	+
	46	+static struct platform_driver clk_mt8183_ipu_adl_drv = {
	47	+ .probe = clk_mt8183_ipu_adl_probe,
	48	+ .driver = {
	49	+ .name = "clk-mt8183-ipu_adl",
	50	+ .of_match_table = of_match_clk_mt8183_ipu_adl,
	51	+ },
	52	+};
	53	+
	54	+builtin_platform_driver(clk_mt8183_ipu_adl_drv);

drivers/clk/mediatek/clk-mt8183-ipu_conn.c+123−0

@@ -0,0 +1,123 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs ipu_conn_cg_regs = {
	15	+ .set_ofs = 0x4,
	16	+ .clr_ofs = 0x8,
	17	+ .sta_ofs = 0x0,
	18	+};
	19	+
	20	+static const struct mtk_gate_regs ipu_conn_apb_cg_regs = {
	21	+ .set_ofs = 0x10,
	22	+ .clr_ofs = 0x10,
	23	+ .sta_ofs = 0x10,
	24	+};
	25	+
	26	+static const struct mtk_gate_regs ipu_conn_axi_cg_regs = {
	27	+ .set_ofs = 0x18,
	28	+ .clr_ofs = 0x18,
	29	+ .sta_ofs = 0x18,
	30	+};
	31	+
	32	+static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = {
	33	+ .set_ofs = 0x1c,
	34	+ .clr_ofs = 0x1c,
	35	+ .sta_ofs = 0x1c,
	36	+};
	37	+
	38	+static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = {
	39	+ .set_ofs = 0x20,
	40	+ .clr_ofs = 0x20,
	41	+ .sta_ofs = 0x20,
	42	+};
	43	+
	44	+#define GATE_IPU_CONN(_id, _name, _parent, _shift) \
	45	+ GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
	46	+ &mtk_clk_gate_ops_setclr)
	47	+
	48	+#define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
	49	+ GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
	50	+ &mtk_clk_gate_ops_no_setclr)
	51	+
	52	+#define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
	53	+ GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
	54	+ &mtk_clk_gate_ops_no_setclr_inv)
	55	+
	56	+#define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
	57	+ GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
	58	+ &mtk_clk_gate_ops_no_setclr_inv)
	59	+
	60	+#define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
	61	+ GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
	62	+ &mtk_clk_gate_ops_no_setclr_inv)
	63	+
	64	+static const struct mtk_gate ipu_conn_clks[] = {
	65	+ GATE_IPU_CONN(CLK_IPU_CONN_IPU,
	66	+ "ipu_conn_ipu", "dsp_sel", 0),
	67	+ GATE_IPU_CONN(CLK_IPU_CONN_AHB,
	68	+ "ipu_conn_ahb", "dsp_sel", 1),
	69	+ GATE_IPU_CONN(CLK_IPU_CONN_AXI,
	70	+ "ipu_conn_axi", "dsp_sel", 2),
	71	+ GATE_IPU_CONN(CLK_IPU_CONN_ISP,
	72	+ "ipu_conn_isp", "dsp_sel", 3),
	73	+ GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL,
	74	+ "ipu_conn_cam_adl", "dsp_sel", 4),
	75	+ GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL,
	76	+ "ipu_conn_img_adl", "dsp_sel", 5),
	77	+ GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX,
	78	+ "ipu_conn_dap_rx", "dsp1_sel", 0),
	79	+ GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI,
	80	+ "ipu_conn_apb2axi", "dsp1_sel", 3),
	81	+ GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB,
	82	+ "ipu_conn_apb2ahb", "dsp1_sel", 20),
	83	+ GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2,
	84	+ "ipu_conn_ipu_cab1to2", "dsp1_sel", 6),
	85	+ GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2,
	86	+ "ipu_conn_ipu1_cab1to2", "dsp1_sel", 13),
	87	+ GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2,
	88	+ "ipu_conn_ipu2_cab1to2", "dsp1_sel", 20),
	89	+ GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3,
	90	+ "ipu_conn_cab3to3", "dsp1_sel", 0),
	91	+ GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1,
	92	+ "ipu_conn_cab2to1", "dsp1_sel", 14),
	93	+ GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE,
	94	+ "ipu_conn_cab3to1_slice", "dsp1_sel", 17),
	95	+};
	96	+
	97	+static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
	98	+{
	99	+ struct clk_onecell_data *clk_data;
	100	+ struct device_node *node = pdev->dev.of_node;
	101	+
	102	+ clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
	103	+
	104	+ mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
	105	+ clk_data);
	106	+
	107	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	108	+}
	109	+
	110	+static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
	111	+ { .compatible = "mediatek,mt8183-ipu_conn", },
	112	+ {}
	113	+};
	114	+
	115	+static struct platform_driver clk_mt8183_ipu_conn_drv = {
	116	+ .probe = clk_mt8183_ipu_conn_probe,
	117	+ .driver = {
	118	+ .name = "clk-mt8183-ipu_conn",
	119	+ .of_match_table = of_match_clk_mt8183_ipu_conn,
	120	+ },
	121	+};
	122	+
	123	+builtin_platform_driver(clk_mt8183_ipu_conn_drv);

drivers/clk/mediatek/clk-mt8183-mfgcfg.c+54−0

@@ -0,0 +1,54 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs mfg_cg_regs = {
	15	+ .set_ofs = 0x4,
	16	+ .clr_ofs = 0x8,
	17	+ .sta_ofs = 0x0,
	18	+};
	19	+
	20	+#define GATE_MFG(_id, _name, _parent, _shift) \
	21	+ GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
	22	+ &mtk_clk_gate_ops_setclr)
	23	+
	24	+static const struct mtk_gate mfg_clks[] = {
	25	+ GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
	26	+};
	27	+
	28	+static int clk_mt8183_mfg_probe(struct platform_device *pdev)
	29	+{
	30	+ struct clk_onecell_data *clk_data;
	31	+ struct device_node *node = pdev->dev.of_node;
	32	+
	33	+ clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
	34	+
	35	+ mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
	36	+ clk_data);
	37	+
	38	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	39	+}
	40	+
	41	+static const struct of_device_id of_match_clk_mt8183_mfg[] = {
	42	+ { .compatible = "mediatek,mt8183-mfgcfg", },
	43	+ {}
	44	+};
	45	+
	46	+static struct platform_driver clk_mt8183_mfg_drv = {
	47	+ .probe = clk_mt8183_mfg_probe,
	48	+ .driver = {
	49	+ .name = "clk-mt8183-mfg",
	50	+ .of_match_table = of_match_clk_mt8183_mfg,
	51	+ },
	52	+};
	53	+
	54	+builtin_platform_driver(clk_mt8183_mfg_drv);

drivers/clk/mediatek/clk-mt8183-mm.c+111−0

@@ -0,0 +1,111 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs mm0_cg_regs = {
	15	+ .set_ofs = 0x104,
	16	+ .clr_ofs = 0x108,
	17	+ .sta_ofs = 0x100,
	18	+};
	19	+
	20	+static const struct mtk_gate_regs mm1_cg_regs = {
	21	+ .set_ofs = 0x114,
	22	+ .clr_ofs = 0x118,
	23	+ .sta_ofs = 0x110,
	24	+};
	25	+
	26	+#define GATE_MM0(_id, _name, _parent, _shift) \
	27	+ GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
	28	+ &mtk_clk_gate_ops_setclr)
	29	+
	30	+#define GATE_MM1(_id, _name, _parent, _shift) \
	31	+ GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
	32	+ &mtk_clk_gate_ops_setclr)
	33	+
	34	+static const struct mtk_gate mm_clks[] = {
	35	+ /* MM0 */
	36	+ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
	37	+ GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
	38	+ GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
	39	+ GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
	40	+ GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
	41	+ GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
	42	+ GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
	43	+ GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
	44	+ GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
	45	+ GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
	46	+ GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
	47	+ GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
	48	+ GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
	49	+ GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
	50	+ GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
	51	+ GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
	52	+ GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
	53	+ GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
	54	+ GATE_MM0(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 18),
	55	+ GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
	56	+ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
	57	+ GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
	58	+ GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
	59	+ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
	60	+ GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
	61	+ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
	62	+ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
	63	+ GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
	64	+ GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
	65	+ GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
	66	+ GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
	67	+ GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
	68	+ /* MM1 */
	69	+ GATE_MM1(CLK_MM_DSI0_MM, "mm_dsi0_mm", "mm_sel", 0),
	70	+ GATE_MM1(CLK_MM_DSI0_IF, "mm_dsi0_if", "mm_sel", 1),
	71	+ GATE_MM1(CLK_MM_DPI_MM, "mm_dpi_mm", "mm_sel", 2),
	72	+ GATE_MM1(CLK_MM_DPI_IF, "mm_dpi_if", "dpi0_sel", 3),
	73	+ GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
	74	+ GATE_MM1(CLK_MM_MDP_DL_RX, "mm_mdp_dl_rx", "mm_sel", 5),
	75	+ GATE_MM1(CLK_MM_IPU_DL_RX, "mm_ipu_dl_rx", "mm_sel", 6),
	76	+ GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
	77	+ GATE_MM1(CLK_MM_MMSYS_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
	78	+ GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
	79	+ GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
	80	+ GATE_MM1(CLK_MM_MDP_CCORR, "mm_mdp_ccorr", "mm_sel", 11),
	81	+ GATE_MM1(CLK_MM_DBI_MM, "mm_dbi_mm", "mm_sel", 12),
	82	+ GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13),
	83	+};
	84	+
	85	+static int clk_mt8183_mm_probe(struct platform_device *pdev)
	86	+{
	87	+ struct clk_onecell_data *clk_data;
	88	+ struct device_node *node = pdev->dev.of_node;
	89	+
	90	+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
	91	+
	92	+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
	93	+ clk_data);
	94	+
	95	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	96	+}
	97	+
	98	+static const struct of_device_id of_match_clk_mt8183_mm[] = {
	99	+ { .compatible = "mediatek,mt8183-mmsys", },
	100	+ {}
	101	+};
	102	+
	103	+static struct platform_driver clk_mt8183_mm_drv = {
	104	+ .probe = clk_mt8183_mm_probe,
	105	+ .driver = {
	106	+ .name = "clk-mt8183-mm",
	107	+ .of_match_table = of_match_clk_mt8183_mm,
	108	+ },
	109	+};
	110	+
	111	+builtin_platform_driver(clk_mt8183_mm_drv);

drivers/clk/mediatek/clk-mt8183-vdec.c+67−0

@@ -0,0 +1,67 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs vdec0_cg_regs = {
	15	+ .set_ofs = 0x0,
	16	+ .clr_ofs = 0x4,
	17	+ .sta_ofs = 0x0,
	18	+};
	19	+
	20	+static const struct mtk_gate_regs vdec1_cg_regs = {
	21	+ .set_ofs = 0x8,
	22	+ .clr_ofs = 0xc,
	23	+ .sta_ofs = 0x8,
	24	+};
	25	+
	26	+#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
	27	+ GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
	28	+ &mtk_clk_gate_ops_setclr_inv)
	29	+
	30	+#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
	31	+ GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
	32	+ &mtk_clk_gate_ops_setclr_inv)
	33	+
	34	+static const struct mtk_gate vdec_clks[] = {
	35	+ /* VDEC0 */
	36	+ GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
	37	+ /* VDEC1 */
	38	+ GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
	39	+};
	40	+
	41	+static int clk_mt8183_vdec_probe(struct platform_device *pdev)
	42	+{
	43	+ struct clk_onecell_data *clk_data;
	44	+ struct device_node *node = pdev->dev.of_node;
	45	+
	46	+ clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
	47	+
	48	+ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
	49	+ clk_data);
	50	+
	51	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	52	+}
	53	+
	54	+static const struct of_device_id of_match_clk_mt8183_vdec[] = {
	55	+ { .compatible = "mediatek,mt8183-vdecsys", },
	56	+ {}
	57	+};
	58	+
	59	+static struct platform_driver clk_mt8183_vdec_drv = {
	60	+ .probe = clk_mt8183_vdec_probe,
	61	+ .driver = {
	62	+ .name = "clk-mt8183-vdec",
	63	+ .of_match_table = of_match_clk_mt8183_vdec,
	64	+ },
	65	+};
	66	+
	67	+builtin_platform_driver(clk_mt8183_vdec_drv);

drivers/clk/mediatek/clk-mt8183-venc.c+59−0

@@ -0,0 +1,59 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/platform_device.h>
	8	+
	9	+#include "clk-mtk.h"
	10	+#include "clk-gate.h"
	11	+
	12	+#include <dt-bindings/clock/mt8183-clk.h>
	13	+
	14	+static const struct mtk_gate_regs venc_cg_regs = {
	15	+ .set_ofs = 0x4,
	16	+ .clr_ofs = 0x8,
	17	+ .sta_ofs = 0x0,
	18	+};
	19	+
	20	+#define GATE_VENC_I(_id, _name, _parent, _shift) \
	21	+ GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
	22	+ &mtk_clk_gate_ops_setclr_inv)
	23	+
	24	+static const struct mtk_gate venc_clks[] = {
	25	+ GATE_VENC_I(CLK_VENC_LARB, "venc_larb",
	26	+ "mm_sel", 0),
	27	+ GATE_VENC_I(CLK_VENC_VENC, "venc_venc",
	28	+ "mm_sel", 4),
	29	+ GATE_VENC_I(CLK_VENC_JPGENC, "venc_jpgenc",
	30	+ "mm_sel", 8),
	31	+};
	32	+
	33	+static int clk_mt8183_venc_probe(struct platform_device *pdev)
	34	+{
	35	+ struct clk_onecell_data *clk_data;
	36	+ struct device_node *node = pdev->dev.of_node;
	37	+
	38	+ clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
	39	+
	40	+ mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
	41	+ clk_data);
	42	+
	43	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	44	+}
	45	+
	46	+static const struct of_device_id of_match_clk_mt8183_venc[] = {
	47	+ { .compatible = "mediatek,mt8183-vencsys", },
	48	+ {}
	49	+};
	50	+
	51	+static struct platform_driver clk_mt8183_venc_drv = {
	52	+ .probe = clk_mt8183_venc_probe,
	53	+ .driver = {
	54	+ .name = "clk-mt8183-venc",
	55	+ .of_match_table = of_match_clk_mt8183_venc,
	56	+ },
	57	+};
	58	+
	59	+builtin_platform_driver(clk_mt8183_venc_drv);

drivers/clk/mediatek/clk-mt8183.c+1284−0

@@ -0,0 +1,1284 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2018 MediaTek Inc.
	4	+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+
	6	+#include <linux/delay.h>
	7	+#include <linux/mfd/syscon.h>
	8	+#include <linux/of.h>
	9	+#include <linux/of_address.h>
	10	+#include <linux/of_device.h>
	11	+#include <linux/platform_device.h>
	12	+#include <linux/slab.h>
	13	+
	14	+#include "clk-mtk.h"
	15	+#include "clk-mux.h"
	16	+#include "clk-gate.h"
	17	+
	18	+#include <dt-bindings/clock/mt8183-clk.h>
	19	+
	20	+static DEFINE_SPINLOCK(mt8183_clk_lock);
	21	+
	22	+static const struct mtk_fixed_clk top_fixed_clks[] = {
	23	+ FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
	24	+ FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
	25	+ FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
	26	+};
	27	+
	28	+static const struct mtk_fixed_factor top_divs[] = {
	29	+ FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1,
	30	+ 2),
	31	+ FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
	32	+ 2),
	33	+ FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
	34	+ 1),
	35	+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
	36	+ 2),
	37	+ FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1,
	38	+ 2),
	39	+ FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1,
	40	+ 4),
	41	+ FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1,
	42	+ 8),
	43	+ FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1,
	44	+ 16),
	45	+ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1,
	46	+ 3),
	47	+ FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1,
	48	+ 2),
	49	+ FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1,
	50	+ 4),
	51	+ FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1,
	52	+ 8),
	53	+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1,
	54	+ 5),
	55	+ FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1,
	56	+ 2),
	57	+ FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1,
	58	+ 4),
	59	+ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1,
	60	+ 7),
	61	+ FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1,
	62	+ 2),
	63	+ FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1,
	64	+ 4),
	65	+ FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1,
	66	+ 1),
	67	+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
	68	+ 2),
	69	+ FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
	70	+ 2),
	71	+ FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
	72	+ 4),
	73	+ FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
	74	+ 8),
	75	+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
	76	+ 3),
	77	+ FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
	78	+ 2),
	79	+ FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
	80	+ 4),
	81	+ FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
	82	+ 8),
	83	+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
	84	+ 5),
	85	+ FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
	86	+ 2),
	87	+ FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
	88	+ 4),
	89	+ FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
	90	+ 8),
	91	+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
	92	+ 7),
	93	+ FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1,
	94	+ 1),
	95	+ FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1,
	96	+ 2),
	97	+ FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1,
	98	+ 4),
	99	+ FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1,
	100	+ 8),
	101	+ FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1,
	102	+ 16),
	103	+ FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1,
	104	+ 32),
	105	+ FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
	106	+ 1),
	107	+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
	108	+ 2),
	109	+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
	110	+ 4),
	111	+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
	112	+ 8),
	113	+ FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
	114	+ 1),
	115	+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
	116	+ 2),
	117	+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
	118	+ 4),
	119	+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
	120	+ 8),
	121	+ FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
	122	+ 1),
	123	+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
	124	+ 2),
	125	+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
	126	+ 4),
	127	+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
	128	+ 8),
	129	+ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
	130	+ 16),
	131	+ FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
	132	+ 1),
	133	+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
	134	+ 4),
	135	+ FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
	136	+ 2),
	137	+ FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
	138	+ 4),
	139	+ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
	140	+ 5),
	141	+ FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
	142	+ 2),
	143	+ FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
	144	+ 4),
	145	+ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
	146	+ 6),
	147	+ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
	148	+ 7),
	149	+ FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
	150	+ 1),
	151	+ FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
	152	+ 1),
	153	+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
	154	+ 2),
	155	+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
	156	+ 4),
	157	+ FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
	158	+ 8),
	159	+ FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
	160	+ 16),
	161	+ FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
	162	+ 1),
	163	+ FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
	164	+ 2),
	165	+ FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
	166	+ 4),
	167	+ FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
	168	+ 8),
	169	+ FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
	170	+ 16),
	171	+ FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1,
	172	+ 2),
	173	+ FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
	174	+ 16),
	175	+};
	176	+
	177	+static const char * const axi_parents[] = {
	178	+ "clk26m",
	179	+ "syspll_d2_d4",
	180	+ "syspll_d7",
	181	+ "osc_d4"
	182	+};
	183	+
	184	+static const char * const mm_parents[] = {
	185	+ "clk26m",
	186	+ "mmpll_d7",
	187	+ "syspll_d3",
	188	+ "univpll_d2_d2",
	189	+ "syspll_d2_d2",
	190	+ "syspll_d3_d2"
	191	+};
	192	+
	193	+static const char * const img_parents[] = {
	194	+ "clk26m",
	195	+ "mmpll_d6",
	196	+ "univpll_d3",
	197	+ "syspll_d3",
	198	+ "univpll_d2_d2",
	199	+ "syspll_d2_d2",
	200	+ "univpll_d3_d2",
	201	+ "syspll_d3_d2"
	202	+};
	203	+
	204	+static const char * const cam_parents[] = {
	205	+ "clk26m",
	206	+ "syspll_d2",
	207	+ "mmpll_d6",
	208	+ "syspll_d3",
	209	+ "mmpll_d7",
	210	+ "univpll_d3",
	211	+ "univpll_d2_d2",
	212	+ "syspll_d2_d2",
	213	+ "syspll_d3_d2",
	214	+ "univpll_d3_d2"
	215	+};
	216	+
	217	+static const char * const dsp_parents[] = {
	218	+ "clk26m",
	219	+ "mmpll_d6",
	220	+ "mmpll_d7",
	221	+ "univpll_d3",
	222	+ "syspll_d3",
	223	+ "univpll_d2_d2",
	224	+ "syspll_d2_d2",
	225	+ "univpll_d3_d2",
	226	+ "syspll_d3_d2"
	227	+};
	228	+
	229	+static const char * const dsp1_parents[] = {
	230	+ "clk26m",
	231	+ "mmpll_d6",
	232	+ "mmpll_d7",
	233	+ "univpll_d3",
	234	+ "syspll_d3",
	235	+ "univpll_d2_d2",
	236	+ "syspll_d2_d2",
	237	+ "univpll_d3_d2",
	238	+ "syspll_d3_d2"
	239	+};
	240	+
	241	+static const char * const dsp2_parents[] = {
	242	+ "clk26m",
	243	+ "mmpll_d6",
	244	+ "mmpll_d7",
	245	+ "univpll_d3",
	246	+ "syspll_d3",
	247	+ "univpll_d2_d2",
	248	+ "syspll_d2_d2",
	249	+ "univpll_d3_d2",
	250	+ "syspll_d3_d2"
	251	+};
	252	+
	253	+static const char * const ipu_if_parents[] = {
	254	+ "clk26m",
	255	+ "mmpll_d6",
	256	+ "mmpll_d7",
	257	+ "univpll_d3",
	258	+ "syspll_d3",
	259	+ "univpll_d2_d2",
	260	+ "syspll_d2_d2",
	261	+ "univpll_d3_d2",
	262	+ "syspll_d3_d2"
	263	+};
	264	+
	265	+static const char * const mfg_parents[] = {
	266	+ "clk26m",
	267	+ "mfgpll_ck",
	268	+ "univpll_d3",
	269	+ "syspll_d3"
	270	+};
	271	+
	272	+static const char * const f52m_mfg_parents[] = {
	273	+ "clk26m",
	274	+ "univpll_d3_d2",
	275	+ "univpll_d3_d4",
	276	+ "univpll_d3_d8"
	277	+};
	278	+
	279	+static const char * const camtg_parents[] = {
	280	+ "clk26m",
	281	+ "univ_192m_d8",
	282	+ "univpll_d3_d8",
	283	+ "univ_192m_d4",
	284	+ "univpll_d3_d16",
	285	+ "csw_f26m_ck_d2",
	286	+ "univ_192m_d16",
	287	+ "univ_192m_d32"
	288	+};
	289	+
	290	+static const char * const camtg2_parents[] = {
	291	+ "clk26m",
	292	+ "univ_192m_d8",
	293	+ "univpll_d3_d8",
	294	+ "univ_192m_d4",
	295	+ "univpll_d3_d16",
	296	+ "csw_f26m_ck_d2",
	297	+ "univ_192m_d16",
	298	+ "univ_192m_d32"
	299	+};
	300	+
	301	+static const char * const camtg3_parents[] = {
	302	+ "clk26m",
	303	+ "univ_192m_d8",
	304	+ "univpll_d3_d8",
	305	+ "univ_192m_d4",
	306	+ "univpll_d3_d16",
	307	+ "csw_f26m_ck_d2",
	308	+ "univ_192m_d16",
	309	+ "univ_192m_d32"
	310	+};
	311	+
	312	+static const char * const camtg4_parents[] = {
	313	+ "clk26m",
	314	+ "univ_192m_d8",
	315	+ "univpll_d3_d8",
	316	+ "univ_192m_d4",
	317	+ "univpll_d3_d16",
	318	+ "csw_f26m_ck_d2",
	319	+ "univ_192m_d16",
	320	+ "univ_192m_d32"
	321	+};
	322	+
	323	+static const char * const uart_parents[] = {
	324	+ "clk26m",
	325	+ "univpll_d3_d8"
	326	+};
	327	+
	328	+static const char * const spi_parents[] = {
	329	+ "clk26m",
	330	+ "syspll_d5_d2",
	331	+ "syspll_d3_d4",
	332	+ "msdcpll_d4"
	333	+};
	334	+
	335	+static const char * const msdc50_hclk_parents[] = {
	336	+ "clk26m",
	337	+ "syspll_d2_d2",
	338	+ "syspll_d3_d2"
	339	+};
	340	+
	341	+static const char * const msdc50_0_parents[] = {
	342	+ "clk26m",
	343	+ "msdcpll_ck",
	344	+ "msdcpll_d2",
	345	+ "univpll_d2_d4",
	346	+ "syspll_d3_d2",
	347	+ "univpll_d2_d2"
	348	+};
	349	+
	350	+static const char * const msdc30_1_parents[] = {
	351	+ "clk26m",
	352	+ "univpll_d3_d2",
	353	+ "syspll_d3_d2",
	354	+ "syspll_d7",
	355	+ "msdcpll_d2"
	356	+};
	357	+
	358	+static const char * const msdc30_2_parents[] = {
	359	+ "clk26m",
	360	+ "univpll_d3_d2",
	361	+ "syspll_d3_d2",
	362	+ "syspll_d7",
	363	+ "msdcpll_d2"
	364	+};
	365	+
	366	+static const char * const audio_parents[] = {
	367	+ "clk26m",
	368	+ "syspll_d5_d4",
	369	+ "syspll_d7_d4",
	370	+ "syspll_d2_d16"
	371	+};
	372	+
	373	+static const char * const aud_intbus_parents[] = {
	374	+ "clk26m",
	375	+ "syspll_d2_d4",
	376	+ "syspll_d7_d2"
	377	+};
	378	+
	379	+static const char * const pmicspi_parents[] = {
	380	+ "clk26m",
	381	+ "syspll_d2_d8",
	382	+ "osc_d8"
	383	+};
	384	+
	385	+static const char * const fpwrap_ulposc_parents[] = {
	386	+ "clk26m",
	387	+ "osc_d16",
	388	+ "osc_d4",
	389	+ "osc_d8"
	390	+};
	391	+
	392	+static const char * const atb_parents[] = {
	393	+ "clk26m",
	394	+ "syspll_d2_d2",
	395	+ "syspll_d5"
	396	+};
	397	+
	398	+static const char * const sspm_parents[] = {
	399	+ "clk26m",
	400	+ "univpll_d2_d4",
	401	+ "syspll_d2_d2",
	402	+ "univpll_d2_d2",
	403	+ "syspll_d3"
	404	+};
	405	+
	406	+static const char * const dpi0_parents[] = {
	407	+ "clk26m",
	408	+ "tvdpll_d2",
	409	+ "tvdpll_d4",
	410	+ "tvdpll_d8",
	411	+ "tvdpll_d16",
	412	+ "univpll_d5_d2",
	413	+ "univpll_d3_d4",
	414	+ "syspll_d3_d4",
	415	+ "univpll_d3_d8"
	416	+};
	417	+
	418	+static const char * const scam_parents[] = {
	419	+ "clk26m",
	420	+ "syspll_d5_d2"
	421	+};
	422	+
	423	+static const char * const disppwm_parents[] = {
	424	+ "clk26m",
	425	+ "univpll_d3_d4",
	426	+ "osc_d2",
	427	+ "osc_d4",
	428	+ "osc_d16"
	429	+};
	430	+
	431	+static const char * const usb_top_parents[] = {
	432	+ "clk26m",
	433	+ "univpll_d5_d4",
	434	+ "univpll_d3_d4",
	435	+ "univpll_d5_d2"
	436	+};
	437	+
	438	+
	439	+static const char * const ssusb_top_xhci_parents[] = {
	440	+ "clk26m",
	441	+ "univpll_d5_d4",
	442	+ "univpll_d3_d4",
	443	+ "univpll_d5_d2"
	444	+};
	445	+
	446	+static const char * const spm_parents[] = {
	447	+ "clk26m",
	448	+ "syspll_d2_d8"
	449	+};
	450	+
	451	+static const char * const i2c_parents[] = {
	452	+ "clk26m",
	453	+ "syspll_d2_d8",
	454	+ "univpll_d5_d2"
	455	+};
	456	+
	457	+static const char * const scp_parents[] = {
	458	+ "clk26m",
	459	+ "univpll_d2_d8",
	460	+ "syspll_d5",
	461	+ "syspll_d2_d2",
	462	+ "univpll_d2_d2",
	463	+ "syspll_d3",
	464	+ "univpll_d3"
	465	+};
	466	+
	467	+static const char * const seninf_parents[] = {
	468	+ "clk26m",
	469	+ "univpll_d2_d2",
	470	+ "univpll_d3_d2",
	471	+ "univpll_d2_d4"
	472	+};
	473	+
	474	+static const char * const dxcc_parents[] = {
	475	+ "clk26m",
	476	+ "syspll_d2_d2",
	477	+ "syspll_d2_d4",
	478	+ "syspll_d2_d8"
	479	+};
	480	+
	481	+static const char * const aud_engen1_parents[] = {
	482	+ "clk26m",
	483	+ "apll1_d2",
	484	+ "apll1_d4",
	485	+ "apll1_d8"
	486	+};
	487	+
	488	+static const char * const aud_engen2_parents[] = {
	489	+ "clk26m",
	490	+ "apll2_d2",
	491	+ "apll2_d4",
	492	+ "apll2_d8"
	493	+};
	494	+
	495	+static const char * const faes_ufsfde_parents[] = {
	496	+ "clk26m",
	497	+ "syspll_d2",
	498	+ "syspll_d2_d2",
	499	+ "syspll_d3",
	500	+ "syspll_d2_d4",
	501	+ "univpll_d3"
	502	+};
	503	+
	504	+static const char * const fufs_parents[] = {
	505	+ "clk26m",
	506	+ "syspll_d2_d4",
	507	+ "syspll_d2_d8",
	508	+ "syspll_d2_d16"
	509	+};
	510	+
	511	+static const char * const aud_1_parents[] = {
	512	+ "clk26m",
	513	+ "apll1_ck"
	514	+};
	515	+
	516	+static const char * const aud_2_parents[] = {
	517	+ "clk26m",
	518	+ "apll2_ck"
	519	+};
	520	+
	521	+/*
	522	+ * CRITICAL CLOCK:
	523	+ * axi_sel is the main bus clock of whole SOC.
	524	+ * spm_sel is the clock of the always-on co-processor.
	525	+ */
	526	+static const struct mtk_mux top_muxes[] = {
	527	+ /* CLK_CFG_0 */
	528	+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
	529	+ axi_parents, 0x40,
	530	+ 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
	531	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
	532	+ mm_parents, 0x40,
	533	+ 0x44, 0x48, 8, 3, 15, 0x004, 1),
	534	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
	535	+ img_parents, 0x40,
	536	+ 0x44, 0x48, 16, 3, 23, 0x004, 2),
	537	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
	538	+ cam_parents, 0x40,
	539	+ 0x44, 0x48, 24, 4, 31, 0x004, 3),
	540	+ /* CLK_CFG_1 */
	541	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
	542	+ dsp_parents, 0x50,
	543	+ 0x54, 0x58, 0, 4, 7, 0x004, 4),
	544	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
	545	+ dsp1_parents, 0x50,
	546	+ 0x54, 0x58, 8, 4, 15, 0x004, 5),
	547	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
	548	+ dsp2_parents, 0x50,
	549	+ 0x54, 0x58, 16, 4, 23, 0x004, 6),
	550	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
	551	+ ipu_if_parents, 0x50,
	552	+ 0x54, 0x58, 24, 4, 31, 0x004, 7),
	553	+ /* CLK_CFG_2 */
	554	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
	555	+ mfg_parents, 0x60,
	556	+ 0x64, 0x68, 0, 2, 7, 0x004, 8),
	557	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
	558	+ f52m_mfg_parents, 0x60,
	559	+ 0x64, 0x68, 8, 2, 15, 0x004, 9),
	560	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
	561	+ camtg_parents, 0x60,
	562	+ 0x64, 0x68, 16, 3, 23, 0x004, 10),
	563	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
	564	+ camtg2_parents, 0x60,
	565	+ 0x64, 0x68, 24, 3, 31, 0x004, 11),
	566	+ /* CLK_CFG_3 */
	567	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
	568	+ camtg3_parents, 0x70,
	569	+ 0x74, 0x78, 0, 3, 7, 0x004, 12),
	570	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
	571	+ camtg4_parents, 0x70,
	572	+ 0x74, 0x78, 8, 3, 15, 0x004, 13),
	573	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
	574	+ uart_parents, 0x70,
	575	+ 0x74, 0x78, 16, 1, 23, 0x004, 14),
	576	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
	577	+ spi_parents, 0x70,
	578	+ 0x74, 0x78, 24, 2, 31, 0x004, 15),
	579	+ /* CLK_CFG_4 */
	580	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
	581	+ msdc50_hclk_parents, 0x80,
	582	+ 0x84, 0x88, 0, 2, 7, 0x004, 16),
	583	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
	584	+ msdc50_0_parents, 0x80,
	585	+ 0x84, 0x88, 8, 3, 15, 0x004, 17),
	586	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
	587	+ msdc30_1_parents, 0x80,
	588	+ 0x84, 0x88, 16, 3, 23, 0x004, 18),
	589	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
	590	+ msdc30_2_parents, 0x80,
	591	+ 0x84, 0x88, 24, 3, 31, 0x004, 19),
	592	+ /* CLK_CFG_5 */
	593	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
	594	+ audio_parents, 0x90,
	595	+ 0x94, 0x98, 0, 2, 7, 0x004, 20),
	596	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
	597	+ aud_intbus_parents, 0x90,
	598	+ 0x94, 0x98, 8, 2, 15, 0x004, 21),
	599	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
	600	+ pmicspi_parents, 0x90,
	601	+ 0x94, 0x98, 16, 2, 23, 0x004, 22),
	602	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
	603	+ fpwrap_ulposc_parents, 0x90,
	604	+ 0x94, 0x98, 24, 2, 31, 0x004, 23),
	605	+ /* CLK_CFG_6 */
	606	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
	607	+ atb_parents, 0xa0,
	608	+ 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
	609	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSPM, "sspm_sel",
	610	+ sspm_parents, 0xa0,
	611	+ 0xa4, 0xa8, 8, 3, 15, 0x004, 25),
	612	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
	613	+ dpi0_parents, 0xa0,
	614	+ 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
	615	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
	616	+ scam_parents, 0xa0,
	617	+ 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
	618	+ /* CLK_CFG_7 */
	619	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
	620	+ disppwm_parents, 0xb0,
	621	+ 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
	622	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
	623	+ usb_top_parents, 0xb0,
	624	+ 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
	625	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
	626	+ ssusb_top_xhci_parents, 0xb0,
	627	+ 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
	628	+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
	629	+ spm_parents, 0xb0,
	630	+ 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
	631	+ /* CLK_CFG_8 */
	632	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
	633	+ i2c_parents, 0xc0,
	634	+ 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
	635	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
	636	+ scp_parents, 0xc0,
	637	+ 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
	638	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
	639	+ seninf_parents, 0xc0,
	640	+ 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
	641	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
	642	+ dxcc_parents, 0xc0,
	643	+ 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
	644	+ /* CLK_CFG_9 */
	645	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
	646	+ aud_engen1_parents, 0xd0,
	647	+ 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
	648	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
	649	+ aud_engen2_parents, 0xd0,
	650	+ 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
	651	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
	652	+ faes_ufsfde_parents, 0xd0,
	653	+ 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
	654	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
	655	+ fufs_parents, 0xd0,
	656	+ 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
	657	+ /* CLK_CFG_10 */
	658	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
	659	+ aud_1_parents, 0xe0,
	660	+ 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
	661	+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
	662	+ aud_2_parents, 0xe0,
	663	+ 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
	664	+};
	665	+
	666	+static const char * const apll_i2s0_parents[] = {
	667	+ "aud_1_sel",
	668	+ "aud_2_sel"
	669	+};
	670	+
	671	+static const char * const apll_i2s1_parents[] = {
	672	+ "aud_1_sel",
	673	+ "aud_2_sel"
	674	+};
	675	+
	676	+static const char * const apll_i2s2_parents[] = {
	677	+ "aud_1_sel",
	678	+ "aud_2_sel"
	679	+};
	680	+
	681	+static const char * const apll_i2s3_parents[] = {
	682	+ "aud_1_sel",
	683	+ "aud_2_sel"
	684	+};
	685	+
	686	+static const char * const apll_i2s4_parents[] = {
	687	+ "aud_1_sel",
	688	+ "aud_2_sel"
	689	+};
	690	+
	691	+static const char * const apll_i2s5_parents[] = {
	692	+ "aud_1_sel",
	693	+ "aud_2_sel"
	694	+};
	695	+
	696	+static struct mtk_composite top_aud_muxes[] = {
	697	+ MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
	698	+ 0x320, 8, 1),
	699	+ MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
	700	+ 0x320, 9, 1),
	701	+ MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
	702	+ 0x320, 10, 1),
	703	+ MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
	704	+ 0x320, 11, 1),
	705	+ MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
	706	+ 0x320, 12, 1),
	707	+ MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
	708	+ 0x328, 20, 1),
	709	+};
	710	+
	711	+static const char * const mcu_mp0_parents[] = {
	712	+ "clk26m",
	713	+ "armpll_ll",
	714	+ "armpll_div_pll1",
	715	+ "armpll_div_pll2"
	716	+};
	717	+
	718	+static const char * const mcu_mp2_parents[] = {
	719	+ "clk26m",
	720	+ "armpll_l",
	721	+ "armpll_div_pll1",
	722	+ "armpll_div_pll2"
	723	+};
	724	+
	725	+static const char * const mcu_bus_parents[] = {
	726	+ "clk26m",
	727	+ "ccipll",
	728	+ "armpll_div_pll1",
	729	+ "armpll_div_pll2"
	730	+};
	731	+
	732	+static struct mtk_composite mcu_muxes[] = {
	733	+ /* mp0_pll_divider_cfg */
	734	+ MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
	735	+ /* mp2_pll_divider_cfg */
	736	+ MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
	737	+ /* bus_pll_divider_cfg */
	738	+ MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
	739	+};
	740	+
	741	+static struct mtk_composite top_aud_divs[] = {
	742	+ DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
	743	+ 0x320, 2, 0x324, 8, 0),
	744	+ DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel",
	745	+ 0x320, 3, 0x324, 8, 8),
	746	+ DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel",
	747	+ 0x320, 4, 0x324, 8, 16),
	748	+ DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel",
	749	+ 0x320, 5, 0x324, 8, 24),
	750	+ DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel",
	751	+ 0x320, 6, 0x328, 8, 0),
	752	+ DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
	753	+ 0x320, 7, 0x328, 8, 8),
	754	+};
	755	+
	756	+static const struct mtk_gate_regs top_cg_regs = {
	757	+ .set_ofs = 0x104,
	758	+ .clr_ofs = 0x104,
	759	+ .sta_ofs = 0x104,
	760	+};
	761	+
	762	+#define GATE_TOP(_id, _name, _parent, _shift) \
	763	+ GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \
	764	+ &mtk_clk_gate_ops_no_setclr_inv)
	765	+
	766	+static const struct mtk_gate top_clks[] = {
	767	+ /* TOP */
	768	+ GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
	769	+ GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
	770	+};
	771	+
	772	+static const struct mtk_gate_regs infra0_cg_regs = {
	773	+ .set_ofs = 0x80,
	774	+ .clr_ofs = 0x84,
	775	+ .sta_ofs = 0x90,
	776	+};
	777	+
	778	+static const struct mtk_gate_regs infra1_cg_regs = {
	779	+ .set_ofs = 0x88,
	780	+ .clr_ofs = 0x8c,
	781	+ .sta_ofs = 0x94,
	782	+};
	783	+
	784	+static const struct mtk_gate_regs infra2_cg_regs = {
	785	+ .set_ofs = 0xa4,
	786	+ .clr_ofs = 0xa8,
	787	+ .sta_ofs = 0xac,
	788	+};
	789	+
	790	+static const struct mtk_gate_regs infra3_cg_regs = {
	791	+ .set_ofs = 0xc0,
	792	+ .clr_ofs = 0xc4,
	793	+ .sta_ofs = 0xc8,
	794	+};
	795	+
	796	+#define GATE_INFRA0(_id, _name, _parent, _shift) \
	797	+ GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
	798	+ &mtk_clk_gate_ops_setclr)
	799	+
	800	+#define GATE_INFRA1(_id, _name, _parent, _shift) \
	801	+ GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
	802	+ &mtk_clk_gate_ops_setclr)
	803	+
	804	+#define GATE_INFRA2(_id, _name, _parent, _shift) \
	805	+ GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
	806	+ &mtk_clk_gate_ops_setclr)
	807	+
	808	+#define GATE_INFRA3(_id, _name, _parent, _shift) \
	809	+ GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
	810	+ &mtk_clk_gate_ops_setclr)
	811	+
	812	+static const struct mtk_gate infra_clks[] = {
	813	+ /* INFRA0 */
	814	+ GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
	815	+ "axi_sel", 0),
	816	+ GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
	817	+ "axi_sel", 1),
	818	+ GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
	819	+ "axi_sel", 2),
	820	+ GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
	821	+ "axi_sel", 3),
	822	+ GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
	823	+ "scp_sel", 4),
	824	+ GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
	825	+ "f_f26m_ck", 5),
	826	+ GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
	827	+ "axi_sel", 6),
	828	+ GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
	829	+ "axi_sel", 8),
	830	+ GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
	831	+ "axi_sel", 9),
	832	+ GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
	833	+ "axi_sel", 10),
	834	+ GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
	835	+ "i2c_sel", 11),
	836	+ GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
	837	+ "i2c_sel", 12),
	838	+ GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
	839	+ "i2c_sel", 13),
	840	+ GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
	841	+ "i2c_sel", 14),
	842	+ GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
	843	+ "axi_sel", 15),
	844	+ GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
	845	+ "i2c_sel", 16),
	846	+ GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
	847	+ "i2c_sel", 17),
	848	+ GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
	849	+ "i2c_sel", 18),
	850	+ GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
	851	+ "i2c_sel", 19),
	852	+ GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
	853	+ "i2c_sel", 21),
	854	+ GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
	855	+ "uart_sel", 22),
	856	+ GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
	857	+ "uart_sel", 23),
	858	+ GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
	859	+ "uart_sel", 24),
	860	+ GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
	861	+ "uart_sel", 25),
	862	+ GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
	863	+ "axi_sel", 27),
	864	+ GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
	865	+ "axi_sel", 28),
	866	+ GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
	867	+ "axi_sel", 31),
	868	+ /* INFRA1 */
	869	+ GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
	870	+ "spi_sel", 1),
	871	+ GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
	872	+ "msdc50_hclk_sel", 2),
	873	+ GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
	874	+ "axi_sel", 4),
	875	+ GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
	876	+ "axi_sel", 5),
	877	+ GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
	878	+ "msdc50_0_sel", 6),
	879	+ GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
	880	+ "f_f26m_ck", 7),
	881	+ GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
	882	+ "axi_sel", 8),
	883	+ GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
	884	+ "axi_sel", 9),
	885	+ GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
	886	+ "f_f26m_ck", 10),
	887	+ GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
	888	+ "axi_sel", 11),
	889	+ GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
	890	+ "axi_sel", 12),
	891	+ GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
	892	+ "axi_sel", 13),
	893	+ GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
	894	+ "f_f26m_ck", 14),
	895	+ GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
	896	+ "msdc30_1_sel", 16),
	897	+ GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
	898	+ "msdc30_2_sel", 17),
	899	+ GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
	900	+ "axi_sel", 18),
	901	+ GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
	902	+ "axi_sel", 19),
	903	+ GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
	904	+ "axi_sel", 20),
	905	+ GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
	906	+ "axi_sel", 23),
	907	+ GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
	908	+ "axi_sel", 24),
	909	+ GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio",
	910	+ "axi_sel", 25),
	911	+ GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
	912	+ "axi_sel", 26),
	913	+ GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
	914	+ "dxcc_sel", 27),
	915	+ GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
	916	+ "dxcc_sel", 28),
	917	+ GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
	918	+ "axi_sel", 30),
	919	+ GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
	920	+ "f_f26m_ck", 31),
	921	+ /* INFRA2 */
	922	+ GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
	923	+ "f_f26m_ck", 0),
	924	+ GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
	925	+ "usb_top_sel", 1),
	926	+ GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
	927	+ "axi_sel", 2),
	928	+ GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk",
	929	+ "axi_sel", 3),
	930	+ GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk",
	931	+ "f_f26m_ck", 4),
	932	+ GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
	933	+ "spi_sel", 6),
	934	+ GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
	935	+ "i2c_sel", 7),
	936	+ GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
	937	+ "f_f26m_ck", 8),
	938	+ GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
	939	+ "spi_sel", 9),
	940	+ GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
	941	+ "spi_sel", 10),
	942	+ GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
	943	+ "ssusb_top_xhci_sel", 11),
	944	+ GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
	945	+ "fufs_sel", 12),
	946	+ GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
	947	+ "fufs_sel", 13),
	948	+ GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
	949	+ "axi_sel", 14),
	950	+ GATE_INFRA2(CLK_INFRA_SSPM, "infra_sspm",
	951	+ "sspm_sel", 15),
	952	+ GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
	953	+ "axi_sel", 16),
	954	+ GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
	955	+ "axi_sel", 17),
	956	+ GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
	957	+ "i2c_sel", 18),
	958	+ GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
	959	+ "i2c_sel", 19),
	960	+ GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
	961	+ "i2c_sel", 20),
	962	+ GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
	963	+ "i2c_sel", 21),
	964	+ GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
	965	+ "i2c_sel", 22),
	966	+ GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
	967	+ "i2c_sel", 23),
	968	+ GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
	969	+ "i2c_sel", 24),
	970	+ GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
	971	+ "spi_sel", 25),
	972	+ GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
	973	+ "spi_sel", 26),
	974	+ GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
	975	+ "axi_sel", 27),
	976	+ GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
	977	+ "fufs_sel", 28),
	978	+ GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
	979	+ "faes_ufsfde_sel", 29),
	980	+ GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
	981	+ "fufs_sel", 30),
	982	+ /* INFRA3 */
	983	+ GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
	984	+ "msdc50_0_sel", 0),
	985	+ GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
	986	+ "msdc50_0_sel", 1),
	987	+ GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
	988	+ "msdc50_0_sel", 2),
	989	+ GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
	990	+ "f_f26m_ck", 3),
	991	+ GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
	992	+ "f_f26m_ck", 4),
	993	+ GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
	994	+ "axi_sel", 5),
	995	+ GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
	996	+ "i2c_sel", 6),
	997	+ GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
	998	+ "msdc50_hclk_sel", 7),
	999	+ GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
	1000	+ "msdc50_hclk_sel", 8),
	1001	+ GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
	1002	+ "axi_sel", 16),
	1003	+ GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
	1004	+ "axi_sel", 17),
	1005	+ GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
	1006	+ "axi_sel", 18),
	1007	+ GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
	1008	+ "axi_sel", 19),
	1009	+ GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
	1010	+ "f_f26m_ck", 20),
	1011	+ GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
	1012	+ "axi_sel", 21),
	1013	+ GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
	1014	+ "i2c_sel", 22),
	1015	+ GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
	1016	+ "i2c_sel", 23),
	1017	+ GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
	1018	+ "msdc50_0_sel", 24),
	1019	+};
	1020	+
	1021	+static const struct mtk_gate_regs apmixed_cg_regs = {
	1022	+ .set_ofs = 0x20,
	1023	+ .clr_ofs = 0x20,
	1024	+ .sta_ofs = 0x20,
	1025	+};
	1026	+
	1027	+#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
	1028	+ GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
	1029	+ _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
	1030	+
	1031	+#define GATE_APMIXED(_id, _name, _parent, _shift) \
	1032	+ GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
	1033	+
	1034	+/*
	1035	+ * CRITICAL CLOCK:
	1036	+ * apmixed_appll26m is the toppest clock gate of all PLLs.
	1037	+ */
	1038	+static const struct mtk_gate apmixed_clks[] = {
	1039	+ /* AUDIO0 */
	1040	+ GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m",
	1041	+ "f_f26m_ck", 4),
	1042	+ GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
	1043	+ "f_f26m_ck", 5, CLK_IS_CRITICAL),
	1044	+ GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
	1045	+ "f_f26m_ck", 6),
	1046	+ GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m",
	1047	+ "f_f26m_ck", 7),
	1048	+ GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m",
	1049	+ "f_f26m_ck", 8),
	1050	+ GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m",
	1051	+ "f_f26m_ck", 9),
	1052	+ GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
	1053	+ "f_f26m_ck", 11),
	1054	+ GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m",
	1055	+ "f_f26m_ck", 13),
	1056	+ GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
	1057	+ "f_f26m_ck", 14),
	1058	+ GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
	1059	+ "f_f26m_ck", 16),
	1060	+ GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
	1061	+ "f_f26m_ck", 17),
	1062	+};
	1063	+
	1064	+#define MT8183_PLL_FMAX (3800UL * MHZ)
	1065	+#define MT8183_PLL_FMIN (1500UL * MHZ)
	1066	+
	1067	+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
	1068	+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
	1069	+ _pd_shift, _tuner_reg, _tuner_en_reg, \
	1070	+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
	1071	+ _pcw_chg_reg, _div_table) { \
	1072	+ .id = _id, \
	1073	+ .name = _name, \
	1074	+ .reg = _reg, \
	1075	+ .pwr_reg = _pwr_reg, \
	1076	+ .en_mask = _en_mask, \
	1077	+ .flags = _flags, \
	1078	+ .rst_bar_mask = _rst_bar_mask, \
	1079	+ .fmax = MT8183_PLL_FMAX, \
	1080	+ .fmin = MT8183_PLL_FMIN, \
	1081	+ .pcwbits = _pcwbits, \
	1082	+ .pcwibits = _pcwibits, \
	1083	+ .pd_reg = _pd_reg, \
	1084	+ .pd_shift = _pd_shift, \
	1085	+ .tuner_reg = _tuner_reg, \
	1086	+ .tuner_en_reg = _tuner_en_reg, \
	1087	+ .tuner_en_bit = _tuner_en_bit, \
	1088	+ .pcw_reg = _pcw_reg, \
	1089	+ .pcw_shift = _pcw_shift, \
	1090	+ .pcw_chg_reg = _pcw_chg_reg, \
	1091	+ .div_table = _div_table, \
	1092	+ }
	1093	+
	1094	+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
	1095	+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
	1096	+ _pd_shift, _tuner_reg, _tuner_en_reg, \
	1097	+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
	1098	+ _pcw_chg_reg) \
	1099	+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
	1100	+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
	1101	+ _pd_shift, _tuner_reg, _tuner_en_reg, \
	1102	+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
	1103	+ _pcw_chg_reg, NULL)
	1104	+
	1105	+static const struct mtk_pll_div_table armpll_div_table[] = {
	1106	+ { .div = 0, .freq = MT8183_PLL_FMAX },
	1107	+ { .div = 1, .freq = 1500 * MHZ },
	1108	+ { .div = 2, .freq = 750 * MHZ },
	1109	+ { .div = 3, .freq = 375 * MHZ },
	1110	+ { .div = 4, .freq = 187500000 },
	1111	+ { } /* sentinel */
	1112	+};
	1113	+
	1114	+static const struct mtk_pll_div_table mfgpll_div_table[] = {
	1115	+ { .div = 0, .freq = MT8183_PLL_FMAX },
	1116	+ { .div = 1, .freq = 1600 * MHZ },
	1117	+ { .div = 2, .freq = 800 * MHZ },
	1118	+ { .div = 3, .freq = 400 * MHZ },
	1119	+ { .div = 4, .freq = 200 * MHZ },
	1120	+ { } /* sentinel */
	1121	+};
	1122	+
	1123	+static const struct mtk_pll_data plls[] = {
	1124	+ PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
	1125	+ HAVE_RST_BAR \| PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
	1126	+ 0x0204, 0, 0, armpll_div_table),
	1127	+ PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
	1128	+ HAVE_RST_BAR \| PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
	1129	+ 0x0214, 0, 0, armpll_div_table),
	1130	+ PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
	1131	+ HAVE_RST_BAR \| PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
	1132	+ 0x0294, 0, 0),
	1133	+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
	1134	+ HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
	1135	+ 0x0224, 0, 0),
	1136	+ PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
	1137	+ HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
	1138	+ 0x0234, 0, 0),
	1139	+ PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
	1140	+ 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
	1141	+ mfgpll_div_table),
	1142	+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
	1143	+ 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
	1144	+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
	1145	+ 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
	1146	+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
	1147	+ HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
	1148	+ 0x0274, 0, 0),
	1149	+ PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
	1150	+ 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
	1151	+ PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
	1152	+ 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
	1153	+};
	1154	+
	1155	+static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
	1156	+{
	1157	+ struct clk_onecell_data *clk_data;
	1158	+ struct device_node *node = pdev->dev.of_node;
	1159	+
	1160	+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
	1161	+
	1162	+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
	1163	+
	1164	+ mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
	1165	+ clk_data);
	1166	+
	1167	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	1168	+}
	1169	+
	1170	+static int clk_mt8183_top_probe(struct platform_device *pdev)
	1171	+{
	1172	+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	1173	+ void __iomem *base;
	1174	+ struct clk_onecell_data *clk_data;
	1175	+ struct device_node *node = pdev->dev.of_node;
	1176	+
	1177	+ base = devm_ioremap_resource(&pdev->dev, res);
	1178	+ if (IS_ERR(base))
	1179	+ return PTR_ERR(base);
	1180	+
	1181	+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
	1182	+
	1183	+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
	1184	+ clk_data);
	1185	+
	1186	+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
	1187	+
	1188	+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
	1189	+ node, &mt8183_clk_lock, clk_data);
	1190	+
	1191	+ mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
	1192	+ base, &mt8183_clk_lock, clk_data);
	1193	+
	1194	+ mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
	1195	+ base, &mt8183_clk_lock, clk_data);
	1196	+
	1197	+ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
	1198	+ clk_data);
	1199	+
	1200	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	1201	+}
	1202	+
	1203	+static int clk_mt8183_infra_probe(struct platform_device *pdev)
	1204	+{
	1205	+ struct clk_onecell_data *clk_data;
	1206	+ struct device_node *node = pdev->dev.of_node;
	1207	+
	1208	+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
	1209	+
	1210	+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
	1211	+ clk_data);
	1212	+
	1213	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	1214	+}
	1215	+
	1216	+static int clk_mt8183_mcu_probe(struct platform_device *pdev)
	1217	+{
	1218	+ struct clk_onecell_data *clk_data;
	1219	+ struct device_node *node = pdev->dev.of_node;
	1220	+ void __iomem *base;
	1221	+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	1222	+
	1223	+ base = devm_ioremap_resource(&pdev->dev, res);
	1224	+ if (IS_ERR(base))
	1225	+ return PTR_ERR(base);
	1226	+
	1227	+ clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
	1228	+
	1229	+ mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
	1230	+ &mt8183_clk_lock, clk_data);
	1231	+
	1232	+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	1233	+}
	1234	+
	1235	+static const struct of_device_id of_match_clk_mt8183[] = {
	1236	+ {
	1237	+ .compatible = "mediatek,mt8183-apmixedsys",
	1238	+ .data = clk_mt8183_apmixed_probe,
	1239	+ }, {
	1240	+ .compatible = "mediatek,mt8183-topckgen",
	1241	+ .data = clk_mt8183_top_probe,
	1242	+ }, {
	1243	+ .compatible = "mediatek,mt8183-infracfg",
	1244	+ .data = clk_mt8183_infra_probe,
	1245	+ }, {
	1246	+ .compatible = "mediatek,mt8183-mcucfg",
	1247	+ .data = clk_mt8183_mcu_probe,
	1248	+ }, {
	1249	+ /* sentinel */
	1250	+ }
	1251	+};
	1252	+
	1253	+static int clk_mt8183_probe(struct platform_device *pdev)
	1254	+{
	1255	+ int (clk_probe)(struct platform_device pdev);
	1256	+ int r;
	1257	+
	1258	+ clk_probe = of_device_get_match_data(&pdev->dev);
	1259	+ if (!clk_probe)
	1260	+ return -EINVAL;
	1261	+
	1262	+ r = clk_probe(pdev);
	1263	+ if (r)
	1264	+ dev_err(&pdev->dev,
	1265	+ "could not register clock provider: %s: %d\n",
	1266	+ pdev->name, r);
	1267	+
	1268	+ return r;
	1269	+}
	1270	+
	1271	+static struct platform_driver clk_mt8183_drv = {
	1272	+ .probe = clk_mt8183_probe,
	1273	+ .driver = {
	1274	+ .name = "clk-mt8183",
	1275	+ .of_match_table = of_match_clk_mt8183,
	1276	+ },
	1277	+};
	1278	+
	1279	+static int __init clk_mt8183_init(void)
	1280	+{
	1281	+ return platform_driver_register(&clk_mt8183_drv);
	1282	+}
	1283	+
	1284	+arch_initcall(clk_mt8183_init);

drivers/clk/mediatek/clk-mt8516.c+815−0

@@ -0,0 +1,815 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright (c) 2019 MediaTek Inc.
	4	+ * Author: James Liao <jamesjj.liao@mediatek.com>
	5	+ * Fabien Parent <fparent@baylibre.com>
	6	+ */
	7	+
	8	+#include <linux/delay.h>
	9	+#include <linux/of.h>
	10	+#include <linux/of_address.h>
	11	+#include <linux/slab.h>
	12	+#include <linux/mfd/syscon.h>
	13	+
	14	+#include "clk-mtk.h"
	15	+#include "clk-gate.h"
	16	+
	17	+#include <dt-bindings/clock/mt8516-clk.h>
	18	+
	19	+static DEFINE_SPINLOCK(mt8516_clk_lock);
	20	+
	21	+static const struct mtk_fixed_clk fixed_clks[] __initconst = {
	22	+ FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
	23	+ FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
	24	+ FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
	25	+};
	26	+
	27	+static const struct mtk_fixed_factor top_divs[] __initconst = {
	28	+ FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
	29	+ FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
	30	+ FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
	31	+ FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
	32	+ FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
	33	+ FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
	34	+ FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
	35	+ FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
	36	+ FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
	37	+ FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
	38	+ FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
	39	+ FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
	40	+ FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
	41	+ FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
	42	+ FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
	43	+ FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
	44	+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
	45	+ FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
	46	+ FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
	47	+ FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
	48	+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
	49	+ FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
	50	+ FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
	51	+ FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
	52	+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
	53	+ FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
	54	+ FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
	55	+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
	56	+ FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
	57	+ FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
	58	+ FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
	59	+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
	60	+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
	61	+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
	62	+ FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
	63	+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
	64	+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
	65	+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
	66	+ FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
	67	+ FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
	68	+ FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
	69	+ FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
	70	+ FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
	71	+};
	72	+
	73	+static const char * const uart0_parents[] __initconst = {
	74	+ "clk26m_ck",
	75	+ "univpll_d24"
	76	+};
	77	+
	78	+static const char * const ahb_infra_parents[] __initconst = {
	79	+ "clk_null",
	80	+ "clk26m_ck",
	81	+ "mainpll_d11",
	82	+ "clk_null",
	83	+ "mainpll_d12",
	84	+ "clk_null",
	85	+ "clk_null",
	86	+ "clk_null",
	87	+ "clk_null",
	88	+ "clk_null",
	89	+ "clk_null",
	90	+ "clk_null",
	91	+ "mainpll_d10"
	92	+};
	93	+
	94	+static const char * const msdc0_parents[] __initconst = {
	95	+ "clk26m_ck",
	96	+ "univpll_d6",
	97	+ "mainpll_d8",
	98	+ "univpll_d8",
	99	+ "mainpll_d16",
	100	+ "mmpll_200m",
	101	+ "mainpll_d12",
	102	+ "mmpll_d2"
	103	+};
	104	+
	105	+static const char * const uart1_parents[] __initconst = {
	106	+ "clk26m_ck",
	107	+ "univpll_d24"
	108	+};
	109	+
	110	+static const char * const msdc1_parents[] __initconst = {
	111	+ "clk26m_ck",
	112	+ "univpll_d6",
	113	+ "mainpll_d8",
	114	+ "univpll_d8",
	115	+ "mainpll_d16",
	116	+ "mmpll_200m",
	117	+ "mainpll_d12",
	118	+ "mmpll_d2"
	119	+};
	120	+
	121	+static const char * const pmicspi_parents[] __initconst = {
	122	+ "univpll_d20",
	123	+ "usb_phy48m_ck",
	124	+ "univpll_d16",
	125	+ "clk26m_ck"
	126	+};
	127	+
	128	+static const char * const qaxi_aud26m_parents[] __initconst = {
	129	+ "clk26m_ck",
	130	+ "ahb_infra_sel"
	131	+};
	132	+
	133	+static const char * const aud_intbus_parents[] __initconst = {
	134	+ "clk_null",
	135	+ "clk26m_ck",
	136	+ "mainpll_d22",
	137	+ "clk_null",
	138	+ "mainpll_d11"
	139	+};
	140	+
	141	+static const char * const nfi2x_pad_parents[] __initconst = {
	142	+ "clk_null",
	143	+ "clk_null",
	144	+ "clk_null",
	145	+ "clk_null",
	146	+ "clk_null",
	147	+ "clk_null",
	148	+ "clk_null",
	149	+ "clk_null",
	150	+ "clk26m_ck",
	151	+ "clk_null",
	152	+ "clk_null",
	153	+ "clk_null",
	154	+ "clk_null",
	155	+ "clk_null",
	156	+ "clk_null",
	157	+ "clk_null",
	158	+ "clk_null",
	159	+ "mainpll_d12",
	160	+ "mainpll_d8",
	161	+ "clk_null",
	162	+ "mainpll_d6",
	163	+ "clk_null",
	164	+ "clk_null",
	165	+ "clk_null",
	166	+ "clk_null",
	167	+ "clk_null",
	168	+ "clk_null",
	169	+ "clk_null",
	170	+ "clk_null",
	171	+ "clk_null",
	172	+ "clk_null",
	173	+ "clk_null",
	174	+ "mainpll_d4",
	175	+ "clk_null",
	176	+ "clk_null",
	177	+ "clk_null",
	178	+ "clk_null",
	179	+ "clk_null",
	180	+ "clk_null",
	181	+ "clk_null",
	182	+ "clk_null",
	183	+ "clk_null",
	184	+ "clk_null",
	185	+ "clk_null",
	186	+ "clk_null",
	187	+ "clk_null",
	188	+ "clk_null",
	189	+ "clk_null",
	190	+ "clk_null",
	191	+ "clk_null",
	192	+ "clk_null",
	193	+ "clk_null",
	194	+ "clk_null",
	195	+ "clk_null",
	196	+ "clk_null",
	197	+ "clk_null",
	198	+ "clk_null",
	199	+ "clk_null",
	200	+ "clk_null",
	201	+ "clk_null",
	202	+ "clk_null",
	203	+ "clk_null",
	204	+ "clk_null",
	205	+ "clk_null",
	206	+ "clk_null",
	207	+ "clk_null",
	208	+ "clk_null",
	209	+ "clk_null",
	210	+ "clk_null",
	211	+ "clk_null",
	212	+ "clk_null",
	213	+ "clk_null",
	214	+ "clk_null",
	215	+ "clk_null",
	216	+ "clk_null",
	217	+ "clk_null",
	218	+ "clk_null",
	219	+ "clk_null",
	220	+ "clk_null",
	221	+ "clk_null",
	222	+ "clk_null",
	223	+ "mainpll_d10",
	224	+ "mainpll_d7",
	225	+ "clk_null",
	226	+ "mainpll_d5"
	227	+};
	228	+
	229	+static const char * const nfi1x_pad_parents[] __initconst = {
	230	+ "ahb_infra_sel",
	231	+ "nfi1x_ck"
	232	+};
	233	+
	234	+static const char * const ddrphycfg_parents[] __initconst = {
	235	+ "clk26m_ck",
	236	+ "mainpll_d16"
	237	+};
	238	+
	239	+static const char * const usb_78m_parents[] __initconst = {
	240	+ "clk_null",
	241	+ "clk26m_ck",
	242	+ "univpll_d16",
	243	+ "clk_null",
	244	+ "mainpll_d20"
	245	+};
	246	+
	247	+static const char * const spinor_parents[] __initconst = {
	248	+ "clk26m_d2",
	249	+ "clk26m_ck",
	250	+ "mainpll_d40",
	251	+ "univpll_d24",
	252	+ "univpll_d20",
	253	+ "mainpll_d20",
	254	+ "mainpll_d16",
	255	+ "univpll_d12"
	256	+};
	257	+
	258	+static const char * const msdc2_parents[] __initconst = {
	259	+ "clk26m_ck",
	260	+ "univpll_d6",
	261	+ "mainpll_d8",
	262	+ "univpll_d8",
	263	+ "mainpll_d16",
	264	+ "mmpll_200m",
	265	+ "mainpll_d12",
	266	+ "mmpll_d2"
	267	+};
	268	+
	269	+static const char * const eth_parents[] __initconst = {
	270	+ "clk26m_ck",
	271	+ "mainpll_d40",
	272	+ "univpll_d24",
	273	+ "univpll_d20",
	274	+ "mainpll_d20"
	275	+};
	276	+
	277	+static const char * const aud1_parents[] __initconst = {
	278	+ "clk26m_ck",
	279	+ "apll1_ck"
	280	+};
	281	+
	282	+static const char * const aud2_parents[] __initconst = {
	283	+ "clk26m_ck",
	284	+ "apll2_ck"
	285	+};
	286	+
	287	+static const char * const aud_engen1_parents[] __initconst = {
	288	+ "clk26m_ck",
	289	+ "rg_apll1_d2_en",
	290	+ "rg_apll1_d4_en",
	291	+ "rg_apll1_d8_en"
	292	+};
	293	+
	294	+static const char * const aud_engen2_parents[] __initconst = {
	295	+ "clk26m_ck",
	296	+ "rg_apll2_d2_en",
	297	+ "rg_apll2_d4_en",
	298	+ "rg_apll2_d8_en"
	299	+};
	300	+
	301	+static const char * const i2c_parents[] __initconst = {
	302	+ "clk26m_ck",
	303	+ "univpll_d20",
	304	+ "univpll_d16",
	305	+ "univpll_d12"
	306	+};
	307	+
	308	+static const char * const aud_i2s0_m_parents[] __initconst = {
	309	+ "rg_aud1",
	310	+ "rg_aud2"
	311	+};
	312	+
	313	+static const char * const pwm_parents[] __initconst = {
	314	+ "clk26m_ck",
	315	+ "univpll_d12"
	316	+};
	317	+
	318	+static const char * const spi_parents[] __initconst = {
	319	+ "clk26m_ck",
	320	+ "univpll_d12",
	321	+ "univpll_d8",
	322	+ "univpll_d6"
	323	+};
	324	+
	325	+static const char * const aud_spdifin_parents[] __initconst = {
	326	+ "clk26m_ck",
	327	+ "univpll_d2"
	328	+};
	329	+
	330	+static const char * const uart2_parents[] __initconst = {
	331	+ "clk26m_ck",
	332	+ "univpll_d24"
	333	+};
	334	+
	335	+static const char * const bsi_parents[] __initconst = {
	336	+ "clk26m_ck",
	337	+ "mainpll_d10",
	338	+ "mainpll_d12",
	339	+ "mainpll_d20"
	340	+};
	341	+
	342	+static const char * const dbg_atclk_parents[] __initconst = {
	343	+ "clk_null",
	344	+ "clk26m_ck",
	345	+ "mainpll_d5",
	346	+ "clk_null",
	347	+ "univpll_d5"
	348	+};
	349	+
	350	+static const char * const csw_nfiecc_parents[] __initconst = {
	351	+ "clk_null",
	352	+ "mainpll_d7",
	353	+ "mainpll_d6",
	354	+ "clk_null",
	355	+ "mainpll_d5"
	356	+};
	357	+
	358	+static const char * const nfiecc_parents[] __initconst = {
	359	+ "clk_null",
	360	+ "nfi2x_pad_sel",
	361	+ "mainpll_d4",
	362	+ "clk_null",
	363	+ "csw_nfiecc_sel"
	364	+};
	365	+
	366	+static struct mtk_composite top_muxes[] __initdata = {
	367	+ /* CLK_MUX_SEL0 */
	368	+ MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
	369	+ 0x000, 0, 1),
	370	+ MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
	371	+ 0x000, 4, 4),
	372	+ MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
	373	+ 0x000, 11, 3),
	374	+ MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
	375	+ 0x000, 19, 1),
	376	+ MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
	377	+ 0x000, 20, 3),
	378	+ MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
	379	+ 0x000, 24, 2),
	380	+ MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
	381	+ 0x000, 26, 1),
	382	+ MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
	383	+ 0x000, 27, 3),
	384	+ /* CLK_MUX_SEL1 */
	385	+ MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
	386	+ 0x004, 0, 7),
	387	+ MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
	388	+ 0x004, 7, 1),
	389	+ MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
	390	+ 0x004, 20, 3),
	391	+ /* CLK_MUX_SEL8 */
	392	+ MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
	393	+ 0x040, 0, 3),
	394	+ MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
	395	+ 0x040, 3, 3),
	396	+ MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
	397	+ 0x040, 6, 3),
	398	+ MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
	399	+ 0x040, 22, 1),
	400	+ MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
	401	+ 0x040, 23, 1),
	402	+ MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
	403	+ 0x040, 24, 2),
	404	+ MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
	405	+ 0x040, 26, 2),
	406	+ MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
	407	+ 0x040, 28, 2),
	408	+ /* CLK_SEL_9 */
	409	+ MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
	410	+ 0x044, 12, 1),
	411	+ MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
	412	+ 0x044, 13, 1),
	413	+ MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
	414	+ 0x044, 14, 1),
	415	+ MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
	416	+ 0x044, 15, 1),
	417	+ MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
	418	+ 0x044, 16, 1),
	419	+ MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
	420	+ 0x044, 17, 1),
	421	+ MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
	422	+ 0x044, 18, 1),
	423	+ /* CLK_MUX_SEL13 */
	424	+ MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
	425	+ 0x07c, 0, 1),
	426	+ MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
	427	+ 0x07c, 1, 2),
	428	+ MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
	429	+ 0x07c, 3, 1),
	430	+ MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
	431	+ 0x07c, 4, 1),
	432	+ MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
	433	+ 0x07c, 5, 2),
	434	+ MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
	435	+ 0x07c, 7, 3),
	436	+ MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
	437	+ 0x07c, 10, 3),
	438	+ MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
	439	+ 0x07c, 13, 3),
	440	+};
	441	+
	442	+static const char * const ifr_mux1_parents[] __initconst = {
	443	+ "clk26m_ck",
	444	+ "armpll",
	445	+ "univpll",
	446	+ "mainpll_d2"
	447	+};
	448	+
	449	+static const char * const ifr_eth_25m_parents[] __initconst = {
	450	+ "eth_d2_ck",
	451	+ "rg_eth"
	452	+};
	453	+
	454	+static const char * const ifr_i2c0_parents[] __initconst = {
	455	+ "ahb_infra_d2",
	456	+ "rg_i2c"
	457	+};
	458	+
	459	+static const struct mtk_composite ifr_muxes[] __initconst = {
	460	+ MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
	461	+ 2, 2),
	462	+ MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
	463	+ 0, 1),
	464	+ MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
	465	+ 1, 1),
	466	+ MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
	467	+ 2, 1),
	468	+ MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
	469	+ 3, 1),
	470	+};
	471	+
	472	+#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
	473	+ .id = _id, \
	474	+ .name = _name, \
	475	+ .parent_name = _parent, \
	476	+ .div_reg = _reg, \
	477	+ .div_shift = _shift, \
	478	+ .div_width = _width, \
	479	+}
	480	+
	481	+static const struct mtk_clk_divider top_adj_divs[] = {
	482	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
	483	+ 0x0048, 0, 8),
	484	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
	485	+ 0x0048, 8, 8),
	486	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
	487	+ 0x0048, 16, 8),
	488	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
	489	+ 0x0048, 24, 8),
	490	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
	491	+ 0x004c, 0, 8),
	492	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
	493	+ 0x004c, 8, 8),
	494	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
	495	+ 0x004c, 16, 8),
	496	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
	497	+ 0x004c, 24, 8),
	498	+ DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
	499	+ 0x0078, 0, 8),
	500	+};
	501	+
	502	+static const struct mtk_gate_regs top1_cg_regs = {
	503	+ .set_ofs = 0x54,
	504	+ .clr_ofs = 0x84,
	505	+ .sta_ofs = 0x24,
	506	+};
	507	+
	508	+static const struct mtk_gate_regs top2_cg_regs = {
	509	+ .set_ofs = 0x6c,
	510	+ .clr_ofs = 0x9c,
	511	+ .sta_ofs = 0x3c,
	512	+};
	513	+
	514	+static const struct mtk_gate_regs top3_cg_regs = {
	515	+ .set_ofs = 0xa0,
	516	+ .clr_ofs = 0xb0,
	517	+ .sta_ofs = 0x70,
	518	+};
	519	+
	520	+static const struct mtk_gate_regs top4_cg_regs = {
	521	+ .set_ofs = 0xa4,
	522	+ .clr_ofs = 0xb4,
	523	+ .sta_ofs = 0x74,
	524	+};
	525	+
	526	+static const struct mtk_gate_regs top5_cg_regs = {
	527	+ .set_ofs = 0x44,
	528	+ .clr_ofs = 0x44,
	529	+ .sta_ofs = 0x44,
	530	+};
	531	+
	532	+#define GATE_TOP1(_id, _name, _parent, _shift) { \
	533	+ .id = _id, \
	534	+ .name = _name, \
	535	+ .parent_name = _parent, \
	536	+ .regs = &top1_cg_regs, \
	537	+ .shift = _shift, \
	538	+ .ops = &mtk_clk_gate_ops_setclr, \
	539	+ }
	540	+
	541	+#define GATE_TOP2(_id, _name, _parent, _shift) { \
	542	+ .id = _id, \
	543	+ .name = _name, \
	544	+ .parent_name = _parent, \
	545	+ .regs = &top2_cg_regs, \
	546	+ .shift = _shift, \
	547	+ .ops = &mtk_clk_gate_ops_setclr, \
	548	+ }
	549	+
	550	+#define GATE_TOP2_I(_id, _name, _parent, _shift) { \
	551	+ .id = _id, \
	552	+ .name = _name, \
	553	+ .parent_name = _parent, \
	554	+ .regs = &top2_cg_regs, \
	555	+ .shift = _shift, \
	556	+ .ops = &mtk_clk_gate_ops_setclr_inv, \
	557	+ }
	558	+
	559	+#define GATE_TOP3(_id, _name, _parent, _shift) { \
	560	+ .id = _id, \
	561	+ .name = _name, \
	562	+ .parent_name = _parent, \
	563	+ .regs = &top3_cg_regs, \
	564	+ .shift = _shift, \
	565	+ .ops = &mtk_clk_gate_ops_setclr, \
	566	+ }
	567	+
	568	+#define GATE_TOP4_I(_id, _name, _parent, _shift) { \
	569	+ .id = _id, \
	570	+ .name = _name, \
	571	+ .parent_name = _parent, \
	572	+ .regs = &top4_cg_regs, \
	573	+ .shift = _shift, \
	574	+ .ops = &mtk_clk_gate_ops_setclr_inv, \
	575	+ }
	576	+
	577	+#define GATE_TOP5(_id, _name, _parent, _shift) { \
	578	+ .id = _id, \
	579	+ .name = _name, \
	580	+ .parent_name = _parent, \
	581	+ .regs = &top5_cg_regs, \
	582	+ .shift = _shift, \
	583	+ .ops = &mtk_clk_gate_ops_no_setclr, \
	584	+ }
	585	+
	586	+static const struct mtk_gate top_clks[] __initconst = {
	587	+ /* TOP1 */
	588	+ GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
	589	+ GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
	590	+ GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
	591	+ GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
	592	+ GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
	593	+ GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
	594	+ GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
	595	+ GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
	596	+ GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
	597	+ GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
	598	+ GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
	599	+ GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
	600	+ GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
	601	+ GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
	602	+ GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
	603	+ GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
	604	+ GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
	605	+ GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
	606	+ GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
	607	+ GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
	608	+ GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
	609	+ GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
	610	+ GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
	611	+ GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
	612	+ GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
	613	+ GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
	614	+ GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
	615	+ GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
	616	+ GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
	617	+ GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
	618	+ /* TOP2 */
	619	+ GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
	620	+ GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
	621	+ GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
	622	+ GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
	623	+ GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
	624	+ GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
	625	+ GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
	626	+ GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
	627	+ GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
	628	+ GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
	629	+ GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
	630	+ GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
	631	+ GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
	632	+ GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
	633	+ GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
	634	+ 15),
	635	+ GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
	636	+ GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
	637	+ GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
	638	+ GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
	639	+ GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
	640	+ GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
	641	+ GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
	642	+ GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
	643	+ GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
	644	+ GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
	645	+ GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
	646	+ GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
	647	+ /* TOP3 */
	648	+ GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
	649	+ GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
	650	+ GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
	651	+ GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
	652	+ GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
	653	+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
	654	+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
	655	+ GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
	656	+ GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
	657	+ GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
	658	+ 14),
	659	+ GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
	660	+ GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
	661	+ GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
	662	+ GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
	663	+ /* TOP4 */
	664	+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
	665	+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
	666	+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
	667	+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
	668	+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
	669	+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
	670	+ /* TOP5 */
	671	+ GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
	672	+ GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
	673	+ GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
	674	+ GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
	675	+ GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
	676	+ GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
	677	+ GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
	678	+ GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
	679	+ GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
	680	+};
	681	+
	682	+static void __init mtk_topckgen_init(struct device_node *node)
	683	+{
	684	+ struct clk_onecell_data *clk_data;
	685	+ int r;
	686	+ void __iomem *base;
	687	+
	688	+ base = of_iomap(node, 0);
	689	+ if (!base) {
	690	+ pr_err("%s(): ioremap failed\n", __func__);
	691	+ return;
	692	+ }
	693	+
	694	+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
	695	+
	696	+ mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
	697	+ clk_data);
	698	+ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
	699	+
	700	+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
	701	+ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
	702	+ &mt8516_clk_lock, clk_data);
	703	+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
	704	+ base, &mt8516_clk_lock, clk_data);
	705	+
	706	+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	707	+ if (r)
	708	+ pr_err("%s(): could not register clock provider: %d\n",
	709	+ __func__, r);
	710	+}
	711	+CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init);
	712	+
	713	+static void __init mtk_infracfg_init(struct device_node *node)
	714	+{
	715	+ struct clk_onecell_data *clk_data;
	716	+ int r;
	717	+ void __iomem *base;
	718	+
	719	+ base = of_iomap(node, 0);
	720	+ if (!base) {
	721	+ pr_err("%s(): ioremap failed\n", __func__);
	722	+ return;
	723	+ }
	724	+
	725	+ clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
	726	+
	727	+ mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
	728	+ &mt8516_clk_lock, clk_data);
	729	+
	730	+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	731	+ if (r)
	732	+ pr_err("%s(): could not register clock provider: %d\n",
	733	+ __func__, r);
	734	+}
	735	+CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init);
	736	+
	737	+#define MT8516_PLL_FMAX (1502UL * MHZ)
	738	+
	739	+#define CON0_MT8516_RST_BAR BIT(27)
	740	+
	741	+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
	742	+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
	743	+ _pcw_shift, _div_table) { \
	744	+ .id = _id, \
	745	+ .name = _name, \
	746	+ .reg = _reg, \
	747	+ .pwr_reg = _pwr_reg, \
	748	+ .en_mask = _en_mask, \
	749	+ .flags = _flags, \
	750	+ .rst_bar_mask = CON0_MT8516_RST_BAR, \
	751	+ .fmax = MT8516_PLL_FMAX, \
	752	+ .pcwbits = _pcwbits, \
	753	+ .pd_reg = _pd_reg, \
	754	+ .pd_shift = _pd_shift, \
	755	+ .tuner_reg = _tuner_reg, \
	756	+ .pcw_reg = _pcw_reg, \
	757	+ .pcw_shift = _pcw_shift, \
	758	+ .div_table = _div_table, \
	759	+ }
	760	+
	761	+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
	762	+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
	763	+ _pcw_shift) \
	764	+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
	765	+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
	766	+ NULL)
	767	+
	768	+static const struct mtk_pll_div_table mmpll_div_table[] = {
	769	+ { .div = 0, .freq = MT8516_PLL_FMAX },
	770	+ { .div = 1, .freq = 1000000000 },
	771	+ { .div = 2, .freq = 604500000 },
	772	+ { .div = 3, .freq = 253500000 },
	773	+ { .div = 4, .freq = 126750000 },
	774	+ { } /* sentinel */
	775	+};
	776	+
	777	+static const struct mtk_pll_data plls[] = {
	778	+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
	779	+ 21, 0x0104, 24, 0, 0x0104, 0),
	780	+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001,
	781	+ HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
	782	+ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001,
	783	+ HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
	784	+ PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0,
	785	+ 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
	786	+ PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0,
	787	+ 31, 0x0180, 1, 0x0194, 0x0184, 0),
	788	+ PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0,
	789	+ 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
	790	+};
	791	+
	792	+static void __init mtk_apmixedsys_init(struct device_node *node)
	793	+{
	794	+ struct clk_onecell_data *clk_data;
	795	+ void __iomem *base;
	796	+ int r;
	797	+
	798	+ base = of_iomap(node, 0);
	799	+ if (!base) {
	800	+ pr_err("%s(): ioremap failed\n", __func__);
	801	+ return;
	802	+ }
	803	+
	804	+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
	805	+
	806	+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
	807	+
	808	+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
	809	+ if (r)
	810	+ pr_err("%s(): could not register clock provider: %d\n",
	811	+ __func__, r);
	812	+
	813	+}
	814	+CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8516-apmixedsys",
	815	+ mtk_apmixedsys_init);

drivers/clk/mediatek/clk-mtk.h+3−0

@@ -227,10 +227,13 @@ struct mtk_pll_data { · 226 unmodified lines
227	227	unsigned int flags;
228	228	const struct clk_ops *ops;
229	229	u32 rst_bar_mask;
	230	+ unsigned long fmin;
230	231	unsigned long fmax;
231	232	int pcwbits;
	233	+ int pcwibits;
232	234	uint32_t pcw_reg;
233	235	int pcw_shift;
	236	+ uint32_t pcw_chg_reg;
234	237	const struct mtk_pll_div_table *div_table;
235	238	const char *parent_name;
236	239	};

drivers/clk/mediatek/clk-mux.c+223−0

@@ -0,0 +1,223 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright (c) 2018 MediaTek Inc.
	4	+ * Author: Owen Chen <owen.chen@mediatek.com>
	5	+ */
	6	+
	7	+#include <linux/of.h>
	8	+#include <linux/of_address.h>
	9	+#include <linux/slab.h>
	10	+#include <linux/mfd/syscon.h>
	11	+
	12	+#include "clk-mtk.h"
	13	+#include "clk-mux.h"
	14	+
	15	+static inline struct mtk_clk_mux to_mtk_clk_mux(struct clk_hw hw)
	16	+{
	17	+ return container_of(hw, struct mtk_clk_mux, hw);
	18	+}
	19	+
	20	+static int mtk_clk_mux_enable(struct clk_hw *hw)
	21	+{
	22	+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
	23	+ u32 mask = BIT(mux->data->gate_shift);
	24	+
	25	+ return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
	26	+ mask, ~mask);
	27	+}
	28	+
	29	+static void mtk_clk_mux_disable(struct clk_hw *hw)
	30	+{
	31	+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
	32	+ u32 mask = BIT(mux->data->gate_shift);
	33	+
	34	+ regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
	35	+}
	36	+
	37	+static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
	38	+{
	39	+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
	40	+
	41	+ return regmap_write(mux->regmap, mux->data->clr_ofs,
	42	+ BIT(mux->data->gate_shift));
	43	+}
	44	+
	45	+static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
	46	+{
	47	+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
	48	+
	49	+ regmap_write(mux->regmap, mux->data->set_ofs,
	50	+ BIT(mux->data->gate_shift));
	51	+}
	52	+
	53	+static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
	54	+{
	55	+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
	56	+ u32 val;
	57	+
	58	+ regmap_read(mux->regmap, mux->data->mux_ofs, &val);
	59	+
	60	+ return (val & BIT(mux->data->gate_shift)) == 0;
	61	+}
	62	+
	63	+static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
	64	+{
	65	+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
	66	+ u32 mask = GENMASK(mux->data->mux_width - 1, 0);
	67	+ u32 val;
	68	+
	69	+ regmap_read(mux->regmap, mux->data->mux_ofs, &val);
	70	+ val = (val >> mux->data->mux_shift) & mask;
	71	+
	72	+ return val;
	73	+}
	74	+
	75	+static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
	76	+{
	77	+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
	78	+ u32 mask = GENMASK(mux->data->mux_width - 1, 0);
	79	+ unsigned long flags = 0;
	80	+
	81	+ if (mux->lock)
	82	+ spin_lock_irqsave(mux->lock, flags);
	83	+ else
	84	+ __acquire(mux->lock);
	85	+
	86	+ regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
	87	+ index << mux->data->mux_shift);
	88	+
	89	+ if (mux->lock)
	90	+ spin_unlock_irqrestore(mux->lock, flags);
	91	+ else
	92	+ __release(mux->lock);
	93	+
	94	+ return 0;
	95	+}
	96	+
	97	+static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
	98	+{
	99	+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
	100	+ u32 mask = GENMASK(mux->data->mux_width - 1, 0);
	101	+ u32 val, orig;
	102	+ unsigned long flags = 0;
	103	+
	104	+ if (mux->lock)
	105	+ spin_lock_irqsave(mux->lock, flags);
	106	+ else
	107	+ __acquire(mux->lock);
	108	+
	109	+ regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
	110	+ val = (orig & ~(mask << mux->data->mux_shift))
	111	+ \| (index << mux->data->mux_shift);
	112	+
	113	+ if (val != orig) {
	114	+ regmap_write(mux->regmap, mux->data->clr_ofs,
	115	+ mask << mux->data->mux_shift);
	116	+ regmap_write(mux->regmap, mux->data->set_ofs,
	117	+ index << mux->data->mux_shift);
	118	+
	119	+ if (mux->data->upd_shift >= 0)
	120	+ regmap_write(mux->regmap, mux->data->upd_ofs,
	121	+ BIT(mux->data->upd_shift));
	122	+ }
	123	+
	124	+ if (mux->lock)
	125	+ spin_unlock_irqrestore(mux->lock, flags);
	126	+ else
	127	+ __release(mux->lock);
	128	+
	129	+ return 0;
	130	+}
	131	+
	132	+const struct clk_ops mtk_mux_ops = {
	133	+ .get_parent = mtk_clk_mux_get_parent,
	134	+ .set_parent = mtk_clk_mux_set_parent_lock,
	135	+};
	136	+
	137	+const struct clk_ops mtk_mux_clr_set_upd_ops = {
	138	+ .get_parent = mtk_clk_mux_get_parent,
	139	+ .set_parent = mtk_clk_mux_set_parent_setclr_lock,
	140	+};
	141	+
	142	+const struct clk_ops mtk_mux_gate_ops = {
	143	+ .enable = mtk_clk_mux_enable,
	144	+ .disable = mtk_clk_mux_disable,
	145	+ .is_enabled = mtk_clk_mux_is_enabled,
	146	+ .get_parent = mtk_clk_mux_get_parent,
	147	+ .set_parent = mtk_clk_mux_set_parent_lock,
	148	+};
	149	+
	150	+const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
	151	+ .enable = mtk_clk_mux_enable_setclr,
	152	+ .disable = mtk_clk_mux_disable_setclr,
	153	+ .is_enabled = mtk_clk_mux_is_enabled,
	154	+ .get_parent = mtk_clk_mux_get_parent,
	155	+ .set_parent = mtk_clk_mux_set_parent_setclr_lock,
	156	+};
	157	+
	158	+struct clk mtk_clk_register_mux(const struct mtk_mux mux,
	159	+ struct regmap *regmap,
	160	+ spinlock_t *lock)
	161	+{
	162	+ struct mtk_clk_mux *clk_mux;
	163	+ struct clk_init_data init;
	164	+ struct clk *clk;
	165	+
	166	+ clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
	167	+ if (!clk_mux)
	168	+ return ERR_PTR(-ENOMEM);
	169	+
	170	+ init.name = mux->name;
	171	+ init.flags = mux->flags \| CLK_SET_RATE_PARENT;
	172	+ init.parent_names = mux->parent_names;
	173	+ init.num_parents = mux->num_parents;
	174	+ init.ops = mux->ops;
	175	+
	176	+ clk_mux->regmap = regmap;
	177	+ clk_mux->data = mux;
	178	+ clk_mux->lock = lock;
	179	+ clk_mux->hw.init = &init;
	180	+
	181	+ clk = clk_register(NULL, &clk_mux->hw);
	182	+ if (IS_ERR(clk)) {
	183	+ kfree(clk_mux);
	184	+ return clk;
	185	+ }
	186	+
	187	+ return clk;
	188	+}
	189	+
	190	+int mtk_clk_register_muxes(const struct mtk_mux *muxes,
	191	+ int num, struct device_node *node,
	192	+ spinlock_t *lock,
	193	+ struct clk_onecell_data *clk_data)
	194	+{
	195	+ struct regmap *regmap;
	196	+ struct clk *clk;
	197	+ int i;
	198	+
	199	+ regmap = syscon_node_to_regmap(node);
	200	+ if (IS_ERR(regmap)) {
	201	+ pr_err("Cannot find regmap for %pOF: %ld\n", node,
	202	+ PTR_ERR(regmap));
	203	+ return PTR_ERR(regmap);
	204	+ }
	205	+
	206	+ for (i = 0; i < num; i++) {
	207	+ const struct mtk_mux *mux = &muxes[i];
	208	+
	209	+ if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
	210	+ clk = mtk_clk_register_mux(mux, regmap, lock);
	211	+
	212	+ if (IS_ERR(clk)) {
	213	+ pr_err("Failed to register clk %s: %ld\n",
	214	+ mux->name, PTR_ERR(clk));
	215	+ continue;
	216	+ }
	217	+
	218	+ clk_data->clks[mux->id] = clk;
	219	+ }
	220	+ }
	221	+
	222	+ return 0;
	223	+}

drivers/clk/mediatek/clk-mux.h+89−0

@@ -0,0 +1,89 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2018 MediaTek Inc.
	4	+ * Author: Owen Chen <owen.chen@mediatek.com>
	5	+ */
	6	+
	7	+#ifndef __DRV_CLK_MTK_MUX_H
	8	+#define __DRV_CLK_MTK_MUX_H
	9	+
	10	+#include <linux/clk-provider.h>
	11	+
	12	+struct mtk_clk_mux {
	13	+ struct clk_hw hw;
	14	+ struct regmap *regmap;
	15	+ const struct mtk_mux *data;
	16	+ spinlock_t *lock;
	17	+};
	18	+
	19	+struct mtk_mux {
	20	+ int id;
	21	+ const char *name;
	22	+ const char * const *parent_names;
	23	+ unsigned int flags;
	24	+
	25	+ u32 mux_ofs;
	26	+ u32 set_ofs;
	27	+ u32 clr_ofs;
	28	+ u32 upd_ofs;
	29	+
	30	+ u8 mux_shift;
	31	+ u8 mux_width;
	32	+ u8 gate_shift;
	33	+ s8 upd_shift;
	34	+
	35	+ const struct clk_ops *ops;
	36	+
	37	+ signed char num_parents;
	38	+};
	39	+
	40	+extern const struct clk_ops mtk_mux_ops;
	41	+extern const struct clk_ops mtk_mux_clr_set_upd_ops;
	42	+extern const struct clk_ops mtk_mux_gate_ops;
	43	+extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
	44	+
	45	+#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
	46	+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
	47	+ _gate, _upd_ofs, _upd, _flags, _ops) { \
	48	+ .id = _id, \
	49	+ .name = _name, \
	50	+ .mux_ofs = _mux_ofs, \
	51	+ .set_ofs = _mux_set_ofs, \
	52	+ .clr_ofs = _mux_clr_ofs, \
	53	+ .upd_ofs = _upd_ofs, \
	54	+ .mux_shift = _shift, \
	55	+ .mux_width = _width, \
	56	+ .gate_shift = _gate, \
	57	+ .upd_shift = _upd, \
	58	+ .parent_names = _parents, \
	59	+ .num_parents = ARRAY_SIZE(_parents), \
	60	+ .flags = _flags, \
	61	+ .ops = &_ops, \
	62	+ }
	63	+
	64	+#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
	65	+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
	66	+ _gate, _upd_ofs, _upd, _flags) \
	67	+ GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
	68	+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
	69	+ _gate, _upd_ofs, _upd, _flags, \
	70	+ mtk_mux_gate_clr_set_upd_ops)
	71	+
	72	+#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
	73	+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
	74	+ _gate, _upd_ofs, _upd) \
	75	+ MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
	76	+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
	77	+ _width, _gate, _upd_ofs, _upd, \
	78	+ CLK_SET_RATE_PARENT)
	79	+
	80	+struct clk mtk_clk_register_mux(const struct mtk_mux mux,
	81	+ struct regmap *regmap,
	82	+ spinlock_t *lock);
	83	+
	84	+int mtk_clk_register_muxes(const struct mtk_mux *muxes,
	85	+ int num, struct device_node *node,
	86	+ spinlock_t *lock,
	87	+ struct clk_onecell_data *clk_data);
	88	+
	89	+#endif /* __DRV_CLK_MTK_MUX_H */

drivers/clk/mediatek/clk-pll.c+55−32

@@ -27,11 +27,13 @@ · 26 unmodified lines
27	27	#define CON0_BASE_EN BIT(0)
28	28	#define CON0_PWR_ON BIT(0)
29	29	#define CON0_ISO_EN BIT(1)
30		−#define CON0_PCW_CHG BIT(31)
	30	+#define PCW_CHG_MASK BIT(31)
31	31
32	32	#define AUDPLL_TUNER_EN BIT(31)
33	33
34	34	#define POSTDIV_MASK 0x7
	35	+
	36	+/* default 7 bits integer, can be overridden with pcwibits. */
35	37	#define INTEGER_BITS 7
36	38
37	39	/*
@@ -49,6 +51,7 @@ struct mtk_clk_pll { · 11 unmodified lines
49	51	void __iomem *tuner_addr;
50	52	void __iomem *tuner_en_addr;
51	53	void __iomem *pcw_addr;
	54	+ void __iomem *pcw_chg_addr;
52	55	const struct mtk_pll_data *data;
53	56	};
54	57
@@ -68,12 +71,15 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, · 13 unmodified lines
68	71	u32 pcw, int postdiv)
69	72	{
70	73	int pcwbits = pll->data->pcwbits;
71		− int pcwfbits;
	74	+ int pcwfbits = 0;
	75	+ int ibits;
72	76	u64 vco;
73	77	u8 c = 0;
74	78
75	79	/* The fractional part of the PLL divider. */
76		− pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
	80	+ ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
	81	+ if (pcwbits > ibits)
	82	+ pcwfbits = pcwbits - ibits;
77	83
78	84	vco = (u64)fin * pcw;
79	85
@@ -88,13 +94,39 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, · 8 unmodified lines
88	94	return ((unsigned long)vco + postdiv - 1) / postdiv;
89	95	}
90	96
	97	+static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
	98	+{
	99	+ u32 r;
	100	+
	101	+ if (pll->tuner_en_addr) {
	102	+ r = readl(pll->tuner_en_addr) \| BIT(pll->data->tuner_en_bit);
	103	+ writel(r, pll->tuner_en_addr);
	104	+ } else if (pll->tuner_addr) {
	105	+ r = readl(pll->tuner_addr) \| AUDPLL_TUNER_EN;
	106	+ writel(r, pll->tuner_addr);
	107	+ }
	108	+}
	109	+
	110	+static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
	111	+{
	112	+ u32 r;
	113	+
	114	+ if (pll->tuner_en_addr) {
	115	+ r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
	116	+ writel(r, pll->tuner_en_addr);
	117	+ } else if (pll->tuner_addr) {
	118	+ r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
	119	+ writel(r, pll->tuner_addr);
	120	+ }
	121	+}
	122	+
91	123	static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
92	124	int postdiv)
93	125	{
94		− u32 con1, val;
95		− int pll_en;
	126	+ u32 chg, val;
96	127
97		− pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
	128	+ /* disable tuner */
	129	+ __mtk_pll_tuner_disable(pll);
98	130
99	131	/* set postdiv */
100	132	val = readl(pll->pd_addr);
@@ -112,18 +144,15 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, · 11 unmodified lines
112	144	pll->data->pcw_shift);
113	145	val \|= pcw << pll->data->pcw_shift;
114	146	writel(val, pll->pcw_addr);
115		−
116		− con1 = readl(pll->base_addr + REG_CON1);
117		−
118		− if (pll_en)
119		− con1 \|= CON0_PCW_CHG;
120		−
121		− writel(con1, pll->base_addr + REG_CON1);
	147	+ chg = readl(pll->pcw_chg_addr) \| PCW_CHG_MASK;
	148	+ writel(chg, pll->pcw_chg_addr);
122	149	if (pll->tuner_addr)
123		− writel(con1 + 1, pll->tuner_addr);
	150	+ writel(val + 1, pll->tuner_addr);
	151	+
	152	+ /* restore tuner_en */
	153	+ __mtk_pll_tuner_enable(pll);
124	154
125		− if (pll_en)
126		− udelay(20);
	155	+ udelay(20);
127	156	}
128	157
129	158	/*
@@ -138,9 +167,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, · 8 unmodified lines
138	167	static void mtk_pll_calc_values(struct mtk_clk_pll pll, u32 pcw, u32 *postdiv,
139	168	u32 freq, u32 fin)
140	169	{
141		− unsigned long fmin = 1000 * MHZ;
	170	+ unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
142	171	const struct mtk_pll_div_table *div_table = pll->data->div_table;
143	172	u64 _pcw;
	173	+ int ibits;
144	174	u32 val;
145	175
146	176	if (freq > pll->data->fmax)
@@ -164,7 +194,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll pll, u32 pcw, u32 *postdiv, · 17 unmodified lines
164	194	}
165	195
166	196	/* _pcw = freq * postdiv / fin * 2^pcwfbits */
167		− _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
	197	+ ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
	198	+ _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
168	199	do_div(_pcw, fin);
169	200
170	201	*pcw = (u32)_pcw;
@@ -228,13 +259,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) · 57 unmodified lines
228	259	r \|= pll->data->en_mask;
229	260	writel(r, pll->base_addr + REG_CON0);
230	261
231		− if (pll->tuner_en_addr) {
232		− r = readl(pll->tuner_en_addr) \| BIT(pll->data->tuner_en_bit);
233		− writel(r, pll->tuner_en_addr);
234		− } else if (pll->tuner_addr) {
235		− r = readl(pll->tuner_addr) \| AUDPLL_TUNER_EN;
236		− writel(r, pll->tuner_addr);
237		− }
	262	+ __mtk_pll_tuner_enable(pll);
238	263
239	264	udelay(20);
240	265
@@ -258,13 +283,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) · 17 unmodified lines
258	283	writel(r, pll->base_addr + REG_CON0);
259	284	}
260	285
261		− if (pll->tuner_en_addr) {
262		− r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
263		− writel(r, pll->tuner_en_addr);
264		− } else if (pll->tuner_addr) {
265		− r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
266		− writel(r, pll->tuner_addr);
267		− }
	286	+ __mtk_pll_tuner_disable(pll);
268	287
269	288	r = readl(pll->base_addr + REG_CON0);
270	289	r &= ~CON0_BASE_EN;
@@ -302,6 +321,10 @@ static struct clk mtk_clk_register_pll(const struct mtk_pll_data data, · 31 unmodified lines
302	321	pll->pwr_addr = base + data->pwr_reg;
303	322	pll->pd_addr = base + data->pd_reg;
304	323	pll->pcw_addr = base + data->pcw_reg;
	324	+ if (data->pcw_chg_reg)
	325	+ pll->pcw_chg_addr = base + data->pcw_chg_reg;
	326	+ else
	327	+ pll->pcw_chg_addr = pll->base_addr + REG_CON1;
305	328	if (data->tuner_reg)
306	329	pll->tuner_addr = base + data->tuner_reg;
307	330	if (data->tuner_en_reg)

drivers/clk/qcom/Kconfig+6−0

@@ -243,6 +243,12 @@ config SDM_GCC_660 · 242 unmodified lines
243	243	Say Y if you want to use peripheral devices such as UART, SPI,
244	244	i2C, USB, UFS, SDDC, PCIe, etc.
245	245
	246	+config QCS_TURING_404
	247	+ tristate "QCS404 Turing Clock Controller"
	248	+ help
	249	+ Support for the Turing Clock Controller on QCS404, provides clocks
	250	+ and resets for the Turing subsystem.
	251	+
246	252	config SDM_GCC_845
247	253	tristate "SDM845 Global Clock Controller"
248	254	select QCOM_GDSC

drivers/clk/qcom/Makefile+1−0

@@ -42,6 +42,7 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o · 41 unmodified lines
42	42	obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
43	43	obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
44	44	obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
	45	+obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
45	46	obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
46	47	obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
47	48	obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o

drivers/clk/qcom/clk-branch.c+6−0

@@ -146,6 +146,12 @@ const struct clk_ops clk_branch2_ops = { · 145 unmodified lines
146	146	};
147	147	EXPORT_SYMBOL_GPL(clk_branch2_ops);
148	148
	149	+const struct clk_ops clk_branch2_aon_ops = {
	150	+ .enable = clk_branch2_enable,
	151	+ .is_enabled = clk_is_enabled_regmap,
	152	+};
	153	+EXPORT_SYMBOL_GPL(clk_branch2_aon_ops);
	154	+
149	155	const struct clk_ops clk_branch_simple_ops = {
150	156	.enable = clk_enable_regmap,
151	157	.disable = clk_disable_regmap,

drivers/clk/qcom/clk-branch.h+1−0

@@ -40,6 +40,7 @@ struct clk_branch { · 39 unmodified lines
40	40	extern const struct clk_ops clk_branch_ops;
41	41	extern const struct clk_ops clk_branch2_ops;
42	42	extern const struct clk_ops clk_branch_simple_ops;
	43	+extern const struct clk_ops clk_branch2_aon_ops;
43	44
44	45	#define to_clk_branch(_hw) \
45	46	container_of(to_clk_regmap(_hw), struct clk_branch, clkr)

drivers/clk/qcom/gcc-msm8998.c+1−1

@@ -2161,7 +2161,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { · 2160 unmodified lines
2161	2161
2162	2162	static struct clk_branch gcc_pcie_0_pipe_clk = {
2163	2163	.halt_reg = 0x6b018,
2164		− .halt_check = BRANCH_HALT,
	2164	+ .halt_check = BRANCH_HALT_SKIP,
2165	2165	.clkr = {
2166	2166	.enable_reg = 0x6b018,
2167	2167	.enable_mask = BIT(0),

drivers/clk/qcom/gcc-qcs404.c+90−0

@@ -260,6 +260,20 @@ static const char * const gcc_parent_names_15[] = { · 259 unmodified lines
260	260	"core_bi_pll_test_se",
261	261	};
262	262
	263	+static const struct parent_map gcc_parent_map_16[] = {
	264	+ { P_XO, 0 },
	265	+ { P_GPLL0_OUT_MAIN, 1 },
	266	+ { P_GPLL0_OUT_AUX, 2 },
	267	+ { P_CORE_BI_PLL_TEST_SE, 7 },
	268	+};
	269	+
	270	+static const char * const gcc_parent_names_16[] = {
	271	+ "cxo",
	272	+ "gpll0_out_main",
	273	+ "gpll0_out_aux",
	274	+ "core_bi_pll_test_se",
	275	+};
	276	+
263	277	static struct clk_fixed_factor cxo = {
264	278	.mult = 1,
265	279	.div = 1,
@@ -1194,6 +1208,28 @@ static struct clk_rcg2 vsync_clk_src = { · 928 unmodified lines
1194	1208	},
1195	1209	};
1196	1210
	1211	+static const struct freq_tbl ftbl_cdsp_bimc_clk_src[] = {
	1212	+ F(19200000, P_XO, 1, 0, 0),
	1213	+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
	1214	+ F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
	1215	+ F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
	1216	+ { }
	1217	+};
	1218	+
	1219	+static struct clk_rcg2 cdsp_bimc_clk_src = {
	1220	+ .cmd_rcgr = 0x5e010,
	1221	+ .mnd_width = 0,
	1222	+ .hid_width = 5,
	1223	+ .parent_map = gcc_parent_map_16,
	1224	+ .freq_tbl = ftbl_cdsp_bimc_clk_src,
	1225	+ .clkr.hw.init = &(struct clk_init_data) {
	1226	+ .name = "cdsp_bimc_clk_src",
	1227	+ .parent_names = gcc_parent_names_16,
	1228	+ .num_parents = 4,
	1229	+ .ops = &clk_rcg2_ops,
	1230	+ },
	1231	+};
	1232	+
1197	1233	static struct clk_branch gcc_apss_ahb_clk = {
1198	1234	.halt_reg = 0x4601c,
1199	1235	.halt_check = BRANCH_HALT_VOTED,
@@ -1255,6 +1291,24 @@ static struct clk_branch gcc_bimc_gpu_clk = { · 55 unmodified lines
1255	1291	},
1256	1292	};
1257	1293
	1294	+static struct clk_branch gcc_bimc_cdsp_clk = {
	1295	+ .halt_reg = 0x31030,
	1296	+ .halt_check = BRANCH_HALT,
	1297	+ .clkr = {
	1298	+ .enable_reg = 0x31030,
	1299	+ .enable_mask = BIT(0),
	1300	+ .hw.init = &(struct clk_init_data) {
	1301	+ .name = "gcc_bimc_cdsp_clk",
	1302	+ .parent_names = (const char *[]) {
	1303	+ "cdsp_bimc_clk_src",
	1304	+ },
	1305	+ .num_parents = 1,
	1306	+ .flags = CLK_SET_RATE_PARENT,
	1307	+ .ops = &clk_branch2_ops,
	1308	+ },
	1309	+ },
	1310	+};
	1311	+
1258	1312	static struct clk_branch gcc_bimc_mdss_clk = {
1259	1313	.halt_reg = 0x31038,
1260	1314	.halt_check = BRANCH_HALT,
@@ -1792,6 +1846,24 @@ static struct clk_branch gcc_gfx_tbu_clk = { · 531 unmodified lines
1792	1846	},
1793	1847	};
1794	1848
	1849	+static struct clk_branch gcc_cdsp_tbu_clk = {
	1850	+ .halt_reg = 0x1203c,
	1851	+ .halt_check = BRANCH_VOTED,
	1852	+ .clkr = {
	1853	+ .enable_reg = 0x13020,
	1854	+ .enable_mask = BIT(9),
	1855	+ .hw.init = &(struct clk_init_data) {
	1856	+ .name = "gcc_cdsp_tbu_clk",
	1857	+ .parent_names = (const char *[]) {
	1858	+ "cdsp_bimc_clk_src",
	1859	+ },
	1860	+ .num_parents = 1,
	1861	+ .flags = CLK_SET_RATE_PARENT,
	1862	+ .ops = &clk_branch2_ops,
	1863	+ },
	1864	+ },
	1865	+};
	1866	+
1795	1867	static struct clk_branch gcc_gp1_clk = {
1796	1868	.halt_reg = 0x8000,
1797	1869	.halt_check = BRANCH_HALT,
@@ -2304,6 +2376,19 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { · 506 unmodified lines
2304	2376	},
2305	2377	};
2306	2378
	2379	+static struct clk_branch gcc_cdsp_cfg_ahb_clk = {
	2380	+ .halt_reg = 0x5e004,
	2381	+ .halt_check = BRANCH_HALT,
	2382	+ .clkr = {
	2383	+ .enable_reg = 0x5e004,
	2384	+ .enable_mask = BIT(0),
	2385	+ .hw.init = &(struct clk_init_data) {
	2386	+ .name = "gcc_cdsp_cfg_ahb_cbcr",
	2387	+ .ops = &clk_branch2_ops,
	2388	+ },
	2389	+ },
	2390	+};
	2391	+
2307	2392	static struct clk_branch gcc_sdcc2_ahb_clk = {
2308	2393	.halt_reg = 0x4301c,
2309	2394	.halt_check = BRANCH_HALT,
@@ -2548,6 +2633,7 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { · 238 unmodified lines
2548	2633	[GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2549	2634	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
2550	2635	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
	2636	+ [GCC_BIMC_CDSP_CLK] = &gcc_bimc_cdsp_clk.clkr,
2551	2637	[GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
2552	2638	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2553	2639	[GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
@@ -2605,6 +2691,7 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { · 51 unmodified lines
2605	2691	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2606	2692	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2607	2693	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
	2694	+ [GCC_CDSP_CFG_AHB_CLK] = &gcc_cdsp_cfg_ahb_clk.clkr,
2608	2695	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2609	2696	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2610	2697	[GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
@@ -2645,6 +2732,7 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { · 34 unmodified lines
2645	2732	[GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2646	2733	[GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2647	2734	[GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
	2735	+ [GCC_CDSP_BIMC_CLK_SRC] = &cdsp_bimc_clk_src.clkr,
2648	2736	[GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
2649	2737	&gcc_usb_hs_inactivity_timers_clk.clkr,
2650	2738	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
@@ -2653,6 +2741,7 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { · 2 unmodified lines
2653	2741	[GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
2654	2742	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2655	2743	[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
	2744	+ [GCC_CDSP_TBU_CLK] = &gcc_cdsp_tbu_clk.clkr,
2656	2745	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2657	2746	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2658	2747	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
@@ -2664,6 +2753,7 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { · 5 unmodified lines
2664	2753
2665	2754	static const struct qcom_reset_map gcc_qcs404_resets[] = {
2666	2755	[GCC_GENI_IR_BCR] = { 0x0F000 },
	2756	+ [GCC_CDSP_RESTART] = { 0x18000 },
2667	2757	[GCC_USB_HS_BCR] = { 0x41000 },
2668	2758	[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2669	2759	[GCC_QUSB2_PHY_BCR] = { 0x4103c },

drivers/clk/qcom/turingcc-qcs404.c+170−0

@@ -0,0 +1,170 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright (c) 2019, Linaro Ltd.
	4	+ */
	5	+
	6	+#include <linux/bitops.h>
	7	+#include <linux/err.h>
	8	+#include <linux/platform_device.h>
	9	+#include <linux/module.h>
	10	+#include <linux/of_address.h>
	11	+#include <linux/pm_clock.h>
	12	+#include <linux/pm_runtime.h>
	13	+#include <linux/regmap.h>
	14	+
	15	+#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
	16	+
	17	+#include "clk-regmap.h"
	18	+#include "clk-branch.h"
	19	+#include "common.h"
	20	+#include "reset.h"
	21	+
	22	+static struct clk_branch turing_wrapper_aon_cbcr = {
	23	+ .halt_reg = 0x5098,
	24	+ .halt_check = BRANCH_HALT,
	25	+ .clkr = {
	26	+ .enable_reg = 0x5098,
	27	+ .enable_mask = BIT(0),
	28	+ .hw.init = &(struct clk_init_data) {
	29	+ .name = "turing_wrapper_aon_clk",
	30	+ .ops = &clk_branch2_aon_ops,
	31	+ },
	32	+ },
	33	+};
	34	+
	35	+static struct clk_branch turing_q6ss_ahbm_aon_cbcr = {
	36	+ .halt_reg = 0x9000,
	37	+ .halt_check = BRANCH_HALT,
	38	+ .clkr = {
	39	+ .enable_reg = 0x9000,
	40	+ .enable_mask = BIT(0),
	41	+ .hw.init = &(struct clk_init_data) {
	42	+ .name = "turing_q6ss_ahbm_aon_cbcr",
	43	+ .ops = &clk_branch2_ops,
	44	+ },
	45	+ },
	46	+};
	47	+
	48	+static struct clk_branch turing_q6ss_q6_axim_clk = {
	49	+ .halt_reg = 0xb000,
	50	+ .halt_check = BRANCH_HALT,
	51	+ .clkr = {
	52	+ .enable_reg = 0xb000,
	53	+ .enable_mask = BIT(0),
	54	+ .hw.init = &(struct clk_init_data) {
	55	+ .name = "turing_q6ss_q6_axim_clk",
	56	+ .ops = &clk_branch2_aon_ops,
	57	+ },
	58	+ },
	59	+};
	60	+
	61	+static struct clk_branch turing_q6ss_ahbs_aon_cbcr = {
	62	+ .halt_reg = 0x10000,
	63	+ .halt_check = BRANCH_HALT,
	64	+ .clkr = {
	65	+ .enable_reg = 0x10000,
	66	+ .enable_mask = BIT(0),
	67	+ .hw.init = &(struct clk_init_data) {
	68	+ .name = "turing_q6ss_ahbs_aon_clk",
	69	+ .ops = &clk_branch2_aon_ops,
	70	+ },
	71	+ },
	72	+};
	73	+
	74	+static struct clk_branch turing_wrapper_qos_ahbs_aon_cbcr = {
	75	+ .halt_reg = 0x11014,
	76	+ .halt_check = BRANCH_HALT,
	77	+ .clkr = {
	78	+ .enable_reg = 0x11014,
	79	+ .enable_mask = BIT(0),
	80	+ .hw.init = &(struct clk_init_data) {
	81	+ .name = "turing_wrapper_qos_ahbs_aon_clk",
	82	+ .ops = &clk_branch2_aon_ops,
	83	+ },
	84	+ },
	85	+};
	86	+
	87	+static struct clk_regmap *turingcc_clocks[] = {
	88	+ [TURING_WRAPPER_AON_CLK] = &turing_wrapper_aon_cbcr.clkr,
	89	+ [TURING_Q6SS_AHBM_AON_CLK] = &turing_q6ss_ahbm_aon_cbcr.clkr,
	90	+ [TURING_Q6SS_Q6_AXIM_CLK] = &turing_q6ss_q6_axim_clk.clkr,
	91	+ [TURING_Q6SS_AHBS_AON_CLK] = &turing_q6ss_ahbs_aon_cbcr.clkr,
	92	+ [TURING_WRAPPER_QOS_AHBS_AON_CLK] = &turing_wrapper_qos_ahbs_aon_cbcr.clkr,
	93	+};
	94	+
	95	+static const struct regmap_config turingcc_regmap_config = {
	96	+ .reg_bits = 32,
	97	+ .reg_stride = 4,
	98	+ .val_bits = 32,
	99	+ .max_register = 0x30000,
	100	+ .fast_io = true,
	101	+};
	102	+
	103	+static const struct qcom_cc_desc turingcc_desc = {
	104	+ .config = &turingcc_regmap_config,
	105	+ .clks = turingcc_clocks,
	106	+ .num_clks = ARRAY_SIZE(turingcc_clocks),
	107	+};
	108	+
	109	+static int turingcc_probe(struct platform_device *pdev)
	110	+{
	111	+ int ret;
	112	+
	113	+ pm_runtime_enable(&pdev->dev);
	114	+ ret = pm_clk_create(&pdev->dev);
	115	+ if (ret)
	116	+ goto disable_pm_runtime;
	117	+
	118	+ ret = pm_clk_add(&pdev->dev, NULL);
	119	+ if (ret < 0) {
	120	+ dev_err(&pdev->dev, "failed to acquire iface clock\n");
	121	+ goto destroy_pm_clk;
	122	+ }
	123	+
	124	+ ret = qcom_cc_probe(pdev, &turingcc_desc);
	125	+ if (ret < 0)
	126	+ goto destroy_pm_clk;
	127	+
	128	+ return 0;
	129	+
	130	+destroy_pm_clk:
	131	+ pm_clk_destroy(&pdev->dev);
	132	+
	133	+disable_pm_runtime:
	134	+ pm_runtime_disable(&pdev->dev);
	135	+
	136	+ return ret;
	137	+}
	138	+
	139	+static int turingcc_remove(struct platform_device *pdev)
	140	+{
	141	+ pm_clk_destroy(&pdev->dev);
	142	+ pm_runtime_disable(&pdev->dev);
	143	+
	144	+ return 0;
	145	+}
	146	+
	147	+static const struct dev_pm_ops turingcc_pm_ops = {
	148	+ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
	149	+};
	150	+
	151	+static const struct of_device_id turingcc_match_table[] = {
	152	+ { .compatible = "qcom,qcs404-turingcc" },
	153	+ { }
	154	+};
	155	+MODULE_DEVICE_TABLE(of, turingcc_match_table);
	156	+
	157	+static struct platform_driver turingcc_driver = {
	158	+ .probe = turingcc_probe,
	159	+ .remove = turingcc_remove,
	160	+ .driver = {
	161	+ .name = "qcs404-turingcc",
	162	+ .of_match_table = turingcc_match_table,
	163	+ .pm = &turingcc_pm_ops,
	164	+ },
	165	+};
	166	+
	167	+module_platform_driver(turingcc_driver);
	168	+
	169	+MODULE_DESCRIPTION("Qualcomm QCS404 Turing Clock Controller");
	170	+MODULE_LICENSE("GPL v2");

drivers/clk/renesas/r7s9210-cpg-mssr.c+2−1

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	11
12	12	#include <linux/clk.h>
13	13	#include <linux/clk-provider.h>
	14	+#include <linux/io.h>
14	15	#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
15	16	#include "renesas-cpg-mssr.h"
16	17
@@ -119,7 +120,7 @@ static void __init r7s9210_update_clk_table(struct clk *extal_clk, · 102 unmodified lines
119	120	if (clk_get_rate(extal_clk) > 12000000)
120	121	cpg_mode = 1;
121	122
122		− frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
	123	+ frqcr = readl(base + CPG_FRQCR) & 0xFFF;
123	124	if (frqcr == 0x012)
124	125	index = 0;
125	126	else if (frqcr == 0x112)

drivers/clk/renesas/r8a774a1-cpg-mssr.c+9−9

@@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { · 70 unmodified lines
71	71	DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
72	72
73	73	/* Core Clock Outputs */
74		− DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
75		− DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
	74	+ DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
	75	+ DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
76	76	DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
77	77	DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
78	78	DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { · 44 unmodified lines
123	123	DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO),
124	124	DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO),
125	125	DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO),
126		− DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3),
127		− DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3),
	126	+ DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S3D1),
	127	+ DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S3D1),
128	128	DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3),
129	129	DEF_MOD("cmt3", 300, R8A774A1_CLK_R),
130	130	DEF_MOD("cmt2", 301, R8A774A1_CLK_R),
@@ -143,8 +143,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { · 12 unmodified lines
143	143	DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
144	144	DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
145	145	DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
146		− DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3),
147		− DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3),
	146	+ DEF_MOD("audmac1", 501, R8A774A1_CLK_S1D2),
	147	+ DEF_MOD("audmac0", 502, R8A774A1_CLK_S1D2),
148	148	DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
149	149	DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
150	150	DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
@@ -165,9 +165,9 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { · 14 unmodified lines
165	165	DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2),
166	166	DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1),
167	167	DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
168		− DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4),
169		− DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4),
170		− DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
	168	+ DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D2),
	169	+ DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D2),
	170	+ DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D2),
171	171	DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
172	172	DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
173	173	DEF_MOD("du2", 722, R8A774A1_CLK_S2D1),

drivers/clk/renesas/r8a774c0-cpg-mssr.c+4−3

@@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { · 80 unmodified lines
81	81	/* Core Clock Outputs */
82	82	DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1),
83	83	DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1),
	84	+ DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
84	85	DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
85	86	DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1),
86	87	DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),
@@ -157,7 +158,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { · 70 unmodified lines
157	158	DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
158	159	DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
159	160
160		− DEF_MOD("audmac0", 502, R8A774C0_CLK_S3D4),
	161	+ DEF_MOD("audmac0", 502, R8A774C0_CLK_S1D2),
161	162	DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
162	163	DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
163	164	DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
@@ -177,8 +178,8 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { · 13 unmodified lines
177	178	DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1),
178	179	DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
179	180
180		− DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D4),
181		− DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
	181	+ DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2),
	182	+ DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D2),
182	183	DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
183	184	DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
184	185	DEF_MOD("du0", 724, R8A774C0_CLK_S1D1),

drivers/clk/renesas/r8a7795-cpg-mssr.c+21−20

@@ -3,6 +3,7 @@ · 2 unmodified lines
3	3	* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
4	4	*
5	5	* Copyright (C) 2015 Glider bvba
	6	+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
6	7	*
7	8	* Based on clk-rcar-gen3.c
8	9	*
@@ -73,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { · 64 unmodified lines
73	74	DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
74	75
75	76	/* Core Clock Outputs */
76		− DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
77		− DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
	77	+ DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
	78	+ DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
78	79	DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
79	80	DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
80	81	DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -129,8 +130,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { · 48 unmodified lines
129	130	DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
130	131	DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
131	132	DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
132		− DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
133		− DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
	133	+ DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
	134	+ DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
134	135	DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
135	136	DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
136	137	DEF_MOD("cmt3", 300, R8A7795_CLK_R),
@@ -153,16 +154,16 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { · 16 unmodified lines
153	154	DEF_MOD("rwdt", 402, R8A7795_CLK_R),
154	155	DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
155	156	DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
156		− DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
157		− DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
158		− DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
159		− DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
160		− DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
161		− DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
162		− DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
163		− DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
164		− DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
165		− DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
	157	+ DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
	158	+ DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
	159	+ DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
	160	+ DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
	161	+ DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
	162	+ DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
	163	+ DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
	164	+ DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
	165	+ DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
	166	+ DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
166	167	DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
167	168	DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
168	169	DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
@@ -194,12 +195,12 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { · 25 unmodified lines
194	195	DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
195	196	DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
196	197	DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
197		− DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
198		− DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
199		− DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
200		− DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
201		− DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
202		− DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
	198	+ DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
	199	+ DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
	200	+ DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
	201	+ DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
	202	+ DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
	203	+ DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
203	204	DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
204	205	DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
205	206	DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),

drivers/clk/renesas/r8a7796-cpg-mssr.c+18−17

@@ -3,6 +3,7 @@ · 2 unmodified lines
3	3	* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
4	4	*
5	5	* Copyright (C) 2016 Glider bvba
	6	+ * Copyright (C) 2018 Renesas Electronics Corp.
6	7	*
7	8	* Based on r8a7795-cpg-mssr.c
8	9	*
@@ -73,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { · 64 unmodified lines
73	74	DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
74	75
75	76	/* Core Clock Outputs */
76		− DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
77		− DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
	77	+ DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
	78	+ DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
78	79	DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
79	80	DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
80	81	DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -126,8 +127,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { · 45 unmodified lines
126	127	DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
127	128	DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
128	129	DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
129		− DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
130		− DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
	130	+ DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
	131	+ DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
131	132	DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
132	133	DEF_MOD("cmt3", 300, R8A7796_CLK_R),
133	134	DEF_MOD("cmt2", 301, R8A7796_CLK_R),
@@ -146,16 +147,16 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { · 12 unmodified lines
146	147	DEF_MOD("rwdt", 402, R8A7796_CLK_R),
147	148	DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
148	149	DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
149		− DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
150		− DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
151		− DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
152		− DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
153		− DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
154		− DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
155		− DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
156		− DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
157		− DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
158		− DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
	150	+ DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
	151	+ DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
	152	+ DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
	153	+ DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
	154	+ DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
	155	+ DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
	156	+ DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
	157	+ DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
	158	+ DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
	159	+ DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
159	160	DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
160	161	DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
161	162	DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
@@ -176,9 +177,9 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { · 14 unmodified lines
176	177	DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
177	178	DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
178	179	DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
179		− DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
180		− DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
181		− DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
	180	+ DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
	181	+ DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
	182	+ DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
182	183	DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
183	184	DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
184	185	DEF_MOD("du2", 722, R8A7796_CLK_S2D1),

drivers/clk/renesas/r8a77965-cpg-mssr.c+17−16

@@ -3,6 +3,7 @@ · 2 unmodified lines
3	3	* r8a77965 Clock Pulse Generator / Module Standby and Software Reset
4	4	*
5	5	* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
	6	+ * Copyright (C) 2019 Renesas Electronics Corp.
6	7	*
7	8	* Based on r8a7795-cpg-mssr.c
8	9	*
@@ -71,7 +72,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { · 62 unmodified lines
71	72	DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
72	73
73	74	/* Core Clock Outputs */
74		− DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
	75	+ DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
75	76	DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
76	77	DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
77	78	DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -123,8 +124,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { · 45 unmodified lines
123	124	DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
124	125	DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
125	126	DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
126		− DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
127		− DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
	127	+ DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
	128	+ DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
128	129	DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
129	130
130	131	DEF_MOD("cmt3", 300, R8A77965_CLK_R),
@@ -146,16 +147,16 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { · 15 unmodified lines
146	147	DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
147	148	DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
148	149
149		− DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
150		− DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
151		− DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
152		− DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
153		− DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
154		− DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
155		− DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
156		− DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
157		− DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
158		− DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
	150	+ DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
	151	+ DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
	152	+ DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
	153	+ DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
	154	+ DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
	155	+ DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
	156	+ DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
	157	+ DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
	158	+ DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
	159	+ DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
159	160	DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
160	161	DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
161	162	DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
@@ -175,9 +176,9 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { · 13 unmodified lines
175	176	DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
176	177	DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
177	178
178		− DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
179		− DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
180		− DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
	179	+ DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
	180	+ DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
	181	+ DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
181	182	DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
182	183	DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
183	184	DEF_MOD("du3", 721, R8A77965_CLK_S2D1),

drivers/clk/renesas/r8a77980-cpg-mssr.c+1−1

@@ -171,7 +171,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { · 170 unmodified lines
171	171	DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
172	172	DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
173	173	DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
174		− DEF_MOD("rpc-if", 917, R8A77980_CLK_RPC),
	174	+ DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
175	175	DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
176	176	DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
177	177	DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),

drivers/clk/renesas/r8a77990-cpg-mssr.c+13−12

@@ -2,7 +2,7 @@ · 1 unmodified line
2	2	/*
3	3	* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
4	4	*
5		− * Copyright (C) 2018 Renesas Electronics Corp.
	5	+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
6	6	*
7	7	* Based on r8a7795-cpg-mssr.c
8	8	*
@@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { · 72 unmodified lines
81	81	/* Core Clock Outputs */
82	82	DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
83	83	DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
	84	+ DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
84	85	DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
85	86	DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
86	87	DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
@@ -152,15 +153,15 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { · 65 unmodified lines
152	153	DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
153	154	DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
154	155
155		− DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
156		− DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
157		− DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
158		− DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
159		− DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
160		− DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
161		− DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
162		− DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
163		− DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
	156	+ DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
	157	+ DEF_MOD("drif31", 508, R8A77990_CLK_S3D2),
	158	+ DEF_MOD("drif30", 509, R8A77990_CLK_S3D2),
	159	+ DEF_MOD("drif21", 510, R8A77990_CLK_S3D2),
	160	+ DEF_MOD("drif20", 511, R8A77990_CLK_S3D2),
	161	+ DEF_MOD("drif11", 512, R8A77990_CLK_S3D2),
	162	+ DEF_MOD("drif10", 513, R8A77990_CLK_S3D2),
	163	+ DEF_MOD("drif01", 514, R8A77990_CLK_S3D2),
	164	+ DEF_MOD("drif00", 515, R8A77990_CLK_S3D2),
164	165	DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
165	166	DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
166	167	DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
@@ -180,8 +181,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { · 13 unmodified lines
180	181	DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
181	182	DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
182	183
183		− DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
184		− DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
	184	+ DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
	185	+ DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
185	186	DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
186	187	DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
187	188	DEF_MOD("du0", 724, R8A77990_CLK_S1D1),

drivers/clk/renesas/r8a77995-cpg-mssr.c+1−1

@@ -133,7 +133,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { · 132 unmodified lines
133	133	DEF_MOD("rwdt", 402, R8A77995_CLK_R),
134	134	DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
135	135	DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
136		− DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
	136	+ DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
137	137	DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
138	138	DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
139	139	DEF_MOD("thermal", 522, R8A77995_CLK_CP),

drivers/clk/renesas/r9a06g032-clocks.c+1−0

@@ -170,6 +170,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = { · 169 unmodified lines
170	170	D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
171	171	D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
172	172	D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
	173	+ D_GATE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
173	174	D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
174	175	D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
175	176	D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),

drivers/clk/renesas/rcar-gen3-cpg.c+33−38

@@ -3,6 +3,7 @@ · 2 unmodified lines
3	3	* R-Car Gen3 Clock Pulse Generator
4	4	*
5	5	* Copyright (C) 2015-2018 Glider bvba
	6	+ * Copyright (C) 2019 Renesas Electronics Corp.
6	7	*
7	8	* Based on clk-rcar-gen3.c
8	9	*
@@ -88,14 +89,13 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, · 79 unmodified lines
88	89	#define CPG_FRQCRB 0x00000004
89	90	#define CPG_FRQCRB_KICK BIT(31)
90	91	#define CPG_FRQCRC 0x000000e0
91		−#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8)
92		−#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0)
93	92
94	93	struct cpg_z_clk {
95	94	struct clk_hw hw;
96	95	void __iomem *reg;
97	96	void __iomem *kick_reg;
98	97	unsigned long mask;
	98	+ unsigned int fixed_div;
99	99	};
100	100
101	101	#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
@@ -110,17 +110,18 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, · 8 unmodified lines
110	110	val = readl(zclk->reg) & zclk->mask;
111	111	mult = 32 - (val >> __ffs(zclk->mask));
112	112
113		− /* Factor of 2 is for fixed divider */
114		− return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);
	113	+ return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
	114	+ 32 * zclk->fixed_div);
115	115	}
116	116
117	117	static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
118	118	unsigned long *parent_rate)
119	119	{
120		− /* Factor of 2 is for fixed divider */
121		− unsigned long prate = *parent_rate / 2;
	120	+ struct cpg_z_clk *zclk = to_z_clk(hw);
	121	+ unsigned long prate;
122	122	unsigned int mult;
123	123
	124	+ prate = *parent_rate / zclk->fixed_div;
124	125	mult = div_u64(rate * 32ULL, prate);
125	126	mult = clamp(mult, 1U, 32U);
126	127
@@ -134,8 +135,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, · 7 unmodified lines
134	135	unsigned int mult;
135	136	unsigned int i;
136	137
137		− /* Factor of 2 is for fixed divider */
138		− mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
	138	+ mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
	139	+ parent_rate);
139	140	mult = clamp(mult, 1U, 32U);
140	141
141	142	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
@@ -178,7 +179,8 @@ static const struct clk_ops cpg_z_clk_ops = { · 36 unmodified lines
178	179	static struct clk * __init cpg_z_clk_register(const char *name,
179	180	const char *parent_name,
180	181	void __iomem *reg,
181		− unsigned long mask)
	182	+ unsigned int div,
	183	+ unsigned int offset)
182	184	{
183	185	struct clk_init_data init;
184	186	struct cpg_z_clk *zclk;
@@ -197,7 +199,8 @@ static struct clk * __init cpg_z_clk_register(const char *name, · 12 unmodified lines
197	199	zclk->reg = reg + CPG_FRQCRC;
198	200	zclk->kick_reg = reg + CPG_FRQCRB;
199	201	zclk->hw.init = &init;
200		− zclk->mask = mask;
	202	+ zclk->mask = GENMASK(offset + 4, offset);
	203	+ zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
201	204
202	205	clk = clk_register(NULL, &zclk->hw);
203	206	if (IS_ERR(clk))
@@ -234,8 +237,6 @@ struct sd_clock { · 30 unmodified lines
234	237	const struct sd_div_table *div_table;
235	238	struct cpg_simple_notifier csn;
236	239	unsigned int div_num;
237		− unsigned int div_min;
238		− unsigned int div_max;
239	240	unsigned int cur_div_idx;
240	241	};
241	242
@@ -312,14 +313,20 @@ static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, · 70 unmodified lines
312	313	unsigned long rate,
313	314	unsigned long parent_rate)
314	315	{
315		− unsigned int div;
316		−
317		− if (!rate)
318		− rate = 1;
319		−
320		− div = DIV_ROUND_CLOSEST(parent_rate, rate);
	316	+ unsigned long calc_rate, diff, diff_min = ULONG_MAX;
	317	+ unsigned int i, best_div = 0;
	318	+
	319	+ for (i = 0; i < clock->div_num; i++) {
	320	+ calc_rate = DIV_ROUND_CLOSEST(parent_rate,
	321	+ clock->div_table[i].div);
	322	+ diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate;
	323	+ if (diff < diff_min) {
	324	+ best_div = clock->div_table[i].div;
	325	+ diff_min = diff;
	326	+ }
	327	+ }
321	328
322		− return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
	329	+ return best_div;
323	330	}
324	331
325	332	static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -369,27 +376,26 @@ static u32 cpg_quirks __initdata; · 43 unmodified lines
369	376	#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
370	377	#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
371	378
372		−static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
373		− void __iomem base, const char parent_name,
	379	+static struct clk * __init cpg_sd_clk_register(const char *name,
	380	+ void __iomem base, unsigned int offset, const char parent_name,
374	381	struct raw_notifier_head *notifiers)
375	382	{
376	383	struct clk_init_data init;
377	384	struct sd_clock *clock;
378	385	struct clk *clk;
379		− unsigned int i;
380	386	u32 val;
381	387
382	388	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
383	389	if (!clock)
384	390	return ERR_PTR(-ENOMEM);
385	391
386		− init.name = core->name;
	392	+ init.name = name;
387	393	init.ops = &cpg_sd_clock_ops;
388	394	init.flags = CLK_SET_RATE_PARENT;
389	395	init.parent_names = &parent_name;
390	396	init.num_parents = 1;
391	397
392		− clock->csn.reg = base + core->offset;
	398	+ clock->csn.reg = base + offset;
393	399	clock->hw.init = &init;
394	400	clock->div_table = cpg_sd_div_table;
395	401	clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
@@ -403,13 +409,6 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, · 7 unmodified lines
403	409	val \|= CPG_SD_STP_MASK \| (clock->div_table[0].val & CPG_SD_FC_MASK);
404	410	writel(val, clock->csn.reg);
405	411
406		− clock->div_max = clock->div_table[0].div;
407		− clock->div_min = clock->div_max;
408		− for (i = 1; i < clock->div_num; i++) {
409		− clock->div_max = max(clock->div_max, clock->div_table[i].div);
410		− clock->div_min = min(clock->div_min, clock->div_table[i].div);
411		− }
412		−
413	412	clk = clk_register(NULL, &clock->hw);
414	413	if (IS_ERR(clk))
415	414	goto free_clock;
@@ -606,8 +605,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, · 190 unmodified lines
606	605	break;
607	606
608	607	case CLK_TYPE_GEN3_SD:
609		− return cpg_sd_clk_register(core, base, __clk_get_name(parent),
610		− notifiers);
	608	+ return cpg_sd_clk_register(core->name, base, core->offset,
	609	+ __clk_get_name(parent), notifiers);
611	610
612	611	case CLK_TYPE_GEN3_R:
613	612	if (cpg_quirks & RCKCR_CKSEL) {
@@ -658,11 +657,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, · 44 unmodified lines
658	657
659	658	case CLK_TYPE_GEN3_Z:
660	659	return cpg_z_clk_register(core->name, __clk_get_name(parent),
661		− base, CPG_FRQCRC_ZFC_MASK);
662		−
663		− case CLK_TYPE_GEN3_Z2:
664		− return cpg_z_clk_register(core->name, __clk_get_name(parent),
665		− base, CPG_FRQCRC_Z2FC_MASK);
	660	+ base, core->div, core->offset);
666	661
667	662	case CLK_TYPE_GEN3_OSC:
668	663	/*

drivers/clk/renesas/rcar-gen3-cpg.h+4−1

@@ -3,6 +3,7 @@ · 2 unmodified lines
3	3	* R-Car Gen3 Clock Pulse Generator
4	4	*
5	5	* Copyright (C) 2015-2018 Glider bvba
	6	+ * Copyright (C) 2018 Renesas Electronics Corp.
6	7	*
7	8	*/
8	9
@@ -20,7 +21,6 @@ enum rcar_gen3_clk_types { · 11 unmodified lines
20	21	CLK_TYPE_GEN3_R,
21	22	CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
22	23	CLK_TYPE_GEN3_Z,
23		− CLK_TYPE_GEN3_Z2,
24	24	CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
25	25	CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
26	26	CLK_TYPE_GEN3_RPCSRC,
@@ -51,6 +51,9 @@ enum rcar_gen3_clk_types { · 24 unmodified lines
51	51	DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
52	52	(_parent0) << 16 \| (_parent1), .div = (_div0) << 16 \| (_div1))
53	53
	54	+#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
	55	+ DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
	56	+
54	57	struct rcar_gen3_cpg_pll_config {
55	58	u8 extal_div;
56	59	u8 pll1_mult;

include/dt-bindings/clock/imx7ulp-clock.h+0−1

@@ -65,7 +65,6 @@ · 64 unmodified lines
65	65	#define IMX7ULP_CLK_FLEXBUS 2
66	66	#define IMX7ULP_CLK_SEMA42_1 3
67	67	#define IMX7ULP_CLK_DMA_MUX1 4
68		−#define IMX7ULP_CLK_SNVS 5
69	68	#define IMX7ULP_CLK_CAAM 6
70	69	#define IMX7ULP_CLK_LPTPM4 7
71	70	#define IMX7ULP_CLK_LPTPM5 8

include/dt-bindings/clock/mt8183-clk.h+422−0

@@ -0,0 +1,422 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2018 MediaTek Inc.
	4	+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
	5	+ */
	6	+
	7	+#ifndef _DT_BINDINGS_CLK_MT8183_H
	8	+#define _DT_BINDINGS_CLK_MT8183_H
	9	+
	10	+/* APMIXED */
	11	+#define CLK_APMIXED_ARMPLL_LL 0
	12	+#define CLK_APMIXED_ARMPLL_L 1
	13	+#define CLK_APMIXED_CCIPLL 2
	14	+#define CLK_APMIXED_MAINPLL 3
	15	+#define CLK_APMIXED_UNIV2PLL 4
	16	+#define CLK_APMIXED_MSDCPLL 5
	17	+#define CLK_APMIXED_MMPLL 6
	18	+#define CLK_APMIXED_MFGPLL 7
	19	+#define CLK_APMIXED_TVDPLL 8
	20	+#define CLK_APMIXED_APLL1 9
	21	+#define CLK_APMIXED_APLL2 10
	22	+#define CLK_APMIXED_SSUSB_26M 11
	23	+#define CLK_APMIXED_APPLL_26M 12
	24	+#define CLK_APMIXED_MIPIC0_26M 13
	25	+#define CLK_APMIXED_MDPLLGP_26M 14
	26	+#define CLK_APMIXED_MMSYS_26M 15
	27	+#define CLK_APMIXED_UFS_26M 16
	28	+#define CLK_APMIXED_MIPIC1_26M 17
	29	+#define CLK_APMIXED_MEMPLL_26M 18
	30	+#define CLK_APMIXED_CLKSQ_LVPLL_26M 19
	31	+#define CLK_APMIXED_MIPID0_26M 20
	32	+#define CLK_APMIXED_MIPID1_26M 21
	33	+#define CLK_APMIXED_NR_CLK 22
	34	+
	35	+/* TOPCKGEN */
	36	+#define CLK_TOP_MUX_AXI 0
	37	+#define CLK_TOP_MUX_MM 1
	38	+#define CLK_TOP_MUX_CAM 2
	39	+#define CLK_TOP_MUX_MFG 3
	40	+#define CLK_TOP_MUX_CAMTG 4
	41	+#define CLK_TOP_MUX_UART 5
	42	+#define CLK_TOP_MUX_SPI 6
	43	+#define CLK_TOP_MUX_MSDC50_0_HCLK 7
	44	+#define CLK_TOP_MUX_MSDC50_0 8
	45	+#define CLK_TOP_MUX_MSDC30_1 9
	46	+#define CLK_TOP_MUX_MSDC30_2 10
	47	+#define CLK_TOP_MUX_AUDIO 11
	48	+#define CLK_TOP_MUX_AUD_INTBUS 12
	49	+#define CLK_TOP_MUX_FPWRAP_ULPOSC 13
	50	+#define CLK_TOP_MUX_SCP 14
	51	+#define CLK_TOP_MUX_ATB 15
	52	+#define CLK_TOP_MUX_SSPM 16
	53	+#define CLK_TOP_MUX_DPI0 17
	54	+#define CLK_TOP_MUX_SCAM 18
	55	+#define CLK_TOP_MUX_AUD_1 19
	56	+#define CLK_TOP_MUX_AUD_2 20
	57	+#define CLK_TOP_MUX_DISP_PWM 21
	58	+#define CLK_TOP_MUX_SSUSB_TOP_XHCI 22
	59	+#define CLK_TOP_MUX_USB_TOP 23
	60	+#define CLK_TOP_MUX_SPM 24
	61	+#define CLK_TOP_MUX_I2C 25
	62	+#define CLK_TOP_MUX_F52M_MFG 26
	63	+#define CLK_TOP_MUX_SENINF 27
	64	+#define CLK_TOP_MUX_DXCC 28
	65	+#define CLK_TOP_MUX_CAMTG2 29
	66	+#define CLK_TOP_MUX_AUD_ENG1 30
	67	+#define CLK_TOP_MUX_AUD_ENG2 31
	68	+#define CLK_TOP_MUX_FAES_UFSFDE 32
	69	+#define CLK_TOP_MUX_FUFS 33
	70	+#define CLK_TOP_MUX_IMG 34
	71	+#define CLK_TOP_MUX_DSP 35
	72	+#define CLK_TOP_MUX_DSP1 36
	73	+#define CLK_TOP_MUX_DSP2 37
	74	+#define CLK_TOP_MUX_IPU_IF 38
	75	+#define CLK_TOP_MUX_CAMTG3 39
	76	+#define CLK_TOP_MUX_CAMTG4 40
	77	+#define CLK_TOP_MUX_PMICSPI 41
	78	+#define CLK_TOP_SYSPLL_CK 42
	79	+#define CLK_TOP_SYSPLL_D2 43
	80	+#define CLK_TOP_SYSPLL_D3 44
	81	+#define CLK_TOP_SYSPLL_D5 45
	82	+#define CLK_TOP_SYSPLL_D7 46
	83	+#define CLK_TOP_SYSPLL_D2_D2 47
	84	+#define CLK_TOP_SYSPLL_D2_D4 48
	85	+#define CLK_TOP_SYSPLL_D2_D8 49
	86	+#define CLK_TOP_SYSPLL_D2_D16 50
	87	+#define CLK_TOP_SYSPLL_D3_D2 51
	88	+#define CLK_TOP_SYSPLL_D3_D4 52
	89	+#define CLK_TOP_SYSPLL_D3_D8 53
	90	+#define CLK_TOP_SYSPLL_D5_D2 54
	91	+#define CLK_TOP_SYSPLL_D5_D4 55
	92	+#define CLK_TOP_SYSPLL_D7_D2 56
	93	+#define CLK_TOP_SYSPLL_D7_D4 57
	94	+#define CLK_TOP_UNIVPLL_CK 58
	95	+#define CLK_TOP_UNIVPLL_D2 59
	96	+#define CLK_TOP_UNIVPLL_D3 60
	97	+#define CLK_TOP_UNIVPLL_D5 61
	98	+#define CLK_TOP_UNIVPLL_D7 62
	99	+#define CLK_TOP_UNIVPLL_D2_D2 63
	100	+#define CLK_TOP_UNIVPLL_D2_D4 64
	101	+#define CLK_TOP_UNIVPLL_D2_D8 65
	102	+#define CLK_TOP_UNIVPLL_D3_D2 66
	103	+#define CLK_TOP_UNIVPLL_D3_D4 67
	104	+#define CLK_TOP_UNIVPLL_D3_D8 68
	105	+#define CLK_TOP_UNIVPLL_D5_D2 69
	106	+#define CLK_TOP_UNIVPLL_D5_D4 70
	107	+#define CLK_TOP_UNIVPLL_D5_D8 71
	108	+#define CLK_TOP_APLL1_CK 72
	109	+#define CLK_TOP_APLL1_D2 73
	110	+#define CLK_TOP_APLL1_D4 74
	111	+#define CLK_TOP_APLL1_D8 75
	112	+#define CLK_TOP_APLL2_CK 76
	113	+#define CLK_TOP_APLL2_D2 77
	114	+#define CLK_TOP_APLL2_D4 78
	115	+#define CLK_TOP_APLL2_D8 79
	116	+#define CLK_TOP_TVDPLL_CK 80
	117	+#define CLK_TOP_TVDPLL_D2 81
	118	+#define CLK_TOP_TVDPLL_D4 82
	119	+#define CLK_TOP_TVDPLL_D8 83
	120	+#define CLK_TOP_TVDPLL_D16 84
	121	+#define CLK_TOP_MSDCPLL_CK 85
	122	+#define CLK_TOP_MSDCPLL_D2 86
	123	+#define CLK_TOP_MSDCPLL_D4 87
	124	+#define CLK_TOP_MSDCPLL_D8 88
	125	+#define CLK_TOP_MSDCPLL_D16 89
	126	+#define CLK_TOP_AD_OSC_CK 90
	127	+#define CLK_TOP_OSC_D2 91
	128	+#define CLK_TOP_OSC_D4 92
	129	+#define CLK_TOP_OSC_D8 93
	130	+#define CLK_TOP_OSC_D16 94
	131	+#define CLK_TOP_F26M_CK_D2 95
	132	+#define CLK_TOP_MFGPLL_CK 96
	133	+#define CLK_TOP_UNIVP_192M_CK 97
	134	+#define CLK_TOP_UNIVP_192M_D2 98
	135	+#define CLK_TOP_UNIVP_192M_D4 99
	136	+#define CLK_TOP_UNIVP_192M_D8 100
	137	+#define CLK_TOP_UNIVP_192M_D16 101
	138	+#define CLK_TOP_UNIVP_192M_D32 102
	139	+#define CLK_TOP_MMPLL_CK 103
	140	+#define CLK_TOP_MMPLL_D4 104
	141	+#define CLK_TOP_MMPLL_D4_D2 105
	142	+#define CLK_TOP_MMPLL_D4_D4 106
	143	+#define CLK_TOP_MMPLL_D5 107
	144	+#define CLK_TOP_MMPLL_D5_D2 108
	145	+#define CLK_TOP_MMPLL_D5_D4 109
	146	+#define CLK_TOP_MMPLL_D6 110
	147	+#define CLK_TOP_MMPLL_D7 111
	148	+#define CLK_TOP_CLK26M 112
	149	+#define CLK_TOP_CLK13M 113
	150	+#define CLK_TOP_ULPOSC 114
	151	+#define CLK_TOP_UNIVP_192M 115
	152	+#define CLK_TOP_MUX_APLL_I2S0 116
	153	+#define CLK_TOP_MUX_APLL_I2S1 117
	154	+#define CLK_TOP_MUX_APLL_I2S2 118
	155	+#define CLK_TOP_MUX_APLL_I2S3 119
	156	+#define CLK_TOP_MUX_APLL_I2S4 120
	157	+#define CLK_TOP_MUX_APLL_I2S5 121
	158	+#define CLK_TOP_APLL12_DIV0 122
	159	+#define CLK_TOP_APLL12_DIV1 123
	160	+#define CLK_TOP_APLL12_DIV2 124
	161	+#define CLK_TOP_APLL12_DIV3 125
	162	+#define CLK_TOP_APLL12_DIV4 126
	163	+#define CLK_TOP_APLL12_DIVB 127
	164	+#define CLK_TOP_UNIVPLL 128
	165	+#define CLK_TOP_ARMPLL_DIV_PLL1 129
	166	+#define CLK_TOP_ARMPLL_DIV_PLL2 130
	167	+#define CLK_TOP_UNIVPLL_D3_D16 131
	168	+#define CLK_TOP_NR_CLK 132
	169	+
	170	+/* CAMSYS */
	171	+#define CLK_CAM_LARB6 0
	172	+#define CLK_CAM_DFP_VAD 1
	173	+#define CLK_CAM_CAM 2
	174	+#define CLK_CAM_CAMTG 3
	175	+#define CLK_CAM_SENINF 4
	176	+#define CLK_CAM_CAMSV0 5
	177	+#define CLK_CAM_CAMSV1 6
	178	+#define CLK_CAM_CAMSV2 7
	179	+#define CLK_CAM_CCU 8
	180	+#define CLK_CAM_LARB3 9
	181	+#define CLK_CAM_NR_CLK 10
	182	+
	183	+/* INFRACFG_AO */
	184	+#define CLK_INFRA_PMIC_TMR 0
	185	+#define CLK_INFRA_PMIC_AP 1
	186	+#define CLK_INFRA_PMIC_MD 2
	187	+#define CLK_INFRA_PMIC_CONN 3
	188	+#define CLK_INFRA_SCPSYS 4
	189	+#define CLK_INFRA_SEJ 5
	190	+#define CLK_INFRA_APXGPT 6
	191	+#define CLK_INFRA_ICUSB 7
	192	+#define CLK_INFRA_GCE 8
	193	+#define CLK_INFRA_THERM 9
	194	+#define CLK_INFRA_I2C0 10
	195	+#define CLK_INFRA_I2C1 11
	196	+#define CLK_INFRA_I2C2 12
	197	+#define CLK_INFRA_I2C3 13
	198	+#define CLK_INFRA_PWM_HCLK 14
	199	+#define CLK_INFRA_PWM1 15
	200	+#define CLK_INFRA_PWM2 16
	201	+#define CLK_INFRA_PWM3 17
	202	+#define CLK_INFRA_PWM4 18
	203	+#define CLK_INFRA_PWM 19
	204	+#define CLK_INFRA_UART0 20
	205	+#define CLK_INFRA_UART1 21
	206	+#define CLK_INFRA_UART2 22
	207	+#define CLK_INFRA_UART3 23
	208	+#define CLK_INFRA_GCE_26M 24
	209	+#define CLK_INFRA_CQ_DMA_FPC 25
	210	+#define CLK_INFRA_BTIF 26
	211	+#define CLK_INFRA_SPI0 27
	212	+#define CLK_INFRA_MSDC0 28
	213	+#define CLK_INFRA_MSDC1 29
	214	+#define CLK_INFRA_MSDC2 30
	215	+#define CLK_INFRA_MSDC0_SCK 31
	216	+#define CLK_INFRA_DVFSRC 32
	217	+#define CLK_INFRA_GCPU 33
	218	+#define CLK_INFRA_TRNG 34
	219	+#define CLK_INFRA_AUXADC 35
	220	+#define CLK_INFRA_CPUM 36
	221	+#define CLK_INFRA_CCIF1_AP 37
	222	+#define CLK_INFRA_CCIF1_MD 38
	223	+#define CLK_INFRA_AUXADC_MD 39
	224	+#define CLK_INFRA_MSDC1_SCK 40
	225	+#define CLK_INFRA_MSDC2_SCK 41
	226	+#define CLK_INFRA_AP_DMA 42
	227	+#define CLK_INFRA_XIU 43
	228	+#define CLK_INFRA_DEVICE_APC 44
	229	+#define CLK_INFRA_CCIF_AP 45
	230	+#define CLK_INFRA_DEBUGSYS 46
	231	+#define CLK_INFRA_AUDIO 47
	232	+#define CLK_INFRA_CCIF_MD 48
	233	+#define CLK_INFRA_DXCC_SEC_CORE 49
	234	+#define CLK_INFRA_DXCC_AO 50
	235	+#define CLK_INFRA_DRAMC_F26M 51
	236	+#define CLK_INFRA_IRTX 52
	237	+#define CLK_INFRA_DISP_PWM 53
	238	+#define CLK_INFRA_CLDMA_BCLK 54
	239	+#define CLK_INFRA_AUDIO_26M_BCLK 55
	240	+#define CLK_INFRA_SPI1 56
	241	+#define CLK_INFRA_I2C4 57
	242	+#define CLK_INFRA_MODEM_TEMP_SHARE 58
	243	+#define CLK_INFRA_SPI2 59
	244	+#define CLK_INFRA_SPI3 60
	245	+#define CLK_INFRA_UNIPRO_SCK 61
	246	+#define CLK_INFRA_UNIPRO_TICK 62
	247	+#define CLK_INFRA_UFS_MP_SAP_BCLK 63
	248	+#define CLK_INFRA_MD32_BCLK 64
	249	+#define CLK_INFRA_SSPM 65
	250	+#define CLK_INFRA_UNIPRO_MBIST 66
	251	+#define CLK_INFRA_SSPM_BUS_HCLK 67
	252	+#define CLK_INFRA_I2C5 68
	253	+#define CLK_INFRA_I2C5_ARBITER 69
	254	+#define CLK_INFRA_I2C5_IMM 70
	255	+#define CLK_INFRA_I2C1_ARBITER 71
	256	+#define CLK_INFRA_I2C1_IMM 72
	257	+#define CLK_INFRA_I2C2_ARBITER 73
	258	+#define CLK_INFRA_I2C2_IMM 74
	259	+#define CLK_INFRA_SPI4 75
	260	+#define CLK_INFRA_SPI5 76
	261	+#define CLK_INFRA_CQ_DMA 77
	262	+#define CLK_INFRA_UFS 78
	263	+#define CLK_INFRA_AES_UFSFDE 79
	264	+#define CLK_INFRA_UFS_TICK 80
	265	+#define CLK_INFRA_MSDC0_SELF 81
	266	+#define CLK_INFRA_MSDC1_SELF 82
	267	+#define CLK_INFRA_MSDC2_SELF 83
	268	+#define CLK_INFRA_SSPM_26M_SELF 84
	269	+#define CLK_INFRA_SSPM_32K_SELF 85
	270	+#define CLK_INFRA_UFS_AXI 86
	271	+#define CLK_INFRA_I2C6 87
	272	+#define CLK_INFRA_AP_MSDC0 88
	273	+#define CLK_INFRA_MD_MSDC0 89
	274	+#define CLK_INFRA_USB 90
	275	+#define CLK_INFRA_DEVMPU_BCLK 91
	276	+#define CLK_INFRA_CCIF2_AP 92
	277	+#define CLK_INFRA_CCIF2_MD 93
	278	+#define CLK_INFRA_CCIF3_AP 94
	279	+#define CLK_INFRA_CCIF3_MD 95
	280	+#define CLK_INFRA_SEJ_F13M 96
	281	+#define CLK_INFRA_AES_BCLK 97
	282	+#define CLK_INFRA_I2C7 98
	283	+#define CLK_INFRA_I2C8 99
	284	+#define CLK_INFRA_FBIST2FPC 100
	285	+#define CLK_INFRA_NR_CLK 101
	286	+
	287	+/* MFGCFG */
	288	+#define CLK_MFG_BG3D 0
	289	+#define CLK_MFG_NR_CLK 1
	290	+
	291	+/* IMG */
	292	+#define CLK_IMG_OWE 0
	293	+#define CLK_IMG_WPE_B 1
	294	+#define CLK_IMG_WPE_A 2
	295	+#define CLK_IMG_MFB 3
	296	+#define CLK_IMG_RSC 4
	297	+#define CLK_IMG_DPE 5
	298	+#define CLK_IMG_FDVT 6
	299	+#define CLK_IMG_DIP 7
	300	+#define CLK_IMG_LARB2 8
	301	+#define CLK_IMG_LARB5 9
	302	+#define CLK_IMG_NR_CLK 10
	303	+
	304	+/* MMSYS_CONFIG */
	305	+#define CLK_MM_SMI_COMMON 0
	306	+#define CLK_MM_SMI_LARB0 1
	307	+#define CLK_MM_SMI_LARB1 2
	308	+#define CLK_MM_GALS_COMM0 3
	309	+#define CLK_MM_GALS_COMM1 4
	310	+#define CLK_MM_GALS_CCU2MM 5
	311	+#define CLK_MM_GALS_IPU12MM 6
	312	+#define CLK_MM_GALS_IMG2MM 7
	313	+#define CLK_MM_GALS_CAM2MM 8
	314	+#define CLK_MM_GALS_IPU2MM 9
	315	+#define CLK_MM_MDP_DL_TXCK 10
	316	+#define CLK_MM_IPU_DL_TXCK 11
	317	+#define CLK_MM_MDP_RDMA0 12
	318	+#define CLK_MM_MDP_RDMA1 13
	319	+#define CLK_MM_MDP_RSZ0 14
	320	+#define CLK_MM_MDP_RSZ1 15
	321	+#define CLK_MM_MDP_TDSHP 16
	322	+#define CLK_MM_MDP_WROT0 17
	323	+#define CLK_MM_FAKE_ENG 18
	324	+#define CLK_MM_DISP_OVL0 19
	325	+#define CLK_MM_DISP_OVL0_2L 20
	326	+#define CLK_MM_DISP_OVL1_2L 21
	327	+#define CLK_MM_DISP_RDMA0 22
	328	+#define CLK_MM_DISP_RDMA1 23
	329	+#define CLK_MM_DISP_WDMA0 24
	330	+#define CLK_MM_DISP_COLOR0 25
	331	+#define CLK_MM_DISP_CCORR0 26
	332	+#define CLK_MM_DISP_AAL0 27
	333	+#define CLK_MM_DISP_GAMMA0 28
	334	+#define CLK_MM_DISP_DITHER0 29
	335	+#define CLK_MM_DISP_SPLIT 30
	336	+#define CLK_MM_DSI0_MM 31
	337	+#define CLK_MM_DSI0_IF 32
	338	+#define CLK_MM_DPI_MM 33
	339	+#define CLK_MM_DPI_IF 34
	340	+#define CLK_MM_FAKE_ENG2 35
	341	+#define CLK_MM_MDP_DL_RX 36
	342	+#define CLK_MM_IPU_DL_RX 37
	343	+#define CLK_MM_26M 38
	344	+#define CLK_MM_MMSYS_R2Y 39
	345	+#define CLK_MM_DISP_RSZ 40
	346	+#define CLK_MM_MDP_WDMA0 41
	347	+#define CLK_MM_MDP_AAL 42
	348	+#define CLK_MM_MDP_CCORR 43
	349	+#define CLK_MM_DBI_MM 44
	350	+#define CLK_MM_DBI_IF 45
	351	+#define CLK_MM_NR_CLK 46
	352	+
	353	+/* VDEC_GCON */
	354	+#define CLK_VDEC_VDEC 0
	355	+#define CLK_VDEC_LARB1 1
	356	+#define CLK_VDEC_NR_CLK 2
	357	+
	358	+/* VENC_GCON */
	359	+#define CLK_VENC_LARB 0
	360	+#define CLK_VENC_VENC 1
	361	+#define CLK_VENC_JPGENC 2
	362	+#define CLK_VENC_NR_CLK 3
	363	+
	364	+/* AUDIO */
	365	+#define CLK_AUDIO_TML 0
	366	+#define CLK_AUDIO_DAC_PREDIS 1
	367	+#define CLK_AUDIO_DAC 2
	368	+#define CLK_AUDIO_ADC 3
	369	+#define CLK_AUDIO_APLL_TUNER 4
	370	+#define CLK_AUDIO_APLL2_TUNER 5
	371	+#define CLK_AUDIO_24M 6
	372	+#define CLK_AUDIO_22M 7
	373	+#define CLK_AUDIO_AFE 8
	374	+#define CLK_AUDIO_I2S4 9
	375	+#define CLK_AUDIO_I2S3 10
	376	+#define CLK_AUDIO_I2S2 11
	377	+#define CLK_AUDIO_I2S1 12
	378	+#define CLK_AUDIO_PDN_ADDA6_ADC 13
	379	+#define CLK_AUDIO_TDM 14
	380	+#define CLK_AUDIO_NR_CLK 15
	381	+
	382	+/* IPU_CONN */
	383	+#define CLK_IPU_CONN_IPU 0
	384	+#define CLK_IPU_CONN_AHB 1
	385	+#define CLK_IPU_CONN_AXI 2
	386	+#define CLK_IPU_CONN_ISP 3
	387	+#define CLK_IPU_CONN_CAM_ADL 4
	388	+#define CLK_IPU_CONN_IMG_ADL 5
	389	+#define CLK_IPU_CONN_DAP_RX 6
	390	+#define CLK_IPU_CONN_APB2AXI 7
	391	+#define CLK_IPU_CONN_APB2AHB 8
	392	+#define CLK_IPU_CONN_IPU_CAB1TO2 9
	393	+#define CLK_IPU_CONN_IPU1_CAB1TO2 10
	394	+#define CLK_IPU_CONN_IPU2_CAB1TO2 11
	395	+#define CLK_IPU_CONN_CAB3TO3 12
	396	+#define CLK_IPU_CONN_CAB2TO1 13
	397	+#define CLK_IPU_CONN_CAB3TO1_SLICE 14
	398	+#define CLK_IPU_CONN_NR_CLK 15
	399	+
	400	+/* IPU_ADL */
	401	+#define CLK_IPU_ADL_CABGEN 0
	402	+#define CLK_IPU_ADL_NR_CLK 1
	403	+
	404	+/* IPU_CORE0 */
	405	+#define CLK_IPU_CORE0_JTAG 0
	406	+#define CLK_IPU_CORE0_AXI 1
	407	+#define CLK_IPU_CORE0_IPU 2
	408	+#define CLK_IPU_CORE0_NR_CLK 3
	409	+
	410	+/* IPU_CORE1 */
	411	+#define CLK_IPU_CORE1_JTAG 0
	412	+#define CLK_IPU_CORE1_AXI 1
	413	+#define CLK_IPU_CORE1_IPU 2
	414	+#define CLK_IPU_CORE1_NR_CLK 3
	415	+
	416	+/* MCUCFG */
	417	+#define CLK_MCU_MP0_SEL 0
	418	+#define CLK_MCU_MP2_SEL 1
	419	+#define CLK_MCU_BUS_SEL 2
	420	+#define CLK_MCU_NR_CLK 3
	421	+
	422	+#endif /* _DT_BINDINGS_CLK_MT8183_H */

include/dt-bindings/clock/mt8516-clk.h+211−0

@@ -0,0 +1,211 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2019 MediaTek Inc.
	4	+ * Copyright (c) 2019 BayLibre, SAS.
	5	+ * Author: James Liao <jamesjj.liao@mediatek.com>
	6	+ */
	7	+
	8	+#ifndef _DT_BINDINGS_CLK_MT8516_H
	9	+#define _DT_BINDINGS_CLK_MT8516_H
	10	+
	11	+/* APMIXEDSYS */
	12	+
	13	+#define CLK_APMIXED_ARMPLL 0
	14	+#define CLK_APMIXED_MAINPLL 1
	15	+#define CLK_APMIXED_UNIVPLL 2
	16	+#define CLK_APMIXED_MMPLL 3
	17	+#define CLK_APMIXED_APLL1 4
	18	+#define CLK_APMIXED_APLL2 5
	19	+#define CLK_APMIXED_NR_CLK 6
	20	+
	21	+/* INFRACFG */
	22	+
	23	+#define CLK_IFR_MUX1_SEL 0
	24	+#define CLK_IFR_ETH_25M_SEL 1
	25	+#define CLK_IFR_I2C0_SEL 2
	26	+#define CLK_IFR_I2C1_SEL 3
	27	+#define CLK_IFR_I2C2_SEL 4
	28	+#define CLK_IFR_NR_CLK 5
	29	+
	30	+/* TOPCKGEN */
	31	+
	32	+#define CLK_TOP_CLK_NULL 0
	33	+#define CLK_TOP_I2S_INFRA_BCK 1
	34	+#define CLK_TOP_MEMPLL 2
	35	+#define CLK_TOP_DMPLL 3
	36	+#define CLK_TOP_MAINPLL_D2 4
	37	+#define CLK_TOP_MAINPLL_D4 5
	38	+#define CLK_TOP_MAINPLL_D8 6
	39	+#define CLK_TOP_MAINPLL_D16 7
	40	+#define CLK_TOP_MAINPLL_D11 8
	41	+#define CLK_TOP_MAINPLL_D22 9
	42	+#define CLK_TOP_MAINPLL_D3 10
	43	+#define CLK_TOP_MAINPLL_D6 11
	44	+#define CLK_TOP_MAINPLL_D12 12
	45	+#define CLK_TOP_MAINPLL_D5 13
	46	+#define CLK_TOP_MAINPLL_D10 14
	47	+#define CLK_TOP_MAINPLL_D20 15
	48	+#define CLK_TOP_MAINPLL_D40 16
	49	+#define CLK_TOP_MAINPLL_D7 17
	50	+#define CLK_TOP_MAINPLL_D14 18
	51	+#define CLK_TOP_UNIVPLL_D2 19
	52	+#define CLK_TOP_UNIVPLL_D4 20
	53	+#define CLK_TOP_UNIVPLL_D8 21
	54	+#define CLK_TOP_UNIVPLL_D16 22
	55	+#define CLK_TOP_UNIVPLL_D3 23
	56	+#define CLK_TOP_UNIVPLL_D6 24
	57	+#define CLK_TOP_UNIVPLL_D12 25
	58	+#define CLK_TOP_UNIVPLL_D24 26
	59	+#define CLK_TOP_UNIVPLL_D5 27
	60	+#define CLK_TOP_UNIVPLL_D20 28
	61	+#define CLK_TOP_MMPLL380M 29
	62	+#define CLK_TOP_MMPLL_D2 30
	63	+#define CLK_TOP_MMPLL_200M 31
	64	+#define CLK_TOP_USB_PHY48M 32
	65	+#define CLK_TOP_APLL1 33
	66	+#define CLK_TOP_APLL1_D2 34
	67	+#define CLK_TOP_APLL1_D4 35
	68	+#define CLK_TOP_APLL1_D8 36
	69	+#define CLK_TOP_APLL2 37
	70	+#define CLK_TOP_APLL2_D2 38
	71	+#define CLK_TOP_APLL2_D4 39
	72	+#define CLK_TOP_APLL2_D8 40
	73	+#define CLK_TOP_CLK26M 41
	74	+#define CLK_TOP_CLK26M_D2 42
	75	+#define CLK_TOP_AHB_INFRA_D2 43
	76	+#define CLK_TOP_NFI1X 44
	77	+#define CLK_TOP_ETH_D2 45
	78	+#define CLK_TOP_THEM 46
	79	+#define CLK_TOP_APDMA 47
	80	+#define CLK_TOP_I2C0 48
	81	+#define CLK_TOP_I2C1 49
	82	+#define CLK_TOP_AUXADC1 50
	83	+#define CLK_TOP_NFI 51
	84	+#define CLK_TOP_NFIECC 52
	85	+#define CLK_TOP_DEBUGSYS 53
	86	+#define CLK_TOP_PWM 54
	87	+#define CLK_TOP_UART0 55
	88	+#define CLK_TOP_UART1 56
	89	+#define CLK_TOP_BTIF 57
	90	+#define CLK_TOP_USB 58
	91	+#define CLK_TOP_FLASHIF_26M 59
	92	+#define CLK_TOP_AUXADC2 60
	93	+#define CLK_TOP_I2C2 61
	94	+#define CLK_TOP_MSDC0 62
	95	+#define CLK_TOP_MSDC1 63
	96	+#define CLK_TOP_NFI2X 64
	97	+#define CLK_TOP_PMICWRAP_AP 65
	98	+#define CLK_TOP_SEJ 66
	99	+#define CLK_TOP_MEMSLP_DLYER 67
	100	+#define CLK_TOP_SPI 68
	101	+#define CLK_TOP_APXGPT 69
	102	+#define CLK_TOP_AUDIO 70
	103	+#define CLK_TOP_PMICWRAP_MD 71
	104	+#define CLK_TOP_PMICWRAP_CONN 72
	105	+#define CLK_TOP_PMICWRAP_26M 73
	106	+#define CLK_TOP_AUX_ADC 74
	107	+#define CLK_TOP_AUX_TP 75
	108	+#define CLK_TOP_MSDC2 76
	109	+#define CLK_TOP_RBIST 77
	110	+#define CLK_TOP_NFI_BUS 78
	111	+#define CLK_TOP_GCE 79
	112	+#define CLK_TOP_TRNG 80
	113	+#define CLK_TOP_SEJ_13M 81
	114	+#define CLK_TOP_AES 82
	115	+#define CLK_TOP_PWM_B 83
	116	+#define CLK_TOP_PWM1_FB 84
	117	+#define CLK_TOP_PWM2_FB 85
	118	+#define CLK_TOP_PWM3_FB 86
	119	+#define CLK_TOP_PWM4_FB 87
	120	+#define CLK_TOP_PWM5_FB 88
	121	+#define CLK_TOP_USB_1P 89
	122	+#define CLK_TOP_FLASHIF_FREERUN 90
	123	+#define CLK_TOP_66M_ETH 91
	124	+#define CLK_TOP_133M_ETH 92
	125	+#define CLK_TOP_FETH_25M 93
	126	+#define CLK_TOP_FETH_50M 94
	127	+#define CLK_TOP_FLASHIF_AXI 95
	128	+#define CLK_TOP_USBIF 96
	129	+#define CLK_TOP_UART2 97
	130	+#define CLK_TOP_BSI 98
	131	+#define CLK_TOP_RG_SPINOR 99
	132	+#define CLK_TOP_RG_MSDC2 100
	133	+#define CLK_TOP_RG_ETH 101
	134	+#define CLK_TOP_RG_AUD1 102
	135	+#define CLK_TOP_RG_AUD2 103
	136	+#define CLK_TOP_RG_AUD_ENGEN1 104
	137	+#define CLK_TOP_RG_AUD_ENGEN2 105
	138	+#define CLK_TOP_RG_I2C 106
	139	+#define CLK_TOP_RG_PWM_INFRA 107
	140	+#define CLK_TOP_RG_AUD_SPDIF_IN 108
	141	+#define CLK_TOP_RG_UART2 109
	142	+#define CLK_TOP_RG_BSI 110
	143	+#define CLK_TOP_RG_DBG_ATCLK 111
	144	+#define CLK_TOP_RG_NFIECC 112
	145	+#define CLK_TOP_RG_APLL1_D2_EN 113
	146	+#define CLK_TOP_RG_APLL1_D4_EN 114
	147	+#define CLK_TOP_RG_APLL1_D8_EN 115
	148	+#define CLK_TOP_RG_APLL2_D2_EN 116
	149	+#define CLK_TOP_RG_APLL2_D4_EN 117
	150	+#define CLK_TOP_RG_APLL2_D8_EN 118
	151	+#define CLK_TOP_APLL12_DIV0 119
	152	+#define CLK_TOP_APLL12_DIV1 120
	153	+#define CLK_TOP_APLL12_DIV2 121
	154	+#define CLK_TOP_APLL12_DIV3 122
	155	+#define CLK_TOP_APLL12_DIV4 123
	156	+#define CLK_TOP_APLL12_DIV4B 124
	157	+#define CLK_TOP_APLL12_DIV5 125
	158	+#define CLK_TOP_APLL12_DIV5B 126
	159	+#define CLK_TOP_APLL12_DIV6 127
	160	+#define CLK_TOP_UART0_SEL 128
	161	+#define CLK_TOP_EMI_DDRPHY_SEL 129
	162	+#define CLK_TOP_AHB_INFRA_SEL 130
	163	+#define CLK_TOP_MSDC0_SEL 131
	164	+#define CLK_TOP_UART1_SEL 132
	165	+#define CLK_TOP_MSDC1_SEL 133
	166	+#define CLK_TOP_PMICSPI_SEL 134
	167	+#define CLK_TOP_QAXI_AUD26M_SEL 135
	168	+#define CLK_TOP_AUD_INTBUS_SEL 136
	169	+#define CLK_TOP_NFI2X_PAD_SEL 137
	170	+#define CLK_TOP_NFI1X_PAD_SEL 138
	171	+#define CLK_TOP_DDRPHYCFG_SEL 139
	172	+#define CLK_TOP_USB_78M_SEL 140
	173	+#define CLK_TOP_SPINOR_SEL 141
	174	+#define CLK_TOP_MSDC2_SEL 142
	175	+#define CLK_TOP_ETH_SEL 143
	176	+#define CLK_TOP_AUD1_SEL 144
	177	+#define CLK_TOP_AUD2_SEL 145
	178	+#define CLK_TOP_AUD_ENGEN1_SEL 146
	179	+#define CLK_TOP_AUD_ENGEN2_SEL 147
	180	+#define CLK_TOP_I2C_SEL 148
	181	+#define CLK_TOP_AUD_I2S0_M_SEL 149
	182	+#define CLK_TOP_AUD_I2S1_M_SEL 150
	183	+#define CLK_TOP_AUD_I2S2_M_SEL 151
	184	+#define CLK_TOP_AUD_I2S3_M_SEL 152
	185	+#define CLK_TOP_AUD_I2S4_M_SEL 153
	186	+#define CLK_TOP_AUD_I2S5_M_SEL 154
	187	+#define CLK_TOP_AUD_SPDIF_B_SEL 155
	188	+#define CLK_TOP_PWM_SEL 156
	189	+#define CLK_TOP_SPI_SEL 157
	190	+#define CLK_TOP_AUD_SPDIFIN_SEL 158
	191	+#define CLK_TOP_UART2_SEL 159
	192	+#define CLK_TOP_BSI_SEL 160
	193	+#define CLK_TOP_DBG_ATCLK_SEL 161
	194	+#define CLK_TOP_CSW_NFIECC_SEL 162
	195	+#define CLK_TOP_NFIECC_SEL 163
	196	+#define CLK_TOP_APLL12_CK_DIV0 164
	197	+#define CLK_TOP_APLL12_CK_DIV1 165
	198	+#define CLK_TOP_APLL12_CK_DIV2 166
	199	+#define CLK_TOP_APLL12_CK_DIV3 167
	200	+#define CLK_TOP_APLL12_CK_DIV4 168
	201	+#define CLK_TOP_APLL12_CK_DIV4B 169
	202	+#define CLK_TOP_APLL12_CK_DIV5 170
	203	+#define CLK_TOP_APLL12_CK_DIV5B 171
	204	+#define CLK_TOP_APLL12_CK_DIV6 172
	205	+#define CLK_TOP_USB_78M 173
	206	+#define CLK_TOP_MSDC0_INFRA 174
	207	+#define CLK_TOP_MSDC1_INFRA 175
	208	+#define CLK_TOP_MSDC2_INFRA 176
	209	+#define CLK_TOP_NR_CLK 177
	210	+
	211	+#endif /* _DT_BINDINGS_CLK_MT8516_H */

include/dt-bindings/clock/qcom,gcc-qcs404.h+5−0

@@ -146,6 +146,10 @@ · 145 unmodified lines
146	146	#define GCC_MDP_TBU_CLK 138
147	147	#define GCC_QDSS_DAP_CLK 139
148	148	#define GCC_DCC_XO_CLK 140
	149	+#define GCC_CDSP_CFG_AHB_CLK 143
	150	+#define GCC_BIMC_CDSP_CLK 144
	151	+#define GCC_CDSP_TBU_CLK 145
	152	+#define GCC_CDSP_BIMC_CLK_SRC 146
149	153
150	154	#define GCC_GENI_IR_BCR 0
151	155	#define GCC_USB_HS_BCR 1
@@ -161,5 +165,6 @@ · 9 unmodified lines
161	165	#define GCC_PCIE_0_LINK_DOWN_BCR 11
162	166	#define GCC_PCIEPHY_0_PHY_BCR 12
163	167	#define GCC_EMAC_BCR 13
	168	+#define GCC_CDSP_RESTART 14
164	169
165	170	#endif

include/dt-bindings/clock/qcom,turingcc-qcs404.h+15−0

@@ -0,0 +1,15 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2019, Linaro Ltd
	4	+ */
	5	+
	6	+#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H
	7	+#define _DT_BINDINGS_CLK_TURING_QCS404_H
	8	+
	9	+#define TURING_Q6SS_Q6_AXIM_CLK 0
	10	+#define TURING_Q6SS_AHBM_AON_CLK 1
	11	+#define TURING_WRAPPER_AON_CLK 2
	12	+#define TURING_Q6SS_AHBS_AON_CLK 3
	13	+#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4
	14	+
	15	+#endif

include/linux/math64.h+13−0

@@ -284,4 +284,17 @@ static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor) · 283 unmodified lines
284	284	#define DIV64_U64_ROUND_UP(ll, d) \
285	285	({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); })
286	286
	287	+/**
	288	+ * DIV64_U64_ROUND_CLOSEST - unsigned 64bit divide with 64bit divisor rounded to nearest integer
	289	+ * @dividend: unsigned 64bit dividend
	290	+ * @divisor: unsigned 64bit divisor
	291	+ *
	292	+ * Divide unsigned 64bit dividend by unsigned 64bit divisor
	293	+ * and round to closest integer.
	294	+ *
	295	+ * Return: dividend / divisor rounded to nearest integer
	296	+ */
	297	+#define DIV64_U64_ROUND_CLOSEST(dividend, divisor) \
	298	+ ({ u64 _tmp = (divisor); div64_u64((dividend) + _tmp / 2, _tmp); })
	299	+
287	300	#endif /* _LINUX_MATH64_H */

Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next

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