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Merge tag 'x86_cleanups_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cleanups from Borislav Petkov: - Simplify inline asm flag output operands now that the minimum compiler version supports the =@ccCOND syntax - Remove a bunch of AS_* Kconfig symbols which detect assembler support for various instruction mnemonics now that the minimum assembler version supports them all - The usual cleanups all over the place * tag 'x86_cleanups_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/asm: Remove code depending on __GCC_ASM_FLAG_OUTPUTS__ x86/sgx: Use ENCLS mnemonic in <kernel/cpu/sgx/encls.h> x86/mtrr: Remove license boilerplate text with bad FSF address x86/asm: Use RDPKRU and WRPKRU mnemonics in <asm/special_insns.h> x86/idle: Use MONITORX and MWAITX mnemonics in <asm/mwait.h> x86/entry/fred: Push __KERNEL_CS directly x86/kconfig: Remove CONFIG_AS_AVX512 crypto: x86 - Remove CONFIG_AS_VPCLMULQDQ crypto: X86 - Remove CONFIG_AS_VAES crypto: x86 - Remove CONFIG_AS_GFNI x86/kconfig: Drop unused and needless config X86_64_SMP

Linus Torvalds committed 1 year ago

Commit 2f0a7502 parents 6bb71f0 c6c973d34 files · +55 −239Browse files

Unified · Split

34 files
  1. arch/x86/Kconfig +0 −4
  2. arch/x86/Kconfig.assembler +0 −20
  3. arch/x86/boot/bitops.h +1 −1
  4. arch/x86/boot/boot.h +4 −4
  5. arch/x86/boot/string.c +2 −2
  6. arch/x86/crypto/Kconfig +1 −1
  7. arch/x86/crypto/Makefile +2 −4
  8. arch/x86/crypto/aes-ctr-avx-x86_64.S +0 −2
  9. arch/x86/crypto/aes-xts-avx-x86_64.S +0 −2
  10. arch/x86/crypto/aesni-intel_glue.c +3 −19
  11. arch/x86/crypto/aria-aesni-avx-asm_64.S +0 −10
  12. arch/x86/crypto/aria-aesni-avx2-asm_64.S +1 −9
  13. arch/x86/crypto/aria_aesni_avx2_glue.c +1 −3
  14. arch/x86/crypto/aria_aesni_avx_glue.c +1 −3
  15. arch/x86/entry/entry_64_fred.S +1 −2
  16. arch/x86/include/asm/archrandom.h +2 −4
  17. arch/x86/include/asm/asm.h +0 −12
  18. arch/x86/include/asm/bitops.h +6 −12
  19. arch/x86/include/asm/cmpxchg.h +4 −8
  20. arch/x86/include/asm/cmpxchg_32.h +2 −4
  21. arch/x86/include/asm/cmpxchg_64.h +1 −2
  22. arch/x86/include/asm/mtrr.h +1 −14
  23. arch/x86/include/asm/mwait.h +2 −6
  24. arch/x86/include/asm/percpu.h +4 −8
  25. arch/x86/include/asm/rmwcc.h +2 −24
  26. arch/x86/include/asm/sev.h +1 −2
  27. arch/x86/include/asm/signal.h +1 −2
  28. arch/x86/include/asm/special_insns.h +3 −7
  29. arch/x86/include/asm/uaccess.h +3 −4
  30. arch/x86/kernel/cpu/mtrr/cleanup.c +1 −14
  31. arch/x86/kernel/cpu/mtrr/mtrr.c +1 −14
  32. arch/x86/kernel/cpu/sgx/encls.h +3 −3
  33. tools/arch/x86/include/asm/asm.h +0 −12
  34. tools/perf/bench/find-bit-bench.c +1 −1
arch/x86/Kconfig+0−4
@@ -412,10 +412,6 @@ config HAVE_INTEL_TXT · 411 unmodified lines
412 def_bool y412 def_bool y
413 depends on INTEL_IOMMU && ACPI413 depends on INTEL_IOMMU && ACPI
414 414
415config X86_64_SMP
416 def_bool y
417 depends on X86_64 && SMP
418
419config ARCH_SUPPORTS_UPROBES415config ARCH_SUPPORTS_UPROBES
420 def_bool y416 def_bool y
421 417
arch/x86/Kconfig.assembler+0−20
@@ -1,26 +1,6 @@
1# SPDX-License-Identifier: GPL-2.01# SPDX-License-Identifier: GPL-2.0
2# Copyright (C) 2020 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.2# Copyright (C) 2020 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
3 3
4config AS_AVX512
5 def_bool $(as-instr,vpmovm2b %k1$(comma)%zmm5)
6 help
7 Supported by binutils >= 2.25 and LLVM integrated assembler
8
9config AS_GFNI
10 def_bool $(as-instr,vgf2p8mulb %xmm0$(comma)%xmm1$(comma)%xmm2)
11 help
12 Supported by binutils >= 2.30 and LLVM integrated assembler
13
14config AS_VAES
15 def_bool $(as-instr,vaesenc %ymm0$(comma)%ymm1$(comma)%ymm2)
16 help
17 Supported by binutils >= 2.30 and LLVM integrated assembler
18
19config AS_VPCLMULQDQ
20 def_bool $(as-instr,vpclmulqdq \$0x10$(comma)%ymm0$(comma)%ymm1$(comma)%ymm2)
21 help
22 Supported by binutils >= 2.30 and LLVM integrated assembler
23
24config AS_WRUSS4config AS_WRUSS
25 def_bool $(as-instr64,wrussq %rax$(comma)(%rbx))5 def_bool $(as-instr64,wrussq %rax$(comma)(%rbx))
26 help6 help
arch/x86/boot/bitops.h+1−1
@@ -27,7 +27,7 @@ static inline bool variable_test_bit(int nr, const void *addr) · 26 unmodified lines
27 bool v;27 bool v;
28 const u32 *p = addr;28 const u32 *p = addr;
29 29
30 asm("btl %2,%1" CC_SET(c) : CC_OUT(c) (v) : "m" (*p), "Ir" (nr));30 asm("btl %2,%1" : "=@ccc" (v) : "m" (*p), "Ir" (nr));
31 return v;31 return v;
32}32}
33 33
arch/x86/boot/boot.h+4−4
@@ -155,15 +155,15 @@ static inline void wrgs32(u32 v, addr_t addr) · 154 unmodified lines
155static inline bool memcmp_fs(const void *s1, addr_t s2, size_t len)155static inline bool memcmp_fs(const void *s1, addr_t s2, size_t len)
156{156{
157 bool diff;157 bool diff;
158 asm volatile("fs repe cmpsb" CC_SET(nz)158 asm volatile("fs repe cmpsb"
159 : CC_OUT(nz) (diff), "+D" (s1), "+S" (s2), "+c" (len));159 : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len));
160 return diff;160 return diff;
161}161}
162static inline bool memcmp_gs(const void *s1, addr_t s2, size_t len)162static inline bool memcmp_gs(const void *s1, addr_t s2, size_t len)
163{163{
164 bool diff;164 bool diff;
165 asm volatile("gs repe cmpsb" CC_SET(nz)165 asm volatile("gs repe cmpsb"
166 : CC_OUT(nz) (diff), "+D" (s1), "+S" (s2), "+c" (len));166 : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len));
167 return diff;167 return diff;
168}168}
169 169
arch/x86/boot/string.c+2−2
@@ -32,8 +32,8 @@ · 31 unmodified lines
32int memcmp(const void *s1, const void *s2, size_t len)32int memcmp(const void *s1, const void *s2, size_t len)
33{33{
34 bool diff;34 bool diff;
35 asm("repe cmpsb" CC_SET(nz)35 asm("repe cmpsb"
36 : CC_OUT(nz) (diff), "+D" (s1), "+S" (s2), "+c" (len));36 : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len));
37 return diff;37 return diff;
38}38}
39 39
arch/x86/crypto/Kconfig+1−1
@@ -306,7 +306,7 @@ config CRYPTO_ARIA_AESNI_AVX2_X86_64 · 305 unmodified lines
306 306
307config CRYPTO_ARIA_GFNI_AVX512_X86_64307config CRYPTO_ARIA_GFNI_AVX512_X86_64
308 tristate "Ciphers: ARIA with modes: ECB, CTR (AVX512/GFNI)"308 tristate "Ciphers: ARIA with modes: ECB, CTR (AVX512/GFNI)"
309 depends on 64BIT && AS_GFNI309 depends on 64BIT
310 select CRYPTO_SKCIPHER310 select CRYPTO_SKCIPHER
311 select CRYPTO_ALGAPI311 select CRYPTO_ALGAPI
312 select CRYPTO_ARIA312 select CRYPTO_ARIA
arch/x86/crypto/Makefile+2−4
@@ -46,10 +46,8 @@ obj-$(CONFIG_CRYPTO_AES_NI_INTEL) += aesni-intel.o · 45 unmodified lines
46aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o46aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o
47aesni-intel-$(CONFIG_64BIT) += aes-ctr-avx-x86_64.o \47aesni-intel-$(CONFIG_64BIT) += aes-ctr-avx-x86_64.o \
48 aes-gcm-aesni-x86_64.o \48 aes-gcm-aesni-x86_64.o \
49 aes-xts-avx-x86_64.o49 aes-xts-avx-x86_64.o \
50ifeq ($(CONFIG_AS_VAES)$(CONFIG_AS_VPCLMULQDQ),yy)50 aes-gcm-avx10-x86_64.o
51aesni-intel-$(CONFIG_64BIT) += aes-gcm-avx10-x86_64.o
52endif
53 51
54obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o52obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
55ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o53ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o
arch/x86/crypto/aes-ctr-avx-x86_64.S+0−2
@@ -552,7 +552,6 @@ SYM_TYPED_FUNC_START(aes_xctr_crypt_aesni_avx) · 551 unmodified lines
552 _aes_ctr_crypt 1552 _aes_ctr_crypt 1
553SYM_FUNC_END(aes_xctr_crypt_aesni_avx)553SYM_FUNC_END(aes_xctr_crypt_aesni_avx)
554 554
555#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
556.set VL, 32555.set VL, 32
557.set USE_AVX512, 0556.set USE_AVX512, 0
558SYM_TYPED_FUNC_START(aes_ctr64_crypt_vaes_avx2)557SYM_TYPED_FUNC_START(aes_ctr64_crypt_vaes_avx2)
@@ -570,4 +569,3 @@ SYM_FUNC_END(aes_ctr64_crypt_vaes_avx512) · 11 unmodified lines
570SYM_TYPED_FUNC_START(aes_xctr_crypt_vaes_avx512)569SYM_TYPED_FUNC_START(aes_xctr_crypt_vaes_avx512)
571 _aes_ctr_crypt 1570 _aes_ctr_crypt 1
572SYM_FUNC_END(aes_xctr_crypt_vaes_avx512)571SYM_FUNC_END(aes_xctr_crypt_vaes_avx512)
573#endif // CONFIG_AS_VAES && CONFIG_AS_VPCLMULQDQ
arch/x86/crypto/aes-xts-avx-x86_64.S+0−2
@@ -886,7 +886,6 @@ SYM_TYPED_FUNC_START(aes_xts_decrypt_aesni_avx) · 885 unmodified lines
886 _aes_xts_crypt 0886 _aes_xts_crypt 0
887SYM_FUNC_END(aes_xts_decrypt_aesni_avx)887SYM_FUNC_END(aes_xts_decrypt_aesni_avx)
888 888
889#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
890.set VL, 32889.set VL, 32
891.set USE_AVX512, 0890.set USE_AVX512, 0
892SYM_TYPED_FUNC_START(aes_xts_encrypt_vaes_avx2)891SYM_TYPED_FUNC_START(aes_xts_encrypt_vaes_avx2)
@@ -904,4 +903,3 @@ SYM_FUNC_END(aes_xts_encrypt_vaes_avx512) · 11 unmodified lines
904SYM_TYPED_FUNC_START(aes_xts_decrypt_vaes_avx512)903SYM_TYPED_FUNC_START(aes_xts_decrypt_vaes_avx512)
905 _aes_xts_crypt 0904 _aes_xts_crypt 0
906SYM_FUNC_END(aes_xts_decrypt_vaes_avx512)905SYM_FUNC_END(aes_xts_decrypt_vaes_avx512)
907#endif /* CONFIG_AS_VAES && CONFIG_AS_VPCLMULQDQ */
arch/x86/crypto/aesni-intel_glue.c+3−19
@@ -828,10 +828,8 @@ static struct skcipher_alg skcipher_algs_##suffix[] = {{ \ · 827 unmodified lines
828}}828}}
829 829
830DEFINE_AVX_SKCIPHER_ALGS(aesni_avx, "aesni-avx", 500);830DEFINE_AVX_SKCIPHER_ALGS(aesni_avx, "aesni-avx", 500);
831#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
832DEFINE_AVX_SKCIPHER_ALGS(vaes_avx2, "vaes-avx2", 600);831DEFINE_AVX_SKCIPHER_ALGS(vaes_avx2, "vaes-avx2", 600);
833DEFINE_AVX_SKCIPHER_ALGS(vaes_avx512, "vaes-avx512", 800);832DEFINE_AVX_SKCIPHER_ALGS(vaes_avx512, "vaes-avx512", 800);
834#endif
835 833
836/* The common part of the x86_64 AES-GCM key struct */834/* The common part of the x86_64 AES-GCM key struct */
837struct aes_gcm_key {835struct aes_gcm_key {
@@ -912,17 +910,8 @@ struct aes_gcm_key_avx10 { · 74 unmodified lines
912#define FLAG_RFC4106 BIT(0)910#define FLAG_RFC4106 BIT(0)
913#define FLAG_ENC BIT(1)911#define FLAG_ENC BIT(1)
914#define FLAG_AVX BIT(2)912#define FLAG_AVX BIT(2)
915#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)913#define FLAG_AVX10_256 BIT(3)
916# define FLAG_AVX10_256 BIT(3)914#define FLAG_AVX10_512 BIT(4)
917# define FLAG_AVX10_512 BIT(4)
918#else
919 /*
920 * This should cause all calls to the AVX10 assembly functions to be
921 * optimized out, avoiding the need to ifdef each call individually.
922 */
923# define FLAG_AVX10_256 0
924# define FLAG_AVX10_512 0
925#endif
926 915
927static inline struct aes_gcm_key *916static inline struct aes_gcm_key *
928aes_gcm_key_get(struct crypto_aead *tfm, int flags)917aes_gcm_key_get(struct crypto_aead *tfm, int flags)
@@ -1519,7 +1508,6 @@ DEFINE_GCM_ALGS(aesni_avx, FLAG_AVX, · 590 unmodified lines
1519 "generic-gcm-aesni-avx", "rfc4106-gcm-aesni-avx",1508 "generic-gcm-aesni-avx", "rfc4106-gcm-aesni-avx",
1520 AES_GCM_KEY_AESNI_SIZE, 500);1509 AES_GCM_KEY_AESNI_SIZE, 500);
1521 1510
1522#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
1523/* aes_gcm_algs_vaes_avx10_256 */1511/* aes_gcm_algs_vaes_avx10_256 */
1524DEFINE_GCM_ALGS(vaes_avx10_256, FLAG_AVX10_256,1512DEFINE_GCM_ALGS(vaes_avx10_256, FLAG_AVX10_256,
1525 "generic-gcm-vaes-avx10_256", "rfc4106-gcm-vaes-avx10_256",1513 "generic-gcm-vaes-avx10_256", "rfc4106-gcm-vaes-avx10_256",
@@ -1529,7 +1517,6 @@ DEFINE_GCM_ALGS(vaes_avx10_256, FLAG_AVX10_256, · 3 unmodified lines
1529DEFINE_GCM_ALGS(vaes_avx10_512, FLAG_AVX10_512,1517DEFINE_GCM_ALGS(vaes_avx10_512, FLAG_AVX10_512,
1530 "generic-gcm-vaes-avx10_512", "rfc4106-gcm-vaes-avx10_512",1518 "generic-gcm-vaes-avx10_512", "rfc4106-gcm-vaes-avx10_512",
1531 AES_GCM_KEY_AVX10_SIZE, 800);1519 AES_GCM_KEY_AVX10_SIZE, 800);
1532#endif /* CONFIG_AS_VAES && CONFIG_AS_VPCLMULQDQ */
1533 1520
1534static int __init register_avx_algs(void)1521static int __init register_avx_algs(void)
1535{1522{
@@ -1551,7 +1538,6 @@ static int __init register_avx_algs(void) · 15 unmodified lines
1551 * Similarly, the assembler support was added at about the same time.1538 * Similarly, the assembler support was added at about the same time.
1552 * For simplicity, just always check for VAES and VPCLMULQDQ together.1539 * For simplicity, just always check for VAES and VPCLMULQDQ together.
1553 */1540 */
1554#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
1555 if (!boot_cpu_has(X86_FEATURE_AVX2) ||1541 if (!boot_cpu_has(X86_FEATURE_AVX2) ||
1556 !boot_cpu_has(X86_FEATURE_VAES) ||1542 !boot_cpu_has(X86_FEATURE_VAES) ||
1557 !boot_cpu_has(X86_FEATURE_VPCLMULQDQ) ||1543 !boot_cpu_has(X86_FEATURE_VPCLMULQDQ) ||
@@ -1592,7 +1578,7 @@ static int __init register_avx_algs(void) · 34 unmodified lines
1592 ARRAY_SIZE(aes_gcm_algs_vaes_avx10_512));1578 ARRAY_SIZE(aes_gcm_algs_vaes_avx10_512));
1593 if (err)1579 if (err)
1594 return err;1580 return err;
1595#endif /* CONFIG_AS_VAES && CONFIG_AS_VPCLMULQDQ */1581
1596 return 0;1582 return 0;
1597}1583}
1598 1584
@@ -1607,12 +1593,10 @@ static void unregister_avx_algs(void) · 8 unmodified lines
1607{1593{
1608 unregister_skciphers(skcipher_algs_aesni_avx);1594 unregister_skciphers(skcipher_algs_aesni_avx);
1609 unregister_aeads(aes_gcm_algs_aesni_avx);1595 unregister_aeads(aes_gcm_algs_aesni_avx);
1610#if defined(CONFIG_AS_VAES) && defined(CONFIG_AS_VPCLMULQDQ)
1611 unregister_skciphers(skcipher_algs_vaes_avx2);1596 unregister_skciphers(skcipher_algs_vaes_avx2);
1612 unregister_skciphers(skcipher_algs_vaes_avx512);1597 unregister_skciphers(skcipher_algs_vaes_avx512);
1613 unregister_aeads(aes_gcm_algs_vaes_avx10_256);1598 unregister_aeads(aes_gcm_algs_vaes_avx10_256);
1614 unregister_aeads(aes_gcm_algs_vaes_avx10_512);1599 unregister_aeads(aes_gcm_algs_vaes_avx10_512);
1615#endif
1616}1600}
1617#else /* CONFIG_X86_64 */1601#else /* CONFIG_X86_64 */
1618static struct aead_alg aes_gcm_algs_aesni[0];1602static struct aead_alg aes_gcm_algs_aesni[0];
arch/x86/crypto/aria-aesni-avx-asm_64.S+0−10
@@ -295,7 +295,6 @@ · 294 unmodified lines
295 vpshufb t1, t0, t2; \295 vpshufb t1, t0, t2; \
296 vpxor t2, x7, x7;296 vpxor t2, x7, x7;
297 297
298#ifdef CONFIG_AS_GFNI
299#define aria_sbox_8way_gfni(x0, x1, x2, x3, \298#define aria_sbox_8way_gfni(x0, x1, x2, x3, \
300 x4, x5, x6, x7, \299 x4, x5, x6, x7, \
301 t0, t1, t2, t3, \300 t0, t1, t2, t3, \
@@ -318,8 +317,6 @@ · 16 unmodified lines
318 vgf2p8affineinvqb $0, t2, x3, x3; \317 vgf2p8affineinvqb $0, t2, x3, x3; \
319 vgf2p8affineinvqb $0, t2, x7, x7318 vgf2p8affineinvqb $0, t2, x7, x7
320 319
321#endif /* CONFIG_AS_GFNI */
322
323#define aria_sbox_8way(x0, x1, x2, x3, \320#define aria_sbox_8way(x0, x1, x2, x3, \
324 x4, x5, x6, x7, \321 x4, x5, x6, x7, \
325 t0, t1, t2, t3, \322 t0, t1, t2, t3, \
@@ -561,7 +558,6 @@ · 235 unmodified lines
561 y4, y5, y6, y7, \558 y4, y5, y6, y7, \
562 mem_tmp, 8);559 mem_tmp, 8);
563 560
564#ifdef CONFIG_AS_GFNI
565#define aria_fe_gfni(x0, x1, x2, x3, \561#define aria_fe_gfni(x0, x1, x2, x3, \
566 x4, x5, x6, x7, \562 x4, x5, x6, x7, \
567 y0, y1, y2, y3, \563 y0, y1, y2, y3, \
@@ -719,8 +715,6 @@ · 151 unmodified lines
719 y4, y5, y6, y7, \715 y4, y5, y6, y7, \
720 mem_tmp, 8);716 mem_tmp, 8);
721 717
722#endif /* CONFIG_AS_GFNI */
723
724/* NB: section is mergeable, all elements must be aligned 16-byte blocks */718/* NB: section is mergeable, all elements must be aligned 16-byte blocks */
725.section .rodata.cst16, "aM", @progbits, 16719.section .rodata.cst16, "aM", @progbits, 16
726.align 16720.align 16
@@ -772,7 +766,6 @@ · 45 unmodified lines
772.Ltf_hi__x2__and__fwd_aff:766.Ltf_hi__x2__and__fwd_aff:
773 .octa 0x3F893781E95FE1576CDA64D2BA0CB204767 .octa 0x3F893781E95FE1576CDA64D2BA0CB204
774 768
775#ifdef CONFIG_AS_GFNI
776/* AES affine: */769/* AES affine: */
777#define tf_aff_const BV8(1, 1, 0, 0, 0, 1, 1, 0)770#define tf_aff_const BV8(1, 1, 0, 0, 0, 1, 1, 0)
778.Ltf_aff_bitmatrix:771.Ltf_aff_bitmatrix:
@@ -871,7 +864,6 @@ · 92 unmodified lines
871 BV8(0, 0, 0, 0, 0, 1, 0, 0),864 BV8(0, 0, 0, 0, 0, 1, 0, 0),
872 BV8(0, 0, 0, 0, 0, 0, 1, 0),865 BV8(0, 0, 0, 0, 0, 0, 1, 0),
873 BV8(0, 0, 0, 0, 0, 0, 0, 1))866 BV8(0, 0, 0, 0, 0, 0, 0, 1))
874#endif /* CONFIG_AS_GFNI */
875 867
876/* 4-bit mask */868/* 4-bit mask */
877.section .rodata.cst4.L0f0f0f0f, "aM", @progbits, 4869.section .rodata.cst4.L0f0f0f0f, "aM", @progbits, 4
@@ -1140,7 +1132,6 @@ SYM_TYPED_FUNC_START(aria_aesni_avx_ctr_crypt_16way) · 262 unmodified lines
1140 RET;1132 RET;
1141SYM_FUNC_END(aria_aesni_avx_ctr_crypt_16way)1133SYM_FUNC_END(aria_aesni_avx_ctr_crypt_16way)
1142 1134
1143#ifdef CONFIG_AS_GFNI
1144SYM_FUNC_START_LOCAL(__aria_aesni_avx_gfni_crypt_16way)1135SYM_FUNC_START_LOCAL(__aria_aesni_avx_gfni_crypt_16way)
1145 /* input:1136 /* input:
1146 * %r9: rk1137 * %r9: rk
@@ -1359,4 +1350,3 @@ SYM_TYPED_FUNC_START(aria_aesni_avx_gfni_ctr_crypt_16way) · 212 unmodified lines
1359 FRAME_END1350 FRAME_END
1360 RET;1351 RET;
1361SYM_FUNC_END(aria_aesni_avx_gfni_ctr_crypt_16way)1352SYM_FUNC_END(aria_aesni_avx_gfni_ctr_crypt_16way)
1362#endif /* CONFIG_AS_GFNI */
arch/x86/crypto/aria-aesni-avx2-asm_64.S+1−9
@@ -302,7 +302,6 @@ · 301 unmodified lines
302 vpbroadcastb ((round * 16) + idx + 4)(rk), t0; \302 vpbroadcastb ((round * 16) + idx + 4)(rk), t0; \
303 vpxor t0, x7, x7;303 vpxor t0, x7, x7;
304 304
305#ifdef CONFIG_AS_GFNI
306#define aria_sbox_8way_gfni(x0, x1, x2, x3, \305#define aria_sbox_8way_gfni(x0, x1, x2, x3, \
307 x4, x5, x6, x7, \306 x4, x5, x6, x7, \
308 t0, t1, t2, t3, \307 t0, t1, t2, t3, \
@@ -325,7 +324,6 @@ · 16 unmodified lines
325 vgf2p8affineinvqb $0, t2, x3, x3; \324 vgf2p8affineinvqb $0, t2, x3, x3; \
326 vgf2p8affineinvqb $0, t2, x7, x7325 vgf2p8affineinvqb $0, t2, x7, x7
327 326
328#endif /* CONFIG_AS_GFNI */
329#define aria_sbox_8way(x0, x1, x2, x3, \327#define aria_sbox_8way(x0, x1, x2, x3, \
330 x4, x5, x6, x7, \328 x4, x5, x6, x7, \
331 t0, t1, t2, t3, \329 t0, t1, t2, t3, \
@@ -598,7 +596,7 @@ · 266 unmodified lines
598 aria_load_state_8way(y0, y1, y2, y3, \596 aria_load_state_8way(y0, y1, y2, y3, \
599 y4, y5, y6, y7, \597 y4, y5, y6, y7, \
600 mem_tmp, 8);598 mem_tmp, 8);
601#ifdef CONFIG_AS_GFNI599
602#define aria_fe_gfni(x0, x1, x2, x3, \600#define aria_fe_gfni(x0, x1, x2, x3, \
603 x4, x5, x6, x7, \601 x4, x5, x6, x7, \
604 y0, y1, y2, y3, \602 y0, y1, y2, y3, \
@@ -752,7 +750,6 @@ · 147 unmodified lines
752 aria_load_state_8way(y0, y1, y2, y3, \750 aria_load_state_8way(y0, y1, y2, y3, \
753 y4, y5, y6, y7, \751 y4, y5, y6, y7, \
754 mem_tmp, 8);752 mem_tmp, 8);
755#endif /* CONFIG_AS_GFNI */
756 753
757.section .rodata.cst32.shufb_16x16b, "aM", @progbits, 32754.section .rodata.cst32.shufb_16x16b, "aM", @progbits, 32
758.align 32755.align 32
@@ -806,7 +803,6 @@ · 47 unmodified lines
806.Ltf_hi__x2__and__fwd_aff:803.Ltf_hi__x2__and__fwd_aff:
807 .octa 0x3F893781E95FE1576CDA64D2BA0CB204804 .octa 0x3F893781E95FE1576CDA64D2BA0CB204
808 805
809#ifdef CONFIG_AS_GFNI
810.section .rodata.cst8, "aM", @progbits, 8806.section .rodata.cst8, "aM", @progbits, 8
811.align 8807.align 8
812/* AES affine: */808/* AES affine: */
@@ -868,8 +864,6 @@ · 55 unmodified lines
868 BV8(0, 0, 0, 0, 0, 0, 1, 0),864 BV8(0, 0, 0, 0, 0, 0, 1, 0),
869 BV8(0, 0, 0, 0, 0, 0, 0, 1))865 BV8(0, 0, 0, 0, 0, 0, 0, 1))
870 866
871#endif /* CONFIG_AS_GFNI */
872
873/* 4-bit mask */867/* 4-bit mask */
874.section .rodata.cst4.L0f0f0f0f, "aM", @progbits, 4868.section .rodata.cst4.L0f0f0f0f, "aM", @progbits, 4
875.align 4869.align 4
@@ -1219,7 +1213,6 @@ SYM_TYPED_FUNC_START(aria_aesni_avx2_ctr_crypt_32way) · 343 unmodified lines
1219 RET;1213 RET;
1220SYM_FUNC_END(aria_aesni_avx2_ctr_crypt_32way)1214SYM_FUNC_END(aria_aesni_avx2_ctr_crypt_32way)
1221 1215
1222#ifdef CONFIG_AS_GFNI
1223SYM_FUNC_START_LOCAL(__aria_aesni_avx2_gfni_crypt_32way)1216SYM_FUNC_START_LOCAL(__aria_aesni_avx2_gfni_crypt_32way)
1224 /* input:1217 /* input:
1225 * %r9: rk1218 * %r9: rk
@@ -1438,4 +1431,3 @@ SYM_TYPED_FUNC_START(aria_aesni_avx2_gfni_ctr_crypt_32way) · 212 unmodified lines
1438 FRAME_END1431 FRAME_END
1439 RET;1432 RET;
1440SYM_FUNC_END(aria_aesni_avx2_gfni_ctr_crypt_32way)1433SYM_FUNC_END(aria_aesni_avx2_gfni_ctr_crypt_32way)
1441#endif /* CONFIG_AS_GFNI */
arch/x86/crypto/aria_aesni_avx2_glue.c+1−3
@@ -26,7 +26,6 @@ asmlinkage void aria_aesni_avx2_ctr_crypt_32way(const void *ctx, u8 *dst, · 25 unmodified lines
26 const u8 *src,26 const u8 *src,
27 u8 *keystream, u8 *iv);27 u8 *keystream, u8 *iv);
28EXPORT_SYMBOL_GPL(aria_aesni_avx2_ctr_crypt_32way);28EXPORT_SYMBOL_GPL(aria_aesni_avx2_ctr_crypt_32way);
29#ifdef CONFIG_AS_GFNI
30asmlinkage void aria_aesni_avx2_gfni_encrypt_32way(const void *ctx, u8 *dst,29asmlinkage void aria_aesni_avx2_gfni_encrypt_32way(const void *ctx, u8 *dst,
31 const u8 *src);30 const u8 *src);
32EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_encrypt_32way);31EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_encrypt_32way);
@@ -37,7 +36,6 @@ asmlinkage void aria_aesni_avx2_gfni_ctr_crypt_32way(const void *ctx, u8 *dst, · 4 unmodified lines
37 const u8 *src,36 const u8 *src,
38 u8 *keystream, u8 *iv);37 u8 *keystream, u8 *iv);
39EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_ctr_crypt_32way);38EXPORT_SYMBOL_GPL(aria_aesni_avx2_gfni_ctr_crypt_32way);
40#endif /* CONFIG_AS_GFNI */
41 39
42static struct aria_avx_ops aria_ops;40static struct aria_avx_ops aria_ops;
43 41
@@ -213,7 +211,7 @@ static int __init aria_avx2_init(void) · 169 unmodified lines
213 return -ENODEV;211 return -ENODEV;
214 }212 }
215 213
216 if (boot_cpu_has(X86_FEATURE_GFNI) && IS_ENABLED(CONFIG_AS_GFNI)) {214 if (boot_cpu_has(X86_FEATURE_GFNI)) {
217 aria_ops.aria_encrypt_16way = aria_aesni_avx_gfni_encrypt_16way;215 aria_ops.aria_encrypt_16way = aria_aesni_avx_gfni_encrypt_16way;
218 aria_ops.aria_decrypt_16way = aria_aesni_avx_gfni_decrypt_16way;216 aria_ops.aria_decrypt_16way = aria_aesni_avx_gfni_decrypt_16way;
219 aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_gfni_ctr_crypt_16way;217 aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_gfni_ctr_crypt_16way;
arch/x86/crypto/aria_aesni_avx_glue.c+1−3
@@ -26,7 +26,6 @@ asmlinkage void aria_aesni_avx_ctr_crypt_16way(const void *ctx, u8 *dst, · 25 unmodified lines
26 const u8 *src,26 const u8 *src,
27 u8 *keystream, u8 *iv);27 u8 *keystream, u8 *iv);
28EXPORT_SYMBOL_GPL(aria_aesni_avx_ctr_crypt_16way);28EXPORT_SYMBOL_GPL(aria_aesni_avx_ctr_crypt_16way);
29#ifdef CONFIG_AS_GFNI
30asmlinkage void aria_aesni_avx_gfni_encrypt_16way(const void *ctx, u8 *dst,29asmlinkage void aria_aesni_avx_gfni_encrypt_16way(const void *ctx, u8 *dst,
31 const u8 *src);30 const u8 *src);
32EXPORT_SYMBOL_GPL(aria_aesni_avx_gfni_encrypt_16way);31EXPORT_SYMBOL_GPL(aria_aesni_avx_gfni_encrypt_16way);
@@ -37,7 +36,6 @@ asmlinkage void aria_aesni_avx_gfni_ctr_crypt_16way(const void *ctx, u8 *dst, · 4 unmodified lines
37 const u8 *src,36 const u8 *src,
38 u8 *keystream, u8 *iv);37 u8 *keystream, u8 *iv);
39EXPORT_SYMBOL_GPL(aria_aesni_avx_gfni_ctr_crypt_16way);38EXPORT_SYMBOL_GPL(aria_aesni_avx_gfni_ctr_crypt_16way);
40#endif /* CONFIG_AS_GFNI */
41 39
42static struct aria_avx_ops aria_ops;40static struct aria_avx_ops aria_ops;
43 41
@@ -199,7 +197,7 @@ static int __init aria_avx_init(void) · 155 unmodified lines
199 return -ENODEV;197 return -ENODEV;
200 }198 }
201 199
202 if (boot_cpu_has(X86_FEATURE_GFNI) && IS_ENABLED(CONFIG_AS_GFNI)) {200 if (boot_cpu_has(X86_FEATURE_GFNI)) {
203 aria_ops.aria_encrypt_16way = aria_aesni_avx_gfni_encrypt_16way;201 aria_ops.aria_encrypt_16way = aria_aesni_avx_gfni_encrypt_16way;
204 aria_ops.aria_decrypt_16way = aria_aesni_avx_gfni_decrypt_16way;202 aria_ops.aria_decrypt_16way = aria_aesni_avx_gfni_decrypt_16way;
205 aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_gfni_ctr_crypt_16way;203 aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_gfni_ctr_crypt_16way;
arch/x86/entry/entry_64_fred.S+1−2
@@ -97,8 +97,7 @@ SYM_FUNC_START(asm_fred_entry_from_kvm) · 96 unmodified lines
97 push %rdi /* fred_ss handed in by the caller */97 push %rdi /* fred_ss handed in by the caller */
98 push %rbp98 push %rbp
99 pushf99 pushf
100 mov $__KERNEL_CS, %rax100 push $__KERNEL_CS
101 push %rax
102 101
103 /*102 /*
104 * Unlike the IDT event delivery, FRED _always_ pushes an error code103 * Unlike the IDT event delivery, FRED _always_ pushes an error code
arch/x86/include/asm/archrandom.h+2−4
@@ -23,8 +23,7 @@ static inline bool __must_check rdrand_long(unsigned long *v) · 22 unmodified lines
23 unsigned int retry = RDRAND_RETRY_LOOPS;23 unsigned int retry = RDRAND_RETRY_LOOPS;
24 do {24 do {
25 asm volatile("rdrand %[out]"25 asm volatile("rdrand %[out]"
26 CC_SET(c)26 : "=@ccc" (ok), [out] "=r" (*v));
27 : CC_OUT(c) (ok), [out] "=r" (*v));
28 if (ok)27 if (ok)
29 return true;28 return true;
30 } while (--retry);29 } while (--retry);
@@ -35,8 +34,7 @@ static inline bool __must_check rdseed_long(unsigned long *v) · 4 unmodified lines
35{34{
36 bool ok;35 bool ok;
37 asm volatile("rdseed %[out]"36 asm volatile("rdseed %[out]"
38 CC_SET(c)37 : "=@ccc" (ok), [out] "=r" (*v));
39 : CC_OUT(c) (ok), [out] "=r" (*v));
40 return ok;38 return ok;
41}39}
42 40
arch/x86/include/asm/asm.h+0−12
@@ -122,18 +122,6 @@ static __always_inline __pure void *rip_rel_ptr(void *p) · 121 unmodified lines
122}122}
123#endif123#endif
124 124
125/*
126 * Macros to generate condition code outputs from inline assembly,
127 * The output operand must be type "bool".
128 */
129#ifdef __GCC_ASM_FLAG_OUTPUTS__
130# define CC_SET(c) "\n\t/* output condition code " #c "*/\n"
131# define CC_OUT(c) "=@cc" #c
132#else
133# define CC_SET(c) "\n\tset" #c " %[_cc_" #c "]\n"
134# define CC_OUT(c) [_cc_ ## c] "=qm"
135#endif
136
137#ifdef __KERNEL__125#ifdef __KERNEL__
138 126
139# include <asm/extable_fixup_types.h>127# include <asm/extable_fixup_types.h>
arch/x86/include/asm/bitops.h+6−12
@@ -99,8 +99,7 @@ static __always_inline bool arch_xor_unlock_is_negative_byte(unsigned long mask, · 98 unmodified lines
99{99{
100 bool negative;100 bool negative;
101 asm_inline volatile(LOCK_PREFIX "xorb %2,%1"101 asm_inline volatile(LOCK_PREFIX "xorb %2,%1"
102 CC_SET(s)102 : "=@ccs" (negative), WBYTE_ADDR(addr)
103 : CC_OUT(s) (negative), WBYTE_ADDR(addr)
104 : "iq" ((char)mask) : "memory");103 : "iq" ((char)mask) : "memory");
105 return negative;104 return negative;
106}105}
@@ -149,8 +148,7 @@ arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr) · 42 unmodified lines
149 bool oldbit;148 bool oldbit;
150 149
151 asm(__ASM_SIZE(bts) " %2,%1"150 asm(__ASM_SIZE(bts) " %2,%1"
152 CC_SET(c)151 : "=@ccc" (oldbit)
153 : CC_OUT(c) (oldbit)
154 : ADDR, "Ir" (nr) : "memory");152 : ADDR, "Ir" (nr) : "memory");
155 return oldbit;153 return oldbit;
156}154}
@@ -175,8 +173,7 @@ arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) · 18 unmodified lines
175 bool oldbit;173 bool oldbit;
176 174
177 asm volatile(__ASM_SIZE(btr) " %2,%1"175 asm volatile(__ASM_SIZE(btr) " %2,%1"
178 CC_SET(c)176 : "=@ccc" (oldbit)
179 : CC_OUT(c) (oldbit)
180 : ADDR, "Ir" (nr) : "memory");177 : ADDR, "Ir" (nr) : "memory");
181 return oldbit;178 return oldbit;
182}179}
@@ -187,8 +184,7 @@ arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr) · 4 unmodified lines
187 bool oldbit;184 bool oldbit;
188 185
189 asm volatile(__ASM_SIZE(btc) " %2,%1"186 asm volatile(__ASM_SIZE(btc) " %2,%1"
190 CC_SET(c)187 : "=@ccc" (oldbit)
191 : CC_OUT(c) (oldbit)
192 : ADDR, "Ir" (nr) : "memory");188 : ADDR, "Ir" (nr) : "memory");
193 189
194 return oldbit;190 return oldbit;
@@ -211,8 +207,7 @@ static __always_inline bool constant_test_bit_acquire(long nr, const volatile un · 16 unmodified lines
211 bool oldbit;207 bool oldbit;
212 208
213 asm volatile("testb %2,%1"209 asm volatile("testb %2,%1"
214 CC_SET(nz)210 : "=@ccnz" (oldbit)
215 : CC_OUT(nz) (oldbit)
216 : "m" (((unsigned char *)addr)[nr >> 3]),211 : "m" (((unsigned char *)addr)[nr >> 3]),
217 "i" (1 << (nr & 7))212 "i" (1 << (nr & 7))
218 :"memory");213 :"memory");
@@ -225,8 +220,7 @@ static __always_inline bool variable_test_bit(long nr, volatile const unsigned l · 6 unmodified lines
225 bool oldbit;220 bool oldbit;
226 221
227 asm volatile(__ASM_SIZE(bt) " %2,%1"222 asm volatile(__ASM_SIZE(bt) " %2,%1"
228 CC_SET(c)223 : "=@ccc" (oldbit)
229 : CC_OUT(c) (oldbit)
230 : "m" (*(unsigned long *)addr), "Ir" (nr) : "memory");224 : "m" (*(unsigned long *)addr), "Ir" (nr) : "memory");
231 225
232 return oldbit;226 return oldbit;
arch/x86/include/asm/cmpxchg.h+4−8
@@ -166,8 +166,7 @@ extern void __add_wrong_size(void) · 165 unmodified lines
166 { \166 { \
167 volatile u8 *__ptr = (volatile u8 *)(_ptr); \167 volatile u8 *__ptr = (volatile u8 *)(_ptr); \
168 asm_inline volatile(lock "cmpxchgb %[new], %[ptr]" \168 asm_inline volatile(lock "cmpxchgb %[new], %[ptr]" \
169 CC_SET(z) \169 : "=@ccz" (success), \
170 : CC_OUT(z) (success), \
171 [ptr] "+m" (*__ptr), \170 [ptr] "+m" (*__ptr), \
172 [old] "+a" (__old) \171 [old] "+a" (__old) \
173 : [new] "q" (__new) \172 : [new] "q" (__new) \
@@ -178,8 +177,7 @@ extern void __add_wrong_size(void) · 4 unmodified lines
178 { \177 { \
179 volatile u16 *__ptr = (volatile u16 *)(_ptr); \178 volatile u16 *__ptr = (volatile u16 *)(_ptr); \
180 asm_inline volatile(lock "cmpxchgw %[new], %[ptr]" \179 asm_inline volatile(lock "cmpxchgw %[new], %[ptr]" \
181 CC_SET(z) \180 : "=@ccz" (success), \
182 : CC_OUT(z) (success), \
183 [ptr] "+m" (*__ptr), \181 [ptr] "+m" (*__ptr), \
184 [old] "+a" (__old) \182 [old] "+a" (__old) \
185 : [new] "r" (__new) \183 : [new] "r" (__new) \
@@ -190,8 +188,7 @@ extern void __add_wrong_size(void) · 4 unmodified lines
190 { \188 { \
191 volatile u32 *__ptr = (volatile u32 *)(_ptr); \189 volatile u32 *__ptr = (volatile u32 *)(_ptr); \
192 asm_inline volatile(lock "cmpxchgl %[new], %[ptr]" \190 asm_inline volatile(lock "cmpxchgl %[new], %[ptr]" \
193 CC_SET(z) \191 : "=@ccz" (success), \
194 : CC_OUT(z) (success), \
195 [ptr] "+m" (*__ptr), \192 [ptr] "+m" (*__ptr), \
196 [old] "+a" (__old) \193 [old] "+a" (__old) \
197 : [new] "r" (__new) \194 : [new] "r" (__new) \
@@ -202,8 +199,7 @@ extern void __add_wrong_size(void) · 4 unmodified lines
202 { \199 { \
203 volatile u64 *__ptr = (volatile u64 *)(_ptr); \200 volatile u64 *__ptr = (volatile u64 *)(_ptr); \
204 asm_inline volatile(lock "cmpxchgq %[new], %[ptr]" \201 asm_inline volatile(lock "cmpxchgq %[new], %[ptr]" \
205 CC_SET(z) \202 : "=@ccz" (success), \
206 : CC_OUT(z) (success), \
207 [ptr] "+m" (*__ptr), \203 [ptr] "+m" (*__ptr), \
208 [old] "+a" (__old) \204 [old] "+a" (__old) \
209 : [new] "r" (__new) \205 : [new] "r" (__new) \
arch/x86/include/asm/cmpxchg_32.h+2−4
@@ -46,8 +46,7 @@ static __always_inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new · 45 unmodified lines
46 bool ret; \46 bool ret; \
47 \47 \
48 asm_inline volatile(_lock "cmpxchg8b %[ptr]" \48 asm_inline volatile(_lock "cmpxchg8b %[ptr]" \
49 CC_SET(e) \49 : "=@ccz" (ret), \
50 : CC_OUT(e) (ret), \
51 [ptr] "+m" (*(_ptr)), \50 [ptr] "+m" (*(_ptr)), \
52 "+a" (o.low), "+d" (o.high) \51 "+a" (o.low), "+d" (o.high) \
53 : "b" (n.low), "c" (n.high) \52 : "b" (n.low), "c" (n.high) \
@@ -125,8 +124,7 @@ static __always_inline u64 arch_cmpxchg64_local(volatile u64 *ptr, u64 old, u64 · 71 unmodified lines
125 ALTERNATIVE(_lock_loc \124 ALTERNATIVE(_lock_loc \
126 "call cmpxchg8b_emu", \125 "call cmpxchg8b_emu", \
127 _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \126 _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \
128 CC_SET(e) \127 : ALT_OUTPUT_SP("=@ccz" (ret), \
129 : ALT_OUTPUT_SP(CC_OUT(e) (ret), \
130 "+a" (o.low), "+d" (o.high)) \128 "+a" (o.low), "+d" (o.high)) \
131 : "b" (n.low), "c" (n.high), \129 : "b" (n.low), "c" (n.high), \
132 [ptr] "S" (_ptr) \130 [ptr] "S" (_ptr) \
arch/x86/include/asm/cmpxchg_64.h+1−2
@@ -66,8 +66,7 @@ static __always_inline u128 arch_cmpxchg128_local(volatile u128 *ptr, u128 old, · 65 unmodified lines
66 bool ret; \66 bool ret; \
67 \67 \
68 asm_inline volatile(_lock "cmpxchg16b %[ptr]" \68 asm_inline volatile(_lock "cmpxchg16b %[ptr]" \
69 CC_SET(e) \69 : "=@ccz" (ret), \
70 : CC_OUT(e) (ret), \
71 [ptr] "+m" (*(_ptr)), \70 [ptr] "+m" (*(_ptr)), \
72 "+a" (o.low), "+d" (o.high) \71 "+a" (o.low), "+d" (o.high) \
73 : "b" (n.low), "c" (n.high) \72 : "b" (n.low), "c" (n.high) \
arch/x86/include/asm/mtrr.h+1−14
@@ -1,21 +1,8 @@
1/* SPDX-License-Identifier: LGPL-2.0+ */
1/* Generic MTRR (Memory Type Range Register) ioctls.2/* Generic MTRR (Memory Type Range Register) ioctls.
2 3
3 Copyright (C) 1997-1999 Richard Gooch4 Copyright (C) 1997-1999 Richard Gooch
4 5
5 This library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Library General Public
7 License as published by the Free Software Foundation; either
8 version 2 of the License, or (at your option) any later version.
9
10 This library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Library General Public License for more details.
14
15 You should have received a copy of the GNU Library General Public
16 License along with this library; if not, write to the Free
17 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 Richard Gooch may be reached by email at rgooch@atnf.csiro.au6 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
20 The postal address is:7 The postal address is:
21 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.8 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
arch/x86/include/asm/mwait.h+2−6
@@ -36,9 +36,7 @@ static __always_inline void __monitor(const void *eax, u32 ecx, u32 edx) · 35 unmodified lines
36 36
37static __always_inline void __monitorx(const void *eax, u32 ecx, u32 edx)37static __always_inline void __monitorx(const void *eax, u32 ecx, u32 edx)
38{38{
39 /* "monitorx %eax, %ecx, %edx" */39 asm volatile("monitorx" :: "a" (eax), "c" (ecx), "d"(edx));
40 asm volatile(".byte 0x0f, 0x01, 0xfa"
41 :: "a" (eax), "c" (ecx), "d"(edx));
42}40}
43 41
44static __always_inline void __mwait(u32 eax, u32 ecx)42static __always_inline void __mwait(u32 eax, u32 ecx)
@@ -80,9 +78,7 @@ static __always_inline void __mwaitx(u32 eax, u32 ebx, u32 ecx) · 35 unmodified lines
80{78{
81 /* No need for TSA buffer clearing on AMD */79 /* No need for TSA buffer clearing on AMD */
82 80
83 /* "mwaitx %eax, %ebx, %ecx" */81 asm volatile("mwaitx" :: "a" (eax), "b" (ebx), "c" (ecx));
84 asm volatile(".byte 0x0f, 0x01, 0xfb"
85 :: "a" (eax), "b" (ebx), "c" (ecx));
86}82}
87 83
88/*84/*
arch/x86/include/asm/percpu.h+4−8
@@ -309,8 +309,7 @@ do { \ · 308 unmodified lines
309 \309 \
310 asm qual (__pcpu_op_##size("cmpxchg") "%[nval], " \310 asm qual (__pcpu_op_##size("cmpxchg") "%[nval], " \
311 __percpu_arg([var]) \311 __percpu_arg([var]) \
312 CC_SET(z) \312 : "=@ccz" (success), \
313 : CC_OUT(z) (success), \
314 [oval] "+a" (pco_old__), \313 [oval] "+a" (pco_old__), \
315 [var] "+m" (__my_cpu_var(_var)) \314 [var] "+m" (__my_cpu_var(_var)) \
316 : [nval] __pcpu_reg_##size(, pco_new__) \315 : [nval] __pcpu_reg_##size(, pco_new__) \
@@ -367,8 +366,7 @@ do { \ · 50 unmodified lines
367 asm_inline qual ( \366 asm_inline qual ( \
368 ALTERNATIVE("call this_cpu_cmpxchg8b_emu", \367 ALTERNATIVE("call this_cpu_cmpxchg8b_emu", \
369 "cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \368 "cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \
370 CC_SET(z) \369 : ALT_OUTPUT_SP("=@ccz" (success), \
371 : ALT_OUTPUT_SP(CC_OUT(z) (success), \
372 [var] "+m" (__my_cpu_var(_var)), \370 [var] "+m" (__my_cpu_var(_var)), \
373 "+a" (old__.low), "+d" (old__.high)) \371 "+a" (old__.low), "+d" (old__.high)) \
374 : "b" (new__.low), "c" (new__.high), \372 : "b" (new__.low), "c" (new__.high), \
@@ -436,8 +434,7 @@ do { \ · 61 unmodified lines
436 asm_inline qual ( \434 asm_inline qual ( \
437 ALTERNATIVE("call this_cpu_cmpxchg16b_emu", \435 ALTERNATIVE("call this_cpu_cmpxchg16b_emu", \
438 "cmpxchg16b " __percpu_arg([var]), X86_FEATURE_CX16) \436 "cmpxchg16b " __percpu_arg([var]), X86_FEATURE_CX16) \
439 CC_SET(z) \437 : ALT_OUTPUT_SP("=@ccz" (success), \
440 : ALT_OUTPUT_SP(CC_OUT(z) (success), \
441 [var] "+m" (__my_cpu_var(_var)), \438 [var] "+m" (__my_cpu_var(_var)), \
442 "+a" (old__.low), "+d" (old__.high)) \439 "+a" (old__.low), "+d" (old__.high)) \
443 : "b" (new__.low), "c" (new__.high), \440 : "b" (new__.low), "c" (new__.high), \
@@ -585,8 +582,7 @@ do { \ · 141 unmodified lines
585 bool oldbit; \582 bool oldbit; \
586 \583 \
587 asm volatile("btl %[nr], " __percpu_arg([var]) \584 asm volatile("btl %[nr], " __percpu_arg([var]) \
588 CC_SET(c) \585 : "=@ccc" (oldbit) \
589 : CC_OUT(c) (oldbit) \
590 : [var] "m" (__my_cpu_var(_var)), \586 : [var] "m" (__my_cpu_var(_var)), \
591 [nr] "rI" (_nr)); \587 [nr] "rI" (_nr)); \
592 oldbit; \588 oldbit; \
arch/x86/include/asm/rmwcc.h+2−24
@@ -6,37 +6,15 @@ · 5 unmodified lines
6 6
7#define __CLOBBERS_MEM(clb...) "memory", ## clb7#define __CLOBBERS_MEM(clb...) "memory", ## clb
8 8
9#ifndef __GCC_ASM_FLAG_OUTPUTS__
10
11/* Use asm goto */
12
13#define __GEN_RMWcc(fullop, _var, cc, clobbers, ...) \
14({ \
15 bool c = false; \
16 asm goto (fullop "; j" #cc " %l[cc_label]" \
17 : : [var] "m" (_var), ## __VA_ARGS__ \
18 : clobbers : cc_label); \
19 if (0) { \
20cc_label: c = true; \
21 } \
22 c; \
23})
24
25#else /* defined(__GCC_ASM_FLAG_OUTPUTS__) */
26
27/* Use flags output or a set instruction */
28
29#define __GEN_RMWcc(fullop, _var, cc, clobbers, ...) \9#define __GEN_RMWcc(fullop, _var, cc, clobbers, ...) \
30({ \10({ \
31 bool c; \11 bool c; \
32 asm_inline volatile (fullop CC_SET(cc) \12 asm_inline volatile (fullop \
33 : [var] "+m" (_var), CC_OUT(cc) (c) \13 : [var] "+m" (_var), "=@cc" #cc (c) \
34 : __VA_ARGS__ : clobbers); \14 : __VA_ARGS__ : clobbers); \
35 c; \15 c; \
36})16})
37 17
38#endif /* defined(__GCC_ASM_FLAG_OUTPUTS__) */
39
40#define GEN_UNARY_RMWcc_4(op, var, cc, arg0) \18#define GEN_UNARY_RMWcc_4(op, var, cc, arg0) \
41 __GEN_RMWcc(op " " arg0, var, cc, __CLOBBERS_MEM())19 __GEN_RMWcc(op " " arg0, var, cc, __CLOBBERS_MEM())
42 20
arch/x86/include/asm/sev.h+1−2
@@ -491,8 +491,7 @@ static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) · 490 unmodified lines
491 491
492 /* "pvalidate" mnemonic support in binutils 2.36 and newer */492 /* "pvalidate" mnemonic support in binutils 2.36 and newer */
493 asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFF\n\t"493 asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFF\n\t"
494 CC_SET(c)494 : "=@ccc"(no_rmpupdate), "=a"(rc)
495 : CC_OUT(c) (no_rmpupdate), "=a"(rc)
496 : "a"(vaddr), "c"(rmp_psize), "d"(validate)495 : "a"(vaddr), "c"(rmp_psize), "d"(validate)
497 : "memory", "cc");496 : "memory", "cc");
498 497
arch/x86/include/asm/signal.h+1−2
@@ -83,8 +83,7 @@ static inline int __const_sigismember(sigset_t *set, int _sig) · 82 unmodified lines
83static inline int __gen_sigismember(sigset_t *set, int _sig)83static inline int __gen_sigismember(sigset_t *set, int _sig)
84{84{
85 bool ret;85 bool ret;
86 asm("btl %2,%1" CC_SET(c)86 asm("btl %2,%1" : "=@ccc"(ret) : "m"(*set), "Ir"(_sig-1));
87 : CC_OUT(c) (ret) : "m"(*set), "Ir"(_sig-1));
88 return ret;87 return ret;
89}88}
90 89
arch/x86/include/asm/special_insns.h+3−7
@@ -75,9 +75,7 @@ static inline u32 rdpkru(void) · 74 unmodified lines
75 * "rdpkru" instruction. Places PKRU contents in to EAX,75 * "rdpkru" instruction. Places PKRU contents in to EAX,
76 * clears EDX and requires that ecx=0.76 * clears EDX and requires that ecx=0.
77 */77 */
78 asm volatile(".byte 0x0f,0x01,0xee\n\t"78 asm volatile("rdpkru" : "=a" (pkru), "=d" (edx) : "c" (ecx));
79 : "=a" (pkru), "=d" (edx)
80 : "c" (ecx));
81 return pkru;79 return pkru;
82}80}
83 81
@@ -89,8 +87,7 @@ static inline void wrpkru(u32 pkru) · 5 unmodified lines
89 * "wrpkru" instruction. Loads contents in EAX to PKRU,87 * "wrpkru" instruction. Loads contents in EAX to PKRU,
90 * requires that ecx = edx = 0.88 * requires that ecx = edx = 0.
91 */89 */
92 asm volatile(".byte 0x0f,0x01,0xef\n\t"90 asm volatile("wrpkru" : : "a" (pkru), "c"(ecx), "d"(edx));
93 : : "a" (pkru), "c"(ecx), "d"(edx));
94}91}
95 92
96#else93#else
@@ -287,8 +284,7 @@ static inline int enqcmds(void __iomem *dst, const void *src) · 190 unmodified lines
287 * See movdir64b()'s comment on operand specification.284 * See movdir64b()'s comment on operand specification.
288 */285 */
289 asm volatile(".byte 0xf3, 0x0f, 0x38, 0xf8, 0x02, 0x66, 0x90"286 asm volatile(".byte 0xf3, 0x0f, 0x38, 0xf8, 0x02, 0x66, 0x90"
290 CC_SET(z)287 : "=@ccz" (zf), "+m" (*__dst)
291 : CC_OUT(z) (zf), "+m" (*__dst)
292 : "m" (*__src), "a" (__dst), "d" (__src));288 : "m" (*__src), "a" (__dst), "d" (__src));
293 289
294 /* Submission failure is indicated via EFLAGS.ZF=1 */290 /* Submission failure is indicated via EFLAGS.ZF=1 */
arch/x86/include/asm/uaccess.h+3−4
@@ -378,7 +378,7 @@ do { \ · 377 unmodified lines
378 asm_goto_output("\n" \378 asm_goto_output("\n" \
379 "1: " LOCK_PREFIX "cmpxchg"itype" %[new], %[ptr]\n"\379 "1: " LOCK_PREFIX "cmpxchg"itype" %[new], %[ptr]\n"\
380 _ASM_EXTABLE_UA(1b, %l[label]) \380 _ASM_EXTABLE_UA(1b, %l[label]) \
381 : CC_OUT(z) (success), \381 : "=@ccz" (success), \
382 [ptr] "+m" (*_ptr), \382 [ptr] "+m" (*_ptr), \
383 [old] "+a" (__old) \383 [old] "+a" (__old) \
384 : [new] ltype (__new) \384 : [new] ltype (__new) \
@@ -397,7 +397,7 @@ do { \ · 12 unmodified lines
397 asm_goto_output("\n" \397 asm_goto_output("\n" \
398 "1: " LOCK_PREFIX "cmpxchg8b %[ptr]\n" \398 "1: " LOCK_PREFIX "cmpxchg8b %[ptr]\n" \
399 _ASM_EXTABLE_UA(1b, %l[label]) \399 _ASM_EXTABLE_UA(1b, %l[label]) \
400 : CC_OUT(z) (success), \400 : "=@ccz" (success), \
401 "+A" (__old), \401 "+A" (__old), \
402 [ptr] "+m" (*_ptr) \402 [ptr] "+m" (*_ptr) \
403 : "b" ((u32)__new), \403 : "b" ((u32)__new), \
@@ -417,11 +417,10 @@ do { \ · 13 unmodified lines
417 __typeof__(*(_ptr)) __new = (_new); \417 __typeof__(*(_ptr)) __new = (_new); \
418 asm volatile("\n" \418 asm volatile("\n" \
419 "1: " LOCK_PREFIX "cmpxchg"itype" %[new], %[ptr]\n"\419 "1: " LOCK_PREFIX "cmpxchg"itype" %[new], %[ptr]\n"\
420 CC_SET(z) \
421 "2:\n" \420 "2:\n" \
422 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, \421 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, \
423 %[errout]) \422 %[errout]) \
424 : CC_OUT(z) (success), \423 : "=@ccz" (success), \
425 [errout] "+r" (__err), \424 [errout] "+r" (__err), \
426 [ptr] "+m" (*_ptr), \425 [ptr] "+m" (*_ptr), \
427 [old] "+a" (__old) \426 [old] "+a" (__old) \
arch/x86/kernel/cpu/mtrr/cleanup.c+1−14
@@ -1,21 +1,8 @@
1// SPDX-License-Identifier: LGPL-2.0+
1/*2/*
2 * MTRR (Memory Type Range Register) cleanup3 * MTRR (Memory Type Range Register) cleanup
3 *4 *
4 * Copyright (C) 2009 Yinghai Lu5 * Copyright (C) 2009 Yinghai Lu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Library General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Library General Public License for more details.
15 *
16 * You should have received a copy of the GNU Library General Public
17 * License along with this library; if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */6 */
20#include <linux/init.h>7#include <linux/init.h>
21#include <linux/pci.h>8#include <linux/pci.h>
arch/x86/kernel/cpu/mtrr/mtrr.c+1−14
@@ -1,22 +1,9 @@
1// SPDX-License-Identifier: LGPL-2.0+
1/* Generic MTRR (Memory Type Range Register) driver.2/* Generic MTRR (Memory Type Range Register) driver.
2 3
3 Copyright (C) 1997-2000 Richard Gooch4 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel5 Copyright (c) 2002 Patrick Mochel
5 6
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
10
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
15
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au7 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:8 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.9 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
arch/x86/kernel/cpu/sgx/encls.h+3−3
@@ -68,7 +68,7 @@ static inline bool encls_failed(int ret) · 67 unmodified lines
68 ({ \68 ({ \
69 int ret; \69 int ret; \
70 asm volatile( \70 asm volatile( \
71 "1: .byte 0x0f, 0x01, 0xcf;\n\t" \71 "1: encls\n" \
72 "2:\n" \72 "2:\n" \
73 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_FAULT_SGX) \73 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_FAULT_SGX) \
74 : "=a"(ret) \74 : "=a"(ret) \
@@ -111,8 +111,8 @@ static inline bool encls_failed(int ret) · 36 unmodified lines
111 ({ \111 ({ \
112 int ret; \112 int ret; \
113 asm volatile( \113 asm volatile( \
114 "1: .byte 0x0f, 0x01, 0xcf;\n\t" \114 "1: encls\n\t" \
115 " xor %%eax,%%eax;\n" \115 "xor %%eax,%%eax\n" \
116 "2:\n" \116 "2:\n" \
117 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_FAULT_SGX) \117 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_FAULT_SGX) \
118 : "=a"(ret), "=b"(rbx_out) \118 : "=a"(ret), "=b"(rbx_out) \
tools/arch/x86/include/asm/asm.h+0−12
@@ -108,18 +108,6 @@ · 107 unmodified lines
108 108
109#endif109#endif
110 110
111/*
112 * Macros to generate condition code outputs from inline assembly,
113 * The output operand must be type "bool".
114 */
115#ifdef __GCC_ASM_FLAG_OUTPUTS__
116# define CC_SET(c) "\n\t/* output condition code " #c "*/\n"
117# define CC_OUT(c) "=@cc" #c
118#else
119# define CC_SET(c) "\n\tset" #c " %[_cc_" #c "]\n"
120# define CC_OUT(c) [_cc_ ## c] "=qm"
121#endif
122
123#ifdef __KERNEL__111#ifdef __KERNEL__
124 112
125/* Exception table entry */113/* Exception table entry */
tools/perf/bench/find-bit-bench.c+1−1
@@ -37,7 +37,7 @@ static noinline void workload(int val) · 36 unmodified lines
37 accumulator++;37 accumulator++;
38}38}
39 39
40#if (defined(__i386__) || defined(__x86_64__)) && defined(__GCC_ASM_FLAG_OUTPUTS__)40#if defined(__i386__) || defined(__x86_64__)
41static bool asm_test_bit(long nr, const unsigned long *addr)41static bool asm_test_bit(long nr, const unsigned long *addr)
42{42{
43 bool oldbit;43 bool oldbit;

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