Pull LoongArch updates from Huacai Chen: - Switch to relative exception tables - Add unaligned access support - Add alternative runtime patching mechanism - Add FDT booting support from efi system table - Add suspend/hibernation (ACPI S3/S4) support - Add basic STACKPROTECTOR support - Add ftrace (function tracer) support - Update the default config file * tag 'loongarch-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: (24 commits) LoongArch: Update Loongson-3 default config file LoongArch: modules/ftrace: Initialize PLT at load time LoongArch/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support LoongArch/ftrace: Add HAVE_DYNAMIC_FTRACE_WITH_ARGS support LoongArch/ftrace: Add HAVE_DYNAMIC_FTRACE_WITH_REGS support LoongArch/ftrace: Add dynamic function graph tracer support LoongArch/ftrace: Add dynamic function tracer support LoongArch/ftrace: Add recordmcount support LoongArch/ftrace: Add basic support LoongArch: module: Use got/plt section indices for relocations LoongArch: Add basic STACKPROTECTOR support LoongArch: Add hibernation (ACPI S4) support LoongArch: Add suspend (ACPI S3) support LoongArch: Add processing ISA Node in DeviceTree LoongArch: Add FDT booting support from efi system table LoongArch: Use alternative to optimize libraries LoongArch: Add alternative runtime patching mechanism LoongArch: Add unaligned access support LoongArch: BPF: Add BPF exception tables LoongArch: Remove the .fixup section usage ...
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| @@ -1523,6 +1523,14 @@ static int addend_mips_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) · 1522 unmodified lines | ||
| 1523 | 1523 | #define R_RISCV_SUB32 39 |
| 1524 | 1524 | #endif |
| 1525 | 1525 | |
| 1526 | +#ifndef EM_LOONGARCH | |
| 1527 | +#define EM_LOONGARCH 258 | |
| 1528 | +#endif | |
| 1529 | + | |
| 1530 | +#ifndef R_LARCH_SUB32 | |
| 1531 | +#define R_LARCH_SUB32 55 | |
| 1532 | +#endif | |
| 1533 | + | |
| 1526 | 1534 | static void section_rela(const char *modname, struct elf_info *elf, |
| 1527 | 1535 | Elf_Shdr *sechdr) |
| 1528 | 1536 | { |
| @@ -1564,6 +1572,11 @@ static void section_rela(const char *modname, struct elf_info *elf, · 35 unmodified lines | ||
| 1564 | 1572 | ELF_R_TYPE(r.r_info) == R_RISCV_SUB32) |
| 1565 | 1573 | continue; |
| 1566 | 1574 | break; |
| 1575 | + case EM_LOONGARCH: | |
| 1576 | + if (!strcmp("__ex_table", fromsec) && | |
| 1577 | + ELF_R_TYPE(r.r_info) == R_LARCH_SUB32) | |
| 1578 | + continue; | |
| 1579 | + break; | |
| 1567 | 1580 | } |
| 1568 | 1581 | sym = elf->symtab_start + r_sym; |
| 1569 | 1582 | /* Skip special sections */ |
| @@ -38,6 +38,14 @@ · 37 unmodified lines | ||
| 38 | 38 | #define R_AARCH64_ABS64 257 |
| 39 | 39 | #endif |
| 40 | 40 | |
| 41 | +#ifndef EM_LOONGARCH | |
| 42 | +#define EM_LOONGARCH 258 | |
| 43 | +#define R_LARCH_32 1 | |
| 44 | +#define R_LARCH_64 2 | |
| 45 | +#define R_LARCH_MARK_LA 20 | |
| 46 | +#define R_LARCH_SOP_PUSH_PLT_PCREL 29 | |
| 47 | +#endif | |
| 48 | + | |
| 41 | 49 | #define R_ARM_PC24 1 |
| 42 | 50 | #define R_ARM_THM_CALL 10 |
| 43 | 51 | #define R_ARM_CALL 28 |
| @@ -441,6 +449,28 @@ static int arm64_is_fake_mcount(Elf64_Rel const *rp) · 397 unmodified lines | ||
| 441 | 449 | return ELF64_R_TYPE(w8(rp->r_info)) != R_AARCH64_CALL26; |
| 442 | 450 | } |
| 443 | 451 | |
| 452 | +static int LARCH32_is_fake_mcount(Elf32_Rel const *rp) | |
| 453 | +{ | |
| 454 | + switch (ELF64_R_TYPE(w(rp->r_info))) { | |
| 455 | + case R_LARCH_MARK_LA: | |
| 456 | + case R_LARCH_SOP_PUSH_PLT_PCREL: | |
| 457 | + return 0; | |
| 458 | + } | |
| 459 | + | |
| 460 | + return 1; | |
| 461 | +} | |
| 462 | + | |
| 463 | +static int LARCH64_is_fake_mcount(Elf64_Rel const *rp) | |
| 464 | +{ | |
| 465 | + switch (ELF64_R_TYPE(w(rp->r_info))) { | |
| 466 | + case R_LARCH_MARK_LA: | |
| 467 | + case R_LARCH_SOP_PUSH_PLT_PCREL: | |
| 468 | + return 0; | |
| 469 | + } | |
| 470 | + | |
| 471 | + return 1; | |
| 472 | +} | |
| 473 | + | |
| 444 | 474 | /* 64-bit EM_MIPS has weird ELF64_Rela.r_info. |
| 445 | 475 | * http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf |
| 446 | 476 | * We interpret Table 29 Relocation Operation (Elf64_Rel, Elf64_Rela) [p.40] |
| @@ -558,6 +588,7 @@ static int do_file(char const *const fname) · 111 unmodified lines | ||
| 558 | 588 | break; |
| 559 | 589 | case EM_IA_64: reltype = R_IA64_IMM64; break; |
| 560 | 590 | case EM_MIPS: /* reltype: e_class */ break; |
| 591 | + case EM_LOONGARCH: /* reltype: e_class */ break; | |
| 561 | 592 | case EM_PPC: reltype = R_PPC_ADDR32; break; |
| 562 | 593 | case EM_PPC64: reltype = R_PPC64_ADDR64; break; |
| 563 | 594 | case EM_S390: /* reltype: e_class */ break; |
| @@ -589,6 +620,10 @@ static int do_file(char const *const fname) · 25 unmodified lines | ||
| 589 | 620 | reltype = R_MIPS_32; |
| 590 | 621 | is_fake_mcount32 = MIPS32_is_fake_mcount; |
| 591 | 622 | } |
| 623 | + if (w2(ehdr->e_machine) == EM_LOONGARCH) { | |
| 624 | + reltype = R_LARCH_32; | |
| 625 | + is_fake_mcount32 = LARCH32_is_fake_mcount; | |
| 626 | + } | |
| 592 | 627 | if (do32(ehdr, fname, reltype) < 0) |
| 593 | 628 | goto out; |
| 594 | 629 | break; |
| @@ -610,6 +645,10 @@ static int do_file(char const *const fname) · 15 unmodified lines | ||
| 610 | 645 | Elf64_r_info = MIPS64_r_info; |
| 611 | 646 | is_fake_mcount64 = MIPS64_is_fake_mcount; |
| 612 | 647 | } |
| 648 | + if (w2(ghdr->e_machine) == EM_LOONGARCH) { | |
| 649 | + reltype = R_LARCH_64; | |
| 650 | + is_fake_mcount64 = LARCH64_is_fake_mcount; | |
| 651 | + } | |
| 613 | 652 | if (do64(ghdr, fname, reltype) < 0) |
| 614 | 653 | goto out; |
| 615 | 654 | break; |
| @@ -304,6 +304,7 @@ static int do_file(char const *const fname, void *addr) · 303 unmodified lines | ||
| 304 | 304 | switch (r2(&ehdr->e_machine)) { |
| 305 | 305 | case EM_386: |
| 306 | 306 | case EM_AARCH64: |
| 307 | + case EM_LOONGARCH: | |
| 307 | 308 | case EM_RISCV: |
| 308 | 309 | case EM_S390: |
| 309 | 310 | case EM_X86_64: |
| @@ -317,7 +318,6 @@ static int do_file(char const *const fname, void *addr) · 7 unmodified lines | ||
| 317 | 318 | case EM_ARCOMPACT: |
| 318 | 319 | case EM_ARCV2: |
| 319 | 320 | case EM_ARM: |
| 320 | − case EM_LOONGARCH: | |
| 321 | 321 | case EM_MICROBLAZE: |
| 322 | 322 | case EM_MIPS: |
| 323 | 323 | case EM_XTENSA: |