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drm/i915/dg2: Enable 5th port

DG2 supports a 5th display output which the hardware refers to as "TC1," even though it isn't a Type-C output. This behaves similarly to the TC1 on past platforms with just a couple minor differences: * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on ICP/TGP/ADP. * DG2 doesn't need the hpd inversion setting that we had to use on DG1 v2: intel_ddi_init(dev_priv, PORT_TC1); [Matt]

Matt Roper committed 4 years ago

Commit 2f8a6691 parent 9b693454 files · +20 −3Browse files

Unified · Split

4 files
  1. drivers/gpu/drm/i915/display/intel_display.c +1 −0
  2. drivers/gpu/drm/i915/display/intel_gmbus.c +14 −2
  3. drivers/gpu/drm/i915/i915_irq.c +4 −1
  4. drivers/gpu/drm/i915/i915_reg.h +1 −0
drivers/gpu/drm/i915/display/intel_display.c+1−0
@@ -8757,6 +8757,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) · 8756 unmodified lines
8757 intel_ddi_init(dev_priv, PORT_B);8757 intel_ddi_init(dev_priv, PORT_B);
8758 intel_ddi_init(dev_priv, PORT_C);8758 intel_ddi_init(dev_priv, PORT_C);
8759 intel_ddi_init(dev_priv, PORT_D_XELPD);8759 intel_ddi_init(dev_priv, PORT_D_XELPD);
8760 intel_ddi_init(dev_priv, PORT_TC1);
8760 } else if (IS_ALDERLAKE_P(dev_priv)) {8761 } else if (IS_ALDERLAKE_P(dev_priv)) {
8761 intel_ddi_init(dev_priv, PORT_A);8762 intel_ddi_init(dev_priv, PORT_A);
8762 intel_ddi_init(dev_priv, PORT_B);8763 intel_ddi_init(dev_priv, PORT_B);
drivers/gpu/drm/i915/display/intel_gmbus.c+14−2
@@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = { · 97 unmodified lines
98 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },98 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
99};99};
100 100
101static const struct gmbus_pin gmbus_pins_dg2[] = {
102 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
103 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
104 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
105 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
106 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
107};
108
101/* pin is expected to be valid */109/* pin is expected to be valid */
102static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,110static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
103 unsigned int pin)111 unsigned int pin)
104{112{
105 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)113 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
114 return &gmbus_pins_dg2[pin];
115 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
106 return &gmbus_pins_dg1[pin];116 return &gmbus_pins_dg1[pin];
107 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)117 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
108 return &gmbus_pins_icp[pin];118 return &gmbus_pins_icp[pin];
@@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, · 14 unmodified lines
123{133{
124 unsigned int size;134 unsigned int size;
125 135
126 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)136 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
137 size = ARRAY_SIZE(gmbus_pins_dg2);
138 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
127 size = ARRAY_SIZE(gmbus_pins_dg1);139 size = ARRAY_SIZE(gmbus_pins_dg1);
128 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)140 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
129 size = ARRAY_SIZE(gmbus_pins_icp);141 size = ARRAY_SIZE(gmbus_pins_icp);
drivers/gpu/drm/i915/i915_irq.c+4−1
@@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = { · 178 unmodified lines
179 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),179 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
180 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),180 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
181 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),181 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
182 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
182};183};
183 184
184static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)185static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) · 4239 unmodified lines
4424 if (I915_HAS_HOTPLUG(dev_priv))4425 if (I915_HAS_HOTPLUG(dev_priv))
4425 dev_priv->hotplug_funcs = &i915_hpd_funcs;4426 dev_priv->hotplug_funcs = &i915_hpd_funcs;
4426 } else {4427 } else {
4427 if (HAS_PCH_DG1(dev_priv))4428 if (HAS_PCH_DG2(dev_priv))
4429 dev_priv->hotplug_funcs = &icp_hpd_funcs;
4430 else if (HAS_PCH_DG1(dev_priv))
4428 dev_priv->hotplug_funcs = &dg1_hpd_funcs;4431 dev_priv->hotplug_funcs = &dg1_hpd_funcs;
4429 else if (DISPLAY_VER(dev_priv) >= 11)4432 else if (DISPLAY_VER(dev_priv) >= 11)
4430 dev_priv->hotplug_funcs = &gen11_hpd_funcs;4433 dev_priv->hotplug_funcs = &gen11_hpd_funcs;
drivers/gpu/drm/i915/i915_reg.h+1−0
@@ -6059,6 +6059,7 @@ · 6058 unmodified lines
6059/* south display engine interrupt: ICP/TGP */6059/* south display engine interrupt: ICP/TGP */
6060#define SDE_GMBUS_ICP (1 << 23)6060#define SDE_GMBUS_ICP (1 << 23)
6061#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))6061#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
6062#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
6062#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))6063#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
6063#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \6064#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
6064 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \6065 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \

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