lael-labs/linux

arch/blackfin/include/asm/bfin_sport.h+0−6

 #endif
-/* Workaround defBF*.h SPORT MMRs till they get cleansed */
-#undef DTYPE_NORM
-#undef SLEN
-#undef SP_WOFF
-#undef SP_WSIZE
 /* SPORT_TCR1 Masks */
 #define TSPEN		0x0001	/* TX enable */
 #define ITCLK		0x0002	/* Internal TX Clock Select */

arch/blackfin/mach-bf518/include/mach/defBF51x_base.h+0−82

@@ -913,88 +913,6 @@ · 912 unmodified lines
913	#define PH6 0x0040	913	#define PH6 0x0040
914	#define PH7 0x0080	914	#define PH7 0x0080
915		915
916
917	/* ***************** SERIAL PORT MASKS ************************************/
918	/* SPORTx_TCR1 Masks */
919	#define TSPEN 0x0001 /* Transmit Enable */
920	#define ITCLK 0x0002 /* Internal Transmit Clock Select */
921	#define DTYPE_NORM 0x0004 /* Data Format Normal */
922	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
923	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
924	#define TLSBIT 0x0010 /* Transmit Bit Order */
925	#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
926	#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
927	#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
928	#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
929	#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
930	#define TCKFE 0x4000 /* Clock Falling Edge Select */
931
932	/* SPORTx_TCR2 Masks and Macro */
933	#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
934	#define TXSE 0x0100 /* TX Secondary Enable */
935	#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
936	#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
937
938	/* SPORTx_RCR1 Masks */
939	#define RSPEN 0x0001 /* Receive Enable */
940	#define IRCLK 0x0002 /* Internal Receive Clock Select */
941	#define DTYPE_NORM 0x0004 /* Data Format Normal */
942	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
943	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
944	#define RLSBIT 0x0010 /* Receive Bit Order */
945	#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
946	#define RFSR 0x0400 /* Receive Frame Sync Required Select */
947	#define LRFS 0x1000 /* Low Receive Frame Sync Select */
948	#define LARFS 0x2000 /* Late Receive Frame Sync Select */
949	#define RCKFE 0x4000 /* Clock Falling Edge Select */
950
951	/* SPORTx_RCR2 Masks */
952	#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
953	#define RXSE 0x0100 /* RX Secondary Enable */
954	#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
955	#define RRFST 0x0400 /* Right-First Data Order */
956
957	/* SPORTx_STAT Masks */
958	#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
959	#define RUVF 0x0002 /* Sticky Receive Underflow Status */
960	#define ROVF 0x0004 /* Sticky Receive Overflow Status */
961	#define TXF 0x0008 /* Transmit FIFO Full Status */
962	#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
963	#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
964	#define TXHRE 0x0040 /* Transmit Hold Register Empty */
965
966	/* SPORTx_MCMC1 Macros */
967	#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
968
969	/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
970	#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
971
972	/* SPORTx_MCMC2 Masks */
973	#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
974	#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
975	#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
976	#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
977	#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
978	#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
979	#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
980	#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
981	#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
982	#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
983	#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
984	#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
985	#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
986	#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
987	#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
988	#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
989	#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
990	#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
991	#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
992	#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
993	#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
994	#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
995	#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
996
997
998	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/	916	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/
999	/* EBIU_AMGCTL Masks */	917	/* EBIU_AMGCTL Masks */
1000	#define AMCKEN 0x0001 /* Enable CLKOUT */	918	#define AMCKEN 0x0001 /* Enable CLKOUT */

arch/blackfin/mach-bf527/boards/cm_bf527.c+0−1

@@ -145,7 +145,6 @@ static struct mtd_partition partition_info[] = { · 144 unmodified lines
145	};	145	};
146		146
147	static struct bf5xx_nand_platform bf5xx_nand_platform = {	147	static struct bf5xx_nand_platform bf5xx_nand_platform = {
148	.page_size = NFC_PG_SIZE_256,
149	.data_width = NFC_NWIDTH_8,	148	.data_width = NFC_NWIDTH_8,
150	.partitions = partition_info,	149	.partitions = partition_info,
151	.nr_partitions = ARRAY_SIZE(partition_info),	150	.nr_partitions = ARRAY_SIZE(partition_info),

arch/blackfin/mach-bf527/boards/ezbrd.c+0−1

@@ -149,7 +149,6 @@ static struct mtd_partition partition_info[] = { · 148 unmodified lines
149	};	149	};
150		150
151	static struct bf5xx_nand_platform bf5xx_nand_platform = {	151	static struct bf5xx_nand_platform bf5xx_nand_platform = {
152	.page_size = NFC_PG_SIZE_256,
153	.data_width = NFC_NWIDTH_8,	152	.data_width = NFC_NWIDTH_8,
154	.partitions = partition_info,	153	.partitions = partition_info,
155	.nr_partitions = ARRAY_SIZE(partition_info),	154	.nr_partitions = ARRAY_SIZE(partition_info),

arch/blackfin/mach-bf527/boards/ezkit.c+0−1

@@ -234,7 +234,6 @@ static struct mtd_partition partition_info[] = { · 233 unmodified lines
234	};	234	};
235		235
236	static struct bf5xx_nand_platform bf5xx_nand_platform = {	236	static struct bf5xx_nand_platform bf5xx_nand_platform = {
237	.page_size = NFC_PG_SIZE_256,
238	.data_width = NFC_NWIDTH_8,	237	.data_width = NFC_NWIDTH_8,
239	.partitions = partition_info,	238	.partitions = partition_info,
240	.nr_partitions = ARRAY_SIZE(partition_info),	239	.nr_partitions = ARRAY_SIZE(partition_info),

arch/blackfin/mach-bf527/include/mach/defBF52x_base.h+0−82

@@ -922,88 +922,6 @@ · 921 unmodified lines
922	#define PH14 0x4000	922	#define PH14 0x4000
923	#define PH15 0x8000	923	#define PH15 0x8000
924		924
925
926	/* ***************** SERIAL PORT MASKS ************************************/
927	/* SPORTx_TCR1 Masks */
928	#define TSPEN 0x0001 /* Transmit Enable */
929	#define ITCLK 0x0002 /* Internal Transmit Clock Select */
930	#define DTYPE_NORM 0x0004 /* Data Format Normal */
931	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
932	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
933	#define TLSBIT 0x0010 /* Transmit Bit Order */
934	#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
935	#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
936	#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
937	#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
938	#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
939	#define TCKFE 0x4000 /* Clock Falling Edge Select */
940
941	/* SPORTx_TCR2 Masks and Macro */
942	#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
943	#define TXSE 0x0100 /* TX Secondary Enable */
944	#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
945	#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
946
947	/* SPORTx_RCR1 Masks */
948	#define RSPEN 0x0001 /* Receive Enable */
949	#define IRCLK 0x0002 /* Internal Receive Clock Select */
950	#define DTYPE_NORM 0x0004 /* Data Format Normal */
951	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
952	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
953	#define RLSBIT 0x0010 /* Receive Bit Order */
954	#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
955	#define RFSR 0x0400 /* Receive Frame Sync Required Select */
956	#define LRFS 0x1000 /* Low Receive Frame Sync Select */
957	#define LARFS 0x2000 /* Late Receive Frame Sync Select */
958	#define RCKFE 0x4000 /* Clock Falling Edge Select */
959
960	/* SPORTx_RCR2 Masks */
961	#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
962	#define RXSE 0x0100 /* RX Secondary Enable */
963	#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
964	#define RRFST 0x0400 /* Right-First Data Order */
965
966	/* SPORTx_STAT Masks */
967	#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
968	#define RUVF 0x0002 /* Sticky Receive Underflow Status */
969	#define ROVF 0x0004 /* Sticky Receive Overflow Status */
970	#define TXF 0x0008 /* Transmit FIFO Full Status */
971	#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
972	#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
973	#define TXHRE 0x0040 /* Transmit Hold Register Empty */
974
975	/* SPORTx_MCMC1 Macros */
976	#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
977
978	/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
979	#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
980
981	/* SPORTx_MCMC2 Masks */
982	#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
983	#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
984	#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
985	#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
986	#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
987	#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
988	#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
989	#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
990	#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
991	#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
992	#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
993	#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
994	#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
995	#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
996	#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
997	#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
998	#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
999	#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1000	#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1001	#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1002	#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1003	#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1004	#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1005
1006
1007	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/	925	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/
1008	/* EBIU_AMGCTL Masks */	926	/* EBIU_AMGCTL Masks */
1009	#define AMCKEN 0x0001 /* Enable CLKOUT */	927	#define AMCKEN 0x0001 /* Enable CLKOUT */

arch/blackfin/mach-bf533/include/mach/defBF532.h+0−92

@@ -509,98 +509,6 @@ · 508 unmodified lines
509	#define IREN_P 0x01	509	#define IREN_P 0x01
510	#define UCEN_P 0x00	510	#define UCEN_P 0x00
511		511
512	/* ******** SERIAL PORT MASKS ******************** */
513
514	/* SPORTx_TCR1 Masks */
515	#define TSPEN 0x0001 /* TX enable */
516	#define ITCLK 0x0002 /* Internal TX Clock Select */
517	#define TDTYPE 0x000C /* TX Data Formatting Select */
518	#define DTYPE_NORM 0x0000 /* Data Format Normal */
519	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
520	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
521	#define TLSBIT 0x0010 /* TX Bit Order */
522	#define ITFS 0x0200 /* Internal TX Frame Sync Select */
523	#define TFSR 0x0400 /* TX Frame Sync Required Select */
524	#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
525	#define LTFS 0x1000 /* Low TX Frame Sync Select */
526	#define LATFS 0x2000 /* Late TX Frame Sync Select */
527	#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
528
529	/* SPORTx_TCR2 Masks */
530	#if defined(__ADSPBF531__) \|\| defined(__ADSPBF532__) \|\| \
531	defined(__ADSPBF533__)
532	# define SLEN 0x001F /TX Word Length /
533	#else
534	# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
535	#endif
536	#define TXSE 0x0100 /TX Secondary Enable /
537	#define TSFSE 0x0200 /TX Stereo Frame Sync Enable /
538	#define TRFST 0x0400 /TX Right-First Data Order /
539
540	/* SPORTx_RCR1 Masks */
541	#define RSPEN 0x0001 /* RX enable */
542	#define IRCLK 0x0002 /* Internal RX Clock Select */
543	#define RDTYPE 0x000C /* RX Data Formatting Select */
544	#define DTYPE_NORM 0x0000 /* no companding */
545	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
546	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
547	#define RLSBIT 0x0010 /* RX Bit Order */
548	#define IRFS 0x0200 /* Internal RX Frame Sync Select */
549	#define RFSR 0x0400 /* RX Frame Sync Required Select */
550	#define LRFS 0x1000 /* Low RX Frame Sync Select */
551	#define LARFS 0x2000 /* Late RX Frame Sync Select */
552	#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
553
554	/* SPORTx_RCR2 Masks */
555	/* SLEN defined above */
556	#define RXSE 0x0100 /RX Secondary Enable /
557	#define RSFSE 0x0200 /RX Stereo Frame Sync Enable /
558	#define RRFST 0x0400 /Right-First Data Order /
559
560	/SPORTx_STAT Masks /
561	#define RXNE 0x0001 /RX FIFO Not Empty Status /
562	#define RUVF 0x0002 /RX Underflow Status /
563	#define ROVF 0x0004 /RX Overflow Status /
564	#define TXF 0x0008 /TX FIFO Full Status /
565	#define TUVF 0x0010 /TX Underflow Status /
566	#define TOVF 0x0020 /TX Overflow Status /
567	#define TXHRE 0x0040 /TX Hold Register Empty /
568
569	/SPORTx_MCMC1 Masks /
570	#define SP_WSIZE 0x0000F000 /Multichannel Window Size Field /
571	#define SP_WOFF 0x000003FF /Multichannel Window Offset Field /
572	/* SPORTx_MCMC1 Macros */
573	#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
574	/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
575	#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
576
577	/SPORTx_MCMC2 Masks /
578	#define MCCRM 0x00000003 /Multichannel Clock Recovery Mode /
579	#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
580	#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
581	#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
582	#define MCDTXPE 0x00000004 /Multichannel DMA Transmit Packing /
583	#define MCDRXPE 0x00000008 /Multichannel DMA Receive Packing /
584	#define MCMEN 0x00000010 /Multichannel Frame Mode Enable /
585	#define FSDR 0x00000080 /Multichannel Frame Sync to Data Relationship /
586	#define MFD 0x0000F000 /Multichannel Frame Delay /
587	#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
588	#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
589	#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
590	#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
591	#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
592	#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
593	#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
594	#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
595	#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
596	#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
597	#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
598	#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
599	#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
600	#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
601	#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
602	#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
603
604	/* ******* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ************** */	512	/* ******* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ************** */
605		513
606	/* PPI_CONTROL Masks */	514	/* PPI_CONTROL Masks */

arch/blackfin/mach-bf537/include/mach/defBF534.h+0−80

@@ -1241,86 +1241,6 @@ · 1240 unmodified lines
1241	#define PH14 0x4000	1241	#define PH14 0x4000
1242	#define PH15 0x8000	1242	#define PH15 0x8000
1243		1243
1244	/* ***************** SERIAL PORT MASKS ************************************/
1245	/* SPORTx_TCR1 Masks */
1246	#define TSPEN 0x0001 /* Transmit Enable */
1247	#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1248	#define DTYPE_NORM 0x0004 /* Data Format Normal */
1249	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1250	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1251	#define TLSBIT 0x0010 /* Transmit Bit Order */
1252	#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1253	#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1254	#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1255	#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1256	#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1257	#define TCKFE 0x4000 /* Clock Falling Edge Select */
1258
1259	/* SPORTx_TCR2 Masks and Macro */
1260	#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1261	#define TXSE 0x0100 /* TX Secondary Enable */
1262	#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1263	#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1264
1265	/* SPORTx_RCR1 Masks */
1266	#define RSPEN 0x0001 /* Receive Enable */
1267	#define IRCLK 0x0002 /* Internal Receive Clock Select */
1268	#define DTYPE_NORM 0x0004 /* Data Format Normal */
1269	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1270	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1271	#define RLSBIT 0x0010 /* Receive Bit Order */
1272	#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1273	#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1274	#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1275	#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1276	#define RCKFE 0x4000 /* Clock Falling Edge Select */
1277
1278	/* SPORTx_RCR2 Masks */
1279	#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1280	#define RXSE 0x0100 /* RX Secondary Enable */
1281	#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1282	#define RRFST 0x0400 /* Right-First Data Order */
1283
1284	/* SPORTx_STAT Masks */
1285	#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1286	#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1287	#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1288	#define TXF 0x0008 /* Transmit FIFO Full Status */
1289	#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1290	#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1291	#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1292
1293	/* SPORTx_MCMC1 Macros */
1294	#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1295
1296	/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1297	#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1298
1299	/* SPORTx_MCMC2 Masks */
1300	#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1301	#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1302	#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1303	#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1304	#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1305	#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1306	#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1307	#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1308	#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1309	#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1310	#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1311	#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1312	#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1313	#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1314	#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1315	#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1316	#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1317	#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1318	#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1319	#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1320	#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1321	#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1322	#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1323
1324	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/	1244	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/
1325	/* EBIU_AMGCTL Masks */	1245	/* EBIU_AMGCTL Masks */
1326	#define AMCKEN 0x0001 /* Enable CLKOUT */	1246	#define AMCKEN 0x0001 /* Enable CLKOUT */

arch/blackfin/mach-bf538/include/mach/defBF539.h+0−107

@@ -1610,113 +1610,6 @@ · 1609 unmodified lines
1610	#define UCEN_P 0x00	1610	#define UCEN_P 0x00
1611		1611
1612		1612
1613	/* ******** SERIAL PORT MASKS ******************** */
1614	/* SPORTx_TCR1 Masks */
1615	#define TSPEN 0x0001 /* TX enable */
1616	#define ITCLK 0x0002 /* Internal TX Clock Select */
1617	#define TDTYPE 0x000C /* TX Data Formatting Select */
1618	#define DTYPE_NORM 0x0000 /* Data Format Normal */
1619	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1620	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1621	#define TLSBIT 0x0010 /* TX Bit Order */
1622	#define ITFS 0x0200 /* Internal TX Frame Sync Select */
1623	#define TFSR 0x0400 /* TX Frame Sync Required Select */
1624	#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
1625	#define LTFS 0x1000 /* Low TX Frame Sync Select */
1626	#define LATFS 0x2000 /* Late TX Frame Sync Select */
1627	#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
1628	/* SPORTx_RCR1 Deprecated Masks */
1629	#define TULAW DTYPE_ULAW /* Compand Using u-Law */
1630	#define TALAW DTYPE_ALAW /* Compand Using A-Law */
1631
1632	/* SPORTx_TCR2 Masks */
1633	#ifdef _MISRA_RULES
1634	#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
1635	#else
1636	#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1637	#endif /* _MISRA_RULES */
1638	#define TXSE 0x0100 /TX Secondary Enable /
1639	#define TSFSE 0x0200 /TX Stereo Frame Sync Enable /
1640	#define TRFST 0x0400 /TX Right-First Data Order /
1641
1642	/* SPORTx_RCR1 Masks */
1643	#define RSPEN 0x0001 /* RX enable */
1644	#define IRCLK 0x0002 /* Internal RX Clock Select */
1645	#define RDTYPE 0x000C /* RX Data Formatting Select */
1646	#define DTYPE_NORM 0x0000 /* no companding */
1647	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1648	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1649	#define RLSBIT 0x0010 /* RX Bit Order */
1650	#define IRFS 0x0200 /* Internal RX Frame Sync Select */
1651	#define RFSR 0x0400 /* RX Frame Sync Required Select */
1652	#define LRFS 0x1000 /* Low RX Frame Sync Select */
1653	#define LARFS 0x2000 /* Late RX Frame Sync Select */
1654	#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
1655	/* SPORTx_RCR1 Deprecated Masks */
1656	#define RULAW DTYPE_ULAW /* Compand Using u-Law */
1657	#define RALAW DTYPE_ALAW /* Compand Using A-Law */
1658
1659	/* SPORTx_RCR2 Masks */
1660	#ifdef _MISRA_RULES
1661	#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
1662	#else
1663	#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1664	#endif /* _MISRA_RULES */
1665	#define RXSE 0x0100 /RX Secondary Enable /
1666	#define RSFSE 0x0200 /RX Stereo Frame Sync Enable /
1667	#define RRFST 0x0400 /Right-First Data Order /
1668
1669	/SPORTx_STAT Masks /
1670	#define RXNE 0x0001 /RX FIFO Not Empty Status /
1671	#define RUVF 0x0002 /RX Underflow Status /
1672	#define ROVF 0x0004 /RX Overflow Status /
1673	#define TXF 0x0008 /TX FIFO Full Status /
1674	#define TUVF 0x0010 /TX Underflow Status /
1675	#define TOVF 0x0020 /TX Overflow Status /
1676	#define TXHRE 0x0040 /TX Hold Register Empty /
1677
1678	/SPORTx_MCMC1 Masks /
1679	#define WOFF 0x000003FF /Multichannel Window Offset Field /
1680	/* SPORTx_MCMC1 Macros */
1681	#ifdef _MISRA_RULES
1682	#define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
1683	/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
1684	#define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1685	#else
1686	#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1687	/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
1688	#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1689	#endif /* _MISRA_RULES */
1690
1691
1692	/SPORTx_MCMC2 Masks /
1693	#define MCCRM 0x0003 /Multichannel Clock Recovery Mode /
1694	#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1695	#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1696	#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1697	#define MCDTXPE 0x0004 /Multichannel DMA Transmit Packing /
1698	#define MCDRXPE 0x0008 /Multichannel DMA Receive Packing /
1699	#define MCMEN 0x0010 /Multichannel Frame Mode Enable /
1700	#define FSDR 0x0080 /Multichannel Frame Sync to Data Relationship /
1701	#define MFD 0xF000 /Multichannel Frame Delay /
1702	#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1703	#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1704	#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1705	#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1706	#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1707	#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1708	#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1709	#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1710	#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1711	#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1712	#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1713	#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1714	#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1715	#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1716	#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1717	#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1718
1719
1720	/* ******* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ************** */	1613	/* ******* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ************** */
1721	/* PPI_CONTROL Masks */	1614	/* PPI_CONTROL Masks */
1722	#define PORT_EN 0x0001 /* PPI Port Enable */	1615	#define PORT_EN 0x0001 /* PPI Port Enable */

arch/blackfin/mach-bf548/boards/cm_bf548.c+0−1

@@ -706,7 +706,6 @@ static struct mtd_partition partition_info[] = { · 705 unmodified lines
706	};	706	};
707		707
708	static struct bf5xx_nand_platform bf5xx_nand_platform = {	708	static struct bf5xx_nand_platform bf5xx_nand_platform = {
709	.page_size = NFC_PG_SIZE_256,
710	.data_width = NFC_NWIDTH_8,	709	.data_width = NFC_NWIDTH_8,
711	.partitions = partition_info,	710	.partitions = partition_info,
712	.nr_partitions = ARRAY_SIZE(partition_info),	711	.nr_partitions = ARRAY_SIZE(partition_info),

arch/blackfin/mach-bf548/boards/ezkit.c+0−1

@@ -849,7 +849,6 @@ static struct mtd_partition partition_info[] = { · 848 unmodified lines
849	};	849	};
850		850
851	static struct bf5xx_nand_platform bf5xx_nand_platform = {	851	static struct bf5xx_nand_platform bf5xx_nand_platform = {
852	.page_size = NFC_PG_SIZE_256,
853	.data_width = NFC_NWIDTH_8,	852	.data_width = NFC_NWIDTH_8,
854	.partitions = partition_info,	853	.partitions = partition_info,
855	.nr_partitions = ARRAY_SIZE(partition_info),	854	.nr_partitions = ARRAY_SIZE(partition_info),

arch/blackfin/mach-bf548/include/mach/defBF54x_base.h+0−67

@@ -2221,73 +2221,6 @@ · 2220 unmodified lines
2221		2221
2222	#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */	2222	#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2223		2223
2224	/* Bit masks for SPORTx_TCR1 */
2225
2226	#define TCKFE 0x4000 /* Clock Falling Edge Select */
2227	#define LATFS 0x2000 /* Late Transmit Frame Sync */
2228	#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
2229	#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
2230	#define TFSR 0x400 /* Transmit Frame Sync Required Select */
2231	#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
2232	#define TLSBIT 0x10 /* Transmit Bit Order */
2233	#define TDTYPE 0xc /* Data Formatting Type Select */
2234	#define ITCLK 0x2 /* Internal Transmit Clock Select */
2235	#define TSPEN 0x1 /* Transmit Enable */
2236
2237	/* Bit masks for SPORTx_TCR2 */
2238
2239	#define TRFST 0x400 /* Left/Right Order */
2240	#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
2241	#define TXSE 0x100 /* TxSEC Enable */
2242	#define SLEN_T 0x1f /* SPORT Word Length */
2243
2244	/* Bit masks for SPORTx_RCR1 */
2245
2246	#define RCKFE 0x4000 /* Clock Falling Edge Select */
2247	#define LARFS 0x2000 /* Late Receive Frame Sync */
2248	#define LRFS 0x1000 /* Low Receive Frame Sync Select */
2249	#define RFSR 0x400 /* Receive Frame Sync Required Select */
2250	#define IRFS 0x200 /* Internal Receive Frame Sync Select */
2251	#define RLSBIT 0x10 /* Receive Bit Order */
2252	#define RDTYPE 0xc /* Data Formatting Type Select */
2253	#define IRCLK 0x2 /* Internal Receive Clock Select */
2254	#define RSPEN 0x1 /* Receive Enable */
2255
2256	/* Bit masks for SPORTx_RCR2 */
2257
2258	#define RRFST 0x400 /* Left/Right Order */
2259	#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
2260	#define RXSE 0x100 /* RxSEC Enable */
2261	#define SLEN_R 0x1f /* SPORT Word Length */
2262
2263	/* Bit masks for SPORTx_STAT */
2264
2265	#define TXHRE 0x40 /* Transmit Hold Register Empty */
2266	#define TOVF 0x20 /* Sticky Transmit Overflow Status */
2267	#define TUVF 0x10 /* Sticky Transmit Underflow Status */
2268	#define TXF 0x8 /* Transmit FIFO Full Status */
2269	#define ROVF 0x4 /* Sticky Receive Overflow Status */
2270	#define RUVF 0x2 /* Sticky Receive Underflow Status */
2271	#define RXNE 0x1 /* Receive FIFO Not Empty Status */
2272
2273	/* Bit masks for SPORTx_MCMC1 */
2274
2275	#define SP_WSIZE 0xf000 /* Window Size */
2276	#define SP_WOFF 0x3ff /* Windows Offset */
2277
2278	/* Bit masks for SPORTx_MCMC2 */
2279
2280	#define MFD 0xf000 /* Multi channel Frame Delay */
2281	#define FSDR 0x80 /* Frame Sync to Data Relationship */
2282	#define MCMEN 0x10 /* Multi channel Frame Mode Enable */
2283	#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
2284	#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
2285	#define MCCRM 0x3 /* 2X Clock Recovery Mode */
2286
2287	/* Bit masks for SPORTx_CHNL */
2288
2289	#define CUR_CHNL 0x3ff /* Current Channel Indicator */
2290
2291	/* Bit masks for UARTx_LCR */	2224	/* Bit masks for UARTx_LCR */
2292		2225
2293	#if 0	2226	#if 0

arch/blackfin/mach-bf561/include/mach/defBF561.h+0−60

@@ -1007,66 +1007,6 @@ · 1006 unmodified lines
1007	#define IREN_P 0x01	1007	#define IREN_P 0x01
1008	#define UCEN_P 0x00	1008	#define UCEN_P 0x00
1009		1009
1010	/* ******** SERIAL PORT MASKS ******************** */
1011
1012	/* SPORTx_TCR1 Masks */
1013	#define TSPEN 0x0001 /* TX enable */
1014	#define ITCLK 0x0002 /* Internal TX Clock Select */
1015	#define TDTYPE 0x000C /* TX Data Formatting Select */
1016	#define TLSBIT 0x0010 /* TX Bit Order */
1017	#define ITFS 0x0200 /* Internal TX Frame Sync Select */
1018	#define TFSR 0x0400 /* TX Frame Sync Required Select */
1019	#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
1020	#define LTFS 0x1000 /* Low TX Frame Sync Select */
1021	#define LATFS 0x2000 /* Late TX Frame Sync Select */
1022	#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
1023
1024	/* SPORTx_TCR2 Masks */
1025	#define SLEN 0x001F /TX Word Length /
1026	#define TXSE 0x0100 /TX Secondary Enable /
1027	#define TSFSE 0x0200 /TX Stereo Frame Sync Enable /
1028	#define TRFST 0x0400 /TX Right-First Data Order /
1029
1030	/* SPORTx_RCR1 Masks */
1031	#define RSPEN 0x0001 /* RX enable */
1032	#define IRCLK 0x0002 /* Internal RX Clock Select */
1033	#define RDTYPE 0x000C /* RX Data Formatting Select */
1034	#define RULAW 0x0008 /* u-Law enable */
1035	#define RALAW 0x000C /* A-Law enable */
1036	#define RLSBIT 0x0010 /* RX Bit Order */
1037	#define IRFS 0x0200 /* Internal RX Frame Sync Select */
1038	#define RFSR 0x0400 /* RX Frame Sync Required Select */
1039	#define LRFS 0x1000 /* Low RX Frame Sync Select */
1040	#define LARFS 0x2000 /* Late RX Frame Sync Select */
1041	#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
1042
1043	/* SPORTx_RCR2 Masks */
1044	#define SLEN 0x001F /RX Word Length /
1045	#define RXSE 0x0100 /RX Secondary Enable /
1046	#define RSFSE 0x0200 /RX Stereo Frame Sync Enable /
1047	#define RRFST 0x0400 /Right-First Data Order /
1048
1049	/SPORTx_STAT Masks /
1050	#define RXNE 0x0001 /RX FIFO Not Empty Status /
1051	#define RUVF 0x0002 /RX Underflow Status /
1052	#define ROVF 0x0004 /RX Overflow Status /
1053	#define TXF 0x0008 /TX FIFO Full Status /
1054	#define TUVF 0x0010 /TX Underflow Status /
1055	#define TOVF 0x0020 /TX Overflow Status /
1056	#define TXHRE 0x0040 /TX Hold Register Empty /
1057
1058	/SPORTx_MCMC1 Masks /
1059	#define SP_WSIZE 0x0000F000 /Multichannel Window Size Field /
1060	#define SP_WOFF 0x000003FF /Multichannel Window Offset Field /
1061
1062	/SPORTx_MCMC2 Masks /
1063	#define MCCRM 0x00000003 /Multichannel Clock Recovery Mode /
1064	#define MCDTXPE 0x00000004 /Multichannel DMA Transmit Packing /
1065	#define MCDRXPE 0x00000008 /Multichannel DMA Receive Packing /
1066	#define MCMEN 0x00000010 /Multichannel Frame Mode Enable /
1067	#define FSDR 0x00000080 /Multichannel Frame Sync to Data Relationship /
1068	#define MFD 0x0000F000 /Multichannel Frame Delay /
1069
1070	/* ******* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ************** */	1010	/* ******* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ************** */
1071		1011
1072	/* PPI_CONTROL Masks */	1012	/* PPI_CONTROL Masks */

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin

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