lael-labs/linux

Makefile+1−1

@@ -1,7 +1,7 @@
1	VERSION = 4	1	VERSION = 4
2	PATCHLEVEL = 7	2	PATCHLEVEL = 7
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc5	4	EXTRAVERSION = -rc6
5	NAME = Psychotic Stoned Sheep	5	NAME = Psychotic Stoned Sheep
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION

arch/arc/Makefile+0−2

@@ -66,8 +66,6 @@ endif · 65 unmodified lines
66		66
67	endif	67	endif
68		68
69	cflags-$(CONFIG_ARC_DW2_UNWIND) += -fasynchronous-unwind-tables
70
71	# By default gcc 4.8 generates dwarf4 which kernel unwinder can't grok	69	# By default gcc 4.8 generates dwarf4 which kernel unwinder can't grok
72	ifeq ($(atleast_gcc48),y)	70	ifeq ($(atleast_gcc48),y)
73	cflags-$(CONFIG_ARC_DW2_UNWIND) += -gdwarf-2	71	cflags-$(CONFIG_ARC_DW2_UNWIND) += -gdwarf-2

arch/arc/kernel/stacktrace.c+1−1

@@ -142,7 +142,7 @@ arc_unwind_core(struct task_struct tsk, struct pt_regs regs, · 141 unmodified lines
142	* prelogue is setup (callee regs saved and then fp set and not other	142	* prelogue is setup (callee regs saved and then fp set and not other
143	* way around	143	* way around
144	*/	144	*/
145	pr_warn("CONFIG_ARC_DW2_UNWIND needs to be enabled\n");	145	pr_warn_once("CONFIG_ARC_DW2_UNWIND needs to be enabled\n");
146	return 0;	146	return 0;
147		147
148	#endif	148	#endif

arch/arm/kvm/arm.c+1−0

@@ -263,6 +263,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) · 262 unmodified lines
263	kvm_timer_vcpu_terminate(vcpu);	263	kvm_timer_vcpu_terminate(vcpu);
264	kvm_vgic_vcpu_destroy(vcpu);	264	kvm_vgic_vcpu_destroy(vcpu);
265	kvm_pmu_vcpu_destroy(vcpu);	265	kvm_pmu_vcpu_destroy(vcpu);
		266	kvm_vcpu_uninit(vcpu);
266	kmem_cache_free(kvm_vcpu_cache, vcpu);	267	kmem_cache_free(kvm_vcpu_cache, vcpu);
267	}	268	}
268		269

arch/mips/include/asm/pgtable.h+6−4

 struct vm_area_struct;
 #define PAGE_NONE	__pgprot(_PAGE_PRESENT | _PAGE_NO_READ | \
-				 _CACHE_CACHABLE_NONCOHERENT)
+				 _page_cachable_default)
 #define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
 				 _page_cachable_default)
 #define PAGE_COPY	__pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | \
 	pte.pte_low  &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
 	pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
 	pte.pte_low  |= pgprot_val(newprot) & ~_PFNX_MASK;
-	pte.pte_high |= pgprot_val(newprot) & ~_PFN_MASK;
+	pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
 	return pte;
 }
 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
 #else
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+	return __pte((pte_val(pte) & _PAGE_CHG_MASK) |
+		     (pgprot_val(newprot) & ~_PAGE_CHG_MASK));
 }
 #endif
 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
 {
-	pmd_val(pmd) = (pmd_val(pmd) & _PAGE_CHG_MASK) | pgprot_val(newprot);
+	pmd_val(pmd) = (pmd_val(pmd) & _PAGE_CHG_MASK) |
+		       (pgprot_val(newprot) & ~_PAGE_CHG_MASK);
 	return pmd;
 }

arch/powerpc/include/asm/book3s/64/pgtable.h+1−0

@@ -230,6 +230,7 @@ extern unsigned long __kernel_virt_size; · 229 unmodified lines
230	#define KERN_VIRT_SIZE __kernel_virt_size	230	#define KERN_VIRT_SIZE __kernel_virt_size
231	extern struct page *vmemmap;	231	extern struct page *vmemmap;
232	extern unsigned long ioremap_bot;	232	extern unsigned long ioremap_bot;
		233	extern unsigned long pci_io_base;
233	#endif /* __ASSEMBLY__ */	234	#endif /* __ASSEMBLY__ */
234		235
235	#include <asm/book3s/64/hash.h>	236	#include <asm/book3s/64/hash.h>

arch/powerpc/kernel/eeh_driver.c+1−1

@@ -647,7 +647,7 @@ static int eeh_reset_device(struct eeh_pe pe, struct pci_bus bus, · 646 unmodified lines
647	pci_unlock_rescan_remove();	647	pci_unlock_rescan_remove();
648	}	648	}
649	} else if (frozen_bus) {	649	} else if (frozen_bus) {
650	eeh_pe_dev_traverse(pe, eeh_rmv_device, &rmv_data);	650	eeh_pe_dev_traverse(pe, eeh_rmv_device, rmv_data);
651	}	651	}
652		652
653	/*	653	/*

arch/powerpc/kernel/pci_64.c+0−1

@@ -47,7 +47,6 @@ static int __init pcibios_init(void) · 46 unmodified lines
47		47
48	printk(KERN_INFO "PCI: Probing PCI hardware\n");	48	printk(KERN_INFO "PCI: Probing PCI hardware\n");
49		49
50	pci_io_base = ISA_IO_BASE;
51	/* For now, override phys_mem_access_prot. If we need it,g	50	/* For now, override phys_mem_access_prot. If we need it,g
52	* later, we may move that initialization to each ppc_md	51	* later, we may move that initialization to each ppc_md
53	*/	52	*/

arch/powerpc/kernel/process.c+10−0

@@ -1505,6 +1505,16 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) · 1504 unmodified lines
1505	current->thread.regs = regs - 1;	1505	current->thread.regs = regs - 1;
1506	}	1506	}
1507		1507
		1508	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
		1509	/*
		1510	* Clear any transactional state, we're exec()ing. The cause is
		1511	* not important as there will never be a recheckpoint so it's not
		1512	* user visible.
		1513	*/
		1514	if (MSR_TM_SUSPENDED(mfmsr()))
		1515	tm_reclaim_current(0);
		1516	#endif
		1517
1508	memset(regs->gpr, 0, sizeof(regs->gpr));	1518	memset(regs->gpr, 0, sizeof(regs->gpr));
1509	regs->ctr = 0;	1519	regs->ctr = 0;
1510	regs->link = 0;	1520	regs->link = 0;

arch/powerpc/kernel/tm.S+44−17

@@ -110,17 +110,11 @@ _GLOBAL(tm_reclaim) · 109 unmodified lines
110	std r3, STK_PARAM(R3)(r1)	110	std r3, STK_PARAM(R3)(r1)
111	SAVE_NVGPRS(r1)	111	SAVE_NVGPRS(r1)
112		112
113	/* We need to setup MSR for VSX register save instructions. Here we	113	/* We need to setup MSR for VSX register save instructions. */
114	* also clear the MSR RI since when we do the treclaim, we won't have a
115	* valid kernel pointer for a while. We clear RI here as it avoids
116	* adding another mtmsr closer to the treclaim. This makes the region
117	* maked as non-recoverable wider than it needs to be but it saves on
118	* inserting another mtmsrd later.
119	*/
120	mfmsr r14	114	mfmsr r14
121	mr r15, r14	115	mr r15, r14
122	ori r15, r15, MSR_FP	116	ori r15, r15, MSR_FP
123	li r16, MSR_RI	117	li r16, 0
124	ori r16, r16, MSR_EE /* IRQs hard off */	118	ori r16, r16, MSR_EE /* IRQs hard off */
125	andc r15, r15, r16	119	andc r15, r15, r16
126	oris r15, r15, MSR_VEC@h	120	oris r15, r15, MSR_VEC@h
@@ -176,7 +170,17 @@ dont_backup_fp: · 49 unmodified lines
176	1: tdeqi r6, 0	170	1: tdeqi r6, 0
177	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0	171	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
178		172
179	/* The moment we treclaim, ALL of our GPRs will switch	173	/* Clear MSR RI since we are about to change r1, EE is already off. */
		174	li r4, 0
		175	mtmsrd r4, 1
		176
		177	/*
		178	* BE CAREFUL HERE:
		179	* At this point we can't take an SLB miss since we have MSR_RI
		180	* off. Load only to/from the stack/paca which are in SLB bolted regions
		181	* until we turn MSR RI back on.
		182	*
		183	* The moment we treclaim, ALL of our GPRs will switch
180	* to user register state. (FPRs, CCR etc. also!)	184	* to user register state. (FPRs, CCR etc. also!)
181	* Use an sprg and a tm_scratch in the PACA to shuffle.	185	* Use an sprg and a tm_scratch in the PACA to shuffle.
182	*/	186	*/
@@ -197,6 +201,11 @@ dont_backup_fp: · 14 unmodified lines
197		201
198	/* Store the PPR in r11 and reset to decent value */	202	/* Store the PPR in r11 and reset to decent value */
199	std r11, GPR11(r1) /* Temporary stash */	203	std r11, GPR11(r1) /* Temporary stash */
		204
		205	/* Reset MSR RI so we can take SLB faults again */
		206	li r11, MSR_RI
		207	mtmsrd r11, 1
		208
200	mfspr r11, SPRN_PPR	209	mfspr r11, SPRN_PPR
201	HMT_MEDIUM	210	HMT_MEDIUM
202		211
@@ -397,11 +406,6 @@ restore_gprs: · 194 unmodified lines
397	ld r5, THREAD_TM_DSCR(r3)	406	ld r5, THREAD_TM_DSCR(r3)
398	ld r6, THREAD_TM_PPR(r3)	407	ld r6, THREAD_TM_PPR(r3)
399		408
400	/* Clear the MSR RI since we are about to change R1. EE is already off
401	*/
402	li r4, 0
403	mtmsrd r4, 1
404
405	REST_GPR(0, r7) /* GPR0 */	409	REST_GPR(0, r7) /* GPR0 */
406	REST_2GPRS(2, r7) /* GPR2-3 */	410	REST_2GPRS(2, r7) /* GPR2-3 */
407	REST_GPR(4, r7) /* GPR4 */	411	REST_GPR(4, r7) /* GPR4 */
@@ -439,10 +443,33 @@ restore_gprs: · 31 unmodified lines
439	ld r6, _CCR(r7)	443	ld r6, _CCR(r7)
440	mtcr r6	444	mtcr r6
441		445
442	REST_GPR(1, r7) /* GPR1 */
443	REST_GPR(5, r7) /* GPR5-7 */
444	REST_GPR(6, r7)	446	REST_GPR(6, r7)
445	ld r7, GPR7(r7)	447
		448	/*
		449	* Store r1 and r5 on the stack so that we can access them
		450	* after we clear MSR RI.
		451	*/
		452
		453	REST_GPR(5, r7)
		454	std r5, -8(r1)
		455	ld r5, GPR1(r7)
		456	std r5, -16(r1)
		457
		458	REST_GPR(7, r7)
		459
		460	/* Clear MSR RI since we are about to change r1. EE is already off */
		461	li r5, 0
		462	mtmsrd r5, 1
		463
		464	/*
		465	* BE CAREFUL HERE:
		466	* At this point we can't take an SLB miss since we have MSR_RI
		467	* off. Load only to/from the stack/paca which are in SLB bolted regions
		468	* until we turn MSR RI back on.
		469	*/
		470
		471	ld r5, -8(r1)
		472	ld r1, -16(r1)
446		473
447	/* Commit register state as checkpointed state: */	474	/* Commit register state as checkpointed state: */
448	TRECHKPT	475	TRECHKPT

arch/powerpc/mm/hash_utils_64.c+4−0

 	vmemmap = (struct page *)H_VMEMMAP_BASE;
 	ioremap_bot = IOREMAP_BASE;
+#ifdef CONFIG_PCI
+	pci_io_base = ISA_IO_BASE;
+#endif
 	/* Initialize the MMU Hash table and create the linear mapping
 	 * of memory. Has to be done before SLB initialization as this is
 	 * currently where the page size encoding is obtained.

arch/powerpc/mm/pgtable-radix.c+5−0

 	__vmalloc_end = RADIX_VMALLOC_END;
 	vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
 	ioremap_bot = IOREMAP_BASE;
+#ifdef CONFIG_PCI
+	pci_io_base = ISA_IO_BASE;
+#endif
 	/*
 	 * For now radix also use the same frag size
 	 */

arch/x86/include/asm/pvclock.h+9−16

@@ -68,30 +68,23 @@ static inline u64 pvclock_scale_delta(u64 delta, u32 mul_frac, int shift) · 67 unmodified lines
68	return product;	68	return product;
69	}	69	}
70		70
71	static __always_inline
72	u64 pvclock_get_nsec_offset(const struct pvclock_vcpu_time_info *src)
73	{
74	u64 delta = rdtsc_ordered() - src->tsc_timestamp;
75	return pvclock_scale_delta(delta, src->tsc_to_system_mul,
76	src->tsc_shift);
77	}
78
79	static __always_inline	71	static __always_inline
80	unsigned __pvclock_read_cycles(const struct pvclock_vcpu_time_info *src,	72	unsigned __pvclock_read_cycles(const struct pvclock_vcpu_time_info *src,
81	cycle_t cycles, u8 flags)	73	cycle_t cycles, u8 flags)
82	{	74	{
83	unsigned version;	75	unsigned version;
84	cycle_t ret, offset;	76	cycle_t offset;
85	u8 ret_flags;	77	u64 delta;
86		78
87	version = src->version;	79	version = src->version;
		80	/* Make the latest version visible */
		81	smp_rmb();
88		82
89	offset = pvclock_get_nsec_offset(src);	83	delta = rdtsc_ordered() - src->tsc_timestamp;
90	ret = src->system_time + offset;	84	offset = pvclock_scale_delta(delta, src->tsc_to_system_mul,
91	ret_flags = src->flags;	85	src->tsc_shift);
92		86	*cycles = src->system_time + offset;
93	*cycles = ret;	87	*flags = src->flags;
94	*flags = ret_flags;
95	return version;	88	return version;
96	}	89	}
97		90

arch/x86/kernel/pvclock.c+9−2

 u8 pvclock_read_flags(struct pvclock_vcpu_time_info *src)
 {
 	unsigned version;
-	cycle_t ret;
 	u8 flags;
 	do {
-		version = __pvclock_read_cycles(src, &ret, &flags);
+		version = src->version;
+		/* Make the latest version visible */
+		smp_rmb();
+		flags = src->flags;
+		/* Make sure that the version double-check is last. */
+		smp_rmb();
 	} while ((src->version & 1) || version != src->version);
 	return flags & valid_flags;
 	do {
 		version = __pvclock_read_cycles(src, &ret, &flags);
+		/* Make sure that the version double-check is last. */
+		smp_rmb();
 	} while ((src->version & 1) || version != src->version);
 	if (unlikely((flags & PVCLOCK_GUEST_STOPPED) != 0)) {

arch/x86/kvm/lapic.c+2−1

@@ -1310,7 +1310,8 @@ void wait_lapic_expire(struct kvm_vcpu *vcpu) · 1309 unmodified lines
1310		1310
1311	/* __delay is delay_tsc whenever the hardware has TSC, thus always. */	1311	/* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1312	if (guest_tsc < tsc_deadline)	1312	if (guest_tsc < tsc_deadline)
1313	__delay(tsc_deadline - guest_tsc);	1313	__delay(min(tsc_deadline - guest_tsc,
		1314	nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1314	}	1315	}
1315		1316
1316	static void start_apic_timer(struct kvm_lapic *apic)	1317	static void start_apic_timer(struct kvm_lapic *apic)

arch/x86/kvm/vmx.c+11−12

 	/* Checks for #GP/#SS exceptions. */
 	exn = false;
-	if (is_protmode(vcpu)) {
+	if (is_long_mode(vcpu)) {
+		/* Long mode: #GP(0)/#SS(0) if the memory address is in a
+		 * non-canonical form. This is the only check on the memory
+		 * destination for long mode!
+		 */
+		exn = is_noncanonical_address(*ret);
+	} else if (is_protmode(vcpu)) {
 		/* Protected mode: apply checks for segment validity in the
 		 * following order:
 		 * - segment type check (#GP(0) may be thrown)
 			 * execute-only code segment
 			 */
 			exn = ((s.type & 0xa) == 8);
-	}
+		if (exn) {
-	if (exn) {
+			kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
-		kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
+			return 1;
-		return 1;
+		}
-	}
-	if (is_long_mode(vcpu)) {
-		/* Long mode: #GP(0)/#SS(0) if the memory address is in a
-		 * non-canonical form. This is an only check for long mode.
-		 */
-		exn = is_noncanonical_address(*ret);
-	} else if (is_protmode(vcpu)) {
 		/* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
 		 */
 		exn = (s.unusable != 0);

arch/x86/kvm/x86.c+0−6

 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
 static unsigned long max_tsc_khz;
-static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
-{
-	return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
-				   vcpu->arch.virtual_tsc_shift);
-}
 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
 {
 	u64 v = (u64)khz * (1000000 + ppm);

arch/x86/kvm/x86.h+7−0

 #define ARCH_X86_KVM_X86_H
 #include <linux/kvm_host.h>
+#include <asm/pvclock.h>
 #include "kvm_cache_regs.h"
 #define MSR_IA32_CR_PAT_DEFAULT  0x0007040600070406ULL
 extern struct static_key kvm_no_apic_vcpu;
+static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
+{
+	return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
+				   vcpu->arch.virtual_tsc_shift);
+}
 /* Same "calling convention" as do_div:
  * - divide (n << 32) by base
  * - put result in n

drivers/acpi/nfit.c+6−6

@@ -928,7 +928,7 @@ static ssize_t format_show(struct device *dev, · 927 unmodified lines
928	{	928	{
929	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);	929	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
930		930
931	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->code));	931	return sprintf(buf, "0x%04x\n", le16_to_cpu(dcr->code));
932	}	932	}
933	static DEVICE_ATTR_RO(format);	933	static DEVICE_ATTR_RO(format);
934		934
@@ -961,8 +961,8 @@ static ssize_t format1_show(struct device *dev, · 26 unmodified lines
961	continue;	961	continue;
962	if (nfit_dcr->dcr->code == dcr->code)	962	if (nfit_dcr->dcr->code == dcr->code)
963	continue;	963	continue;
964	rc = sprintf(buf, "%#x\n",	964	rc = sprintf(buf, "0x%04x\n",
965	be16_to_cpu(nfit_dcr->dcr->code));	965	le16_to_cpu(nfit_dcr->dcr->code));
966	break;	966	break;
967	}	967	}
968	if (rc != ENXIO)	968	if (rc != ENXIO)
@@ -1131,11 +1131,11 @@ static int acpi_nfit_add_dimm(struct acpi_nfit_desc *acpi_desc, · 162 unmodified lines
1131		1131
1132	/*	1132	/*
1133	* Until standardization materializes we need to consider up to 3	1133	* Until standardization materializes we need to consider up to 3
1134	* different command sets. Note, that checking for function0 (bit0)	1134	* different command sets. Note, that checking for zero functions
1135	* tells us if any commands are reachable through this uuid.	1135	* tells us if any commands might be reachable through this uuid.
1136	*/	1136	*/
1137	for (i = NVDIMM_FAMILY_INTEL; i <= NVDIMM_FAMILY_HPE2; i++)	1137	for (i = NVDIMM_FAMILY_INTEL; i <= NVDIMM_FAMILY_HPE2; i++)
1138	if (acpi_check_dsm(adev_dimm->handle, to_nfit_uuid(i), 1, 1))	1138	if (acpi_check_dsm(adev_dimm->handle, to_nfit_uuid(i), 1, 0))
1139	break;	1139	break;
1140		1140
1141	/* limit the supported commands to those that are publicly documented */	1141	/* limit the supported commands to those that are publicly documented */

drivers/acpi/nfit.h+5−5

@@ -53,12 +53,12 @@ enum nfit_uuids { · 52 unmodified lines
53	};	53	};
54		54
55	/*	55	/*
56	* Region format interface codes are stored as an array of bytes in the	56	* Region format interface codes are stored with the interface as the
57	* NFIT DIMM Control Region structure	57	* LSB and the function as the MSB.
58	*/	58	*/
59	#define NFIT_FIC_BYTE cpu_to_be16(0x101) /* byte-addressable energy backed */	59	#define NFIT_FIC_BYTE cpu_to_le16(0x101) /* byte-addressable energy backed */
60	#define NFIT_FIC_BLK cpu_to_be16(0x201) /* block-addressable non-energy backed */	60	#define NFIT_FIC_BLK cpu_to_le16(0x201) /* block-addressable non-energy backed */
61	#define NFIT_FIC_BYTEN cpu_to_be16(0x301) /* byte-addressable non-energy backed */	61	#define NFIT_FIC_BYTEN cpu_to_le16(0x301) /* byte-addressable non-energy backed */
62		62
63	enum {	63	enum {
64	NFIT_BLK_READ_FLUSH = 1,	64	NFIT_BLK_READ_FLUSH = 1,

drivers/acpi/pci_link.c+1−1

@@ -839,7 +839,7 @@ void acpi_penalize_isa_irq(int irq, int active) · 838 unmodified lines
839	{	839	{
840	if ((irq >= 0) && (irq < ARRAY_SIZE(acpi_isa_irq_penalty)))	840	if ((irq >= 0) && (irq < ARRAY_SIZE(acpi_isa_irq_penalty)))
841	acpi_isa_irq_penalty[irq] = acpi_irq_get_penalty(irq) +	841	acpi_isa_irq_penalty[irq] = acpi_irq_get_penalty(irq) +
842	active ? PIRQ_PENALTY_ISA_USED : PIRQ_PENALTY_PCI_USING;	842	(active ? PIRQ_PENALTY_ISA_USED : PIRQ_PENALTY_PCI_USING);
843	}	843	}
844		844
845	bool acpi_isa_irq_available(int irq)	845	bool acpi_isa_irq_available(int irq)

drivers/acpi/utils.c+3−3

 	u64 mask = 0;
 	union acpi_object *obj;
-	if (funcs == 0)
-		return false;
 	obj = acpi_evaluate_dsm(handle, uuid, rev, 0, NULL);
 	if (!obj)
 		return false;
 			mask |= (((u64)obj->buffer.pointer[i]) << (i * 8));
 	ACPI_FREE(obj);
+	if (funcs == 0)
+		return true;
 	/*
 	 * Bit 0 indicates whether there's support for any functions other than
 	 * function 0 for the specified UUID and revision.

drivers/clk/clk-oxnas.c+2−2

@@ -144,9 +144,9 @@ static int oxnas_stdclk_probe(struct platform_device *pdev) · 143 unmodified lines
144	return -ENOMEM;	144	return -ENOMEM;
145		145
146	regmap = syscon_node_to_regmap(of_get_parent(np));	146	regmap = syscon_node_to_regmap(of_get_parent(np));
147	if (!regmap) {	147	if (IS_ERR(regmap)) {
148	dev_err(&pdev->dev, "failed to have parent regmap\n");	148	dev_err(&pdev->dev, "failed to have parent regmap\n");
149	return -EINVAL;	149	return PTR_ERR(regmap);
150	}	150	}
151		151
152	for (i = 0; i < ARRAY_SIZE(clk_oxnas_init); i++) {	152	for (i = 0; i < ARRAY_SIZE(clk_oxnas_init); i++) {

drivers/clk/rockchip/clk-cpu.c+2−2

@@ -321,9 +321,9 @@ struct clk rockchip_clk_register_cpuclk(const char name, · 320 unmodified lines
321	}	321	}
322		322
323	cclk = clk_register(NULL, &cpuclk->hw);	323	cclk = clk_register(NULL, &cpuclk->hw);
324	if (IS_ERR(clk)) {	324	if (IS_ERR(cclk)) {
325	pr_err("%s: could not register cpuclk %s\n", __func__, name);	325	pr_err("%s: could not register cpuclk %s\n", __func__, name);
326	ret = PTR_ERR(clk);	326	ret = PTR_ERR(cclk);
327	goto free_rate_table;	327	goto free_rate_table;
328	}	328	}
329		329

drivers/clk/rockchip/clk-mmc-phase.c+1−11

 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
-#define ROCKCHIP_MMC_INIT_STATE_RESET 0x1
-#define ROCKCHIP_MMC_INIT_STATE_SHIFT 1
 #define PSECS_PER_SEC 1000000000000LL
 		return ERR_PTR(-ENOMEM);
 	init.name = name;
+	init.flags = 0;
 	init.num_parents = num_parents;
 	init.parent_names = parent_names;
 	init.ops = &rockchip_mmc_clk_ops;
 	mmc_clock->reg = reg;
 	mmc_clock->shift = shift;
-	/*
-	 * Assert init_state to soft reset the CLKGEN
-	 * for mmc tuning phase and degree
-	 */
-	if (mmc_clock->shift == ROCKCHIP_MMC_INIT_STATE_SHIFT)
-		writel(HIWORD_UPDATE(ROCKCHIP_MMC_INIT_STATE_RESET,
-				     ROCKCHIP_MMC_INIT_STATE_RESET,
-				     mmc_clock->shift), mmc_clock->reg);
 	clk = clk_register(NULL, &mmc_clock->hw);
 	if (IS_ERR(clk))
 		kfree(mmc_clock);

drivers/clk/rockchip/clk-rk3399.c+6−2

 			RK3399_CLKGATE_CON(13), 1, GFLAGS),
 	/* perihp */
-	GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(5), 0, GFLAGS),
-	GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
+	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(5), 1, GFLAGS),
 	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
 static const char *const rk3399_cru_critical_clocks[] __initconst = {
 	"aclk_cci_pre",
+	"aclk_gic",
+	"aclk_gic_noc",
 	"pclk_perilp0",
 	"pclk_perilp0",
 	"hclk_perilp0",
 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 	if (IS_ERR(ctx)) {
 		pr_err("%s: rockchip clk init failed\n", __func__);
+		iounmap(reg_base);
 		return;
 	}
 	ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
 	if (IS_ERR(ctx)) {
 		pr_err("%s: rockchip pmu clk init failed\n", __func__);
+		iounmap(reg_base);
 		return;
 	}

drivers/cpufreq/cpufreq-dt-platdev.c+4−3

 static int __init cpufreq_dt_platdev_init(void)
 {
 	struct device_node *np = of_find_node_by_path("/");
+	const struct of_device_id *match;
 	if (!np)
 		return -ENODEV;
-	if (!of_match_node(machines, np))
+	match = of_match_node(machines, np);
+	of_node_put(np);
+	if (!match)
 		return -ENODEV;
-	of_node_put(of_root);
 	return PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt", -1,
 							       NULL, 0));
 }

drivers/cpufreq/cpufreq.c+4−0

 	 * -> ask driver for current freq and notify governors about a change
 	 */
 	if (cpufreq_driver->get && !cpufreq_driver->setpolicy) {
+		if (cpufreq_suspended) {
+			ret = -EAGAIN;
+			goto unlock;
+		}
 		new_policy.cur = cpufreq_update_current_freq(policy);
 		if (WARN_ON(!new_policy.cur)) {
 			ret = -EIO;

drivers/cpufreq/intel_pstate.c+3−2

 {
 	struct cpudata *cpu = all_cpu_data[cpu_num];
+	if (cpu->update_util_set)
+		return;
 	/* Prevent intel_pstate_update_util() from using stale data. */
 	cpu->sample.time = 0;
 	cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
 	if (!policy->cpuinfo.max_freq)
 		return -ENODEV;
-	intel_pstate_clear_update_util_hook(policy->cpu);
 	pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
 		 policy->cpuinfo.max_freq, policy->max);

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+4−0

 	if (fences == 0 && handles == 0) {
 		if (adev->pm.dpm_enabled) {
 			amdgpu_dpm_enable_uvd(adev, false);
+			/* just work around for uvd clock remain high even
+			 * when uvd dpm disabled on Polaris10 */
+			if (adev->asic_type == CHIP_POLARIS10)
+				amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 		} else {
 			amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 		}

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+3−0

 #include "dce/dce_10_0_d.h"
 #include "dce/dce_10_0_sh_mask.h"
+#include "smu/smu_7_1_3_d.h"
 #define GFX8_NUM_GFX_RINGS     1
 #define GFX8_NUM_COMPUTE_RINGS 8
 		amdgpu_program_register_sequence(adev,
 						 polaris10_golden_common_all,
 						 (const u32)ARRAY_SIZE(polaris10_golden_common_all));
+		WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
 		break;
 	case CHIP_CARRIZO:
 		amdgpu_program_register_sequence(adev,

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c+124−55

@@ -98,6 +98,7 @@ · 97 unmodified lines
98	#define PCIE_BUS_CLK 10000	98	#define PCIE_BUS_CLK 10000
99	#define TCLK (PCIE_BUS_CLK / 10)	99	#define TCLK (PCIE_BUS_CLK / 10)
100		100
		101	#define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double))
101		102
102	static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =	103	static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103	{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };	104	{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
@@ -1422,22 +1423,19 @@ static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, · 1318 unmodified lines
1422		1423
1423	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;	1424	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1424		1425
1425	if (!data->sclk_dpm_key_disabled) {	1426
1426	/* Get MinVoltage and Frequency from DPM0,	1427	/* Get MinVoltage and Frequency from DPM0,
1427	* already converted to SMC_UL */	1428	* already converted to SMC_UL */
1428	sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;	1429	sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1429	result = polaris10_get_dependency_volt_by_clk(hwmgr,	1430	result = polaris10_get_dependency_volt_by_clk(hwmgr,
1430	table_info->vdd_dep_on_sclk,	1431	table_info->vdd_dep_on_sclk,
1431	table->ACPILevel.SclkFrequency,	1432	sclk_frequency,
1432	&table->ACPILevel.MinVoltage, &mvdd);	1433	&table->ACPILevel.MinVoltage, &mvdd);
1433	PP_ASSERT_WITH_CODE((0 == result),	1434	PP_ASSERT_WITH_CODE((0 == result),
1434	"Cannot find ACPI VDDC voltage value "	1435	"Cannot find ACPI VDDC voltage value "
1435	"in Clock Dependency Table", );	1436	"in Clock Dependency Table",
1436	} else {	1437	);
1437	sclk_frequency = data->vbios_boot_state.sclk_bootup_value;	1438
1438	table->ACPILevel.MinVoltage =
1439	data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1440	}
1441		1439
1442	result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));	1440	result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1443	PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);	1441	PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
@@ -1462,24 +1460,18 @@ static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, · 18 unmodified lines
1462	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);	1460	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1463	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);	1461	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1464		1462
1465	if (!data->mclk_dpm_key_disabled) {	1463
1466	/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */	1464	/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1467	table->MemoryACPILevel.MclkFrequency =	1465	table->MemoryACPILevel.MclkFrequency =
1468	data->dpm_table.mclk_table.dpm_levels[0].value;	1466	data->dpm_table.mclk_table.dpm_levels[0].value;
1469	result = polaris10_get_dependency_volt_by_clk(hwmgr,	1467	result = polaris10_get_dependency_volt_by_clk(hwmgr,
1470	table_info->vdd_dep_on_mclk,	1468	table_info->vdd_dep_on_mclk,
1471	table->MemoryACPILevel.MclkFrequency,	1469	table->MemoryACPILevel.MclkFrequency,
1472	&table->MemoryACPILevel.MinVoltage, &mvdd);	1470	&table->MemoryACPILevel.MinVoltage, &mvdd);
1473	PP_ASSERT_WITH_CODE((0 == result),	1471	PP_ASSERT_WITH_CODE((0 == result),
1474	"Cannot find ACPI VDDCI voltage value "	1472	"Cannot find ACPI VDDCI voltage value "
1475	"in Clock Dependency Table",	1473	"in Clock Dependency Table",
1476	);	1474	);
1477	} else {
1478	table->MemoryACPILevel.MclkFrequency =
1479	data->vbios_boot_state.mclk_bootup_value;
1480	table->MemoryACPILevel.MinVoltage =
1481	data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1482	}
1483		1475
1484	us_mvdd = 0;	1476	us_mvdd = 0;
1485	if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) \|\|	1477	if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) \|\|
@@ -1524,6 +1516,7 @@ static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr, · 38 unmodified lines
1524	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =	1516	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1525	table_info->mm_dep_table;	1517	table_info->mm_dep_table;
1526	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);	1518	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);
		1519	uint32_t vddci;
1527		1520
1528	table->VceLevelCount = (uint8_t)(mm_table->count);	1521	table->VceLevelCount = (uint8_t)(mm_table->count);
1529	table->VceBootLevel = 0;	1522	table->VceBootLevel = 0;
@@ -1533,9 +1526,18 @@ static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr, · 3 unmodified lines
1533	table->VceLevel[count].MinVoltage = 0;	1526	table->VceLevel[count].MinVoltage = 0;
1534	table->VceLevel[count].MinVoltage \|=	1527	table->VceLevel[count].MinVoltage \|=
1535	(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;	1528	(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
		1529
		1530	if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
		1531	vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
		1532	mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
		1533	else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
		1534	vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
		1535	else
		1536	vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
		1537
		1538
1536	table->VceLevel[count].MinVoltage \|=	1539	table->VceLevel[count].MinVoltage \|=
1537	((mm_table->entries[count].vddc - data->vddc_vddci_delta) *	1540	(vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1538	VOLTAGE_SCALE) << VDDCI_SHIFT;
1539	table->VceLevel[count].MinVoltage \|= 1 << PHASES_SHIFT;	1541	table->VceLevel[count].MinVoltage \|= 1 << PHASES_SHIFT;
1540		1542
1541	/retrieve divider value for VBIOS /	1543	/retrieve divider value for VBIOS /
@@ -1564,6 +1566,7 @@ static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr, · 22 unmodified lines
1564	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =	1566	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1565	table_info->mm_dep_table;	1567	table_info->mm_dep_table;
1566	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);	1568	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);
		1569	uint32_t vddci;
1567		1570
1568	table->SamuBootLevel = 0;	1571	table->SamuBootLevel = 0;
1569	table->SamuLevelCount = (uint8_t)(mm_table->count);	1572	table->SamuLevelCount = (uint8_t)(mm_table->count);
@@ -1574,8 +1577,16 @@ static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr, · 4 unmodified lines
1574	table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;	1577	table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1575	table->SamuLevel[count].MinVoltage \|= (mm_table->entries[count].vddc *	1578	table->SamuLevel[count].MinVoltage \|= (mm_table->entries[count].vddc *
1576	VOLTAGE_SCALE) << VDDC_SHIFT;	1579	VOLTAGE_SCALE) << VDDC_SHIFT;
1577	table->SamuLevel[count].MinVoltage \|= ((mm_table->entries[count].vddc -	1580
1578	data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;	1581	if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
		1582	vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
		1583	mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
		1584	else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
		1585	vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
		1586	else
		1587	vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
		1588
		1589	table->SamuLevel[count].MinVoltage \|= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1579	table->SamuLevel[count].MinVoltage \|= 1 << PHASES_SHIFT;	1590	table->SamuLevel[count].MinVoltage \|= 1 << PHASES_SHIFT;
1580		1591
1581	/* retrieve divider value for VBIOS */	1592	/* retrieve divider value for VBIOS */
@@ -1658,6 +1669,7 @@ static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, · 76 unmodified lines
1658	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =	1669	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1659	table_info->mm_dep_table;	1670	table_info->mm_dep_table;
1660	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);	1671	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);
		1672	uint32_t vddci;
1661		1673
1662	table->UvdLevelCount = (uint8_t)(mm_table->count);	1674	table->UvdLevelCount = (uint8_t)(mm_table->count);
1663	table->UvdBootLevel = 0;	1675	table->UvdBootLevel = 0;
@@ -1668,8 +1680,16 @@ static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, · 4 unmodified lines
1668	table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;	1680	table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1669	table->UvdLevel[count].MinVoltage \|= (mm_table->entries[count].vddc *	1681	table->UvdLevel[count].MinVoltage \|= (mm_table->entries[count].vddc *
1670	VOLTAGE_SCALE) << VDDC_SHIFT;	1682	VOLTAGE_SCALE) << VDDC_SHIFT;
1671	table->UvdLevel[count].MinVoltage \|= ((mm_table->entries[count].vddc -	1683
1672	data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;	1684	if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
		1685	vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
		1686	mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
		1687	else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
		1688	vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
		1689	else
		1690	vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
		1691
		1692	table->UvdLevel[count].MinVoltage \|= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1673	table->UvdLevel[count].MinVoltage \|= 1 << PHASES_SHIFT;	1693	table->UvdLevel[count].MinVoltage \|= 1 << PHASES_SHIFT;
1674		1694
1675	/* retrieve divider value for VBIOS */	1695	/* retrieve divider value for VBIOS */
@@ -1690,8 +1710,8 @@ static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, · 14 unmodified lines
1690	CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);	1710	CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1691	CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);	1711	CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1692	CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);	1712	CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1693
1694	}	1713	}
		1714
1695	return result;	1715	return result;
1696	}	1716	}
1697		1717
@@ -1787,24 +1807,32 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) · 89 unmodified lines
1787		1807
1788	ro = efuse * (max -min)/255 + min;	1808	ro = efuse * (max -min)/255 + min;
1789		1809
1790	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */	1810	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset
		1811	* there is a little difference in calculating
		1812	* volt_with_cks with windows */
1791	for (i = 0; i < sclk_table->count; i++) {	1813	for (i = 0; i < sclk_table->count; i++) {
1792	data->smc_state_table.Sclk_CKS_masterEn0_7 \|=	1814	data->smc_state_table.Sclk_CKS_masterEn0_7 \|=
1793	sclk_table->entries[i].cks_enable << i;	1815	sclk_table->entries[i].cks_enable << i;
1794		1816	if (hwmgr->chip_id == CHIP_POLARIS10) {
1795	volt_without_cks = (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \	1817	volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1796	(sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);	1818	(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1797		1819	volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \
1798	volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \	1820	(252248000 - sclk_table->entries[i].clk/100 * 115764));
1799	(sclk_table->entries[i].clk/10000 * 649434 /1000 - 18005)/10);	1821	} else {
		1822	volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
		1823	(2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000));
		1824	volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \
		1825	(3422454 - sclk_table->entries[i].clk/100 * 18886376/10000));
		1826	}
1800		1827
1801	if (volt_without_cks >= volt_with_cks)	1828	if (volt_without_cks >= volt_with_cks)
1802	volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +	1829	volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks +
1803	sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);	1830	sclk_table->entries[i].cks_voffset) * 100 / 625);
1804		1831
1805	data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;	1832	data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1806	}	1833	}
1807		1834
		1835	data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1808	/* Populate CKS Lookup Table */	1836	/* Populate CKS Lookup Table */
1809	if (stretch_amount == 1 \|\| stretch_amount == 2 \|\| stretch_amount == 5)	1837	if (stretch_amount == 1 \|\| stretch_amount == 2 \|\| stretch_amount == 5)
1810	stretch_amount2 = 0;	1838	stretch_amount2 = 0;
@@ -2487,6 +2515,8 @@ int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) · 676 unmodified lines
2487	PP_ASSERT_WITH_CODE((0 == tmp_result),	2515	PP_ASSERT_WITH_CODE((0 == tmp_result),
2488	"Failed to enable VR hot GPIO interrupt!", result = tmp_result);	2516	"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2489		2517
		2518	smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
		2519
2490	tmp_result = polaris10_enable_sclk_control(hwmgr);	2520	tmp_result = polaris10_enable_sclk_control(hwmgr);
2491	PP_ASSERT_WITH_CODE((0 == tmp_result),	2521	PP_ASSERT_WITH_CODE((0 == tmp_result),
2492	"Failed to enable SCLK control!", result = tmp_result);	2522	"Failed to enable SCLK control!", result = tmp_result);
@@ -2913,6 +2943,31 @@ static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) · 420 unmodified lines
2913	return 0;	2943	return 0;
2914	}	2944	}
2915		2945
		2946	int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
		2947	{
		2948	struct phm_ppt_v1_information *table_info =
		2949	(struct phm_ppt_v1_information *)(hwmgr->pptable);
		2950	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
		2951	table_info->vdd_dep_on_mclk;
		2952	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
		2953	table_info->vddc_lookup_table;
		2954	uint32_t i;
		2955
		2956	if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7) {
		2957	if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
		2958	return 0;
		2959
		2960	for (i = 0; i < lookup_table->count; i++) {
		2961	if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
		2962	dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
		2963	return 0;
		2964	}
		2965	}
		2966	}
		2967	return 0;
		2968	}
		2969
		2970
2916	int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)	2971	int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2917	{	2972	{
2918	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);	2973	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);
@@ -2990,6 +3045,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) · 71 unmodified lines
2990		3045
2991	polaris10_set_features_platform_caps(hwmgr);	3046	polaris10_set_features_platform_caps(hwmgr);
2992		3047
		3048	polaris10_patch_voltage_workaround(hwmgr);
2993	polaris10_init_dpm_defaults(hwmgr);	3049	polaris10_init_dpm_defaults(hwmgr);
2994		3050
2995	/* Get leakage voltage based on leakage ID. */	3051	/* Get leakage voltage based on leakage ID. */
@@ -4359,6 +4415,15 @@ static int polaris10_notify_link_speed_change_after_state_change( · 1363 unmodified lines
4359	return 0;	4415	return 0;
4360	}	4416	}
4361		4417
		4418	static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
		4419	{
		4420	struct polaris10_hwmgr data = (struct polaris10_hwmgr )(hwmgr->backend);
		4421
		4422	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
		4423	(PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
		4424	return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
		4425	}
		4426
4362	static int polaris10_set_power_state_tasks(struct pp_hwmgr hwmgr, const void input)	4427	static int polaris10_set_power_state_tasks(struct pp_hwmgr hwmgr, const void input)
4363	{	4428	{
4364	int tmp_result, result = 0;	4429	int tmp_result, result = 0;
@@ -4407,6 +4472,11 @@ static int polaris10_set_power_state_tasks(struct pp_hwmgr hwmgr, const void i · 42 unmodified lines
4407	"Failed to program memory timing parameters!",	4472	"Failed to program memory timing parameters!",
4408	result = tmp_result);	4473	result = tmp_result);
4409		4474
		4475	tmp_result = polaris10_notify_smc_display(hwmgr);
		4476	PP_ASSERT_WITH_CODE((0 == tmp_result),
		4477	"Failed to notify smc display settings!",
		4478	result = tmp_result);
		4479
4410	tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);	4480	tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4411	PP_ASSERT_WITH_CODE((0 == tmp_result),	4481	PP_ASSERT_WITH_CODE((0 == tmp_result),
4412	"Failed to unfreeze SCLK MCLK DPM!",	4482	"Failed to unfreeze SCLK MCLK DPM!",
@@ -4441,6 +4511,7 @@ static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_ · 28 unmodified lines
4441	PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);	4511	PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4442	}	4512	}
4443		4513
		4514
4444	int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)	4515	int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4445	{	4516	{
4446	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;	4517	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
@@ -4460,8 +4531,6 @@ int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwm · 13 unmodified lines
4460		4531
4461	if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */	4532	if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4462	polaris10_notify_smc_display_change(hwmgr, false);	4533	polaris10_notify_smc_display_change(hwmgr, false);
4463	else
4464	polaris10_notify_smc_display_change(hwmgr, true);
4465		4534
4466	return 0;	4535	return 0;
4467	}	4536	}
@@ -4502,6 +4571,8 @@ int polaris10_program_display_gap(struct pp_hwmgr *hwmgr) · 34 unmodified lines
4502	frame_time_in_us = 1000000 / refresh_rate;	4571	frame_time_in_us = 1000000 / refresh_rate;
4503		4572
4504	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;	4573	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
		4574	data->frame_time_x2 = frame_time_in_us * 2 / 100;
		4575
4505	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);	4576	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4506		4577
4507	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);	4578	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
@@ -4510,8 +4581,6 @@ int polaris10_program_display_gap(struct pp_hwmgr *hwmgr) · 2 unmodified lines
4510		4581
4511	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));	4582	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4512		4583
4513	polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4514
4515	return 0;	4584	return 0;
4516	}	4585	}
4517		4586
@@ -4623,7 +4692,7 @@ int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr) · 105 unmodified lines
4623	return 0;	4692	return 0;
4624	}	4693	}
4625		4694
4626	data->need_long_memory_training = true;	4695	data->need_long_memory_training = false;
4627		4696
4628	/*	4697	/*
4629	* PPMCME_FirmwareDescriptorEntry *pfd = NULL;	4698	* PPMCME_FirmwareDescriptorEntry *pfd = NULL;

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h+1−0

@@ -315,6 +315,7 @@ struct polaris10_hwmgr { · 314 unmodified lines
315		315
316	uint32_t avfs_vdroop_override_setting;	316	uint32_t avfs_vdroop_override_setting;
317	bool apply_avfs_cks_off_voltage;	317	bool apply_avfs_cks_off_voltage;
		318	uint32_t frame_time_x2;
318	};	319	};
319		320
320	/* To convert to Q8.8 format for firmware */	321	/* To convert to Q8.8 format for firmware */

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h+2−0

@@ -411,6 +411,8 @@ struct phm_cac_tdp_table { · 410 unmodified lines
411	uint8_t ucVr_I2C_Line;	411	uint8_t ucVr_I2C_Line;
412	uint8_t ucPlx_I2C_address;	412	uint8_t ucPlx_I2C_address;
413	uint8_t ucPlx_I2C_Line;	413	uint8_t ucPlx_I2C_Line;
		414	uint32_t usBoostPowerLimit;
		415	uint8_t ucCKS_LDO_REFSEL;
414	};	416	};
415		417
416	struct phm_ppm_table {	418	struct phm_ppm_table {

drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h+2−0

@@ -392,6 +392,8 @@ typedef uint16_t PPSMC_Result; · 391 unmodified lines
392	#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300)	392	#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300)
393	#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301)	393	#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301)
394		394
		395	#define PPSMC_MSG_SetVBITimeout ((uint16_t) 0x306)
		396
395	#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600)	397	#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600)
396	#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601)	398	#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601)
397	#define PPSMC_MSG_SetAddress ((uint16_t) 0x800)	399	#define PPSMC_MSG_SetAddress ((uint16_t) 0x800)

drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h+2−1

@@ -270,7 +270,8 @@ struct SMU74_Discrete_DpmTable { · 269 unmodified lines
270	uint8_t BootPhases;	270	uint8_t BootPhases;
271		271
272	uint8_t VRHotLevel;	272	uint8_t VRHotLevel;
273	uint8_t Reserved1[3];	273	uint8_t LdoRefSel;
		274	uint8_t Reserved1[2];
274	uint16_t FanStartTemperature;	275	uint16_t FanStartTemperature;
275	uint16_t FanStopTemperature;	276	uint16_t FanStopTemperature;
276	uint16_t MaxVoltage;	277	uint16_t MaxVoltage;

drivers/gpu/drm/i915/i915_debugfs.c+2−2

 		task = get_pid_task(file->pid, PIDTYPE_PID);
 		if (!task) {
 			ret = -ESRCH;
-			goto out_put;
+			goto out_unlock;
 		}
 		seq_printf(m, "\nproc: %s\n", task->comm);
 		put_task_struct(task);
 		idr_for_each(&file_priv->context_idr, per_file_ctx,
 			     (void *)(unsigned long)m);
 	}
+out_unlock:
 	mutex_unlock(&dev->filelist_mutex);
-out_put:
 	intel_runtime_pm_put(dev_priv);
 	mutex_unlock(&dev->struct_mutex);

drivers/gpu/drm/i915/intel_display.c+8−8

@@ -8447,16 +8447,16 @@ static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) · 8446 unmodified lines
8447	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;	8447	tmp \|= FDI_MPHY_IOSFSB_RESET_CTL;
8448	I915_WRITE(SOUTH_CHICKEN2, tmp);	8448	I915_WRITE(SOUTH_CHICKEN2, tmp);
8449		8449
8450	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &	8450	if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8451	FDI_MPHY_IOSFSB_RESET_STATUS, 100))	8451	FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8452	DRM_ERROR("FDI mPHY reset assert timeout\n");	8452	DRM_ERROR("FDI mPHY reset assert timeout\n");
8453		8453
8454	tmp = I915_READ(SOUTH_CHICKEN2);	8454	tmp = I915_READ(SOUTH_CHICKEN2);
8455	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;	8455	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8456	I915_WRITE(SOUTH_CHICKEN2, tmp);	8456	I915_WRITE(SOUTH_CHICKEN2, tmp);
8457		8457
8458	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &	8458	if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8459	FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))	8459	FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8460	DRM_ERROR("FDI mPHY reset de-assert timeout\n");	8460	DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8461	}	8461	}
8462		8462
@@ -9440,8 +9440,8 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, · 977 unmodified lines
9440	val \|= LCPLL_CD_SOURCE_FCLK;	9440	val \|= LCPLL_CD_SOURCE_FCLK;
9441	I915_WRITE(LCPLL_CTL, val);	9441	I915_WRITE(LCPLL_CTL, val);
9442		9442
9443	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &	9443	if (wait_for_us(I915_READ(LCPLL_CTL) &
9444	LCPLL_CD_SOURCE_FCLK_DONE, 1))	9444	LCPLL_CD_SOURCE_FCLK_DONE, 1))
9445	DRM_ERROR("Switching to FCLK failed\n");	9445	DRM_ERROR("Switching to FCLK failed\n");
9446		9446
9447	val = I915_READ(LCPLL_CTL);	9447	val = I915_READ(LCPLL_CTL);
@@ -9514,8 +9514,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) · 66 unmodified lines
9514	val &= ~LCPLL_CD_SOURCE_FCLK;	9514	val &= ~LCPLL_CD_SOURCE_FCLK;
9515	I915_WRITE(LCPLL_CTL, val);	9515	I915_WRITE(LCPLL_CTL, val);
9516		9516
9517	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &	9517	if (wait_for_us((I915_READ(LCPLL_CTL) &
9518	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))	9518	LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9519	DRM_ERROR("Switching back to LCPLL failed\n");	9519	DRM_ERROR("Switching back to LCPLL failed\n");
9520	}	9520	}
9521		9521

drivers/gpu/drm/i915/intel_dp.c+6−4

 		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 					  msecs_to_jiffies_timeout(10));
 	else
-		done = wait_for_atomic(C, 10) == 0;
+		done = wait_for(C, 10) == 0;
 	if (!done)
 		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 			  has_aux_irq);
 void intel_dp_encoder_reset(struct drm_encoder *encoder)
 {
-	struct intel_dp *intel_dp;
+	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	if (!HAS_DDI(dev_priv))
+		intel_dp->DP = I915_READ(intel_dp->output_reg);
 	if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
 		return;
-	intel_dp = enc_to_intel_dp(encoder);
 	pps_lock(intel_dp);
 	/*

drivers/gpu/drm/i915/intel_dpll_mgr.c+2−2

@@ -1377,8 +1377,8 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, · 1376 unmodified lines
1377	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);	1377	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1378	POSTING_READ(BXT_PORT_PLL_ENABLE(port));	1378	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1379		1379
1380	if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &	1380	if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1381	PORT_PLL_LOCK), 200))	1381	200))
1382	DRM_ERROR("PLL %d not locked\n", port);	1382	DRM_ERROR("PLL %d not locked\n", port);
1383		1383
1384	/*	1384	/*

drivers/iio/accel/kxsd9.c+2−2

@@ -81,7 +81,7 @@ static int kxsd9_write_scale(struct iio_dev *indio_dev, int micro) · 80 unmodified lines
81		81
82	mutex_lock(&st->buf_lock);	82	mutex_lock(&st->buf_lock);
83	ret = spi_w8r8(st->us, KXSD9_READ(KXSD9_REG_CTRL_C));	83	ret = spi_w8r8(st->us, KXSD9_READ(KXSD9_REG_CTRL_C));
84	if (ret)	84	if (ret < 0)
85	goto error_ret;	85	goto error_ret;
86	st->tx[0] = KXSD9_WRITE(KXSD9_REG_CTRL_C);	86	st->tx[0] = KXSD9_WRITE(KXSD9_REG_CTRL_C);
87	st->tx[1] = (ret & ~KXSD9_FS_MASK) \| i;	87	st->tx[1] = (ret & ~KXSD9_FS_MASK) \| i;
@@ -163,7 +163,7 @@ static int kxsd9_read_raw(struct iio_dev *indio_dev, · 75 unmodified lines
163	break;	163	break;
164	case IIO_CHAN_INFO_SCALE:	164	case IIO_CHAN_INFO_SCALE:
165	ret = spi_w8r8(st->us, KXSD9_READ(KXSD9_REG_CTRL_C));	165	ret = spi_w8r8(st->us, KXSD9_READ(KXSD9_REG_CTRL_C));
166	if (ret)	166	if (ret < 0)
167	goto error_ret;	167	goto error_ret;
168	*val2 = kxsd9_micro_scales[ret & KXSD9_FS_MASK];	168	*val2 = kxsd9_micro_scales[ret & KXSD9_FS_MASK];
169	ret = IIO_VAL_INT_PLUS_MICRO;	169	ret = IIO_VAL_INT_PLUS_MICRO;

drivers/iio/adc/ad7266.c+5−2

 	st = iio_priv(indio_dev);
-	st->reg = devm_regulator_get(&spi->dev, "vref");
+	st->reg = devm_regulator_get_optional(&spi->dev, "vref");
-	if (!IS_ERR_OR_NULL(st->reg)) {
+	if (!IS_ERR(st->reg)) {
 		ret = regulator_enable(st->reg);
 		if (ret)
 			return ret;
 		st->vref_mv = ret / 1000;
 	} else {
+		/* Any other error indicates that the regulator does exist */
+		if (PTR_ERR(st->reg) != -ENODEV)
+			return PTR_ERR(st->reg);
 		/* Use internal reference */
 		st->vref_mv = 2500;
 	}

drivers/iio/imu/inv_mpu6050/inv_mpu_acpi.c+3−2

@@ -56,6 +56,7 @@ static int asus_acpi_get_sensor_info(struct acpi_device *adev, · 55 unmodified lines
56	int i;	56	int i;
57	acpi_status status;	57	acpi_status status;
58	union acpi_object *cpm;	58	union acpi_object *cpm;
		59	int ret;
59		60
60	status = acpi_evaluate_object(adev->handle, "CNF0", NULL, &buffer);	61	status = acpi_evaluate_object(adev->handle, "CNF0", NULL, &buffer);
61	if (ACPI_FAILURE(status))	62	if (ACPI_FAILURE(status))
@@ -82,10 +83,10 @@ static int asus_acpi_get_sensor_info(struct acpi_device *adev, · 20 unmodified lines
82	}	83	}
83	}	84	}
84	}	85	}
85		86	ret = cpm->package.count;
86	kfree(buffer.pointer);	87	kfree(buffer.pointer);
87		88
88	return cpm->package.count;	89	return ret;
89	}	90	}
90		91
91	static int acpi_i2c_check_resource(struct acpi_resource ares, void data)	92	static int acpi_i2c_check_resource(struct acpi_resource ares, void data)

drivers/iommu/amd_iommu_init.c+1−1

 				break;
 			}
+			devid = e->devid;
 			DUMP_printk("  DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
 				    hid, uid,
 				    PCI_BUS_NUM(devid),
 				    PCI_SLOT(devid),
 				    PCI_FUNC(devid));
-			devid  = e->devid;
 			flags = e->flags;
 			ret = add_acpi_hid_device(hid, uid, &devid, false);

drivers/iommu/intel-iommu.c+1−1

@@ -4607,7 +4607,7 @@ static void free_all_cpu_cached_iovas(unsigned int cpu) · 4606 unmodified lines
4607	if (!iommu)	4607	if (!iommu)
4608	continue;	4608	continue;
4609		4609
4610	for (did = 0; did < 0xffff; did++) {	4610	for (did = 0; did < cap_ndoms(iommu->cap); did++) {
4611	domain = get_iommu_domain(iommu, did);	4611	domain = get_iommu_domain(iommu, did);
4612		4612
4613	if (!domain)	4613	if (!domain)

drivers/iommu/iova.c+6−2

 		/* Try replenishing IOVAs by flushing rcache. */
 		flushed_rcache = true;
+		preempt_disable();
 		for_each_online_cpu(cpu)
 			free_cpu_cached_iovas(cpu, iovad);
+		preempt_enable();
 		goto retry;
 	}
 	bool can_insert = false;
 	unsigned long flags;
-	cpu_rcache = this_cpu_ptr(rcache->cpu_rcaches);
+	cpu_rcache = get_cpu_ptr(rcache->cpu_rcaches);
 	spin_lock_irqsave(&cpu_rcache->lock, flags);
 	if (!iova_magazine_full(cpu_rcache->loaded)) {
 		iova_magazine_push(cpu_rcache->loaded, iova_pfn);
 	spin_unlock_irqrestore(&cpu_rcache->lock, flags);
+	put_cpu_ptr(rcache->cpu_rcaches);
 	if (mag_to_free) {
 		iova_magazine_free_pfns(mag_to_free, iovad);
 	bool has_pfn = false;
 	unsigned long flags;
-	cpu_rcache = this_cpu_ptr(rcache->cpu_rcaches);
+	cpu_rcache = get_cpu_ptr(rcache->cpu_rcaches);
 	spin_lock_irqsave(&cpu_rcache->lock, flags);
 	if (!iova_magazine_empty(cpu_rcache->loaded)) {
 		iova_pfn = iova_magazine_pop(cpu_rcache->loaded, limit_pfn);
 	spin_unlock_irqrestore(&cpu_rcache->lock, flags);
+	put_cpu_ptr(rcache->cpu_rcaches);
 	return iova_pfn;
 }

drivers/mfd/max77620.c+2−0

 		break;
 	case MAX77620:
 		fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
+		break;
 	default:
 		return -EINVAL;
 	}
 		break;
 	case MAX77620:
 		fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
+		break;
 	default:
 		return -EINVAL;
 	}

drivers/net/bonding/bond_3ad.c+7−4

 #define MAC_ADDRESS_EQUAL(A, B)	\
 	ether_addr_equal_64bits((const u8 *)A, (const u8 *)B)
-static struct mac_addr null_mac_addr = { { 0, 0, 0, 0, 0, 0 } };
+static const u8 null_mac_addr[ETH_ALEN + 2] __long_aligned = {
+	0, 0, 0, 0, 0, 0
+};
 static u16 ad_ticks_per_sec;
 static const int ad_delta_in_ticks = (AD_TIMER_INTERVAL * HZ) / 1000;
-static const u8 lacpdu_mcast_addr[ETH_ALEN] = MULTICAST_LACPDU_ADDR;
+static const u8 lacpdu_mcast_addr[ETH_ALEN + 2] __long_aligned =
+	MULTICAST_LACPDU_ADDR;
 /* ================= main 802.3ad protocol functions ================== */
 static int ad_lacpdu_send(struct port *port);
 		aggregator->is_individual = false;
 		aggregator->actor_admin_aggregator_key = 0;
 		aggregator->actor_oper_aggregator_key = 0;
-		aggregator->partner_system = null_mac_addr;
+		eth_zero_addr(aggregator->partner_system.mac_addr_value);
 		aggregator->partner_system_priority = 0;
 		aggregator->partner_oper_aggregator_key = 0;
 		aggregator->receive_state = 0;
 	if (aggregator) {
 		ad_clear_agg(aggregator);
-		aggregator->aggregator_mac_address = null_mac_addr;
+		eth_zero_addr(aggregator->aggregator_mac_address.mac_addr_value);
 		aggregator->aggregator_identifier = 0;
 		aggregator->slave = NULL;
 	}

drivers/net/bonding/bond_alb.c+2−5

-#ifndef __long_aligned
+static const u8 mac_bcast[ETH_ALEN + 2] __long_aligned = {
-#define __long_aligned __attribute__((aligned((sizeof(long)))))
-#endif
-static const u8 mac_bcast[ETH_ALEN] __long_aligned = {
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 };
-static const u8 mac_v6_allmcast[ETH_ALEN] __long_aligned = {
+static const u8 mac_v6_allmcast[ETH_ALEN + 2] __long_aligned = {
 	0x33, 0x33, 0x00, 0x00, 0x00, 0x01
 };
 static const int alb_delta_in_ticks = HZ / ALB_TIMER_TICKS_PER_SEC;

drivers/net/bonding/bond_main.c+1−0

@@ -1584,6 +1584,7 @@ int bond_enslave(struct net_device bond_dev, struct net_device slave_dev) · 1583 unmodified lines
1584	}	1584	}
1585		1585
1586	/* check for initial state */	1586	/* check for initial state */
		1587	new_slave->link = BOND_LINK_NOCHANGE;
1587	if (bond->params.miimon) {	1588	if (bond->params.miimon) {
1588	if (bond_check_dev_link(bond, slave_dev, 0) == BMSR_LSTATUS) {	1589	if (bond_check_dev_link(bond, slave_dev, 0) == BMSR_LSTATUS) {
1589	if (bond->params.updelay) {	1590	if (bond->params.updelay) {

drivers/net/ethernet/broadcom/bcmsysport.c+1−1

@@ -370,7 +370,7 @@ static void bcm_sysport_get_stats(struct net_device *dev, · 369 unmodified lines
370	else	370	else
371	p = (char *)priv;	371	p = (char *)priv;
372	p += s->stat_offset;	372	p += s->stat_offset;
373	data[i] = (u32 )p;	373	data[i] = (unsigned long )p;
374	}	374	}
375	}	375	}
376		376

drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h+6−6

@@ -36,8 +36,8 @@ · 35 unmodified lines
36	#define __T4FW_VERSION_H__	36	#define __T4FW_VERSION_H__
37		37
38	#define T4FW_VERSION_MAJOR 0x01	38	#define T4FW_VERSION_MAJOR 0x01
39	#define T4FW_VERSION_MINOR 0x0E	39	#define T4FW_VERSION_MINOR 0x0F
40	#define T4FW_VERSION_MICRO 0x04	40	#define T4FW_VERSION_MICRO 0x25
41	#define T4FW_VERSION_BUILD 0x00	41	#define T4FW_VERSION_BUILD 0x00
42		42
43	#define T4FW_MIN_VERSION_MAJOR 0x01	43	#define T4FW_MIN_VERSION_MAJOR 0x01
@@ -45,8 +45,8 @@ · 1 unmodified line
45	#define T4FW_MIN_VERSION_MICRO 0x00	45	#define T4FW_MIN_VERSION_MICRO 0x00
46		46
47	#define T5FW_VERSION_MAJOR 0x01	47	#define T5FW_VERSION_MAJOR 0x01
48	#define T5FW_VERSION_MINOR 0x0E	48	#define T5FW_VERSION_MINOR 0x0F
49	#define T5FW_VERSION_MICRO 0x04	49	#define T5FW_VERSION_MICRO 0x25
50	#define T5FW_VERSION_BUILD 0x00	50	#define T5FW_VERSION_BUILD 0x00
51		51
52	#define T5FW_MIN_VERSION_MAJOR 0x00	52	#define T5FW_MIN_VERSION_MAJOR 0x00
@@ -54,8 +54,8 @@ · 1 unmodified line
54	#define T5FW_MIN_VERSION_MICRO 0x00	54	#define T5FW_MIN_VERSION_MICRO 0x00
55		55
56	#define T6FW_VERSION_MAJOR 0x01	56	#define T6FW_VERSION_MAJOR 0x01
57	#define T6FW_VERSION_MINOR 0x0E	57	#define T6FW_VERSION_MINOR 0x0F
58	#define T6FW_VERSION_MICRO 0x04	58	#define T6FW_VERSION_MICRO 0x25
59	#define T6FW_VERSION_BUILD 0x00	59	#define T6FW_VERSION_BUILD 0x00
60		60
61	#define T6FW_MIN_VERSION_MAJOR 0x00	61	#define T6FW_MIN_VERSION_MAJOR 0x00

drivers/net/ethernet/intel/e1000e/netdev.c+9−12

 	writel(val, hw->hw_addr + reg);
 }
-static bool e1000e_vlan_used(struct e1000_adapter *adapter)
-{
-	u16 vid;
-	for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
-		return true;
-	return false;
-}
 /**
  * e1000_regdump - register printout routine
  * @hw: pointer to the HW structure
 	ew32(RCTL, rctl);
-	if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX ||
+	if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
-	    e1000e_vlan_used(adapter))
 		e1000e_vlan_strip_enable(adapter);
 	else
 		e1000e_vlan_strip_disable(adapter);
 	if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
 		features &= ~NETIF_F_RXFCS;
+	/* Since there is no support for separate Rx/Tx vlan accel
+	 * enable/disable make sure Tx flag is always in same state as Rx.
+	 */
+	if (features & NETIF_F_HW_VLAN_CTAG_RX)
+		features |= NETIF_F_HW_VLAN_CTAG_TX;
+	else
+		features &= ~NETIF_F_HW_VLAN_CTAG_TX;
 	return features;
 }

drivers/net/ethernet/intel/ixgbevf/mbx.c+2−2

@@ -85,7 +85,7 @@ static s32 ixgbevf_poll_for_ack(struct ixgbe_hw *hw) · 84 unmodified lines
85	static s32 ixgbevf_read_posted_mbx(struct ixgbe_hw hw, u32 msg, u16 size)	85	static s32 ixgbevf_read_posted_mbx(struct ixgbe_hw hw, u32 msg, u16 size)
86	{	86	{
87	struct ixgbe_mbx_info *mbx = &hw->mbx;	87	struct ixgbe_mbx_info *mbx = &hw->mbx;
88	s32 ret_val = -IXGBE_ERR_MBX;	88	s32 ret_val = IXGBE_ERR_MBX;
89		89
90	if (!mbx->ops.read)	90	if (!mbx->ops.read)
91	goto out;	91	goto out;
@@ -111,7 +111,7 @@ out: · 19 unmodified lines
111	static s32 ixgbevf_write_posted_mbx(struct ixgbe_hw hw, u32 msg, u16 size)	111	static s32 ixgbevf_write_posted_mbx(struct ixgbe_hw hw, u32 msg, u16 size)
112	{	112	{
113	struct ixgbe_mbx_info *mbx = &hw->mbx;	113	struct ixgbe_mbx_info *mbx = &hw->mbx;
114	s32 ret_val = -IXGBE_ERR_MBX;	114	s32 ret_val = IXGBE_ERR_MBX;
115		115
116	/* exit if either we can't write or there isn't a defined timeout */	116	/* exit if either we can't write or there isn't a defined timeout */
117	if (!mbx->ops.write \|\| !mbx->timeout)	117	if (!mbx->ops.write \|\| !mbx->timeout)

drivers/net/ethernet/marvell/mvneta.c+2−0

@@ -3458,6 +3458,8 @@ static int mvneta_open(struct net_device *dev) · 3457 unmodified lines
3458	return 0;	3458	return 0;
3459		3459
3460	err_free_irq:	3460	err_free_irq:
		3461	unregister_cpu_notifier(&pp->cpu_notifier);
		3462	on_each_cpu(mvneta_percpu_disable, pp, true);
3461	free_percpu_irq(pp->dev->irq, pp->ports);	3463	free_percpu_irq(pp->dev->irq, pp->ports);
3462	err_cleanup_txqs:	3464	err_cleanup_txqs:
3463	mvneta_cleanup_txqs(pp);	3465	mvneta_cleanup_txqs(pp);

drivers/net/ethernet/mellanox/mlx5/core/cmd.c+72−57

@@ -295,6 +295,12 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, · 294 unmodified lines
295	case MLX5_CMD_OP_DESTROY_FLOW_GROUP:	295	case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
296	case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:	296	case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
297	case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:	297	case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
		298	case MLX5_CMD_OP_2ERR_QP:
		299	case MLX5_CMD_OP_2RST_QP:
		300	case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
		301	case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
		302	case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
		303	case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
298	return MLX5_CMD_STAT_OK;	304	return MLX5_CMD_STAT_OK;
299		305
300	case MLX5_CMD_OP_QUERY_HCA_CAP:	306	case MLX5_CMD_OP_QUERY_HCA_CAP:
@@ -321,8 +327,6 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, · 20 unmodified lines
321	case MLX5_CMD_OP_RTR2RTS_QP:	327	case MLX5_CMD_OP_RTR2RTS_QP:
322	case MLX5_CMD_OP_RTS2RTS_QP:	328	case MLX5_CMD_OP_RTS2RTS_QP:
323	case MLX5_CMD_OP_SQERR2RTS_QP:	329	case MLX5_CMD_OP_SQERR2RTS_QP:
324	case MLX5_CMD_OP_2ERR_QP:
325	case MLX5_CMD_OP_2RST_QP:
326	case MLX5_CMD_OP_QUERY_QP:	330	case MLX5_CMD_OP_QUERY_QP:
327	case MLX5_CMD_OP_SQD_RTS_QP:	331	case MLX5_CMD_OP_SQD_RTS_QP:
328	case MLX5_CMD_OP_INIT2INIT_QP:	332	case MLX5_CMD_OP_INIT2INIT_QP:
@@ -342,7 +346,6 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, · 13 unmodified lines
342	case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:	346	case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
343	case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:	347	case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
344	case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:	348	case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
345	case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
346	case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:	349	case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
347	case MLX5_CMD_OP_SET_ROCE_ADDRESS:	350	case MLX5_CMD_OP_SET_ROCE_ADDRESS:
348	case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:	351	case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
@@ -390,11 +393,12 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, · 41 unmodified lines
390	case MLX5_CMD_OP_CREATE_RQT:	393	case MLX5_CMD_OP_CREATE_RQT:
391	case MLX5_CMD_OP_MODIFY_RQT:	394	case MLX5_CMD_OP_MODIFY_RQT:
392	case MLX5_CMD_OP_QUERY_RQT:	395	case MLX5_CMD_OP_QUERY_RQT:
		396
393	case MLX5_CMD_OP_CREATE_FLOW_TABLE:	397	case MLX5_CMD_OP_CREATE_FLOW_TABLE:
394	case MLX5_CMD_OP_QUERY_FLOW_TABLE:	398	case MLX5_CMD_OP_QUERY_FLOW_TABLE:
395	case MLX5_CMD_OP_CREATE_FLOW_GROUP:	399	case MLX5_CMD_OP_CREATE_FLOW_GROUP:
396	case MLX5_CMD_OP_QUERY_FLOW_GROUP:	400	case MLX5_CMD_OP_QUERY_FLOW_GROUP:
397	case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:	401
398	case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:	402	case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
399	case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:	403	case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
400	case MLX5_CMD_OP_QUERY_FLOW_COUNTER:	404	case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
@@ -602,11 +606,36 @@ static void dump_command(struct mlx5_core_dev *dev, · 201 unmodified lines
602	pr_debug("\n");	606	pr_debug("\n");
603	}	607	}
604		608
		609	static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
		610	{
		611	struct mlx5_inbox_hdr hdr = (struct mlx5_inbox_hdr )(in->first.data);
		612
		613	return be16_to_cpu(hdr->opcode);
		614	}
		615
		616	static void cb_timeout_handler(struct work_struct *work)
		617	{
		618	struct delayed_work *dwork = container_of(work, struct delayed_work,
		619	work);
		620	struct mlx5_cmd_work_ent *ent = container_of(dwork,
		621	struct mlx5_cmd_work_ent,
		622	cb_timeout_work);
		623	struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
		624	cmd);
		625
		626	ent->ret = -ETIMEDOUT;
		627	mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
		628	mlx5_command_str(msg_to_opcode(ent->in)),
		629	msg_to_opcode(ent->in));
		630	mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
		631	}
		632
605	static void cmd_work_handler(struct work_struct *work)	633	static void cmd_work_handler(struct work_struct *work)
606	{	634	{
607	struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);	635	struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
608	struct mlx5_cmd *cmd = ent->cmd;	636	struct mlx5_cmd *cmd = ent->cmd;
609	struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);	637	struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
		638	unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
610	struct mlx5_cmd_layout *lay;	639	struct mlx5_cmd_layout *lay;
611	struct semaphore *sem;	640	struct semaphore *sem;
612	unsigned long flags;	641	unsigned long flags;
@@ -647,6 +676,9 @@ static void cmd_work_handler(struct work_struct *work) · 34 unmodified lines
647	dump_command(dev, ent, 1);	676	dump_command(dev, ent, 1);
648	ent->ts1 = ktime_get_ns();	677	ent->ts1 = ktime_get_ns();
649		678
		679	if (ent->callback)
		680	schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
		681
650	/* ring doorbell after the descriptor is valid */	682	/* ring doorbell after the descriptor is valid */
651	mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);	683	mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
652	wmb();	684	wmb();
@@ -691,13 +723,6 @@ static const char *deliv_status_to_str(u8 status) · 38 unmodified lines
691	}	723	}
692	}	724	}
693		725
694	static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
695	{
696	struct mlx5_inbox_hdr hdr = (struct mlx5_inbox_hdr )(in->first.data);
697
698	return be16_to_cpu(hdr->opcode);
699	}
700
701	static int wait_func(struct mlx5_core_dev dev, struct mlx5_cmd_work_ent ent)	726	static int wait_func(struct mlx5_core_dev dev, struct mlx5_cmd_work_ent ent)
702	{	727	{
703	unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);	728	unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
@@ -706,13 +731,13 @@ static int wait_func(struct mlx5_core_dev dev, struct mlx5_cmd_work_ent ent) · 2 unmodified lines
706		731
707	if (cmd->mode == CMD_MODE_POLLING) {	732	if (cmd->mode == CMD_MODE_POLLING) {
708	wait_for_completion(&ent->done);	733	wait_for_completion(&ent->done);
709	err = ent->ret;	734	} else if (!wait_for_completion_timeout(&ent->done, timeout)) {
710	} else {	735	ent->ret = -ETIMEDOUT;
711	if (!wait_for_completion_timeout(&ent->done, timeout))	736	mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
712	err = -ETIMEDOUT;
713	else
714	err = 0;
715	}	737	}
		738
		739	err = ent->ret;
		740
716	if (err == -ETIMEDOUT) {	741	if (err == -ETIMEDOUT) {
717	mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",	742	mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
718	mlx5_command_str(msg_to_opcode(ent->in)),	743	mlx5_command_str(msg_to_opcode(ent->in)),
@@ -761,6 +786,7 @@ static int mlx5_cmd_invoke(struct mlx5_core_dev dev, struct mlx5_cmd_msg in, · 42 unmodified lines
761	if (!callback)	786	if (!callback)
762	init_completion(&ent->done);	787	init_completion(&ent->done);
763		788
		789	INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
764	INIT_WORK(&ent->work, cmd_work_handler);	790	INIT_WORK(&ent->work, cmd_work_handler);
765	if (page_queue) {	791	if (page_queue) {
766	cmd_work_handler(&ent->work);	792	cmd_work_handler(&ent->work);
@@ -770,28 +796,26 @@ static int mlx5_cmd_invoke(struct mlx5_core_dev dev, struct mlx5_cmd_msg in, · 3 unmodified lines
770	goto out_free;	796	goto out_free;
771	}	797	}
772		798
773	if (!callback) {	799	if (callback)
774	err = wait_func(dev, ent);	800	goto out;
775	if (err == -ETIMEDOUT)
776	goto out;
777
778	ds = ent->ts2 - ent->ts1;
779	op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
780	if (op < ARRAY_SIZE(cmd->stats)) {
781	stats = &cmd->stats[op];
782	spin_lock_irq(&stats->lock);
783	stats->sum += ds;
784	++stats->n;
785	spin_unlock_irq(&stats->lock);
786	}
787	mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
788	"fw exec time for %s is %lld nsec\n",
789	mlx5_command_str(op), ds);
790	*status = ent->status;
791	free_cmd(ent);
792	}
793		801
794	return err;	802	err = wait_func(dev, ent);
		803	if (err == -ETIMEDOUT)
		804	goto out_free;
		805
		806	ds = ent->ts2 - ent->ts1;
		807	op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
		808	if (op < ARRAY_SIZE(cmd->stats)) {
		809	stats = &cmd->stats[op];
		810	spin_lock_irq(&stats->lock);
		811	stats->sum += ds;
		812	++stats->n;
		813	spin_unlock_irq(&stats->lock);
		814	}
		815	mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
		816	"fw exec time for %s is %lld nsec\n",
		817	mlx5_command_str(op), ds);
		818	*status = ent->status;
795		819
796	out_free:	820	out_free:
797	free_cmd(ent);	821	free_cmd(ent);
@@ -1181,41 +1205,30 @@ err_dbg: · 383 unmodified lines
1181	return err;	1205	return err;
1182	}	1206	}
1183		1207
1184	void mlx5_cmd_use_events(struct mlx5_core_dev *dev)	1208	static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1185	{	1209	{
1186	struct mlx5_cmd *cmd = &dev->cmd;	1210	struct mlx5_cmd *cmd = &dev->cmd;
1187	int i;	1211	int i;
1188		1212
1189	for (i = 0; i < cmd->max_reg_cmds; i++)	1213	for (i = 0; i < cmd->max_reg_cmds; i++)
1190	down(&cmd->sem);	1214	down(&cmd->sem);
1191
1192	down(&cmd->pages_sem);	1215	down(&cmd->pages_sem);
1193		1216
1194	flush_workqueue(cmd->wq);	1217	cmd->mode = mode;
1195
1196	cmd->mode = CMD_MODE_EVENTS;
1197		1218
1198	up(&cmd->pages_sem);	1219	up(&cmd->pages_sem);
1199	for (i = 0; i < cmd->max_reg_cmds; i++)	1220	for (i = 0; i < cmd->max_reg_cmds; i++)
1200	up(&cmd->sem);	1221	up(&cmd->sem);
1201	}	1222	}
1202		1223
1203	void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)	1224	void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1204	{	1225	{
1205	struct mlx5_cmd *cmd = &dev->cmd;	1226	mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1206	int i;	1227	}
1207
1208	for (i = 0; i < cmd->max_reg_cmds; i++)
1209	down(&cmd->sem);
1210
1211	down(&cmd->pages_sem);
1212
1213	flush_workqueue(cmd->wq);
1214	cmd->mode = CMD_MODE_POLLING;
1215		1228
1216	up(&cmd->pages_sem);	1229	void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1217	for (i = 0; i < cmd->max_reg_cmds; i++)	1230	{
1218	up(&cmd->sem);	1231	mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1219	}	1232	}
1220		1233
1221	static void free_msg(struct mlx5_core_dev dev, struct mlx5_cmd_msg msg)	1234	static void free_msg(struct mlx5_core_dev dev, struct mlx5_cmd_msg msg)
@@ -1251,6 +1264,8 @@ void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec) · 29 unmodified lines
1251	struct semaphore *sem;	1264	struct semaphore *sem;
1252		1265
1253	ent = cmd->ent_arr[i];	1266	ent = cmd->ent_arr[i];
		1267	if (ent->callback)
		1268	cancel_delayed_work(&ent->cb_timeout_work);
1254	if (ent->page_queue)	1269	if (ent->page_queue)
1255	sem = &cmd->pages_sem;	1270	sem = &cmd->pages_sem;
1256	else	1271	else

drivers/net/ethernet/mellanox/mlx5/core/en.h+10−1

 #ifdef CONFIG_MLX5_CORE_EN_DCB
 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
-#define MLX5E_MIN_BW_ALLOC 1   /* Min percentage of BW allocation */
 #endif
 struct mlx5e_cq_moder {
 enum {
 	MLX5E_RQ_STATE_POST_WQES_ENABLE,
 	MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
+	MLX5E_RQ_STATE_FLUSH_TIMEOUT,
 	MLX5E_RQ_STATE_AM,
 };
 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
 				  u16 ix);
+typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
 struct mlx5e_dma_info {
 	struct page	*page;
 	dma_addr_t	addr;
 	struct mlx5e_cq        cq;
 	mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 	mlx5e_fp_alloc_wqe     alloc_wqe;
+	mlx5e_fp_dealloc_wqe   dealloc_wqe;
 	unsigned long          state;
 	int                    ix;
 enum {
 	MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
 	MLX5E_SQ_STATE_BF_ENABLE,
+	MLX5E_SQ_STATE_TX_TIMEOUT,
 };
 struct mlx5e_ico_wqe_info {
 	struct workqueue_struct    *wq;
 	struct work_struct         update_carrier_work;
 	struct work_struct         set_rx_mode_work;
+	struct work_struct         tx_timeout_work;
 	struct delayed_work        update_stats_work;
 	u32                        pflags;
 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
+void mlx5e_free_tx_descs(struct mlx5e_sq *sq);
+void mlx5e_free_rx_descs(struct mlx5e_rq *rq);
 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
+void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
+void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
 				    struct mlx5_cqe64 *cqe,

drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c+6−2

 			tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
 			break;
 		case IEEE_8021QAZ_TSA_ETS:
-			tc_tx_bw[i] = ets->tc_tx_bw[i] ?: MLX5E_MIN_BW_ALLOC;
+			tc_tx_bw[i] = ets->tc_tx_bw[i];
 			break;
 		}
 	}
 	/* Validate Bandwidth Sum */
 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
-		if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS)
+		if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
+			if (!ets->tc_tx_bw[i])
+				return -EINVAL;
 			bw_sum += ets->tc_tx_bw[i];
+		}
 	}
 	if (bw_sum != 0 && bw_sum != 100)

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+90−10

 #include "eswitch.h"
 #include "vxlan.h"
+enum {
+	MLX5_EN_QP_FLUSH_TIMEOUT_MS	= 5000,
+	MLX5_EN_QP_FLUSH_MSLEEP_QUANT	= 20,
+	MLX5_EN_QP_FLUSH_MAX_ITER	= MLX5_EN_QP_FLUSH_TIMEOUT_MS /
+					  MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
+};
 struct mlx5e_rq_param {
 	u32			rqc[MLX5_ST_SZ_DW(rqc)];
 	struct mlx5_wq_param	wq;
 	port_state = mlx5_query_vport_state(mdev,
 		MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
-	if (port_state == VPORT_STATE_UP)
+	if (port_state == VPORT_STATE_UP) {
+		netdev_info(priv->netdev, "Link up\n");
 		netif_carrier_on(priv->netdev);
-	else
+	} else {
+		netdev_info(priv->netdev, "Link down\n");
 		netif_carrier_off(priv->netdev);
+	}
 }
 static void mlx5e_update_carrier_work(struct work_struct *work)
 	mutex_unlock(&priv->state_lock);
 }
+static void mlx5e_tx_timeout_work(struct work_struct *work)
+{
+	struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
+					       tx_timeout_work);
+	int err;
+	rtnl_lock();
+	mutex_lock(&priv->state_lock);
+	if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
+		goto unlock;
+	mlx5e_close_locked(priv->netdev);
+	err = mlx5e_open_locked(priv->netdev);
+	if (err)
+		netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
+			   err);
+unlock:
+	mutex_unlock(&priv->state_lock);
+	rtnl_unlock();
+}
 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 {
 	struct mlx5e_sw_stats *s = &priv->stats.sw;
 		}
 		rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 		rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
+		rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 		rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 		rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 		}
 		rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 		rq->alloc_wqe = mlx5e_alloc_rx_wqe;
+		rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 		rq->wqe_sz = (priv->params.lro_en) ?
 				priv->params.lro_wqe_sz :
 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 {
+	int tout = 0;
+	int err;
 	clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 	napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
-	mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
+	err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
-	while (!mlx5_wq_ll_is_empty(&rq->wq))
+	while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
-		msleep(20);
+	       tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
+		msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
+	if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
+		set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
 	/* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 	napi_synchronize(&rq->channel->napi);
 	cancel_work_sync(&rq->am.work);
 	mlx5e_disable_rq(rq);
+	mlx5e_free_rx_descs(rq);
 	mlx5e_destroy_rq(rq);
 }
 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 {
+	int tout = 0;
+	int err;
 	if (sq->txq) {
 		clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 		/* prevent netif_tx_wake_queue */
 		if (mlx5e_sq_has_room_for(sq, 1))
 			mlx5e_send_nop(sq, true);
-		mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR,
+		err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
-				false, 0);
+				      MLX5_SQC_STATE_ERR, false, 0);
+		if (err)
+			set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 	}
-	while (sq->cc != sq->pc) /* wait till sq is empty */
+	/* wait till sq is empty, unless a TX timeout occurred on this SQ */
-		msleep(20);
+	while (sq->cc != sq->pc &&
+	       !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
+		msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
+		if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
+			set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
+	}
 	/* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 	napi_synchronize(&sq->channel->napi);
+	mlx5e_free_tx_descs(sq);
 	mlx5e_disable_sq(sq);
 	mlx5e_destroy_sq(sq);
 }
 	netdev_set_num_tc(netdev, ntc);
+	/* Map netdev TCs to offset 0
+	 * We have our own UP to TXQ mapping for QoS
+	 */
 	for (tc = 0; tc < ntc; tc++)
-		netdev_set_tc_queue(netdev, tc, nch, tc * nch);
+		netdev_set_tc_queue(netdev, tc, nch, 0);
 }
 int mlx5e_open_locked(struct net_device *netdev)
 	return features;
 }
+static void mlx5e_tx_timeout(struct net_device *dev)
+{
+	struct mlx5e_priv *priv = netdev_priv(dev);
+	bool sched_work = false;
+	int i;
+	netdev_err(dev, "TX timeout detected\n");
+	for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
+		struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
+		if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
+			continue;
+		sched_work = true;
+		set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
+		netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
+			   i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
+	}
+	if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
+		schedule_work(&priv->tx_timeout_work);
+}
 static const struct net_device_ops mlx5e_netdev_ops_basic = {
 	.ndo_open                = mlx5e_open,
 	.ndo_stop                = mlx5e_close,
 #ifdef CONFIG_RFS_ACCEL
 	.ndo_rx_flow_steer	 = mlx5e_rx_flow_steer,
 #endif
+	.ndo_tx_timeout          = mlx5e_tx_timeout,
 };
 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
 	.ndo_get_vf_config       = mlx5e_get_vf_config,
 	.ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
 	.ndo_get_vf_stats        = mlx5e_get_vf_stats,
+	.ndo_tx_timeout          = mlx5e_tx_timeout,
 };
 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
 	INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
 	INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
+	INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
 	INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
 }

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c+41−0

@@ -212,6 +212,20 @@ err_free_skb: · 211 unmodified lines
212	return -ENOMEM;	212	return -ENOMEM;
213	}	213	}
214		214
		215	void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
		216	{
		217	struct sk_buff *skb = rq->skb[ix];
		218
		219	if (skb) {
		220	rq->skb[ix] = NULL;
		221	dma_unmap_single(rq->pdev,
		222	((dma_addr_t )skb->cb),
		223	rq->wqe_sz,
		224	DMA_FROM_DEVICE);
		225	dev_kfree_skb(skb);
		226	}
		227	}
		228
215	static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)	229	static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
216	{	230	{
217	return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;	231	return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
@@ -574,6 +588,30 @@ int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq rq, struct mlx5e_rx_wqe wqe, u16 ix) · 356 unmodified lines
574	return 0;	588	return 0;
575	}	589	}
576		590
		591	void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
		592	{
		593	struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
		594
		595	wi->free_wqe(rq, wi);
		596	}
		597
		598	void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
		599	{
		600	struct mlx5_wq_ll *wq = &rq->wq;
		601	struct mlx5e_rx_wqe *wqe;
		602	__be16 wqe_ix_be;
		603	u16 wqe_ix;
		604
		605	while (!mlx5_wq_ll_is_empty(wq)) {
		606	wqe_ix_be = *wq->tail_next;
		607	wqe_ix = be16_to_cpu(wqe_ix_be);
		608	wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
		609	rq->dealloc_wqe(rq, wqe_ix);
		610	mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
		611	&wqe->next.next_wqe_index);
		612	}
		613	}
		614
577	#define RQ_CANNOT_POST(rq) \	615	#define RQ_CANNOT_POST(rq) \
578	(!test_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state) \|\| \	616	(!test_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state) \|\| \
579	test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))	617	test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
@@ -878,6 +916,9 @@ int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) · 298 unmodified lines
878	struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);	916	struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
879	int work_done = 0;	917	int work_done = 0;
880		918
		919	if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state)))
		920	return 0;
		921
881	if (cq->decmprs_left)	922	if (cq->decmprs_left)
882	work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);	923	work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
883		924

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+48−4

@@ -110,8 +110,20 @@ u16 mlx5e_select_queue(struct net_device dev, struct sk_buff skb, · 109 unmodified lines
110	{	110	{
111	struct mlx5e_priv *priv = netdev_priv(dev);	111	struct mlx5e_priv *priv = netdev_priv(dev);
112	int channel_ix = fallback(dev, skb);	112	int channel_ix = fallback(dev, skb);
113	int up = (netdev_get_num_tc(dev) && skb_vlan_tag_present(skb)) ?	113	int up = 0;
114	skb->vlan_tci >> VLAN_PRIO_SHIFT : 0;	114
		115	if (!netdev_get_num_tc(dev))
		116	return channel_ix;
		117
		118	if (skb_vlan_tag_present(skb))
		119	up = skb->vlan_tci >> VLAN_PRIO_SHIFT;
		120
		121	/* channel_ix can be larger than num_channels since
		122	* dev->num_real_tx_queues = num_channels * num_tc
		123	*/
		124	if (channel_ix >= priv->params.num_channels)
		125	channel_ix = reciprocal_scale(channel_ix,
		126	priv->params.num_channels);
115		127
116	return priv->channeltc_to_txq_map[channel_ix][up];	128	return priv->channeltc_to_txq_map[channel_ix][up];
117	}	129	}
@@ -123,7 +135,7 @@ static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq, · 5 unmodified lines
123	* headers and occur before the data gather.	135	* headers and occur before the data gather.
124	* Therefore these headers must be copied into the WQE	136	* Therefore these headers must be copied into the WQE
125	*/	137	*/
126	#define MLX5E_MIN_INLINE ETH_HLEN	138	#define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
127		139
128	if (bf) {	140	if (bf) {
129	u16 ihs = skb_headlen(skb);	141	u16 ihs = skb_headlen(skb);
@@ -135,7 +147,7 @@ static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq, · 5 unmodified lines
135	return skb_headlen(skb);	147	return skb_headlen(skb);
136	}	148	}
137		149
138	return MLX5E_MIN_INLINE;	150	return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
139	}	151	}
140		152
141	static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,	153	static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
@@ -341,6 +353,35 @@ netdev_tx_t mlx5e_xmit(struct sk_buff skb, struct net_device dev) · 199 unmodified lines
341	return mlx5e_sq_xmit(sq, skb);	353	return mlx5e_sq_xmit(sq, skb);
342	}	354	}
343		355
		356	void mlx5e_free_tx_descs(struct mlx5e_sq *sq)
		357	{
		358	struct mlx5e_tx_wqe_info *wi;
		359	struct sk_buff *skb;
		360	u16 ci;
		361	int i;
		362
		363	while (sq->cc != sq->pc) {
		364	ci = sq->cc & sq->wq.sz_m1;
		365	skb = sq->skb[ci];
		366	wi = &sq->wqe_info[ci];
		367
		368	if (!skb) { /* nop */
		369	sq->cc++;
		370	continue;
		371	}
		372
		373	for (i = 0; i < wi->num_dma; i++) {
		374	struct mlx5e_sq_dma *dma =
		375	mlx5e_dma_get(sq, sq->dma_fifo_cc++);
		376
		377	mlx5e_tx_dma_unmap(sq->pdev, dma);
		378	}
		379
		380	dev_kfree_skb_any(skb);
		381	sq->cc += wi->num_wqebbs;
		382	}
		383	}
		384
344	bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)	385	bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
345	{	386	{
346	struct mlx5e_sq *sq;	387	struct mlx5e_sq *sq;
@@ -352,6 +393,9 @@ bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget) · 5 unmodified lines
352		393
353	sq = container_of(cq, struct mlx5e_sq, cq);	394	sq = container_of(cq, struct mlx5e_sq, cq);
354		395
		396	if (unlikely(test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)))
		397	return false;
		398
355	npkts = 0;	399	npkts = 0;
356	nbytes = 0;	400	nbytes = 0;
357		401

drivers/net/ethernet/mellanox/mlx5/core/health.c+8−3

 void mlx5_enter_error_state(struct mlx5_core_dev *dev)
 {
+	mutex_lock(&dev->intf_state_mutex);
 	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
-		return;
+		goto unlock;
 	mlx5_core_err(dev, "start\n");
-	if (pci_channel_offline(dev->pdev) || in_fatal(dev))
+	if (pci_channel_offline(dev->pdev) || in_fatal(dev)) {
 		dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
+		trigger_cmd_completions(dev);
+	}
 	mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 0);
 	mlx5_core_err(dev, "end\n");
+unlock:
+	mutex_unlock(&dev->intf_state_mutex);
 }
 static void mlx5_handle_bad_state(struct mlx5_core_dev *dev)
 	u32 count;
 	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
-		trigger_cmd_completions(dev);
 		mod_timer(&health->timer, get_next_poll_jiffies());
 		return;
 	}

drivers/net/ethernet/mellanox/mlx5/core/main.c+15−26

 	mlx5_pci_err_detected(dev->pdev, 0);
 }
-/* wait for the device to show vital signs. For now we check
+/* wait for the device to show vital signs by waiting
- * that we can read the device ID and that the health buffer
+ * for the health counter to start counting.
- * shows a non zero value which is different than 0xffffffff
  */
-static void wait_vital(struct pci_dev *pdev)
+static int wait_vital(struct pci_dev *pdev)
 {
 	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
 	struct mlx5_core_health *health = &dev->priv.health;
 	const int niter = 100;
+	u32 last_count = 0;
 	u32 count;
-	u16 did;
 	int i;
-	/* Wait for firmware to be ready after reset */
-	msleep(1000);
-	for (i = 0; i < niter; i++) {
-		if (pci_read_config_word(pdev, 2, &did)) {
-			dev_warn(&pdev->dev, "failed reading config word\n");
-			break;
-		}
-		if (did == pdev->device) {
-			dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
-			break;
-		}
-		msleep(50);
-	}
-	if (i == niter)
-		dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
 	for (i = 0; i < niter; i++) {
 		count = ioread32be(health->health_counter);
 		if (count && count != 0xffffffff) {
-			dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
+			if (last_count && last_count != count) {
-			break;
+				dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
+				return 0;
+			}
+			last_count = count;
 		}
 		msleep(50);
 	}
-	if (i == niter)
+	return -ETIMEDOUT;
-		dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
 }
 static void mlx5_pci_resume(struct pci_dev *pdev)
 	dev_info(&pdev->dev, "%s was called\n", __func__);
 	pci_save_state(pdev);
-	wait_vital(pdev);
+	err = wait_vital(pdev);
+	if (err) {
+		dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
+		return;
+	}
 	err = mlx5_load_one(dev, priv);
 	if (err)

drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c+44−19

@@ -345,7 +345,6 @@ retry: · 344 unmodified lines
345	func_id, npages, err);	345	func_id, npages, err);
346	goto out_4k;	346	goto out_4k;
347	}	347	}
348	dev->priv.fw_pages += npages;
349		348
350	err = mlx5_cmd_status_to_err(&out.hdr);	349	err = mlx5_cmd_status_to_err(&out.hdr);
351	if (err) {	350	if (err) {
@@ -373,6 +372,33 @@ out_free: · 21 unmodified lines
373	return err;	372	return err;
374	}	373	}
375		374
		375	static int reclaim_pages_cmd(struct mlx5_core_dev *dev,
		376	struct mlx5_manage_pages_inbox *in, int in_size,
		377	struct mlx5_manage_pages_outbox *out, int out_size)
		378	{
		379	struct fw_page *fwp;
		380	struct rb_node *p;
		381	u32 npages;
		382	u32 i = 0;
		383
		384	if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)
		385	return mlx5_cmd_exec_check_status(dev, (u32 *)in, in_size,
		386	(u32 *)out, out_size);
		387
		388	npages = be32_to_cpu(in->num_entries);
		389
		390	p = rb_first(&dev->priv.page_root);
		391	while (p && i < npages) {
		392	fwp = rb_entry(p, struct fw_page, rb_node);
		393	out->pas[i] = cpu_to_be64(fwp->addr);
		394	p = rb_next(p);
		395	i++;
		396	}
		397
		398	out->num_entries = cpu_to_be32(i);
		399	return 0;
		400	}
		401
376	static int reclaim_pages(struct mlx5_core_dev *dev, u32 func_id, int npages,	402	static int reclaim_pages(struct mlx5_core_dev *dev, u32 func_id, int npages,
377	int *nclaimed)	403	int *nclaimed)
378	{	404	{
@@ -398,15 +424,9 @@ static int reclaim_pages(struct mlx5_core_dev *dev, u32 func_id, int npages, · 19 unmodified lines
398	in.func_id = cpu_to_be16(func_id);	424	in.func_id = cpu_to_be16(func_id);
399	in.num_entries = cpu_to_be32(npages);	425	in.num_entries = cpu_to_be32(npages);
400	mlx5_core_dbg(dev, "npages %d, outlen %d\n", npages, outlen);	426	mlx5_core_dbg(dev, "npages %d, outlen %d\n", npages, outlen);
401	err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);	427	err = reclaim_pages_cmd(dev, &in, sizeof(in), out, outlen);
402	if (err) {	428	if (err) {
403	mlx5_core_err(dev, "failed reclaiming pages\n");	429	mlx5_core_err(dev, "failed reclaiming pages: err %d\n", err);
404	goto out_free;
405	}
406	dev->priv.fw_pages -= npages;
407
408	if (out->hdr.status) {
409	err = mlx5_cmd_status_to_err(&out->hdr);
410	goto out_free;	430	goto out_free;
411	}	431	}
412		432
@@ -417,13 +437,15 @@ static int reclaim_pages(struct mlx5_core_dev *dev, u32 func_id, int npages, · 4 unmodified lines
417	err = -EINVAL;	437	err = -EINVAL;
418	goto out_free;	438	goto out_free;
419	}	439	}
420	if (nclaimed)
421	*nclaimed = num_claimed;
422		440
423	for (i = 0; i < num_claimed; i++) {	441	for (i = 0; i < num_claimed; i++) {
424	addr = be64_to_cpu(out->pas[i]);	442	addr = be64_to_cpu(out->pas[i]);
425	free_4k(dev, addr);	443	free_4k(dev, addr);
426	}	444	}
		445
		446	if (nclaimed)
		447	*nclaimed = num_claimed;
		448
427	dev->priv.fw_pages -= num_claimed;	449	dev->priv.fw_pages -= num_claimed;
428	if (func_id)	450	if (func_id)
429	dev->priv.vfs_pages -= num_claimed;	451	dev->priv.vfs_pages -= num_claimed;
@@ -514,14 +536,10 @@ int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev) · 84 unmodified lines
514	p = rb_first(&dev->priv.page_root);	536	p = rb_first(&dev->priv.page_root);
515	if (p) {	537	if (p) {
516	fwp = rb_entry(p, struct fw_page, rb_node);	538	fwp = rb_entry(p, struct fw_page, rb_node);
517	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {	539	err = reclaim_pages(dev, fwp->func_id,
518	free_4k(dev, fwp->addr);	540	optimal_reclaimed_pages(),
519	nclaimed = 1;	541	&nclaimed);
520	} else {	542
521	err = reclaim_pages(dev, fwp->func_id,
522	optimal_reclaimed_pages(),
523	&nclaimed);
524	}
525	if (err) {	543	if (err) {
526	mlx5_core_warn(dev, "failed reclaiming pages (%d)\n",	544	mlx5_core_warn(dev, "failed reclaiming pages (%d)\n",
527	err);	545	err);
@@ -536,6 +554,13 @@ int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev) · 8 unmodified lines
536	}	554	}
537	} while (p);	555	} while (p);
538		556
		557	WARN(dev->priv.fw_pages,
		558	"FW pages counter is %d after reclaiming all pages\n",
		559	dev->priv.fw_pages);
		560	WARN(dev->priv.vfs_pages,
		561	"VFs FW pages counter is %d after reclaiming all pages\n",
		562	dev->priv.vfs_pages);
		563
539	return 0;	564	return 0;
540	}	565	}
541		566

drivers/net/ethernet/mellanox/mlx5/core/vport.c+0−3

 {
 	int inlen = MLX5_ST_SZ_BYTES(modify_nic_vport_context_in);
 	void *nic_vport_context;
-	u8 *guid;
 	void *in;
 	int err;
 	nic_vport_context = MLX5_ADDR_OF(modify_nic_vport_context_in,
 					 in, nic_vport_context);
-	guid = MLX5_ADDR_OF(nic_vport_context, nic_vport_context,
-			    node_guid);
 	MLX5_SET64(nic_vport_context, nic_vport_context, node_guid, node_guid);
 	err = mlx5_modify_nic_vport_context(mdev, in, inlen);

drivers/net/ethernet/microchip/enc28j60.c+5−2

 			enc28j60_phy_read(priv, PHIR);
 		}
 		/* TX complete handler */
-		if ((intflags & EIR_TXIF) != 0) {
+		if (((intflags & EIR_TXIF) != 0) &&
+		    ((intflags & EIR_TXERIF) == 0)) {
 			bool err = false;
 			loop++;
 			if (netif_msg_intr(priv))
 					enc28j60_tx_clear(ndev, true);
 			} else
 				enc28j60_tx_clear(ndev, true);
-			locked_reg_bfclr(priv, EIR, EIR_TXERIF);
+			locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF);
 		}
 		/* RX Error handler */
 		if ((intflags & EIR_RXERIF) != 0) {
  */
 static void enc28j60_hw_tx(struct enc28j60_net *priv)
 {
+	BUG_ON(!priv->tx_skb);
 	if (netif_msg_tx_queued(priv))
 		printk(KERN_DEBUG DRV_NAME
 			": Tx Packet Len:%d\n", priv->tx_skb->len);

drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c+2−0

@@ -772,6 +772,8 @@ netdev_tx_t qlcnic_xmit_frame(struct sk_buff skb, struct net_device netdev) · 771 unmodified lines
772	tx_ring->tx_stats.tx_bytes += skb->len;	772	tx_ring->tx_stats.tx_bytes += skb->len;
773	tx_ring->tx_stats.xmit_called++;	773	tx_ring->tx_stats.xmit_called++;
774		774
		775	/* Ensure writes are complete before HW fetches Tx descriptors */
		776	wmb();
775	qlcnic_update_cmd_producer(tx_ring);	777	qlcnic_update_cmd_producer(tx_ring);
776		778
777	return NETDEV_TX_OK;	779	return NETDEV_TX_OK;

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+1−1

@@ -2819,7 +2819,7 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id) · 2818 unmodified lines
2819	priv->tx_path_in_lpi_mode = true;	2819	priv->tx_path_in_lpi_mode = true;
2820	if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)	2820	if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2821	priv->tx_path_in_lpi_mode = false;	2821	priv->tx_path_in_lpi_mode = false;
2822	if (status & CORE_IRQ_MTL_RX_OVERFLOW)	2822	if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2823	priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,	2823	priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2824	priv->rx_tail_addr,	2824	priv->rx_tail_addr,
2825	STMMAC_CHAN0);	2825	STMMAC_CHAN0);

drivers/net/geneve.c+7−2

@@ -1036,12 +1036,17 @@ static netdev_tx_t geneve_xmit(struct sk_buff skb, struct net_device dev) · 1035 unmodified lines
1036		1036
1037	static int __geneve_change_mtu(struct net_device *dev, int new_mtu, bool strict)	1037	static int __geneve_change_mtu(struct net_device *dev, int new_mtu, bool strict)
1038	{	1038	{
		1039	struct geneve_dev *geneve = netdev_priv(dev);
1039	/* The max_mtu calculation does not take account of GENEVE	1040	/* The max_mtu calculation does not take account of GENEVE
1040	* options, to avoid excluding potentially valid	1041	* options, to avoid excluding potentially valid
1041	* configurations.	1042	* configurations.
1042	*/	1043	*/
1043	int max_mtu = IP_MAX_MTU - GENEVE_BASE_HLEN - sizeof(struct iphdr)	1044	int max_mtu = IP_MAX_MTU - GENEVE_BASE_HLEN - dev->hard_header_len;
1044	- dev->hard_header_len;	1045
		1046	if (geneve->remote.sa.sa_family == AF_INET6)
		1047	max_mtu -= sizeof(struct ipv6hdr);
		1048	else
		1049	max_mtu -= sizeof(struct iphdr);
1045		1050
1046	if (new_mtu < 68)	1051	if (new_mtu < 68)
1047	return -EINVAL;	1052	return -EINVAL;

drivers/net/macsec.c+1−0

@@ -2640,6 +2640,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, · 2639 unmodified lines
2640	u64_stats_update_begin(&secy_stats->syncp);	2640	u64_stats_update_begin(&secy_stats->syncp);
2641	secy_stats->stats.OutPktsUntagged++;	2641	secy_stats->stats.OutPktsUntagged++;
2642	u64_stats_update_end(&secy_stats->syncp);	2642	u64_stats_update_end(&secy_stats->syncp);
		2643	skb->dev = macsec->real_dev;
2643	len = skb->len;	2644	len = skb->len;
2644	ret = dev_queue_xmit(skb);	2645	ret = dev_queue_xmit(skb);
2645	count_tx(dev, ret, len);	2646	count_tx(dev, ret, len);

drivers/net/phy/dp83867.c+9−4

 /* PHY CTRL bits */
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
+#define DP83867_PHYCR_FIFO_DEPTH_MASK		(3 << 14)
 /* RGMIIDCTL bits */
 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4
 static int dp83867_config_init(struct phy_device *phydev)
 {
 	struct dp83867_private *dp83867;
-	int ret;
+	int ret, val;
-	u16 val, delay;
+	u16 delay;
 	if (!phydev->priv) {
 		dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 	}
 	if (phy_interface_is_rgmii(phydev)) {
-		ret = phy_write(phydev, MII_DP83867_PHYCTRL,
+		val = phy_read(phydev, MII_DP83867_PHYCTRL);
-			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+		if (val < 0)
+			return val;
+		val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
+		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
+		ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 		if (ret)
 			return ret;
 	}

drivers/net/usb/cdc_ncm.c+7−0

@@ -854,6 +854,13 @@ int cdc_ncm_bind_common(struct usbnet dev, struct usb_interface intf, u8 data_ · 853 unmodified lines
854	if (cdc_ncm_init(dev))	854	if (cdc_ncm_init(dev))
855	goto error2;	855	goto error2;
856		856
		857	/* Some firmwares need a pause here or they will silently fail
		858	* to set up the interface properly. This value was decided
		859	* empirically on a Sierra Wireless MC7455 running 02.08.02.00
		860	* firmware.
		861	*/
		862	usleep_range(10000, 20000);
		863
857	/* configure data interface */	864	/* configure data interface */
858	temp = usb_set_interface(dev->udev, iface_no, data_altsetting);	865	temp = usb_set_interface(dev->udev, iface_no, data_altsetting);
859	if (temp) {	866	if (temp) {

drivers/net/usb/r8152.c+28−7

 #define NETNEXT_VERSION		"08"
 /* Information for net */
-#define NET_VERSION		"4"
+#define NET_VERSION		"5"
 #define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
 		int (*eee_set)(struct r8152 *, struct ethtool_eee *);
 		bool (*in_nway)(struct r8152 *);
 		void (*hw_phy_cfg)(struct r8152 *);
+		void (*autosuspend_en)(struct r8152 *tp, bool enable);
 	} rtl_ops;
 	int intr_interval;
 	if (enable) {
 		u32 ocp_data;
-		r8153_u1u2en(tp, false);
-		r8153_u2p3en(tp, false);
 		__rtl_set_wol(tp, WAKE_ANY);
 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 	} else {
+		u32 ocp_data;
 		__rtl_set_wol(tp, tp->saved_wolopts);
+		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
+		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
+		ocp_data &= ~LINK_OFF_WAKE_EN;
+		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
+		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
+	}
+}
+static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
+{
+	rtl_runtime_suspend_enable(tp, enable);
+	if (enable) {
+		r8153_u1u2en(tp, false);
+		r8153_u2p3en(tp, false);
+	} else {
 		r8153_u2p3en(tp, true);
 		r8153_u1u2en(tp, true);
 	}
 		napi_disable(&tp->napi);
 		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
 			rtl_stop_rx(tp);
-			rtl_runtime_suspend_enable(tp, true);
+			tp->rtl_ops.autosuspend_en(tp, true);
 		} else {
 			cancel_delayed_work_sync(&tp->schedule);
 			tp->rtl_ops.down(tp);
 	if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
 		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
-			rtl_runtime_suspend_enable(tp, false);
+			tp->rtl_ops.autosuspend_en(tp, false);
 			clear_bit(SELECTIVE_SUSPEND, &tp->flags);
 			napi_disable(&tp->napi);
 			set_bit(WORK_ENABLE, &tp->flags);
 		usb_submit_urb(tp->intr_urb, GFP_KERNEL);
 	} else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
 		if (tp->netdev->flags & IFF_UP)
-			rtl_runtime_suspend_enable(tp, false);
+			tp->rtl_ops.autosuspend_en(tp, false);
 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
 	}
 		ops->eee_set		= r8152_set_eee;
 		ops->in_nway		= rtl8152_in_nway;
 		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;
+		ops->autosuspend_en	= rtl_runtime_suspend_enable;
 		break;
 	case RTL_VER_03:
 		ops->eee_set		= r8153_set_eee;
 		ops->in_nway		= rtl8153_in_nway;
 		ops->hw_phy_cfg		= r8153_hw_phy_cfg;
+		ops->autosuspend_en	= rtl8153_runtime_enable;
 		break;
 	default:

drivers/net/usb/usbnet.c+7−3

 	dev->hard_mtu = net->mtu + net->hard_header_len;
 	if (dev->rx_urb_size == old_hard_mtu) {
 		dev->rx_urb_size = dev->hard_mtu;
-		if (dev->rx_urb_size > old_rx_urb_size)
+		if (dev->rx_urb_size > old_rx_urb_size) {
+			usbnet_pause_rx(dev);
 			usbnet_unlink_rx_urbs(dev);
+			usbnet_resume_rx(dev);
+		}
 	}
 	/* max qlen depend on hard_mtu and rx_urb_size */
 	} else if (netif_running (dev->net) &&
 		   netif_device_present (dev->net) &&
 		   netif_carrier_ok(dev->net) &&
-		   !timer_pending (&dev->delay) &&
+		   !timer_pending(&dev->delay) &&
-		   !test_bit (EVENT_RX_HALT, &dev->flags)) {
+		   !test_bit(EVENT_RX_PAUSED, &dev->flags) &&
+		   !test_bit(EVENT_RX_HALT, &dev->flags)) {
 		int	temp = dev->rxq.qlen;
 		if (temp < RX_QLEN(dev)) {

drivers/nvdimm/pfn_devs.c+40−11

 int nd_pfn_validate(struct nd_pfn *nd_pfn, const char *sig)
 {
 	u64 checksum, offset;
+	unsigned long align;
+	enum nd_pfn_mode mode;
 	struct nd_namespace_io *nsio;
 	struct nd_pfn_sb *pfn_sb = nd_pfn->pfn_sb;
 	struct nd_namespace_common *ndns = nd_pfn->ndns;
 		return -ENXIO;
 	}
+	align = le32_to_cpu(pfn_sb->align);
+	offset = le64_to_cpu(pfn_sb->dataoff);
+	if (align == 0)
+		align = 1UL << ilog2(offset);
+	mode = le32_to_cpu(pfn_sb->mode);
 	if (!nd_pfn->uuid) {
-		/* from probe we allocate */
+		/*
+		 * When probing a namepace via nd_pfn_probe() the uuid
+		 * is NULL (see: nd_pfn_devinit()) we init settings from
+		 * pfn_sb
+		 */
 		nd_pfn->uuid = kmemdup(pfn_sb->uuid, 16, GFP_KERNEL);
 		if (!nd_pfn->uuid)
 			return -ENOMEM;
+		nd_pfn->align = align;
+		nd_pfn->mode = mode;
 	} else {
-		/* from init we validate */
+		/*
+		 * When probing a pfn / dax instance we validate the
+		 * live settings against the pfn_sb
+		 */
 		if (memcmp(nd_pfn->uuid, pfn_sb->uuid, 16) != 0)
 			return -ENODEV;
+		/*
+		 * If the uuid validates, but other settings mismatch
+		 * return EINVAL because userspace has managed to change
+		 * the configuration without specifying new
+		 * identification.
+		 */
+		if (nd_pfn->align != align || nd_pfn->mode != mode) {
+			dev_err(&nd_pfn->dev,
+					"init failed, settings mismatch\n");
+			dev_dbg(&nd_pfn->dev, "align: %lx:%lx mode: %d:%d\n",
+					nd_pfn->align, align, nd_pfn->mode,
+					mode);
+			return -EINVAL;
+		}
 	}
-	if (nd_pfn->align == 0)
+	if (align > nvdimm_namespace_capacity(ndns)) {
-		nd_pfn->align = le32_to_cpu(pfn_sb->align);
-	if (nd_pfn->align > nvdimm_namespace_capacity(ndns)) {
 		dev_err(&nd_pfn->dev, "alignment: %lx exceeds capacity %llx\n",
-				nd_pfn->align, nvdimm_namespace_capacity(ndns));
+				align, nvdimm_namespace_capacity(ndns));
 		return -EINVAL;
 	}
 	 * namespace has changed since the pfn superblock was
 	 * established.
 	 */
-	offset = le64_to_cpu(pfn_sb->dataoff);
 	nsio = to_nd_namespace_io(&ndns->dev);
 	if (offset >= resource_size(&nsio->res)) {
 		dev_err(&nd_pfn->dev, "pfn array size exceeds capacity of %s\n",
 		return -EBUSY;
 	}
-	if ((nd_pfn->align && !IS_ALIGNED(offset, nd_pfn->align))
+	if ((align && !IS_ALIGNED(offset, align))
 			|| !IS_ALIGNED(offset, PAGE_SIZE)) {
-		dev_err(&nd_pfn->dev, "bad offset: %#llx dax disabled\n",
+		dev_err(&nd_pfn->dev,
-				offset);
+				"bad offset: %#llx dax disabled align: %#lx\n",
+				offset, align);
 		return -ENXIO;
 	}
 	res->start += start_pad;
 	res->end -= end_trunc;
-	nd_pfn->mode = le32_to_cpu(nd_pfn->pfn_sb->mode);
 	if (nd_pfn->mode == PFN_MODE_RAM) {
 		if (offset < SZ_8K)
 			return ERR_PTR(-EINVAL);

drivers/phy/phy-bcm-ns-usb2.c+2−2

@@ -109,8 +109,8 @@ static int bcm_ns_usb2_probe(struct platform_device *pdev) · 108 unmodified lines
109	}	109	}
110		110
111	usb2->phy = devm_phy_create(dev, NULL, &ops);	111	usb2->phy = devm_phy_create(dev, NULL, &ops);
112	if (IS_ERR(dev))	112	if (IS_ERR(usb2->phy))
113	return PTR_ERR(dev);	113	return PTR_ERR(usb2->phy);
114		114
115	phy_set_drvdata(usb2->phy, usb2);	115	phy_set_drvdata(usb2->phy, usb2);
116	platform_set_drvdata(pdev, usb2);	116	platform_set_drvdata(pdev, usb2);

drivers/phy/phy-miphy28lp.c+2−1

@@ -1143,7 +1143,8 @@ static int miphy28lp_probe_resets(struct device_node *node, · 1142 unmodified lines
1143	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;	1143	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1144	int err;	1144	int err;
1145		1145
1146	miphy_phy->miphy_rst = of_reset_control_get(node, "miphy-sw-rst");	1146	miphy_phy->miphy_rst =
		1147	of_reset_control_get_shared(node, "miphy-sw-rst");
1147		1148
1148	if (IS_ERR(miphy_phy->miphy_rst)) {	1149	if (IS_ERR(miphy_phy->miphy_rst)) {
1149	dev_err(miphy_dev->dev,	1150	dev_err(miphy_dev->dev,

drivers/phy/phy-rcar-gen3-usb2.c+1−13

 	extcon_set_cable_state_(ch->extcon, EXTCON_USB, true);
 }
-static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch)
-{
-	return !!(readl(ch->base + USB2_ADPCTRL) &
-		  USB2_ADPCTRL_OTGSESSVLD);
-}
 static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
 {
 	return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
 static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
 {
-	bool is_host = true;
+	if (!rcar_gen3_check_id(ch))
-	/* B-device? */
-	if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch))
-		is_host = false;
-	if (is_host)
 		rcar_gen3_init_for_host(ch);
 	else
 		rcar_gen3_init_for_peri(ch);

drivers/phy/phy-rockchip-dp.c+1−1

@@ -90,7 +90,7 @@ static int rockchip_dp_phy_probe(struct platform_device *pdev) · 89 unmodified lines
90	return -ENODEV;	90	return -ENODEV;
91		91
92	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);	92	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
93	if (IS_ERR(dp))	93	if (!dp)
94	return -ENOMEM;	94	return -ENOMEM;
95		95
96	dp->dev = dev;	96	dp->dev = dev;

drivers/phy/phy-stih407-usb.c+2−2

@@ -105,13 +105,13 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev) · 104 unmodified lines
105	phy_dev->dev = dev;	105	phy_dev->dev = dev;
106	dev_set_drvdata(dev, phy_dev);	106	dev_set_drvdata(dev, phy_dev);
107		107
108	phy_dev->rstc = devm_reset_control_get(dev, "global");	108	phy_dev->rstc = devm_reset_control_get_shared(dev, "global");
109	if (IS_ERR(phy_dev->rstc)) {	109	if (IS_ERR(phy_dev->rstc)) {
110	dev_err(dev, "failed to ctrl picoPHY reset\n");	110	dev_err(dev, "failed to ctrl picoPHY reset\n");
111	return PTR_ERR(phy_dev->rstc);	111	return PTR_ERR(phy_dev->rstc);
112	}	112	}
113		113
114	phy_dev->rstport = devm_reset_control_get(dev, "port");	114	phy_dev->rstport = devm_reset_control_get_exclusive(dev, "port");
115	if (IS_ERR(phy_dev->rstport)) {	115	if (IS_ERR(phy_dev->rstport)) {
116	dev_err(dev, "failed to ctrl picoPHY reset\n");	116	dev_err(dev, "failed to ctrl picoPHY reset\n");
117	return PTR_ERR(phy_dev->rstport);	117	return PTR_ERR(phy_dev->rstport);

drivers/phy/phy-sun4i-usb.c+7−7

drivers/platform/chrome/cros_ec_dev.c+7−1

 		goto exit;
 	}
+	if (u_cmd.outsize != s_cmd->outsize ||
+	    u_cmd.insize != s_cmd->insize) {
+		ret = -EINVAL;
+		goto exit;
+	}
 	s_cmd->command += ec->cmd_offset;
 	ret = cros_ec_cmd_xfer(ec->ec_dev, s_cmd);
 	/* Only copy data to userland if data was received. */
 	if (ret < 0)
 		goto exit;
-	if (copy_to_user(arg, s_cmd, sizeof(*s_cmd) + u_cmd.insize))
+	if (copy_to_user(arg, s_cmd, sizeof(*s_cmd) + s_cmd->insize))
 		ret = -EFAULT;
 exit:
 	kfree(s_cmd);

drivers/regulator/anatop-regulator.c+1−1

@@ -296,7 +296,7 @@ static int anatop_regulator_probe(struct platform_device *pdev) · 295 unmodified lines
296	if (!sreg->sel && !strcmp(sreg->name, "vddpu"))	296	if (!sreg->sel && !strcmp(sreg->name, "vddpu"))
297	sreg->sel = 22;	297	sreg->sel = 22;
298		298
299	if (!sreg->sel) {	299	if (!sreg->bypass && !sreg->sel) {
300	dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");	300	dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
301	return -EINVAL;	301	return -EINVAL;
302	}	302	}

drivers/regulator/max77620-regulator.c+6−1

 	unsigned int val;
 	int ret;
+	if (!rinfo)
+		return 0;
 	switch (fps_src) {
 	case MAX77620_FPS_SRC_0:
 	case MAX77620_FPS_SRC_1:
 	int pd = rpdata->active_fps_pd_slot;
 	int ret = 0;
+	if (!rinfo)
+		return 0;
 	if (is_suspend) {
 		pu = rpdata->suspend_fps_pu_slot;
 		pd = rpdata->suspend_fps_pd_slot;
 	RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1),
 	RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
 	RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
-	RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
 	RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
 	RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),

drivers/s390/net/qeth_l2_main.c+1−0

@@ -1045,6 +1045,7 @@ static void qeth_l2_remove_device(struct ccwgroup_device *cgdev) · 1044 unmodified lines
1045	qeth_l2_set_offline(cgdev);	1045	qeth_l2_set_offline(cgdev);
1046		1046
1047	if (card->dev) {	1047	if (card->dev) {
		1048	netif_napi_del(&card->napi);
1048	unregister_netdev(card->dev);	1049	unregister_netdev(card->dev);
1049	card->dev = NULL;	1050	card->dev = NULL;
1050	}	1051	}

drivers/s390/net/qeth_l3_main.c+1−0

@@ -3167,6 +3167,7 @@ static void qeth_l3_remove_device(struct ccwgroup_device *cgdev) · 3166 unmodified lines
3167	qeth_l3_set_offline(cgdev);	3167	qeth_l3_set_offline(cgdev);
3168		3168
3169	if (card->dev) {	3169	if (card->dev) {
		3170	netif_napi_del(&card->napi);
3170	unregister_netdev(card->dev);	3171	unregister_netdev(card->dev);
3171	card->dev = NULL;	3172	card->dev = NULL;
3172	}	3173	}

drivers/spi/spi-rockchip.c+3−1

 		struct spi_device *spi,
 		struct spi_transfer *xfer)
 {
-	int ret = 1;
+	int ret = 0;
 	struct rockchip_spi *rs = spi_master_get_devdata(master);
 	WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 			spi_enable_chip(rs, 1);
 			ret = rockchip_spi_prepare_dma(rs);
 		}
+		/* successful DMA prepare means the transfer is in progress */
+		ret = ret ? ret : 1;
 	} else {
 		spi_enable_chip(rs, 1);
 		ret = rockchip_spi_pio_transfer(rs);

drivers/spi/spi-sun4i.c+19−4

 {
 	struct sun4i_spi *sspi = spi_master_get_devdata(master);
 	unsigned int mclk_rate, div, timeout;
+	unsigned int start, end, tx_time;
 	unsigned int tx_len = 0;
 	int ret = 0;
 	u32 reg;
 	/* We don't support transfer larger than the FIFO */
 	if (tfr->len > SUN4I_FIFO_DEPTH)
-		return -EINVAL;
+		return -EMSGSIZE;
+	if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)
+		return -EMSGSIZE;
 	reinit_completion(&sspi->done);
 	sspi->tx_buf = tfr->tx_buf;
 	sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
 	sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
-	/* Fill the TX FIFO */
+	/*
-	sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
+	 * Fill the TX FIFO
+	 * Filling the FIFO fully causes timeout for some reason
+	 * at least on spi2 on A10s
+	 */
+	sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
 	/* Enable the interrupts */
 	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
 	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 	sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
+	tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
+	start = jiffies;
 	timeout = wait_for_completion_timeout(&sspi->done,
-					      msecs_to_jiffies(1000));
+					      msecs_to_jiffies(tx_time));
+	end = jiffies;
 	if (!timeout) {
+		dev_warn(&master->dev,
+			 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
+			 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
+			 jiffies_to_msecs(end - start), tx_time);
 		ret = -ETIMEDOUT;
 		goto out;
 	}

drivers/spi/spi-sun6i.c+9−1

 {
 	struct sun6i_spi *sspi = spi_master_get_devdata(master);
 	unsigned int mclk_rate, div, timeout;
+	unsigned int start, end, tx_time;
 	unsigned int tx_len = 0;
 	int ret = 0;
 	u32 reg;
 	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
+	tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
+	start = jiffies;
 	timeout = wait_for_completion_timeout(&sspi->done,
-					      msecs_to_jiffies(1000));
+					      msecs_to_jiffies(tx_time));
+	end = jiffies;
 	if (!timeout) {
+		dev_warn(&master->dev,
+			 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
+			 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
+			 jiffies_to_msecs(end - start), tx_time);
 		ret = -ETIMEDOUT;
 		goto out;
 	}

drivers/spi/spi-ti-qspi.c+7−0

@@ -646,6 +646,13 @@ free_master: · 645 unmodified lines
646		646
647	static int ti_qspi_remove(struct platform_device *pdev)	647	static int ti_qspi_remove(struct platform_device *pdev)
648	{	648	{
		649	struct ti_qspi *qspi = platform_get_drvdata(pdev);
		650	int rc;
		651
		652	rc = spi_master_suspend(qspi->master);
		653	if (rc)
		654	return rc;
		655
649	pm_runtime_put_sync(&pdev->dev);	656	pm_runtime_put_sync(&pdev->dev);
650	pm_runtime_disable(&pdev->dev);	657	pm_runtime_disable(&pdev->dev);
651		658

drivers/staging/iio/accel/sca3000_core.c+1−1

@@ -594,7 +594,7 @@ static ssize_t sca3000_read_frequency(struct device *dev, · 593 unmodified lines
594	goto error_ret_mut;	594	goto error_ret_mut;
595	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);	595	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
596	mutex_unlock(&st->lock);	596	mutex_unlock(&st->lock);
597	if (ret)	597	if (ret < 0)
598	goto error_ret;	598	goto error_ret;
599	val = ret;	599	val = ret;
600	if (base_freq > 0)	600	if (base_freq > 0)

drivers/staging/iio/adc/ad7606_spi.c+1−1

@@ -21,7 +21,7 @@ static int ad7606_spi_read_block(struct device *dev, · 20 unmodified lines
21	{	21	{
22	struct spi_device *spi = to_spi_device(dev);	22	struct spi_device *spi = to_spi_device(dev);
23	int i, ret;	23	int i, ret;
24	unsigned short *data;	24	unsigned short *data = buf;
25	__be16 *bdata = buf;	25	__be16 *bdata = buf;
26		26
27	ret = spi_read(spi, buf, count * 2);	27	ret = spi_read(spi, buf, count * 2);

drivers/staging/iio/impedance-analyzer/ad5933.c+3−3

 		st->settling_cycles = val;
 		/* 2x, 4x handling, see datasheet */
-		if (val > 511)
+		if (val > 1022)
-			val = (val >> 1) | (1 << 9);
-		else if (val > 1022)
 			val = (val >> 2) | (3 << 9);
+		else if (val > 511)
+			val = (val >> 1) | (1 << 9);
 		dat = cpu_to_be16(val);
 		ret = ad5933_i2c_write(st->client,

drivers/tty/pty.c+5−2

@@ -667,8 +667,11 @@ static void pty_unix98_remove(struct tty_driver driver, struct tty_struct tty) · 666 unmodified lines
667	fsi = tty->driver_data;	667	fsi = tty->driver_data;
668	else	668	else
669	fsi = tty->link->driver_data;	669	fsi = tty->link->driver_data;
670	devpts_kill_index(fsi, tty->index);	670
671	devpts_release(fsi);	671	if (fsi) {
		672	devpts_kill_index(fsi, tty->index);
		673	devpts_release(fsi);
		674	}
672	}	675	}
673		676
674	static const struct tty_operations ptm_unix98_ops = {	677	static const struct tty_operations ptm_unix98_ops = {

drivers/tty/vt/vt.c+1−0

@@ -750,6 +750,7 @@ static void visual_init(struct vc_data *vc, int num, int init) · 749 unmodified lines
750	vc->vc_complement_mask = 0;	750	vc->vc_complement_mask = 0;
751	vc->vc_can_do_color = 0;	751	vc->vc_can_do_color = 0;
752	vc->vc_panic_force_write = false;	752	vc->vc_panic_force_write = false;
		753	vc->vc_cur_blink_ms = DEFAULT_CURSOR_BLINK_MS;
753	vc->vc_sw->con_init(vc, init);	754	vc->vc_sw->con_init(vc, init);
754	if (!vc->vc_complement_mask)	755	if (!vc->vc_complement_mask)
755	vc->vc_complement_mask = vc->vc_can_do_color ? 0x7700 : 0x0800;	756	vc->vc_complement_mask = vc->vc_can_do_color ? 0x7700 : 0x0800;

drivers/usb/common/usb-otg-fsm.c+2−0

  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
+#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/mutex.h>
 	return fsm->state_changed;
 }
 EXPORT_SYMBOL_GPL(otg_statemachine);
+MODULE_LICENSE("GPL");

drivers/usb/core/hcd.c+7−10

  * Don't deallocate the bandwidth_mutex until the last shared usb_hcd is
  * deallocated.
  *
- * Make sure to only deallocate the bandwidth_mutex when the primary HCD is
+ * Make sure to deallocate the bandwidth_mutex only when the last HCD is
- * freed.  When hcd_release() is called for either hcd in a peer set
+ * freed.  When hcd_release() is called for either hcd in a peer set,
- * invalidate the peer's ->shared_hcd and ->primary_hcd pointers to
+ * invalidate the peer's ->shared_hcd and ->primary_hcd pointers.
- * block new peering attempts
  */
 static void hcd_release(struct kref *kref)
 {
 	struct usb_hcd *hcd = container_of (kref, struct usb_hcd, kref);
 	mutex_lock(&usb_port_peer_mutex);
-	if (usb_hcd_is_primary_hcd(hcd)) {
-		kfree(hcd->address0_mutex);
-		kfree(hcd->bandwidth_mutex);
-	}
 	if (hcd->shared_hcd) {
 		struct usb_hcd *peer = hcd->shared_hcd;
 		peer->shared_hcd = NULL;
-		if (peer->primary_hcd == hcd)
+		peer->primary_hcd = NULL;
-			peer->primary_hcd = NULL;
+	} else {
+		kfree(hcd->address0_mutex);
+		kfree(hcd->bandwidth_mutex);
 	}
 	mutex_unlock(&usb_port_peer_mutex);
 	kfree(hcd);

drivers/usb/dwc3/dwc3-st.c+4−2

 	dev_vdbg(&pdev->dev, "glue-logic addr 0x%p, syscfg-reg offset 0x%x\n",
 		 dwc3_data->glue_base, dwc3_data->syscfg_reg_off);
-	dwc3_data->rstc_pwrdn = devm_reset_control_get(dev, "powerdown");
+	dwc3_data->rstc_pwrdn =
+		devm_reset_control_get_exclusive(dev, "powerdown");
 	if (IS_ERR(dwc3_data->rstc_pwrdn)) {
 		dev_err(&pdev->dev, "could not get power controller\n");
 		ret = PTR_ERR(dwc3_data->rstc_pwrdn);
 	/* Manage PowerDown */
 	reset_control_deassert(dwc3_data->rstc_pwrdn);
-	dwc3_data->rstc_rst = devm_reset_control_get(dev, "softreset");
+	dwc3_data->rstc_rst =
+		devm_reset_control_get_shared(dev, "softreset");
 	if (IS_ERR(dwc3_data->rstc_rst)) {
 		dev_err(&pdev->dev, "could not get reset controller\n");
 		ret = PTR_ERR(dwc3_data->rstc_rst);

drivers/usb/host/ehci-st.c+4−2

 		priv->clk48 = NULL;
 	}
-	priv->pwr = devm_reset_control_get_optional(&dev->dev, "power");
+	priv->pwr =
+		devm_reset_control_get_optional_shared(&dev->dev, "power");
 	if (IS_ERR(priv->pwr)) {
 		err = PTR_ERR(priv->pwr);
 		if (err == -EPROBE_DEFER)
 		priv->pwr = NULL;
 	}
-	priv->rst = devm_reset_control_get_optional(&dev->dev, "softreset");
+	priv->rst =
+		devm_reset_control_get_optional_shared(&dev->dev, "softreset");
 	if (IS_ERR(priv->rst)) {
 		err = PTR_ERR(priv->rst);
 		if (err == -EPROBE_DEFER)

drivers/usb/host/ohci-st.c+4−2

 		priv->clk48 = NULL;
 	}
-	priv->pwr = devm_reset_control_get_optional(&dev->dev, "power");
+	priv->pwr =
+		devm_reset_control_get_optional_shared(&dev->dev, "power");
 	if (IS_ERR(priv->pwr)) {
 		err = PTR_ERR(priv->pwr);
 		goto err_put_clks;
 	}
-	priv->rst = devm_reset_control_get_optional(&dev->dev, "softreset");
+	priv->rst =
+		devm_reset_control_get_optional_shared(&dev->dev, "softreset");
 	if (IS_ERR(priv->rst)) {
 		err = PTR_ERR(priv->rst);
 		goto err_put_clks;

fs/9p/vfs_file.c+3−3

@@ -74,7 +74,7 @@ int v9fs_file_open(struct inode inode, struct file file) · 73 unmodified lines
74	v9fs_proto_dotu(v9ses));	74	v9fs_proto_dotu(v9ses));
75	fid = file->private_data;	75	fid = file->private_data;
76	if (!fid) {	76	if (!fid) {
77	fid = v9fs_fid_clone(file->f_path.dentry);	77	fid = v9fs_fid_clone(file_dentry(file));
78	if (IS_ERR(fid))	78	if (IS_ERR(fid))
79	return PTR_ERR(fid);	79	return PTR_ERR(fid);
80		80
@@ -100,7 +100,7 @@ int v9fs_file_open(struct inode inode, struct file file) · 19 unmodified lines
100	* because we want write after unlink usecase	100	* because we want write after unlink usecase
101	* to work.	101	* to work.
102	*/	102	*/
103	fid = v9fs_writeback_fid(file->f_path.dentry);	103	fid = v9fs_writeback_fid(file_dentry(file));
104	if (IS_ERR(fid)) {	104	if (IS_ERR(fid)) {
105	err = PTR_ERR(fid);	105	err = PTR_ERR(fid);
106	mutex_unlock(&v9inode->v_mutex);	106	mutex_unlock(&v9inode->v_mutex);
@@ -516,7 +516,7 @@ v9fs_mmap_file_mmap(struct file filp, struct vm_area_struct vma) · 409 unmodified lines
516	* because we want write after unlink usecase	516	* because we want write after unlink usecase
517	* to work.	517	* to work.
518	*/	518	*/
519	fid = v9fs_writeback_fid(filp->f_path.dentry);	519	fid = v9fs_writeback_fid(file_dentry(filp));
520	if (IS_ERR(fid)) {	520	if (IS_ERR(fid)) {
521	retval = PTR_ERR(fid);	521	retval = PTR_ERR(fid);
522	mutex_unlock(&v9inode->v_mutex);	522	mutex_unlock(&v9inode->v_mutex);

fs/ceph/export.c+3−7

 	}
 	dentry = d_obtain_alias(inode);
-	if (IS_ERR(dentry)) {
+	if (IS_ERR(dentry))
-		iput(inode);
 		return dentry;
-	}
 	err = ceph_init_dentry(dentry);
 	if (err < 0) {
 		dput(dentry);
 		return ERR_PTR(-ENOENT);
 	dentry = d_obtain_alias(inode);
-	if (IS_ERR(dentry)) {
+	if (IS_ERR(dentry))
-		iput(inode);
 		return dentry;
-	}
 	err = ceph_init_dentry(dentry);
 	if (err < 0) {
 		dput(dentry);
 	dout("fh_to_parent %llx\n", cfh->parent_ino);
 	dentry = __get_parent(sb, NULL, cfh->ino);
-	if (IS_ERR(dentry) && PTR_ERR(dentry) == -ENOENT)
+	if (unlikely(dentry == ERR_PTR(-ENOENT)))
 		dentry = __fh_to_dentry(sb, cfh->parent_ino);
 	return dentry;
 }

fs/dax.c+6−1

 				dax.addr += first;
 				size = map_len - first;
 			}
-			max = min(pos + size, end);
+			/*
+			 * pos + size is one past the last offset for IO,
+			 * so pos + size can overflow loff_t at extreme offsets.
+			 * Cast to u64 to catch this and get the true minimum.
+			 */
+			max = min_t(u64, pos + size, end);
 		}
 		if (iov_iter_rw(iter) == WRITE) {

fs/fuse/dir.c+4−0

 	struct dentry *newent;
 	bool outarg_valid = true;
+	fuse_lock_inode(dir);
 	err = fuse_lookup_name(dir->i_sb, get_node_id(dir), &entry->d_name,
 			       &outarg, &inode);
+	fuse_unlock_inode(dir);
 	if (err == -ENOENT) {
 		outarg_valid = false;
 		err = 0;
 		fuse_read_fill(req, file, ctx->pos, PAGE_SIZE,
 			       FUSE_READDIR);
 	}
+	fuse_lock_inode(inode);
 	fuse_request_send(fc, req);
+	fuse_unlock_inode(inode);
 	nbytes = req->out.args[0].size;
 	err = req->out.h.error;
 	fuse_put_request(fc, req);

fs/fuse/fuse_i.h+9−0

 	/** Miscellaneous bits describing inode state */
 	unsigned long state;
+	/** Lock for serializing lookup and readdir for back compatibility*/
+	struct mutex mutex;
 };
 /** FUSE inode state bits */
 	/** write-back cache policy (default is write-through) */
 	unsigned writeback_cache:1;
+	/** allow parallel lookups and readdir (default is serialized) */
+	unsigned parallel_dirops:1;
 	/*
 	 * The following bitfields are only for optimization purposes
 	 * and hence races in setting them will not cause malfunction
 void fuse_set_initialized(struct fuse_conn *fc);
+void fuse_unlock_inode(struct inode *inode);
+void fuse_lock_inode(struct inode *inode);
 #endif /* _FS_FUSE_I_H */

fs/fuse/inode.c+18−1

 	INIT_LIST_HEAD(&fi->queued_writes);
 	INIT_LIST_HEAD(&fi->writepages);
 	init_waitqueue_head(&fi->page_waitq);
+	mutex_init(&fi->mutex);
 	fi->forget = fuse_alloc_forget();
 	if (!fi->forget) {
 		kmem_cache_free(fuse_inode_cachep, inode);
 	struct fuse_inode *fi = get_fuse_inode(inode);
 	BUG_ON(!list_empty(&fi->write_files));
 	BUG_ON(!list_empty(&fi->queued_writes));
+	mutex_destroy(&fi->mutex);
 	kfree(fi->forget);
 	call_rcu(&inode->i_rcu, fuse_i_callback);
 }
 	return 0;
 }
+void fuse_lock_inode(struct inode *inode)
+{
+	if (!get_fuse_conn(inode)->parallel_dirops)
+		mutex_lock(&get_fuse_inode(inode)->mutex);
+}
+void fuse_unlock_inode(struct inode *inode)
+{
+	if (!get_fuse_conn(inode)->parallel_dirops)
+		mutex_unlock(&get_fuse_inode(inode)->mutex);
+}
 static void fuse_umount_begin(struct super_block *sb)
 {
 	fuse_abort_conn(get_fuse_conn_super(sb));
 				fc->async_dio = 1;
 			if (arg->flags & FUSE_WRITEBACK_CACHE)
 				fc->writeback_cache = 1;
+			if (arg->flags & FUSE_PARALLEL_DIROPS)
+				fc->parallel_dirops = 1;
 			if (arg->time_gran && arg->time_gran <= 1000000000)
 				fc->sb->s_time_gran = arg->time_gran;
 		} else {
 		FUSE_SPLICE_WRITE | FUSE_SPLICE_MOVE | FUSE_SPLICE_READ |
 		FUSE_FLOCK_LOCKS | FUSE_IOCTL_DIR | FUSE_AUTO_INVAL_DATA |
 		FUSE_DO_READDIRPLUS | FUSE_READDIRPLUS_AUTO | FUSE_ASYNC_DIO |
-		FUSE_WRITEBACK_CACHE | FUSE_NO_OPEN_SUPPORT;
+		FUSE_WRITEBACK_CACHE | FUSE_NO_OPEN_SUPPORT |
+		FUSE_PARALLEL_DIROPS;
 	req->in.h.opcode = FUSE_INIT;
 	req->in.numargs = 1;
 	req->in.args[0].size = sizeof(*arg);

fs/libfs.c+71−38

 }
 EXPORT_SYMBOL(dcache_dir_close);
+/* parent is locked at least shared */
+static struct dentry *next_positive(struct dentry *parent,
+				    struct list_head *from,
+				    int count)
+{
+	unsigned *seq = &parent->d_inode->i_dir_seq, n;
+	struct dentry *res;
+	struct list_head *p;
+	bool skipped;
+	int i;
+retry:
+	i = count;
+	skipped = false;
+	n = smp_load_acquire(seq) & ~1;
+	res = NULL;
+	rcu_read_lock();
+	for (p = from->next; p != &parent->d_subdirs; p = p->next) {
+		struct dentry *d = list_entry(p, struct dentry, d_child);
+		if (!simple_positive(d)) {
+			skipped = true;
+		} else if (!--i) {
+			res = d;
+			break;
+		}
+	}
+	rcu_read_unlock();
+	if (skipped) {
+		smp_rmb();
+		if (unlikely(*seq != n))
+			goto retry;
+	}
+	return res;
+}
+static void move_cursor(struct dentry *cursor, struct list_head *after)
+{
+	struct dentry *parent = cursor->d_parent;
+	unsigned n, *seq = &parent->d_inode->i_dir_seq;
+	spin_lock(&parent->d_lock);
+	for (;;) {
+		n = *seq;
+		if (!(n & 1) && cmpxchg(seq, n, n + 1) == n)
+			break;
+		cpu_relax();
+	}
+	__list_del(cursor->d_child.prev, cursor->d_child.next);
+	if (after)
+		list_add(&cursor->d_child, after);
+	else
+		list_add_tail(&cursor->d_child, &parent->d_subdirs);
+	smp_store_release(seq, n + 2);
+	spin_unlock(&parent->d_lock);
+}
 loff_t dcache_dir_lseek(struct file *file, loff_t offset, int whence)
 {
 	struct dentry *dentry = file->f_path.dentry;
 	if (offset != file->f_pos) {
 		file->f_pos = offset;
 		if (file->f_pos >= 2) {
-			struct list_head *p;
 			struct dentry *cursor = file->private_data;
+			struct dentry *to;
 			loff_t n = file->f_pos - 2;
-			spin_lock(&dentry->d_lock);
+			inode_lock_shared(dentry->d_inode);
-			/* d_lock not required for cursor */
+			to = next_positive(dentry, &dentry->d_subdirs, n);
-			list_del(&cursor->d_child);
+			move_cursor(cursor, to ? &to->d_child : NULL);
-			p = dentry->d_subdirs.next;
+			inode_unlock_shared(dentry->d_inode);
-			while (n && p != &dentry->d_subdirs) {
-				struct dentry *next;
-				next = list_entry(p, struct dentry, d_child);
-				spin_lock_nested(&next->d_lock, DENTRY_D_LOCK_NESTED);
-				if (simple_positive(next))
-					n--;
-				spin_unlock(&next->d_lock);
-				p = p->next;
-			}
-			list_add_tail(&cursor->d_child, p);
-			spin_unlock(&dentry->d_lock);
 		}
 	}
 	return offset;
 {
 	struct dentry *dentry = file->f_path.dentry;
 	struct dentry *cursor = file->private_data;
-	struct list_head *p, *q = &cursor->d_child;
+	struct list_head *p = &cursor->d_child;
+	struct dentry *next;
+	bool moved = false;
 	if (!dir_emit_dots(file, ctx))
 		return 0;
-	spin_lock(&dentry->d_lock);
-	if (ctx->pos == 2)
-		list_move(q, &dentry->d_subdirs);
-	for (p = q->next; p != &dentry->d_subdirs; p = p->next) {
+	if (ctx->pos == 2)
-		struct dentry *next = list_entry(p, struct dentry, d_child);
+		p = &dentry->d_subdirs;
-		spin_lock_nested(&next->d_lock, DENTRY_D_LOCK_NESTED);
+	while ((next = next_positive(dentry, p, 1)) != NULL) {
-		if (!simple_positive(next)) {
-			spin_unlock(&next->d_lock);
-			continue;
-		}
-		spin_unlock(&next->d_lock);
-		spin_unlock(&dentry->d_lock);
 		if (!dir_emit(ctx, next->d_name.name, next->d_name.len,
 			      d_inode(next)->i_ino, dt_type(d_inode(next))))
-			return 0;
+			break;
-		spin_lock(&dentry->d_lock);
+		moved = true;
-		spin_lock_nested(&next->d_lock, DENTRY_D_LOCK_NESTED);
+		p = &next->d_child;
-		/* next is still alive */
-		list_move(q, p);
-		spin_unlock(&next->d_lock);
-		p = q;
 		ctx->pos++;
 	}
-	spin_unlock(&dentry->d_lock);
+	if (moved)
+		move_cursor(cursor, p);
 	return 0;
 }
 EXPORT_SYMBOL(dcache_readdir);

fs/lockd/svc.c+10−3

 };
 #endif
-static void lockd_svc_exit_thread(void)
+static void lockd_unregister_notifiers(void)
 {
 	unregister_inetaddr_notifier(&lockd_inetaddr_notifier);
 #if IS_ENABLED(CONFIG_IPV6)
 	unregister_inet6addr_notifier(&lockd_inet6addr_notifier);
 #endif
+}
+static void lockd_svc_exit_thread(void)
+{
+	lockd_unregister_notifiers();
 	svc_exit_thread(nlmsvc_rqst);
 }
 	 * Note: svc_serv structures have an initial use count of 1,
 	 * so we exit through here on both success and failure.
 	 */
-err_net:
+err_put:
 	svc_destroy(serv);
 err_create:
 	mutex_unlock(&nlmsvc_mutex);
 err_start:
 	lockd_down_net(serv, net);
-	goto err_net;
+err_net:
+	lockd_unregister_notifiers();
+	goto err_put;
 }
 EXPORT_SYMBOL_GPL(lockd_up);

fs/locks.c+1−1

@@ -1628,7 +1628,7 @@ generic_add_lease(struct file filp, long arg, struct file_lock flp, void *pr · 1627 unmodified lines
1628	{	1628	{
1629	struct file_lock fl, my_fl = NULL, *lease;	1629	struct file_lock fl, my_fl = NULL, *lease;
1630	struct dentry *dentry = filp->f_path.dentry;	1630	struct dentry *dentry = filp->f_path.dentry;
1631	struct inode *inode = dentry->d_inode;	1631	struct inode *inode = file_inode(filp);
1632	struct file_lock_context *ctx;	1632	struct file_lock_context *ctx;
1633	bool is_deleg = (*flp)->fl_flags & FL_DELEG;	1633	bool is_deleg = (*flp)->fl_flags & FL_DELEG;
1634	int error;	1634	int error;

fs/namespace.c+1−0

@@ -1562,6 +1562,7 @@ void __detach_mounts(struct dentry *dentry) · 1561 unmodified lines
1562	goto out_unlock;	1562	goto out_unlock;
1563		1563
1564	lock_mount_hash();	1564	lock_mount_hash();
		1565	event++;
1565	while (!hlist_empty(&mp->m_list)) {	1566	while (!hlist_empty(&mp->m_list)) {
1566	mnt = hlist_entry(mp->m_list.first, struct mount, mnt_mp_list);	1567	mnt = hlist_entry(mp->m_list.first, struct mount, mnt_mp_list);
1567	if (mnt->mnt.mnt_flags & MNT_UMOUNT) {	1568	if (mnt->mnt.mnt_flags & MNT_UMOUNT) {

fs/overlayfs/inode.c+26−3

 	if (err)
 		goto out;
+	if (attr->ia_valid & ATTR_SIZE) {
+		struct inode *realinode = d_inode(ovl_dentry_real(dentry));
+		err = -ETXTBSY;
+		if (atomic_read(&realinode->i_writecount) < 0)
+			goto out_drop_write;
+	}
 	err = ovl_copy_up(dentry);
 	if (!err) {
+		struct inode *winode = NULL;
 		upperdentry = ovl_dentry_upper(dentry);
+		if (attr->ia_valid & ATTR_SIZE) {
+			winode = d_inode(upperdentry);
+			err = get_write_access(winode);
+			if (err)
+				goto out_drop_write;
+		}
 		inode_lock(upperdentry->d_inode);
 		err = notify_change(upperdentry, attr, NULL);
 		if (!err)
 			ovl_copyattr(upperdentry->d_inode, dentry->d_inode);
 		inode_unlock(upperdentry->d_inode);
+		if (winode)
+			put_write_access(winode);
 	}
+out_drop_write:
 	ovl_drop_write(dentry);
 out:
 	return err;
 		err = vfs_getattr(&realpath, &stat);
 		if (err)
-			return err;
+			goto out_dput;
+		err = -ESTALE;
 		if ((stat.mode ^ inode->i_mode) & S_IFMT)
-			return -ESTALE;
+			goto out_dput;
 		inode->i_mode = stat.mode;
 		inode->i_uid = stat.uid;
 		inode->i_gid = stat.gid;
-		return generic_permission(inode, mask);
+		err = generic_permission(inode, mask);
+		goto out_dput;
 	}
 	/* Careful in RCU walk mode */

fs/overlayfs/super.c+7−5

@@ -1082,11 +1082,13 @@ static int ovl_fill_super(struct super_block sb, void data, int silent) · 1081 unmodified lines
1082	if (err < 0)	1082	if (err < 0)
1083	goto out_put_workdir;	1083	goto out_put_workdir;
1084		1084
1085	if (!err) {	1085	/*
1086	pr_err("overlayfs: upper fs needs to support d_type.\n");	1086	* We allowed this configuration and don't want to
1087	err = -EINVAL;	1087	* break users over kernel upgrade. So warn instead
1088	goto out_put_workdir;	1088	* of erroring out.
1089	}	1089	*/
		1090	if (!err)
		1091	pr_warn("overlayfs: upper fs needs to support d_type.\n");
1090	}	1092	}
1091	}	1093	}
1092		1094

include/drm/i915_pciids.h+4−6

 	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
 	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
 	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
+	INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
 	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
 #define INTEL_KBL_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
 	INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
-	INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
+	INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
-	INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
 #define INTEL_KBL_GT4_IDS(info) \
-	INTEL_VGA_DEVICE(0x5932, info), /* DT  GT4 */ \
+	INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
-	INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \
-	INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \
-	INTEL_VGA_DEVICE(0x593D, info)  /* WKS GT4 */
 #define INTEL_KBL_IDS(info) \
 	INTEL_KBL_GT1_IDS(info), \

include/kvm/arm_pmu.h+2−2

 #ifndef __ASM_ARM_KVM_PMU_H
 #define __ASM_ARM_KVM_PMU_H
-#ifdef CONFIG_KVM_ARM_PMU
 #include <linux/perf_event.h>
 #include <asm/perf_event.h>
 #define ARMV8_PMU_CYCLE_IDX		(ARMV8_PMU_MAX_COUNTERS - 1)
+#ifdef CONFIG_KVM_ARM_PMU
 struct kvm_pmc {
 	u8 idx;	/* index into the pmu->pmc array */
 	struct perf_event *perf_event;

include/linux/mfd/da9052/da9052.h+1−1

@@ -171,7 +171,7 @@ static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg, · 170 unmodified lines
171	static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,	171	static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
172	unsigned reg_cnt, unsigned char *val)	172	unsigned reg_cnt, unsigned char *val)
173	{	173	{
174	int ret;	174	int ret = 0;
175	int i;	175	int i;
176		176
177	for (i = 0; i < reg_cnt; i++) {	177	for (i = 0; i < reg_cnt; i++) {

include/linux/mlx5/driver.h+1−0

@@ -654,6 +654,7 @@ struct mlx5_cmd_work_ent { · 653 unmodified lines
654	void *uout;	654	void *uout;
655	int uout_size;	655	int uout_size;
656	mlx5_cmd_cbk_t callback;	656	mlx5_cmd_cbk_t callback;
		657	struct delayed_work cb_timeout_work;
657	void *context;	658	void *context;
658	int idx;	659	int idx;
659	struct completion done;	660	struct completion done;

include/linux/pwm.h+10−6

@@ -464,6 +464,8 @@ static inline bool pwm_can_sleep(struct pwm_device *pwm) · 463 unmodified lines
464		464
465	static inline void pwm_apply_args(struct pwm_device *pwm)	465	static inline void pwm_apply_args(struct pwm_device *pwm)
466	{	466	{
		467	struct pwm_state state = { };
		468
467	/*	469	/*
468	* PWM users calling pwm_apply_args() expect to have a fresh config	470	* PWM users calling pwm_apply_args() expect to have a fresh config
469	* where the polarity and period are set according to pwm_args info.	471	* where the polarity and period are set according to pwm_args info.
@@ -476,18 +478,20 @@ static inline void pwm_apply_args(struct pwm_device *pwm) · 6 unmodified lines
476	* at startup (even if they are actually enabled), thus authorizing	478	* at startup (even if they are actually enabled), thus authorizing
477	* polarity setting.	479	* polarity setting.
478	*	480	*
479	* Instead of setting ->enabled to false, we call pwm_disable()	481	* To fulfill this requirement, we apply a new state which disables
480	* before pwm_set_polarity() to ensure that everything is configured	482	* the PWM device and set the reference period and polarity config.
481	* as expected, and the PWM is really disabled when the user request
482	* it.
483	*	483	*
484	* Note that PWM users requiring a smooth handover between the	484	* Note that PWM users requiring a smooth handover between the
485	* bootloader and the kernel (like critical regulators controlled by	485	* bootloader and the kernel (like critical regulators controlled by
486	* PWM devices) will have to switch to the atomic API and avoid calling	486	* PWM devices) will have to switch to the atomic API and avoid calling
487	* pwm_apply_args().	487	* pwm_apply_args().
488	*/	488	*/
489	pwm_disable(pwm);	489
490	pwm_set_polarity(pwm, pwm->args.polarity);	490	state.enabled = false;
		491	state.polarity = pwm->args.polarity;
		492	state.period = pwm->args.period;
		493
		494	pwm_apply_state(pwm, &state);
491	}	495	}
492		496
493	struct pwm_lookup {	497	struct pwm_lookup {

include/linux/reset.h+167−44

@@ -84,8 +84,8 @@ static inline struct reset_control *__devm_reset_control_get( · 83 unmodified lines
84	#endif /* CONFIG_RESET_CONTROLLER */	84	#endif /* CONFIG_RESET_CONTROLLER */
85		85
86	/**	86	/**
87	* reset_control_get - Lookup and obtain an exclusive reference to a	87	* reset_control_get_exclusive - Lookup and obtain an exclusive reference
88	* reset controller.	88	* to a reset controller.
89	* @dev: device to be reset by the controller	89	* @dev: device to be reset by the controller
90	* @id: reset line name	90	* @id: reset line name
91	*	91	*
@@ -98,8 +98,8 @@ static inline struct reset_control *__devm_reset_control_get( · 6 unmodified lines
98	*	98	*
99	* Use of id names is optional.	99	* Use of id names is optional.
100	*/	100	*/
101	static inline struct reset_control *__must_check reset_control_get(	101	static inline struct reset_control *
102	struct device dev, const char id)	102	__must_check reset_control_get_exclusive(struct device dev, const char id)
103	{	103	{
104	#ifndef CONFIG_RESET_CONTROLLER	104	#ifndef CONFIG_RESET_CONTROLLER
105	WARN_ON(1);	105	WARN_ON(1);
@@ -107,12 +107,6 @@ static inline struct reset_control *__must_check reset_control_get( · 1 unmodified line
107	return __of_reset_control_get(dev ? dev->of_node : NULL, id, 0, 0);	107	return __of_reset_control_get(dev ? dev->of_node : NULL, id, 0, 0);
108	}	108	}
109		109
110	static inline struct reset_control *reset_control_get_optional(
111	struct device dev, const char id)
112	{
113	return __of_reset_control_get(dev ? dev->of_node : NULL, id, 0, 0);
114	}
115
116	/**	110	/**
117	* reset_control_get_shared - Lookup and obtain a shared reference to a	111	* reset_control_get_shared - Lookup and obtain a shared reference to a
118	* reset controller.	112	* reset controller.
@@ -141,9 +135,21 @@ static inline struct reset_control *reset_control_get_shared( · 22 unmodified lines
141	return __of_reset_control_get(dev ? dev->of_node : NULL, id, 0, 1);	135	return __of_reset_control_get(dev ? dev->of_node : NULL, id, 0, 1);
142	}	136	}
143		137
		138	static inline struct reset_control *reset_control_get_optional_exclusive(
		139	struct device dev, const char id)
		140	{
		141	return __of_reset_control_get(dev ? dev->of_node : NULL, id, 0, 0);
		142	}
		143
		144	static inline struct reset_control *reset_control_get_optional_shared(
		145	struct device dev, const char id)
		146	{
		147	return __of_reset_control_get(dev ? dev->of_node : NULL, id, 0, 1);
		148	}
		149
144	/**	150	/**
145	* of_reset_control_get - Lookup and obtain an exclusive reference to a	151	* of_reset_control_get_exclusive - Lookup and obtain an exclusive reference
146	* reset controller.	152	* to a reset controller.
147	* @node: device to be reset by the controller	153	* @node: device to be reset by the controller
148	* @id: reset line name	154	* @id: reset line name
149	*	155	*
@@ -151,15 +157,41 @@ static inline struct reset_control *reset_control_get_shared( · 1 unmodified line
151	*	157	*
152	* Use of id names is optional.	158	* Use of id names is optional.
153	*/	159	*/
154	static inline struct reset_control *of_reset_control_get(	160	static inline struct reset_control *of_reset_control_get_exclusive(
155	struct device_node node, const char id)	161	struct device_node node, const char id)
156	{	162	{
157	return __of_reset_control_get(node, id, 0, 0);	163	return __of_reset_control_get(node, id, 0, 0);
158	}	164	}
159		165
160	/**	166	/**
161	* of_reset_control_get_by_index - Lookup and obtain an exclusive reference to	167	* of_reset_control_get_shared - Lookup and obtain an shared reference
162	* a reset controller by index.	168	* to a reset controller.
		169	* @node: device to be reset by the controller
		170	* @id: reset line name
		171	*
		172	* When a reset-control is shared, the behavior of reset_control_assert /
		173	* deassert is changed, the reset-core will keep track of a deassert_count
		174	* and only (re-)assert the reset after reset_control_assert has been called
		175	* as many times as reset_control_deassert was called. Also see the remark
		176	* about shared reset-controls in the reset_control_assert docs.
		177	*
		178	* Calling reset_control_assert without first calling reset_control_deassert
		179	* is not allowed on a shared reset control. Calling reset_control_reset is
		180	* also not allowed on a shared reset control.
		181	* Returns a struct reset_control or IS_ERR() condition containing errno.
		182	*
		183	* Use of id names is optional.
		184	*/
		185	static inline struct reset_control *of_reset_control_get_shared(
		186	struct device_node node, const char id)
		187	{
		188	return __of_reset_control_get(node, id, 0, 1);
		189	}
		190
		191	/**
		192	* of_reset_control_get_exclusive_by_index - Lookup and obtain an exclusive
		193	* reference to a reset controller
		194	* by index.
163	* @node: device to be reset by the controller	195	* @node: device to be reset by the controller
164	* @index: index of the reset controller	196	* @index: index of the reset controller
165	*	197	*
@@ -167,49 +199,60 @@ static inline struct reset_control *of_reset_control_get( · 1 unmodified line
167	* in whatever order. Returns a struct reset_control or IS_ERR() condition	199	* in whatever order. Returns a struct reset_control or IS_ERR() condition
168	* containing errno.	200	* containing errno.
169	*/	201	*/
170	static inline struct reset_control *of_reset_control_get_by_index(	202	static inline struct reset_control *of_reset_control_get_exclusive_by_index(
171	struct device_node *node, int index)	203	struct device_node *node, int index)
172	{	204	{
173	return __of_reset_control_get(node, NULL, index, 0);	205	return __of_reset_control_get(node, NULL, index, 0);
174	}	206	}
175		207
176	/**	208	/**
177	* devm_reset_control_get - resource managed reset_control_get()	209	* of_reset_control_get_shared_by_index - Lookup and obtain an shared
178	* @dev: device to be reset by the controller	210	* reference to a reset controller
179	* @id: reset line name	211	* by index.
		212	* @node: device to be reset by the controller
		213	* @index: index of the reset controller
		214	*
		215	* When a reset-control is shared, the behavior of reset_control_assert /
		216	* deassert is changed, the reset-core will keep track of a deassert_count
		217	* and only (re-)assert the reset after reset_control_assert has been called
		218	* as many times as reset_control_deassert was called. Also see the remark
		219	* about shared reset-controls in the reset_control_assert docs.
		220	*
		221	* Calling reset_control_assert without first calling reset_control_deassert
		222	* is not allowed on a shared reset control. Calling reset_control_reset is
		223	* also not allowed on a shared reset control.
		224	* Returns a struct reset_control or IS_ERR() condition containing errno.
180	*	225	*
181	* Managed reset_control_get(). For reset controllers returned from this	226	* This is to be used to perform a list of resets for a device or power domain
182	* function, reset_control_put() is called automatically on driver detach.	227	* in whatever order. Returns a struct reset_control or IS_ERR() condition
183	* See reset_control_get() for more information.	228	* containing errno.
184	*/	229	*/
185	static inline struct reset_control *__must_check devm_reset_control_get(	230	static inline struct reset_control *of_reset_control_get_shared_by_index(
186	struct device dev, const char id)	231	struct device_node *node, int index)
187	{
188	#ifndef CONFIG_RESET_CONTROLLER
189	WARN_ON(1);
190	#endif
191	return __devm_reset_control_get(dev, id, 0, 0);
192	}
193
194	static inline struct reset_control *devm_reset_control_get_optional(
195	struct device dev, const char id)
196	{	232	{
197	return __devm_reset_control_get(dev, id, 0, 0);	233	return __of_reset_control_get(node, NULL, index, 1);
198	}	234	}
199		235
200	/**	236	/**
201	* devm_reset_control_get_by_index - resource managed reset_control_get	237	* devm_reset_control_get_exclusive - resource managed
		238	* reset_control_get_exclusive()
202	* @dev: device to be reset by the controller	239	* @dev: device to be reset by the controller
203	* @index: index of the reset controller	240	* @id: reset line name
204	*	241	*
205	* Managed reset_control_get(). For reset controllers returned from this	242	* Managed reset_control_get_exclusive(). For reset controllers returned
206	* function, reset_control_put() is called automatically on driver detach.	243	* from this function, reset_control_put() is called automatically on driver
207	* See reset_control_get() for more information.	244	* detach.
		245	*
		246	* See reset_control_get_exclusive() for more information.
208	*/	247	*/
209	static inline struct reset_control *devm_reset_control_get_by_index(	248	static inline struct reset_control *
210	struct device *dev, int index)	249	__must_check devm_reset_control_get_exclusive(struct device *dev,
		250	const char *id)
211	{	251	{
212	return __devm_reset_control_get(dev, NULL, index, 0);	252	#ifndef CONFIG_RESET_CONTROLLER
		253	WARN_ON(1);
		254	#endif
		255	return __devm_reset_control_get(dev, id, 0, 0);
213	}	256	}
214		257
215	/**	258	/**
@@ -227,6 +270,36 @@ static inline struct reset_control *devm_reset_control_get_shared( · 11 unmodified lines
227	return __devm_reset_control_get(dev, id, 0, 1);	270	return __devm_reset_control_get(dev, id, 0, 1);
228	}	271	}
229		272
		273	static inline struct reset_control *devm_reset_control_get_optional_exclusive(
		274	struct device dev, const char id)
		275	{
		276	return __devm_reset_control_get(dev, id, 0, 0);
		277	}
		278
		279	static inline struct reset_control *devm_reset_control_get_optional_shared(
		280	struct device dev, const char id)
		281	{
		282	return __devm_reset_control_get(dev, id, 0, 1);
		283	}
		284
		285	/**
		286	* devm_reset_control_get_exclusive_by_index - resource managed
		287	* reset_control_get_exclusive()
		288	* @dev: device to be reset by the controller
		289	* @index: index of the reset controller
		290	*
		291	* Managed reset_control_get_exclusive(). For reset controllers returned from
		292	* this function, reset_control_put() is called automatically on driver
		293	* detach.
		294	*
		295	* See reset_control_get_exclusive() for more information.
		296	*/
		297	static inline struct reset_control *
		298	devm_reset_control_get_exclusive_by_index(struct device *dev, int index)
		299	{
		300	return __devm_reset_control_get(dev, NULL, index, 0);
		301	}
		302
230	/**	303	/**
231	* devm_reset_control_get_shared_by_index - resource managed	304	* devm_reset_control_get_shared_by_index - resource managed
232	* reset_control_get_shared	305	* reset_control_get_shared
@@ -237,10 +310,60 @@ static inline struct reset_control *devm_reset_control_get_shared( · 4 unmodified lines
237	* this function, reset_control_put() is called automatically on driver detach.	310	* this function, reset_control_put() is called automatically on driver detach.
238	* See reset_control_get_shared() for more information.	311	* See reset_control_get_shared() for more information.
239	*/	312	*/
240	static inline struct reset_control *devm_reset_control_get_shared_by_index(	313	static inline struct reset_control *
241	struct device *dev, int index)	314	devm_reset_control_get_shared_by_index(struct device *dev, int index)
242	{	315	{
243	return __devm_reset_control_get(dev, NULL, index, 1);	316	return __devm_reset_control_get(dev, NULL, index, 1);
244	}	317	}
245		318
		319	/*
		320	* TEMPORARY calls to use during transition:
		321	*
		322	* of_reset_control_get() => of_reset_control_get_exclusive()
		323	*
		324	* These inline function calls will be removed once all consumers
		325	* have been moved over to the new explicit API.
		326	*/
		327	static inline struct reset_control *reset_control_get(
		328	struct device dev, const char id)
		329	{
		330	return reset_control_get_exclusive(dev, id);
		331	}
		332
		333	static inline struct reset_control *reset_control_get_optional(
		334	struct device dev, const char id)
		335	{
		336	return reset_control_get_optional_exclusive(dev, id);
		337	}
		338
		339	static inline struct reset_control *of_reset_control_get(
		340	struct device_node node, const char id)
		341	{
		342	return of_reset_control_get_exclusive(node, id);
		343	}
		344
		345	static inline struct reset_control *of_reset_control_get_by_index(
		346	struct device_node *node, int index)
		347	{
		348	return of_reset_control_get_exclusive_by_index(node, index);
		349	}
		350
		351	static inline struct reset_control *devm_reset_control_get(
		352	struct device dev, const char id)
		353	{
		354	return devm_reset_control_get_exclusive(dev, id);
		355	}
		356
		357	static inline struct reset_control *devm_reset_control_get_optional(
		358	struct device dev, const char id)
		359	{
		360	return devm_reset_control_get_optional_exclusive(dev, id);
		361
		362	}
		363
		364	static inline struct reset_control *devm_reset_control_get_by_index(
		365	struct device *dev, int index)
		366	{
		367	return devm_reset_control_get_exclusive_by_index(dev, index);
		368	}
246	#endif	369	#endif

include/linux/skbuff.h+20−0

@@ -1079,6 +1079,7 @@ __skb_set_sw_hash(struct sk_buff *skb, __u32 hash, bool is_l4) · 1078 unmodified lines
1079	}	1079	}
1080		1080
1081	void __skb_get_hash(struct sk_buff *skb);	1081	void __skb_get_hash(struct sk_buff *skb);
		1082	u32 __skb_get_hash_symmetric(struct sk_buff *skb);
1082	u32 skb_get_poff(const struct sk_buff *skb);	1083	u32 skb_get_poff(const struct sk_buff *skb);
1083	u32 __skb_get_poff(const struct sk_buff skb, void data,	1084	u32 __skb_get_poff(const struct sk_buff skb, void data,
1084	const struct flow_keys *keys, int hlen);	1085	const struct flow_keys *keys, int hlen);
@@ -2886,6 +2887,25 @@ static inline void skb_postpush_rcsum(struct sk_buff *skb, · 1801 unmodified lines
2886	skb->csum = csum_partial(start, len, skb->csum);	2887	skb->csum = csum_partial(start, len, skb->csum);
2887	}	2888	}
2888		2889
		2890	/**
		2891	* skb_push_rcsum - push skb and update receive checksum
		2892	* @skb: buffer to update
		2893	* @len: length of data pulled
		2894	*
		2895	* This function performs an skb_push on the packet and updates
		2896	* the CHECKSUM_COMPLETE checksum. It should be used on
		2897	* receive path processing instead of skb_push unless you know
		2898	* that the checksum difference is zero (e.g., a valid IP header)
		2899	* or you are setting ip_summed to CHECKSUM_NONE.
		2900	*/
		2901	static inline unsigned char skb_push_rcsum(struct sk_buff skb,
		2902	unsigned int len)
		2903	{
		2904	skb_push(skb, len);
		2905	skb_postpush_rcsum(skb, skb->data, len);
		2906	return skb->data;
		2907	}
		2908
2889	/**	2909	/**
2890	* pskb_trim_rcsum - trim received skb and update checksum	2910	* pskb_trim_rcsum - trim received skb and update checksum
2891	* @skb: buffer to trim	2911	* @skb: buffer to trim

include/linux/usb/ehci_def.h+2−2

@@ -180,11 +180,11 @@ struct ehci_regs { · 179 unmodified lines
180	* PORTSCx	180	* PORTSCx
181	*/	181	*/
182	/* HOSTPC: offset 0x84 */	182	/* HOSTPC: offset 0x84 */
183	u32 hostpc[1]; /* HOSTPC extension */	183	u32 hostpc[0]; /* HOSTPC extension */
184	#define HOSTPC_PHCD (1<<22) /* Phy clock disable */	184	#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
185	#define HOSTPC_PSPD (3<<25) /* Port speed detection */	185	#define HOSTPC_PSPD (3<<25) /* Port speed detection */
186		186
187	u32 reserved5[16];	187	u32 reserved5[17];
188		188
189	/* USBMODE_EX: offset 0xc8 */	189	/* USBMODE_EX: offset 0xc8 */
190	u32 usbmode_ex; /* USB Device mode extension */	190	u32 usbmode_ex; /* USB Device mode extension */

include/net/bonding.h+6−1

@@ -34,6 +34,9 @@ · 33 unmodified lines
34		34
35	#define BOND_DEFAULT_MIIMON 100	35	#define BOND_DEFAULT_MIIMON 100
36		36
		37	#ifndef __long_aligned
		38	#define __long_aligned __attribute__((aligned((sizeof(long)))))
		39	#endif
37	/*	40	/*
38	* Less bad way to call ioctl from within the kernel; this needs to be	41	* Less bad way to call ioctl from within the kernel; this needs to be
39	* done some other way to get the call out of interrupt context.	42	* done some other way to get the call out of interrupt context.
@@ -138,7 +141,9 @@ struct bond_params { · 98 unmodified lines
138	struct reciprocal_value reciprocal_packets_per_slave;	141	struct reciprocal_value reciprocal_packets_per_slave;
139	u16 ad_actor_sys_prio;	142	u16 ad_actor_sys_prio;
140	u16 ad_user_port_key;	143	u16 ad_user_port_key;
141	u8 ad_actor_system[ETH_ALEN];	144
		145	/* 2 bytes of padding : see ether_addr_equal_64bits() */
		146	u8 ad_actor_system[ETH_ALEN + 2];
142	};	147	};
143		148
144	struct bond_parm_tbl {	149	struct bond_parm_tbl {

include/net/ip.h+2−3

 	return min(dst->dev->mtu, IP_MAX_MTU);
 }
-static inline unsigned int ip_skb_dst_mtu(const struct sk_buff *skb)
+static inline unsigned int ip_skb_dst_mtu(struct sock *sk,
+					  const struct sk_buff *skb)
 {
-	struct sock *sk = skb->sk;
 	if (!sk || !sk_fullsock(sk) || ip_sk_use_pmtu(sk)) {
 		bool forwarding = IPCB(skb)->flags & IPSKB_FORWARDED;

include/uapi/linux/fuse.h+6−1

  *
  *  7.24
  *  - add FUSE_LSEEK for SEEK_HOLE and SEEK_DATA support
+ *
+ *  7.25
+ *  - add FUSE_PARALLEL_DIROPS
  */
 #ifndef _LINUX_FUSE_H
 #define FUSE_KERNEL_VERSION 7
 /** Minor version number of this interface */
-#define FUSE_KERNEL_MINOR_VERSION 24
+#define FUSE_KERNEL_MINOR_VERSION 25
 /** The node ID of the root inode */
 #define FUSE_ROOT_ID 1
  * FUSE_ASYNC_DIO: asynchronous direct I/O submission
  * FUSE_WRITEBACK_CACHE: use writeback cache for buffered writes
  * FUSE_NO_OPEN_SUPPORT: kernel supports zero-message opens
+ * FUSE_PARALLEL_DIROPS: allow parallel lookups and readdir
  */
 #define FUSE_ASYNC_READ		(1 << 0)
 #define FUSE_POSIX_LOCKS	(1 << 1)
 #define FUSE_ASYNC_DIO		(1 << 15)
 #define FUSE_WRITEBACK_CACHE	(1 << 16)
 #define FUSE_NO_OPEN_SUPPORT	(1 << 17)
+#define FUSE_PARALLEL_DIROPS    (1 << 18)
 /**
  * CUSE INIT request/reply flags

net/bridge/br_netfilter_hooks.c+1−1

@@ -700,7 +700,7 @@ static int · 699 unmodified lines
700	br_nf_ip_fragment(struct net net, struct sock sk, struct sk_buff *skb,	700	br_nf_ip_fragment(struct net net, struct sock sk, struct sk_buff *skb,
701	int (output)(struct net , struct sock , struct sk_buff ))	701	int (output)(struct net , struct sock , struct sk_buff ))
702	{	702	{
703	unsigned int mtu = ip_skb_dst_mtu(skb);	703	unsigned int mtu = ip_skb_dst_mtu(sk, skb);
704	struct iphdr *iph = ip_hdr(skb);	704	struct iphdr *iph = ip_hdr(skb);
705		705
706	if (unlikely(((iph->frag_off & htons(IP_DF)) && !skb->ignore_df) \|\|	706	if (unlikely(((iph->frag_off & htons(IP_DF)) && !skb->ignore_df) \|\|

net/core/flow_dissector.c+43−0

@@ -651,6 +651,23 @@ void make_flow_keys_digest(struct flow_keys_digest *digest, · 650 unmodified lines
651	}	651	}
652	EXPORT_SYMBOL(make_flow_keys_digest);	652	EXPORT_SYMBOL(make_flow_keys_digest);
653		653
		654	static struct flow_dissector flow_keys_dissector_symmetric __read_mostly;
		655
		656	u32 __skb_get_hash_symmetric(struct sk_buff *skb)
		657	{
		658	struct flow_keys keys;
		659
		660	__flow_hash_secret_init();
		661
		662	memset(&keys, 0, sizeof(keys));
		663	__skb_flow_dissect(skb, &flow_keys_dissector_symmetric, &keys,
		664	NULL, 0, 0, 0,
		665	FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL);
		666
		667	return __flow_hash_from_keys(&keys, hashrnd);
		668	}
		669	EXPORT_SYMBOL_GPL(__skb_get_hash_symmetric);
		670
654	/**	671	/**
655	* __skb_get_hash: calculate a flow hash	672	* __skb_get_hash: calculate a flow hash
656	* @skb: sk_buff to calculate flow hash from	673	* @skb: sk_buff to calculate flow hash from
@@ -868,6 +885,29 @@ static const struct flow_dissector_key flow_keys_dissector_keys[] = { · 211 unmodified lines
868	},	885	},
869	};	886	};
870		887
		888	static const struct flow_dissector_key flow_keys_dissector_symmetric_keys[] = {
		889	{
		890	.key_id = FLOW_DISSECTOR_KEY_CONTROL,
		891	.offset = offsetof(struct flow_keys, control),
		892	},
		893	{
		894	.key_id = FLOW_DISSECTOR_KEY_BASIC,
		895	.offset = offsetof(struct flow_keys, basic),
		896	},
		897	{
		898	.key_id = FLOW_DISSECTOR_KEY_IPV4_ADDRS,
		899	.offset = offsetof(struct flow_keys, addrs.v4addrs),
		900	},
		901	{
		902	.key_id = FLOW_DISSECTOR_KEY_IPV6_ADDRS,
		903	.offset = offsetof(struct flow_keys, addrs.v6addrs),
		904	},
		905	{
		906	.key_id = FLOW_DISSECTOR_KEY_PORTS,
		907	.offset = offsetof(struct flow_keys, ports),
		908	},
		909	};
		910
871	static const struct flow_dissector_key flow_keys_buf_dissector_keys[] = {	911	static const struct flow_dissector_key flow_keys_buf_dissector_keys[] = {
872	{	912	{
873	.key_id = FLOW_DISSECTOR_KEY_CONTROL,	913	.key_id = FLOW_DISSECTOR_KEY_CONTROL,
@@ -889,6 +929,9 @@ static int __init init_default_flow_dissectors(void) · 15 unmodified lines
889	skb_flow_dissector_init(&flow_keys_dissector,	929	skb_flow_dissector_init(&flow_keys_dissector,
890	flow_keys_dissector_keys,	930	flow_keys_dissector_keys,
891	ARRAY_SIZE(flow_keys_dissector_keys));	931	ARRAY_SIZE(flow_keys_dissector_keys));
		932	skb_flow_dissector_init(&flow_keys_dissector_symmetric,
		933	flow_keys_dissector_symmetric_keys,
		934	ARRAY_SIZE(flow_keys_dissector_symmetric_keys));
892	skb_flow_dissector_init(&flow_keys_buf_dissector,	935	skb_flow_dissector_init(&flow_keys_buf_dissector,
893	flow_keys_buf_dissector_keys,	936	flow_keys_buf_dissector_keys,
894	ARRAY_SIZE(flow_keys_buf_dissector_keys));	937	ARRAY_SIZE(flow_keys_buf_dissector_keys));

net/core/skbuff.c+0−18

@@ -3016,24 +3016,6 @@ int skb_append_pagefrags(struct sk_buff skb, struct page page, · 3015 unmodified lines
3016	}	3016	}
3017	EXPORT_SYMBOL_GPL(skb_append_pagefrags);	3017	EXPORT_SYMBOL_GPL(skb_append_pagefrags);
3018		3018
3019	/**
3020	* skb_push_rcsum - push skb and update receive checksum
3021	* @skb: buffer to update
3022	* @len: length of data pulled
3023	*
3024	* This function performs an skb_push on the packet and updates
3025	* the CHECKSUM_COMPLETE checksum. It should be used on
3026	* receive path processing instead of skb_push unless you know
3027	* that the checksum difference is zero (e.g., a valid IP header)
3028	* or you are setting ip_summed to CHECKSUM_NONE.
3029	*/
3030	static unsigned char skb_push_rcsum(struct sk_buff skb, unsigned len)
3031	{
3032	skb_push(skb, len);
3033	skb_postpush_rcsum(skb, skb->data, len);
3034	return skb->data;
3035	}
3036
3037	/**	3019	/**
3038	* skb_pull_rcsum - pull skb and update receive checksum	3020	* skb_pull_rcsum - pull skb and update receive checksum
3039	* @skb: buffer to update	3021	* @skb: buffer to update

net/decnet/dn_fib.c+12−9

@@ -41,6 +41,7 @@ · 40 unmodified lines
41	#include <net/dn_fib.h>	41	#include <net/dn_fib.h>
42	#include <net/dn_neigh.h>	42	#include <net/dn_neigh.h>
43	#include <net/dn_dev.h>	43	#include <net/dn_dev.h>
		44	#include <net/nexthop.h>
44		45
45	#define RT_MIN_TABLE 1	46	#define RT_MIN_TABLE 1
46		47
@@ -150,14 +151,13 @@ static int dn_fib_count_nhs(const struct nlattr *attr) · 103 unmodified lines
150	struct rtnexthop *nhp = nla_data(attr);	151	struct rtnexthop *nhp = nla_data(attr);
151	int nhs = 0, nhlen = nla_len(attr);	152	int nhs = 0, nhlen = nla_len(attr);
152		153
153	while(nhlen >= (int)sizeof(struct rtnexthop)) {	154	while (rtnh_ok(nhp, nhlen)) {
154	if ((nhlen -= nhp->rtnh_len) < 0)
155	return 0;
156	nhs++;	155	nhs++;
157	nhp = RTNH_NEXT(nhp);	156	nhp = rtnh_next(nhp, &nhlen);
158	}	157	}
159		158
160	return nhs;	159	/* leftover implies invalid nexthop configuration, discard it */
		160	return nhlen > 0 ? 0 : nhs;
161	}	161	}
162		162
163	static int dn_fib_get_nhs(struct dn_fib_info fi, const struct nlattr attr,	163	static int dn_fib_get_nhs(struct dn_fib_info fi, const struct nlattr attr,
@@ -167,21 +167,24 @@ static int dn_fib_get_nhs(struct dn_fib_info fi, const struct nlattr attr, · 3 unmodified lines
167	int nhlen = nla_len(attr);	167	int nhlen = nla_len(attr);
168		168
169	change_nexthops(fi) {	169	change_nexthops(fi) {
170	int attrlen = nhlen - sizeof(struct rtnexthop);	170	int attrlen;
171	if (attrlen < 0 \|\| (nhlen -= nhp->rtnh_len) < 0)	171
		172	if (!rtnh_ok(nhp, nhlen))
172	return -EINVAL;	173	return -EINVAL;
173		174
174	nh->nh_flags = (r->rtm_flags&~0xFF) \| nhp->rtnh_flags;	175	nh->nh_flags = (r->rtm_flags&~0xFF) \| nhp->rtnh_flags;
175	nh->nh_oif = nhp->rtnh_ifindex;	176	nh->nh_oif = nhp->rtnh_ifindex;
176	nh->nh_weight = nhp->rtnh_hops + 1;	177	nh->nh_weight = nhp->rtnh_hops + 1;
177		178
178	if (attrlen) {	179	attrlen = rtnh_attrlen(nhp);
		180	if (attrlen > 0) {
179	struct nlattr *gw_attr;	181	struct nlattr *gw_attr;
180		182
181	gw_attr = nla_find((struct nlattr *) (nhp + 1), attrlen, RTA_GATEWAY);	183	gw_attr = nla_find((struct nlattr *) (nhp + 1), attrlen, RTA_GATEWAY);
182	nh->nh_gw = gw_attr ? nla_get_le16(gw_attr) : 0;	184	nh->nh_gw = gw_attr ? nla_get_le16(gw_attr) : 0;
183	}	185	}
184	nhp = RTNH_NEXT(nhp);	186
		187	nhp = rtnh_next(nhp, &nhlen);
185	} endfor_nexthops(fi);	188	} endfor_nexthops(fi);
186		189
187	return 0;	190	return 0;

net/ipv4/ip_output.c+2−2

@@ -271,7 +271,7 @@ static int ip_finish_output(struct net net, struct sock sk, struct sk_buff *sk · 270 unmodified lines
271	return dst_output(net, sk, skb);	271	return dst_output(net, sk, skb);
272	}	272	}
273	#endif	273	#endif
274	mtu = ip_skb_dst_mtu(skb);	274	mtu = ip_skb_dst_mtu(sk, skb);
275	if (skb_is_gso(skb))	275	if (skb_is_gso(skb))
276	return ip_finish_output_gso(net, sk, skb, mtu);	276	return ip_finish_output_gso(net, sk, skb, mtu);
277		277
@@ -541,7 +541,7 @@ int ip_do_fragment(struct net net, struct sock sk, struct sk_buff *skb, · 263 unmodified lines
541		541
542	iph = ip_hdr(skb);	542	iph = ip_hdr(skb);
543		543
544	mtu = ip_skb_dst_mtu(skb);	544	mtu = ip_skb_dst_mtu(sk, skb);
545	if (IPCB(skb)->frag_max_size && IPCB(skb)->frag_max_size < mtu)	545	if (IPCB(skb)->frag_max_size && IPCB(skb)->frag_max_size < mtu)
546	mtu = IPCB(skb)->frag_max_size;	546	mtu = IPCB(skb)->frag_max_size;
547		547

net/ipv6/ip6_fib.c+1−0

@@ -177,6 +177,7 @@ static void rt6_free_pcpu(struct rt6_info *non_pcpu_rt) · 176 unmodified lines
177	}	177	}
178	}	178	}
179		179
		180	free_percpu(non_pcpu_rt->rt6i_pcpu);
180	non_pcpu_rt->rt6i_pcpu = NULL;	181	non_pcpu_rt->rt6i_pcpu = NULL;
181	}	182	}
182		183

net/packet/af_packet.c+1−1

@@ -1341,7 +1341,7 @@ static unsigned int fanout_demux_hash(struct packet_fanout *f, · 1340 unmodified lines
1341	struct sk_buff *skb,	1341	struct sk_buff *skb,
1342	unsigned int num)	1342	unsigned int num)
1343	{	1343	{
1344	return reciprocal_scale(skb_get_hash(skb), num);	1344	return reciprocal_scale(__skb_get_hash_symmetric(skb), num);
1345	}	1345	}
1346		1346
1347	static unsigned int fanout_demux_lb(struct packet_fanout *f,	1347	static unsigned int fanout_demux_lb(struct packet_fanout *f,

net/rds/tcp.c+3−2

 	ret = rds_tcp_recv_init();
 	if (ret)
-		goto out_slab;
+		goto out_pernet;
 	ret = rds_trans_register(&rds_tcp_transport);
 	if (ret)
 out_recv:
 	rds_tcp_recv_exit();
-out_slab:
+out_pernet:
 	unregister_pernet_subsys(&rds_tcp_net_ops);
+out_slab:
 	kmem_cache_destroy(rds_tcp_conn_slab);
 out:
 	return ret;

net/sched/act_mirred.c+1−1

@@ -181,7 +181,7 @@ static int tcf_mirred(struct sk_buff skb, const struct tc_action a, · 180 unmodified lines
181		181
182	if (!(at & AT_EGRESS)) {	182	if (!(at & AT_EGRESS)) {
183	if (m->tcfm_ok_push)	183	if (m->tcfm_ok_push)
184	skb_push(skb2, skb->mac_len);	184	skb_push_rcsum(skb2, skb->mac_len);
185	}	185	}
186		186
187	/* mirror is always swallowed */	187	/* mirror is always swallowed */

net/tipc/netlink_compat.c+1−1

@@ -604,7 +604,7 @@ static int tipc_nl_compat_link_dump(struct tipc_nl_compat_msg *msg, · 603 unmodified lines
604		604
605	link_info.dest = nla_get_flag(link[TIPC_NLA_LINK_DEST]);	605	link_info.dest = nla_get_flag(link[TIPC_NLA_LINK_DEST]);
606	link_info.up = htonl(nla_get_flag(link[TIPC_NLA_LINK_UP]));	606	link_info.up = htonl(nla_get_flag(link[TIPC_NLA_LINK_UP]));
607	nla_strlcpy(link_info.str, nla_data(link[TIPC_NLA_LINK_NAME]),	607	nla_strlcpy(link_info.str, link[TIPC_NLA_LINK_NAME],
608	TIPC_MAX_LINK_NAME);	608	TIPC_MAX_LINK_NAME);
609		609
610	return tipc_add_tlv(msg->rep, TIPC_TLV_LINK_INFO,	610	return tipc_add_tlv(msg->rep, TIPC_TLV_LINK_INFO,

sound/core/timer.c+1−1

 		qhead = tu->qhead++;
 		tu->qhead %= tu->queue_size;
+		tu->qused--;
 		spin_unlock_irq(&tu->qlock);
 		if (tu->tread) {
 		}
 		spin_lock_irq(&tu->qlock);
-		tu->qused--;
 		if (err < 0)
 			goto _error;
 		result += unit;

sound/pci/au88x0/au88x0_core.c+2−3

 	int page, p, pp, delta, i;
 	page =
-	    (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) &
+	    (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2))
-	     WT_SUBBUF_MASK)
+	     >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
-	    >> WT_SUBBUF_SHIFT;
 	if (dma->nr_periods >= 4)
 		delta = (page - dma->period_real) & 3;
 	else {

sound/pci/echoaudio/echoaudio.c+2−2

@@ -2200,11 +2200,11 @@ static int snd_echo_resume(struct device *dev) · 2199 unmodified lines
2200	u32 pipe_alloc_mask;	2200	u32 pipe_alloc_mask;
2201	int err;	2201	int err;
2202		2202
2203	commpage_bak = kmalloc(sizeof(struct echoaudio), GFP_KERNEL);	2203	commpage_bak = kmalloc(sizeof(*commpage), GFP_KERNEL);
2204	if (commpage_bak == NULL)	2204	if (commpage_bak == NULL)
2205	return -ENOMEM;	2205	return -ENOMEM;
2206	commpage = chip->comm_page;	2206	commpage = chip->comm_page;
2207	memcpy(commpage_bak, commpage, sizeof(struct comm_page));	2207	memcpy(commpage_bak, commpage, sizeof(*commpage));
2208		2208
2209	err = init_hw(chip, chip->pci->device, chip->pci->subsystem_device);	2209	err = init_hw(chip, chip->pci->device, chip->pci->subsystem_device);
2210	if (err < 0) {	2210	if (err < 0) {

sound/pci/hda/hda_generic.c+2−0

@@ -3977,6 +3977,8 @@ static hda_nid_t set_path_power(struct hda_codec *codec, hda_nid_t nid, · 3976 unmodified lines
3977		3977
3978	for (n = 0; n < spec->paths.used; n++) {	3978	for (n = 0; n < spec->paths.used; n++) {
3979	path = snd_array_elem(&spec->paths, n);	3979	path = snd_array_elem(&spec->paths, n);
		3980	if (!path->depth)
		3981	continue;
3980	if (path->path[0] == nid \|\|	3982	if (path->path[0] == nid \|\|
3981	path->path[path->depth - 1] == nid) {	3983	path->path[path->depth - 1] == nid) {
3982	bool pin_old = path->pin_enabled;	3984	bool pin_old = path->pin_enabled;

sound/pci/hda/hda_intel.c+5−1

 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
+#define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
-			IS_KBL(pci) || IS_KBL_LP(pci)
+			IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)
 static char *driver_short_names[] = {
 	[AZX_DRIVER_ICH] = "HDA Intel",
 	/* Kabylake-LP */
 	{ PCI_DEVICE(0x8086, 0x9d71),
 	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
+	/* Kabylake-H */
+	{ PCI_DEVICE(0x8086, 0xa2f0),
+	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
 	/* Broxton-P(Apollolake) */
 	{ PCI_DEVICE(0x8086, 0x5a98),
 	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },

sound/pci/hda/patch_realtek.c+1−0

@@ -5651,6 +5651,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { · 5650 unmodified lines
5651	SND_PCI_QUIRK(0x17aa, 0x504a, "ThinkPad X260", ALC292_FIXUP_TPT440_DOCK),	5651	SND_PCI_QUIRK(0x17aa, 0x504a, "ThinkPad X260", ALC292_FIXUP_TPT440_DOCK),
5652	SND_PCI_QUIRK(0x17aa, 0x504b, "Thinkpad", ALC293_FIXUP_LENOVO_SPK_NOISE),	5652	SND_PCI_QUIRK(0x17aa, 0x504b, "Thinkpad", ALC293_FIXUP_LENOVO_SPK_NOISE),
5653	SND_PCI_QUIRK(0x17aa, 0x5050, "Thinkpad T560p", ALC292_FIXUP_TPT460),	5653	SND_PCI_QUIRK(0x17aa, 0x5050, "Thinkpad T560p", ALC292_FIXUP_TPT460),
		5654	SND_PCI_QUIRK(0x17aa, 0x5051, "Thinkpad L460", ALC292_FIXUP_TPT460),
5654	SND_PCI_QUIRK(0x17aa, 0x5053, "Thinkpad T460", ALC292_FIXUP_TPT460),	5655	SND_PCI_QUIRK(0x17aa, 0x5053, "Thinkpad T460", ALC292_FIXUP_TPT460),
5655	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),	5656	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
5656	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),	5657	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),

sound/soc/codecs/Kconfig+4−3

 	tristate
 config SND_SOC_HDMI_CODEC
-       tristate
+	tristate
-       select SND_PCM_ELD
+	select SND_PCM_ELD
-       select SND_PCM_IEC958
+	select SND_PCM_IEC958
+	select HDMI
 config SND_SOC_ES8328
 	tristate "Everest Semi ES8328 CODEC"

sound/soc/codecs/ak4613.c+1−1

 	.max_register		= 0x16,
 	.reg_defaults		= ak4613_reg,
 	.num_reg_defaults	= ARRAY_SIZE(ak4613_reg),
+	.cache_type		= REGCACHE_RBTREE,
 };
 static const struct of_device_id ak4613_of_match[] = {
 static struct i2c_driver ak4613_i2c_driver = {
 	.driver = {
 		.name = "ak4613-codec",
-		.owner = THIS_MODULE,
 		.of_match_table = ak4613_of_match,
 	},
 	.probe		= ak4613_i2c_probe,

sound/soc/codecs/cx20442.c+1−0

@@ -226,6 +226,7 @@ static int v253_open(struct tty_struct *tty) · 225 unmodified lines
226	if (!tty->disc_data)	226	if (!tty->disc_data)
227	return -ENODEV;	227	return -ENODEV;
228		228
		229	tty->receive_room = 16;
229	if (tty->ops->write(tty, v253_init, len) != len) {	230	if (tty->ops->write(tty, v253_init, len) != len) {
230	ret = -EIO;	231	ret = -EIO;
231	goto err;	232	goto err;

sound/soc/codecs/hdac_hdmi.c+20−0

 	 * exit, we call pm_runtime_suspend() so that will do for us
 	 */
 	hlink = snd_hdac_ext_bus_get_link(edev->ebus, dev_name(&edev->hdac.dev));
+	if (!hlink) {
+		dev_err(&edev->hdac.dev, "hdac link not found\n");
+		return -EIO;
+	}
 	snd_hdac_ext_bus_link_get(edev->ebus, hlink);
 	ret = create_fill_widget_route_map(dapm);
 	/* hold the ref while we probe */
 	hlink = snd_hdac_ext_bus_get_link(edev->ebus, dev_name(&edev->hdac.dev));
+	if (!hlink) {
+		dev_err(&edev->hdac.dev, "hdac link not found\n");
+		return -EIO;
+	}
 	snd_hdac_ext_bus_link_get(edev->ebus, hlink);
 	hdmi_priv = devm_kzalloc(&codec->dev, sizeof(*hdmi_priv), GFP_KERNEL);
 	}
 	hlink = snd_hdac_ext_bus_get_link(ebus, dev_name(dev));
+	if (!hlink) {
+		dev_err(dev, "hdac link not found\n");
+		return -EIO;
+	}
 	snd_hdac_ext_bus_link_put(ebus, hlink);
 	return 0;
 		return 0;
 	hlink = snd_hdac_ext_bus_get_link(ebus, dev_name(dev));
+	if (!hlink) {
+		dev_err(dev, "hdac link not found\n");
+		return -EIO;
+	}
 	snd_hdac_ext_bus_link_get(ebus, hlink);
 	err = snd_hdac_display_power(bus, true);

sound/soc/codecs/rt5645.c+1−1

@@ -253,7 +253,7 @@ static const struct reg_default rt5650_reg[] = { · 252 unmodified lines
253	{ 0x2b, 0x5454 },	253	{ 0x2b, 0x5454 },
254	{ 0x2c, 0xaaa0 },	254	{ 0x2c, 0xaaa0 },
255	{ 0x2d, 0x0000 },	255	{ 0x2d, 0x0000 },
256	{ 0x2f, 0x1002 },	256	{ 0x2f, 0x5002 },
257	{ 0x31, 0x5000 },	257	{ 0x31, 0x5000 },
258	{ 0x32, 0x0000 },	258	{ 0x32, 0x0000 },
259	{ 0x33, 0x0000 },	259	{ 0x33, 0x0000 },

sound/soc/codecs/rt5670.c+1−1

@@ -619,7 +619,7 @@ static const struct snd_kcontrol_new rt5670_snd_controls[] = { · 618 unmodified lines
619	RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),	619	RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
620	SOC_DOUBLE_TLV("HP Playback Volume", RT5670_HP_VOL,	620	SOC_DOUBLE_TLV("HP Playback Volume", RT5670_HP_VOL,
621	RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,	621	RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
622	39, 0, out_vol_tlv),	622	39, 1, out_vol_tlv),
623	/* OUTPUT Control */	623	/* OUTPUT Control */
624	SOC_DOUBLE("OUT Channel Switch", RT5670_LOUT1,	624	SOC_DOUBLE("OUT Channel Switch", RT5670_LOUT1,
625	RT5670_VOL_L_SFT, RT5670_VOL_R_SFT, 1, 1),	625	RT5670_VOL_L_SFT, RT5670_VOL_R_SFT, 1, 1),

sound/soc/codecs/wm5102.c+1−1

@@ -1872,7 +1872,7 @@ static struct snd_soc_dai_driver wm5102_dai[] = { · 1871 unmodified lines
1872	.capture = {	1872	.capture = {
1873	.stream_name = "Audio Trace CPU",	1873	.stream_name = "Audio Trace CPU",
1874	.channels_min = 1,	1874	.channels_min = 1,
1875	.channels_max = 6,	1875	.channels_max = 4,
1876	.rates = WM5102_RATES,	1876	.rates = WM5102_RATES,
1877	.formats = WM5102_FORMATS,	1877	.formats = WM5102_FORMATS,
1878	},	1878	},

sound/soc/codecs/wm5110.c+1−0

@@ -1723,6 +1723,7 @@ static const struct snd_soc_dapm_route wm5110_dapm_routes[] = { · 1722 unmodified lines
1723	{ "OUT2L", NULL, "SYSCLK" },	1723	{ "OUT2L", NULL, "SYSCLK" },
1724	{ "OUT2R", NULL, "SYSCLK" },	1724	{ "OUT2R", NULL, "SYSCLK" },
1725	{ "OUT3L", NULL, "SYSCLK" },	1725	{ "OUT3L", NULL, "SYSCLK" },
		1726	{ "OUT3R", NULL, "SYSCLK" },
1726	{ "OUT4L", NULL, "SYSCLK" },	1727	{ "OUT4L", NULL, "SYSCLK" },
1727	{ "OUT4R", NULL, "SYSCLK" },	1728	{ "OUT4R", NULL, "SYSCLK" },
1728	{ "OUT5L", NULL, "SYSCLK" },	1729	{ "OUT5L", NULL, "SYSCLK" },

sound/soc/codecs/wm8940.c+1−0

@@ -743,6 +743,7 @@ static const struct regmap_config wm8940_regmap = { · 742 unmodified lines
743	.max_register = WM8940_MONOMIX,	743	.max_register = WM8940_MONOMIX,
744	.reg_defaults = wm8940_reg_defaults,	744	.reg_defaults = wm8940_reg_defaults,
745	.num_reg_defaults = ARRAY_SIZE(wm8940_reg_defaults),	745	.num_reg_defaults = ARRAY_SIZE(wm8940_reg_defaults),
		746	.cache_type = REGCACHE_RBTREE,
746		747
747	.readable_reg = wm8940_readable_register,	748	.readable_reg = wm8940_readable_register,
748	.volatile_reg = wm8940_volatile_register,	749	.volatile_reg = wm8940_volatile_register,

sound/soc/davinci/davinci-mcasp.c+52−4

@@ -1513,8 +1513,9 @@ static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { · 1512 unmodified lines
1513	};	1513	};
1514		1514
1515	static struct davinci_mcasp_pdata dra7_mcasp_pdata = {	1515	static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1516	.tx_dma_offset = 0x200,	1516	/* The CFG port offset will be calculated if it is needed */
1517	.rx_dma_offset = 0x284,	1517	.tx_dma_offset = 0,
		1518	.rx_dma_offset = 0,
1518	.version = MCASP_VERSION_4,	1519	.version = MCASP_VERSION_4,
1519	};	1520	};
1520		1521
@@ -1734,6 +1735,52 @@ static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) · 213 unmodified lines
1734	return PCM_EDMA;	1735	return PCM_EDMA;
1735	}	1736	}
1736		1737
		1738	static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
		1739	{
		1740	int i;
		1741	u32 offset = 0;
		1742
		1743	if (pdata->version != MCASP_VERSION_4)
		1744	return pdata->tx_dma_offset;
		1745
		1746	for (i = 0; i < pdata->num_serializer; i++) {
		1747	if (pdata->serial_dir[i] == TX_MODE) {
		1748	if (!offset) {
		1749	offset = DAVINCI_MCASP_TXBUF_REG(i);
		1750	} else {
		1751	pr_err("%s: Only one serializer allowed!\n",
		1752	__func__);
		1753	break;
		1754	}
		1755	}
		1756	}
		1757
		1758	return offset;
		1759	}
		1760
		1761	static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
		1762	{
		1763	int i;
		1764	u32 offset = 0;
		1765
		1766	if (pdata->version != MCASP_VERSION_4)
		1767	return pdata->rx_dma_offset;
		1768
		1769	for (i = 0; i < pdata->num_serializer; i++) {
		1770	if (pdata->serial_dir[i] == RX_MODE) {
		1771	if (!offset) {
		1772	offset = DAVINCI_MCASP_RXBUF_REG(i);
		1773	} else {
		1774	pr_err("%s: Only one serializer allowed!\n",
		1775	__func__);
		1776	break;
		1777	}
		1778	}
		1779	}
		1780
		1781	return offset;
		1782	}
		1783
1737	static int davinci_mcasp_probe(struct platform_device *pdev)	1784	static int davinci_mcasp_probe(struct platform_device *pdev)
1738	{	1785	{
1739	struct snd_dmaengine_dai_dma_data *dma_data;	1786	struct snd_dmaengine_dai_dma_data *dma_data;
@@ -1862,7 +1909,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev) · 122 unmodified lines
1862	if (dat)	1909	if (dat)
1863	dma_data->addr = dat->start;	1910	dma_data->addr = dat->start;
1864	else	1911	else
1865	dma_data->addr = mem->start + pdata->tx_dma_offset;	1912	dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1866		1913
1867	dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];	1914	dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1868	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);	1915	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
@@ -1883,7 +1930,8 @@ static int davinci_mcasp_probe(struct platform_device *pdev) · 14 unmodified lines
1883	if (dat)	1930	if (dat)
1884	dma_data->addr = dat->start;	1931	dma_data->addr = dat->start;
1885	else	1932	else
1886	dma_data->addr = mem->start + pdata->rx_dma_offset;	1933	dma_data->addr =
		1934	mem->start + davinci_mcasp_rxdma_offset(pdata);
1887		1935
1888	dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];	1936	dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1889	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);	1937	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);

sound/soc/davinci/davinci-mcasp.h+2−2

@@ -85,9 +85,9 @@ · 84 unmodified lines
85	(n << 2))	85	(n << 2))
86		86
87	/* Transmit Buffer for Serializer n */	87	/* Transmit Buffer for Serializer n */
88	#define DAVINCI_MCASP_TXBUF_REG 0x200	88	#define DAVINCI_MCASP_TXBUF_REG(n) (0x200 + (n << 2))
89	/* Receive Buffer for Serializer n */	89	/* Receive Buffer for Serializer n */
90	#define DAVINCI_MCASP_RXBUF_REG 0x280	90	#define DAVINCI_MCASP_RXBUF_REG(n) (0x280 + (n << 2))
91		91
92	/* McASP FIFO Registers */	92	/* McASP FIFO Registers */
93	#define DAVINCI_MCASP_V2_AFIFO_BASE (0x1010)	93	#define DAVINCI_MCASP_V2_AFIFO_BASE (0x1010)

sound/soc/fsl/fsl_ssi.c+6−6

 	ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 	case SND_SOC_DAIFMT_I2S:
+		regmap_update_bits(regs, CCSR_SSI_STCCR,
+				   CCSR_SSI_SxCCR_DC_MASK,
+				   CCSR_SSI_SxCCR_DC(2));
+		regmap_update_bits(regs, CCSR_SSI_SRCCR,
+				   CCSR_SSI_SxCCR_DC_MASK,
+				   CCSR_SSI_SxCCR_DC(2));
 		switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 		case SND_SOC_DAIFMT_CBM_CFS:
 		case SND_SOC_DAIFMT_CBS_CFS:
 			ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
-			regmap_update_bits(regs, CCSR_SSI_STCCR,
-					CCSR_SSI_SxCCR_DC_MASK,
-					CCSR_SSI_SxCCR_DC(2));
-			regmap_update_bits(regs, CCSR_SSI_SRCCR,
-					CCSR_SSI_SxCCR_DC_MASK,
-					CCSR_SSI_SxCCR_DC(2));
 			break;
 		case SND_SOC_DAIFMT_CBM_CFM:
 			ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;

sound/soc/intel/atom/sst-mfld-platform-compress.c+7−2

 	case SNDRV_PCM_TRIGGER_START:
 		if (stream->compr_ops->stream_start)
 			return stream->compr_ops->stream_start(sst->dev, stream->id);
+		break;
 	case SNDRV_PCM_TRIGGER_STOP:
 		if (stream->compr_ops->stream_drop)
 			return stream->compr_ops->stream_drop(sst->dev, stream->id);
+		break;
 	case SND_COMPR_TRIGGER_DRAIN:
 		if (stream->compr_ops->stream_drain)
 			return stream->compr_ops->stream_drain(sst->dev, stream->id);
+		break;
 	case SND_COMPR_TRIGGER_PARTIAL_DRAIN:
 		if (stream->compr_ops->stream_partial_drain)
 			return stream->compr_ops->stream_partial_drain(sst->dev, stream->id);
+		break;
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		if (stream->compr_ops->stream_pause)
 			return stream->compr_ops->stream_pause(sst->dev, stream->id);
+		break;
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		if (stream->compr_ops->stream_pause_release)
 			return stream->compr_ops->stream_pause_release(sst->dev, stream->id);
-	default:
+		break;
-		return -EINVAL;
 	}
+	return -EINVAL;
 }
 static int sst_platform_compr_pointer(struct snd_compr_stream *cstream,

sound/soc/intel/skylake/bxt-sst.c+1−0

@@ -291,6 +291,7 @@ int bxt_sst_dsp_init(struct device dev, void __iomem mmio_base, int irq, · 290 unmodified lines
291	sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),	291	sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
292	SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);	292	SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
293		293
		294	INIT_LIST_HEAD(&sst->module_list);
294	ret = skl_ipc_init(dev, skl);	295	ret = skl_ipc_init(dev, skl);
295	if (ret)	296	if (ret)
296	return ret;	297	return ret;

sound/soc/sh/rcar/adg.c+1−1

@@ -518,7 +518,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, · 517 unmodified lines
518	}	518	}
519	}	519	}
520		520
521	rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr);	521	rsnd_mod_bset(adg_mod, SSICKR, 0x80FF0000, ckr);
522	rsnd_mod_write(adg_mod, BRRA, rbga);	522	rsnd_mod_write(adg_mod, BRRA, rbga);
523	rsnd_mod_write(adg_mod, BRRB, rbgb);	523	rsnd_mod_write(adg_mod, BRRB, rbgb);
524		524

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

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@@ -175,7 +175,7 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data, · 174 unmodified lines
175	{	175	{
176	struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);	176	struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
177	u32 temp, usbc_bit = BIT(phy->index * 2);	177	u32 temp, usbc_bit = BIT(phy->index * 2);
178	void *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;	178	void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
179	int i;	179	int i;
180		180
181	mutex_lock(&phy_data->mutex);	181	mutex_lock(&phy_data->mutex);
@@ -514,9 +514,9 @@ static int sun4i_usb_phy_remove(struct platform_device *pdev) · 332 unmodified lines
514		514
515	if (data->vbus_power_nb_registered)	515	if (data->vbus_power_nb_registered)
516	power_supply_unreg_notifier(&data->vbus_power_nb);	516	power_supply_unreg_notifier(&data->vbus_power_nb);
517	if (data->id_det_irq >= 0)	517	if (data->id_det_irq > 0)
518	devm_free_irq(dev, data->id_det_irq, data);	518	devm_free_irq(dev, data->id_det_irq, data);
519	if (data->vbus_det_irq >= 0)	519	if (data->vbus_det_irq > 0)
520	devm_free_irq(dev, data->vbus_det_irq, data);	520	devm_free_irq(dev, data->vbus_det_irq, data);
521		521
522	cancel_delayed_work_sync(&data->detect);	522	cancel_delayed_work_sync(&data->detect);
@@ -645,11 +645,11 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) · 122 unmodified lines
645		645
646	data->id_det_irq = gpiod_to_irq(data->id_det_gpio);	646	data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
647	data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);	647	data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
648	if ((data->id_det_gpio && data->id_det_irq < 0) \|\|	648	if ((data->id_det_gpio && data->id_det_irq <= 0) \|\|
649	(data->vbus_det_gpio && data->vbus_det_irq < 0))	649	(data->vbus_det_gpio && data->vbus_det_irq <= 0))
650	data->phy0_poll = true;	650	data->phy0_poll = true;
651		651
652	if (data->id_det_irq >= 0) {	652	if (data->id_det_irq > 0) {
653	ret = devm_request_irq(dev, data->id_det_irq,	653	ret = devm_request_irq(dev, data->id_det_irq,
654	sun4i_usb_phy0_id_vbus_det_irq,	654	sun4i_usb_phy0_id_vbus_det_irq,
655	IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING,	655	IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING,
@@ -660,7 +660,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) · 4 unmodified lines
660	}	660	}
661	}	661	}
662		662
663	if (data->vbus_det_irq >= 0) {	663	if (data->vbus_det_irq > 0) {
664	ret = devm_request_irq(dev, data->vbus_det_irq,	664	ret = devm_request_irq(dev, data->vbus_det_irq,
665	sun4i_usb_phy0_id_vbus_det_irq,	665	sun4i_usb_phy0_id_vbus_det_irq,
666	IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING,	666	IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING,