Requires enabling the vblank machinery for them.
Unified · Split
| @@ -463,6 +463,26 @@ static void dm_pflip_high_irq(void *interrupt_params) · 462 unmodified lines | ||
| 463 | 463 | vrr_active, (int) !e); |
| 464 | 464 | } |
| 465 | 465 | |
| 466 | +static void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) | |
| 467 | +{ | |
| 468 | + struct drm_crtc *crtc = &acrtc->base; | |
| 469 | + struct drm_device *dev = crtc->dev; | |
| 470 | + unsigned long flags; | |
| 471 | + | |
| 472 | + drm_crtc_handle_vblank(crtc); | |
| 473 | + | |
| 474 | + spin_lock_irqsave(&dev->event_lock, flags); | |
| 475 | + | |
| 476 | + /* Send completion event for cursor-only commits */ | |
| 477 | + if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { | |
| 478 | + drm_crtc_send_vblank_event(crtc, acrtc->event); | |
| 479 | + drm_crtc_vblank_put(crtc); | |
| 480 | + acrtc->event = NULL; | |
| 481 | + } | |
| 482 | + | |
| 483 | + spin_unlock_irqrestore(&dev->event_lock, flags); | |
| 484 | +} | |
| 485 | + | |
| 466 | 486 | static void dm_vupdate_high_irq(void *interrupt_params) |
| 467 | 487 | { |
| 468 | 488 | struct common_irq_params *irq_params = interrupt_params; |
| @@ -501,7 +521,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) · 32 unmodified lines | ||
| 501 | 521 | * if a pageflip happened inside front-porch. |
| 502 | 522 | */ |
| 503 | 523 | if (vrr_active) { |
| 504 | − drm_crtc_handle_vblank(&acrtc->base); | |
| 524 | + dm_crtc_handle_vblank(acrtc); | |
| 505 | 525 | |
| 506 | 526 | /* BTR processing for pre-DCE12 ASICs */ |
| 507 | 527 | if (acrtc->dm_irq_params.stream && |
| @@ -553,7 +573,7 @@ static void dm_crtc_high_irq(void *interrupt_params) · 45 unmodified lines | ||
| 553 | 573 | * to dm_vupdate_high_irq after end of front-porch. |
| 554 | 574 | */ |
| 555 | 575 | if (!vrr_active) |
| 556 | − drm_crtc_handle_vblank(&acrtc->base); | |
| 576 | + dm_crtc_handle_vblank(acrtc); | |
| 557 | 577 | |
| 558 | 578 | /** |
| 559 | 579 | * Following stuff must happen at start of vblank, for crc |
| @@ -9174,6 +9194,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 8614 unmodified lines | ||
| 9174 | 9194 | struct amdgpu_bo *abo; |
| 9175 | 9195 | uint32_t target_vblank, last_flip_vblank; |
| 9176 | 9196 | bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); |
| 9197 | + bool cursor_update = false; | |
| 9177 | 9198 | bool pflip_present = false; |
| 9178 | 9199 | struct { |
| 9179 | 9200 | struct dc_surface_update surface_updates[MAX_SURFACES]; |
| @@ -9209,8 +9230,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 29 unmodified lines | ||
| 9209 | 9230 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
| 9210 | 9231 | |
| 9211 | 9232 | /* Cursor plane is handled after stream updates */ |
| 9212 | − if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
| 9233 | + if (plane->type == DRM_PLANE_TYPE_CURSOR) { | |
| 9234 | + if ((fb && crtc == pcrtc) || | |
| 9235 | + (old_plane_state->fb && old_plane_state->crtc == pcrtc)) | |
| 9236 | + cursor_update = true; | |
| 9237 | + | |
| 9213 | 9238 | continue; |
| 9239 | + } | |
| 9214 | 9240 | |
| 9215 | 9241 | if (!fb || !crtc || pcrtc != crtc) |
| 9216 | 9242 | continue; |
| @@ -9373,6 +9399,17 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 156 unmodified lines | ||
| 9373 | 9399 | bundle->stream_update.vrr_infopacket = |
| 9374 | 9400 | &acrtc_state->stream->vrr_infopacket; |
| 9375 | 9401 | } |
| 9402 | + } else if (cursor_update && acrtc_state->active_planes > 0 && | |
| 9403 | + !acrtc_state->force_dpms_off && | |
| 9404 | + acrtc_attach->base.state->event) { | |
| 9405 | + drm_crtc_vblank_get(pcrtc); | |
| 9406 | + | |
| 9407 | + spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
| 9408 | + | |
| 9409 | + acrtc_attach->event = acrtc_attach->base.state->event; | |
| 9410 | + acrtc_attach->base.state->event = NULL; | |
| 9411 | + | |
| 9412 | + spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
| 9376 | 9413 | } |
| 9377 | 9414 | |
| 9378 | 9415 | /* Update the planes if changed or disable if we don't have any. */ |