Add a new vEVENTQ type for VINTFs that are assigned to the user space. Simply report the two 64-bit LVCMDQ_ERR_MAPs register values.
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| @@ -1146,10 +1146,12 @@ struct iommufd_vevent_header { · 1145 unmodified lines | ||
| 1146 | 1146 | * enum iommu_veventq_type - Virtual Event Queue Type |
| 1147 | 1147 | * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use |
| 1148 | 1148 | * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue |
| 1149 | + * @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ | |
| 1149 | 1150 | */ |
| 1150 | 1151 | enum iommu_veventq_type { |
| 1151 | 1152 | IOMMU_VEVENTQ_TYPE_DEFAULT = 0, |
| 1152 | 1153 | IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, |
| 1154 | + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2, | |
| 1153 | 1155 | }; |
| 1154 | 1156 | |
| 1155 | 1157 | /** |
| @@ -1173,6 +1175,19 @@ struct iommu_vevent_arm_smmuv3 { · 17 unmodified lines | ||
| 1173 | 1175 | __aligned_le64 evt[4]; |
| 1174 | 1176 | }; |
| 1175 | 1177 | |
| 1178 | +/** | |
| 1179 | + * struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ | |
| 1180 | + * (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV) | |
| 1181 | + * @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian. | |
| 1182 | + * (Refer to register LVCMDQ_ERR_MAPs per VINTF ) | |
| 1183 | + * | |
| 1184 | + * The 128-bit register value from HW exclusively reflect the error bits for a | |
| 1185 | + * Virtual Interface represented by a vIOMMU object. Read and report directly. | |
| 1186 | + */ | |
| 1187 | +struct iommu_vevent_tegra241_cmdqv { | |
| 1188 | + __aligned_le64 lvcmdq_err_map[2]; | |
| 1189 | +}; | |
| 1190 | + | |
| 1176 | 1191 | /** |
| 1177 | 1192 | * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) |
| 1178 | 1193 | * @size: sizeof(struct iommu_veventq_alloc) |