History

Merge branch 'i2c/for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c updates from Wolfram Sang: - mostly driver updates. Bigger ones for mlxcpld and iproc. But most of them are all over the place. - removal of the efm32, sirf, u300, and zte zx bus drivers because of platform removal. So, we have a pleasant diffstat this time. - first set of cleanups in the I2C core as preparation to increase maximum length of SMBus transfers to 255 (as specified in the new standard). Better documentation of struct i2c_msg and its flags stand out here. - the testunit can now respond to SMBus block process calls which is the testcase when implementing the above new maximum length. * 'i2c/for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (62 commits) i2c: remove redundant error print in stm32f7_i2c_probe i2c: testunit: add support for block process calls i2c: busses: Replace spin_lock_irqsave with spin_lock in hard IRQ dt-bindings: eeprom: at24: Document ROHM BR24G01 i2c: i801: Add support for Intel Alder Lake PCH-P i2c: mv64xxx: Fix check for missing clock after adding RPM i2c: mux: mlxcpld: Add callback to notify mux creation completion i2c: mux: mlxcpld: Extend supported mux number i2c: mux: mlxcpld: Extend driver to support word address space devices i2c: mux: mlxcpld: Get rid of adapter numbers enforcement i2c: mux: mlxcpld: Prepare mux selection infrastructure for two-byte support i2c: mux: mlxcpld: Convert driver to platform driver i2c: imx: Synthesize end of transaction events without idle interrupts i2c: i2c-qcom-geni: Add shutdown callback for i2c i2c: mv64xxx: Add runtime PM support i2c: amd-mp2: Remove unused macro i2c: amd-mp2: convert to PCI logging functions i2c: mux: mlxcpld: Move header file out of x86 realm platform/x86: mlxcpld: Update module license i2c: mux: mlxcpld: Update module license ...

Linus Torvalds committed 5 years ago

Commit 32c080c2 parents a26a9d8 0b16cfd44 files · +906 −3201Browse files

Unified · Split

44 files
  1. Documentation/devicetree/bindings/eeprom/at24.yaml +6 −3
  2. Documentation/devicetree/bindings/i2c/i2c-sirf.txt +0 −19
  3. Documentation/devicetree/bindings/i2c/i2c-stu300.txt +0 −15
  4. Documentation/devicetree/bindings/i2c/i2c-zx2967.txt +0 −22
  5. Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +7 −14
  6. Documentation/devicetree/bindings/i2c/renesas,i2c.txt +1 −0
  7. Documentation/i2c/slave-testunit-backend.rst +21 −2
  8. drivers/gpio/gpiolib.c +4 −0
  9. drivers/i2c/algos/i2c-algo-bit.c +1 −3
  10. drivers/i2c/busses/Kconfig +0 −39
  11. drivers/i2c/busses/Makefile +0 −4
  12. drivers/i2c/busses/i2c-amd-mp2-pci.c +23 −32
  13. drivers/i2c/busses/i2c-amd-mp2-plat.c +1 −2
  14. drivers/i2c/busses/i2c-amd-mp2.h +0 −6
  15. drivers/i2c/busses/i2c-bcm-iproc.c +200 −54
  16. drivers/i2c/busses/i2c-digicolor.c +2 −3
  17. drivers/i2c/busses/i2c-efm32.c +0 −469
  18. drivers/i2c/busses/i2c-elektor.c +1 −2
  19. drivers/i2c/busses/i2c-gpio.c +1 −1
  20. drivers/i2c/busses/i2c-hix5hd2.c +1 −3
  21. drivers/i2c/busses/i2c-i801.c +8 −9
  22. drivers/i2c/busses/i2c-imx.c +55 −10
  23. drivers/i2c/busses/i2c-jz4780.c +2 −3
  24. drivers/i2c/busses/i2c-mlxcpld.c +66 −31
  25. drivers/i2c/busses/i2c-mv64xxx.c +79 −43
  26. drivers/i2c/busses/i2c-qcom-geni.c +77 −16
  27. drivers/i2c/busses/i2c-qup.c +1 −1
  28. drivers/i2c/busses/i2c-rcar.c +48 −18
  29. drivers/i2c/busses/i2c-s3c2410.c +1 −1
  30. drivers/i2c/busses/i2c-sirf.c +0 −475
  31. drivers/i2c/busses/i2c-stm32f7.c +1 −5
  32. drivers/i2c/busses/i2c-stu300.c +0 −1008
  33. drivers/i2c/busses/i2c-tegra.c +5 −4
  34. drivers/i2c/busses/i2c-zx2967.c +0 −602
  35. drivers/i2c/i2c-core-acpi.c +1 −5
  36. drivers/i2c/i2c-core-smbus.c +20 −26
  37. drivers/i2c/i2c-slave-testunit.c +10 −2
  38. drivers/i2c/i2c-stub.c +0 −1
  39. drivers/i2c/muxes/i2c-mux-gpio.c +82 −30
  40. drivers/i2c/muxes/i2c-mux-mlxcpld.c +78 −85
  41. include/linux/platform_data/mlxcpld.h +31 −0
  42. include/linux/platform_data/x86/mlxcpld.h +0 −52
  43. include/uapi/linux/i2c-dev.h +5 −20
  44. include/uapi/linux/i2c.h +67 −61
Documentation/devicetree/bindings/eeprom/at24.yaml+6−3
@@ -95,9 +95,6 @@ properties: · 94 unmodified lines
9595 pattern: spd$
9696 # These are special cases that don't conform to the above pattern.
9797 # Each requires a standard at24 model as fallback.
98− - items:
99− - const: rohm,br24t01
100− - const: atmel,24c01
10198 - items:
10299 - const: nxp,se97b
103100 - const: atmel,24c02
@@ -113,6 +110,12 @@ properties: · 9 unmodified lines
113110 - items:
114111 - const: renesas,r1ex24128
115112 - const: atmel,24c128
113+ - items:
114+ - const: rohm,br24g01
115+ - const: atmel,24c01
116+ - items:
117+ - const: rohm,br24t01
118+ - const: atmel,24c01
116119
117120 label:
118121 description: Descriptive name of the EEPROM.
Documentation/devicetree/bindings/i2c/i2c-sirf.txt+0−19
@@ -1,19 +0,0 @@
1−I2C for SiRFprimaII platforms
2−
3−Required properties :
4−- compatible : Must be "sirf,prima2-i2c"
5−- reg: physical base address of the controller and length of memory mapped
6− region.
7−- interrupts: interrupt number to the cpu.
8−
9−Optional properties:
10−- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
11− The absence of the property indicates the default frequency 100 kHz.
12−
13−Examples :
14−
15−i2c0: i2c@b00e0000 {
16− compatible = "sirf,prima2-i2c";
17− reg = <0xb00e0000 0x10000>;
18− interrupts = <24>;
19−};
Documentation/devicetree/bindings/i2c/i2c-stu300.txt+0−15
@@ -1,15 +0,0 @@
1−ST Microelectronics DDC I2C
2−
3−Required properties :
4−- compatible : Must be "st,ddci2c"
5−- reg: physical base address of the controller and length of memory mapped
6− region.
7−- interrupts: interrupt number to the cpu.
8−- #address-cells = <1>;
9−- #size-cells = <0>;
10−
11−Optional properties:
12−- Child nodes conforming to i2c bus binding
13−
14−Examples :
15−
Documentation/devicetree/bindings/i2c/i2c-zx2967.txt+0−22
@@ -1,22 +0,0 @@
1−ZTE zx2967 I2C controller
2−
3−Required properties:
4− - compatible: must be "zte,zx296718-i2c"
5− - reg: physical address and length of the device registers
6− - interrupts: a single interrupt specifier
7− - clocks: clock for the device
8− - #address-cells: should be <1>
9− - #size-cells: should be <0>
10− - clock-frequency: the desired I2C bus clock frequency.
11−
12−Examples:
13−
14− i2c@112000 {
15− compatible = "zte,zx296718-i2c";
16− reg = <0x00112000 0x1000>;
17− interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
18− clocks = <&osc24m>;
19− #address-cells = <1>
20− #size-cells = <0>;
21− clock-frequency = <1600000>;
22− };
Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml+7−14
@@ -18,21 +18,14 @@ properties: · 17 unmodified lines
1818 - const: allwinner,sun4i-a10-i2c
1919 - const: allwinner,sun6i-a31-i2c
2020 - items:
21− - const: allwinner,sun8i-a23-i2c
21+ - enum:
22+ - allwinner,sun8i-a23-i2c
23+ - allwinner,sun8i-a83t-i2c
24+ - allwinner,sun50i-a64-i2c
25+ - allwinner,sun50i-a100-i2c
26+ - allwinner,sun50i-h6-i2c
27+ - allwinner,sun50i-h616-i2c
2228 - const: allwinner,sun6i-a31-i2c
23− - items:
24− - const: allwinner,sun8i-a83t-i2c
25− - const: allwinner,sun6i-a31-i2c
26− - items:
27− - const: allwinner,sun50i-a64-i2c
28− - const: allwinner,sun6i-a31-i2c
29− - items:
30− - const: allwinner,sun50i-a100-i2c
31− - const: allwinner,sun6i-a31-i2c
32− - items:
33− - const: allwinner,sun50i-h6-i2c
34− - const: allwinner,sun6i-a31-i2c
35−
3629 - const: marvell,mv64xxx-i2c
3730 - const: marvell,mv78230-i2c
3831 - const: marvell,mv78230-a0-i2c
Documentation/devicetree/bindings/i2c/renesas,i2c.txt+1−0
@@ -26,6 +26,7 @@ Required properties: · 25 unmodified lines
2626 "renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC.
2727 "renesas,i2c-r8a77990" if the device is a part of a R8A77990 SoC.
2828 "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
29+ "renesas,i2c-r8a779a0" if the device is a part of a R8A779A0 SoC.
2930 "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
3031 "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
3132 device.
Documentation/i2c/slave-testunit-backend.rst+21−2
@@ -22,8 +22,9 @@ Instantiating the device is regular. Example for bus 0, address 0x30: · 21 unmodified lines
2222
2323 After that, you will have a write-only device listening. Reads will just return
2424 an 8-bit version number of the testunit. When writing, the device consists of 4
25−8-bit registers and all must be written to start a testcase, i.e. you must
26−always write 4 bytes to the device. The registers are:
25+8-bit registers and, except for some "partial" commands, all registers must be
26+written to start a testcase, i.e. you usually write 4 bytes to the device. The
27+registers are:
2728
2829 0x00 CMD - which test to trigger
2930 0x01 DATAL - configuration byte 1 for the test
@@ -67,3 +68,21 @@ status word is currently ignored in the Linux Kernel. Example to send a · 37 unmodified lines
6768 notification after 10ms:
6869
6970 # i2cset -y 0 0x30 0x02 0x42 0x64 0x01 i
71+
72+0x03 SMBUS_BLOCK_PROC_CALL (partial command)
73+ DATAL - must be '1', i.e. one further byte will be written
74+ DATAH - number of bytes to be sent back
75+ DELAY - not applicable, partial command!
76+
77+This test will respond to a block process call as defined by the SMBus
78+specification. The one data byte written specifies how many bytes will be sent
79+back in the following read transfer. Note that in this read transfer, the
80+testunit will prefix the length of the bytes to follow. So, if your host bus
81+driver emulates SMBus calls like the majority does, it needs to support the
82+I2C_M_RECV_LEN flag of an i2c_msg. This is a good testcase for it. The returned
83+data consists of the length first, and then of an array of bytes from length-1
84+to 0. Here is an example which emulates i2c_smbus_block_process_call() using
85+i2ctransfer (you need i2c-tools v4.2 or later):
86+
87+# i2ctransfer -y 0 w3@0x30 0x03 0x01 0x10 r?
88+0x10 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
drivers/gpio/gpiolib.c+4−0
@@ -3469,6 +3469,10 @@ EXPORT_SYMBOL_GPL(gpiod_add_lookup_table); · 3468 unmodified lines
34693469 */
34703470 void gpiod_remove_lookup_table(struct gpiod_lookup_table *table)
34713471 {
3472+ /* Nothing to remove */
3473+ if (!table)
3474+ return;
3475+
34723476 mutex_lock(&gpio_lookup_lock);
34733477
34743478 list_del(&table->list);
drivers/i2c/algos/i2c-algo-bit.c+1−3
@@ -622,9 +622,7 @@ static int bit_xfer_atomic(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], · 621 unmodified lines
622622
623623 static u32 bit_func(struct i2c_adapter *adap)
624624 {
625− return I2C_FUNC_I2C | I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_EMUL |
626− I2C_FUNC_SMBUS_READ_BLOCK_DATA |
627− I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
625+ return I2C_FUNC_I2C | I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_EMUL_ALL |
628626 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
629627 }
630628
drivers/i2c/busses/Kconfig+0−39
@@ -586,13 +586,6 @@ config I2C_DIGICOLOR · 585 unmodified lines
586586 This driver can also be built as a module. If so, the module
587587 will be called i2c-digicolor.
588588
589−config I2C_EFM32
590− tristate "EFM32 I2C controller"
591− depends on ARCH_EFM32 || COMPILE_TEST
592− help
593− This driver supports the i2c block found in Energy Micro's EFM32
594− SoCs.
595−
596589 config I2C_EG20T
597590 tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) I2C"
598591 depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
@@ -1000,16 +993,6 @@ config I2C_SIMTEC · 401 unmodified lines
1000993 This driver can also be built as a module. If so, the module
1001994 will be called i2c-simtec.
1002995
1003−config I2C_SIRF
1004− tristate "CSR SiRFprimaII I2C interface"
1005− depends on ARCH_SIRF || COMPILE_TEST
1006− help
1007− If you say yes to this option, support will be included for the
1008− CSR SiRFprimaII I2C interface.
1009−
1010− This driver can also be built as a module. If so, the module
1011− will be called i2c-sirf.
1012−
1013996 config I2C_SPRD
1014997 tristate "Spreadtrum I2C interface"
1015998 depends on I2C=y && (ARCH_SPRD || COMPILE_TEST)
@@ -1050,19 +1033,6 @@ config I2C_STM32F7 · 34 unmodified lines
10501033 This driver can also be built as module. If so, the module
10511034 will be called i2c-stm32f7.
10521035
1053−config I2C_STU300
1054− tristate "ST Microelectronics DDC I2C interface"
1055− depends on MACH_U300 || COMPILE_TEST
1056− default y if MACH_U300
1057− help
1058− If you say yes to this option, support will be included for the
1059− I2C interface from ST Microelectronics simply called "DDC I2C"
1060− supporting both I2C and DDC, used in e.g. the U300 series
1061− mobile platforms.
1062−
1063− This driver can also be built as a module. If so, the module
1064− will be called i2c-stu300.
1065−
10661036 config I2C_SUN6I_P2WI
10671037 tristate "Allwinner sun6i internal P2WI controller"
10681038 depends on RESET_CONTROLLER
@@ -1401,15 +1371,6 @@ config I2C_OPAL · 332 unmodified lines
14011371 This driver can also be built as a module. If so, the module will be
14021372 called as i2c-opal.
14031373
1404−config I2C_ZX2967
1405− tristate "ZTE ZX2967 I2C support"
1406− depends on ARCH_ZX
1407− default y
1408− help
1409− Selecting this option will add ZX2967 I2C driver.
1410− This driver can also be built as a module. If so, the module will be
1411− called i2c-zx2967.
1412−
14131374 config I2C_FSI
14141375 tristate "FSI I2C driver"
14151376 depends on FSI
drivers/i2c/busses/Makefile+0−4
@@ -58,7 +58,6 @@ i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_BAYTRAIL) += i2c-designware-bayt · 57 unmodified lines
5858 obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
5959 i2c-designware-pci-y := i2c-designware-pcidrv.o
6060 obj-$(CONFIG_I2C_DIGICOLOR) += i2c-digicolor.o
61−obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o
6261 obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
6362 obj-$(CONFIG_I2C_EMEV2) += i2c-emev2.o
6463 obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
@@ -99,13 +98,11 @@ obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o · 34 unmodified lines
9998 obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
10099 obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
101100 obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
102−obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o
103101 obj-$(CONFIG_I2C_SPRD) += i2c-sprd.o
104102 obj-$(CONFIG_I2C_ST) += i2c-st.o
105103 obj-$(CONFIG_I2C_STM32F4) += i2c-stm32f4.o
106104 i2c-stm32f7-drv-objs := i2c-stm32f7.o i2c-stm32.o
107105 obj-$(CONFIG_I2C_STM32F7) += i2c-stm32f7-drv.o
108−obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
109106 obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o
110107 obj-$(CONFIG_I2C_SYNQUACER) += i2c-synquacer.o
111108 obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
@@ -122,7 +119,6 @@ obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o · 10 unmodified lines
122119 obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
123120 obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
124121 obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
125−obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
126122
127123 # External I2C/SMBus adapter drivers
128124 obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
drivers/i2c/busses/i2c-amd-mp2-pci.c+23−32
@@ -30,7 +30,7 @@ static void amd_mp2_c2p_mutex_unlock(struct amd_i2c_common *i2c_common) · 29 unmodified lines
3030 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
3131
3232 if (unlikely(privdata->c2p_lock_busid != i2c_common->bus_id)) {
33− dev_warn(ndev_dev(privdata),
33+ pci_warn(privdata->pci_dev,
3434 "bus %d attempting to unlock C2P locked by bus %d\n",
3535 i2c_common->bus_id, privdata->c2p_lock_busid);
3636 return;
@@ -59,8 +59,7 @@ int amd_mp2_bus_enable_set(struct amd_i2c_common *i2c_common, bool enable) · 22 unmodified lines
5959 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
6060 union i2c_cmd_base i2c_cmd_base;
6161
62− dev_dbg(ndev_dev(privdata), "%s id: %d\n", __func__,
63− i2c_common->bus_id);
62+ pci_dbg(privdata->pci_dev, "id: %d\n", i2c_common->bus_id);
6463
6564 i2c_cmd_base.ul = 0;
6665 i2c_cmd_base.s.i2c_cmd = enable ? i2c_enable : i2c_disable;
@@ -111,20 +110,19 @@ EXPORT_SYMBOL_GPL(amd_mp2_rw); · 44 unmodified lines
111110 static void amd_mp2_pci_check_rw_event(struct amd_i2c_common *i2c_common)
112111 {
113112 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
113+ struct pci_dev *pdev = privdata->pci_dev;
114114 int len = i2c_common->eventval.r.length;
115115 u32 slave_addr = i2c_common->eventval.r.slave_addr;
116116 bool err = false;
117117
118118 if (unlikely(len != i2c_common->msg->len)) {
119− dev_err(ndev_dev(privdata),
120− "length %d in event doesn't match buffer length %d!\n",
119+ pci_err(pdev, "length %d in event doesn't match buffer length %d!\n",
121120 len, i2c_common->msg->len);
122121 err = true;
123122 }
124123
125124 if (unlikely(slave_addr != i2c_common->msg->addr)) {
126− dev_err(ndev_dev(privdata),
127− "unexpected slave address %x (expected: %x)!\n",
125+ pci_err(pdev, "unexpected slave address %x (expected: %x)!\n",
128126 slave_addr, i2c_common->msg->addr);
129127 err = true;
130128 }
@@ -136,13 +134,14 @@ static void amd_mp2_pci_check_rw_event(struct amd_i2c_common *i2c_common) · 5 unmodified lines
136134 static void __amd_mp2_process_event(struct amd_i2c_common *i2c_common)
137135 {
138136 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
137+ struct pci_dev *pdev = privdata->pci_dev;
139138 enum status_type sts = i2c_common->eventval.r.status;
140139 enum response_type res = i2c_common->eventval.r.response;
141140 int len = i2c_common->eventval.r.length;
142141
143142 if (res != command_success) {
144143 if (res != command_failed)
145− dev_err(ndev_dev(privdata), "invalid response to i2c command!\n");
144+ pci_err(pdev, "invalid response to i2c command!\n");
146145 return;
147146 }
148147
@@ -155,32 +154,26 @@ static void __amd_mp2_process_event(struct amd_i2c_common *i2c_common) · 6 unmodified lines
155154 privdata->mmio + AMD_C2P_MSG2,
156155 len);
157156 } else if (sts != i2c_readfail_event) {
158− dev_err(ndev_dev(privdata),
159− "invalid i2c status after read (%d)!\n", sts);
157+ pci_err(pdev, "invalid i2c status after read (%d)!\n", sts);
160158 }
161159 break;
162160 case i2c_write:
163161 if (sts == i2c_writecomplete_event)
164162 amd_mp2_pci_check_rw_event(i2c_common);
165163 else if (sts != i2c_writefail_event)
166− dev_err(ndev_dev(privdata),
167− "invalid i2c status after write (%d)!\n", sts);
164+ pci_err(pdev, "invalid i2c status after write (%d)!\n", sts);
168165 break;
169166 case i2c_enable:
170167 if (sts == i2c_busenable_complete)
171168 i2c_common->cmd_success = true;
172169 else if (sts != i2c_busenable_failed)
173− dev_err(ndev_dev(privdata),
174− "invalid i2c status after bus enable (%d)!\n",
175− sts);
170+ pci_err(pdev, "invalid i2c status after bus enable (%d)!\n", sts);
176171 break;
177172 case i2c_disable:
178173 if (sts == i2c_busdisable_complete)
179174 i2c_common->cmd_success = true;
180175 else if (sts != i2c_busdisable_failed)
181− dev_err(ndev_dev(privdata),
182− "invalid i2c status after bus disable (%d)!\n",
183− sts);
176+ pci_err(pdev, "invalid i2c status after bus disable (%d)!\n", sts);
184177 break;
185178 default:
186179 break;
@@ -190,10 +183,10 @@ static void __amd_mp2_process_event(struct amd_i2c_common *i2c_common) · 3 unmodified lines
190183 void amd_mp2_process_event(struct amd_i2c_common *i2c_common)
191184 {
192185 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
186+ struct pci_dev *pdev = privdata->pci_dev;
193187
194188 if (unlikely(i2c_common->reqcmd == i2c_none)) {
195− dev_warn(ndev_dev(privdata),
196− "received msg but no cmd was sent (bus = %d)!\n",
189+ pci_warn(pdev, "received msg but no cmd was sent (bus = %d)!\n",
197190 i2c_common->bus_id);
198191 return;
199192 }
@@ -208,6 +201,7 @@ EXPORT_SYMBOL_GPL(amd_mp2_process_event); · 8 unmodified lines
208201 static irqreturn_t amd_mp2_irq_isr(int irq, void *dev)
209202 {
210203 struct amd_mp2_dev *privdata = dev;
204+ struct pci_dev *pdev = privdata->pci_dev;
211205 struct amd_i2c_common *i2c_common;
212206 u32 val;
213207 unsigned int bus_id;
@@ -236,8 +230,7 @@ static irqreturn_t amd_mp2_irq_isr(int irq, void *dev) · 22 unmodified lines
236230 val = readl(privdata->mmio + AMD_P2C_MSG_INTEN);
237231 if (val != 0) {
238232 writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
239− dev_warn(ndev_dev(privdata),
240− "received irq without message\n");
233+ pci_warn(pdev, "received irq without message\n");
241234 ret = IRQ_HANDLED;
242235 }
243236 }
@@ -255,13 +248,13 @@ EXPORT_SYMBOL_GPL(amd_mp2_rw_timeout); · 11 unmodified lines
255248 int amd_mp2_register_cb(struct amd_i2c_common *i2c_common)
256249 {
257250 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
251+ struct pci_dev *pdev = privdata->pci_dev;
258252
259253 if (i2c_common->bus_id > 1)
260254 return -EINVAL;
261255
262256 if (privdata->busses[i2c_common->bus_id]) {
263− dev_err(ndev_dev(privdata),
264− "Bus %d already taken!\n", i2c_common->bus_id);
257+ pci_err(pdev, "Bus %d already taken!\n", i2c_common->bus_id);
265258 return -EINVAL;
266259 }
267260
@@ -301,13 +294,13 @@ static int amd_mp2_pci_init(struct amd_mp2_dev *privdata, · 33 unmodified lines
301294
302295 rc = pcim_enable_device(pci_dev);
303296 if (rc) {
304− dev_err(ndev_dev(privdata), "Failed to enable MP2 PCI device\n");
297+ pci_err(pci_dev, "Failed to enable MP2 PCI device\n");
305298 goto err_pci_enable;
306299 }
307300
308301 rc = pcim_iomap_regions(pci_dev, 1 << 2, pci_name(pci_dev));
309302 if (rc) {
310− dev_err(ndev_dev(privdata), "I/O memory remapping failed\n");
303+ pci_err(pci_dev, "I/O memory remapping failed\n");
311304 goto err_pci_enable;
312305 }
313306 privdata->mmio = pcim_iomap_table(pci_dev)[2];
@@ -327,7 +320,7 @@ static int amd_mp2_pci_init(struct amd_mp2_dev *privdata, · 13 unmodified lines
327320 rc = devm_request_irq(&pci_dev->dev, pci_dev->irq, amd_mp2_irq_isr,
328321 IRQF_SHARED, dev_name(&pci_dev->dev), privdata);
329322 if (rc)
330− dev_err(&pci_dev->dev, "Failure requesting irq %i: %d\n",
323+ pci_err(pci_dev, "Failure requesting irq %i: %d\n",
331324 pci_dev->irq, rc);
332325
333326 return rc;
@@ -363,7 +356,7 @@ static int amd_mp2_pci_probe(struct pci_dev *pci_dev, · 29 unmodified lines
363356
364357 privdata->probed = true;
365358
366− dev_info(&pci_dev->dev, "MP2 device registered.\n");
359+ pci_info(pci_dev, "MP2 device registered.\n");
367360 return 0;
368361 }
369362
@@ -397,8 +390,7 @@ static int amd_mp2_pci_suspend(struct device *dev) · 27 unmodified lines
397390
398391 ret = pci_save_state(pci_dev);
399392 if (ret) {
400− dev_err(ndev_dev(privdata),
401− "pci_save_state failed = %d\n", ret);
393+ pci_err(pci_dev, "pci_save_state failed = %d\n", ret);
402394 return ret;
403395 }
404396
@@ -417,8 +409,7 @@ static int amd_mp2_pci_resume(struct device *dev) · 12 unmodified lines
417409 pci_restore_state(pci_dev);
418410 ret = pci_enable_device(pci_dev);
419411 if (ret < 0) {
420− dev_err(ndev_dev(privdata),
421− "pci_enable_device failed = %d\n", ret);
412+ pci_err(pci_dev, "pci_enable_device failed = %d\n", ret);
422413 return ret;
423414 }
424415
drivers/i2c/busses/i2c-amd-mp2-plat.c+1−2
@@ -88,8 +88,7 @@ static void i2c_amd_cmd_completion(struct amd_i2c_common *i2c_common) · 87 unmodified lines
8888 union i2c_event *event = &i2c_common->eventval;
8989
9090 if (event->r.status == i2c_readcomplete_event)
91− dev_dbg(&i2c_dev->pdev->dev, "%s readdata:%*ph\n",
92− __func__, event->r.length,
91+ dev_dbg(&i2c_dev->pdev->dev, "readdata:%*ph\n", event->r.length,
9392 i2c_common->msg->buf);
9493
9594 complete(&i2c_dev->cmd_complete);
drivers/i2c/busses/i2c-amd-mp2.h+0−6
@@ -185,12 +185,6 @@ struct amd_mp2_dev { · 184 unmodified lines
185185 unsigned int probed;
186186 };
187187
188−#define ndev_pdev(ndev) ((ndev)->pci_dev)
189−#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
190−#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
191−#define work_amd_i2c_common(__work) \
192− container_of(__work, struct amd_i2c_common, work.work)
193−
194188 /* PCIe communication driver */
195189
196190 int amd_mp2_rw(struct amd_i2c_common *i2c_common, enum i2c_cmd reqcmd);
drivers/i2c/busses/i2c-bcm-iproc.c+200−54
@@ -93,6 +93,7 @@ · 92 unmodified lines
9393 #define S_CMD_STATUS_MASK 0x07
9494 #define S_CMD_STATUS_SUCCESS 0x0
9595 #define S_CMD_STATUS_TIMEOUT 0x5
96+#define S_CMD_STATUS_MASTER_ABORT 0x7
9697
9798 #define IE_OFFSET 0x38
9899 #define IE_M_RX_FIFO_FULL_SHIFT 31
@@ -159,6 +160,11 @@ · 60 unmodified lines
159160
160161 #define IE_S_ALL_INTERRUPT_SHIFT 21
161162 #define IE_S_ALL_INTERRUPT_MASK 0x3f
163+/*
164+ * It takes ~18us to reading 10bytes of data, hence to keep tasklet
165+ * running for less time, max slave read per tasklet is set to 10 bytes.
166+ */
167+#define MAX_SLAVE_RX_PER_INT 10
162168
163169 enum i2c_slave_read_status {
164170 I2C_SLAVE_RX_FIFO_EMPTY = 0,
@@ -205,8 +211,18 @@ struct bcm_iproc_i2c_dev { · 40 unmodified lines
205211 /* bytes that have been read */
206212 unsigned int rx_bytes;
207213 unsigned int thld_bytes;
214+
215+ bool slave_rx_only;
216+ bool rx_start_rcvd;
217+ bool slave_read_complete;
218+ u32 tx_underrun;
219+ u32 slave_int_mask;
220+ struct tasklet_struct slave_rx_tasklet;
208221 };
209222
223+/* tasklet to process slave rx data */
224+static void slave_rx_tasklet_fn(unsigned long);
225+
210226 /*
211227 * Can be expanded in the future if more interrupt status bits are utilized
212228 */
@@ -215,7 +231,8 @@ struct bcm_iproc_i2c_dev { · 2 unmodified lines
215231
216232 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
217233 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
218− | BIT(IS_S_TX_UNDERRUN_SHIFT))
234+ | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
235+ | BIT(IS_S_RX_THLD_SHIFT))
219236
220237 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
221238 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
@@ -259,6 +276,7 @@ static void bcm_iproc_i2c_slave_init( · 37 unmodified lines
259276 {
260277 u32 val;
261278
279+ iproc_i2c->tx_underrun = 0;
262280 if (need_reset) {
263281 /* put controller in reset */
264282 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
@@ -295,8 +313,13 @@ static void bcm_iproc_i2c_slave_init( · 30 unmodified lines
295313
296314 /* Enable interrupt register to indicate a valid byte in receive fifo */
297315 val = BIT(IE_S_RX_EVENT_SHIFT);
316+ /* Enable interrupt register to indicate Slave Rx FIFO Full */
317+ val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);
318+ /* Enable interrupt register to indicate a Master read transaction */
319+ val |= BIT(IE_S_RD_EVENT_SHIFT);
298320 /* Enable interrupt register for the Slave BUSY command */
299321 val |= BIT(IE_S_START_BUSY_SHIFT);
322+ iproc_i2c->slave_int_mask = val;
300323 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
301324 }
302325
@@ -311,9 +334,10 @@ static void bcm_iproc_i2c_check_slave_status( · 8 unmodified lines
311334 return;
312335
313336 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
314− if (val == S_CMD_STATUS_TIMEOUT) {
315− dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
316−
337+ if (val == S_CMD_STATUS_TIMEOUT || val == S_CMD_STATUS_MASTER_ABORT) {
338+ dev_err(iproc_i2c->device, (val == S_CMD_STATUS_TIMEOUT) ?
339+ "slave random stretch time timeout\n" :
340+ "Master aborted read transaction\n");
317341 /* re-initialize i2c for recovery */
318342 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
319343 bcm_iproc_i2c_slave_init(iproc_i2c, true);
@@ -321,76 +345,187 @@ static void bcm_iproc_i2c_check_slave_status( · 1 unmodified line
321345 }
322346 }
323347
324−static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
325− u32 status)
348+static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
326349 {
350+ u8 rx_data, rx_status;
351+ u32 rx_bytes = 0;
327352 u32 val;
328− u8 value, rx_status;
329353
330− /* Slave RX byte receive */
331− if (status & BIT(IS_S_RX_EVENT_SHIFT)) {
354+ while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
332355 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
333356 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
334− if (rx_status == I2C_SLAVE_RX_START) {
335− /* Start of SMBUS for Master write */
336− i2c_slave_event(iproc_i2c->slave,
337− I2C_SLAVE_WRITE_REQUESTED, &value);
357+ rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
338358
339− val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
340− value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
359+ if (rx_status == I2C_SLAVE_RX_START) {
360+ /* Start of SMBUS Master write */
341361 i2c_slave_event(iproc_i2c->slave,
342− I2C_SLAVE_WRITE_RECEIVED, &value);
343− } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
344− /* Start of SMBUS for Master Read */
362+ I2C_SLAVE_WRITE_REQUESTED, &rx_data);
363+ iproc_i2c->rx_start_rcvd = true;
364+ iproc_i2c->slave_read_complete = false;
365+ } else if (rx_status == I2C_SLAVE_RX_DATA &&
366+ iproc_i2c->rx_start_rcvd) {
367+ /* Middle of SMBUS Master write */
345368 i2c_slave_event(iproc_i2c->slave,
346− I2C_SLAVE_READ_REQUESTED, &value);
347− iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
369+ I2C_SLAVE_WRITE_RECEIVED, &rx_data);
370+ } else if (rx_status == I2C_SLAVE_RX_END &&
371+ iproc_i2c->rx_start_rcvd) {
372+ /* End of SMBUS Master write */
373+ if (iproc_i2c->slave_rx_only)
374+ i2c_slave_event(iproc_i2c->slave,
375+ I2C_SLAVE_WRITE_RECEIVED,
376+ &rx_data);
377+
378+ i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
379+ &rx_data);
380+ } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
381+ iproc_i2c->rx_start_rcvd = false;
382+ iproc_i2c->slave_read_complete = true;
383+ break;
384+ }
348385
349− val = BIT(S_CMD_START_BUSY_SHIFT);
350− iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
386+ rx_bytes++;
387+ }
388+}
351389
352− /*
353− * Enable interrupt for TX FIFO becomes empty and
354− * less than PKT_LENGTH bytes were output on the SMBUS
355− */
356− val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
357− val |= BIT(IE_S_TX_UNDERRUN_SHIFT);
358− iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
359− } else {
360− /* Master write other than start */
361− value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
390+static void slave_rx_tasklet_fn(unsigned long data)
391+{
392+ struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
393+ u32 int_clr;
394+
395+ bcm_iproc_i2c_slave_read(iproc_i2c);
396+
397+ /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
398+ int_clr = BIT(IS_S_RX_EVENT_SHIFT);
399+
400+ if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
401+ /*
402+ * In case of single byte master-read request,
403+ * IS_S_TX_UNDERRUN_SHIFT event is generated before
404+ * IS_S_START_BUSY_SHIFT event. Hence start slave data send
405+ * from first IS_S_TX_UNDERRUN_SHIFT event.
406+ *
407+ * This means don't send any data from slave when
408+ * IS_S_RD_EVENT_SHIFT event is generated else it will increment
409+ * eeprom or other backend slave driver read pointer twice.
410+ */
411+ iproc_i2c->tx_underrun = 0;
412+ iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
413+
414+ /* clear IS_S_RD_EVENT_SHIFT interrupt */
415+ int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
416+ }
417+
418+ /* clear slave interrupt */
419+ iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
420+ /* enable slave interrupts */
421+ iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
422+}
423+
424+static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
425+ u32 status)
426+{
427+ u32 val;
428+ u8 value;
429+
430+ /*
431+ * Slave events in case of master-write, master-write-read and,
432+ * master-read
433+ *
434+ * Master-write : only IS_S_RX_EVENT_SHIFT event
435+ * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
436+ * events
437+ * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
438+ * events or only IS_S_RD_EVENT_SHIFT
439+ *
440+ * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt
441+ * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes
442+ * full. This can happen if Master issues write requests of more than
443+ * 64 bytes.
444+ */
445+ if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
446+ status & BIT(IS_S_RD_EVENT_SHIFT) ||
447+ status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
448+ /* disable slave interrupts */
449+ val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
450+ val &= ~iproc_i2c->slave_int_mask;
451+ iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
452+
453+ if (status & BIT(IS_S_RD_EVENT_SHIFT))
454+ /* Master-write-read request */
455+ iproc_i2c->slave_rx_only = false;
456+ else
457+ /* Master-write request only */
458+ iproc_i2c->slave_rx_only = true;
459+
460+ /* schedule tasklet to read data later */
461+ tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
462+
463+ /*
464+ * clear only IS_S_RX_EVENT_SHIFT and
465+ * IS_S_RX_FIFO_FULL_SHIFT interrupt.
466+ */
467+ val = BIT(IS_S_RX_EVENT_SHIFT);
468+ if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT))
469+ val |= BIT(IS_S_RX_FIFO_FULL_SHIFT);
470+ iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val);
471+ }
472+
473+ if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
474+ iproc_i2c->tx_underrun++;
475+ if (iproc_i2c->tx_underrun == 1)
476+ /* Start of SMBUS for Master Read */
362477 i2c_slave_event(iproc_i2c->slave,
363− I2C_SLAVE_WRITE_RECEIVED, &value);
364− if (rx_status == I2C_SLAVE_RX_END)
365− i2c_slave_event(iproc_i2c->slave,
366− I2C_SLAVE_STOP, &value);
367− }
368− } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
369− /* Master read other than start */
370− i2c_slave_event(iproc_i2c->slave,
371− I2C_SLAVE_READ_PROCESSED, &value);
478+ I2C_SLAVE_READ_REQUESTED,
479+ &value);
480+ else
481+ /* Master read other than start */
482+ i2c_slave_event(iproc_i2c->slave,
483+ I2C_SLAVE_READ_PROCESSED,
484+ &value);
372485
373486 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
487+ /* start transfer */
374488 val = BIT(S_CMD_START_BUSY_SHIFT);
375489 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
490+
491+ /* clear interrupt */
492+ iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
493+ BIT(IS_S_TX_UNDERRUN_SHIFT));
376494 }
377495
378− /* Stop */
496+ /* Stop received from master in case of master read transaction */
379497 if (status & BIT(IS_S_START_BUSY_SHIFT)) {
380− i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
381498 /*
382− * Enable interrupt for TX FIFO becomes empty and
499+ * Disable interrupt for TX FIFO becomes empty and
383500 * less than PKT_LENGTH bytes were output on the SMBUS
384501 */
385− val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
386− val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
387− iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
502+ iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
503+ iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
504+ iproc_i2c->slave_int_mask);
505+
506+ /* End of SMBUS for Master Read */
507+ val = BIT(S_TX_WR_STATUS_SHIFT);
508+ iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
509+
510+ val = BIT(S_CMD_START_BUSY_SHIFT);
511+ iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
512+
513+ /* flush TX FIFOs */
514+ val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
515+ val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
516+ iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
517+
518+ i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
519+
520+ /* clear interrupt */
521+ iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
522+ BIT(IS_S_START_BUSY_SHIFT));
388523 }
389524
390− /* clear interrupt status */
391− iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
525+ /* check slave transmit status only if slave is transmitting */
526+ if (!iproc_i2c->slave_rx_only)
527+ bcm_iproc_i2c_check_slave_status(iproc_i2c);
392528
393− bcm_iproc_i2c_check_slave_status(iproc_i2c);
394529 return true;
395530 }
396531
@@ -505,12 +640,17 @@ static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, · 108 unmodified lines
505640 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
506641 {
507642 struct bcm_iproc_i2c_dev *iproc_i2c = data;
508− u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
643+ u32 slave_status;
644+ u32 status;
509645 bool ret;
510− u32 sl_status = status & ISR_MASK_SLAVE;
511646
512− if (sl_status) {
513− ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status);
647+ status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
648+ /* process only slave interrupt which are enabled */
649+ slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
650+ ISR_MASK_SLAVE;
651+
652+ if (slave_status) {
653+ ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
514654 if (ret)
515655 return IRQ_HANDLED;
516656 else
@@ -1066,6 +1206,10 @@ static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave) · 549 unmodified lines
10661206 return -EAFNOSUPPORT;
10671207
10681208 iproc_i2c->slave = slave;
1209+
1210+ tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1211+ (unsigned long)iproc_i2c);
1212+
10691213 bcm_iproc_i2c_slave_init(iproc_i2c, false);
10701214 return 0;
10711215 }
@@ -1086,6 +1230,8 @@ static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) · 14 unmodified lines
10861230 IE_S_ALL_INTERRUPT_SHIFT);
10871231 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
10881232
1233+ tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1234+
10891235 /* Erase the slave address programmed */
10901236 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
10911237 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
drivers/i2c/busses/i2c-digicolor.c+2−3
@@ -160,12 +160,11 @@ static irqreturn_t dc_i2c_irq(int irq, void *dev_id) · 159 unmodified lines
160160 {
161161 struct dc_i2c *i2c = dev_id;
162162 int cmd_status = dc_i2c_cmd_status(i2c);
163− unsigned long flags;
164163 u8 addr_cmd;
165164
166165 writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);
167166
168− spin_lock_irqsave(&i2c->lock, flags);
167+ spin_lock(&i2c->lock);
169168
170169 if (cmd_status == II_CMD_STATUS_ACK_BAD
171170 || cmd_status == II_CMD_STATUS_ABORT) {
@@ -207,7 +206,7 @@ static irqreturn_t dc_i2c_irq(int irq, void *dev_id) · 35 unmodified lines
207206 }
208207
209208 out:
210− spin_unlock_irqrestore(&i2c->lock, flags);
209+ spin_unlock(&i2c->lock);
211210 return IRQ_HANDLED;
212211 }
213212
drivers/i2c/busses/i2c-efm32.c+0−469
@@ -1,469 +0,0 @@
1−// SPDX-License-Identifier: GPL-2.0-only
2−/*
3− * Copyright (C) 2014 Uwe Kleine-Koenig for Pengutronix
4− */
5−#include <linux/module.h>
6−#include <linux/platform_device.h>
7−#include <linux/i2c.h>
8−#include <linux/io.h>
9−#include <linux/interrupt.h>
10−#include <linux/err.h>
11−#include <linux/clk.h>
12−
13−#define DRIVER_NAME "efm32-i2c"
14−
15−#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask)
16−
17−#define REG_CTRL 0x00
18−#define REG_CTRL_EN 0x00001
19−#define REG_CTRL_SLAVE 0x00002
20−#define REG_CTRL_AUTOACK 0x00004
21−#define REG_CTRL_AUTOSE 0x00008
22−#define REG_CTRL_AUTOSN 0x00010
23−#define REG_CTRL_ARBDIS 0x00020
24−#define REG_CTRL_GCAMEN 0x00040
25−#define REG_CTRL_CLHR__MASK 0x00300
26−#define REG_CTRL_BITO__MASK 0x03000
27−#define REG_CTRL_BITO_OFF 0x00000
28−#define REG_CTRL_BITO_40PCC 0x01000
29−#define REG_CTRL_BITO_80PCC 0x02000
30−#define REG_CTRL_BITO_160PCC 0x03000
31−#define REG_CTRL_GIBITO 0x08000
32−#define REG_CTRL_CLTO__MASK 0x70000
33−#define REG_CTRL_CLTO_OFF 0x00000
34−
35−#define REG_CMD 0x04
36−#define REG_CMD_START 0x00001
37−#define REG_CMD_STOP 0x00002
38−#define REG_CMD_ACK 0x00004
39−#define REG_CMD_NACK 0x00008
40−#define REG_CMD_CONT 0x00010
41−#define REG_CMD_ABORT 0x00020
42−#define REG_CMD_CLEARTX 0x00040
43−#define REG_CMD_CLEARPC 0x00080
44−
45−#define REG_STATE 0x08
46−#define REG_STATE_BUSY 0x00001
47−#define REG_STATE_MASTER 0x00002
48−#define REG_STATE_TRANSMITTER 0x00004
49−#define REG_STATE_NACKED 0x00008
50−#define REG_STATE_BUSHOLD 0x00010
51−#define REG_STATE_STATE__MASK 0x000e0
52−#define REG_STATE_STATE_IDLE 0x00000
53−#define REG_STATE_STATE_WAIT 0x00020
54−#define REG_STATE_STATE_START 0x00040
55−#define REG_STATE_STATE_ADDR 0x00060
56−#define REG_STATE_STATE_ADDRACK 0x00080
57−#define REG_STATE_STATE_DATA 0x000a0
58−#define REG_STATE_STATE_DATAACK 0x000c0
59−
60−#define REG_STATUS 0x0c
61−#define REG_STATUS_PSTART 0x00001
62−#define REG_STATUS_PSTOP 0x00002
63−#define REG_STATUS_PACK 0x00004
64−#define REG_STATUS_PNACK 0x00008
65−#define REG_STATUS_PCONT 0x00010
66−#define REG_STATUS_PABORT 0x00020
67−#define REG_STATUS_TXC 0x00040
68−#define REG_STATUS_TXBL 0x00080
69−#define REG_STATUS_RXDATAV 0x00100
70−
71−#define REG_CLKDIV 0x10
72−#define REG_CLKDIV_DIV__MASK 0x001ff
73−#define REG_CLKDIV_DIV(div) MASK_VAL(REG_CLKDIV_DIV__MASK, (div))
74−
75−#define REG_SADDR 0x14
76−#define REG_SADDRMASK 0x18
77−#define REG_RXDATA 0x1c
78−#define REG_RXDATAP 0x20
79−#define REG_TXDATA 0x24
80−#define REG_IF 0x28
81−#define REG_IF_START 0x00001
82−#define REG_IF_RSTART 0x00002
83−#define REG_IF_ADDR 0x00004
84−#define REG_IF_TXC 0x00008
85−#define REG_IF_TXBL 0x00010
86−#define REG_IF_RXDATAV 0x00020
87−#define REG_IF_ACK 0x00040
88−#define REG_IF_NACK 0x00080
89−#define REG_IF_MSTOP 0x00100
90−#define REG_IF_ARBLOST 0x00200
91−#define REG_IF_BUSERR 0x00400
92−#define REG_IF_BUSHOLD 0x00800
93−#define REG_IF_TXOF 0x01000
94−#define REG_IF_RXUF 0x02000
95−#define REG_IF_BITO 0x04000
96−#define REG_IF_CLTO 0x08000
97−#define REG_IF_SSTOP 0x10000
98−
99−#define REG_IFS 0x2c
100−#define REG_IFC 0x30
101−#define REG_IFC__MASK 0x1ffcf
102−
103−#define REG_IEN 0x34
104−
105−#define REG_ROUTE 0x38
106−#define REG_ROUTE_SDAPEN 0x00001
107−#define REG_ROUTE_SCLPEN 0x00002
108−#define REG_ROUTE_LOCATION__MASK 0x00700
109−#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
110−
111−struct efm32_i2c_ddata {
112− struct i2c_adapter adapter;
113−
114− struct clk *clk;
115− void __iomem *base;
116− unsigned int irq;
117− u8 location;
118− unsigned long frequency;
119−
120− /* transfer data */
121− struct completion done;
122− struct i2c_msg *msgs;
123− size_t num_msgs;
124− size_t current_word, current_msg;
125− int retval;
126−};
127−
128−static u32 efm32_i2c_read32(struct efm32_i2c_ddata *ddata, unsigned offset)
129−{
130− return readl(ddata->base + offset);
131−}
132−
133−static void efm32_i2c_write32(struct efm32_i2c_ddata *ddata,
134− unsigned offset, u32 value)
135−{
136− writel(value, ddata->base + offset);
137−}
138−
139−static void efm32_i2c_send_next_msg(struct efm32_i2c_ddata *ddata)
140−{
141− struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
142−
143− efm32_i2c_write32(ddata, REG_CMD, REG_CMD_START);
144− efm32_i2c_write32(ddata, REG_TXDATA, i2c_8bit_addr_from_msg(cur_msg));
145−}
146−
147−static void efm32_i2c_send_next_byte(struct efm32_i2c_ddata *ddata)
148−{
149− struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
150−
151− if (ddata->current_word >= cur_msg->len) {
152− /* cur_msg completely transferred */
153− ddata->current_word = 0;
154− ddata->current_msg += 1;
155−
156− if (ddata->current_msg >= ddata->num_msgs) {
157− efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
158− complete(&ddata->done);
159− } else {
160− efm32_i2c_send_next_msg(ddata);
161− }
162− } else {
163− efm32_i2c_write32(ddata, REG_TXDATA,
164− cur_msg->buf[ddata->current_word++]);
165− }
166−}
167−
168−static void efm32_i2c_recv_next_byte(struct efm32_i2c_ddata *ddata)
169−{
170− struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
171−
172− cur_msg->buf[ddata->current_word] = efm32_i2c_read32(ddata, REG_RXDATA);
173− ddata->current_word += 1;
174− if (ddata->current_word >= cur_msg->len) {
175− /* cur_msg completely transferred */
176− ddata->current_word = 0;
177− ddata->current_msg += 1;
178−
179− efm32_i2c_write32(ddata, REG_CMD, REG_CMD_NACK);
180−
181− if (ddata->current_msg >= ddata->num_msgs) {
182− efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
183− complete(&ddata->done);
184− } else {
185− efm32_i2c_send_next_msg(ddata);
186− }
187− } else {
188− efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ACK);
189− }
190−}
191−
192−static irqreturn_t efm32_i2c_irq(int irq, void *dev_id)
193−{
194− struct efm32_i2c_ddata *ddata = dev_id;
195− struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
196− u32 irqflag = efm32_i2c_read32(ddata, REG_IF);
197− u32 state = efm32_i2c_read32(ddata, REG_STATE);
198−
199− efm32_i2c_write32(ddata, REG_IFC, irqflag & REG_IFC__MASK);
200−
201− switch (state & REG_STATE_STATE__MASK) {
202− case REG_STATE_STATE_IDLE:
203− /* arbitration lost? */
204− ddata->retval = -EAGAIN;
205− complete(&ddata->done);
206− break;
207− case REG_STATE_STATE_WAIT:
208− /*
209− * huh, this shouldn't happen.
210− * Reset hardware state and get out
211− */
212− ddata->retval = -EIO;
213− efm32_i2c_write32(ddata, REG_CMD,
214− REG_CMD_STOP | REG_CMD_ABORT |
215− REG_CMD_CLEARTX | REG_CMD_CLEARPC);
216− complete(&ddata->done);
217− break;
218− case REG_STATE_STATE_START:
219− /* "caller" is expected to send an address */
220− break;
221− case REG_STATE_STATE_ADDR:
222− /* wait for Ack or NAck of slave */
223− break;
224− case REG_STATE_STATE_ADDRACK:
225− if (state & REG_STATE_NACKED) {
226− efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
227− ddata->retval = -ENXIO;
228− complete(&ddata->done);
229− } else if (cur_msg->flags & I2C_M_RD) {
230− /* wait for slave to send first data byte */
231− } else {
232− efm32_i2c_send_next_byte(ddata);
233− }
234− break;
235− case REG_STATE_STATE_DATA:
236− if (cur_msg->flags & I2C_M_RD) {
237− efm32_i2c_recv_next_byte(ddata);
238− } else {
239− /* wait for Ack or Nack of slave */
240− }
241− break;
242− case REG_STATE_STATE_DATAACK:
243− if (state & REG_STATE_NACKED) {
244− efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
245− complete(&ddata->done);
246− } else {
247− efm32_i2c_send_next_byte(ddata);
248− }
249− }
250−
251− return IRQ_HANDLED;
252−}
253−
254−static int efm32_i2c_master_xfer(struct i2c_adapter *adap,
255− struct i2c_msg *msgs, int num)
256−{
257− struct efm32_i2c_ddata *ddata = i2c_get_adapdata(adap);
258− int ret;
259−
260− if (ddata->msgs)
261− return -EBUSY;
262−
263− ddata->msgs = msgs;
264− ddata->num_msgs = num;
265− ddata->current_word = 0;
266− ddata->current_msg = 0;
267− ddata->retval = -EIO;
268−
269− reinit_completion(&ddata->done);
270−
271− dev_dbg(&ddata->adapter.dev, "state: %08x, status: %08x\n",
272− efm32_i2c_read32(ddata, REG_STATE),
273− efm32_i2c_read32(ddata, REG_STATUS));
274−
275− efm32_i2c_send_next_msg(ddata);
276−
277− wait_for_completion(&ddata->done);
278−
279− if (ddata->current_msg >= ddata->num_msgs)
280− ret = ddata->num_msgs;
281− else
282− ret = ddata->retval;
283−
284− return ret;
285−}
286−
287−static u32 efm32_i2c_functionality(struct i2c_adapter *adap)
288−{
289− return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
290−}
291−
292−static const struct i2c_algorithm efm32_i2c_algo = {
293− .master_xfer = efm32_i2c_master_xfer,
294− .functionality = efm32_i2c_functionality,
295−};
296−
297−static u32 efm32_i2c_get_configured_location(struct efm32_i2c_ddata *ddata)
298−{
299− u32 reg = efm32_i2c_read32(ddata, REG_ROUTE);
300−
301− return (reg & REG_ROUTE_LOCATION__MASK) >>
302− __ffs(REG_ROUTE_LOCATION__MASK);
303−}
304−
305−static int efm32_i2c_probe(struct platform_device *pdev)
306−{
307− struct efm32_i2c_ddata *ddata;
308− struct resource *res;
309− unsigned long rate;
310− struct device_node *np = pdev->dev.of_node;
311− u32 location, frequency;
312− int ret;
313− u32 clkdiv;
314−
315− ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
316− if (!ddata)
317− return -ENOMEM;
318− platform_set_drvdata(pdev, ddata);
319−
320− init_completion(&ddata->done);
321− strlcpy(ddata->adapter.name, pdev->name, sizeof(ddata->adapter.name));
322− ddata->adapter.owner = THIS_MODULE;
323− ddata->adapter.algo = &efm32_i2c_algo;
324− ddata->adapter.dev.parent = &pdev->dev;
325− ddata->adapter.dev.of_node = pdev->dev.of_node;
326− i2c_set_adapdata(&ddata->adapter, ddata);
327−
328− ddata->clk = devm_clk_get(&pdev->dev, NULL);
329− if (IS_ERR(ddata->clk)) {
330− ret = PTR_ERR(ddata->clk);
331− dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
332− return ret;
333− }
334−
335− ddata->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
336− if (IS_ERR(ddata->base))
337− return PTR_ERR(ddata->base);
338−
339− if (resource_size(res) < 0x42) {
340− dev_err(&pdev->dev, "memory resource too small\n");
341− return -EINVAL;
342− }
343−
344− ret = platform_get_irq(pdev, 0);
345− if (ret <= 0) {
346− if (!ret)
347− ret = -EINVAL;
348− return ret;
349− }
350−
351− ddata->irq = ret;
352−
353− ret = clk_prepare_enable(ddata->clk);
354− if (ret < 0) {
355− dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
356− return ret;
357− }
358−
359−
360− ret = of_property_read_u32(np, "energymicro,location", &location);
361−
362− if (ret)
363− /* fall back to wrongly namespaced property */
364− ret = of_property_read_u32(np, "efm32,location", &location);
365−
366− if (!ret) {
367− dev_dbg(&pdev->dev, "using location %u\n", location);
368− } else {
369− /* default to location configured in hardware */
370− location = efm32_i2c_get_configured_location(ddata);
371−
372− dev_info(&pdev->dev, "fall back to location %u\n", location);
373− }
374−
375− ddata->location = location;
376−
377− ret = of_property_read_u32(np, "clock-frequency", &frequency);
378− if (!ret) {
379− dev_dbg(&pdev->dev, "using frequency %u\n", frequency);
380− } else {
381− frequency = I2C_MAX_STANDARD_MODE_FREQ;
382− dev_info(&pdev->dev, "defaulting to 100 kHz\n");
383− }
384− ddata->frequency = frequency;
385−
386− rate = clk_get_rate(ddata->clk);
387− if (!rate) {
388− dev_err(&pdev->dev, "there is no input clock available\n");
389− ret = -EINVAL;
390− goto err_disable_clk;
391− }
392− clkdiv = DIV_ROUND_UP(rate, 8 * ddata->frequency) - 1;
393− if (clkdiv >= 0x200) {
394− dev_err(&pdev->dev,
395− "input clock too fast (%lu) to divide down to bus freq (%lu)",
396− rate, ddata->frequency);
397− ret = -EINVAL;
398− goto err_disable_clk;
399− }
400−
401− dev_dbg(&pdev->dev, "input clock = %lu, bus freq = %lu, clkdiv = %lu\n",
402− rate, ddata->frequency, (unsigned long)clkdiv);
403− efm32_i2c_write32(ddata, REG_CLKDIV, REG_CLKDIV_DIV(clkdiv));
404−
405− efm32_i2c_write32(ddata, REG_ROUTE, REG_ROUTE_SDAPEN |
406− REG_ROUTE_SCLPEN |
407− REG_ROUTE_LOCATION(ddata->location));
408−
409− efm32_i2c_write32(ddata, REG_CTRL, REG_CTRL_EN |
410− REG_CTRL_BITO_160PCC | 0 * REG_CTRL_GIBITO);
411−
412− efm32_i2c_write32(ddata, REG_IFC, REG_IFC__MASK);
413− efm32_i2c_write32(ddata, REG_IEN, REG_IF_TXC | REG_IF_ACK | REG_IF_NACK
414− | REG_IF_ARBLOST | REG_IF_BUSERR | REG_IF_RXDATAV);
415−
416− /* to make bus idle */
417− efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ABORT);
418−
419− ret = request_irq(ddata->irq, efm32_i2c_irq, 0, DRIVER_NAME, ddata);
420− if (ret < 0) {
421− dev_err(&pdev->dev, "failed to request irq (%d)\n", ret);
422− goto err_disable_clk;
423− }
424−
425− ret = i2c_add_adapter(&ddata->adapter);
426− if (ret) {
427− free_irq(ddata->irq, ddata);
428−
429−err_disable_clk:
430− clk_disable_unprepare(ddata->clk);
431− }
432− return ret;
433−}
434−
435−static int efm32_i2c_remove(struct platform_device *pdev)
436−{
437− struct efm32_i2c_ddata *ddata = platform_get_drvdata(pdev);
438−
439− i2c_del_adapter(&ddata->adapter);
440− free_irq(ddata->irq, ddata);
441− clk_disable_unprepare(ddata->clk);
442−
443− return 0;
444−}
445−
446−static const struct of_device_id efm32_i2c_dt_ids[] = {
447− {
448− .compatible = "energymicro,efm32-i2c",
449− }, {
450− /* sentinel */
451− }
452−};
453−MODULE_DEVICE_TABLE(of, efm32_i2c_dt_ids);
454−
455−static struct platform_driver efm32_i2c_driver = {
456− .probe = efm32_i2c_probe,
457− .remove = efm32_i2c_remove,
458−
459− .driver = {
460− .name = DRIVER_NAME,
461− .of_match_table = efm32_i2c_dt_ids,
462− },
463−};
464−module_platform_driver(efm32_i2c_driver);
465−
466−MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
467−MODULE_DESCRIPTION("EFM32 i2c driver");
468−MODULE_LICENSE("GPL v2");
469−MODULE_ALIAS("platform:" DRIVER_NAME);
drivers/i2c/busses/i2c-elektor.c+1−2
@@ -49,7 +49,7 @@ static int mmapped; · 48 unmodified lines
4949
5050 static wait_queue_head_t pcf_wait;
5151 static int pcf_pending;
52−static spinlock_t lock;
52+static DEFINE_SPINLOCK(lock);
5353
5454 static struct i2c_adapter pcf_isa_ops;
5555
@@ -132,7 +132,6 @@ static irqreturn_t pcf_isa_handler(int this_irq, void *dev_id) { · 76 unmodified lines
132132
133133 static int pcf_isa_init(void)
134134 {
135− spin_lock_init(&lock);
136135 if (!mmapped) {
137136 if (!request_region(base, 2, pcf_isa_ops.name)) {
138137 printk(KERN_ERR "%s: requested I/O region (%#x:2) is "
drivers/i2c/busses/i2c-gpio.c+1−1
@@ -520,5 +520,5 @@ module_exit(i2c_gpio_exit); · 519 unmodified lines
520520
521521 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
522522 MODULE_DESCRIPTION("Platform-independent bitbanging I2C driver");
523−MODULE_LICENSE("GPL");
523+MODULE_LICENSE("GPL v2");
524524 MODULE_ALIAS("platform:i2c-gpio");
drivers/i2c/busses/i2c-hix5hd2.c+1−3
@@ -413,10 +413,8 @@ static int hix5hd2_i2c_probe(struct platform_device *pdev) · 412 unmodified lines
413413 return PTR_ERR(priv->regs);
414414
415415 irq = platform_get_irq(pdev, 0);
416− if (irq <= 0) {
417− dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
416+ if (irq <= 0)
418417 return irq;
419− }
420418
421419 priv->clk = devm_clk_get(&pdev->dev, NULL);
422420 if (IS_ERR(priv->clk)) {
drivers/i2c/busses/i2c-i801.c+8−9
@@ -72,6 +72,7 @@ · 71 unmodified lines
7272 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
7373 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
7474 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
75+ * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
7576 *
7677 * Features supported by this driver:
7778 * Software PEC no
@@ -228,6 +229,7 @@ · 150 unmodified lines
228229 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
229230 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
230231 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
232+#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
231233 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
232234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
233235 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
@@ -1084,6 +1086,7 @@ static const struct pci_device_id i801_ids[] = { · 850 unmodified lines
10841086 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
10851087 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
10861088 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
1089+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) },
10871090 { 0, }
10881091 };
10891092
@@ -1433,7 +1436,7 @@ static int i801_add_mux(struct i801_priv *priv) · 343 unmodified lines
14331436 const struct i801_mux_config *mux_config;
14341437 struct i2c_mux_gpio_platform_data gpio_data;
14351438 struct gpiod_lookup_table *lookup;
1436− int err, i;
1439+ int i;
14371440
14381441 if (!priv->mux_drvdata)
14391442 return 0;
@@ -1473,22 +1476,17 @@ static int i801_add_mux(struct i801_priv *priv) · 33 unmodified lines
14731476 PLATFORM_DEVID_NONE, &gpio_data,
14741477 sizeof(struct i2c_mux_gpio_platform_data));
14751478 if (IS_ERR(priv->mux_pdev)) {
1476− err = PTR_ERR(priv->mux_pdev);
14771479 gpiod_remove_lookup_table(lookup);
1478− priv->mux_pdev = NULL;
14791480 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1480− return err;
14811481 }
14821482
1483− return 0;
1483+ return PTR_ERR_OR_ZERO(priv->mux_pdev);
14841484 }
14851485
14861486 static void i801_del_mux(struct i801_priv *priv)
14871487 {
1488− if (priv->mux_pdev)
1489− platform_device_unregister(priv->mux_pdev);
1490− if (priv->lookup)
1491− gpiod_remove_lookup_table(priv->lookup);
1488+ platform_device_unregister(priv->mux_pdev);
1489+ gpiod_remove_lookup_table(priv->lookup);
14921490 }
14931491
14941492 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
@@ -1772,6 +1770,7 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) · 277 unmodified lines
17721770 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
17731771 case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
17741772 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
1773+ case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS:
17751774 priv->features |= FEATURE_BLOCK_PROC;
17761775 priv->features |= FEATURE_I2C_BLOCK_READ;
17771776 priv->features |= FEATURE_IRQ;
drivers/i2c/busses/i2c-imx.c+55−10
@@ -209,6 +209,7 @@ struct imx_i2c_struct { · 208 unmodified lines
209209
210210 struct imx_i2c_dma *dma;
211211 struct i2c_client *slave;
212+ enum i2c_slave_event last_slave_event;
212213 };
213214
214215 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
@@ -550,7 +551,7 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, · 335 unmodified lines
550551
551552 i2c_imx->cur_clk = i2c_clk_rate;
552553
553− div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
554+ div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);
554555 if (div < i2c_clk_div[0].div)
555556 i = 0;
556557 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
@@ -568,8 +569,8 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, · 11 unmodified lines
568569 * This delay is used in I2C bus disable function
569570 * to fix chip hardware bug.
570571 */
571− i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
572− + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
572+ i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,
573+ i2c_clk_rate / 2);
573574
574575 #ifdef CONFIG_I2C_DEBUG_BUS
575576 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
@@ -675,6 +676,36 @@ static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) · 99 unmodified lines
675676 }
676677 }
677678
679+static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx,
680+ enum i2c_slave_event event, u8 *val)
681+{
682+ i2c_slave_event(i2c_imx->slave, event, val);
683+ i2c_imx->last_slave_event = event;
684+}
685+
686+static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx)
687+{
688+ u8 val;
689+
690+ while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {
691+ switch (i2c_imx->last_slave_event) {
692+ case I2C_SLAVE_READ_REQUESTED:
693+ i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED,
694+ &val);
695+ break;
696+
697+ case I2C_SLAVE_WRITE_REQUESTED:
698+ case I2C_SLAVE_READ_PROCESSED:
699+ case I2C_SLAVE_WRITE_RECEIVED:
700+ i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val);
701+ break;
702+
703+ case I2C_SLAVE_STOP:
704+ break;
705+ }
706+ }
707+}
708+
678709 static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx,
679710 unsigned int status, unsigned int ctl)
680711 {
@@ -687,9 +718,11 @@ static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, · 6 unmodified lines
687718 }
688719
689720 if (status & I2SR_IAAS) { /* Addressed as a slave */
721+ i2c_imx_slave_finish_op(i2c_imx);
690722 if (status & I2SR_SRW) { /* Master wants to read from us*/
691723 dev_dbg(&i2c_imx->adapter.dev, "read requested");
692− i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value);
724+ i2c_imx_slave_event(i2c_imx,
725+ I2C_SLAVE_READ_REQUESTED, &value);
693726
694727 /* Slave transmit */
695728 ctl |= I2CR_MTX;
@@ -699,7 +732,8 @@ static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, · 3 unmodified lines
699732 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
700733 } else { /* Master wants to write to us */
701734 dev_dbg(&i2c_imx->adapter.dev, "write requested");
702− i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
735+ i2c_imx_slave_event(i2c_imx,
736+ I2C_SLAVE_WRITE_REQUESTED, &value);
703737
704738 /* Slave receive */
705739 ctl &= ~I2CR_MTX;
@@ -710,17 +744,20 @@ static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, · 4 unmodified lines
710744 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */
711745 if (status & I2SR_IBB) { /* No STOP signal detected */
712746 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
713− i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
747+ i2c_imx_slave_event(i2c_imx,
748+ I2C_SLAVE_WRITE_RECEIVED, &value);
714749 } else { /* STOP signal is detected */
715750 dev_dbg(&i2c_imx->adapter.dev,
716751 "STOP signal detected");
717− i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value);
752+ i2c_imx_slave_event(i2c_imx,
753+ I2C_SLAVE_STOP, &value);
718754 }
719755 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
720756 ctl |= I2CR_MTX;
721757 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
722758
723− i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value);
759+ i2c_imx_slave_event(i2c_imx,
760+ I2C_SLAVE_READ_PROCESSED, &value);
724761
725762 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
726763 } else { /* Transmit mode received NAK */
@@ -761,6 +798,7 @@ static int i2c_imx_reg_slave(struct i2c_client *client) · 34 unmodified lines
761798 return -EBUSY;
762799
763800 i2c_imx->slave = client;
801+ i2c_imx->last_slave_event = I2C_SLAVE_STOP;
764802
765803 /* Resume */
766804 ret = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
@@ -813,10 +851,17 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id) · 46 unmodified lines
813851
814852 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
815853 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
854+
816855 if (status & I2SR_IIF) {
817856 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
818− if (i2c_imx->slave && !(ctl & I2CR_MSTA))
819− return i2c_imx_slave_isr(i2c_imx, status, ctl);
857+ if (i2c_imx->slave) {
858+ if (!(ctl & I2CR_MSTA)) {
859+ return i2c_imx_slave_isr(i2c_imx, status, ctl);
860+ } else if (i2c_imx->last_slave_event !=
861+ I2C_SLAVE_STOP) {
862+ i2c_imx_slave_finish_op(i2c_imx);
863+ }
864+ }
820865 return i2c_imx_master_isr(i2c_imx, status);
821866 }
822867
drivers/i2c/busses/i2c-jz4780.c+2−3
@@ -437,9 +437,8 @@ static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id) · 436 unmodified lines
437437 unsigned short intst;
438438 unsigned short intmsk;
439439 struct jz4780_i2c *i2c = dev_id;
440− unsigned long flags;
441440
442− spin_lock_irqsave(&i2c->lock, flags);
441+ spin_lock(&i2c->lock);
443442 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
444443 intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST);
445444
@@ -551,7 +550,7 @@ static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id) · 105 unmodified lines
551550 }
552551
553552 done:
554− spin_unlock_irqrestore(&i2c->lock, flags);
553+ spin_unlock(&i2c->lock);
555554 return IRQ_HANDLED;
556555 }
557556
drivers/i2c/busses/i2c-mlxcpld.c+66−31
@@ -1,34 +1,8 @@
1+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
12 /*
2− * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
3− * Copyright (c) 2016 Michael Shych <michaels@mellanox.com>
3+ * Mellanox i2c driver
44 *
5− * Redistribution and use in source and binary forms, with or without
6− * modification, are permitted provided that the following conditions are met:
7− *
8− * 1. Redistributions of source code must retain the above copyright
9− * notice, this list of conditions and the following disclaimer.
10− * 2. Redistributions in binary form must reproduce the above copyright
11− * notice, this list of conditions and the following disclaimer in the
12− * documentation and/or other materials provided with the distribution.
13− * 3. Neither the names of the copyright holders nor the names of its
14− * contributors may be used to endorse or promote products derived from
15− * this software without specific prior written permission.
16− *
17− * Alternatively, this software may be distributed under the terms of the
18− * GNU General Public License ("GPL") version 2 as published by the Free
19− * Software Foundation.
20− *
21− * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22− * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23− * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24− * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25− * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26− * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27− * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28− * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29− * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30− * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31− * POSSIBILITY OF SUCH DAMAGE.
5+ * Copyright (C) 2016-2020 Mellanox Technologies
326 */
337
348 #include <linux/delay.h>
@@ -37,7 +11,9 @@ · 2 unmodified lines
3711 #include <linux/io.h>
3812 #include <linux/kernel.h>
3913 #include <linux/module.h>
14+#include <linux/platform_data/mlxreg.h>
4015 #include <linux/platform_device.h>
16+#include <linux/regmap.h>
4117
4218 /* General defines */
4319 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR 0x2000
@@ -51,7 +27,7 @@ · 7 unmodified lines
5127 #define MLXCPLD_I2C_MAX_ADDR_LEN 4
5228 #define MLXCPLD_I2C_RETR_NUM 2
5329 #define MLXCPLD_I2C_XFER_TO 500000 /* usec */
54−#define MLXCPLD_I2C_POLL_TIME 2000 /* usec */
30+#define MLXCPLD_I2C_POLL_TIME 400 /* usec */
5531
5632 /* LPC I2C registers */
5733 #define MLXCPLD_LPCI2C_CPBLTY_REG 0x0
@@ -72,6 +48,16 @@ · 14 unmodified lines
7248 #define MLXCPLD_LPCI2C_ACK_IND 1
7349 #define MLXCPLD_LPCI2C_NACK_IND 2
7450
51+#define MLXCPLD_I2C_FREQ_1000KHZ_SET 0x04
52+#define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0f
53+#define MLXCPLD_I2C_FREQ_100KHZ_SET 0x42
54+
55+enum mlxcpld_i2c_frequency {
56+ MLXCPLD_I2C_FREQ_1000KHZ = 1,
57+ MLXCPLD_I2C_FREQ_400KHZ = 2,
58+ MLXCPLD_I2C_FREQ_100KHZ = 3,
59+};
60+
7561 struct mlxcpld_i2c_curr_xfer {
7662 u8 cmd;
7763 u8 addr_width;
@@ -489,8 +475,45 @@ static struct i2c_adapter mlxcpld_i2c_adapter = { · 411 unmodified lines
489475 .nr = MLXCPLD_I2C_BUS_NUM,
490476 };
491477
478+static int
479+mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv *priv,
480+ struct mlxreg_core_hotplug_platform_data *pdata)
481+{
482+ struct mlxreg_core_item *item = pdata->items;
483+ struct mlxreg_core_data *data;
484+ u32 regval;
485+ u8 freq;
486+ int err;
487+
488+ if (!item)
489+ return 0;
490+
491+ /* Read frequency setting. */
492+ data = item->data;
493+ err = regmap_read(pdata->regmap, data->reg, &regval);
494+ if (err)
495+ return err;
496+
497+ /* Set frequency only if it is not 100KHz, which is default. */
498+ switch ((data->reg & data->mask) >> data->bit) {
499+ case MLXCPLD_I2C_FREQ_1000KHZ:
500+ freq = MLXCPLD_I2C_FREQ_1000KHZ_SET;
501+ break;
502+ case MLXCPLD_I2C_FREQ_400KHZ:
503+ freq = MLXCPLD_I2C_FREQ_400KHZ_SET;
504+ break;
505+ default:
506+ return 0;
507+ }
508+
509+ mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_HALF_CYC_REG, &freq, 1);
510+
511+ return 0;
512+}
513+
492514 static int mlxcpld_i2c_probe(struct platform_device *pdev)
493515 {
516+ struct mlxreg_core_hotplug_platform_data *pdata;
494517 struct mlxcpld_i2c_priv *priv;
495518 int err;
496519 u8 val;
@@ -505,6 +528,14 @@ static int mlxcpld_i2c_probe(struct platform_device *pdev) · 8 unmodified lines
505528 priv->dev = &pdev->dev;
506529 priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR;
507530
531+ /* Set I2C bus frequency if platform data provides this info. */
532+ pdata = dev_get_platdata(&pdev->dev);
533+ if (pdata) {
534+ err = mlxcpld_i2c_set_frequency(priv, pdata);
535+ if (err)
536+ goto mlxcpld_i2_probe_failed;
537+ }
538+
508539 /* Register with i2c layer */
509540 mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO);
510541 /* Read capability register */
@@ -523,8 +554,12 @@ static int mlxcpld_i2c_probe(struct platform_device *pdev) · 12 unmodified lines
523554
524555 err = i2c_add_numbered_adapter(&priv->adap);
525556 if (err)
526− mutex_destroy(&priv->lock);
557+ goto mlxcpld_i2_probe_failed;
527558
559+ return 0;
560+
561+mlxcpld_i2_probe_failed:
562+ mutex_destroy(&priv->lock);
528563 return err;
529564 }
530565
drivers/i2c/busses/i2c-mv64xxx.c+79−43
@@ -18,6 +18,7 @@ · 17 unmodified lines
1818 #include <linux/mv643xx_i2c.h>
1919 #include <linux/platform_device.h>
2020 #include <linux/pinctrl/consumer.h>
21+#include <linux/pm_runtime.h>
2122 #include <linux/reset.h>
2223 #include <linux/io.h>
2324 #include <linux/of.h>
@@ -717,6 +718,10 @@ mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) · 693 unmodified lines
717718 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
718719 int rc, ret = num;
719720
721+ rc = pm_runtime_resume_and_get(&adap->dev);
722+ if (rc)
723+ return rc;
724+
720725 BUG_ON(drv_data->msgs != NULL);
721726 drv_data->msgs = msgs;
722727 drv_data->num_msgs = num;
@@ -732,6 +737,9 @@ mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) · 9 unmodified lines
732737 drv_data->num_msgs = 0;
733738 drv_data->msgs = NULL;
734739
740+ pm_runtime_mark_last_busy(&adap->dev);
741+ pm_runtime_put_autosuspend(&adap->dev);
742+
735743 return ret;
736744 }
737745
@@ -805,7 +813,7 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, · 67 unmodified lines
805813 * need to know tclk in order to calculate bus clock
806814 * factors.
807815 */
808− if (IS_ERR(drv_data->clk)) {
816+ if (!drv_data->clk) {
809817 rc = -ENODEV;
810818 goto out;
811819 }
@@ -828,7 +836,6 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, · 16 unmodified lines
828836 rc = PTR_ERR(drv_data->rstc);
829837 goto out;
830838 }
831− reset_control_deassert(drv_data->rstc);
832839
833840 /* Its not yet defined how timeouts will be specified in device tree.
834841 * So hard code the value to 1 second.
@@ -893,6 +900,32 @@ static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data, · 58 unmodified lines
893900 return 0;
894901 }
895902
903+static int
904+mv64xxx_i2c_runtime_suspend(struct device *dev)
905+{
906+ struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
907+
908+ reset_control_assert(drv_data->rstc);
909+ clk_disable_unprepare(drv_data->reg_clk);
910+ clk_disable_unprepare(drv_data->clk);
911+
912+ return 0;
913+}
914+
915+static int
916+mv64xxx_i2c_runtime_resume(struct device *dev)
917+{
918+ struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
919+
920+ clk_prepare_enable(drv_data->clk);
921+ clk_prepare_enable(drv_data->reg_clk);
922+ reset_control_reset(drv_data->rstc);
923+
924+ mv64xxx_i2c_hw_init(drv_data);
925+
926+ return 0;
927+}
928+
896929 static int
897930 mv64xxx_i2c_probe(struct platform_device *pd)
898931 {
@@ -920,18 +953,22 @@ mv64xxx_i2c_probe(struct platform_device *pd) · 21 unmodified lines
920953
921954 /* Not all platforms have clocks */
922955 drv_data->clk = devm_clk_get(&pd->dev, NULL);
923− if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
924− return -EPROBE_DEFER;
925− if (!IS_ERR(drv_data->clk))
926− clk_prepare_enable(drv_data->clk);
956+ if (IS_ERR(drv_data->clk)) {
957+ if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
958+ return -EPROBE_DEFER;
959+ drv_data->clk = NULL;
960+ }
927961
928962 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
929− if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
930− return -EPROBE_DEFER;
931− if (!IS_ERR(drv_data->reg_clk))
932− clk_prepare_enable(drv_data->reg_clk);
963+ if (IS_ERR(drv_data->reg_clk)) {
964+ if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
965+ return -EPROBE_DEFER;
966+ drv_data->reg_clk = NULL;
967+ }
933968
934969 drv_data->irq = platform_get_irq(pd, 0);
970+ if (drv_data->irq < 0)
971+ return drv_data->irq;
935972
936973 if (pdata) {
937974 drv_data->freq_m = pdata->freq_m;
@@ -942,16 +979,12 @@ mv64xxx_i2c_probe(struct platform_device *pd) · 4 unmodified lines
942979 } else if (pd->dev.of_node) {
943980 rc = mv64xxx_of_config(drv_data, &pd->dev);
944981 if (rc)
945− goto exit_clk;
946− }
947− if (drv_data->irq < 0) {
948− rc = drv_data->irq;
949− goto exit_reset;
982+ return rc;
950983 }
951984
952985 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
953986 if (rc == -EPROBE_DEFER)
954− goto exit_reset;
987+ return rc;
955988
956989 drv_data->adapter.dev.parent = &pd->dev;
957990 drv_data->adapter.algo = &mv64xxx_i2c_algo;
@@ -962,7 +995,14 @@ mv64xxx_i2c_probe(struct platform_device *pd) · 4 unmodified lines
962995 platform_set_drvdata(pd, drv_data);
963996 i2c_set_adapdata(&drv_data->adapter, drv_data);
964997
965− mv64xxx_i2c_hw_init(drv_data);
998+ pm_runtime_set_autosuspend_delay(&pd->dev, MSEC_PER_SEC);
999+ pm_runtime_use_autosuspend(&pd->dev);
1000+ pm_runtime_enable(&pd->dev);
1001+ if (!pm_runtime_enabled(&pd->dev)) {
1002+ rc = mv64xxx_i2c_runtime_resume(&pd->dev);
1003+ if (rc)
1004+ goto exit_disable_pm;
1005+ }
9661006
9671007 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
9681008 MV64XXX_I2C_CTLR_NAME, drv_data);
@@ -970,7 +1010,7 @@ mv64xxx_i2c_probe(struct platform_device *pd) · 1 unmodified line
9701010 dev_err(&drv_data->adapter.dev,
9711011 "mv64xxx: Can't register intr handler irq%d: %d\n",
9721012 drv_data->irq, rc);
973− goto exit_reset;
1013+ goto exit_disable_pm;
9741014 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
9751015 dev_err(&drv_data->adapter.dev,
9761016 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
@@ -981,54 +1021,50 @@ mv64xxx_i2c_probe(struct platform_device *pd) · 4 unmodified lines
9811021
9821022 exit_free_irq:
9831023 free_irq(drv_data->irq, drv_data);
984−exit_reset:
985− reset_control_assert(drv_data->rstc);
986−exit_clk:
987− clk_disable_unprepare(drv_data->reg_clk);
988− clk_disable_unprepare(drv_data->clk);
1024+exit_disable_pm:
1025+ pm_runtime_disable(&pd->dev);
1026+ if (!pm_runtime_status_suspended(&pd->dev))
1027+ mv64xxx_i2c_runtime_suspend(&pd->dev);
9891028
9901029 return rc;
9911030 }
9921031
9931032 static int
994−mv64xxx_i2c_remove(struct platform_device *dev)
1033+mv64xxx_i2c_remove(struct platform_device *pd)
9951034 {
996− struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
1035+ struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pd);
9971036
9981037 i2c_del_adapter(&drv_data->adapter);
9991038 free_irq(drv_data->irq, drv_data);
1000− reset_control_assert(drv_data->rstc);
1001− clk_disable_unprepare(drv_data->reg_clk);
1002− clk_disable_unprepare(drv_data->clk);
1039+ pm_runtime_disable(&pd->dev);
1040+ if (!pm_runtime_status_suspended(&pd->dev))
1041+ mv64xxx_i2c_runtime_suspend(&pd->dev);
10031042
10041043 return 0;
10051044 }
10061045
1007−#ifdef CONFIG_PM
1008−static int mv64xxx_i2c_resume(struct device *dev)
1046+static void
1047+mv64xxx_i2c_shutdown(struct platform_device *pd)
10091048 {
1010− struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
1011−
1012− mv64xxx_i2c_hw_init(drv_data);
1013−
1014− return 0;
1049+ pm_runtime_disable(&pd->dev);
1050+ if (!pm_runtime_status_suspended(&pd->dev))
1051+ mv64xxx_i2c_runtime_suspend(&pd->dev);
10151052 }
10161053
1017−static const struct dev_pm_ops mv64xxx_i2c_pm = {
1018− .resume = mv64xxx_i2c_resume,
1054+static const struct dev_pm_ops mv64xxx_i2c_pm_ops = {
1055+ SET_RUNTIME_PM_OPS(mv64xxx_i2c_runtime_suspend,
1056+ mv64xxx_i2c_runtime_resume, NULL)
1057+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1058+ pm_runtime_force_resume)
10191059 };
10201060
1021−#define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm)
1022−#else
1023−#define mv64xxx_i2c_pm_ops NULL
1024−#endif
1025−
10261061 static struct platform_driver mv64xxx_i2c_driver = {
10271062 .probe = mv64xxx_i2c_probe,
10281063 .remove = mv64xxx_i2c_remove,
1064+ .shutdown = mv64xxx_i2c_shutdown,
10291065 .driver = {
10301066 .name = MV64XXX_I2C_CTLR_NAME,
1031− .pm = mv64xxx_i2c_pm_ops,
1067+ .pm = &mv64xxx_i2c_pm_ops,
10321068 .of_match_table = mv64xxx_i2c_of_match_table,
10331069 },
10341070 };
drivers/i2c/busses/i2c-qcom-geni.c+77−16
@@ -86,6 +86,9 @@ struct geni_i2c_dev { · 85 unmodified lines
8686 u32 clk_freq_out;
8787 const struct geni_i2c_clk_fld *clk_fld;
8888 int suspended;
89+ void *dma_buf;
90+ size_t xfer_len;
91+ dma_addr_t dma_addr;
8992 };
9093
9194 struct geni_i2c_err_log {
@@ -348,14 +351,65 @@ static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) · 256 unmodified lines
348351 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
349352 }
350353
354+static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
355+ struct i2c_msg *cur)
356+{
357+ gi2c->cur_rd = 0;
358+ if (gi2c->dma_buf) {
359+ if (gi2c->err)
360+ geni_i2c_rx_fsm_rst(gi2c);
361+ geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
362+ i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
363+ }
364+}
365+
366+static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
367+ struct i2c_msg *cur)
368+{
369+ gi2c->cur_wr = 0;
370+ if (gi2c->dma_buf) {
371+ if (gi2c->err)
372+ geni_i2c_tx_fsm_rst(gi2c);
373+ geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
374+ i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
375+ }
376+}
377+
378+static void geni_i2c_stop_xfer(struct geni_i2c_dev *gi2c)
379+{
380+ int ret;
381+ u32 geni_status;
382+ struct i2c_msg *cur;
383+
384+ /* Resume device, as runtime suspend can happen anytime during transfer */
385+ ret = pm_runtime_get_sync(gi2c->se.dev);
386+ if (ret < 0) {
387+ dev_err(gi2c->se.dev, "Failed to resume device: %d\n", ret);
388+ return;
389+ }
390+
391+ geni_status = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
392+ if (geni_status & M_GENI_CMD_ACTIVE) {
393+ cur = gi2c->cur;
394+ geni_i2c_abort_xfer(gi2c);
395+ if (cur->flags & I2C_M_RD)
396+ geni_i2c_rx_msg_cleanup(gi2c, cur);
397+ else
398+ geni_i2c_tx_msg_cleanup(gi2c, cur);
399+ }
400+
401+ pm_runtime_put_sync_suspend(gi2c->se.dev);
402+}
403+
351404 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
352405 u32 m_param)
353406 {
354− dma_addr_t rx_dma;
407+ dma_addr_t rx_dma = 0;
355408 unsigned long time_left;
356409 void *dma_buf;
357410 struct geni_se *se = &gi2c->se;
358411 size_t len = msg->len;
412+ struct i2c_msg *cur;
359413
360414 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
361415 if (dma_buf)
@@ -370,19 +424,18 @@ static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, · 8 unmodified lines
370424 geni_se_select_mode(se, GENI_SE_FIFO);
371425 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
372426 dma_buf = NULL;
427+ } else {
428+ gi2c->xfer_len = len;
429+ gi2c->dma_addr = rx_dma;
430+ gi2c->dma_buf = dma_buf;
373431 }
374432
433+ cur = gi2c->cur;
375434 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
376435 if (!time_left)
377436 geni_i2c_abort_xfer(gi2c);
378437
379− gi2c->cur_rd = 0;
380− if (dma_buf) {
381− if (gi2c->err)
382− geni_i2c_rx_fsm_rst(gi2c);
383− geni_se_rx_dma_unprep(se, rx_dma, len);
384− i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
385− }
438+ geni_i2c_rx_msg_cleanup(gi2c, cur);
386439
387440 return gi2c->err;
388441 }
@@ -390,11 +443,12 @@ static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, · 1 unmodified line
390443 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
391444 u32 m_param)
392445 {
393− dma_addr_t tx_dma;
446+ dma_addr_t tx_dma = 0;
394447 unsigned long time_left;
395448 void *dma_buf;
396449 struct geni_se *se = &gi2c->se;
397450 size_t len = msg->len;
451+ struct i2c_msg *cur;
398452
399453 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
400454 if (dma_buf)
@@ -409,22 +463,21 @@ static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, · 8 unmodified lines
409463 geni_se_select_mode(se, GENI_SE_FIFO);
410464 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
411465 dma_buf = NULL;
466+ } else {
467+ gi2c->xfer_len = len;
468+ gi2c->dma_addr = tx_dma;
469+ gi2c->dma_buf = dma_buf;
412470 }
413471
414472 if (!dma_buf) /* Get FIFO IRQ */
415473 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
416474
475+ cur = gi2c->cur;
417476 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
418477 if (!time_left)
419478 geni_i2c_abort_xfer(gi2c);
420479
421− gi2c->cur_wr = 0;
422− if (dma_buf) {
423− if (gi2c->err)
424− geni_i2c_tx_fsm_rst(gi2c);
425− geni_se_tx_dma_unprep(se, tx_dma, len);
426− i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
427− }
480+ geni_i2c_tx_msg_cleanup(gi2c, cur);
428481
429482 return gi2c->err;
430483 }
@@ -623,6 +676,13 @@ static int geni_i2c_remove(struct platform_device *pdev) · 192 unmodified lines
623676 return 0;
624677 }
625678
679+static void geni_i2c_shutdown(struct platform_device *pdev)
680+{
681+ struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
682+
683+ geni_i2c_stop_xfer(gi2c);
684+}
685+
626686 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
627687 {
628688 int ret;
@@ -687,6 +747,7 @@ MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); · 58 unmodified lines
687747 static struct platform_driver geni_i2c_driver = {
688748 .probe = geni_i2c_probe,
689749 .remove = geni_i2c_remove,
750+ .shutdown = geni_i2c_shutdown,
690751 .driver = {
691752 .name = "geni_i2c",
692753 .pm = &geni_i2c_pm_ops,
drivers/i2c/busses/i2c-qup.c+1−1
@@ -1603,7 +1603,7 @@ out: · 1602 unmodified lines
16031603
16041604 static u32 qup_i2c_func(struct i2c_adapter *adap)
16051605 {
1606− return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1606+ return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
16071607 }
16081608
16091609 static const struct i2c_algorithm qup_i2c_algo = {
drivers/i2c/busses/i2c-rcar.c+48−18
@@ -91,7 +91,6 @@ · 90 unmodified lines
9191
9292 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
9393 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
94−#define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
9594 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
9695
9796 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
@@ -120,6 +119,7 @@ enum rcar_i2c_type { · 22 unmodified lines
120119 };
121120
122121 struct rcar_i2c_priv {
122+ u32 flags;
123123 void __iomem *io;
124124 struct i2c_adapter adap;
125125 struct i2c_msg *msg;
@@ -130,7 +130,6 @@ struct rcar_i2c_priv { · 4 unmodified lines
130130
131131 int pos;
132132 u32 icccr;
133− u32 flags;
134133 u8 recovery_icmcr; /* protected by adapter lock */
135134 enum rcar_i2c_type devtype;
136135 struct i2c_client *slave;
@@ -621,27 +620,16 @@ static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) · 484 unmodified lines
621620 /*
622621 * This driver has a lock-free design because there are IP cores (at least
623622 * R-Car Gen2) which have an inherent race condition in their hardware design.
624− * There, we need to clear RCAR_BUS_MASK_DATA bits as soon as possible after
623+ * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after
625624 * the interrupt was generated, otherwise an unwanted repeated message gets
626625 * generated. It turned out that taking a spinlock at the beginning of the ISR
627626 * was already causing repeated messages. Thus, this driver was converted to
628627 * the now lockless behaviour. Please keep this in mind when hacking the driver.
628+ * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are
629+ * likely affected. Therefore, we have different interrupt handler entries.
629630 */
630−static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
631+static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr)
631632 {
632− struct rcar_i2c_priv *priv = ptr;
633− u32 msr, val;
634−
635− /* Clear START or STOP immediately, except for REPSTART after read */
636− if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) {
637− val = rcar_i2c_read(priv, ICMCR);
638− rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
639− }
640−
641− msr = rcar_i2c_read(priv, ICMSR);
642−
643− /* Only handle interrupts that are currently enabled */
644− msr &= rcar_i2c_read(priv, ICMIER);
645633 if (!msr) {
646634 if (rcar_i2c_slave_irq(priv))
647635 return IRQ_HANDLED;
@@ -685,6 +673,41 @@ out: · 37 unmodified lines
685673 return IRQ_HANDLED;
686674 }
687675
676+static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr)
677+{
678+ struct rcar_i2c_priv *priv = ptr;
679+ u32 msr;
680+
681+ /* Clear START or STOP immediately, except for REPSTART after read */
682+ if (likely(!(priv->flags & ID_P_REP_AFTER_RD)))
683+ rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
684+
685+ /* Only handle interrupts that are currently enabled */
686+ msr = rcar_i2c_read(priv, ICMSR);
687+ msr &= rcar_i2c_read(priv, ICMIER);
688+
689+ return rcar_i2c_irq(irq, priv, msr);
690+}
691+
692+static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr)
693+{
694+ struct rcar_i2c_priv *priv = ptr;
695+ u32 msr;
696+
697+ /* Only handle interrupts that are currently enabled */
698+ msr = rcar_i2c_read(priv, ICMSR);
699+ msr &= rcar_i2c_read(priv, ICMIER);
700+
701+ /*
702+ * Clear START or STOP immediately, except for REPSTART after read or
703+ * if a spurious interrupt was detected.
704+ */
705+ if (likely(!(priv->flags & ID_P_REP_AFTER_RD) && msr))
706+ rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
707+
708+ return rcar_i2c_irq(irq, priv, msr);
709+}
710+
688711 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
689712 enum dma_transfer_direction dir,
690713 dma_addr_t port_addr)
@@ -931,6 +954,8 @@ static int rcar_i2c_probe(struct platform_device *pdev) · 240 unmodified lines
931954 struct rcar_i2c_priv *priv;
932955 struct i2c_adapter *adap;
933956 struct device *dev = &pdev->dev;
957+ unsigned long irqflags = 0;
958+ irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq;
934959 int ret;
935960
936961 /* Otherwise logic will break because some bytes must always use PIO */
@@ -979,6 +1004,11 @@ static int rcar_i2c_probe(struct platform_device *pdev) · 42 unmodified lines
9791004
9801005 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
9811006
1007+ if (priv->devtype < I2C_RCAR_GEN3) {
1008+ irqflags |= IRQF_NO_THREAD;
1009+ irqhandler = rcar_i2c_gen2_irq;
1010+ }
1011+
9821012 if (priv->devtype == I2C_RCAR_GEN3) {
9831013 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
9841014 if (!IS_ERR(priv->rstc)) {
@@ -998,7 +1028,7 @@ static int rcar_i2c_probe(struct platform_device *pdev) · 13 unmodified lines
9981028 priv->flags |= ID_P_HOST_NOTIFY;
9991029
10001030 priv->irq = platform_get_irq(pdev, 0);
1001− ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv);
1031+ ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv);
10021032 if (ret < 0) {
10031033 dev_err(dev, "cannot get irq %d\n", priv->irq);
10041034 goto out_pm_disable;
drivers/i2c/busses/i2c-s3c2410.c+1−1
@@ -781,7 +781,7 @@ static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, · 780 unmodified lines
781781 /* declare our i2c functionality */
782782 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
783783 {
784− return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
784+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART |
785785 I2C_FUNC_PROTOCOL_MANGLING;
786786 }
787787
drivers/i2c/busses/i2c-sirf.c+0−475
@@ -1,475 +0,0 @@
1−// SPDX-License-Identifier: GPL-2.0-or-later
2−/*
3− * I2C bus driver for CSR SiRFprimaII
4− *
5− * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6− */
7−
8−#include <linux/interrupt.h>
9−#include <linux/kernel.h>
10−#include <linux/module.h>
11−#include <linux/slab.h>
12−#include <linux/platform_device.h>
13−#include <linux/i2c.h>
14−#include <linux/clk.h>
15−#include <linux/err.h>
16−#include <linux/io.h>
17−
18−#define SIRFSOC_I2C_CLK_CTRL 0x00
19−#define SIRFSOC_I2C_STATUS 0x0C
20−#define SIRFSOC_I2C_CTRL 0x10
21−#define SIRFSOC_I2C_IO_CTRL 0x14
22−#define SIRFSOC_I2C_SDA_DELAY 0x18
23−#define SIRFSOC_I2C_CMD_START 0x1C
24−#define SIRFSOC_I2C_CMD_BUF 0x30
25−#define SIRFSOC_I2C_DATA_BUF 0x80
26−
27−#define SIRFSOC_I2C_CMD_BUF_MAX 16
28−#define SIRFSOC_I2C_DATA_BUF_MAX 16
29−
30−#define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
31−#define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8))
32−#define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8)
33−
34−#define SIRFSOC_I2C_DIV_MASK (0xFFFF)
35−
36−/* I2C status flags */
37−#define SIRFSOC_I2C_STAT_BUSY BIT(0)
38−#define SIRFSOC_I2C_STAT_TIP BIT(1)
39−#define SIRFSOC_I2C_STAT_NACK BIT(2)
40−#define SIRFSOC_I2C_STAT_TR_INT BIT(4)
41−#define SIRFSOC_I2C_STAT_STOP BIT(6)
42−#define SIRFSOC_I2C_STAT_CMD_DONE BIT(8)
43−#define SIRFSOC_I2C_STAT_ERR BIT(9)
44−#define SIRFSOC_I2C_CMD_INDEX (0x1F<<16)
45−
46−/* I2C control flags */
47−#define SIRFSOC_I2C_RESET BIT(0)
48−#define SIRFSOC_I2C_CORE_EN BIT(1)
49−#define SIRFSOC_I2C_MASTER_MODE BIT(2)
50−#define SIRFSOC_I2C_CMD_DONE_EN BIT(11)
51−#define SIRFSOC_I2C_ERR_INT_EN BIT(12)
52−
53−#define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF)
54−#define SIRFSOC_I2C_SCLF_FILTER (3<<8)
55−
56−#define SIRFSOC_I2C_START_CMD BIT(0)
57−
58−#define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7)
59−#define SIRFSOC_I2C_NACK BIT(3)
60−#define SIRFSOC_I2C_WRITE BIT(4)
61−#define SIRFSOC_I2C_READ BIT(5)
62−#define SIRFSOC_I2C_STOP BIT(6)
63−#define SIRFSOC_I2C_START BIT(7)
64−
65−#define SIRFSOC_I2C_ERR_NOACK 1
66−#define SIRFSOC_I2C_ERR_TIMEOUT 2
67−
68−struct sirfsoc_i2c {
69− void __iomem *base;
70− struct clk *clk;
71− u32 cmd_ptr; /* Current position in CMD buffer */
72− u8 *buf; /* Buffer passed by user */
73− u32 msg_len; /* Message length */
74− u32 finished_len; /* number of bytes read/written */
75− u32 read_cmd_len; /* number of read cmd sent */
76− int msg_read; /* 1 indicates a read message */
77− int err_status; /* 1 indicates an error on bus */
78−
79− u32 sda_delay; /* For suspend/resume */
80− u32 clk_div;
81− int last; /* Last message in transfer, STOP cmd can be sent */
82−
83− struct completion done; /* indicates completion of message transfer */
84− struct i2c_adapter adapter;
85−};
86−
87−static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
88−{
89− u32 data = 0;
90− int i;
91−
92− for (i = 0; i < siic->read_cmd_len; i++) {
93− if (!(i & 0x3))
94− data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
95− siic->buf[siic->finished_len++] =
96− (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
97− SIRFSOC_I2C_DATA_SHIFT(i));
98− }
99−}
100−
101−static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
102−{
103− u32 regval;
104− int i = 0;
105−
106− if (siic->msg_read) {
107− while (((siic->finished_len + i) < siic->msg_len)
108− && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
109− regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
110− if (((siic->finished_len + i) ==
111− (siic->msg_len - 1)) && siic->last)
112− regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
113− writel(regval,
114− siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
115− i++;
116− }
117−
118− siic->read_cmd_len = i;
119− } else {
120− while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
121− && (siic->finished_len < siic->msg_len)) {
122− regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
123− if ((siic->finished_len == (siic->msg_len - 1))
124− && siic->last)
125− regval |= SIRFSOC_I2C_STOP;
126− writel(regval,
127− siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
128− writel(siic->buf[siic->finished_len++],
129− siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
130− }
131− }
132− siic->cmd_ptr = 0;
133−
134− /* Trigger the transfer */
135− writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
136−}
137−
138−static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
139−{
140− struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
141− u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
142−
143− if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
144− /* Error conditions */
145− siic->err_status = SIRFSOC_I2C_ERR_NOACK;
146− writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
147−
148− if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
149− dev_dbg(&siic->adapter.dev, "ACK not received\n");
150− else
151− dev_err(&siic->adapter.dev, "I2C error\n");
152−
153− /*
154− * Due to hardware ANOMALY, we need to reset I2C earlier after
155− * we get NOACK while accessing non-existing clients, otherwise
156− * we will get errors even we access existing clients later
157− */
158− writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
159− siic->base + SIRFSOC_I2C_CTRL);
160− while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
161− cpu_relax();
162−
163− complete(&siic->done);
164− } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
165− /* CMD buffer execution complete */
166− if (siic->msg_read)
167− i2c_sirfsoc_read_data(siic);
168− if (siic->finished_len == siic->msg_len)
169− complete(&siic->done);
170− else /* Fill a new CMD buffer for left data */
171− i2c_sirfsoc_queue_cmd(siic);
172−
173− writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
174− }
175−
176− return IRQ_HANDLED;
177−}
178−
179−static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
180− struct i2c_msg *msg)
181−{
182− unsigned char addr;
183− u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;
184−
185− /* no data and last message -> add STOP */
186− if (siic->last && (msg->len == 0))
187− regval |= SIRFSOC_I2C_STOP;
188−
189− writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
190−
191− addr = i2c_8bit_addr_from_msg(msg);
192−
193− /* Reverse direction bit */
194− if (msg->flags & I2C_M_REV_DIR_ADDR)
195− addr ^= 1;
196−
197− writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
198−}
199−
200−static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
201−{
202− u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
203− /* timeout waiting for the xfer to finish or fail */
204− int timeout = msecs_to_jiffies((msg->len + 1) * 50);
205−
206− i2c_sirfsoc_set_address(siic, msg);
207−
208− writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
209− siic->base + SIRFSOC_I2C_CTRL);
210− i2c_sirfsoc_queue_cmd(siic);
211−
212− if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
213− siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT;
214− dev_err(&siic->adapter.dev, "Transfer timeout\n");
215− }
216−
217− writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
218− siic->base + SIRFSOC_I2C_CTRL);
219− writel(0, siic->base + SIRFSOC_I2C_CMD_START);
220−
221− /* i2c control doesn't response, reset it */
222− if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) {
223− writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
224− siic->base + SIRFSOC_I2C_CTRL);
225− while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
226− cpu_relax();
227− }
228− return siic->err_status ? -EAGAIN : 0;
229−}
230−
231−static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
232−{
233− return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
234−}
235−
236−static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
237− int num)
238−{
239− struct sirfsoc_i2c *siic = adap->algo_data;
240− int i, ret;
241−
242− clk_enable(siic->clk);
243−
244− for (i = 0; i < num; i++) {
245− siic->buf = msgs[i].buf;
246− siic->msg_len = msgs[i].len;
247− siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
248− siic->err_status = 0;
249− siic->cmd_ptr = 0;
250− siic->finished_len = 0;
251− siic->last = (i == (num - 1));
252−
253− ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
254− if (ret) {
255− clk_disable(siic->clk);
256− return ret;
257− }
258− }
259−
260− clk_disable(siic->clk);
261− return num;
262−}
263−
264−/* I2C algorithms associated with this master controller driver */
265−static const struct i2c_algorithm i2c_sirfsoc_algo = {
266− .master_xfer = i2c_sirfsoc_xfer,
267− .functionality = i2c_sirfsoc_func,
268−};
269−
270−static int i2c_sirfsoc_probe(struct platform_device *pdev)
271−{
272− struct sirfsoc_i2c *siic;
273− struct i2c_adapter *adap;
274− struct clk *clk;
275− int bitrate;
276− int ctrl_speed;
277− int irq;
278−
279− int err;
280− u32 regval;
281−
282− clk = clk_get(&pdev->dev, NULL);
283− if (IS_ERR(clk)) {
284− err = PTR_ERR(clk);
285− dev_err(&pdev->dev, "Clock get failed\n");
286− goto err_get_clk;
287− }
288−
289− err = clk_prepare(clk);
290− if (err) {
291− dev_err(&pdev->dev, "Clock prepare failed\n");
292− goto err_clk_prep;
293− }
294−
295− err = clk_enable(clk);
296− if (err) {
297− dev_err(&pdev->dev, "Clock enable failed\n");
298− goto err_clk_en;
299− }
300−
301− ctrl_speed = clk_get_rate(clk);
302−
303− siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
304− if (!siic) {
305− err = -ENOMEM;
306− goto out;
307− }
308− adap = &siic->adapter;
309− adap->class = I2C_CLASS_DEPRECATED;
310−
311− siic->base = devm_platform_ioremap_resource(pdev, 0);
312− if (IS_ERR(siic->base)) {
313− err = PTR_ERR(siic->base);
314− goto out;
315− }
316−
317− irq = platform_get_irq(pdev, 0);
318− if (irq < 0) {
319− err = irq;
320− goto out;
321− }
322− err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
323− dev_name(&pdev->dev), siic);
324− if (err)
325− goto out;
326−
327− adap->algo = &i2c_sirfsoc_algo;
328− adap->algo_data = siic;
329− adap->retries = 3;
330−
331− adap->dev.of_node = pdev->dev.of_node;
332− adap->dev.parent = &pdev->dev;
333− adap->nr = pdev->id;
334−
335− strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
336−
337− platform_set_drvdata(pdev, adap);
338− init_completion(&siic->done);
339−
340− /* Controller initialisation */
341−
342− writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
343− while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
344− cpu_relax();
345− writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
346− siic->base + SIRFSOC_I2C_CTRL);
347−
348− siic->clk = clk;
349−
350− err = of_property_read_u32(pdev->dev.of_node,
351− "clock-frequency", &bitrate);
352− if (err < 0)
353− bitrate = I2C_MAX_STANDARD_MODE_FREQ;
354−
355− /*
356− * Due to some hardware design issues, we need to tune the formula.
357− * Since i2c is open drain interface that allows the slave to
358− * stall the transaction by holding the SCL line at '0', the RTL
359− * implementation is waiting for SCL feedback from the pin after
360− * setting it to High-Z ('1'). This wait adds to the high-time
361− * interval counter few cycles of the input synchronization
362− * (depending on the SCL_FILTER_REG field), and also the time it
363− * takes for the board pull-up resistor to rise the SCL line.
364− * For slow SCL settings these additions are negligible,
365− * but they start to affect the speed when clock is set to faster
366− * frequencies.
367− * Through the actual tests, use the different user_div value(which
368− * in the divider formula 'Fio / (Fi2c * user_div)') to adapt
369− * the different ranges of i2c bus clock frequency, to make the SCL
370− * more accurate.
371− */
372− if (bitrate <= 30000)
373− regval = ctrl_speed / (bitrate * 5);
374− else if (bitrate > 30000 && bitrate <= 280000)
375− regval = (2 * ctrl_speed) / (bitrate * 11);
376− else
377− regval = ctrl_speed / (bitrate * 6);
378−
379− writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
380− if (regval > 0xFF)
381− writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
382− else
383− writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
384−
385− err = i2c_add_numbered_adapter(adap);
386− if (err < 0)
387− goto out;
388−
389− clk_disable(clk);
390−
391− dev_info(&pdev->dev, " I2C adapter ready to operate\n");
392−
393− return 0;
394−
395−out:
396− clk_disable(clk);
397−err_clk_en:
398− clk_unprepare(clk);
399−err_clk_prep:
400− clk_put(clk);
401−err_get_clk:
402− return err;
403−}
404−
405−static int i2c_sirfsoc_remove(struct platform_device *pdev)
406−{
407− struct i2c_adapter *adapter = platform_get_drvdata(pdev);
408− struct sirfsoc_i2c *siic = adapter->algo_data;
409−
410− writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
411− i2c_del_adapter(adapter);
412− clk_unprepare(siic->clk);
413− clk_put(siic->clk);
414− return 0;
415−}
416−
417−#ifdef CONFIG_PM
418−static int i2c_sirfsoc_suspend(struct device *dev)
419−{
420− struct i2c_adapter *adapter = dev_get_drvdata(dev);
421− struct sirfsoc_i2c *siic = adapter->algo_data;
422−
423− clk_enable(siic->clk);
424− siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
425− siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
426− clk_disable(siic->clk);
427− return 0;
428−}
429−
430−static int i2c_sirfsoc_resume(struct device *dev)
431−{
432− struct i2c_adapter *adapter = dev_get_drvdata(dev);
433− struct sirfsoc_i2c *siic = adapter->algo_data;
434−
435− clk_enable(siic->clk);
436− writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
437− while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
438− cpu_relax();
439− writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
440− siic->base + SIRFSOC_I2C_CTRL);
441− writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
442− writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
443− clk_disable(siic->clk);
444− return 0;
445−}
446−
447−static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
448− .suspend = i2c_sirfsoc_suspend,
449− .resume = i2c_sirfsoc_resume,
450−};
451−#endif
452−
453−static const struct of_device_id sirfsoc_i2c_of_match[] = {
454− { .compatible = "sirf,prima2-i2c", },
455− {},
456−};
457−MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
458−
459−static struct platform_driver i2c_sirfsoc_driver = {
460− .driver = {
461− .name = "sirfsoc_i2c",
462−#ifdef CONFIG_PM
463− .pm = &i2c_sirfsoc_pm_ops,
464−#endif
465− .of_match_table = sirfsoc_i2c_of_match,
466− },
467− .probe = i2c_sirfsoc_probe,
468− .remove = i2c_sirfsoc_remove,
469−};
470−module_platform_driver(i2c_sirfsoc_driver);
471−
472−MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
473−MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
474−MODULE_AUTHOR("Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
475−MODULE_LICENSE("GPL v2");
drivers/i2c/busses/i2c-stm32f7.c+1−5
@@ -2035,12 +2035,8 @@ static int stm32f7_i2c_probe(struct platform_device *pdev) · 2034 unmodified lines
20352035 }
20362036
20372037 irq_error = platform_get_irq(pdev, 1);
2038− if (irq_error <= 0) {
2039− if (irq_error != -EPROBE_DEFER)
2040− dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
2041− irq_error);
2038+ if (irq_error <= 0)
20422039 return irq_error ? : -ENOENT;
2043− }
20442040
20452041 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
20462042 "wakeup-source");
drivers/i2c/busses/i2c-stu300.c+0−1008
@@ -1,1008 +0,0 @@
1−// SPDX-License-Identifier: GPL-2.0-only
2−/*
3− * Copyright (C) 2007-2012 ST-Ericsson AB
4− * ST DDC I2C master mode driver, used in e.g. U300 series platforms.
5− * Author: Linus Walleij <linus.walleij@stericsson.com>
6− * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7− */
8−#include <linux/init.h>
9−#include <linux/module.h>
10−#include <linux/platform_device.h>
11−#include <linux/delay.h>
12−#include <linux/i2c.h>
13−#include <linux/spinlock.h>
14−#include <linux/completion.h>
15−#include <linux/err.h>
16−#include <linux/interrupt.h>
17−#include <linux/clk.h>
18−#include <linux/io.h>
19−#include <linux/slab.h>
20−
21−/* the name of this kernel module */
22−#define NAME "stu300"
23−
24−/* CR (Control Register) 8bit (R/W) */
25−#define I2C_CR (0x00000000)
26−#define I2C_CR_RESET_VALUE (0x00)
27−#define I2C_CR_RESET_UMASK (0x00)
28−#define I2C_CR_DDC1_ENABLE (0x80)
29−#define I2C_CR_TRANS_ENABLE (0x40)
30−#define I2C_CR_PERIPHERAL_ENABLE (0x20)
31−#define I2C_CR_DDC2B_ENABLE (0x10)
32−#define I2C_CR_START_ENABLE (0x08)
33−#define I2C_CR_ACK_ENABLE (0x04)
34−#define I2C_CR_STOP_ENABLE (0x02)
35−#define I2C_CR_INTERRUPT_ENABLE (0x01)
36−/* SR1 (Status Register 1) 8bit (R/-) */
37−#define I2C_SR1 (0x00000004)
38−#define I2C_SR1_RESET_VALUE (0x00)
39−#define I2C_SR1_RESET_UMASK (0x00)
40−#define I2C_SR1_EVF_IND (0x80)
41−#define I2C_SR1_ADD10_IND (0x40)
42−#define I2C_SR1_TRA_IND (0x20)
43−#define I2C_SR1_BUSY_IND (0x10)
44−#define I2C_SR1_BTF_IND (0x08)
45−#define I2C_SR1_ADSL_IND (0x04)
46−#define I2C_SR1_MSL_IND (0x02)
47−#define I2C_SR1_SB_IND (0x01)
48−/* SR2 (Status Register 2) 8bit (R/-) */
49−#define I2C_SR2 (0x00000008)
50−#define I2C_SR2_RESET_VALUE (0x00)
51−#define I2C_SR2_RESET_UMASK (0x40)
52−#define I2C_SR2_MASK (0xBF)
53−#define I2C_SR2_SCLFAL_IND (0x80)
54−#define I2C_SR2_ENDAD_IND (0x20)
55−#define I2C_SR2_AF_IND (0x10)
56−#define I2C_SR2_STOPF_IND (0x08)
57−#define I2C_SR2_ARLO_IND (0x04)
58−#define I2C_SR2_BERR_IND (0x02)
59−#define I2C_SR2_DDC2BF_IND (0x01)
60−/* CCR (Clock Control Register) 8bit (R/W) */
61−#define I2C_CCR (0x0000000C)
62−#define I2C_CCR_RESET_VALUE (0x00)
63−#define I2C_CCR_RESET_UMASK (0x00)
64−#define I2C_CCR_MASK (0xFF)
65−#define I2C_CCR_FMSM (0x80)
66−#define I2C_CCR_CC_MASK (0x7F)
67−/* OAR1 (Own Address Register 1) 8bit (R/W) */
68−#define I2C_OAR1 (0x00000010)
69−#define I2C_OAR1_RESET_VALUE (0x00)
70−#define I2C_OAR1_RESET_UMASK (0x00)
71−#define I2C_OAR1_ADD_MASK (0xFF)
72−/* OAR2 (Own Address Register 2) 8bit (R/W) */
73−#define I2C_OAR2 (0x00000014)
74−#define I2C_OAR2_RESET_VALUE (0x40)
75−#define I2C_OAR2_RESET_UMASK (0x19)
76−#define I2C_OAR2_MASK (0xE6)
77−#define I2C_OAR2_FR_25_10MHZ (0x00)
78−#define I2C_OAR2_FR_10_1667MHZ (0x20)
79−#define I2C_OAR2_FR_1667_2667MHZ (0x40)
80−#define I2C_OAR2_FR_2667_40MHZ (0x60)
81−#define I2C_OAR2_FR_40_5333MHZ (0x80)
82−#define I2C_OAR2_FR_5333_66MHZ (0xA0)
83−#define I2C_OAR2_FR_66_80MHZ (0xC0)
84−#define I2C_OAR2_FR_80_100MHZ (0xE0)
85−#define I2C_OAR2_FR_MASK (0xE0)
86−#define I2C_OAR2_ADD_MASK (0x06)
87−/* DR (Data Register) 8bit (R/W) */
88−#define I2C_DR (0x00000018)
89−#define I2C_DR_RESET_VALUE (0x00)
90−#define I2C_DR_RESET_UMASK (0xFF)
91−#define I2C_DR_D_MASK (0xFF)
92−/* ECCR (Extended Clock Control Register) 8bit (R/W) */
93−#define I2C_ECCR (0x0000001C)
94−#define I2C_ECCR_RESET_VALUE (0x00)
95−#define I2C_ECCR_RESET_UMASK (0xE0)
96−#define I2C_ECCR_MASK (0x1F)
97−#define I2C_ECCR_CC_MASK (0x1F)
98−
99−/*
100− * These events are more or less responses to commands
101− * sent into the hardware, presumably reflecting the state
102− * of an internal state machine.
103− */
104−enum stu300_event {
105− STU300_EVENT_NONE = 0,
106− STU300_EVENT_1,
107− STU300_EVENT_2,
108− STU300_EVENT_3,
109− STU300_EVENT_4,
110− STU300_EVENT_5,
111− STU300_EVENT_6,
112− STU300_EVENT_7,
113− STU300_EVENT_8,
114− STU300_EVENT_9
115−};
116−
117−enum stu300_error {
118− STU300_ERROR_NONE = 0,
119− STU300_ERROR_ACKNOWLEDGE_FAILURE,
120− STU300_ERROR_BUS_ERROR,
121− STU300_ERROR_ARBITRATION_LOST,
122− STU300_ERROR_UNKNOWN
123−};
124−
125−/* timeout waiting for the controller to respond */
126−#define STU300_TIMEOUT (msecs_to_jiffies(1000))
127−
128−/*
129− * The number of address send athemps tried before giving up.
130− * If the first one fails it seems like 5 to 8 attempts are required.
131− */
132−#define NUM_ADDR_RESEND_ATTEMPTS 12
133−
134−/* I2C clock speed, in Hz 0-400kHz*/
135−static unsigned int scl_frequency = I2C_MAX_STANDARD_MODE_FREQ;
136−module_param(scl_frequency, uint, 0644);
137−
138−/**
139− * struct stu300_dev - the stu300 driver state holder
140− * @pdev: parent platform device
141− * @adapter: corresponding I2C adapter
142− * @clk: hardware block clock
143− * @irq: assigned interrupt line
144− * @cmd_issue_lock: this locks the following cmd_ variables
145− * @cmd_complete: acknowledge completion for an I2C command
146− * @cmd_event: expected event coming in as a response to a command
147− * @cmd_err: error code as response to a command
148− * @speed: current bus speed in Hz
149− * @msg_index: index of current message
150− * @msg_len: length of current message
151− */
152−
153−struct stu300_dev {
154− struct platform_device *pdev;
155− struct i2c_adapter adapter;
156− void __iomem *virtbase;
157− struct clk *clk;
158− int irq;
159− spinlock_t cmd_issue_lock;
160− struct completion cmd_complete;
161− enum stu300_event cmd_event;
162− enum stu300_error cmd_err;
163− unsigned int speed;
164− int msg_index;
165− int msg_len;
166−};
167−
168−/* Local forward function declarations */
169−static int stu300_init_hw(struct stu300_dev *dev);
170−
171−/*
172− * The block needs writes in both MSW and LSW in order
173− * for all data lines to reach their destination.
174− */
175−static inline void stu300_wr8(u32 value, void __iomem *address)
176−{
177− writel((value << 16) | value, address);
178−}
179−
180−/*
181− * This merely masks off the duplicates which appear
182− * in bytes 1-3. You _MUST_ use 32-bit bus access on this
183− * device, else it will not work.
184− */
185−static inline u32 stu300_r8(void __iomem *address)
186−{
187− return readl(address) & 0x000000FFU;
188−}
189−
190−static void stu300_irq_enable(struct stu300_dev *dev)
191−{
192− u32 val;
193− val = stu300_r8(dev->virtbase + I2C_CR);
194− val |= I2C_CR_INTERRUPT_ENABLE;
195− /* Twice paranoia (possible HW glitch) */
196− stu300_wr8(val, dev->virtbase + I2C_CR);
197− stu300_wr8(val, dev->virtbase + I2C_CR);
198−}
199−
200−static void stu300_irq_disable(struct stu300_dev *dev)
201−{
202− u32 val;
203− val = stu300_r8(dev->virtbase + I2C_CR);
204− val &= ~I2C_CR_INTERRUPT_ENABLE;
205− /* Twice paranoia (possible HW glitch) */
206− stu300_wr8(val, dev->virtbase + I2C_CR);
207− stu300_wr8(val, dev->virtbase + I2C_CR);
208−}
209−
210−
211−/*
212− * Tells whether a certain event or events occurred in
213− * response to a command. The events represent states in
214− * the internal state machine of the hardware. The events
215− * are not very well described in the hardware
216− * documentation and can only be treated as abstract state
217− * machine states.
218− *
219− * @ret 0 = event has not occurred or unknown error, any
220− * other value means the correct event occurred or an error.
221− */
222−
223−static int stu300_event_occurred(struct stu300_dev *dev,
224− enum stu300_event mr_event) {
225− u32 status1;
226− u32 status2;
227−
228− /* What event happened? */
229− status1 = stu300_r8(dev->virtbase + I2C_SR1);
230−
231− if (!(status1 & I2C_SR1_EVF_IND))
232− /* No event at all */
233− return 0;
234−
235− status2 = stu300_r8(dev->virtbase + I2C_SR2);
236−
237− /* Block any multiple interrupts */
238− stu300_irq_disable(dev);
239−
240− /* Check for errors first */
241− if (status2 & I2C_SR2_AF_IND) {
242− dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
243− return 1;
244− } else if (status2 & I2C_SR2_BERR_IND) {
245− dev->cmd_err = STU300_ERROR_BUS_ERROR;
246− return 1;
247− } else if (status2 & I2C_SR2_ARLO_IND) {
248− dev->cmd_err = STU300_ERROR_ARBITRATION_LOST;
249− return 1;
250− }
251−
252− switch (mr_event) {
253− case STU300_EVENT_1:
254− if (status1 & I2C_SR1_ADSL_IND)
255− return 1;
256− break;
257− case STU300_EVENT_2:
258− case STU300_EVENT_3:
259− case STU300_EVENT_7:
260− case STU300_EVENT_8:
261− if (status1 & I2C_SR1_BTF_IND) {
262− return 1;
263− }
264− break;
265− case STU300_EVENT_4:
266− if (status2 & I2C_SR2_STOPF_IND)
267− return 1;
268− break;
269− case STU300_EVENT_5:
270− if (status1 & I2C_SR1_SB_IND)
271− /* Clear start bit */
272− return 1;
273− break;
274− case STU300_EVENT_6:
275− if (status2 & I2C_SR2_ENDAD_IND) {
276− /* First check for any errors */
277− return 1;
278− }
279− break;
280− case STU300_EVENT_9:
281− if (status1 & I2C_SR1_ADD10_IND)
282− return 1;
283− break;
284− default:
285− break;
286− }
287− /* If we get here, we're on thin ice.
288− * Here we are in a status where we have
289− * gotten a response that does not match
290− * what we requested.
291− */
292− dev->cmd_err = STU300_ERROR_UNKNOWN;
293− dev_err(&dev->pdev->dev,
294− "Unhandled interrupt! %d sr1: 0x%x sr2: 0x%x\n",
295− mr_event, status1, status2);
296− return 0;
297−}
298−
299−static irqreturn_t stu300_irh(int irq, void *data)
300−{
301− struct stu300_dev *dev = data;
302− int res;
303−
304− /* Just make sure that the block is clocked */
305− clk_enable(dev->clk);
306−
307− /* See if this was what we were waiting for */
308− spin_lock(&dev->cmd_issue_lock);
309−
310− res = stu300_event_occurred(dev, dev->cmd_event);
311− if (res || dev->cmd_err != STU300_ERROR_NONE)
312− complete(&dev->cmd_complete);
313−
314− spin_unlock(&dev->cmd_issue_lock);
315−
316− clk_disable(dev->clk);
317−
318− return IRQ_HANDLED;
319−}
320−
321−/*
322− * Sends a command and then waits for the bits masked by *flagmask*
323− * to go high or low by IRQ awaiting.
324− */
325−static int stu300_start_and_await_event(struct stu300_dev *dev,
326− u8 cr_value,
327− enum stu300_event mr_event)
328−{
329− int ret;
330−
331− /* Lock command issue, fill in an event we wait for */
332− spin_lock_irq(&dev->cmd_issue_lock);
333− init_completion(&dev->cmd_complete);
334− dev->cmd_err = STU300_ERROR_NONE;
335− dev->cmd_event = mr_event;
336− spin_unlock_irq(&dev->cmd_issue_lock);
337−
338− /* Turn on interrupt, send command and wait. */
339− cr_value |= I2C_CR_INTERRUPT_ENABLE;
340− stu300_wr8(cr_value, dev->virtbase + I2C_CR);
341− ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
342− STU300_TIMEOUT);
343− if (ret < 0) {
344− dev_err(&dev->pdev->dev,
345− "wait_for_completion_interruptible_timeout() "
346− "returned %d waiting for event %04x\n", ret, mr_event);
347− return ret;
348− }
349−
350− if (ret == 0) {
351− dev_err(&dev->pdev->dev, "controller timed out "
352− "waiting for event %d, reinit hardware\n", mr_event);
353− (void) stu300_init_hw(dev);
354− return -ETIMEDOUT;
355− }
356−
357− if (dev->cmd_err != STU300_ERROR_NONE) {
358− dev_err(&dev->pdev->dev, "controller (start) "
359− "error %d waiting for event %d, reinit hardware\n",
360− dev->cmd_err, mr_event);
361− (void) stu300_init_hw(dev);
362− return -EIO;
363− }
364−
365− return 0;
366−}
367−
368−/*
369− * This waits for a flag to be set, if it is not set on entry, an interrupt is
370− * configured to wait for the flag using a completion.
371− */
372−static int stu300_await_event(struct stu300_dev *dev,
373− enum stu300_event mr_event)
374−{
375− int ret;
376−
377− /* Is it already here? */
378− spin_lock_irq(&dev->cmd_issue_lock);
379− dev->cmd_err = STU300_ERROR_NONE;
380− dev->cmd_event = mr_event;
381−
382− init_completion(&dev->cmd_complete);
383−
384− /* Turn on the I2C interrupt for current operation */
385− stu300_irq_enable(dev);
386−
387− /* Unlock the command block and wait for the event to occur */
388− spin_unlock_irq(&dev->cmd_issue_lock);
389−
390− ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
391− STU300_TIMEOUT);
392− if (ret < 0) {
393− dev_err(&dev->pdev->dev,
394− "wait_for_completion_interruptible_timeout()"
395− "returned %d waiting for event %04x\n", ret, mr_event);
396− return ret;
397− }
398−
399− if (ret == 0) {
400− if (mr_event != STU300_EVENT_6) {
401− dev_err(&dev->pdev->dev, "controller "
402− "timed out waiting for event %d, reinit "
403− "hardware\n", mr_event);
404− (void) stu300_init_hw(dev);
405− }
406− return -ETIMEDOUT;
407− }
408−
409− if (dev->cmd_err != STU300_ERROR_NONE) {
410− if (mr_event != STU300_EVENT_6) {
411− dev_err(&dev->pdev->dev, "controller "
412− "error (await_event) %d waiting for event %d, "
413− "reinit hardware\n", dev->cmd_err, mr_event);
414− (void) stu300_init_hw(dev);
415− }
416− return -EIO;
417− }
418−
419− return 0;
420−}
421−
422−/*
423− * Waits for the busy bit to go low by repeated polling.
424− */
425−#define BUSY_RELEASE_ATTEMPTS 10
426−static int stu300_wait_while_busy(struct stu300_dev *dev)
427−{
428− unsigned long timeout;
429− int i;
430−
431− for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) {
432− timeout = jiffies + STU300_TIMEOUT;
433−
434− while (!time_after(jiffies, timeout)) {
435− /* Is not busy? */
436− if ((stu300_r8(dev->virtbase + I2C_SR1) &
437− I2C_SR1_BUSY_IND) == 0)
438− return 0;
439− msleep(1);
440− }
441−
442− dev_err(&dev->pdev->dev, "transaction timed out "
443− "waiting for device to be free (not busy). "
444− "Attempt: %d\n", i+1);
445−
446− dev_err(&dev->pdev->dev, "base address = "
447− "0x%p, reinit hardware\n", dev->virtbase);
448−
449− (void) stu300_init_hw(dev);
450− }
451−
452− dev_err(&dev->pdev->dev, "giving up after %d attempts "
453− "to reset the bus.\n", BUSY_RELEASE_ATTEMPTS);
454−
455− return -ETIMEDOUT;
456−}
457−
458−struct stu300_clkset {
459− unsigned long rate;
460− u32 setting;
461−};
462−
463−static const struct stu300_clkset stu300_clktable[] = {
464− { 0, 0xFFU },
465− { 2500000, I2C_OAR2_FR_25_10MHZ },
466− { 10000000, I2C_OAR2_FR_10_1667MHZ },
467− { 16670000, I2C_OAR2_FR_1667_2667MHZ },
468− { 26670000, I2C_OAR2_FR_2667_40MHZ },
469− { 40000000, I2C_OAR2_FR_40_5333MHZ },
470− { 53330000, I2C_OAR2_FR_5333_66MHZ },
471− { 66000000, I2C_OAR2_FR_66_80MHZ },
472− { 80000000, I2C_OAR2_FR_80_100MHZ },
473− { 100000000, 0xFFU },
474−};
475−
476−
477−static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate)
478−{
479−
480− u32 val;
481− int i = 0;
482−
483− /* Locate the appropriate clock setting */
484− while (i < ARRAY_SIZE(stu300_clktable) - 1 &&
485− stu300_clktable[i].rate < clkrate)
486− i++;
487−
488− if (stu300_clktable[i].setting == 0xFFU) {
489− dev_err(&dev->pdev->dev, "too %s clock rate requested "
490− "(%lu Hz).\n", i ? "high" : "low", clkrate);
491− return -EINVAL;
492− }
493−
494− stu300_wr8(stu300_clktable[i].setting,
495− dev->virtbase + I2C_OAR2);
496−
497− dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz "
498− "virtbase %p\n", clkrate, dev->speed, dev->virtbase);
499−
500− if (dev->speed > I2C_MAX_STANDARD_MODE_FREQ)
501− /* Fast Mode I2C */
502− val = ((clkrate/dev->speed) - 9)/3 + 1;
503− else
504− /* Standard Mode I2C */
505− val = ((clkrate/dev->speed) - 7)/2 + 1;
506−
507− /* According to spec the divider must be > 2 */
508− if (val < 0x002) {
509− dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n",
510− clkrate);
511− return -EINVAL;
512− }
513−
514− /* We have 12 bits clock divider only! */
515− if (val & 0xFFFFF000U) {
516− dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n",
517− clkrate);
518− return -EINVAL;
519− }
520−
521− if (dev->speed > I2C_MAX_STANDARD_MODE_FREQ) {
522− /* CC6..CC0 */
523− stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM,
524− dev->virtbase + I2C_CCR);
525− dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, "
526− "Fast Mode I2C\n", val);
527− } else {
528− /* CC6..CC0 */
529− stu300_wr8((val & I2C_CCR_CC_MASK),
530− dev->virtbase + I2C_CCR);
531− dev_dbg(&dev->pdev->dev, "set clock divider to "
532− "0x%08x, Standard Mode I2C\n", val);
533− }
534−
535− /* CC11..CC7 */
536− stu300_wr8(((val >> 7) & 0x1F),
537− dev->virtbase + I2C_ECCR);
538−
539− return 0;
540−}
541−
542−
543−static int stu300_init_hw(struct stu300_dev *dev)
544−{
545− u32 dummy;
546− unsigned long clkrate;
547− int ret;
548−
549− /* Disable controller */
550− stu300_wr8(0x00, dev->virtbase + I2C_CR);
551− /*
552− * Set own address to some default value (0x00).
553− * We do not support slave mode anyway.
554− */
555− stu300_wr8(0x00, dev->virtbase + I2C_OAR1);
556− /*
557− * The I2C controller only operates properly in 26 MHz but we
558− * program this driver as if we didn't know. This will also set the two
559− * high bits of the own address to zero as well.
560− * There is no known hardware issue with running in 13 MHz
561− * However, speeds over 200 kHz are not used.
562− */
563− clkrate = clk_get_rate(dev->clk);
564− ret = stu300_set_clk(dev, clkrate);
565−
566− if (ret)
567− return ret;
568− /*
569− * Enable block, do it TWICE (hardware glitch)
570− * Setting bit 7 can enable DDC mode. (Not used currently.)
571− */
572− stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
573− dev->virtbase + I2C_CR);
574− stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
575− dev->virtbase + I2C_CR);
576− /* Make a dummy read of the status register SR1 & SR2 */
577− dummy = stu300_r8(dev->virtbase + I2C_SR2);
578− dummy = stu300_r8(dev->virtbase + I2C_SR1);
579−
580− return 0;
581−}
582−
583−
584−
585−/* Send slave address. */
586−static int stu300_send_address(struct stu300_dev *dev,
587− struct i2c_msg *msg, int resend)
588−{
589− u32 val;
590− int ret;
591−
592− if (msg->flags & I2C_M_TEN) {
593− /* This is probably how 10 bit addresses look */
594− val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) &
595− I2C_DR_D_MASK;
596− if (msg->flags & I2C_M_RD)
597− /* This is the direction bit */
598− val |= 0x01;
599− } else {
600− val = i2c_8bit_addr_from_msg(msg);
601− }
602−
603− if (resend) {
604− if (msg->flags & I2C_M_RD)
605− dev_dbg(&dev->pdev->dev, "read resend\n");
606− else
607− dev_dbg(&dev->pdev->dev, "write resend\n");
608− }
609−
610− stu300_wr8(val, dev->virtbase + I2C_DR);
611−
612− /* For 10bit addressing, await 10bit request (EVENT 9) */
613− if (msg->flags & I2C_M_TEN) {
614− ret = stu300_await_event(dev, STU300_EVENT_9);
615− /*
616− * The slave device wants a 10bit address, send the rest
617− * of the bits (the LSBits)
618− */
619− val = msg->addr & I2C_DR_D_MASK;
620− /* This clears "event 9" */
621− stu300_wr8(val, dev->virtbase + I2C_DR);
622− if (ret != 0)
623− return ret;
624− }
625− /* FIXME: Why no else here? two events for 10bit?
626− * Await event 6 (normal) or event 9 (10bit)
627− */
628−
629− if (resend)
630− dev_dbg(&dev->pdev->dev, "await event 6\n");
631− ret = stu300_await_event(dev, STU300_EVENT_6);
632−
633− /*
634− * Clear any pending EVENT 6 no matter what happened during
635− * await_event.
636− */
637− val = stu300_r8(dev->virtbase + I2C_CR);
638− val |= I2C_CR_PERIPHERAL_ENABLE;
639− stu300_wr8(val, dev->virtbase + I2C_CR);
640−
641− return ret;
642−}
643−
644−static int stu300_xfer_msg(struct i2c_adapter *adap,
645− struct i2c_msg *msg, int stop)
646−{
647− u32 cr;
648− u32 val;
649− u32 i;
650− int ret;
651− int attempts = 0;
652− struct stu300_dev *dev = i2c_get_adapdata(adap);
653−
654− clk_enable(dev->clk);
655−
656− /* Remove this if (0) to trace each and every message. */
657− if (0) {
658− dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, "
659− "flags: 0x%04x, stop: %d\n",
660− msg->addr, msg->len, msg->flags, stop);
661− }
662−
663− /*
664− * For some reason, sending the address sometimes fails when running
665− * on the 13 MHz clock. No interrupt arrives. This is a work around,
666− * which tries to restart and send the address up to 10 times before
667− * really giving up. Usually 5 to 8 attempts are enough.
668− */
669− do {
670− if (attempts)
671− dev_dbg(&dev->pdev->dev, "wait while busy\n");
672− /* Check that the bus is free, or wait until some timeout */
673− ret = stu300_wait_while_busy(dev);
674− if (ret != 0)
675− goto exit_disable;
676−
677− if (attempts)
678− dev_dbg(&dev->pdev->dev, "re-int hw\n");
679− /*
680− * According to ST, there is no problem if the clock is
681− * changed between 13 and 26 MHz during a transfer.
682− */
683− ret = stu300_init_hw(dev);
684− if (ret)
685− goto exit_disable;
686−
687− /* Send a start condition */
688− cr = I2C_CR_PERIPHERAL_ENABLE;
689− /* Setting the START bit puts the block in master mode */
690− if (!(msg->flags & I2C_M_NOSTART))
691− cr |= I2C_CR_START_ENABLE;
692− if ((msg->flags & I2C_M_RD) && (msg->len > 1))
693− /* On read more than 1 byte, we need ack. */
694− cr |= I2C_CR_ACK_ENABLE;
695− /* Check that it gets through */
696− if (!(msg->flags & I2C_M_NOSTART)) {
697− if (attempts)
698− dev_dbg(&dev->pdev->dev, "send start event\n");
699− ret = stu300_start_and_await_event(dev, cr,
700− STU300_EVENT_5);
701− }
702−
703− if (attempts)
704− dev_dbg(&dev->pdev->dev, "send address\n");
705−
706− if (ret == 0)
707− /* Send address */
708− ret = stu300_send_address(dev, msg, attempts != 0);
709−
710− if (ret != 0) {
711− attempts++;
712− dev_dbg(&dev->pdev->dev, "failed sending address, "
713− "retrying. Attempt: %d msg_index: %d/%d\n",
714− attempts, dev->msg_index, dev->msg_len);
715− }
716−
717− } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS);
718−
719− if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) {
720− dev_dbg(&dev->pdev->dev, "managed to get address "
721− "through after %d attempts\n", attempts);
722− } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) {
723− dev_dbg(&dev->pdev->dev, "I give up, tried %d times "
724− "to resend address.\n",
725− NUM_ADDR_RESEND_ATTEMPTS);
726− goto exit_disable;
727− }
728−
729−
730− if (msg->flags & I2C_M_RD) {
731− /* READ: we read the actual bytes one at a time */
732− for (i = 0; i < msg->len; i++) {
733− if (i == msg->len-1) {
734− /*
735− * Disable ACK and set STOP condition before
736− * reading last byte
737− */
738− val = I2C_CR_PERIPHERAL_ENABLE;
739−
740− if (stop)
741− val |= I2C_CR_STOP_ENABLE;
742−
743− stu300_wr8(val,
744− dev->virtbase + I2C_CR);
745− }
746− /* Wait for this byte... */
747− ret = stu300_await_event(dev, STU300_EVENT_7);
748− if (ret != 0)
749− goto exit_disable;
750− /* This clears event 7 */
751− msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR);
752− }
753− } else {
754− /* WRITE: we send the actual bytes one at a time */
755− for (i = 0; i < msg->len; i++) {
756− /* Write the byte */
757− stu300_wr8(msg->buf[i],
758− dev->virtbase + I2C_DR);
759− /* Check status */
760− ret = stu300_await_event(dev, STU300_EVENT_8);
761− /* Next write to DR will clear event 8 */
762− if (ret != 0) {
763− dev_err(&dev->pdev->dev, "error awaiting "
764− "event 8 (%d)\n", ret);
765− goto exit_disable;
766− }
767− }
768− /* Check NAK */
769− if (!(msg->flags & I2C_M_IGNORE_NAK)) {
770− if (stu300_r8(dev->virtbase + I2C_SR2) &
771− I2C_SR2_AF_IND) {
772− dev_err(&dev->pdev->dev, "I2C payload "
773− "send returned NAK!\n");
774− ret = -EIO;
775− goto exit_disable;
776− }
777− }
778− if (stop) {
779− /* Send stop condition */
780− val = I2C_CR_PERIPHERAL_ENABLE;
781− val |= I2C_CR_STOP_ENABLE;
782− stu300_wr8(val, dev->virtbase + I2C_CR);
783− }
784− }
785−
786− /* Check that the bus is free, or wait until some timeout occurs */
787− ret = stu300_wait_while_busy(dev);
788− if (ret != 0) {
789− dev_err(&dev->pdev->dev, "timeout waiting for transfer "
790− "to commence.\n");
791− goto exit_disable;
792− }
793−
794− /* Dummy read status registers */
795− val = stu300_r8(dev->virtbase + I2C_SR2);
796− val = stu300_r8(dev->virtbase + I2C_SR1);
797− ret = 0;
798−
799− exit_disable:
800− /* Disable controller */
801− stu300_wr8(0x00, dev->virtbase + I2C_CR);
802− clk_disable(dev->clk);
803− return ret;
804−}
805−
806−static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
807− int num)
808−{
809− int ret = -1;
810− int i;
811−
812− struct stu300_dev *dev = i2c_get_adapdata(adap);
813− dev->msg_len = num;
814−
815− for (i = 0; i < num; i++) {
816− /*
817− * Another driver appears to send stop for each message,
818− * here we only do that for the last message. Possibly some
819− * peripherals require this behaviour, then their drivers
820− * have to send single messages in order to get "stop" for
821− * each message.
822− */
823− dev->msg_index = i;
824−
825− ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1)));
826−
827− if (ret != 0) {
828− num = ret;
829− break;
830− }
831− }
832−
833− return num;
834−}
835−
836−static int stu300_xfer_todo(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
837−{
838− /* TODO: implement polling for this case if need be. */
839− WARN(1, "%s: atomic transfers not implemented\n", dev_name(&adap->dev));
840− return -EOPNOTSUPP;
841−}
842−
843−static u32 stu300_func(struct i2c_adapter *adap)
844−{
845− /* This is the simplest thing you can think of... */
846− return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
847−}
848−
849−static const struct i2c_algorithm stu300_algo = {
850− .master_xfer = stu300_xfer,
851− .master_xfer_atomic = stu300_xfer_todo,
852− .functionality = stu300_func,
853−};
854−
855−static const struct i2c_adapter_quirks stu300_quirks = {
856− .flags = I2C_AQ_NO_ZERO_LEN,
857−};
858−
859−static int stu300_probe(struct platform_device *pdev)
860−{
861− struct stu300_dev *dev;
862− struct i2c_adapter *adap;
863− int bus_nr;
864− int ret = 0;
865−
866− dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
867− if (!dev)
868− return -ENOMEM;
869−
870− bus_nr = pdev->id;
871− dev->clk = devm_clk_get(&pdev->dev, NULL);
872− if (IS_ERR(dev->clk)) {
873− dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
874− return PTR_ERR(dev->clk);
875− }
876−
877− dev->pdev = pdev;
878− dev->virtbase = devm_platform_ioremap_resource(pdev, 0);
879− dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
880− "base %p\n", bus_nr, dev->virtbase);
881− if (IS_ERR(dev->virtbase))
882− return PTR_ERR(dev->virtbase);
883−
884− dev->irq = platform_get_irq(pdev, 0);
885− ret = devm_request_irq(&pdev->dev, dev->irq, stu300_irh, 0, NAME, dev);
886− if (ret < 0)
887− return ret;
888−
889− dev->speed = scl_frequency;
890−
891− clk_prepare_enable(dev->clk);
892− ret = stu300_init_hw(dev);
893− clk_disable(dev->clk);
894− if (ret != 0) {
895− dev_err(&dev->pdev->dev, "error initializing hardware.\n");
896− return -EIO;
897− }
898−
899− /* IRQ event handling initialization */
900− spin_lock_init(&dev->cmd_issue_lock);
901− dev->cmd_event = STU300_EVENT_NONE;
902− dev->cmd_err = STU300_ERROR_NONE;
903−
904− adap = &dev->adapter;
905− adap->owner = THIS_MODULE;
906− /* DDC class but actually often used for more generic I2C */
907− adap->class = I2C_CLASS_DEPRECATED;
908− strlcpy(adap->name, "ST Microelectronics DDC I2C adapter",
909− sizeof(adap->name));
910− adap->nr = bus_nr;
911− adap->algo = &stu300_algo;
912− adap->dev.parent = &pdev->dev;
913− adap->dev.of_node = pdev->dev.of_node;
914− adap->quirks = &stu300_quirks;
915−
916− i2c_set_adapdata(adap, dev);
917−
918− /* i2c device drivers may be active on return from add_adapter() */
919− ret = i2c_add_numbered_adapter(adap);
920− if (ret)
921− return ret;
922−
923− platform_set_drvdata(pdev, dev);
924− dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
925− dev->virtbase, dev->irq);
926−
927− return 0;
928−}
929−
930−#ifdef CONFIG_PM_SLEEP
931−static int stu300_suspend(struct device *device)
932−{
933− struct stu300_dev *dev = dev_get_drvdata(device);
934−
935− /* Turn off everything */
936− stu300_wr8(0x00, dev->virtbase + I2C_CR);
937− return 0;
938−}
939−
940−static int stu300_resume(struct device *device)
941−{
942− int ret = 0;
943− struct stu300_dev *dev = dev_get_drvdata(device);
944−
945− clk_enable(dev->clk);
946− ret = stu300_init_hw(dev);
947− clk_disable(dev->clk);
948−
949− if (ret != 0)
950− dev_err(device, "error re-initializing hardware.\n");
951− return ret;
952−}
953−
954−static SIMPLE_DEV_PM_OPS(stu300_pm, stu300_suspend, stu300_resume);
955−#define STU300_I2C_PM (&stu300_pm)
956−#else
957−#define STU300_I2C_PM NULL
958−#endif
959−
960−static int stu300_remove(struct platform_device *pdev)
961−{
962− struct stu300_dev *dev = platform_get_drvdata(pdev);
963−
964− i2c_del_adapter(&dev->adapter);
965− /* Turn off everything */
966− stu300_wr8(0x00, dev->virtbase + I2C_CR);
967− return 0;
968−}
969−
970−static const struct of_device_id stu300_dt_match[] = {
971− { .compatible = "st,ddci2c" },
972− {},
973−};
974−MODULE_DEVICE_TABLE(of, stu300_dt_match);
975−
976−static struct platform_driver stu300_i2c_driver = {
977− .driver = {
978− .name = NAME,
979− .pm = STU300_I2C_PM,
980− .of_match_table = stu300_dt_match,
981− },
982− .probe = stu300_probe,
983− .remove = stu300_remove,
984−
985−};
986−
987−static int __init stu300_init(void)
988−{
989− return platform_driver_register(&stu300_i2c_driver);
990−}
991−
992−static void __exit stu300_exit(void)
993−{
994− platform_driver_unregister(&stu300_i2c_driver);
995−}
996−
997−/*
998− * The systems using this bus often have very basic devices such
999− * as regulators on the I2C bus, so this needs to be loaded early.
1000− * Therefore it is registered in the subsys_initcall().
1001− */
1002−subsys_initcall(stu300_init);
1003−module_exit(stu300_exit);
1004−
1005−MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
1006−MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")");
1007−MODULE_LICENSE("GPL");
1008−MODULE_ALIAS("platform:" NAME);
drivers/i2c/busses/i2c-tegra.c+5−4
@@ -550,7 +550,7 @@ static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, · 549 unmodified lines
550550 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
551551 u32 val;
552552
553− if (!i2c_dev->atomic_mode && !in_irq())
553+ if (!i2c_dev->atomic_mode)
554554 return readl_relaxed_poll_timeout(addr, val, !(val & mask),
555555 delay_us, timeout_us);
556556
@@ -1739,9 +1739,10 @@ static int tegra_i2c_probe(struct platform_device *pdev) · 1182 unmodified lines
17391739 /* interrupt will be enabled during of transfer time */
17401740 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
17411741
1742− err = devm_request_irq(i2c_dev->dev, i2c_dev->irq, tegra_i2c_isr,
1743− IRQF_NO_SUSPEND, dev_name(i2c_dev->dev),
1744− i2c_dev);
1742+ err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq,
1743+ NULL, tegra_i2c_isr,
1744+ IRQF_NO_SUSPEND | IRQF_ONESHOT,
1745+ dev_name(i2c_dev->dev), i2c_dev);
17451746 if (err)
17461747 return err;
17471748
drivers/i2c/busses/i2c-zx2967.c+0−602
@@ -1,602 +0,0 @@
1−// SPDX-License-Identifier: GPL-2.0-only
2−/*
3− * Copyright (C) 2017 Sanechips Technology Co., Ltd.
4− * Copyright 2017 Linaro Ltd.
5− *
6− * Author: Baoyou Xie <baoyou.xie@linaro.org>
7− */
8−
9−#include <linux/clk.h>
10−#include <linux/i2c.h>
11−#include <linux/interrupt.h>
12−#include <linux/io.h>
13−#include <linux/module.h>
14−#include <linux/platform_device.h>
15−
16−#define REG_CMD 0x04
17−#define REG_DEVADDR_H 0x0C
18−#define REG_DEVADDR_L 0x10
19−#define REG_CLK_DIV_FS 0x14
20−#define REG_CLK_DIV_HS 0x18
21−#define REG_WRCONF 0x1C
22−#define REG_RDCONF 0x20
23−#define REG_DATA 0x24
24−#define REG_STAT 0x28
25−
26−#define I2C_STOP 0
27−#define I2C_MASTER BIT(0)
28−#define I2C_ADDR_MODE_TEN BIT(1)
29−#define I2C_IRQ_MSK_ENABLE BIT(3)
30−#define I2C_RW_READ BIT(4)
31−#define I2C_CMB_RW_EN BIT(5)
32−#define I2C_START BIT(6)
33−
34−#define I2C_ADDR_LOW_MASK GENMASK(6, 0)
35−#define I2C_ADDR_LOW_SHIFT 0
36−#define I2C_ADDR_HI_MASK GENMASK(2, 0)
37−#define I2C_ADDR_HI_SHIFT 7
38−
39−#define I2C_WFIFO_RESET BIT(7)
40−#define I2C_RFIFO_RESET BIT(7)
41−
42−#define I2C_IRQ_ACK_CLEAR BIT(7)
43−#define I2C_INT_MASK GENMASK(6, 0)
44−
45−#define I2C_TRANS_DONE BIT(0)
46−#define I2C_SR_EDEVICE BIT(1)
47−#define I2C_SR_EDATA BIT(2)
48−
49−#define I2C_FIFO_MAX 16
50−
51−#define I2C_TIMEOUT msecs_to_jiffies(1000)
52−
53−#define DEV(i2c) ((i2c)->adap.dev.parent)
54−
55−struct zx2967_i2c {
56− struct i2c_adapter adap;
57− struct clk *clk;
58− struct completion complete;
59− u32 clk_freq;
60− void __iomem *reg_base;
61− size_t residue;
62− int irq;
63− int msg_rd;
64− u8 *cur_trans;
65− u8 access_cnt;
66− int error;
67−};
68−
69−static void zx2967_i2c_writel(struct zx2967_i2c *i2c,
70− u32 val, unsigned long reg)
71−{
72− writel_relaxed(val, i2c->reg_base + reg);
73−}
74−
75−static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg)
76−{
77− return readl_relaxed(i2c->reg_base + reg);
78−}
79−
80−static void zx2967_i2c_writesb(struct zx2967_i2c *i2c,
81− void *data, unsigned long reg, int len)
82−{
83− writesb(i2c->reg_base + reg, data, len);
84−}
85−
86−static void zx2967_i2c_readsb(struct zx2967_i2c *i2c,
87− void *data, unsigned long reg, int len)
88−{
89− readsb(i2c->reg_base + reg, data, len);
90−}
91−
92−static void zx2967_i2c_start_ctrl(struct zx2967_i2c *i2c)
93−{
94− u32 status;
95− u32 ctl;
96−
97− status = zx2967_i2c_readl(i2c, REG_STAT);
98− status |= I2C_IRQ_ACK_CLEAR;
99− zx2967_i2c_writel(i2c, status, REG_STAT);
100−
101− ctl = zx2967_i2c_readl(i2c, REG_CMD);
102− if (i2c->msg_rd)
103− ctl |= I2C_RW_READ;
104− else
105− ctl &= ~I2C_RW_READ;
106− ctl &= ~I2C_CMB_RW_EN;
107− ctl |= I2C_START;
108− zx2967_i2c_writel(i2c, ctl, REG_CMD);
109−}
110−
111−static void zx2967_i2c_flush_fifos(struct zx2967_i2c *i2c)
112−{
113− u32 offset;
114− u32 val;
115−
116− if (i2c->msg_rd) {
117− offset = REG_RDCONF;
118− val = I2C_RFIFO_RESET;
119− } else {
120− offset = REG_WRCONF;
121− val = I2C_WFIFO_RESET;
122− }
123−
124− val |= zx2967_i2c_readl(i2c, offset);
125− zx2967_i2c_writel(i2c, val, offset);
126−}
127−
128−static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c *i2c, u32 size)
129−{
130− u8 val[I2C_FIFO_MAX] = {0};
131− int i;
132−
133− if (size > I2C_FIFO_MAX) {
134− dev_err(DEV(i2c), "fifo size %d over the max value %d\n",
135− size, I2C_FIFO_MAX);
136− return -EINVAL;
137− }
138−
139− zx2967_i2c_readsb(i2c, val, REG_DATA, size);
140− for (i = 0; i < size; i++) {
141− *i2c->cur_trans++ = val[i];
142− i2c->residue--;
143− }
144−
145− barrier();
146−
147− return 0;
148−}
149−
150−static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c *i2c)
151−{
152− size_t residue = i2c->residue;
153− u8 *buf = i2c->cur_trans;
154−
155− if (residue == 0) {
156− dev_err(DEV(i2c), "residue is %d\n", (int)residue);
157− return -EINVAL;
158− }
159−
160− if (residue <= I2C_FIFO_MAX) {
161− zx2967_i2c_writesb(i2c, buf, REG_DATA, residue);
162−
163− /* Again update before writing to FIFO to make sure isr sees. */
164− i2c->residue = 0;
165− i2c->cur_trans = NULL;
166− } else {
167− zx2967_i2c_writesb(i2c, buf, REG_DATA, I2C_FIFO_MAX);
168− i2c->residue -= I2C_FIFO_MAX;
169− i2c->cur_trans += I2C_FIFO_MAX;
170− }
171−
172− barrier();
173−
174− return 0;
175−}
176−
177−static int zx2967_i2c_reset_hardware(struct zx2967_i2c *i2c)
178−{
179− u32 val;
180− u32 clk_div;
181−
182− val = I2C_MASTER | I2C_IRQ_MSK_ENABLE;
183− zx2967_i2c_writel(i2c, val, REG_CMD);
184−
185− clk_div = clk_get_rate(i2c->clk) / i2c->clk_freq - 1;
186− zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_FS);
187− zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_HS);
188−
189− zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_WRCONF);
190− zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_RDCONF);
191− zx2967_i2c_writel(i2c, 1, REG_RDCONF);
192−
193− zx2967_i2c_flush_fifos(i2c);
194−
195− return 0;
196−}
197−
198−static void zx2967_i2c_isr_clr(struct zx2967_i2c *i2c)
199−{
200− u32 status;
201−
202− status = zx2967_i2c_readl(i2c, REG_STAT);
203− status |= I2C_IRQ_ACK_CLEAR;
204− zx2967_i2c_writel(i2c, status, REG_STAT);
205−}
206−
207−static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id)
208−{
209− u32 status;
210− struct zx2967_i2c *i2c = (struct zx2967_i2c *)dev_id;
211−
212− status = zx2967_i2c_readl(i2c, REG_STAT) & I2C_INT_MASK;
213− zx2967_i2c_isr_clr(i2c);
214−
215− if (status & I2C_SR_EDEVICE)
216− i2c->error = -ENXIO;
217− else if (status & I2C_SR_EDATA)
218− i2c->error = -EIO;
219− else if (status & I2C_TRANS_DONE)
220− i2c->error = 0;
221− else
222− goto done;
223−
224− complete(&i2c->complete);
225−done:
226− return IRQ_HANDLED;
227−}
228−
229−static void zx2967_set_addr(struct zx2967_i2c *i2c, u16 addr)
230−{
231− u16 val;
232−
233− val = (addr >> I2C_ADDR_LOW_SHIFT) & I2C_ADDR_LOW_MASK;
234− zx2967_i2c_writel(i2c, val, REG_DEVADDR_L);
235−
236− val = (addr >> I2C_ADDR_HI_SHIFT) & I2C_ADDR_HI_MASK;
237− zx2967_i2c_writel(i2c, val, REG_DEVADDR_H);
238− if (val)
239− val = zx2967_i2c_readl(i2c, REG_CMD) | I2C_ADDR_MODE_TEN;
240− else
241− val = zx2967_i2c_readl(i2c, REG_CMD) & ~I2C_ADDR_MODE_TEN;
242− zx2967_i2c_writel(i2c, val, REG_CMD);
243−}
244−
245−static int zx2967_i2c_xfer_bytes(struct zx2967_i2c *i2c, u32 bytes)
246−{
247− unsigned long time_left;
248− int rd = i2c->msg_rd;
249− int ret;
250−
251− reinit_completion(&i2c->complete);
252−
253− if (rd) {
254− zx2967_i2c_writel(i2c, bytes - 1, REG_RDCONF);
255− } else {
256− ret = zx2967_i2c_fill_tx_fifo(i2c);
257− if (ret)
258− return ret;
259− }
260−
261− zx2967_i2c_start_ctrl(i2c);
262−
263− time_left = wait_for_completion_timeout(&i2c->complete,
264− I2C_TIMEOUT);
265− if (time_left == 0)
266− return -ETIMEDOUT;
267−
268− if (i2c->error)
269− return i2c->error;
270−
271− return rd ? zx2967_i2c_empty_rx_fifo(i2c, bytes) : 0;
272−}
273−
274−static int zx2967_i2c_xfer_msg(struct zx2967_i2c *i2c,
275− struct i2c_msg *msg)
276−{
277− int ret;
278− int i;
279−
280− zx2967_i2c_flush_fifos(i2c);
281−
282− i2c->cur_trans = msg->buf;
283− i2c->residue = msg->len;
284− i2c->access_cnt = msg->len / I2C_FIFO_MAX;
285− i2c->msg_rd = msg->flags & I2C_M_RD;
286−
287− for (i = 0; i < i2c->access_cnt; i++) {
288− ret = zx2967_i2c_xfer_bytes(i2c, I2C_FIFO_MAX);
289− if (ret)
290− return ret;
291− }
292−
293− if (i2c->residue > 0) {
294− ret = zx2967_i2c_xfer_bytes(i2c, i2c->residue);
295− if (ret)
296− return ret;
297− }
298−
299− i2c->residue = 0;
300− i2c->access_cnt = 0;
301−
302− return 0;
303−}
304−
305−static int zx2967_i2c_xfer(struct i2c_adapter *adap,
306− struct i2c_msg *msgs, int num)
307−{
308− struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
309− int ret;
310− int i;
311−
312− zx2967_set_addr(i2c, msgs->addr);
313−
314− for (i = 0; i < num; i++) {
315− ret = zx2967_i2c_xfer_msg(i2c, &msgs[i]);
316− if (ret)
317− return ret;
318− }
319−
320− return num;
321−}
322−
323−static void
324−zx2967_smbus_xfer_prepare(struct zx2967_i2c *i2c, u16 addr,
325− char read_write, u8 command, int size,
326− union i2c_smbus_data *data)
327−{
328− u32 val;
329−
330− val = zx2967_i2c_readl(i2c, REG_RDCONF);
331− val |= I2C_RFIFO_RESET;
332− zx2967_i2c_writel(i2c, val, REG_RDCONF);
333− zx2967_set_addr(i2c, addr);
334− val = zx2967_i2c_readl(i2c, REG_CMD);
335− val &= ~I2C_RW_READ;
336− zx2967_i2c_writel(i2c, val, REG_CMD);
337−
338− switch (size) {
339− case I2C_SMBUS_BYTE:
340− zx2967_i2c_writel(i2c, command, REG_DATA);
341− break;
342− case I2C_SMBUS_BYTE_DATA:
343− zx2967_i2c_writel(i2c, command, REG_DATA);
344− if (read_write == I2C_SMBUS_WRITE)
345− zx2967_i2c_writel(i2c, data->byte, REG_DATA);
346− break;
347− case I2C_SMBUS_WORD_DATA:
348− zx2967_i2c_writel(i2c, command, REG_DATA);
349− if (read_write == I2C_SMBUS_WRITE) {
350− zx2967_i2c_writel(i2c, (data->word >> 8), REG_DATA);
351− zx2967_i2c_writel(i2c, (data->word & 0xff),
352− REG_DATA);
353− }
354− break;
355− }
356−}
357−
358−static int zx2967_smbus_xfer_read(struct zx2967_i2c *i2c, int size,
359− union i2c_smbus_data *data)
360−{
361− unsigned long time_left;
362− u8 buf[2];
363− u32 val;
364−
365− reinit_completion(&i2c->complete);
366−
367− val = zx2967_i2c_readl(i2c, REG_CMD);
368− val |= I2C_CMB_RW_EN;
369− zx2967_i2c_writel(i2c, val, REG_CMD);
370−
371− val = zx2967_i2c_readl(i2c, REG_CMD);
372− val |= I2C_START;
373− zx2967_i2c_writel(i2c, val, REG_CMD);
374−
375− time_left = wait_for_completion_timeout(&i2c->complete,
376− I2C_TIMEOUT);
377− if (time_left == 0)
378− return -ETIMEDOUT;
379−
380− if (i2c->error)
381− return i2c->error;
382−
383− switch (size) {
384− case I2C_SMBUS_BYTE:
385− case I2C_SMBUS_BYTE_DATA:
386− val = zx2967_i2c_readl(i2c, REG_DATA);
387− data->byte = val;
388− break;
389− case I2C_SMBUS_WORD_DATA:
390− case I2C_SMBUS_PROC_CALL:
391− buf[0] = zx2967_i2c_readl(i2c, REG_DATA);
392− buf[1] = zx2967_i2c_readl(i2c, REG_DATA);
393− data->word = (buf[0] << 8) | buf[1];
394− break;
395− default:
396− return -EOPNOTSUPP;
397− }
398−
399− return 0;
400−}
401−
402−static int zx2967_smbus_xfer_write(struct zx2967_i2c *i2c)
403−{
404− unsigned long time_left;
405− u32 val;
406−
407− reinit_completion(&i2c->complete);
408− val = zx2967_i2c_readl(i2c, REG_CMD);
409− val |= I2C_START;
410− zx2967_i2c_writel(i2c, val, REG_CMD);
411−
412− time_left = wait_for_completion_timeout(&i2c->complete,
413− I2C_TIMEOUT);
414− if (time_left == 0)
415− return -ETIMEDOUT;
416−
417− if (i2c->error)
418− return i2c->error;
419−
420− return 0;
421−}
422−
423−static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr,
424− unsigned short flags, char read_write,
425− u8 command, int size, union i2c_smbus_data *data)
426−{
427− struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
428−
429− if (size == I2C_SMBUS_QUICK)
430− read_write = I2C_SMBUS_WRITE;
431−
432− switch (size) {
433− case I2C_SMBUS_QUICK:
434− case I2C_SMBUS_BYTE:
435− case I2C_SMBUS_BYTE_DATA:
436− case I2C_SMBUS_WORD_DATA:
437− zx2967_smbus_xfer_prepare(i2c, addr, read_write,
438− command, size, data);
439− break;
440− default:
441− return -EOPNOTSUPP;
442− }
443−
444− if (read_write == I2C_SMBUS_READ)
445− return zx2967_smbus_xfer_read(i2c, size, data);
446−
447− return zx2967_smbus_xfer_write(i2c);
448−}
449−
450−static u32 zx2967_i2c_func(struct i2c_adapter *adap)
451−{
452− return I2C_FUNC_I2C |
453− I2C_FUNC_SMBUS_QUICK |
454− I2C_FUNC_SMBUS_BYTE |
455− I2C_FUNC_SMBUS_BYTE_DATA |
456− I2C_FUNC_SMBUS_WORD_DATA |
457− I2C_FUNC_SMBUS_BLOCK_DATA |
458− I2C_FUNC_SMBUS_PROC_CALL |
459− I2C_FUNC_SMBUS_I2C_BLOCK;
460−}
461−
462−static int __maybe_unused zx2967_i2c_suspend(struct device *dev)
463−{
464− struct zx2967_i2c *i2c = dev_get_drvdata(dev);
465−
466− i2c_mark_adapter_suspended(&i2c->adap);
467− clk_disable_unprepare(i2c->clk);
468−
469− return 0;
470−}
471−
472−static int __maybe_unused zx2967_i2c_resume(struct device *dev)
473−{
474− struct zx2967_i2c *i2c = dev_get_drvdata(dev);
475−
476− clk_prepare_enable(i2c->clk);
477− i2c_mark_adapter_resumed(&i2c->adap);
478−
479− return 0;
480−}
481−
482−static SIMPLE_DEV_PM_OPS(zx2967_i2c_dev_pm_ops,
483− zx2967_i2c_suspend, zx2967_i2c_resume);
484−
485−static const struct i2c_algorithm zx2967_i2c_algo = {
486− .master_xfer = zx2967_i2c_xfer,
487− .smbus_xfer = zx2967_smbus_xfer,
488− .functionality = zx2967_i2c_func,
489−};
490−
491−static const struct i2c_adapter_quirks zx2967_i2c_quirks = {
492− .flags = I2C_AQ_NO_ZERO_LEN,
493−};
494−
495−static const struct of_device_id zx2967_i2c_of_match[] = {
496− { .compatible = "zte,zx296718-i2c", },
497− { },
498−};
499−MODULE_DEVICE_TABLE(of, zx2967_i2c_of_match);
500−
501−static int zx2967_i2c_probe(struct platform_device *pdev)
502−{
503− struct zx2967_i2c *i2c;
504− void __iomem *reg_base;
505− struct clk *clk;
506− int ret;
507−
508− i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
509− if (!i2c)
510− return -ENOMEM;
511−
512− reg_base = devm_platform_ioremap_resource(pdev, 0);
513− if (IS_ERR(reg_base))
514− return PTR_ERR(reg_base);
515−
516− clk = devm_clk_get(&pdev->dev, NULL);
517− if (IS_ERR(clk)) {
518− dev_err(&pdev->dev, "missing controller clock");
519− return PTR_ERR(clk);
520− }
521−
522− ret = clk_prepare_enable(clk);
523− if (ret) {
524− dev_err(&pdev->dev, "failed to enable i2c_clk\n");
525− return ret;
526− }
527−
528− ret = device_property_read_u32(&pdev->dev, "clock-frequency",
529− &i2c->clk_freq);
530− if (ret) {
531− dev_err(&pdev->dev, "missing clock-frequency");
532− return ret;
533− }
534−
535− ret = platform_get_irq(pdev, 0);
536− if (ret < 0)
537− return ret;
538−
539− i2c->irq = ret;
540− i2c->reg_base = reg_base;
541− i2c->clk = clk;
542−
543− init_completion(&i2c->complete);
544− platform_set_drvdata(pdev, i2c);
545−
546− ret = zx2967_i2c_reset_hardware(i2c);
547− if (ret) {
548− dev_err(&pdev->dev, "failed to initialize i2c controller\n");
549− goto err_clk_unprepare;
550− }
551−
552− ret = devm_request_irq(&pdev->dev, i2c->irq,
553− zx2967_i2c_isr, 0, dev_name(&pdev->dev), i2c);
554− if (ret) {
555− dev_err(&pdev->dev, "failed to request irq %i\n", i2c->irq);
556− goto err_clk_unprepare;
557− }
558−
559− i2c_set_adapdata(&i2c->adap, i2c);
560− strlcpy(i2c->adap.name, "zx2967 i2c adapter",
561− sizeof(i2c->adap.name));
562− i2c->adap.algo = &zx2967_i2c_algo;
563− i2c->adap.quirks = &zx2967_i2c_quirks;
564− i2c->adap.nr = pdev->id;
565− i2c->adap.dev.parent = &pdev->dev;
566− i2c->adap.dev.of_node = pdev->dev.of_node;
567−
568− ret = i2c_add_numbered_adapter(&i2c->adap);
569− if (ret)
570− goto err_clk_unprepare;
571−
572− return 0;
573−
574−err_clk_unprepare:
575− clk_disable_unprepare(i2c->clk);
576− return ret;
577−}
578−
579−static int zx2967_i2c_remove(struct platform_device *pdev)
580−{
581− struct zx2967_i2c *i2c = platform_get_drvdata(pdev);
582−
583− i2c_del_adapter(&i2c->adap);
584− clk_disable_unprepare(i2c->clk);
585−
586− return 0;
587−}
588−
589−static struct platform_driver zx2967_i2c_driver = {
590− .probe = zx2967_i2c_probe,
591− .remove = zx2967_i2c_remove,
592− .driver = {
593− .name = "zx2967_i2c",
594− .of_match_table = zx2967_i2c_of_match,
595− .pm = &zx2967_i2c_dev_pm_ops,
596− },
597−};
598−module_platform_driver(zx2967_i2c_driver);
599−
600−MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
601−MODULE_DESCRIPTION("ZTE ZX2967 I2C Bus Controller driver");
602−MODULE_LICENSE("GPL v2");
drivers/i2c/i2c-core-acpi.c+1−5
@@ -225,12 +225,8 @@ static void i2c_acpi_register_device(struct i2c_adapter *adapter, · 224 unmodified lines
225225 adev->power.flags.ignore_parent = true;
226226 acpi_device_set_enumerated(adev);
227227
228− if (IS_ERR(i2c_new_client_device(adapter, info))) {
228+ if (IS_ERR(i2c_new_client_device(adapter, info)))
229229 adev->power.flags.ignore_parent = false;
230− dev_err(&adapter->dev,
231− "failed to add I2C device %s from ACPI\n",
232− dev_name(&adev->dev));
233− }
234230 }
235231
236232 static acpi_status i2c_acpi_add_device(acpi_handle handle, u32 level,
drivers/i2c/i2c-core-smbus.c+20−26
@@ -323,8 +323,7 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 322 unmodified lines
323323 */
324324 unsigned char msgbuf0[I2C_SMBUS_BLOCK_MAX+3];
325325 unsigned char msgbuf1[I2C_SMBUS_BLOCK_MAX+2];
326− int num = read_write == I2C_SMBUS_READ ? 2 : 1;
327− int i;
326+ int nmsgs = read_write == I2C_SMBUS_READ ? 2 : 1;
328327 u8 partial_pec = 0;
329328 int status;
330329 struct i2c_msg msg[2] = {
@@ -340,6 +339,8 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 9 unmodified lines
340339 .buf = msgbuf1,
341340 },
342341 };
342+ bool wants_pec = ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK
343+ && size != I2C_SMBUS_I2C_BLOCK_DATA);
343344
344345 msgbuf0[0] = command;
345346 switch (size) {
@@ -348,13 +349,13 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 2 unmodified lines
348349 /* Special case: The read/write field is used as data */
349350 msg[0].flags = flags | (read_write == I2C_SMBUS_READ ?
350351 I2C_M_RD : 0);
351− num = 1;
352+ nmsgs = 1;
352353 break;
353354 case I2C_SMBUS_BYTE:
354355 if (read_write == I2C_SMBUS_READ) {
355356 /* Special case: only a read! */
356357 msg[0].flags = I2C_M_RD | flags;
357− num = 1;
358+ nmsgs = 1;
358359 }
359360 break;
360361 case I2C_SMBUS_BYTE_DATA:
@@ -375,7 +376,7 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 14 unmodified lines
375376 }
376377 break;
377378 case I2C_SMBUS_PROC_CALL:
378− num = 2; /* Special case */
379+ nmsgs = 2; /* Special case */
379380 read_write = I2C_SMBUS_READ;
380381 msg[0].len = 3;
381382 msg[1].len = 2;
@@ -398,12 +399,11 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 16 unmodified lines
398399 }
399400
400401 i2c_smbus_try_get_dmabuf(&msg[0], command);
401− for (i = 1; i < msg[0].len; i++)
402− msg[0].buf[i] = data->block[i - 1];
402+ memcpy(msg[0].buf + 1, data->block, msg[0].len - 1);
403403 }
404404 break;
405405 case I2C_SMBUS_BLOCK_PROC_CALL:
406− num = 2; /* Another special case */
406+ nmsgs = 2; /* Another special case */
407407 read_write = I2C_SMBUS_READ;
408408 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) {
409409 dev_err(&adapter->dev,
@@ -414,8 +414,7 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 4 unmodified lines
414414
415415 msg[0].len = data->block[0] + 2;
416416 i2c_smbus_try_get_dmabuf(&msg[0], command);
417− for (i = 1; i < msg[0].len; i++)
418− msg[0].buf[i] = data->block[i - 1];
417+ memcpy(msg[0].buf + 1, data->block, msg[0].len - 1);
419418
420419 msg[1].flags |= I2C_M_RECV_LEN;
421420 msg[1].len = 1; /* block length will be added by
@@ -437,8 +436,7 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 15 unmodified lines
437436 msg[0].len = data->block[0] + 1;
438437
439438 i2c_smbus_try_get_dmabuf(&msg[0], command);
440− for (i = 1; i <= data->block[0]; i++)
441− msg[0].buf[i] = data->block[i];
439+ memcpy(msg[0].buf + 1, data->block + 1, data->block[0]);
442440 }
443441 break;
444442 default:
@@ -446,33 +444,31 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 1 unmodified line
446444 return -EOPNOTSUPP;
447445 }
448446
449− i = ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK
450− && size != I2C_SMBUS_I2C_BLOCK_DATA);
451− if (i) {
447+ if (wants_pec) {
452448 /* Compute PEC if first message is a write */
453449 if (!(msg[0].flags & I2C_M_RD)) {
454− if (num == 1) /* Write only */
450+ if (nmsgs == 1) /* Write only */
455451 i2c_smbus_add_pec(&msg[0]);
456452 else /* Write followed by read */
457453 partial_pec = i2c_smbus_msg_pec(0, &msg[0]);
458454 }
459455 /* Ask for PEC if last message is a read */
460− if (msg[num-1].flags & I2C_M_RD)
461− msg[num-1].len++;
456+ if (msg[nmsgs - 1].flags & I2C_M_RD)
457+ msg[nmsgs - 1].len++;
462458 }
463459
464− status = __i2c_transfer(adapter, msg, num);
460+ status = __i2c_transfer(adapter, msg, nmsgs);
465461 if (status < 0)
466462 goto cleanup;
467− if (status != num) {
463+ if (status != nmsgs) {
468464 status = -EIO;
469465 goto cleanup;
470466 }
471467 status = 0;
472468
473469 /* Check PEC if last message is a read */
474− if (i && (msg[num-1].flags & I2C_M_RD)) {
475− status = i2c_smbus_check_pec(partial_pec, &msg[num-1]);
470+ if (wants_pec && (msg[nmsgs - 1].flags & I2C_M_RD)) {
471+ status = i2c_smbus_check_pec(partial_pec, &msg[nmsgs - 1]);
476472 if (status < 0)
477473 goto cleanup;
478474 }
@@ -490,8 +486,7 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 11 unmodified lines
490486 data->word = msgbuf1[0] | (msgbuf1[1] << 8);
491487 break;
492488 case I2C_SMBUS_I2C_BLOCK_DATA:
493− for (i = 0; i < data->block[0]; i++)
494− data->block[i + 1] = msg[1].buf[i];
489+ memcpy(data->block + 1, msg[1].buf, data->block[0]);
495490 break;
496491 case I2C_SMBUS_BLOCK_DATA:
497492 case I2C_SMBUS_BLOCK_PROC_CALL:
@@ -502,8 +497,7 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter *adapter, u16 addr, · 4 unmodified lines
502497 status = -EPROTO;
503498 goto cleanup;
504499 }
505− for (i = 0; i < msg[1].buf[0] + 1; i++)
506− data->block[i] = msg[1].buf[i];
500+ memcpy(data->block, msg[1].buf, msg[1].buf[0] + 1);
507501 break;
508502 }
509503
drivers/i2c/i2c-slave-testunit.c+10−2
@@ -19,6 +19,7 @@ · 18 unmodified lines
1919 enum testunit_cmds {
2020 TU_CMD_READ_BYTES = 1, /* save 0 for ABORT, RESET or similar */
2121 TU_CMD_HOST_NOTIFY,
22+ TU_CMD_SMBUS_BLOCK_PROC_CALL,
2223 TU_NUM_CMDS
2324 };
2425
@@ -88,6 +89,8 @@ static int i2c_slave_testunit_slave_cb(struct i2c_client *client, · 63 unmodified lines
8889 enum i2c_slave_event event, u8 *val)
8990 {
9091 struct testunit_data *tu = i2c_get_clientdata(client);
92+ bool is_proc_call = tu->reg_idx == 3 && tu->regs[TU_REG_DATAL] == 1 &&
93+ tu->regs[TU_REG_CMD] == TU_CMD_SMBUS_BLOCK_PROC_CALL;
9194 int ret = 0;
9295
9396 switch (event) {
@@ -118,12 +121,17 @@ static int i2c_slave_testunit_slave_cb(struct i2c_client *client, · 24 unmodified lines
118121 fallthrough;
119122
120123 case I2C_SLAVE_WRITE_REQUESTED:
124+ memset(tu->regs, 0, TU_NUM_REGS);
121125 tu->reg_idx = 0;
122126 break;
123127
124− case I2C_SLAVE_READ_REQUESTED:
125128 case I2C_SLAVE_READ_PROCESSED:
126− *val = TU_CUR_VERSION;
129+ if (is_proc_call && tu->regs[TU_REG_DATAH])
130+ tu->regs[TU_REG_DATAH]--;
131+ fallthrough;
132+
133+ case I2C_SLAVE_READ_REQUESTED:
134+ *val = is_proc_call ? tu->regs[TU_REG_DATAH] : TU_CUR_VERSION;
127135 break;
128136 }
129137
drivers/i2c/i2c-stub.c+0−1
@@ -7,7 +7,6 @@ · 6 unmodified lines
77
88 */
99
10−#define DEBUG 1
1110 #define pr_fmt(fmt) "i2c-stub: " fmt
1211
1312 #include <linux/errno.h>
drivers/i2c/muxes/i2c-mux-gpio.c+82−30
@@ -49,60 +49,112 @@ static int i2c_mux_gpio_deselect(struct i2c_mux_core *muxc, u32 chan) · 48 unmodified lines
4949 return 0;
5050 }
5151
52−#ifdef CONFIG_OF
53−static int i2c_mux_gpio_probe_dt(struct gpiomux *mux,
54− struct platform_device *pdev)
52+#ifdef CONFIG_ACPI
53+
54+static int i2c_mux_gpio_get_acpi_adr(struct device *dev,
55+ struct fwnode_handle *fwdev,
56+ unsigned int *adr)
57+
58+{
59+ unsigned long long adr64;
60+ acpi_status status;
61+
62+ status = acpi_evaluate_integer(ACPI_HANDLE_FWNODE(fwdev),
63+ METHOD_NAME__ADR,
64+ NULL, &adr64);
65+
66+ if (!ACPI_SUCCESS(status)) {
67+ dev_err(dev, "Cannot get address\n");
68+ return -EINVAL;
69+ }
70+
71+ *adr = adr64;
72+ if (*adr != adr64) {
73+ dev_err(dev, "Address out of range\n");
74+ return -ERANGE;
75+ }
76+
77+ return 0;
78+}
79+
80+#else
81+
82+static int i2c_mux_gpio_get_acpi_adr(struct device *dev,
83+ struct fwnode_handle *fwdev,
84+ unsigned int *adr)
85+{
86+ return -EINVAL;
87+}
88+
89+#endif
90+
91+static int i2c_mux_gpio_probe_fw(struct gpiomux *mux,
92+ struct platform_device *pdev)
5593 {
56− struct device_node *np = pdev->dev.of_node;
57− struct device_node *adapter_np, *child;
58− struct i2c_adapter *adapter;
94+ struct device *dev = &pdev->dev;
95+ struct device_node *np = dev->of_node;
96+ struct device_node *adapter_np;
97+ struct i2c_adapter *adapter = NULL;
98+ struct fwnode_handle *child;
5999 unsigned *values;
60− int i = 0;
100+ int rc, i = 0;
101+
102+ if (is_of_node(dev->fwnode)) {
103+ if (!np)
104+ return -ENODEV;
61105
62− if (!np)
63− return -ENODEV;
106+ adapter_np = of_parse_phandle(np, "i2c-parent", 0);
107+ if (!adapter_np) {
108+ dev_err(&pdev->dev, "Cannot parse i2c-parent\n");
109+ return -ENODEV;
110+ }
111+ adapter = of_find_i2c_adapter_by_node(adapter_np);
112+ of_node_put(adapter_np);
113+
114+ } else if (is_acpi_node(dev->fwnode)) {
115+ /*
116+ * In ACPI land the mux should be a direct child of the i2c
117+ * bus it muxes.
118+ */
119+ acpi_handle dev_handle = ACPI_HANDLE(dev->parent);
64120
65− adapter_np = of_parse_phandle(np, "i2c-parent", 0);
66− if (!adapter_np) {
67− dev_err(&pdev->dev, "Cannot parse i2c-parent\n");
68− return -ENODEV;
121+ adapter = i2c_acpi_find_adapter_by_handle(dev_handle);
69122 }
70− adapter = of_find_i2c_adapter_by_node(adapter_np);
71− of_node_put(adapter_np);
123+
72124 if (!adapter)
73125 return -EPROBE_DEFER;
74126
75127 mux->data.parent = i2c_adapter_id(adapter);
76128 put_device(&adapter->dev);
77129
78− mux->data.n_values = of_get_child_count(np);
79−
80− values = devm_kcalloc(&pdev->dev,
130+ mux->data.n_values = device_get_child_node_count(dev);
131+ values = devm_kcalloc(dev,
81132 mux->data.n_values, sizeof(*mux->data.values),
82133 GFP_KERNEL);
83134 if (!values) {
84− dev_err(&pdev->dev, "Cannot allocate values array");
135+ dev_err(dev, "Cannot allocate values array");
85136 return -ENOMEM;
86137 }
87138
88− for_each_child_of_node(np, child) {
89− of_property_read_u32(child, "reg", values + i);
139+ device_for_each_child_node(dev, child) {
140+ if (is_of_node(child)) {
141+ fwnode_property_read_u32(child, "reg", values + i);
142+
143+ } else if (is_acpi_node(child)) {
144+ rc = i2c_mux_gpio_get_acpi_adr(dev, child, values + i);
145+ if (rc)
146+ return rc;
147+ }
148+
90149 i++;
91150 }
92151 mux->data.values = values;
93152
94− if (of_property_read_u32(np, "idle-state", &mux->data.idle))
153+ if (fwnode_property_read_u32(dev->fwnode, "idle-state", &mux->data.idle))
95154 mux->data.idle = I2C_MUX_GPIO_NO_IDLE;
96155
97156 return 0;
98157 }
99−#else
100−static int i2c_mux_gpio_probe_dt(struct gpiomux *mux,
101− struct platform_device *pdev)
102−{
103− return 0;
104−}
105−#endif
106158
107159 static int i2c_mux_gpio_probe(struct platform_device *pdev)
108160 {
@@ -118,7 +170,7 @@ static int i2c_mux_gpio_probe(struct platform_device *pdev) · 9 unmodified lines
118170 return -ENOMEM;
119171
120172 if (!dev_get_platdata(&pdev->dev)) {
121− ret = i2c_mux_gpio_probe_dt(mux, pdev);
173+ ret = i2c_mux_gpio_probe_fw(mux, pdev);
122174 if (ret < 0)
123175 return ret;
124176 } else {
drivers/i2c/muxes/i2c-mux-mlxcpld.c+78−85
@@ -1,35 +1,8 @@
1+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
12 /*
2− * drivers/i2c/muxes/i2c-mux-mlxcpld.c
3− * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
4− * Copyright (c) 2016 Michael Shych <michaels@mellanox.com>
3+ * Mellanox i2c mux driver
54 *
6− * Redistribution and use in source and binary forms, with or without
7− * modification, are permitted provided that the following conditions are met:
8− *
9− * 1. Redistributions of source code must retain the above copyright
10− * notice, this list of conditions and the following disclaimer.
11− * 2. Redistributions in binary form must reproduce the above copyright
12− * notice, this list of conditions and the following disclaimer in the
13− * documentation and/or other materials provided with the distribution.
14− * 3. Neither the names of the copyright holders nor the names of its
15− * contributors may be used to endorse or promote products derived from
16− * this software without specific prior written permission.
17− *
18− * Alternatively, this software may be distributed under the terms of the
19− * GNU General Public License ("GPL") version 2 as published by the Free
20− * Software Foundation.
21− *
22− * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23− * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24− * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25− * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26− * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27− * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28− * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29− * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30− * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31− * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32− * POSSIBILITY OF SUCH DAMAGE.
5+ * Copyright (C) 2016-2020 Mellanox Technologies
336 */
347
358 #include <linux/device.h>
@@ -38,19 +11,19 @@ · 2 unmodified lines
3811 #include <linux/io.h>
3912 #include <linux/init.h>
4013 #include <linux/module.h>
41−#include <linux/platform_data/x86/mlxcpld.h>
14+#include <linux/platform_data/mlxcpld.h>
4215 #include <linux/platform_device.h>
4316 #include <linux/slab.h>
4417
45−#define CPLD_MUX_MAX_NCHANS 8
46−
4718 /* mlxcpld_mux - mux control structure:
48− * @last_chan - last register value
19+ * @last_val - last selected register value or -1 if mux deselected
4920 * @client - I2C device client
21+ * @pdata: platform data
5022 */
5123 struct mlxcpld_mux {
52− u8 last_chan;
24+ int last_val;
5325 struct i2c_client *client;
26+ struct mlxcpld_mux_plat_data pdata;
5427 };
5528
5629 /* MUX logic description.
@@ -81,37 +54,50 @@ struct mlxcpld_mux { · 24 unmodified lines
8154 *
8255 */
8356
84−static const struct i2c_device_id mlxcpld_mux_id[] = {
85− { "mlxcpld_mux_module", 0 },
86− { }
87−};
88−MODULE_DEVICE_TABLE(i2c, mlxcpld_mux_id);
89−
9057 /* Write to mux register. Don't use i2c_transfer() and i2c_smbus_xfer()
9158 * for this as they will try to lock adapter a second time.
9259 */
9360 static int mlxcpld_mux_reg_write(struct i2c_adapter *adap,
94− struct i2c_client *client, u8 val)
61+ struct mlxcpld_mux *mux, u32 val)
9562 {
96− struct mlxcpld_mux_plat_data *pdata = dev_get_platdata(&client->dev);
97− union i2c_smbus_data data = { .byte = val };
98−
99− return __i2c_smbus_xfer(adap, client->addr, client->flags,
100− I2C_SMBUS_WRITE, pdata->sel_reg_addr,
101− I2C_SMBUS_BYTE_DATA, &data);
63+ struct i2c_client *client = mux->client;
64+ union i2c_smbus_data data;
65+ struct i2c_msg msg;
66+ u8 buf[3];
67+
68+ switch (mux->pdata.reg_size) {
69+ case 1:
70+ data.byte = val;
71+ return __i2c_smbus_xfer(adap, client->addr, client->flags,
72+ I2C_SMBUS_WRITE, mux->pdata.sel_reg_addr,
73+ I2C_SMBUS_BYTE_DATA, &data);
74+ case 2:
75+ buf[0] = mux->pdata.sel_reg_addr >> 8;
76+ buf[1] = mux->pdata.sel_reg_addr;
77+ buf[2] = val;
78+ msg.addr = client->addr;
79+ msg.buf = buf;
80+ msg.len = mux->pdata.reg_size + 1;
81+ msg.flags = 0;
82+ return __i2c_transfer(adap, &msg, 1);
83+ default:
84+ return -EINVAL;
85+ }
10286 }
10387
10488 static int mlxcpld_mux_select_chan(struct i2c_mux_core *muxc, u32 chan)
10589 {
106− struct mlxcpld_mux *data = i2c_mux_priv(muxc);
107− struct i2c_client *client = data->client;
108− u8 regval = chan + 1;
90+ struct mlxcpld_mux *mux = i2c_mux_priv(muxc);
91+ u32 regval = chan;
10992 int err = 0;
11093
94+ if (mux->pdata.reg_size == 1)
95+ regval += 1;
96+
11197 /* Only select the channel if its different from the last channel */
112− if (data->last_chan != regval) {
113− err = mlxcpld_mux_reg_write(muxc->parent, client, regval);
114− data->last_chan = err < 0 ? 0 : regval;
98+ if (mux->last_val != regval) {
99+ err = mlxcpld_mux_reg_write(muxc->parent, mux, regval);
100+ mux->last_val = err < 0 ? -1 : regval;
115101 }
116102
117103 return err;
@@ -119,56 +105,64 @@ static int mlxcpld_mux_select_chan(struct i2c_mux_core *muxc, u32 chan) · 1 unmodified line
119105
120106 static int mlxcpld_mux_deselect(struct i2c_mux_core *muxc, u32 chan)
121107 {
122− struct mlxcpld_mux *data = i2c_mux_priv(muxc);
123− struct i2c_client *client = data->client;
108+ struct mlxcpld_mux *mux = i2c_mux_priv(muxc);
124109
125110 /* Deselect active channel */
126− data->last_chan = 0;
111+ mux->last_val = -1;
127112
128− return mlxcpld_mux_reg_write(muxc->parent, client, data->last_chan);
113+ return mlxcpld_mux_reg_write(muxc->parent, mux, 0);
129114 }
130115
131116 /* Probe/reomove functions */
132−static int mlxcpld_mux_probe(struct i2c_client *client,
133− const struct i2c_device_id *id)
117+static int mlxcpld_mux_probe(struct platform_device *pdev)
134118 {
135− struct i2c_adapter *adap = client->adapter;
136− struct mlxcpld_mux_plat_data *pdata = dev_get_platdata(&client->dev);
119+ struct mlxcpld_mux_plat_data *pdata = dev_get_platdata(&pdev->dev);
120+ struct i2c_client *client = to_i2c_client(pdev->dev.parent);
137121 struct i2c_mux_core *muxc;
138− int num, force;
139122 struct mlxcpld_mux *data;
140− int err;
123+ int num, err;
124+ u32 func;
141125
142126 if (!pdata)
143127 return -EINVAL;
144128
145− if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
129+ switch (pdata->reg_size) {
130+ case 1:
131+ func = I2C_FUNC_SMBUS_WRITE_BYTE_DATA;
132+ break;
133+ case 2:
134+ func = I2C_FUNC_I2C;
135+ break;
136+ default:
137+ return -EINVAL;
138+ }
139+
140+ if (!i2c_check_functionality(client->adapter, func))
146141 return -ENODEV;
147142
148− muxc = i2c_mux_alloc(adap, &client->dev, CPLD_MUX_MAX_NCHANS,
143+ muxc = i2c_mux_alloc(client->adapter, &pdev->dev, pdata->num_adaps,
149144 sizeof(*data), 0, mlxcpld_mux_select_chan,
150145 mlxcpld_mux_deselect);
151146 if (!muxc)
152147 return -ENOMEM;
153148
149+ platform_set_drvdata(pdev, muxc);
154150 data = i2c_mux_priv(muxc);
155− i2c_set_clientdata(client, muxc);
156151 data->client = client;
157− data->last_chan = 0; /* force the first selection */
152+ memcpy(&data->pdata, pdata, sizeof(*pdata));
153+ data->last_val = -1; /* force the first selection */
158154
159155 /* Create an adapter for each channel. */
160− for (num = 0; num < CPLD_MUX_MAX_NCHANS; num++) {
161− if (num >= pdata->num_adaps)
162− /* discard unconfigured channels */
163− break;
164−
165− force = pdata->adap_ids[num];
166−
167− err = i2c_mux_add_adapter(muxc, force, num, 0);
156+ for (num = 0; num < pdata->num_adaps; num++) {
157+ err = i2c_mux_add_adapter(muxc, 0, pdata->chan_ids[num], 0);
168158 if (err)
169159 goto virt_reg_failed;
170160 }
171161
162+ /* Notify caller when all channels' adapters are created. */
163+ if (pdata->completion_notify)
164+ pdata->completion_notify(pdata->handle, muxc->parent, muxc->adapter);
165+
172166 return 0;
173167
174168 virt_reg_failed:
@@ -176,24 +170,23 @@ virt_reg_failed: · 1 unmodified line
176170 return err;
177171 }
178172
179−static int mlxcpld_mux_remove(struct i2c_client *client)
173+static int mlxcpld_mux_remove(struct platform_device *pdev)
180174 {
181− struct i2c_mux_core *muxc = i2c_get_clientdata(client);
175+ struct i2c_mux_core *muxc = platform_get_drvdata(pdev);
182176
183177 i2c_mux_del_adapters(muxc);
184178 return 0;
185179 }
186180
187−static struct i2c_driver mlxcpld_mux_driver = {
188− .driver = {
189− .name = "mlxcpld-mux",
181+static struct platform_driver mlxcpld_mux_driver = {
182+ .driver = {
183+ .name = "i2c-mux-mlxcpld",
190184 },
191− .probe = mlxcpld_mux_probe,
192− .remove = mlxcpld_mux_remove,
193− .id_table = mlxcpld_mux_id,
185+ .probe = mlxcpld_mux_probe,
186+ .remove = mlxcpld_mux_remove,
194187 };
195188
196−module_i2c_driver(mlxcpld_mux_driver);
189+module_platform_driver(mlxcpld_mux_driver);
197190
198191 MODULE_AUTHOR("Michael Shych (michaels@mellanox.com)");
199192 MODULE_DESCRIPTION("Mellanox I2C-CPLD-MUX driver");
include/linux/platform_data/mlxcpld.h+31−0
@@ -0,0 +1,31 @@
1+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2+/*
3+ * Mellanox I2C multiplexer support in CPLD
4+ *
5+ * Copyright (C) 2016-2020 Mellanox Technologies
6+ */
7+
8+#ifndef _LINUX_I2C_MLXCPLD_H
9+#define _LINUX_I2C_MLXCPLD_H
10+
11+/* Platform data for the CPLD I2C multiplexers */
12+
13+/* mlxcpld_mux_plat_data - per mux data, used with i2c_register_board_info
14+ * @chan_ids - channels array
15+ * @num_adaps - number of adapters
16+ * @sel_reg_addr - mux select register offset in CPLD space
17+ * @reg_size: register size in bytes
18+ * @handle: handle to be passed by callback
19+ * @completion_notify: callback to notify when all the adapters are created
20+ */
21+struct mlxcpld_mux_plat_data {
22+ int *chan_ids;
23+ int num_adaps;
24+ int sel_reg_addr;
25+ u8 reg_size;
26+ void *handle;
27+ int (*completion_notify)(void *handle, struct i2c_adapter *parent,
28+ struct i2c_adapter *adapters[]);
29+};
30+
31+#endif /* _LINUX_I2C_MLXCPLD_H */
include/linux/platform_data/x86/mlxcpld.h+0−52
@@ -1,52 +0,0 @@
1−/*
2− * mlxcpld.h - Mellanox I2C multiplexer support in CPLD
3− *
4− * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
5− * Copyright (c) 2016 Michael Shych <michaels@mellanox.com>
6− *
7− * Redistribution and use in source and binary forms, with or without
8− * modification, are permitted provided that the following conditions are met:
9− *
10− * 1. Redistributions of source code must retain the above copyright
11− * notice, this list of conditions and the following disclaimer.
12− * 2. Redistributions in binary form must reproduce the above copyright
13− * notice, this list of conditions and the following disclaimer in the
14− * documentation and/or other materials provided with the distribution.
15− * 3. Neither the names of the copyright holders nor the names of its
16− * contributors may be used to endorse or promote products derived from
17− * this software without specific prior written permission.
18− *
19− * Alternatively, this software may be distributed under the terms of the
20− * GNU General Public License ("GPL") version 2 as published by the Free
21− * Software Foundation.
22− *
23− * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24− * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25− * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26− * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27− * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28− * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29− * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30− * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31− * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32− * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33− * POSSIBILITY OF SUCH DAMAGE.
34− */
35−
36−#ifndef _LINUX_I2C_MLXCPLD_H
37−#define _LINUX_I2C_MLXCPLD_H
38−
39−/* Platform data for the CPLD I2C multiplexers */
40−
41−/* mlxcpld_mux_plat_data - per mux data, used with i2c_register_board_info
42− * @adap_ids - adapter array
43− * @num_adaps - number of adapters
44− * @sel_reg_addr - mux select register offset in CPLD space
45− */
46−struct mlxcpld_mux_plat_data {
47− int *adap_ids;
48− int num_adaps;
49− int sel_reg_addr;
50−};
51−
52−#endif /* _LINUX_I2C_MLXCPLD_H */
include/uapi/linux/i2c-dev.h+5−20
@@ -1,25 +1,10 @@
11 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
22 /*
3− i2c-dev.h - i2c-bus driver, char device interface
4−
5− Copyright (C) 1995-97 Simon G. Vogl
6− Copyright (C) 1998-99 Frodo Looijaard <frodol@dds.nl>
7−
8− This program is free software; you can redistribute it and/or modify
9− it under the terms of the GNU General Public License as published by
10− the Free Software Foundation; either version 2 of the License, or
11− (at your option) any later version.
12−
13− This program is distributed in the hope that it will be useful,
14− but WITHOUT ANY WARRANTY; without even the implied warranty of
15− MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16− GNU General Public License for more details.
17−
18− You should have received a copy of the GNU General Public License
19− along with this program; if not, write to the Free Software
20− Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21− MA 02110-1301 USA.
22−*/
3+ * i2c-dev.h - I2C bus char device interface
4+ *
5+ * Copyright (C) 1995-97 Simon G. Vogl
6+ * Copyright (C) 1998-99 Frodo Looijaard <frodol@dds.nl>
7+ */
238
249 #ifndef _UAPI_LINUX_I2C_DEV_H
2510 #define _UAPI_LINUX_I2C_DEV_H
include/uapi/linux/i2c.h+67−61
@@ -1,29 +1,11 @@
11 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2−/* ------------------------------------------------------------------------- */
3−/* */
4−/* i2c.h - definitions for the i2c-bus interface */
5−/* */
6−/* ------------------------------------------------------------------------- */
7−/* Copyright (C) 1995-2000 Simon G. Vogl
8−
9− This program is free software; you can redistribute it and/or modify
10− it under the terms of the GNU General Public License as published by
11− the Free Software Foundation; either version 2 of the License, or
12− (at your option) any later version.
13−
14− This program is distributed in the hope that it will be useful,
15− but WITHOUT ANY WARRANTY; without even the implied warranty of
16− MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17− GNU General Public License for more details.
18−
19− You should have received a copy of the GNU General Public License
20− along with this program; if not, write to the Free Software
21− Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22− MA 02110-1301 USA. */
23−/* ------------------------------------------------------------------------- */
24−
25−/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
26− Frodo Looijaard <frodol@dds.nl> */
2+/*
3+ * i2c.h - definitions for the I2C bus interface
4+ *
5+ * Copyright (C) 1995-2000 Simon G. Vogl
6+ * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
7+ * Frodo Looijaard <frodol@dds.nl>
8+ */
279
2810 #ifndef _UAPI_LINUX_I2C_H
2911 #define _UAPI_LINUX_I2C_H
@@ -32,18 +14,41 @@ · 2 unmodified lines
3214
3315 /**
3416 * struct i2c_msg - an I2C transaction segment beginning with START
35− * @addr: Slave address, either seven or ten bits. When this is a ten
36− * bit address, I2C_M_TEN must be set in @flags and the adapter
37− * must support I2C_FUNC_10BIT_ADDR.
38− * @flags: I2C_M_RD is handled by all adapters. No other flags may be
39− * provided unless the adapter exported the relevant I2C_FUNC_*
40− * flags through i2c_check_functionality().
41− * @len: Number of data bytes in @buf being read from or written to the
42− * I2C slave address. For read transactions where I2C_M_RECV_LEN
43− * is set, the caller guarantees that this buffer can hold up to
44− * 32 bytes in addition to the initial length byte sent by the
45− * slave (plus, if used, the SMBus PEC); and this value will be
46− * incremented by the number of block data bytes received.
17+ *
18+ * @addr: Slave address, either 7 or 10 bits. When this is a 10 bit address,
19+ * %I2C_M_TEN must be set in @flags and the adapter must support
20+ * %I2C_FUNC_10BIT_ADDR.
21+ *
22+ * @flags:
23+ * Supported by all adapters:
24+ * %I2C_M_RD: read data (from slave to master). Guaranteed to be 0x0001!
25+ *
26+ * Optional:
27+ * %I2C_M_DMA_SAFE: the buffer of this message is DMA safe. Makes only sense
28+ * in kernelspace, because userspace buffers are copied anyway
29+ *
30+ * Only if I2C_FUNC_10BIT_ADDR is set:
31+ * %I2C_M_TEN: this is a 10 bit chip address
32+ *
33+ * Only if I2C_FUNC_SMBUS_READ_BLOCK_DATA is set:
34+ * %I2C_M_RECV_LEN: message length will be first received byte
35+ *
36+ * Only if I2C_FUNC_NOSTART is set:
37+ * %I2C_M_NOSTART: skip repeated start sequence
38+
39+ * Only if I2C_FUNC_PROTOCOL_MANGLING is set:
40+ * %I2C_M_NO_RD_ACK: in a read message, master ACK/NACK bit is skipped
41+ * %I2C_M_IGNORE_NAK: treat NACK from client as ACK
42+ * %I2C_M_REV_DIR_ADDR: toggles the Rd/Wr bit
43+ * %I2C_M_STOP: force a STOP condition after the message
44+ *
45+ * @len: Number of data bytes in @buf being read from or written to the I2C
46+ * slave address. For read transactions where %I2C_M_RECV_LEN is set, the
47+ * caller guarantees that this buffer can hold up to %I2C_SMBUS_BLOCK_MAX
48+ * bytes in addition to the initial length byte sent by the slave (plus,
49+ * if used, the SMBus PEC); and this value will be incremented by the number
50+ * of block data bytes received.
51+ *
4752 * @buf: The buffer into which data is read, or from which it's written.
4853 *
4954 * An i2c_msg is the low level representation of one segment of an I2C
@@ -60,40 +65,36 @@ · 10 unmodified lines
6065 * group, it is followed by a STOP. Otherwise it is followed by the next
6166 * @i2c_msg transaction segment, beginning with a (repeated) START.
6267 *
63− * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
68+ * Alternatively, when the adapter supports %I2C_FUNC_PROTOCOL_MANGLING then
6469 * passing certain @flags may have changed those standard protocol behaviors.
6570 * Those flags are only for use with broken/nonconforming slaves, and with
66− * adapters which are known to support the specific mangling options they
67− * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
71+ * adapters which are known to support the specific mangling options they need.
6872 */
6973 struct i2c_msg {
70− __u16 addr; /* slave address */
74+ __u16 addr;
7175 __u16 flags;
72−#define I2C_M_RD 0x0001 /* read data, from slave to master */
73− /* I2C_M_RD is guaranteed to be 0x0001! */
74−#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
75−#define I2C_M_DMA_SAFE 0x0200 /* the buffer of this message is DMA safe */
76− /* makes only sense in kernelspace */
77− /* userspace buffers are copied anyway */
78−#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
79−#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
80−#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
81−#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
82−#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_NOSTART */
83−#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
84− __u16 len; /* msg length */
85− __u8 *buf; /* pointer to msg data */
76+#define I2C_M_RD 0x0001 /* guaranteed to be 0x0001! */
77+#define I2C_M_TEN 0x0010 /* use only if I2C_FUNC_10BIT_ADDR */
78+#define I2C_M_DMA_SAFE 0x0200 /* use only in kernel space */
79+#define I2C_M_RECV_LEN 0x0400 /* use only if I2C_FUNC_SMBUS_READ_BLOCK_DATA */
80+#define I2C_M_NO_RD_ACK 0x0800 /* use only if I2C_FUNC_PROTOCOL_MANGLING */
81+#define I2C_M_IGNORE_NAK 0x1000 /* use only if I2C_FUNC_PROTOCOL_MANGLING */
82+#define I2C_M_REV_DIR_ADDR 0x2000 /* use only if I2C_FUNC_PROTOCOL_MANGLING */
83+#define I2C_M_NOSTART 0x4000 /* use only if I2C_FUNC_NOSTART */
84+#define I2C_M_STOP 0x8000 /* use only if I2C_FUNC_PROTOCOL_MANGLING */
85+ __u16 len;
86+ __u8 *buf;
8687 };
8788
8889 /* To determine what functionality is present */
8990
9091 #define I2C_FUNC_I2C 0x00000001
91−#define I2C_FUNC_10BIT_ADDR 0x00000002
92−#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_IGNORE_NAK etc. */
92+#define I2C_FUNC_10BIT_ADDR 0x00000002 /* required for I2C_M_TEN */
93+#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* required for I2C_M_IGNORE_NAK etc. */
9394 #define I2C_FUNC_SMBUS_PEC 0x00000008
94−#define I2C_FUNC_NOSTART 0x00000010 /* I2C_M_NOSTART */
95+#define I2C_FUNC_NOSTART 0x00000010 /* required for I2C_M_NOSTART */
9596 #define I2C_FUNC_SLAVE 0x00000020
96−#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */
97+#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 or later */
9798 #define I2C_FUNC_SMBUS_QUICK 0x00010000
9899 #define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
99100 #define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000
@@ -102,11 +103,11 @@ struct i2c_msg { · 2 unmodified lines
102103 #define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000
103104 #define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000
104105 #define I2C_FUNC_SMBUS_PROC_CALL 0x00800000
105−#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000
106+#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000 /* required for I2C_M_RECV_LEN */
106107 #define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
107108 #define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */
108109 #define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */
109−#define I2C_FUNC_SMBUS_HOST_NOTIFY 0x10000000
110+#define I2C_FUNC_SMBUS_HOST_NOTIFY 0x10000000 /* SMBus 2.0 or later */
110111
111112 #define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
112113 I2C_FUNC_SMBUS_WRITE_BYTE)
@@ -128,6 +129,11 @@ struct i2c_msg { · 15 unmodified lines
128129 I2C_FUNC_SMBUS_I2C_BLOCK | \
129130 I2C_FUNC_SMBUS_PEC)
130131
132+/* if I2C_M_RECV_LEN is also supported */
133+#define I2C_FUNC_SMBUS_EMUL_ALL (I2C_FUNC_SMBUS_EMUL | \
134+ I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
135+ I2C_FUNC_SMBUS_BLOCK_PROC_CALL)
136+
131137 /*
132138 * Data for SMBus Messages
133139 */

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