The 64 bit value read from MSR_ARCH_PERFMON_FIXED_CTR_CTRL is being bit-wise masked with the value (0x03 << i*4). However, the shifted value is evaluated using 32 bit arithmetic, so will UB when i > 8. Fix this by making 0x03 a ULL so that the shift is performed using 64 bit arithmetic. This makes the arithmetic internally consistent and preparers for the day when hardware provides 8<num_fixed_counters<16.
Unified · Split
| @@ -278,7 +278,7 @@ bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed) · 277 unmodified lines | |||
| 278 | for (i = 0; i < num_counters_fixed; i++) { | 278 | for (i = 0; i < num_counters_fixed; i++) { |
| 279 | if (fixed_counter_disabled(i, pmu)) | 279 | if (fixed_counter_disabled(i, pmu)) |
| 280 | continue; | 280 | continue; |
| 281 | if (val & (0x03 << i*4)) { | 281 | if (val & (0x03ULL << i*4)) { |
| 282 | bios_fail = 1; | 282 | bios_fail = 1; |
| 283 | val_fail = val; | 283 | val_fail = val; |
| 284 | reg_fail = reg; | 284 | reg_fail = reg; |