History

Merge tag 'mlx5-next-2020-12-02' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

Saeed Mahameed says: ==================== mlx5-next-2020-12-02 Low level mlx5 updates required by both netdev and rdma trees. * tag 'mlx5-next-2020-12-02' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux: net/mlx5: Treat host PF vport as other (non eswitch manager) vport net/mlx5: Enable host PF HCA after eswitch is initialized net/mlx5: Rename peer_pf to host_pf net/mlx5: Make API mlx5_core_is_ecpf accept const pointer net/mlx5: Export steering related functions net/mlx5: Expose other function ifc bits net/mlx5: Expose IP-in-IP TX and RX capability bits net/mlx5: Update the hardware interface definition for vhca state net/mlx5: Update the list of the PCI supported devices net/mlx5: Avoid exposing driver internal command helpers net/mlx5: Add ts_cqe_to_dest_cqn related bits net/mlx5: Add misc4 to mlx5_ifc_fte_match_param_bits net/mlx5: Check dr mask size against mlx5_match_param size net/mlx5: Add sampler destination type net/mlx5: Add sample offload hardware bits and structures ====================

Jakub Kicinski committed 5 years ago

Commit 32e41702 parents 6ec1dfb 617b86020 files · +250 −104Browse files

Unified · Split

20 files
  1. drivers/net/ethernet/mellanox/mlx5/core/cmd.c +0 −3
  2. drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c +3 −0
  3. drivers/net/ethernet/mellanox/mlx5/core/ecpf.c +54 −22
  4. drivers/net/ethernet/mellanox/mlx5/core/ecpf.h +3 −0
  5. drivers/net/ethernet/mellanox/mlx5/core/esw/acl/helper.c +4 −1
  6. drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +28 −1
  7. drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +27 −30
  8. drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +7 −10
  9. drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +1 −1
  10. drivers/net/ethernet/mellanox/mlx5/core/main.c +10 −9
  11. drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +4 −0
  12. drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c +6 −6
  13. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c +1 −1
  14. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c +1 −2
  15. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +1 −0
  16. include/linux/mlx5/device.h +8 −0
  17. include/linux/mlx5/driver.h +2 −6
  18. include/linux/mlx5/fs.h +3 −3
  19. include/linux/mlx5/mlx5_ifc.h +86 −8
  20. include/uapi/rdma/mlx5_user_ioctl_cmds.h +1 −1
drivers/net/ethernet/mellanox/mlx5/core/cmd.c+0−3
@@ -2142,7 +2142,6 @@ dma_pool_err: · 2141 unmodified lines
2142 kvfree(cmd->stats);2142 kvfree(cmd->stats);
2143 return err;2143 return err;
2144}2144}
2145EXPORT_SYMBOL(mlx5_cmd_init);
2146 2145
2147void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)2146void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2148{2147{
@@ -2155,11 +2154,9 @@ void mlx5_cmd_cleanup(struct mlx5_core_dev *dev) · 6 unmodified lines
2155 dma_pool_destroy(cmd->pool);2154 dma_pool_destroy(cmd->pool);
2156 kvfree(cmd->stats);2155 kvfree(cmd->stats);
2157}2156}
2158EXPORT_SYMBOL(mlx5_cmd_cleanup);
2159 2157
2160void mlx5_cmd_set_state(struct mlx5_core_dev *dev,2158void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
2161 enum mlx5_cmdif_state cmdif_state)2159 enum mlx5_cmdif_state cmdif_state)
2162{2160{
2163 dev->cmd.state = cmdif_state;2161 dev->cmd.state = cmdif_state;
2164}2162}
2165EXPORT_SYMBOL(mlx5_cmd_set_state);
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c+3−0
@@ -247,6 +247,9 @@ const char *parse_fs_dst(struct trace_seq *p, · 246 unmodified lines
247 case MLX5_FLOW_DESTINATION_TYPE_TIR:247 case MLX5_FLOW_DESTINATION_TYPE_TIR:
248 trace_seq_printf(p, "tir=%u\n", dst->tir_num);248 trace_seq_printf(p, "tir=%u\n", dst->tir_num);
249 break;249 break;
250 case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER:
251 trace_seq_printf(p, "sampler_id=%u\n", dst->sampler_id);
252 break;
250 case MLX5_FLOW_DESTINATION_TYPE_COUNTER:253 case MLX5_FLOW_DESTINATION_TYPE_COUNTER:
251 trace_seq_printf(p, "counter_id=%u\n", counter_id);254 trace_seq_printf(p, "counter_id=%u\n", counter_id);
252 break;255 break;
drivers/net/ethernet/mellanox/mlx5/core/ecpf.c+54−22
@@ -8,37 +8,66 @@ bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev) · 7 unmodified lines
8 return (ioread32be(&dev->iseg->initializing) >> MLX5_ECPU_BIT_NUM) & 1;8 return (ioread32be(&dev->iseg->initializing) >> MLX5_ECPU_BIT_NUM) & 1;
9}9}
10 10
11static int mlx5_peer_pf_init(struct mlx5_core_dev *dev)11static bool mlx5_ecpf_esw_admins_host_pf(const struct mlx5_core_dev *dev)
12{12{
13 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};13 /* In separate host mode, PF enables itself.
14 int err;14 * When ECPF is eswitch manager, eswitch enables host PF after
15 * eswitch is setup.
16 */
17 return mlx5_core_is_ecpf_esw_manager(dev);
18}
19
20int mlx5_cmd_host_pf_enable_hca(struct mlx5_core_dev *dev)
21{
22 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {};
23 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
15 24
16 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);25 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
17 err = mlx5_cmd_exec_in(dev, enable_hca, in);26 MLX5_SET(enable_hca_in, in, function_id, 0);
27 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 0);
28 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
29}
30
31int mlx5_cmd_host_pf_disable_hca(struct mlx5_core_dev *dev)
32{
33 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {};
34 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
35
36 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
37 MLX5_SET(disable_hca_in, in, function_id, 0);
38 MLX5_SET(disable_hca_in, in, embedded_cpu_function, 0);
39 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
40}
41
42static int mlx5_host_pf_init(struct mlx5_core_dev *dev)
43{
44 int err;
45
46 if (mlx5_ecpf_esw_admins_host_pf(dev))
47 return 0;
48
49 /* ECPF shall enable HCA for host PF in the same way a PF
50 * does this for its VFs when ECPF is not a eswitch manager.
51 */
52 err = mlx5_cmd_host_pf_enable_hca(dev);
18 if (err)53 if (err)
19 mlx5_core_err(dev, "Failed to enable peer PF HCA err(%d)\n",54 mlx5_core_err(dev, "Failed to enable external host PF HCA err(%d)\n", err);
20 err);
21 55
22 return err;56 return err;
23}57}
24 58
25static void mlx5_peer_pf_cleanup(struct mlx5_core_dev *dev)59static void mlx5_host_pf_cleanup(struct mlx5_core_dev *dev)
26{60{
27 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
28 int err;61 int err;
29 62
30 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);63 if (mlx5_ecpf_esw_admins_host_pf(dev))
31 err = mlx5_cmd_exec_in(dev, disable_hca, in);64 return;
65
66 err = mlx5_cmd_host_pf_disable_hca(dev);
32 if (err) {67 if (err) {
33 mlx5_core_err(dev, "Failed to disable peer PF HCA err(%d)\n",68 mlx5_core_err(dev, "Failed to disable external host PF HCA err(%d)\n", err);
34 err);
35 return;69 return;
36 }70 }
37
38 err = mlx5_wait_for_pages(dev, &dev->priv.peer_pf_pages);
39 if (err)
40 mlx5_core_warn(dev, "Timeout reclaiming peer PF pages err(%d)\n",
41 err);
42}71}
43 72
44int mlx5_ec_init(struct mlx5_core_dev *dev)73int mlx5_ec_init(struct mlx5_core_dev *dev)
@@ -46,16 +75,19 @@ int mlx5_ec_init(struct mlx5_core_dev *dev) · 1 unmodified line
46 if (!mlx5_core_is_ecpf(dev))75 if (!mlx5_core_is_ecpf(dev))
47 return 0;76 return 0;
48 77
49 /* ECPF shall enable HCA for peer PF in the same way a PF78 return mlx5_host_pf_init(dev);
50 * does this for its VFs.
51 */
52 return mlx5_peer_pf_init(dev);
53}79}
54 80
55void mlx5_ec_cleanup(struct mlx5_core_dev *dev)81void mlx5_ec_cleanup(struct mlx5_core_dev *dev)
56{82{
83 int err;
84
57 if (!mlx5_core_is_ecpf(dev))85 if (!mlx5_core_is_ecpf(dev))
58 return;86 return;
59 87
60 mlx5_peer_pf_cleanup(dev);88 mlx5_host_pf_cleanup(dev);
89
90 err = mlx5_wait_for_pages(dev, &dev->priv.host_pf_pages);
91 if (err)
92 mlx5_core_warn(dev, "Timeout reclaiming external host PF pages err(%d)\n", err);
61}93}
drivers/net/ethernet/mellanox/mlx5/core/ecpf.h+3−0
@@ -17,6 +17,9 @@ bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev); · 16 unmodified lines
17int mlx5_ec_init(struct mlx5_core_dev *dev);17int mlx5_ec_init(struct mlx5_core_dev *dev);
18void mlx5_ec_cleanup(struct mlx5_core_dev *dev);18void mlx5_ec_cleanup(struct mlx5_core_dev *dev);
19 19
20int mlx5_cmd_host_pf_enable_hca(struct mlx5_core_dev *dev);
21int mlx5_cmd_host_pf_disable_hca(struct mlx5_core_dev *dev);
22
20#else /* CONFIG_MLX5_ESWITCH */23#else /* CONFIG_MLX5_ESWITCH */
21 24
22static inline bool25static inline bool
drivers/net/ethernet/mellanox/mlx5/core/esw/acl/helper.c+4−1
@@ -8,6 +8,7 @@ · 7 unmodified lines
8struct mlx5_flow_table *8struct mlx5_flow_table *
9esw_acl_table_create(struct mlx5_eswitch *esw, u16 vport_num, int ns, int size)9esw_acl_table_create(struct mlx5_eswitch *esw, u16 vport_num, int ns, int size)
10{10{
11 struct mlx5_flow_table_attr ft_attr = {};
11 struct mlx5_core_dev *dev = esw->dev;12 struct mlx5_core_dev *dev = esw->dev;
12 struct mlx5_flow_namespace *root_ns;13 struct mlx5_flow_namespace *root_ns;
13 struct mlx5_flow_table *acl;14 struct mlx5_flow_table *acl;
@@ -33,7 +34,9 @@ esw_acl_table_create(struct mlx5_eswitch *esw, u16 vport_num, int ns, int size) · 19 unmodified lines
33 return ERR_PTR(-EOPNOTSUPP);34 return ERR_PTR(-EOPNOTSUPP);
34 }35 }
35 36
36 acl = mlx5_create_vport_flow_table(root_ns, 0, size, 0, vport_num);37 ft_attr.max_fte = size;
38 ft_attr.flags = MLX5_FLOW_TABLE_OTHER_VPORT;
39 acl = mlx5_create_vport_flow_table(root_ns, &ft_attr, vport_num);
37 if (IS_ERR(acl)) {40 if (IS_ERR(acl)) {
38 err = PTR_ERR(acl);41 err = PTR_ERR(acl);
39 esw_warn(dev, "vport[%d] create %s ACL table, err(%d)\n", vport_num,42 esw_warn(dev, "vport[%d] create %s ACL table, err(%d)\n", vport_num,
drivers/net/ethernet/mellanox/mlx5/core/eswitch.c+28−1
@@ -1474,6 +1474,26 @@ vf_err: · 1473 unmodified lines
1474 return err;1474 return err;
1475}1475}
1476 1476
1477static int host_pf_enable_hca(struct mlx5_core_dev *dev)
1478{
1479 if (!mlx5_core_is_ecpf(dev))
1480 return 0;
1481
1482 /* Once vport and representor are ready, take out the external host PF
1483 * out of initializing state. Enabling HCA clears the iser->initializing
1484 * bit and host PF driver loading can progress.
1485 */
1486 return mlx5_cmd_host_pf_enable_hca(dev);
1487}
1488
1489static void host_pf_disable_hca(struct mlx5_core_dev *dev)
1490{
1491 if (!mlx5_core_is_ecpf(dev))
1492 return;
1493
1494 mlx5_cmd_host_pf_disable_hca(dev);
1495}
1496
1477/* mlx5_eswitch_enable_pf_vf_vports() enables vports of PF, ECPF and VFs1497/* mlx5_eswitch_enable_pf_vf_vports() enables vports of PF, ECPF and VFs
1478 * whichever are present on the eswitch.1498 * whichever are present on the eswitch.
1479 */1499 */
@@ -1488,6 +1508,11 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, · 8 unmodified lines
1488 if (ret)1508 if (ret)
1489 return ret;1509 return ret;
1490 1510
1511 /* Enable external host PF HCA */
1512 ret = host_pf_enable_hca(esw->dev);
1513 if (ret)
1514 goto pf_hca_err;
1515
1491 /* Enable ECPF vport */1516 /* Enable ECPF vport */
1492 if (mlx5_ecpf_vport_exists(esw->dev)) {1517 if (mlx5_ecpf_vport_exists(esw->dev)) {
1493 ret = mlx5_eswitch_load_vport(esw, MLX5_VPORT_ECPF, enabled_events);1518 ret = mlx5_eswitch_load_vport(esw, MLX5_VPORT_ECPF, enabled_events);
@@ -1505,8 +1530,9 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, · 11 unmodified lines
1505vf_err:1530vf_err:
1506 if (mlx5_ecpf_vport_exists(esw->dev))1531 if (mlx5_ecpf_vport_exists(esw->dev))
1507 mlx5_eswitch_unload_vport(esw, MLX5_VPORT_ECPF);1532 mlx5_eswitch_unload_vport(esw, MLX5_VPORT_ECPF);
1508
1509ecpf_err:1533ecpf_err:
1534 host_pf_disable_hca(esw->dev);
1535pf_hca_err:
1510 mlx5_eswitch_unload_vport(esw, MLX5_VPORT_PF);1536 mlx5_eswitch_unload_vport(esw, MLX5_VPORT_PF);
1511 return ret;1537 return ret;
1512}1538}
@@ -1521,6 +1547,7 @@ void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw) · 8 unmodified lines
1521 if (mlx5_ecpf_vport_exists(esw->dev))1547 if (mlx5_ecpf_vport_exists(esw->dev))
1522 mlx5_eswitch_unload_vport(esw, MLX5_VPORT_ECPF);1548 mlx5_eswitch_unload_vport(esw, MLX5_VPORT_ECPF);
1523 1549
1550 host_pf_disable_hca(esw->dev);
1524 mlx5_eswitch_unload_vport(esw, MLX5_VPORT_PF);1551 mlx5_eswitch_unload_vport(esw, MLX5_VPORT_PF);
1525}1552}
1526 1553
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c+27−30
@@ -172,10 +172,9 @@ static int mlx5_cmd_update_root_ft(struct mlx5_flow_root_namespace *ns, · 171 unmodified lines
172 MLX5_SET(set_flow_table_root_in, in, table_id, ft->id);172 MLX5_SET(set_flow_table_root_in, in, table_id, ft->id);
173 173
174 MLX5_SET(set_flow_table_root_in, in, underlay_qpn, underlay_qpn);174 MLX5_SET(set_flow_table_root_in, in, underlay_qpn, underlay_qpn);
175 if (ft->vport) {175 MLX5_SET(set_flow_table_root_in, in, vport_number, ft->vport);
176 MLX5_SET(set_flow_table_root_in, in, vport_number, ft->vport);176 MLX5_SET(set_flow_table_root_in, in, other_vport,
177 MLX5_SET(set_flow_table_root_in, in, other_vport, 1);177 !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
178 }
179 178
180 return mlx5_cmd_exec_in(dev, set_flow_table_root, in);179 return mlx5_cmd_exec_in(dev, set_flow_table_root, in);
181}180}
@@ -199,10 +198,9 @@ static int mlx5_cmd_create_flow_table(struct mlx5_flow_root_namespace *ns, · 17 unmodified lines
199 MLX5_SET(create_flow_table_in, in, table_type, ft->type);198 MLX5_SET(create_flow_table_in, in, table_type, ft->type);
200 MLX5_SET(create_flow_table_in, in, flow_table_context.level, ft->level);199 MLX5_SET(create_flow_table_in, in, flow_table_context.level, ft->level);
201 MLX5_SET(create_flow_table_in, in, flow_table_context.log_size, log_size);200 MLX5_SET(create_flow_table_in, in, flow_table_context.log_size, log_size);
202 if (ft->vport) {201 MLX5_SET(create_flow_table_in, in, vport_number, ft->vport);
203 MLX5_SET(create_flow_table_in, in, vport_number, ft->vport);202 MLX5_SET(create_flow_table_in, in, other_vport,
204 MLX5_SET(create_flow_table_in, in, other_vport, 1);203 !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
205 }
206 204
207 MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en,205 MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en,
208 en_decap);206 en_decap);
@@ -252,10 +250,9 @@ static int mlx5_cmd_destroy_flow_table(struct mlx5_flow_root_namespace *ns, · 43 unmodified lines
252 MLX5_CMD_OP_DESTROY_FLOW_TABLE);250 MLX5_CMD_OP_DESTROY_FLOW_TABLE);
253 MLX5_SET(destroy_flow_table_in, in, table_type, ft->type);251 MLX5_SET(destroy_flow_table_in, in, table_type, ft->type);
254 MLX5_SET(destroy_flow_table_in, in, table_id, ft->id);252 MLX5_SET(destroy_flow_table_in, in, table_id, ft->id);
255 if (ft->vport) {253 MLX5_SET(destroy_flow_table_in, in, vport_number, ft->vport);
256 MLX5_SET(destroy_flow_table_in, in, vport_number, ft->vport);254 MLX5_SET(destroy_flow_table_in, in, other_vport,
257 MLX5_SET(destroy_flow_table_in, in, other_vport, 1);255 !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
258 }
259 256
260 return mlx5_cmd_exec_in(dev, destroy_flow_table, in);257 return mlx5_cmd_exec_in(dev, destroy_flow_table, in);
261}258}
@@ -283,11 +280,9 @@ static int mlx5_cmd_modify_flow_table(struct mlx5_flow_root_namespace *ns, · 21 unmodified lines
283 flow_table_context.lag_master_next_table_id, 0);280 flow_table_context.lag_master_next_table_id, 0);
284 }281 }
285 } else {282 } else {
286 if (ft->vport) {283 MLX5_SET(modify_flow_table_in, in, vport_number, ft->vport);
287 MLX5_SET(modify_flow_table_in, in, vport_number,284 MLX5_SET(modify_flow_table_in, in, other_vport,
288 ft->vport);285 !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
289 MLX5_SET(modify_flow_table_in, in, other_vport, 1);
290 }
291 MLX5_SET(modify_flow_table_in, in, modify_field_select,286 MLX5_SET(modify_flow_table_in, in, modify_field_select,
292 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID);287 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID);
293 if (next_ft) {288 if (next_ft) {
@@ -325,6 +320,9 @@ static int mlx5_cmd_create_flow_group(struct mlx5_flow_root_namespace *ns, · 31 unmodified lines
325 MLX5_SET(create_flow_group_in, in, other_vport, 1);320 MLX5_SET(create_flow_group_in, in, other_vport, 1);
326 }321 }
327 322
323 MLX5_SET(create_flow_group_in, in, vport_number, ft->vport);
324 MLX5_SET(create_flow_group_in, in, other_vport,
325 !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
328 err = mlx5_cmd_exec_inout(dev, create_flow_group, in, out);326 err = mlx5_cmd_exec_inout(dev, create_flow_group, in, out);
329 if (!err)327 if (!err)
330 fg->id = MLX5_GET(create_flow_group_out, out,328 fg->id = MLX5_GET(create_flow_group_out, out,
@@ -344,11 +342,9 @@ static int mlx5_cmd_destroy_flow_group(struct mlx5_flow_root_namespace *ns, · 13 unmodified lines
344 MLX5_SET(destroy_flow_group_in, in, table_type, ft->type);342 MLX5_SET(destroy_flow_group_in, in, table_type, ft->type);
345 MLX5_SET(destroy_flow_group_in, in, table_id, ft->id);343 MLX5_SET(destroy_flow_group_in, in, table_id, ft->id);
346 MLX5_SET(destroy_flow_group_in, in, group_id, fg->id);344 MLX5_SET(destroy_flow_group_in, in, group_id, fg->id);
347 if (ft->vport) {345 MLX5_SET(destroy_flow_group_in, in, vport_number, ft->vport);
348 MLX5_SET(destroy_flow_group_in, in, vport_number, ft->vport);346 MLX5_SET(destroy_flow_group_in, in, other_vport,
349 MLX5_SET(destroy_flow_group_in, in, other_vport, 1);347 !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
350 }
351
352 return mlx5_cmd_exec_in(dev, destroy_flow_group, in);348 return mlx5_cmd_exec_in(dev, destroy_flow_group, in);
353}349}
354 350
@@ -427,10 +423,9 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, · 72 unmodified lines
427 MLX5_SET(set_fte_in, in, ignore_flow_level,423 MLX5_SET(set_fte_in, in, ignore_flow_level,
428 !!(fte->action.flags & FLOW_ACT_IGNORE_FLOW_LEVEL));424 !!(fte->action.flags & FLOW_ACT_IGNORE_FLOW_LEVEL));
429 425
430 if (ft->vport) {426 MLX5_SET(set_fte_in, in, vport_number, ft->vport);
431 MLX5_SET(set_fte_in, in, vport_number, ft->vport);427 MLX5_SET(set_fte_in, in, other_vport,
432 MLX5_SET(set_fte_in, in, other_vport, 1);428 !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
433 }
434 429
435 in_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context);430 in_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context);
436 MLX5_SET(flow_context, in_flow_context, group_id, group_id);431 MLX5_SET(flow_context, in_flow_context, group_id, group_id);
@@ -515,6 +510,9 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, · 78 unmodified lines
515 dst->dest_attr.vport.pkt_reformat->id);510 dst->dest_attr.vport.pkt_reformat->id);
516 }511 }
517 break;512 break;
513 case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER:
514 id = dst->dest_attr.sampler_id;
515 break;
518 default:516 default:
519 id = dst->dest_attr.tir_num;517 id = dst->dest_attr.tir_num;
520 }518 }
@@ -601,10 +599,9 @@ static int mlx5_cmd_delete_fte(struct mlx5_flow_root_namespace *ns, · 80 unmodified lines
601 MLX5_SET(delete_fte_in, in, table_type, ft->type);599 MLX5_SET(delete_fte_in, in, table_type, ft->type);
602 MLX5_SET(delete_fte_in, in, table_id, ft->id);600 MLX5_SET(delete_fte_in, in, table_id, ft->id);
603 MLX5_SET(delete_fte_in, in, flow_index, fte->index);601 MLX5_SET(delete_fte_in, in, flow_index, fte->index);
604 if (ft->vport) {602 MLX5_SET(delete_fte_in, in, vport_number, ft->vport);
605 MLX5_SET(delete_fte_in, in, vport_number, ft->vport);603 MLX5_SET(delete_fte_in, in, other_vport,
606 MLX5_SET(delete_fte_in, in, other_vport, 1);604 !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT));
607 }
608 605
609 return mlx5_cmd_exec_in(dev, delete_fte, in);606 return mlx5_cmd_exec_in(dev, delete_fte, in);
610}607}
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c+7−10
@@ -1152,18 +1152,13 @@ struct mlx5_flow_table *mlx5_create_flow_table(struct mlx5_flow_namespace *ns, · 1151 unmodified lines
1152{1152{
1153 return __mlx5_create_flow_table(ns, ft_attr, FS_FT_OP_MOD_NORMAL, 0);1153 return __mlx5_create_flow_table(ns, ft_attr, FS_FT_OP_MOD_NORMAL, 0);
1154}1154}
1155EXPORT_SYMBOL(mlx5_create_flow_table);
1155 1156
1156struct mlx5_flow_table *mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,1157struct mlx5_flow_table *
1157 int prio, int max_fte,1158mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
1158 u32 level, u16 vport)1159 struct mlx5_flow_table_attr *ft_attr, u16 vport)
1159{1160{
1160 struct mlx5_flow_table_attr ft_attr = {};1161 return __mlx5_create_flow_table(ns, ft_attr, FS_FT_OP_MOD_NORMAL, vport);
1161
1162 ft_attr.max_fte = max_fte;
1163 ft_attr.level = level;
1164 ft_attr.prio = prio;
1165
1166 return __mlx5_create_flow_table(ns, &ft_attr, FS_FT_OP_MOD_NORMAL, vport);
1167}1162}
1168 1163
1169struct mlx5_flow_table*1164struct mlx5_flow_table*
@@ -1243,6 +1238,7 @@ struct mlx5_flow_group *mlx5_create_flow_group(struct mlx5_flow_table *ft, · 73 unmodified lines
1243 1238
1244 return fg;1239 return fg;
1245}1240}
1241EXPORT_SYMBOL(mlx5_create_flow_group);
1246 1242
1247static struct mlx5_flow_rule *alloc_rule(struct mlx5_flow_destination *dest)1243static struct mlx5_flow_rule *alloc_rule(struct mlx5_flow_destination *dest)
1248{1244{
@@ -2146,6 +2142,7 @@ void mlx5_destroy_flow_group(struct mlx5_flow_group *fg) · 897 unmodified lines
2146 mlx5_core_warn(get_dev(&fg->node), "Flow group %d wasn't destroyed, refcount > 1\n",2142 mlx5_core_warn(get_dev(&fg->node), "Flow group %d wasn't destroyed, refcount > 1\n",
2147 fg->id);2143 fg->id);
2148}2144}
2145EXPORT_SYMBOL(mlx5_destroy_flow_group);
2149 2146
2150struct mlx5_flow_namespace *mlx5_get_fdb_sub_ns(struct mlx5_core_dev *dev,2147struct mlx5_flow_namespace *mlx5_get_fdb_sub_ns(struct mlx5_core_dev *dev,
2151 int n)2148 int n)
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h+1−1
@@ -194,7 +194,7 @@ struct mlx5_ft_underlay_qp { · 193 unmodified lines
194 u32 qpn;194 u32 qpn;
195};195};
196 196
197#define MLX5_FTE_MATCH_PARAM_RESERVED reserved_at_a00197#define MLX5_FTE_MATCH_PARAM_RESERVED reserved_at_c00
198/* Calculate the fte_match_param length and without the reserved length.198/* Calculate the fte_match_param length and without the reserved length.
199 * Make sure the reserved field is the last.199 * Make sure the reserved field is the last.
200 */200 */
drivers/net/ethernet/mellanox/mlx5/core/main.c+10−9
@@ -1126,23 +1126,23 @@ static int mlx5_load(struct mlx5_core_dev *dev) · 1125 unmodified lines
1126 goto err_sriov;1126 goto err_sriov;
1127 }1127 }
1128 1128
1129 err = mlx5_sriov_attach(dev);
1130 if (err) {
1131 mlx5_core_err(dev, "sriov init failed %d\n", err);
1132 goto err_sriov;
1133 }
1134
1135 err = mlx5_ec_init(dev);1129 err = mlx5_ec_init(dev);
1136 if (err) {1130 if (err) {
1137 mlx5_core_err(dev, "Failed to init embedded CPU\n");1131 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1138 goto err_ec;1132 goto err_ec;
1139 }1133 }
1140 1134
1135 err = mlx5_sriov_attach(dev);
1136 if (err) {
1137 mlx5_core_err(dev, "sriov init failed %d\n", err);
1138 goto err_sriov;
1139 }
1140
1141 return 0;1141 return 0;
1142 1142
1143err_ec:
1144 mlx5_sriov_detach(dev);
1145err_sriov:1143err_sriov:
1144 mlx5_ec_cleanup(dev);
1145err_ec:
1146 mlx5_cleanup_fs(dev);1146 mlx5_cleanup_fs(dev);
1147err_fs:1147err_fs:
1148 mlx5_accel_tls_cleanup(dev);1148 mlx5_accel_tls_cleanup(dev);
@@ -1168,8 +1168,8 @@ err_irq_table: · 19 unmodified lines
1168 1168
1169static void mlx5_unload(struct mlx5_core_dev *dev)1169static void mlx5_unload(struct mlx5_core_dev *dev)
1170{1170{
1171 mlx5_ec_cleanup(dev);
1172 mlx5_sriov_detach(dev);1171 mlx5_sriov_detach(dev);
1172 mlx5_ec_cleanup(dev);
1173 mlx5_cleanup_fs(dev);1173 mlx5_cleanup_fs(dev);
1174 mlx5_accel_ipsec_cleanup(dev);1174 mlx5_accel_ipsec_cleanup(dev);
1175 mlx5_accel_tls_cleanup(dev);1175 mlx5_accel_tls_cleanup(dev);
@@ -1594,6 +1594,7 @@ static const struct pci_device_id mlx5_core_pci_table[] = { · 418 unmodified lines
1594 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */1594 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1595 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */1595 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1596 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */1596 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1597 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1597 { 0, }1598 { 0, }
1598};1599};
1599 1600
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h+4−0
@@ -122,6 +122,10 @@ enum mlx5_semaphore_space_address { · 121 unmodified lines
122 122
123int mlx5_query_hca_caps(struct mlx5_core_dev *dev);123int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
124int mlx5_query_board_id(struct mlx5_core_dev *dev);124int mlx5_query_board_id(struct mlx5_core_dev *dev);
125int mlx5_cmd_init(struct mlx5_core_dev *dev);
126void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
127void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
128 enum mlx5_cmdif_state cmdif_state);
125int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);129int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
126int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);130int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
127int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);131int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c+6−6
@@ -374,7 +374,7 @@ retry: · 373 unmodified lines
374 if (func_id)374 if (func_id)
375 dev->priv.vfs_pages += npages;375 dev->priv.vfs_pages += npages;
376 else if (mlx5_core_is_ecpf(dev) && !ec_function)376 else if (mlx5_core_is_ecpf(dev) && !ec_function)
377 dev->priv.peer_pf_pages += npages;377 dev->priv.host_pf_pages += npages;
378 378
379 mlx5_core_dbg(dev, "npages %d, ec_function %d, func_id 0x%x, err %d\n",379 mlx5_core_dbg(dev, "npages %d, ec_function %d, func_id 0x%x, err %d\n",
380 npages, ec_function, func_id, err);380 npages, ec_function, func_id, err);
@@ -416,7 +416,7 @@ static void release_all_pages(struct mlx5_core_dev *dev, u32 func_id, · 35 unmodified lines
416 if (func_id)416 if (func_id)
417 dev->priv.vfs_pages -= npages;417 dev->priv.vfs_pages -= npages;
418 else if (mlx5_core_is_ecpf(dev) && !ec_function)418 else if (mlx5_core_is_ecpf(dev) && !ec_function)
419 dev->priv.peer_pf_pages -= npages;419 dev->priv.host_pf_pages -= npages;
420 420
421 mlx5_core_dbg(dev, "npages %d, ec_function %d, func_id 0x%x\n",421 mlx5_core_dbg(dev, "npages %d, ec_function %d, func_id 0x%x\n",
422 npages, ec_function, func_id);422 npages, ec_function, func_id);
@@ -506,7 +506,7 @@ static int reclaim_pages(struct mlx5_core_dev *dev, u32 func_id, int npages, · 83 unmodified lines
506 if (func_id)506 if (func_id)
507 dev->priv.vfs_pages -= num_claimed;507 dev->priv.vfs_pages -= num_claimed;
508 else if (mlx5_core_is_ecpf(dev) && !ec_function)508 else if (mlx5_core_is_ecpf(dev) && !ec_function)
509 dev->priv.peer_pf_pages -= num_claimed;509 dev->priv.host_pf_pages -= num_claimed;
510 510
511out_free:511out_free:
512 kvfree(out);512 kvfree(out);
@@ -661,9 +661,9 @@ int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev) · 148 unmodified lines
661 WARN(dev->priv.vfs_pages,661 WARN(dev->priv.vfs_pages,
662 "VFs FW pages counter is %d after reclaiming all pages\n",662 "VFs FW pages counter is %d after reclaiming all pages\n",
663 dev->priv.vfs_pages);663 dev->priv.vfs_pages);
664 WARN(dev->priv.peer_pf_pages,664 WARN(dev->priv.host_pf_pages,
665 "Peer PF FW pages counter is %d after reclaiming all pages\n",665 "External host PF FW pages counter is %d after reclaiming all pages\n",
666 dev->priv.peer_pf_pages);666 dev->priv.host_pf_pages);
667 667
668 return 0;668 return 0;
669}669}
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c+1−1
@@ -643,7 +643,7 @@ static int dr_matcher_init(struct mlx5dr_matcher *matcher, · 642 unmodified lines
643 }643 }
644 644
645 if (mask) {645 if (mask) {
646 if (mask->match_sz > sizeof(struct mlx5dr_match_param)) {646 if (mask->match_sz > DR_SZ_MATCH_PARAM) {
647 mlx5dr_err(dmn, "Invalid match size attribute\n");647 mlx5dr_err(dmn, "Invalid match size attribute\n");
648 return -EINVAL;648 return -EINVAL;
649 }649 }
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c+1−2
@@ -874,8 +874,7 @@ static bool dr_rule_verify(struct mlx5dr_matcher *matcher, · 873 unmodified lines
874 u32 s_idx, e_idx;874 u32 s_idx, e_idx;
875 875
876 if (!value_size ||876 if (!value_size ||
877 (value_size > sizeof(struct mlx5dr_match_param) ||877 (value_size > DR_SZ_MATCH_PARAM || (value_size % sizeof(u32)))) {
878 (value_size % sizeof(u32)))) {
879 mlx5dr_err(matcher->tbl->dmn, "Rule parameters length is incorrect\n");878 mlx5dr_err(matcher->tbl->dmn, "Rule parameters length is incorrect\n");
880 return false;879 return false;
881 }880 }
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h+1−0
@@ -17,6 +17,7 @@ · 16 unmodified lines
17#define WIRE_PORT 0xFFFF17#define WIRE_PORT 0xFFFF
18#define DR_STE_SVLAN 0x118#define DR_STE_SVLAN 0x1
19#define DR_STE_CVLAN 0x219#define DR_STE_CVLAN 0x2
20#define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4)
20 21
21#define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)22#define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
22#define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)23#define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
include/linux/mlx5/device.h+8−0
@@ -346,6 +346,7 @@ enum mlx5_event { · 345 unmodified lines
346 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,346 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
347 347
348 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,348 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
349 MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf,
349 350
350 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,351 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
351 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,352 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
@@ -717,6 +718,11 @@ struct mlx5_eqe_sync_fw_update { · 365 unmodified lines
717 u8 sync_rst_state;718 u8 sync_rst_state;
718};719};
719 720
721struct mlx5_eqe_vhca_state {
722 __be16 ec_function;
723 __be16 function_id;
724} __packed;
725
720union ev_data {726union ev_data {
721 __be32 raw[7];727 __be32 raw[7];
722 struct mlx5_eqe_cmd cmd;728 struct mlx5_eqe_cmd cmd;
@@ -736,6 +742,7 @@ union ev_data { · 13 unmodified lines
736 struct mlx5_eqe_temp_warning temp_warning;742 struct mlx5_eqe_temp_warning temp_warning;
737 struct mlx5_eqe_xrq_err xrq_err;743 struct mlx5_eqe_xrq_err xrq_err;
738 struct mlx5_eqe_sync_fw_update sync_fw_update;744 struct mlx5_eqe_sync_fw_update sync_fw_update;
745 struct mlx5_eqe_vhca_state vhca_state;
739} __packed;746} __packed;
740 747
741struct mlx5_eqe {748struct mlx5_eqe {
@@ -1076,6 +1083,7 @@ enum { · 334 unmodified lines
1076 MLX5_MATCH_INNER_HEADERS = 1 << 2,1083 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1077 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,1084 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
1078 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,1085 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
1086 MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5,
1079};1087};
1080 1088
1081enum {1089enum {
include/linux/mlx5/driver.h+2−6
@@ -547,7 +547,7 @@ struct mlx5_priv { · 546 unmodified lines
547 atomic_t reg_pages;547 atomic_t reg_pages;
548 struct list_head free_list;548 struct list_head free_list;
549 int vfs_pages;549 int vfs_pages;
550 int peer_pf_pages;550 int host_pf_pages;
551 551
552 struct mlx5_core_health health;552 struct mlx5_core_health health;
553 553
@@ -888,10 +888,6 @@ enum { · 334 unmodified lines
888 CMD_ALLOWED_OPCODE_ALL,888 CMD_ALLOWED_OPCODE_ALL,
889};889};
890 890
891int mlx5_cmd_init(struct mlx5_core_dev *dev);
892void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
893void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
894 enum mlx5_cmdif_state cmdif_state);
895void mlx5_cmd_use_events(struct mlx5_core_dev *dev);891void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
896void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);892void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
897void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);893void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
@@ -1137,7 +1133,7 @@ static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev) · 239 unmodified lines
1137 return dev->coredev_type == MLX5_COREDEV_VF;1133 return dev->coredev_type == MLX5_COREDEV_VF;
1138}1134}
1139 1135
1140static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)1136static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1141{1137{
1142 return dev->caps.embedded_cpu;1138 return dev->caps.embedded_cpu;
1143}1139}
include/linux/mlx5/fs.h+3−3
@@ -50,6 +50,7 @@ enum { · 49 unmodified lines
50 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),50 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),
51 MLX5_FLOW_TABLE_TERMINATION = BIT(2),51 MLX5_FLOW_TABLE_TERMINATION = BIT(2),
52 MLX5_FLOW_TABLE_UNMANAGED = BIT(3),52 MLX5_FLOW_TABLE_UNMANAGED = BIT(3),
53 MLX5_FLOW_TABLE_OTHER_VPORT = BIT(4),
53};54};
54 55
55#define LEFTOVERS_RULE_NUM 256#define LEFTOVERS_RULE_NUM 2
@@ -132,6 +133,7 @@ struct mlx5_flow_destination { · 76 unmodified lines
132 struct mlx5_pkt_reformat *pkt_reformat;133 struct mlx5_pkt_reformat *pkt_reformat;
133 u8 flags;134 u8 flags;
134 } vport;135 } vport;
136 u32 sampler_id;
135 };137 };
136};138};
137 139
@@ -173,9 +175,7 @@ mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns, · 35 unmodified lines
173 175
174struct mlx5_flow_table *176struct mlx5_flow_table *
175mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,177mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
176 int prio,178 struct mlx5_flow_table_attr *ft_attr, u16 vport);
177 int num_flow_table_entries,
178 u32 level, u16 vport);
179struct mlx5_flow_table *mlx5_create_lag_demux_flow_table(179struct mlx5_flow_table *mlx5_create_lag_demux_flow_table(
180 struct mlx5_flow_namespace *ns,180 struct mlx5_flow_namespace *ns,
181 int prio, u32 level);181 int prio, u32 level);
include/linux/mlx5/mlx5_ifc.h+86−8
@@ -299,6 +299,8 @@ enum { · 298 unmodified lines
299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
302 MLX5_CMD_OP_MAX304 MLX5_CMD_OP_MAX
303};305};
304 306
@@ -623,6 +625,26 @@ struct mlx5_ifc_fte_match_set_misc3_bits { · 318 unmodified lines
623 u8 reserved_at_140[0xc0];625 u8 reserved_at_140[0xc0];
624};626};
625 627
628struct mlx5_ifc_fte_match_set_misc4_bits {
629 u8 prog_sample_field_value_0[0x20];
630
631 u8 prog_sample_field_id_0[0x20];
632
633 u8 prog_sample_field_value_1[0x20];
634
635 u8 prog_sample_field_id_1[0x20];
636
637 u8 prog_sample_field_value_2[0x20];
638
639 u8 prog_sample_field_id_2[0x20];
640
641 u8 prog_sample_field_value_3[0x20];
642
643 u8 prog_sample_field_id_3[0x20];
644
645 u8 reserved_at_100[0x100];
646};
647
626struct mlx5_ifc_cmd_pas_bits {648struct mlx5_ifc_cmd_pas_bits {
627 u8 pa_h[0x20];649 u8 pa_h[0x20];
628 650
@@ -891,7 +913,10 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits { · 262 unmodified lines
891 u8 tunnel_stateless_ipv4_over_vxlan[0x1];913 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
892 u8 tunnel_stateless_ip_over_ip[0x1];914 u8 tunnel_stateless_ip_over_ip[0x1];
893 u8 insert_trailer[0x1];915 u8 insert_trailer[0x1];
894 u8 reserved_at_2b[0x5];916 u8 reserved_at_2b[0x1];
917 u8 tunnel_stateless_ip_over_ip_rx[0x1];
918 u8 tunnel_stateless_ip_over_ip_tx[0x1];
919 u8 reserved_at_2e[0x2];
895 u8 max_vxlan_udp_ports[0x8];920 u8 max_vxlan_udp_ports[0x8];
896 u8 reserved_at_38[0x6];921 u8 reserved_at_38[0x6];
897 u8 max_geneve_opt_len[0x1];922 u8 max_geneve_opt_len[0x1];
@@ -1224,7 +1249,16 @@ enum mlx5_fc_bulk_alloc_bitmask { · 326 unmodified lines
1224#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))1249#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1225 1250
1226struct mlx5_ifc_cmd_hca_cap_bits {1251struct mlx5_ifc_cmd_hca_cap_bits {
1227 u8 reserved_at_0[0x30];1252 u8 reserved_at_0[0x1f];
1253 u8 vhca_resource_manager[0x1];
1254
1255 u8 reserved_at_20[0x3];
1256 u8 event_on_vhca_state_teardown_request[0x1];
1257 u8 event_on_vhca_state_in_use[0x1];
1258 u8 event_on_vhca_state_active[0x1];
1259 u8 event_on_vhca_state_allocated[0x1];
1260 u8 event_on_vhca_state_invalid[0x1];
1261 u8 reserved_at_28[0x8];
1228 u8 vhca_id[0x10];1262 u8 vhca_id[0x10];
1229 1263
1230 u8 reserved_at_40[0x40];1264 u8 reserved_at_40[0x40];
@@ -1241,7 +1275,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 10 unmodified lines
1241 u8 ece_support[0x1];1275 u8 ece_support[0x1];
1242 u8 reserved_at_a4[0x7];1276 u8 reserved_at_a4[0x7];
1243 u8 log_max_srq[0x5];1277 u8 log_max_srq[0x5];
1244 u8 reserved_at_b0[0x10];1278 u8 reserved_at_b0[0x2];
1279 u8 ts_cqe_to_dest_cqn[0x1];
1280 u8 reserved_at_b3[0xd];
1245 1281
1246 u8 max_sgl_for_optimized_performance[0x8];1282 u8 max_sgl_for_optimized_performance[0x8];
1247 u8 log_max_cq_sz[0x8];1283 u8 log_max_cq_sz[0x8];
@@ -1512,7 +1548,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 264 unmodified lines
1512 u8 disable_local_lb_uc[0x1];1548 u8 disable_local_lb_uc[0x1];
1513 u8 disable_local_lb_mc[0x1];1549 u8 disable_local_lb_mc[0x1];
1514 u8 log_min_hairpin_wq_data_sz[0x5];1550 u8 log_min_hairpin_wq_data_sz[0x5];
1515 u8 reserved_at_3e8[0x3];1551 u8 reserved_at_3e8[0x2];
1552 u8 vhca_state[0x1];
1516 u8 log_max_vlan_list[0x5];1553 u8 log_max_vlan_list[0x5];
1517 u8 reserved_at_3f0[0x3];1554 u8 reserved_at_3f0[0x3];
1518 u8 log_max_current_mc_list[0x5];1555 u8 log_max_current_mc_list[0x5];
@@ -1580,7 +1617,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 61 unmodified lines
1580 u8 max_num_of_monitor_counters[0x10];1617 u8 max_num_of_monitor_counters[0x10];
1581 u8 num_ppcnt_monitor_counters[0x10];1618 u8 num_ppcnt_monitor_counters[0x10];
1582 1619
1583 u8 reserved_at_640[0x10];1620 u8 max_num_sf[0x10];
1584 u8 num_q_monitor_counters[0x10];1621 u8 num_q_monitor_counters[0x10];
1585 1622
1586 u8 reserved_at_660[0x20];1623 u8 reserved_at_660[0x20];
@@ -1616,6 +1653,7 @@ enum mlx5_flow_destination_type { · 29 unmodified lines
1616 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,1653 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1617 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,1654 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1618 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,1655 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1656 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1619 1657
1620 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,1658 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1621 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,1659 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
@@ -1668,7 +1706,9 @@ struct mlx5_ifc_fte_match_param_bits { · 46 unmodified lines
1668 1706
1669 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;1707 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1670 1708
1671 u8 reserved_at_a00[0x600];1709 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1710
1711 u8 reserved_at_c00[0x400];
1672};1712};
1673 1713
1674enum {1714enum {
@@ -3289,8 +3329,12 @@ struct mlx5_ifc_sqc_bits { · 1614 unmodified lines
3289 u8 reserved_at_80[0x10];3329 u8 reserved_at_80[0x10];
3290 u8 hairpin_peer_vhca[0x10];3330 u8 hairpin_peer_vhca[0x10];
3291 3331
3292 u8 reserved_at_a0[0x50];3332 u8 reserved_at_a0[0x20];
3293 3333
3334 u8 reserved_at_c0[0x8];
3335 u8 ts_cqe_to_dest_cqn[0x18];
3336
3337 u8 reserved_at_e0[0x10];
3294 u8 packet_pacing_rate_limit_index[0x10];3338 u8 packet_pacing_rate_limit_index[0x10];
3295 u8 tis_lst_sz[0x10];3339 u8 tis_lst_sz[0x10];
3296 u8 reserved_at_110[0x10];3340 u8 reserved_at_110[0x10];
@@ -4204,7 +4248,11 @@ struct mlx5_ifc_set_hca_cap_in_bits { · 907 unmodified lines
4204 u8 reserved_at_20[0x10];4248 u8 reserved_at_20[0x10];
4205 u8 op_mod[0x10];4249 u8 op_mod[0x10];
4206 4250
4207 u8 reserved_at_40[0x40];4251 u8 other_function[0x1];
4252 u8 reserved_at_41[0xf];
4253 u8 function_id[0x10];
4254
4255 u8 reserved_at_60[0x20];
4208 4256
4209 union mlx5_ifc_hca_cap_union_bits capability;4257 union mlx5_ifc_hca_cap_union_bits capability;
4210};4258};
@@ -5461,6 +5509,7 @@ enum { · 1250 unmodified lines
5461 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,5509 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5462 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,5510 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5463 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,5511 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5512 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
5464};5513};
5465 5514
5466struct mlx5_ifc_query_flow_group_out_bits {5515struct mlx5_ifc_query_flow_group_out_bits {
@@ -10657,11 +10706,13 @@ struct mlx5_ifc_affiliated_event_header_bits { · 5190 unmodified lines
10657enum {10706enum {
10658 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),10707 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10659 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),10708 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
10709 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT(0x20),
10660};10710};
10661 10711
10662enum {10712enum {
10663 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,10713 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10664 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,10714 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10715 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
10665};10716};
10666 10717
10667enum {10718enum {
@@ -10736,6 +10787,33 @@ struct mlx5_ifc_create_encryption_key_in_bits { · 68 unmodified lines
10736 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;10787 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10737};10788};
10738 10789
10790struct mlx5_ifc_sampler_obj_bits {
10791 u8 modify_field_select[0x40];
10792
10793 u8 table_type[0x8];
10794 u8 level[0x8];
10795 u8 reserved_at_50[0xf];
10796 u8 ignore_flow_level[0x1];
10797
10798 u8 sample_ratio[0x20];
10799
10800 u8 reserved_at_80[0x8];
10801 u8 sample_table_id[0x18];
10802
10803 u8 reserved_at_a0[0x8];
10804 u8 default_table_id[0x18];
10805
10806 u8 sw_steering_icm_address_rx[0x40];
10807 u8 sw_steering_icm_address_tx[0x40];
10808
10809 u8 reserved_at_140[0xa0];
10810};
10811
10812struct mlx5_ifc_create_sampler_obj_in_bits {
10813 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10814 struct mlx5_ifc_sampler_obj_bits sampler_object;
10815};
10816
10739enum {10817enum {
10740 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,10818 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10741 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,10819 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
include/uapi/rdma/mlx5_user_ioctl_cmds.h+1−1
@@ -232,7 +232,7 @@ enum mlx5_ib_device_query_context_attrs { · 231 unmodified lines
232 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX = (1U << UVERBS_ID_NS_SHIFT),232 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX = (1U << UVERBS_ID_NS_SHIFT),
233};233};
234 234
235#define MLX5_IB_DW_MATCH_PARAM 0x80235#define MLX5_IB_DW_MATCH_PARAM 0x90
236 236
237struct mlx5_ib_match_params {237struct mlx5_ib_match_params {
238 __u32 match_params[MLX5_IB_DW_MATCH_PARAM];238 __u32 match_params[MLX5_IB_DW_MATCH_PARAM];