drm/radeon/cik: Add macrotile mode array query

This is required to properly calculate the tiling parameters in userspace.

Michel Dänzer committed 12 years ago

Commit 32f79a81 parent 1ddce275 files · +17 −1Browse files

Unified · Split

5 files

@@ -2427,6 +2427,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) · 2426 unmodified lines
2427	2427	gb_tile_moden = 0;
2428	2428	break;
2429	2429	}
	2430	+ rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2430	2431	WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2431	2432	}
2432	2433	} else if (num_pipe_configs == 4) {
@@ -2773,6 +2774,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) · 340 unmodified lines
2773	2774	gb_tile_moden = 0;
2774	2775	break;
2775	2776	}
	2777	+ rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2776	2778	WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2777	2779	}
2778	2780	} else if (num_pipe_configs == 2) {
@@ -2990,6 +2992,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) · 211 unmodified lines
2990	2992	gb_tile_moden = 0;
2991	2993	break;
2992	2994	}
	2995	+ rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2993	2996	WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2994	2997	}
2995	2998	} else

@@ -1982,6 +1982,7 @@ struct cik_asic { · 1981 unmodified lines
1982	1982
1983	1983	unsigned tile_config;
1984	1984	uint32_t tile_mode_array[32];
	1985	+ uint32_t macrotile_mode_array[16];
1985	1986	};
1986	1987
1987	1988	union radeon_asic_config {

@@ -76,9 +76,10 @@ · 75 unmodified lines
76	76	* 2.32.0 - new info request for rings working
77	77	* 2.33.0 - Add SI tiling mode array query
78	78	* 2.34.0 - Add CIK tiling mode array query
	79	+ * 2.35.0 - Add CIK macrotile mode array query
79	80	*/
80	81	#define KMS_DRIVER_MAJOR 2
81		−#define KMS_DRIVER_MINOR 34
	82	+#define KMS_DRIVER_MINOR 35
82	83	#define KMS_DRIVER_PATCHLEVEL 0
83	84	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
84	85	int radeon_driver_unload_kms(struct drm_device *dev);

@@ -449,6 +449,15 @@ int radeon_info_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 448 unmodified lines
449	449	return -EINVAL;
450	450	}
451	451	break;
	452	+ case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
	453	+ if (rdev->family >= CHIP_BONAIRE) {
	454	+ value = rdev->config.cik.macrotile_mode_array;
	455	+ value_size = sizeof(uint32_t)*16;
	456	+ } else {
	457	+ DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
	458	+ return -EINVAL;
	459	+ }
	460	+ break;
452	461	case RADEON_INFO_SI_CP_DMA_COMPUTE:
453	462	*value = 1;
454	463	break;

@@ -981,6 +981,8 @@ struct drm_radeon_cs { · 980 unmodified lines
981	981	#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
982	982	/* query if CP DMA is supported on the compute ring */
983	983	#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
	984	+/* CIK macrotile mode array */
	985	+#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
984	986
985	987
986	988	struct drm_radeon_info {

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