Sync KVM ABI additions and x86 CPU features additions - neither of which has any impact on the tooling build.
Unified · Split
| @@ -91,6 +91,7 @@ struct kvm_regs { · 90 unmodified lines | |||
| 91 | #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 | 91 | #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 |
| 92 | #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 | 92 | #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 |
| 93 | #define KVM_VGIC_ITS_ADDR_TYPE 4 | 93 | #define KVM_VGIC_ITS_ADDR_TYPE 4 |
| 94 | #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 | ||
| 94 | 95 | ||
| 95 | #define KVM_VGIC_V3_DIST_SIZE SZ_64K | 96 | #define KVM_VGIC_V3_DIST_SIZE SZ_64K |
| 96 | #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) | 97 | #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) |
| @@ -91,6 +91,7 @@ struct kvm_regs { · 90 unmodified lines | |||
| 91 | #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 | 91 | #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 |
| 92 | #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 | 92 | #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 |
| 93 | #define KVM_VGIC_ITS_ADDR_TYPE 4 | 93 | #define KVM_VGIC_ITS_ADDR_TYPE 4 |
| 94 | #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 | ||
| 94 | 95 | ||
| 95 | #define KVM_VGIC_V3_DIST_SIZE SZ_64K | 96 | #define KVM_VGIC_V3_DIST_SIZE SZ_64K |
| 96 | #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) | 97 | #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) |
| @@ -633,6 +633,7 @@ struct kvm_ppc_cpu_char { · 632 unmodified lines | |||
| 633 | #define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd) | 633 | #define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd) |
| 634 | 634 | ||
| 635 | #define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe) | 635 | #define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe) |
| 636 | #define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf) | ||
| 636 | 637 | ||
| 637 | /* Transactional Memory checkpointed state: | 638 | /* Transactional Memory checkpointed state: |
| 638 | * This is all GPRs, all VSX regs and a subset of SPRs | 639 | * This is all GPRs, all VSX regs and a subset of SPRs |
| @@ -282,7 +282,9 @@ · 281 unmodified lines | |||
| 282 | #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ | 282 | #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ |
| 283 | #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ | 283 | #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ |
| 284 | #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ | 284 | #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ |
| 285 | #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ | ||
| 285 | #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ | 286 | #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ |
| 287 | #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ | ||
| 286 | 288 | ||
| 287 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ | 289 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ |
| 288 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | 290 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ |
| @@ -948,6 +948,7 @@ struct kvm_ppc_resize_hpt { · 947 unmodified lines | |||
| 948 | #define KVM_CAP_S390_BPB 152 | 948 | #define KVM_CAP_S390_BPB 152 |
| 949 | #define KVM_CAP_GET_MSR_FEATURES 153 | 949 | #define KVM_CAP_GET_MSR_FEATURES 153 |
| 950 | #define KVM_CAP_HYPERV_EVENTFD 154 | 950 | #define KVM_CAP_HYPERV_EVENTFD 154 |
| 951 | #define KVM_CAP_HYPERV_TLBFLUSH 155 | ||
| 951 | 952 | ||
| 952 | #ifdef KVM_CAP_IRQ_ROUTING | 953 | #ifdef KVM_CAP_IRQ_ROUTING |
| 953 | 954 | ||