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Merge tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.6 * SCM major refactoring and cleanup * Properly flag active only power domains as active only * Add SC7180 and SM8150 RPMH power domains * Return EPROBE_DEFER from QMI if packet family is not yet available * tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits) firmware: qcom_scm: Dynamically support SMCCC and legacy conventions firmware: qcom_scm: Remove thin wrappers firmware: qcom_scm: Order functions, definitions by service/command firmware: qcom_scm-32: Add device argument to atomic calls firmware: qcom_scm-32: Create common legacy atomic call firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls firmware: qcom_scm-32: Add funcnum IDs firmware: qcom_scm-32: Use SMC arch wrappers firmware: qcom_scm-64: Improve SMC convention detection firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc firmware: qcom_scm-64: Add SCM results struct firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc firmware: qcom_scm-64: Make SMC macros less magical firmware: qcom_scm: Remove unused qcom_scm_get_version firmware: qcom_scm: Apply consistent naming scheme to command IDs firmware: qcom_scm: Rename macros and structures soc: qcom: rpmhpd: Set 'active_only' for active only power domains firmware: scm: Add stubs for OCMEM and restore_sec_cfg_available dt-bindings: power: rpmpd: Convert rpmpd bindings to yaml ...

Olof Johansson committed 6 years ago

Commit 333505a2 parents a9e3e12 9a434ce16 files · +1504 −1741Browse files

Showing the changes to include/linux (1 of 16 files). Show all

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include/linux/qcom_scm.h+68−51
@@ -1,5 +1,5 @@
1/* SPDX-License-Identifier: GPL-2.0-only */1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.2/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.3 * Copyright (C) 2015 Linaro Ltd.
4 */4 */
5#ifndef __QCOM_SCM_H5#ifndef __QCOM_SCM_H
@@ -55,77 +55,94 @@ enum qcom_scm_sec_dev_id { · 49 unmodified lines
55#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)55#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
56 56
57#if IS_ENABLED(CONFIG_QCOM_SCM)57#if IS_ENABLED(CONFIG_QCOM_SCM)
58extern bool qcom_scm_is_available(void);
59
58extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);60extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
59extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);61extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
60extern bool qcom_scm_is_available(void);62extern void qcom_scm_cpu_power_down(u32 flags);
61extern bool qcom_scm_hdcp_available(void);63extern int qcom_scm_set_remote_state(u32 state, u32 id);
62extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,64
63 u32 *resp);
64extern bool qcom_scm_ocmem_lock_available(void);
65extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
66 u32 size, u32 mode);
67extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
68 u32 size);
69extern bool qcom_scm_pas_supported(u32 peripheral);
70extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,65extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
71 size_t size);66 size_t size);
72extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,67extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
73 phys_addr_t size);68 phys_addr_t size);
74extern int qcom_scm_pas_auth_and_reset(u32 peripheral);69extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
75extern int qcom_scm_pas_shutdown(u32 peripheral);70extern int qcom_scm_pas_shutdown(u32 peripheral);
76extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,71extern bool qcom_scm_pas_supported(u32 peripheral);
77 unsigned int *src,72
78 const struct qcom_scm_vmperm *newvm,73extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
79 unsigned int dest_cnt);74extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
80extern void qcom_scm_cpu_power_down(u32 flags);75
81extern u32 qcom_scm_get_version(void);
82extern int qcom_scm_set_remote_state(u32 state, u32 id);
83extern bool qcom_scm_restore_sec_cfg_available(void);76extern bool qcom_scm_restore_sec_cfg_available(void);
84extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);77extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
85extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);78extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
86extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);79extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
80extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
81 unsigned int *src,
82 const struct qcom_scm_vmperm *newvm,
83 unsigned int dest_cnt);
84
85extern bool qcom_scm_ocmem_lock_available(void);
86extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
87 u32 size, u32 mode);
88extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
89 u32 size);
90
91extern bool qcom_scm_hdcp_available(void);
92extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
93 u32 *resp);
94
87extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);95extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
88extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
89extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
90#else96#else
91 97
92#include <linux/errno.h>98#include <linux/errno.h>
93 99
94static inline
95int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
96{
97 return -ENODEV;
98}
99static inline
100int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
101{
102 return -ENODEV;
103}
104static inline bool qcom_scm_is_available(void) { return false; }100static inline bool qcom_scm_is_available(void) { return false; }
105static inline bool qcom_scm_hdcp_available(void) { return false; }101
106static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,102static inline int qcom_scm_set_cold_boot_addr(void *entry,
107 u32 *resp) { return -ENODEV; }103 const cpumask_t *cpus) { return -ENODEV; }
108static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }104static inline int qcom_scm_set_warm_boot_addr(void *entry,
105 const cpumask_t *cpus) { return -ENODEV; }
106static inline void qcom_scm_cpu_power_down(u32 flags) {}
107static inline u32 qcom_scm_set_remote_state(u32 state,u32 id)
108 { return -ENODEV; }
109
109static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,110static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
110 size_t size) { return -ENODEV; }111 size_t size) { return -ENODEV; }
111static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,112static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
112 phys_addr_t size) { return -ENODEV; }113 phys_addr_t size) { return -ENODEV; }
113static inline int114static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
114qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }115 { return -ENODEV; }
115static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }116static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
117static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
118
119static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
120 { return -ENODEV; }
121static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
122 { return -ENODEV; }
123
124static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
125static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
126 { return -ENODEV; }
127static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
128 { return -ENODEV; }
129static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
130 { return -ENODEV; }
116static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,131static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
117 unsigned int *src,132 unsigned int *src, const struct qcom_scm_vmperm *newvm,
118 const struct qcom_scm_vmperm *newvm,133 unsigned int dest_cnt) { return -ENODEV; }
119 unsigned int dest_cnt) { return -ENODEV; }134
120static inline void qcom_scm_cpu_power_down(u32 flags) {}135static inline bool qcom_scm_ocmem_lock_available(void) { return false; }
121static inline u32 qcom_scm_get_version(void) { return 0; }136static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
122static inline u32137 u32 size, u32 mode) { return -ENODEV; }
123qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }138static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id,
124static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }139 u32 offset, u32 size) { return -ENODEV; }
125static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }140
126static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }141static inline bool qcom_scm_hdcp_available(void) { return false; }
127static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; }142static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
128static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }143 u32 *resp) { return -ENODEV; }
129static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }144
145static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
146 { return -ENODEV; }
130#endif147#endif
131#endif148#endif