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Merge tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.6 * SCM major refactoring and cleanup * Properly flag active only power domains as active only * Add SC7180 and SM8150 RPMH power domains * Return EPROBE_DEFER from QMI if packet family is not yet available * tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits) firmware: qcom_scm: Dynamically support SMCCC and legacy conventions firmware: qcom_scm: Remove thin wrappers firmware: qcom_scm: Order functions, definitions by service/command firmware: qcom_scm-32: Add device argument to atomic calls firmware: qcom_scm-32: Create common legacy atomic call firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls firmware: qcom_scm-32: Add funcnum IDs firmware: qcom_scm-32: Use SMC arch wrappers firmware: qcom_scm-64: Improve SMC convention detection firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc firmware: qcom_scm-64: Add SCM results struct firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc firmware: qcom_scm-64: Make SMC macros less magical firmware: qcom_scm: Remove unused qcom_scm_get_version firmware: qcom_scm: Apply consistent naming scheme to command IDs firmware: qcom_scm: Rename macros and structures soc: qcom: rpmhpd: Set 'active_only' for active only power domains firmware: scm: Add stubs for OCMEM and restore_sec_cfg_available dt-bindings: power: rpmpd: Convert rpmpd bindings to yaml ...

Olof Johansson committed 6 years ago

Commit 333505a2 parents a9e3e12 9a434ce16 files · +1504 −1741Browse files

Showing the changes to include/linux (1 of 16 files). Show all

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include/linux/qcom_scm.h+68−51
@@ -1,5 +1,5 @@
11 /* SPDX-License-Identifier: GPL-2.0-only */
2−/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
2+/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
33 * Copyright (C) 2015 Linaro Ltd.
44 */
55 #ifndef __QCOM_SCM_H
@@ -55,77 +55,94 @@ enum qcom_scm_sec_dev_id { · 49 unmodified lines
5555 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
5656
5757 #if IS_ENABLED(CONFIG_QCOM_SCM)
58+extern bool qcom_scm_is_available(void);
59+
5860 extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
5961 extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
60−extern bool qcom_scm_is_available(void);
61−extern bool qcom_scm_hdcp_available(void);
62−extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
63− u32 *resp);
64−extern bool qcom_scm_ocmem_lock_available(void);
65−extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
66− u32 size, u32 mode);
67−extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
68− u32 size);
69−extern bool qcom_scm_pas_supported(u32 peripheral);
62+extern void qcom_scm_cpu_power_down(u32 flags);
63+extern int qcom_scm_set_remote_state(u32 state, u32 id);
64+
7065 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
7166 size_t size);
7267 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
7368 phys_addr_t size);
7469 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
7570 extern int qcom_scm_pas_shutdown(u32 peripheral);
76−extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
77− unsigned int *src,
78− const struct qcom_scm_vmperm *newvm,
79− unsigned int dest_cnt);
80−extern void qcom_scm_cpu_power_down(u32 flags);
81−extern u32 qcom_scm_get_version(void);
82−extern int qcom_scm_set_remote_state(u32 state, u32 id);
71+extern bool qcom_scm_pas_supported(u32 peripheral);
72+
73+extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
74+extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
75+
8376 extern bool qcom_scm_restore_sec_cfg_available(void);
8477 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
8578 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
8679 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
80+extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
81+ unsigned int *src,
82+ const struct qcom_scm_vmperm *newvm,
83+ unsigned int dest_cnt);
84+
85+extern bool qcom_scm_ocmem_lock_available(void);
86+extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
87+ u32 size, u32 mode);
88+extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
89+ u32 size);
90+
91+extern bool qcom_scm_hdcp_available(void);
92+extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
93+ u32 *resp);
94+
8795 extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
88−extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
89−extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
9096 #else
9197
9298 #include <linux/errno.h>
9399
94−static inline
95−int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
96−{
97− return -ENODEV;
98−}
99−static inline
100−int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
101−{
102− return -ENODEV;
103−}
104100 static inline bool qcom_scm_is_available(void) { return false; }
105−static inline bool qcom_scm_hdcp_available(void) { return false; }
106−static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
107− u32 *resp) { return -ENODEV; }
108−static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
101+
102+static inline int qcom_scm_set_cold_boot_addr(void *entry,
103+ const cpumask_t *cpus) { return -ENODEV; }
104+static inline int qcom_scm_set_warm_boot_addr(void *entry,
105+ const cpumask_t *cpus) { return -ENODEV; }
106+static inline void qcom_scm_cpu_power_down(u32 flags) {}
107+static inline u32 qcom_scm_set_remote_state(u32 state,u32 id)
108+ { return -ENODEV; }
109+
109110 static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
110− size_t size) { return -ENODEV; }
111+ size_t size) { return -ENODEV; }
111112 static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
112− phys_addr_t size) { return -ENODEV; }
113−static inline int
114−qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
113+ phys_addr_t size) { return -ENODEV; }
114+static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
115+ { return -ENODEV; }
115116 static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
117+static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
118+
119+static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
120+ { return -ENODEV; }
121+static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
122+ { return -ENODEV; }
123+
124+static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
125+static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
126+ { return -ENODEV; }
127+static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
128+ { return -ENODEV; }
129+static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
130+ { return -ENODEV; }
116131 static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
117− unsigned int *src,
118− const struct qcom_scm_vmperm *newvm,
119− unsigned int dest_cnt) { return -ENODEV; }
120−static inline void qcom_scm_cpu_power_down(u32 flags) {}
121−static inline u32 qcom_scm_get_version(void) { return 0; }
122−static inline u32
123−qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
124−static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
125−static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
126−static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
127−static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; }
128−static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
129−static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
132+ unsigned int *src, const struct qcom_scm_vmperm *newvm,
133+ unsigned int dest_cnt) { return -ENODEV; }
134+
135+static inline bool qcom_scm_ocmem_lock_available(void) { return false; }
136+static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
137+ u32 size, u32 mode) { return -ENODEV; }
138+static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id,
139+ u32 offset, u32 size) { return -ENODEV; }
140+
141+static inline bool qcom_scm_hdcp_available(void) { return false; }
142+static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
143+ u32 *resp) { return -ENODEV; }
144+
145+static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
146+ { return -ENODEV; }
130147 #endif
131148 #endif