lael-labs/linux

Documentation/devicetree/bindings/display/msm/dp-controller.yaml+146−0

@@ -0,0 +1,146 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: MSM Display Port Controller
	8
	9	maintainers:
	10	- Kuogee Hsieh <khsieh@codeaurora.org>
	11
	12	description: \|
	13	Device tree bindings for DisplayPort host controller for MSM targets
	14	that are compatible with VESA DisplayPort interface specification.
	15
	16	properties:
	17	compatible:
	18	enum:
	19	- qcom,sc7180-dp
	20
	21	reg:
	22	maxItems: 1
	23
	24	interrupts:
	25	maxItems: 1
	26
	27	clocks:
	28	items:
	29	- description: AHB clock to enable register access
	30	- description: Display Port AUX clock
	31	- description: Display Port Link clock
	32	- description: Link interface clock between DP and PHY
	33	- description: Display Port Pixel clock
	34
	35	clock-names:
	36	items:
	37	- const: core_iface
	38	- const: core_aux
	39	- const: ctrl_link
	40	- const: ctrl_link_iface
	41	- const: stream_pixel
	42
	43	assigned-clocks:
	44	items:
	45	- description: link clock source
	46	- description: pixel clock source
	47
	48	assigned-clock-parents:
	49	items:
	50	- description: phy 0 parent
	51	- description: phy 1 parent
	52
	53	phys:
	54	maxItems: 1
	55
	56	phy-names:
	57	items:
	58	- const: dp
	59
	60	operating-points-v2:
	61	maxItems: 1
	62
	63	power-domains:
	64	maxItems: 1
	65
	66	"#sound-dai-cells":
	67	const: 0
	68
	69	ports:
	70	$ref: /schemas/graph.yaml#/properties/ports
	71	properties:
	72	port@0:
	73	$ref: /schemas/graph.yaml#/properties/port
	74	description: Input endpoint of the controller
	75
	76	port@1:
	77	$ref: /schemas/graph.yaml#/properties/port
	78	description: Output endpoint of the controller
	79
	80	required:
	81	- compatible
	82	- reg
	83	- interrupts
	84	- clocks
	85	- clock-names
	86	- phys
	87	- phy-names
	88	- "#sound-dai-cells"
	89	- power-domains
	90	- ports
	91
	92	additionalProperties: false
	93
	94	examples:
	95	- \|
	96	#include <dt-bindings/interrupt-controller/arm-gic.h>
	97	#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
	98	#include <dt-bindings/power/qcom-aoss-qmp.h>
	99	#include <dt-bindings/power/qcom-rpmpd.h>
	100
	101	displayport-controller@ae90000 {
	102	compatible = "qcom,sc7180-dp";
	103	reg = <0xae90000 0x1400>;
	104	interrupt-parent = <&mdss>;
	105	interrupts = <12>;
	106	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	107	<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
	108	<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
	109	<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
	110	<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
	111	clock-names = "core_iface", "core_aux",
	112	"ctrl_link",
	113	"ctrl_link_iface", "stream_pixel";
	114
	115	assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
	116	<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
	117
	118	assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
	119
	120	phys = <&dp_phy>;
	121	phy-names = "dp";
	122
	123	#sound-dai-cells = <0>;
	124
	125	power-domains = <&rpmhpd SC7180_CX>;
	126
	127	ports {
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130
	131	port@0 {
	132	reg = <0>;
	133	endpoint {
	134	remote-endpoint = <&dpu_intf0_out>;
	135	};
	136	};
	137
	138	port@1 {
	139	reg = <1>;
	140	endpoint {
	141	remote-endpoint = <&typec>;
	142	};
	143	};
	144	};
	145	};
	146	...

Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml+228−0

@@ -0,0 +1,228 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Display DPU dt properties for SC7180 target
	8
	9	maintainers:
	10	- Krishna Manikandan <mkrishn@codeaurora.org>
	11
	12	description: \|
	13	Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
	14	sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
	15	bindings of MDSS and DPU are mentioned for SC7180 target.
	16
	17	properties:
	18	compatible:
	19	items:
	20	- const: qcom,sc7180-mdss
	21
	22	reg:
	23	maxItems: 1
	24
	25	reg-names:
	26	const: mdss
	27
	28	power-domains:
	29	maxItems: 1
	30
	31	clocks:
	32	items:
	33	- description: Display AHB clock from gcc
	34	- description: Display AHB clock from dispcc
	35	- description: Display core clock
	36
	37	clock-names:
	38	items:
	39	- const: iface
	40	- const: ahb
	41	- const: core
	42
	43	interrupts:
	44	maxItems: 1
	45
	46	interrupt-controller: true
	47
	48	"#address-cells": true
	49
	50	"#size-cells": true
	51
	52	"#interrupt-cells":
	53	const: 1
	54
	55	iommus:
	56	items:
	57	- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
	58
	59	ranges: true
	60
	61	interconnects:
	62	items:
	63	- description: Interconnect path specifying the port ids for data bus
	64
	65	interconnect-names:
	66	const: mdp0-mem
	67
	68	patternProperties:
	69	"^display-controller@[0-9a-f]+$":
	70	type: object
	71	description: Node containing the properties of DPU.
	72
	73	properties:
	74	compatible:
	75	items:
	76	- const: qcom,sc7180-dpu
	77
	78	reg:
	79	items:
	80	- description: Address offset and size for mdp register set
	81	- description: Address offset and size for vbif register set
	82
	83	reg-names:
	84	items:
	85	- const: mdp
	86	- const: vbif
	87
	88	clocks:
	89	items:
	90	- description: Display hf axi clock
	91	- description: Display ahb clock
	92	- description: Display rotator clock
	93	- description: Display lut clock
	94	- description: Display core clock
	95	- description: Display vsync clock
	96
	97	clock-names:
	98	items:
	99	- const: bus
	100	- const: iface
	101	- const: rot
	102	- const: lut
	103	- const: core
	104	- const: vsync
	105
	106	interrupts:
	107	maxItems: 1
	108
	109	power-domains:
	110	maxItems: 1
	111
	112	operating-points-v2: true
	113
	114	ports:
	115	$ref: /schemas/graph.yaml#/properties/ports
	116	description: \|
	117	Contains the list of output ports from DPU device. These ports
	118	connect to interfaces that are external to the DPU hardware,
	119	such as DSI, DP etc. Each output port contains an endpoint that
	120	describes how it is connected to an external interface.
	121
	122	properties:
	123	port@0:
	124	$ref: /schemas/graph.yaml#/properties/port
	125	description: DPU_INTF1 (DSI1)
	126
	127	port@2:
	128	$ref: /schemas/graph.yaml#/properties/port
	129	description: DPU_INTF0 (DP)
	130
	131	required:
	132	- port@0
	133
	134	required:
	135	- compatible
	136	- reg
	137	- reg-names
	138	- clocks
	139	- interrupts
	140	- power-domains
	141	- operating-points-v2
	142	- ports
	143
	144	required:
	145	- compatible
	146	- reg
	147	- reg-names
	148	- power-domains
	149	- clocks
	150	- interrupts
	151	- interrupt-controller
	152	- iommus
	153	- ranges
	154
	155	additionalProperties: false
	156
	157	examples:
	158	- \|
	159	#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
	160	#include <dt-bindings/clock/qcom,gcc-sc7180.h>
	161	#include <dt-bindings/interrupt-controller/arm-gic.h>
	162	#include <dt-bindings/interconnect/qcom,sdm845.h>
	163	#include <dt-bindings/power/qcom-rpmpd.h>
	164
	165	display-subsystem@ae00000 {
	166	#address-cells = <1>;
	167	#size-cells = <1>;
	168	compatible = "qcom,sc7180-mdss";
	169	reg = <0xae00000 0x1000>;
	170	reg-names = "mdss";
	171	power-domains = <&dispcc MDSS_GDSC>;
	172	clocks = <&gcc GCC_DISP_AHB_CLK>,
	173	<&dispcc DISP_CC_MDSS_AHB_CLK>,
	174	<&dispcc DISP_CC_MDSS_MDP_CLK>;
	175	clock-names = "iface", "ahb", "core";
	176
	177	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	178	interrupt-controller;
	179	#interrupt-cells = <1>;
	180
	181	interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
	182	interconnect-names = "mdp0-mem";
	183
	184	iommus = <&apps_smmu 0x800 0x2>;
	185	ranges;
	186
	187	display-controller@ae01000 {
	188	compatible = "qcom,sc7180-dpu";
	189	reg = <0x0ae01000 0x8f000>,
	190	<0x0aeb0000 0x2008>;
	191
	192	reg-names = "mdp", "vbif";
	193
	194	clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
	195	<&dispcc DISP_CC_MDSS_AHB_CLK>,
	196	<&dispcc DISP_CC_MDSS_ROT_CLK>,
	197	<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
	198	<&dispcc DISP_CC_MDSS_MDP_CLK>,
	199	<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	200	clock-names = "bus", "iface", "rot", "lut", "core",
	201	"vsync";
	202
	203	interrupt-parent = <&mdss>;
	204	interrupts = <0>;
	205	power-domains = <&rpmhpd SC7180_CX>;
	206	operating-points-v2 = <&mdp_opp_table>;
	207
	208	ports {
	209	#address-cells = <1>;
	210	#size-cells = <0>;
	211
	212	port@0 {
	213	reg = <0>;
	214	dpu_intf1_out: endpoint {
	215	remote-endpoint = <&dsi0_in>;
	216	};
	217	};
	218
	219	port@2 {
	220	reg = <2>;
	221	dpu_intf0_out: endpoint {
	222	remote-endpoint = <&dp_in>;
	223	};
	224	};
	225	};
	226	};
	227	};
	228	...

Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml+212−0

@@ -0,0 +1,212 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Display DPU dt properties for SDM845 target
	8
	9	maintainers:
	10	- Krishna Manikandan <mkrishn@codeaurora.org>
	11
	12	description: \|
	13	Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
	14	sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
	15	bindings of MDSS and DPU are mentioned for SDM845 target.
	16
	17	properties:
	18	compatible:
	19	items:
	20	- const: qcom,sdm845-mdss
	21
	22	reg:
	23	maxItems: 1
	24
	25	reg-names:
	26	const: mdss
	27
	28	power-domains:
	29	maxItems: 1
	30
	31	clocks:
	32	items:
	33	- description: Display AHB clock from gcc
	34	- description: Display AXI clock
	35	- description: Display core clock
	36
	37	clock-names:
	38	items:
	39	- const: iface
	40	- const: bus
	41	- const: core
	42
	43	interrupts:
	44	maxItems: 1
	45
	46	interrupt-controller: true
	47
	48	"#address-cells": true
	49
	50	"#size-cells": true
	51
	52	"#interrupt-cells":
	53	const: 1
	54
	55	iommus:
	56	items:
	57	- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
	58	- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
	59
	60	ranges: true
	61
	62	patternProperties:
	63	"^display-controller@[0-9a-f]+$":
	64	type: object
	65	description: Node containing the properties of DPU.
	66
	67	properties:
	68	compatible:
	69	items:
	70	- const: qcom,sdm845-dpu
	71
	72	reg:
	73	items:
	74	- description: Address offset and size for mdp register set
	75	- description: Address offset and size for vbif register set
	76
	77	reg-names:
	78	items:
	79	- const: mdp
	80	- const: vbif
	81
	82	clocks:
	83	items:
	84	- description: Display ahb clock
	85	- description: Display axi clock
	86	- description: Display core clock
	87	- description: Display vsync clock
	88
	89	clock-names:
	90	items:
	91	- const: iface
	92	- const: bus
	93	- const: core
	94	- const: vsync
	95
	96	interrupts:
	97	maxItems: 1
	98
	99	power-domains:
	100	maxItems: 1
	101
	102	operating-points-v2: true
	103	ports:
	104	$ref: /schemas/graph.yaml#/properties/ports
	105	description: \|
	106	Contains the list of output ports from DPU device. These ports
	107	connect to interfaces that are external to the DPU hardware,
	108	such as DSI, DP etc. Each output port contains an endpoint that
	109	describes how it is connected to an external interface.
	110
	111	properties:
	112	port@0:
	113	$ref: /schemas/graph.yaml#/properties/port
	114	description: DPU_INTF1 (DSI1)
	115
	116	port@1:
	117	$ref: /schemas/graph.yaml#/properties/port
	118	description: DPU_INTF2 (DSI2)
	119
	120	required:
	121	- port@0
	122	- port@1
	123
	124	required:
	125	- compatible
	126	- reg
	127	- reg-names
	128	- clocks
	129	- interrupts
	130	- power-domains
	131	- operating-points-v2
	132	- ports
	133
	134	required:
	135	- compatible
	136	- reg
	137	- reg-names
	138	- power-domains
	139	- clocks
	140	- interrupts
	141	- interrupt-controller
	142	- iommus
	143	- ranges
	144
	145	additionalProperties: false
	146
	147	examples:
	148	- \|
	149	#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
	150	#include <dt-bindings/clock/qcom,gcc-sdm845.h>
	151	#include <dt-bindings/interrupt-controller/arm-gic.h>
	152	#include <dt-bindings/power/qcom-rpmpd.h>
	153
	154	display-subsystem@ae00000 {
	155	#address-cells = <1>;
	156	#size-cells = <1>;
	157	compatible = "qcom,sdm845-mdss";
	158	reg = <0x0ae00000 0x1000>;
	159	reg-names = "mdss";
	160	power-domains = <&dispcc MDSS_GDSC>;
	161
	162	clocks = <&gcc GCC_DISP_AHB_CLK>,
	163	<&gcc GCC_DISP_AXI_CLK>,
	164	<&dispcc DISP_CC_MDSS_MDP_CLK>;
	165	clock-names = "iface", "bus", "core";
	166
	167	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	168	interrupt-controller;
	169	#interrupt-cells = <1>;
	170
	171	iommus = <&apps_smmu 0x880 0x8>,
	172	<&apps_smmu 0xc80 0x8>;
	173	ranges;
	174
	175	display-controller@ae01000 {
	176	compatible = "qcom,sdm845-dpu";
	177	reg = <0x0ae01000 0x8f000>,
	178	<0x0aeb0000 0x2008>;
	179	reg-names = "mdp", "vbif";
	180
	181	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	182	<&dispcc DISP_CC_MDSS_AXI_CLK>,
	183	<&dispcc DISP_CC_MDSS_MDP_CLK>,
	184	<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	185	clock-names = "iface", "bus", "core", "vsync";
	186
	187	interrupt-parent = <&mdss>;
	188	interrupts = <0>;
	189	power-domains = <&rpmhpd SDM845_CX>;
	190	operating-points-v2 = <&mdp_opp_table>;
	191
	192	ports {
	193	#address-cells = <1>;
	194	#size-cells = <0>;
	195
	196	port@0 {
	197	reg = <0>;
	198	dpu_intf1_out: endpoint {
	199	remote-endpoint = <&dsi0_in>;
	200	};
	201	};
	202
	203	port@1 {
	204	reg = <1>;
	205	dpu_intf2_out: endpoint {
	206	remote-endpoint = <&dsi1_in>;
	207	};
	208	};
	209	};
	210	};
	211	};
	212	...

Documentation/devicetree/bindings/display/msm/dpu.txt+0−141

@@ -1,141 +0,0 @@
1	Qualcomm Technologies, Inc. DPU KMS
2
3	Description:
4
5	Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
6	sub-blocks like DPU display controller, DSI and DP interfaces etc.
7	The DPU display controller is found in SDM845 SoC.
8
9	MDSS:
10	Required properties:
11	- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
12	- reg: physical base address and length of controller's registers.
13	- reg-names: register region names. The following region is required:
14	* "mdss"
15	- power-domains: a power domain consumer specifier according to
16	Documentation/devicetree/bindings/power/power_domain.txt
17	- clocks: list of clock specifiers for clocks needed by the device.
18	- clock-names: device clock names, must be in same order as clocks property.
19	The following clocks are required:
20	* "iface"
21	* "bus"
22	* "core"
23	- interrupts: interrupt signal from MDSS.
24	- interrupt-controller: identifies the node as an interrupt controller.
25	- #interrupt-cells: specifies the number of cells needed to encode an interrupt
26	source, should be 1.
27	- iommus: phandle of iommu device node.
28	- #address-cells: number of address cells for the MDSS children. Should be 1.
29	- #size-cells: Should be 1.
30	- ranges: parent bus address space is the same as the child bus address space.
31	- interconnects : interconnect path specifier for MDSS according to
32	Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
33	2 paths corresponding to 2 AXI ports.
34	- interconnect-names : MDSS will have 2 port names to differentiate between the
35	2 interconnect paths defined with interconnect specifier.
36
37	Optional properties:
38	- assigned-clocks: list of clock specifiers for clocks needing rate assignment
39	- assigned-clock-rates: list of clock frequencies sorted in the same order as
40	the assigned-clocks property.
41
42	MDP:
43	Required properties:
44	- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
45	- reg: physical base address and length of controller's registers.
46	- reg-names : register region names. The following region is required:
47	* "mdp"
48	* "vbif"
49	- clocks: list of clock specifiers for clocks needed by the device.
50	- clock-names: device clock names, must be in same order as clocks property.
51	The following clocks are required.
52	* "bus"
53	* "iface"
54	* "core"
55	* "vsync"
56	- interrupts: interrupt line from DPU to MDSS.
57	- ports: contains the list of output ports from DPU device. These ports connect
58	to interfaces that are external to the DPU hardware, such as DSI, DP etc.
59
60	Each output port contains an endpoint that describes how it is connected to an
61	external interface. These are described by the standard properties documented
62	here:
63	Documentation/devicetree/bindings/graph.txt
64	Documentation/devicetree/bindings/media/video-interfaces.txt
65
66	Port 0 -> DPU_INTF1 (DSI1)
67	Port 1 -> DPU_INTF2 (DSI2)
68
69	Optional properties:
70	- assigned-clocks: list of clock specifiers for clocks needing rate assignment
71	- assigned-clock-rates: list of clock frequencies sorted in the same order as
72	the assigned-clocks property.
73
74	Example:
75
76	mdss: mdss@ae00000 {
77	compatible = "qcom,sdm845-mdss";
78	reg = <0xae00000 0x1000>;
79	reg-names = "mdss";
80
81	power-domains = <&clock_dispcc 0>;
82
83	clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
84	<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
85	clock-names = "iface", "bus", "core";
86
87	assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88	assigned-clock-rates = <300000000>;
89
90	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
91	interrupt-controller;
92	#interrupt-cells = <1>;
93
94	interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
95	<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
96
97	interconnect-names = "mdp0-mem", "mdp1-mem";
98
99	iommus = <&apps_iommu 0>;
100
101	#address-cells = <2>;
102	#size-cells = <1>;
103	ranges = <0 0 0xae00000 0xb2008>;
104
105	mdss_mdp: mdp@ae01000 {
106	compatible = "qcom,sdm845-dpu";
107	reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
108	reg-names = "mdp", "vbif";
109
110	clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
111	<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
112	<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
113	<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
114	clock-names = "iface", "bus", "core", "vsync";
115
116	assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
117	<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
118	assigned-clock-rates = <0 0 300000000 19200000>;
119
120	interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
121
122	ports {
123	#address-cells = <1>;
124	#size-cells = <0>;
125
126	port@0 {
127	reg = <0>;
128	dpu_intf1_out: endpoint {
129	remote-endpoint = <&dsi0_in>;
130	};
131	};
132
133	port@1 {
134	reg = <1>;
135	dpu_intf2_out: endpoint {
136	remote-endpoint = <&dsi1_in>;
137	};
138	};
139	};
140	};
141	};

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml+185−0

@@ -0,0 +1,185 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Display DSI controller
	8
	9	maintainers:
	10	- Krishna Manikandan <mkrishn@codeaurora.org>
	11
	12	allOf:
	13	- $ref: "../dsi-controller.yaml#"
	14
	15	properties:
	16	compatible:
	17	items:
	18	- const: qcom,mdss-dsi-ctrl
	19
	20	reg:
	21	maxItems: 1
	22
	23	reg-names:
	24	const: dsi_ctrl
	25
	26	interrupts:
	27	maxItems: 1
	28
	29	clocks:
	30	items:
	31	- description: Display byte clock
	32	- description: Display byte interface clock
	33	- description: Display pixel clock
	34	- description: Display escape clock
	35	- description: Display AHB clock
	36	- description: Display AXI clock
	37
	38	clock-names:
	39	items:
	40	- const: byte
	41	- const: byte_intf
	42	- const: pixel
	43	- const: core
	44	- const: iface
	45	- const: bus
	46
	47	phys:
	48	maxItems: 1
	49
	50	phy-names:
	51	const: dsi
	52
	53	"#address-cells": true
	54
	55	"#size-cells": true
	56
	57	syscon-sfpb:
	58	description: A phandle to mmss_sfpb syscon node (only for DSIv2).
	59	$ref: "/schemas/types.yaml#/definitions/phandle"
	60
	61	qcom,dual-dsi-mode:
	62	type: boolean
	63	description: \|
	64	Indicates if the DSI controller is driving a panel which needs
	65	2 DSI links.
	66
	67	power-domains:
	68	maxItems: 1
	69
	70	operating-points-v2: true
	71
	72	ports:
	73	$ref: "/schemas/graph.yaml#/properties/ports"
	74	description: \|
	75	Contains DSI controller input and output ports as children, each
	76	containing one endpoint subnode.
	77
	78	properties:
	79	port@0:
	80	$ref: "/schemas/graph.yaml#/properties/port"
	81	description: \|
	82	Input endpoints of the controller.
	83	properties:
	84	endpoint:
	85	$ref: /schemas/media/video-interfaces.yaml#
	86	unevaluatedProperties: false
	87	properties:
	88	data-lanes:
	89	maxItems: 4
	90	minItems: 4
	91	items:
	92	enum: [ 0, 1, 2, 3 ]
	93
	94	port@1:
	95	$ref: "/schemas/graph.yaml#/properties/port"
	96	description: \|
	97	Output endpoints of the controller.
	98	properties:
	99	endpoint:
	100	$ref: /schemas/media/video-interfaces.yaml#
	101	unevaluatedProperties: false
	102	properties:
	103	data-lanes:
	104	maxItems: 4
	105	minItems: 4
	106	items:
	107	enum: [ 0, 1, 2, 3 ]
	108
	109	required:
	110	- port@0
	111	- port@1
	112
	113	required:
	114	- compatible
	115	- reg
	116	- reg-names
	117	- interrupts
	118	- clocks
	119	- clock-names
	120	- phys
	121	- phy-names
	122	- power-domains
	123	- operating-points-v2
	124	- ports
	125
	126	additionalProperties: false
	127
	128	examples:
	129	- \|
	130	#include <dt-bindings/interrupt-controller/arm-gic.h>
	131	#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
	132	#include <dt-bindings/clock/qcom,gcc-sdm845.h>
	133	#include <dt-bindings/power/qcom-rpmpd.h>
	134
	135	dsi@ae94000 {
	136	compatible = "qcom,mdss-dsi-ctrl";
	137	reg = <0x0ae94000 0x400>;
	138	reg-names = "dsi_ctrl";
	139
	140	#address-cells = <1>;
	141	#size-cells = <0>;
	142
	143	interrupt-parent = <&mdss>;
	144	interrupts = <4>;
	145
	146	clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
	147	<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
	148	<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
	149	<&dispcc DISP_CC_MDSS_ESC0_CLK>,
	150	<&dispcc DISP_CC_MDSS_AHB_CLK>,
	151	<&dispcc DISP_CC_MDSS_AXI_CLK>;
	152	clock-names = "byte",
	153	"byte_intf",
	154	"pixel",
	155	"core",
	156	"iface",
	157	"bus";
	158
	159	phys = <&dsi0_phy>;
	160	phy-names = "dsi";
	161
	162	power-domains = <&rpmhpd SC7180_CX>;
	163	operating-points-v2 = <&dsi_opp_table>;
	164
	165	ports {
	166	#address-cells = <1>;
	167	#size-cells = <0>;
	168
	169	port@0 {
	170	reg = <0>;
	171	dsi0_in: endpoint {
	172	remote-endpoint = <&dpu_intf1_out>;
	173	};
	174	};
	175
	176	port@1 {
	177	reg = <1>;
	178	dsi0_out: endpoint {
	179	remote-endpoint = <&sn65dsi86_in>;
	180	data-lanes = <0 1 2 3>;
	181	};
	182	};
	183	};
	184	};
	185	...

Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml+68−0

@@ -0,0 +1,68 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Display DSI 10nm PHY
	8
	9	maintainers:
	10	- Krishna Manikandan <mkrishn@codeaurora.org>
	11
	12	allOf:
	13	- $ref: dsi-phy-common.yaml#
	14
	15	properties:
	16	compatible:
	17	oneOf:
	18	- const: qcom,dsi-phy-10nm
	19	- const: qcom,dsi-phy-10nm-8998
	20
	21	reg:
	22	items:
	23	- description: dsi phy register set
	24	- description: dsi phy lane register set
	25	- description: dsi pll register set
	26
	27	reg-names:
	28	items:
	29	- const: dsi_phy
	30	- const: dsi_phy_lane
	31	- const: dsi_pll
	32
	33	vdds-supply:
	34	description: \|
	35	Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
	36	connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
	37
	38	required:
	39	- compatible
	40	- reg
	41	- reg-names
	42	- vdds-supply
	43
	44	unevaluatedProperties: false
	45
	46	examples:
	47	- \|
	48	#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
	49	#include <dt-bindings/clock/qcom,rpmh.h>
	50
	51	dsi-phy@ae94400 {
	52	compatible = "qcom,dsi-phy-10nm";
	53	reg = <0x0ae94400 0x200>,
	54	<0x0ae94600 0x280>,
	55	<0x0ae94a00 0x1e0>;
	56	reg-names = "dsi_phy",
	57	"dsi_phy_lane",
	58	"dsi_pll";
	59
	60	#clock-cells = <1>;
	61	#phy-cells = <0>;
	62
	63	vdds-supply = <&vdda_mipi_dsi0_pll>;
	64	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	65	<&rpmhcc RPMH_CXO_CLK>;
	66	clock-names = "iface", "ref";
	67	};
	68	...

Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml+66−0

@@ -0,0 +1,66 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Display DSI 14nm PHY
	8
	9	maintainers:
	10	- Krishna Manikandan <mkrishn@codeaurora.org>
	11
	12	allOf:
	13	- $ref: dsi-phy-common.yaml#
	14
	15	properties:
	16	compatible:
	17	oneOf:
	18	- const: qcom,dsi-phy-14nm
	19	- const: qcom,dsi-phy-14nm-660
	20
	21	reg:
	22	items:
	23	- description: dsi phy register set
	24	- description: dsi phy lane register set
	25	- description: dsi pll register set
	26
	27	reg-names:
	28	items:
	29	- const: dsi_phy
	30	- const: dsi_phy_lane
	31	- const: dsi_pll
	32
	33	vcca-supply:
	34	description: Phandle to vcca regulator device node.
	35
	36	required:
	37	- compatible
	38	- reg
	39	- reg-names
	40	- vcca-supply
	41
	42	unevaluatedProperties: false
	43
	44	examples:
	45	- \|
	46	#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
	47	#include <dt-bindings/clock/qcom,rpmh.h>
	48
	49	dsi-phy@ae94400 {
	50	compatible = "qcom,dsi-phy-14nm";
	51	reg = <0x0ae94400 0x200>,
	52	<0x0ae94600 0x280>,
	53	<0x0ae94a00 0x1e0>;
	54	reg-names = "dsi_phy",
	55	"dsi_phy_lane",
	56	"dsi_pll";
	57
	58	#clock-cells = <1>;
	59	#phy-cells = <0>;
	60
	61	vcca-supply = <&vcca_reg>;
	62	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	63	<&rpmhcc RPMH_CXO_CLK>;
	64	clock-names = "iface", "ref";
	65	};
	66	...

Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml+71−0

@@ -0,0 +1,71 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Display DSI 20nm PHY
	8
	9	maintainers:
	10	- Krishna Manikandan <mkrishn@codeaurora.org>
	11
	12	allOf:
	13	- $ref: dsi-phy-common.yaml#
	14
	15	properties:
	16	compatible:
	17	oneOf:
	18	- const: qcom,dsi-phy-20nm
	19
	20	reg:
	21	items:
	22	- description: dsi pll register set
	23	- description: dsi phy register set
	24	- description: dsi phy regulator register set
	25
	26	reg-names:
	27	items:
	28	- const: dsi_pll
	29	- const: dsi_phy
	30	- const: dsi_phy_regulator
	31
	32	vcca-supply:
	33	description: Phandle to vcca regulator device node.
	34
	35	vddio-supply:
	36	description: Phandle to vdd-io regulator device node.
	37
	38	required:
	39	- compatible
	40	- reg
	41	- reg-names
	42	- vddio-supply
	43	- vcca-supply
	44
	45	unevaluatedProperties: false
	46
	47	examples:
	48	- \|
	49	#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
	50	#include <dt-bindings/clock/qcom,rpmh.h>
	51
	52	dsi-phy@fd922a00 {
	53	compatible = "qcom,dsi-phy-20nm";
	54	reg = <0xfd922a00 0xd4>,
	55	<0xfd922b00 0x2b0>,
	56	<0xfd922d80 0x7b>;
	57	reg-names = "dsi_pll",
	58	"dsi_phy",
	59	"dsi_phy_regulator";
	60
	61	#clock-cells = <1>;
	62	#phy-cells = <0>;
	63
	64	vcca-supply = <&vcca_reg>;
	65	vddio-supply = <&vddio_reg>;
	66
	67	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	68	<&rpmhcc RPMH_CXO_CLK>;
	69	clock-names = "iface", "ref";
	70	};
	71	...

Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml+68−0

@@ -0,0 +1,68 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm Display DSI 28nm PHY
	8
	9	maintainers:
	10	- Krishna Manikandan <mkrishn@codeaurora.org>
	11
	12	allOf:
	13	- $ref: dsi-phy-common.yaml#
	14
	15	properties:
	16	compatible:
	17	oneOf:
	18	- const: qcom,dsi-phy-28nm-hpm
	19	- const: qcom,dsi-phy-28nm-lp
	20	- const: qcom,dsi-phy-28nm-8960
	21
	22	reg:
	23	items:
	24	- description: dsi pll register set
	25	- description: dsi phy register set
	26	- description: dsi phy regulator register set
	27
	28	reg-names:
	29	items:
	30	- const: dsi_pll
	31	- const: dsi_phy
	32	- const: dsi_phy_regulator
	33
	34	vddio-supply:
	35	description: Phandle to vdd-io regulator device node.
	36
	37	required:
	38	- compatible
	39	- reg
	40	- reg-names
	41	- vddio-supply
	42
	43	unevaluatedProperties: false
	44
	45	examples:
	46	- \|
	47	#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
	48	#include <dt-bindings/clock/qcom,rpmh.h>
	49
	50	dsi-phy@fd922a00 {
	51	compatible = "qcom,dsi-phy-28nm-lp";
	52	reg = <0xfd922a00 0xd4>,
	53	<0xfd922b00 0x2b0>,
	54	<0xfd922d80 0x7b>;
	55	reg-names = "dsi_pll",
	56	"dsi_phy",
	57	"dsi_phy_regulator";
	58
	59	#clock-cells = <1>;
	60	#phy-cells = <0>;
	61
	62	vddio-supply = <&vddio_reg>;
	63
	64	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	65	<&rpmhcc RPMH_CXO_CLK>;
	66	clock-names = "iface", "ref";
	67	};
	68	...

Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml+40−0

@@ -0,0 +1,40 @@
	1	# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Description of Qualcomm Display DSI PHY common dt properties
	8
	9	maintainers:
	10	- Krishna Manikandan <mkrishn@codeaurora.org>
	11
	12	description: \|
	13	This defines the DSI PHY dt properties which are common for all
	14	dsi phy versions.
	15
	16	properties:
	17	"#clock-cells":
	18	const: 1
	19
	20	"#phy-cells":
	21	const: 0
	22
	23	clocks:
	24	items:
	25	- description: Display AHB clock
	26	- description: Board XO source
	27
	28	clock-names:
	29	items:
	30	- const: iface
	31	- const: ref
	32
	33	required:
	34	- clocks
	35	- clock-names
	36	- "#clock-cells"
	37	- "#phy-cells"
	38
	39	additionalProperties: true
	40	...

Documentation/devicetree/bindings/display/msm/dsi.txt+0−249

@@ -1,249 +0,0 @@
1	Qualcomm Technologies Inc. adreno/snapdragon DSI output
2
3	DSI Controller:
4	Required properties:
5	- compatible:
6	* "qcom,mdss-dsi-ctrl"
7	- reg: Physical base address and length of the registers of controller
8	- reg-names: The names of register regions. The following regions are required:
9	* "dsi_ctrl"
10	- interrupts: The interrupt signal from the DSI block.
11	- power-domains: Should be <&mmcc MDSS_GDSC>.
12	- clocks: Phandles to device clocks.
13	- clock-names: the following clocks are required:
14	* "mdp_core"
15	* "iface"
16	* "bus"
17	* "core_mmss"
18	* "byte"
19	* "pixel"
20	* "core"
21	For DSIv2, we need an additional clock:
22	* "src"
23	For DSI6G v2.0 onwards, we need also need the clock:
24	* "byte_intf"
25	- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26	- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
27	by a DSI PHY block. See [1] for details on clock bindings.
28	- vdd-supply: phandle to vdd regulator device node
29	- vddio-supply: phandle to vdd-io regulator device node
30	- vdda-supply: phandle to vdda regulator device node
31	- phys: phandle to DSI PHY device node
32	- phy-names: the name of the corresponding PHY device
33	- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34	- ports: Contains 2 DSI controller ports as child nodes. Each port contains
35	an endpoint subnode as defined in [2] and [3].
36
37	Optional properties:
38	- panel@0: Node of panel connected to this DSI controller.
39	See files in [4] for each supported panel.
40	- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
41	driving a panel which needs 2 DSI links.
42	- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43	the master link of the 2-DSI panel.
44	- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45	driving a 2-DSI panel whose 2 links need receive command simultaneously.
46	- pinctrl-names: the pin control state names; should contain "default"
47	- pinctrl-0: the default pinctrl state (active)
48	- pinctrl-n: the "sleep" pinctrl state
49	- ports: contains DSI controller input and output ports as children, each
50	containing one endpoint subnode.
51
52	DSI Endpoint properties:
53	- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
54	input endpoint. For port@1, set to the MDP interface output. See [2] for
55	device graph info.
56
57	- data-lanes: this describes how the physical DSI data lanes are mapped
58	to the logical lanes on the given platform. The value contained in
59	index n describes what physical lane is mapped to the logical lane n
60	(DATAn, where n lies between 0 and 3). The clock lane position is fixed
61	and can't be changed. Hence, they aren't a part of the DT bindings. See
62	[3] for more info on the data-lanes property.
63
64	For example:
65
66	data-lanes = <3 0 1 2>;
67
68	The above mapping describes that the logical data lane DATA0 is mapped to
69	the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
70	to phys DATA1 and logic DATA3 to phys DATA2.
71
72	There are only a limited number of physical to logical mappings possible:
73	<0 1 2 3>
74	<1 2 3 0>
75	<2 3 0 1>
76	<3 0 1 2>
77	<0 3 2 1>
78	<1 0 3 2>
79	<2 1 0 3>
80	<3 2 1 0>
81
82	DSI PHY:
83	Required properties:
84	- compatible: Could be the following
85	* "qcom,dsi-phy-28nm-hpm"
86	* "qcom,dsi-phy-28nm-lp"
87	* "qcom,dsi-phy-20nm"
88	* "qcom,dsi-phy-28nm-8960"
89	* "qcom,dsi-phy-14nm"
90	* "qcom,dsi-phy-14nm-660"
91	* "qcom,dsi-phy-10nm"
92	* "qcom,dsi-phy-10nm-8998"
93	* "qcom,dsi-phy-7nm"
94	* "qcom,dsi-phy-7nm-8150"
95	- reg: Physical base address and length of the registers of PLL, PHY. Some
96	revisions require the PHY regulator base address, whereas others require the
97	PHY lane base address. See below for each PHY revision.
98	- reg-names: The names of register regions. The following regions are required:
99	For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
100	* "dsi_pll"
101	* "dsi_phy"
102	* "dsi_phy_regulator"
103	For DSI 14nm, 10nm and 7nm PHYs:
104	* "dsi_pll"
105	* "dsi_phy"
106	* "dsi_phy_lane"
107	- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
108	2 clocks: A byte clock (index 0), and a pixel clock (index 1).
109	- power-domains: Should be <&mmcc MDSS_GDSC>.
110	- clocks: Phandles to device clocks. See [1] for details on clock bindings.
111	- clock-names: the following clocks are required:
112	* "iface"
113	* "ref" (only required for new DTS files/entries)
114	For 28nm HPM/LP, 28nm 8960 PHYs:
115	- vddio-supply: phandle to vdd-io regulator device node
116	For 20nm PHY:
117	- vddio-supply: phandle to vdd-io regulator device node
118	- vcca-supply: phandle to vcca regulator device node
119	For 14nm PHY:
120	- vcca-supply: phandle to vcca regulator device node
121	For 10nm and 7nm PHY:
122	- vdds-supply: phandle to vdds regulator device node
123
124	Optional properties:
125	- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
126	regulator is wanted.
127	- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
128	panels in microseconds. Driver uses this number to adjust
129	the clock rate according to the expected transfer time.
130	Increasing this value would slow down the mdp processing
131	and can result in slower performance.
132	Decreasing this value can speed up the mdp processing,
133	but this can also impact power consumption.
134	As a rule this time should not be higher than the time
135	that would be expected with the processing at the
136	dsi link rate since anyways this would be the maximum
137	transfer time that could be achieved.
138	If ping pong split is enabled, this time should not be higher
139	than two times the dsi link rate time.
140	If the property is not specified, then the default value is 14000 us.
141
142	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
143	[2] Documentation/devicetree/bindings/graph.txt
144	[3] Documentation/devicetree/bindings/media/video-interfaces.txt
145	[4] Documentation/devicetree/bindings/display/panel/
146
147	Example:
148	dsi0: dsi@fd922800 {
149	compatible = "qcom,mdss-dsi-ctrl";
150	qcom,dsi-host-index = <0>;
151	interrupt-parent = <&mdp>;
152	interrupts = <4 0>;
153	reg-names = "dsi_ctrl";
154	reg = <0xfd922800 0x200>;
155	power-domains = <&mmcc MDSS_GDSC>;
156	clock-names =
157	"bus",
158	"byte",
159	"core",
160	"core_mmss",
161	"iface",
162	"mdp_core",
163	"pixel";
164	clocks =
165	<&mmcc MDSS_AXI_CLK>,
166	<&mmcc MDSS_BYTE0_CLK>,
167	<&mmcc MDSS_ESC0_CLK>,
168	<&mmcc MMSS_MISC_AHB_CLK>,
169	<&mmcc MDSS_AHB_CLK>,
170	<&mmcc MDSS_MDP_CLK>,
171	<&mmcc MDSS_PCLK0_CLK>;
172
173	assigned-clocks =
174	<&mmcc BYTE0_CLK_SRC>,
175	<&mmcc PCLK0_CLK_SRC>;
176	assigned-clock-parents =
177	<&dsi_phy0 0>,
178	<&dsi_phy0 1>;
179
180	vdda-supply = <&pma8084_l2>;
181	vdd-supply = <&pma8084_l22>;
182	vddio-supply = <&pma8084_l12>;
183
184	phys = <&dsi_phy0>;
185	phy-names ="dsi-phy";
186
187	qcom,dual-dsi-mode;
188	qcom,master-dsi;
189	qcom,sync-dual-dsi;
190
191	qcom,mdss-mdp-transfer-time-us = <12000>;
192
193	pinctrl-names = "default", "sleep";
194	pinctrl-0 = <&dsi_active>;
195	pinctrl-1 = <&dsi_suspend>;
196
197	ports {
198	#address-cells = <1>;
199	#size-cells = <0>;
200
201	port@0 {
202	reg = <0>;
203	dsi0_in: endpoint {
204	remote-endpoint = <&mdp_intf1_out>;
205	};
206	};
207
208	port@1 {
209	reg = <1>;
210	dsi0_out: endpoint {
211	remote-endpoint = <&panel_in>;
212	data-lanes = <0 1 2 3>;
213	};
214	};
215	};
216
217	panel: panel@0 {
218	compatible = "sharp,lq101r1sx01";
219	reg = <0>;
220	link2 = <&secondary>;
221
222	power-supply = <...>;
223	backlight = <...>;
224
225	port {
226	panel_in: endpoint {
227	remote-endpoint = <&dsi0_out>;
228	};
229	};
230	};
231	};
232
233	dsi_phy0: dsi-phy@fd922a00 {
234	compatible = "qcom,dsi-phy-28nm-hpm";
235	qcom,dsi-phy-index = <0>;
236	reg-names =
237	"dsi_pll",
238	"dsi_phy",
239	"dsi_phy_regulator";
240	reg = <0xfd922a00 0xd4>,
241	<0xfd922b00 0x2b0>,
242	<0xfd922d80 0x7b>;
243	clock-names = "iface";
244	clocks = <&mmcc MDSS_AHB_CLK>;
245	#clock-cells = <1>;
246	vddio-supply = <&pma8084_l12>;
247
248	qcom,dsi-phy-regulator-ldo-mode;
249	};

drivers/gpu/drm/drm_atomic.c+23−5

 /*
  * Copyright (C) 2014 Red Hat
  * Copyright (C) 2014 Intel Corp.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
 }
 EXPORT_SYMBOL(__drm_atomic_helper_set_config);
-void drm_atomic_print_state(const struct drm_atomic_state *state)
+/**
+ * drm_atomic_print_new_state - prints drm atomic state
+ * @state: atomic configuration to check
+ * @p: drm printer
+ *
+ * This functions prints the drm atomic state snapshot using the drm printer
+ * which is passed to it. This snapshot can be used for debugging purposes.
+ *
+ * Note that this function looks into the new state objects and hence its not
+ * safe to be used after the call to drm_atomic_helper_commit_hw_done().
+ */
+void drm_atomic_print_new_state(const struct drm_atomic_state *state,
+		struct drm_printer *p)
 {
-	struct drm_printer p = drm_info_printer(state->dev->dev);
 	struct drm_plane *plane;
 	struct drm_plane_state *plane_state;
 	struct drm_crtc *crtc;
 	struct drm_connector_state *connector_state;
 	int i;
+	if (!p) {
+		DRM_ERROR("invalid drm printer\n");
+		return;
+	}
 	DRM_DEBUG_ATOMIC("checking %p\n", state);
 	for_each_new_plane_in_state(state, plane, plane_state, i)
-		drm_atomic_plane_print_state(&p, plane_state);
+		drm_atomic_plane_print_state(p, plane_state);
 	for_each_new_crtc_in_state(state, crtc, crtc_state, i)
-		drm_atomic_crtc_print_state(&p, crtc_state);
+		drm_atomic_crtc_print_state(p, crtc_state);
 	for_each_new_connector_in_state(state, connector, connector_state, i)
-		drm_atomic_connector_print_state(&p, connector_state);
+		drm_atomic_connector_print_state(p, connector_state);
 }
+EXPORT_SYMBOL(drm_atomic_print_new_state);
 static void __drm_state_dump(struct drm_device *dev, struct drm_printer *p,
 			     bool take_locks)

drivers/gpu/drm/drm_atomic_uapi.c+3−1

  * Copyright (C) 2014 Red Hat
  * Copyright (C) 2014 Intel Corp.
  * Copyright (C) 2018 Intel Corp.
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
 	struct drm_out_fence_state *fence_state;
 	int ret = 0;
 	unsigned int i, j, num_fences;
+	struct drm_printer p = drm_info_printer(dev->dev);
 	/* disallow for drivers not supporting atomic: */
 	if (!drm_core_check_feature(dev, DRIVER_ATOMIC))
 		ret = drm_atomic_nonblocking_commit(state);
 	} else {
 		if (drm_debug_enabled(DRM_UT_STATE))
-			drm_atomic_print_state(state);
+			drm_atomic_print_new_state(state, &p);
 		ret = drm_atomic_commit(state);
 	}

drivers/gpu/drm/drm_crtc_internal.h+3−1

  *   Jesse Barnes <jesse.barnes@intel.com>
  * Copyright © 2014 Intel Corporation
  *   Daniel Vetter <daniel.vetter@ffwll.ch>
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
 int __drm_atomic_helper_set_config(struct drm_mode_set *set,
 				   struct drm_atomic_state *state);
-void drm_atomic_print_state(const struct drm_atomic_state *state);
+void drm_atomic_print_new_state(const struct drm_atomic_state *state,
+		struct drm_printer *p);
 /* drm_atomic_uapi.c */
 int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state,

drivers/gpu/drm/msm/Makefile+2−1

 	disp/dpu1/dpu_encoder_phys_cmd.o \
 	disp/dpu1/dpu_encoder_phys_vid.o \
 	disp/dpu1/dpu_formats.o \
-	disp/dpu1/dpu_hw_blk.o \
 	disp/dpu1/dpu_hw_catalog.o \
 	disp/dpu1/dpu_hw_ctl.o \
 	disp/dpu1/dpu_hw_interrupts.o \
 	disp/dpu1/dpu_plane.o \
 	disp/dpu1/dpu_rm.o \
 	disp/dpu1/dpu_vbif.o \
+	disp/msm_disp_snapshot.o \
+	disp/msm_disp_snapshot_util.o \
 	msm_atomic.o \
 	msm_atomic_tracepoints.o \
 	msm_debugfs.o \

drivers/gpu/drm/msm/adreno/a2xx.xml.h+42−18

@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16	- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17	- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18	- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19	- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20	- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22	- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23	- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24		24
25	Copyright (C) 2013-2020 by the following authors:	25	Copyright (C) 2013-2021 by the following authors:
26	- Rob Clark <robdclark@gmail.com> (robclark)	26	- Rob Clark <robdclark@gmail.com> (robclark)
27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28		28
@@ -1258,11 +1258,17 @@ static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) · 1229 unmodified lines
1258		1258
1259	#define REG_A2XX_NQWAIT_UNTIL 0x00000394	1259	#define REG_A2XX_NQWAIT_UNTIL 0x00000394
1260		1260
1261	#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395	1261	#define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395
1262		1262
1263	#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397	1263	#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396
1264		1264
1265	#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398	1265	#define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397
		1266
		1267	#define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398
		1268
		1269	#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399
		1270
		1271	#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a
1266		1272
1267	#define REG_A2XX_RBBM_DEBUG 0x0000039b	1273	#define REG_A2XX_RBBM_DEBUG 0x0000039b
1268		1274
@@ -2922,10 +2928,28 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) · 1653 unmodified lines
2922		2928
2923	#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04	2929	#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
2924		2930
		2931	#define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05
		2932
		2933	#define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06
		2934
		2935	#define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07
		2936
2925	#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08	2937	#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
2926		2938
2927	#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09	2939	#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
2928		2940
		2941	#define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a
		2942
		2943	#define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b
		2944
		2945	#define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c
		2946
		2947	#define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d
		2948
		2949	#define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e
		2950
		2951	#define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f
		2952
2929	#define REG_A2XX_SQ_TEX_0 0x00000000	2953	#define REG_A2XX_SQ_TEX_0 0x00000000
2930	#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003	2954	#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
2931	#define A2XX_SQ_TEX_0_TYPE__SHIFT 0	2955	#define A2XX_SQ_TEX_0_TYPE__SHIFT 0

drivers/gpu/drm/msm/adreno/a3xx.xml.h+20−20

@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16	- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17	- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18	- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19	- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20	- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22	- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23	- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24		24
25	Copyright (C) 2013-2020 by the following authors:	25	Copyright (C) 2013-2021 by the following authors:
26	- Rob Clark <robdclark@gmail.com> (robclark)	26	- Rob Clark <robdclark@gmail.com> (robclark)
27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28		28
@@ -1215,7 +1215,7 @@ static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) · 1186 unmodified lines
1215	#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16	1215	#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
1216	static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)	1216	static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
1217	{	1217	{
1218	return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;	1218	return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
1219	}	1219	}
1220		1220
1221	static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }	1221	static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
@@ -1328,7 +1328,7 @@ static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) · 106 unmodified lines
1328	#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16	1328	#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
1329	static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)	1329	static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
1330	{	1330	{
1331	return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;	1331	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
1332	}	1332	}
1333		1333
1334	#define REG_A3XX_RB_BLEND_GREEN 0x000020e5	1334	#define REG_A3XX_RB_BLEND_GREEN 0x000020e5
@@ -1342,7 +1342,7 @@ static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) · 7 unmodified lines
1342	#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16	1342	#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1343	static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)	1343	static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
1344	{	1344	{
1345	return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;	1345	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
1346	}	1346	}
1347		1347
1348	#define REG_A3XX_RB_BLEND_BLUE 0x000020e6	1348	#define REG_A3XX_RB_BLEND_BLUE 0x000020e6
@@ -1356,7 +1356,7 @@ static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) · 7 unmodified lines
1356	#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16	1356	#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1357	static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)	1357	static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
1358	{	1358	{
1359	return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;	1359	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
1360	}	1360	}
1361		1361
1362	#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7	1362	#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
@@ -1370,7 +1370,7 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) · 7 unmodified lines
1370	#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16	1370	#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1371	static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)	1371	static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
1372	{	1372	{
1373	return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;	1373	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
1374	}	1374	}
1375		1375
1376	#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8	1376	#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8

drivers/gpu/drm/msm/adreno/a4xx.xml.h+19−19

@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16	- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17	- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18	- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19	- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20	- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22	- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23	- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24		24
25	Copyright (C) 2013-2020 by the following authors:	25	Copyright (C) 2013-2021 by the following authors:
26	- Rob Clark <robdclark@gmail.com> (robclark)	26	- Rob Clark <robdclark@gmail.com> (robclark)
27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28		28
@@ -1085,7 +1085,7 @@ static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) · 1056 unmodified lines
1085	#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16	1085	#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1086	static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)	1086	static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1087	{	1087	{
1088	return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;	1088	return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1089	}	1089	}
1090		1090
1091	#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1	1091	#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
@@ -1113,7 +1113,7 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) · 21 unmodified lines
1113	#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16	1113	#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1114	static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)	1114	static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1115	{	1115	{
1116	return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;	1116	return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1117	}	1117	}
1118		1118
1119	#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3	1119	#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
@@ -1141,7 +1141,7 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) · 21 unmodified lines
1141	#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16	1141	#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1142	static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)	1142	static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1143	{	1143	{
1144	return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;	1144	return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1145	}	1145	}
1146		1146
1147	#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5	1147	#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
@@ -1169,7 +1169,7 @@ static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) · 21 unmodified lines
1169	#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16	1169	#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1170	static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)	1170	static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1171	{	1171	{
1172	return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;	1172	return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1173	}	1173	}
1174		1174
1175	#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7	1175	#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7

drivers/gpu/drm/msm/adreno/a5xx.xml.h+70−25

 git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-05-27 20:18:13)
-Copyright (C) 2013-2020 by the following authors:
+Copyright (C) 2013-2021 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
 #define A5XX_RBBM_STATUS_HI_BUSY				0x00000001
 #define REG_A5XX_RBBM_STATUS3					0x00000530
+#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000
 #define REG_A5XX_RBBM_INT_0_STATUS				0x000004e1
 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7				0x00000e57
 #define REG_A5XX_VPC_DBG_ECO_CNTL				0x00000e60
+#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS			0x00000400
 #define REG_A5XX_VPC_ADDR_MODE_CNTL				0x00000e61
 #define REG_A5XX_GRAS_CL_CNTL					0x0000e000
 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040
-#define REG_A5XX_UNKNOWN_E001					0x0000e001
+#define REG_A5XX_GRAS_VS_CL_CNTL				0x0000e001
+#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
+#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0
+static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
+{
+	return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
+}
+#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
+#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT			8
+static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
+{
+	return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
+}
 #define REG_A5XX_UNKNOWN_E004					0x0000e004
 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT				16
 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
 {
-	return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
+	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
 }
 #define REG_A5XX_RB_BLEND_RED_F32				0x0000e1a1
 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT			16
 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
 {
-	return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
+	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
 }
 #define REG_A5XX_RB_BLEND_GREEN_F32				0x0000e1a3
 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT				16
 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
 {
-	return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
+	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
 }
 #define REG_A5XX_RB_BLEND_BLUE_F32				0x0000e1a5
 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16
 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
 {
-	return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
+	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
 }
 #define REG_A5XX_RB_BLEND_ALPHA_F32				0x0000e1a7
 #define REG_A5XX_VPC_GS_SIV_CNTL				0x0000e298
-#define REG_A5XX_UNKNOWN_E29A					0x0000e29a
+#define REG_A5XX_VPC_CLIP_CNTL					0x0000e29a
+#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
+#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT			0
+static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
+{
+	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
+}
+#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
+#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT		8
+static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
+{
+	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
+}
+#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
+#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT		16
+static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
+{
+	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
+}
 #define REG_A5XX_VPC_PACK					0x0000e29d
 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK			0x000000ff
 }
 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE			0x00000040
-#define REG_A5XX_UNKNOWN_E389					0x0000e389
+#define REG_A5XX_PC_CLIP_CNTL					0x0000e389
+#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
+#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT			0
+static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
+{
+	return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
+}
 #define REG_A5XX_PC_RESTART_INDEX				0x0000e38c
 #define REG_A5XX_SP_FS_OBJ_START_HI				0x0000e5c4
 #define REG_A5XX_SP_BLEND_CNTL					0x0000e5c9
-#define A5XX_SP_BLEND_CNTL_ENABLED				0x00000001
+#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
+#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
+static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
+{
+	return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
+}
 #define A5XX_SP_BLEND_CNTL_UNK8					0x00000100
 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
 }
 #define REG_A5XX_TEX_SAMP_2					0x00000002
-#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xfffffff0
+#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xffffff80
-#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT			4
+#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT			7
 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
 {
 	return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
 }
 #define REG_A5XX_TEX_CONST_2					0x00000002
+#define A5XX_TEX_CONST_2_UNK4					0x00000010
 #define A5XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
 #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
 static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
 {
 	return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
 }
+#define A5XX_TEX_CONST_2_UNK31					0x80000000
 #define REG_A5XX_TEX_CONST_3					0x00000003
 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff

drivers/gpu/drm/msm/adreno/a5xx_gpu.c+22−7

 		if (!a5xx_gpu->shadow_bo) {
 			a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
 				sizeof(u32) * gpu->nr_rings,
-				MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
+				MSM_BO_WC | MSM_BO_MAP_PRIV,
 				gpu->aspace, &a5xx_gpu->shadow_bo,
 				&a5xx_gpu->shadow_iova);
 	return true;
 }
-static int a5xx_fault_handler(void *arg, unsigned long iova, int flags)
+static int a5xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
 {
 	struct msm_gpu *gpu = arg;
 	pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)),
 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)));
-	return -EFAULT;
+	return 0;
 }
 static void a5xx_cp_err_irq(struct msm_gpu *gpu)
 	struct drm_device *dev = gpu->dev;
 	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
+	/*
+	 * If stalled on SMMU fault, we could trip the GPU's hang detection,
+	 * but the fault handler will trigger the devcore dump, and we want
+	 * to otherwise resume normally rather than killing the submit, so
+	 * just bail.
+	 */
+	if (gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24))
+		return;
 	DRM_DEV_ERROR(dev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
 		ring ? ring->id : -1, ring ? ring->seqno : 0,
 		gpu_read(gpu, REG_A5XX_RBBM_STATUS),
 		struct a5xx_crashdumper *dumper)
 {
 	dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
-		SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
+		SZ_1M, MSM_BO_WC, gpu->aspace,
 		&dumper->bo, &dumper->iova);
 	if (!IS_ERR(dumper->ptr))
 {
 	struct a5xx_gpu_state *a5xx_state = kzalloc(sizeof(*a5xx_state),
 			GFP_KERNEL);
+	bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24));
 	if (!a5xx_state)
 		return ERR_PTR(-ENOMEM);
 	a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS);
-	/* Get the HLSQ regs with the help of the crashdumper */
+	/*
-	a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
+	 * Get the HLSQ regs with the help of the crashdumper, but only if
+	 * we are not stalled in an iommu fault (in which case the crashdumper
+	 * would not have access to memory)
+	 */
+	if (!stalled)
+		a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
 	a5xx_set_hwcg(gpu, true);
 		nvmem_cell_put(cell);
 	}
-	dev_pm_opp_set_supported_hw(dev, &val, 1);
+	devm_pm_opp_set_supported_hw(dev, &val, 1);
 }
 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)

drivers/gpu/drm/msm/adreno/a5xx_power.c+1−1

@@ -363,7 +363,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) · 362 unmodified lines
363	bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2;	363	bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2;
364		364
365	ptr = msm_gem_kernel_new_locked(drm, bosize,	365	ptr = msm_gem_kernel_new_locked(drm, bosize,
366	MSM_BO_UNCACHED \| MSM_BO_GPU_READONLY, gpu->aspace,	366	MSM_BO_WC \| MSM_BO_GPU_READONLY, gpu->aspace,
367	&a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova);	367	&a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova);
368	if (IS_ERR(ptr))	368	if (IS_ERR(ptr))
369	return;	369	return;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c+2−2

@@ -230,7 +230,7 @@ static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu, · 229 unmodified lines
230		230
231	ptr = msm_gem_kernel_new(gpu->dev,	231	ptr = msm_gem_kernel_new(gpu->dev,
232	A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE,	232	A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE,
233	MSM_BO_UNCACHED \| MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);	233	MSM_BO_WC \| MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
234		234
235	if (IS_ERR(ptr))	235	if (IS_ERR(ptr))
236	return PTR_ERR(ptr);	236	return PTR_ERR(ptr);
@@ -238,7 +238,7 @@ static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu, · 1 unmodified line
238	/* The buffer to store counters needs to be unprivileged */	238	/* The buffer to store counters needs to be unprivileged */
239	counters = msm_gem_kernel_new(gpu->dev,	239	counters = msm_gem_kernel_new(gpu->dev,
240	A5XX_PREEMPT_COUNTER_SIZE,	240	A5XX_PREEMPT_COUNTER_SIZE,
241	MSM_BO_UNCACHED, gpu->aspace, &counters_bo, &counters_iova);	241	MSM_BO_WC, gpu->aspace, &counters_bo, &counters_iova);
242	if (IS_ERR(counters)) {	242	if (IS_ERR(counters)) {
243	msm_gem_kernel_put(bo, gpu->aspace, true);	243	msm_gem_kernel_put(bo, gpu->aspace, true);
244	return PTR_ERR(counters);	244	return PTR_ERR(counters);

drivers/gpu/drm/msm/adreno/a6xx.xml.h+1059−1142

@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16	- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17	- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18	- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19	- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20	- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22	- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23	- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24		24
25	Copyright (C) 2013-2020 by the following authors:	25	Copyright (C) 2013-2021 by the following authors:
26	- Rob Clark <robdclark@gmail.com> (robclark)	26	- Rob Clark <robdclark@gmail.com> (robclark)
27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28		28
@@ -168,7 +168,7 @@ enum a6xx_format { · 139 unmodified lines
168	FMT6_ASTC_10x10 = 204,	168	FMT6_ASTC_10x10 = 204,
169	FMT6_ASTC_12x10 = 205,	169	FMT6_ASTC_12x10 = 205,
170	FMT6_ASTC_12x12 = 206,	170	FMT6_ASTC_12x12 = 206,
171	FMT6_S8Z24_UINT = 234,	171	FMT6_Z24_UINT_S8_UINT = 234,
172	FMT6_NONE = 255,	172	FMT6_NONE = 255,
173	};	173	};
174		174
@@ -907,6 +907,11 @@ enum a6xx_tess_output { · 732 unmodified lines
907	TESS_CCW_TRIS = 3,	907	TESS_CCW_TRIS = 3,
908	};	908	};
909		909
		910	enum a6xx_threadsize {
		911	THREAD64 = 0,
		912	THREAD128 = 1,
		913	};
		914
910	enum a6xx_tex_filter {	915	enum a6xx_tex_filter {
911	A6XX_TEX_NEAREST = 0,	916	A6XX_TEX_NEAREST = 0,
912	A6XX_TEX_LINEAR = 1,	917	A6XX_TEX_LINEAR = 1,
@@ -1007,9 +1012,7 @@ enum a6xx_tex_type { · 94 unmodified lines
1007		1012
1008	#define REG_A6XX_CP_PROTECT_STATUS 0x00000824	1013	#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1009		1014
1010	#define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830	1015	#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
1011
1012	#define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831
1013		1016
1014	#define REG_A6XX_CP_MISC_CNTL 0x00000840	1017	#define REG_A6XX_CP_MISC_CNTL 0x00000840
1015		1018
@@ -1104,33 +1107,7 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) · 88 unmodified lines
1104		1107
1105	#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8	1108	#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1106		1109
1107	#define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0	1110	static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
1108
1109	#define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1
1110
1111	#define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2
1112
1113	#define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3
1114
1115	#define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4
1116
1117	#define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5
1118
1119	#define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6
1120
1121	#define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7
1122
1123	#define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8
1124
1125	#define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9
1126
1127	#define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da
1128
1129	#define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db
1130
1131	#define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc
1132
1133	#define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd
1134		1111
1135	#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900	1112	#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
1136		1113
@@ -1176,15 +1153,21 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) · 39 unmodified lines
1176		1153
1177	#define REG_A6XX_CP_SDS_BASE_HI 0x0000092f	1154	#define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
1178		1155
1179	#define REG_A6XX_CP_SDS_REM_SIZE 0x0000092e	1156	#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
		1157
		1158	#define REG_A6XX_CP_MRB_BASE 0x00000931
		1159
		1160	#define REG_A6XX_CP_MRB_BASE_HI 0x00000932
1180		1161
1181	#define REG_A6XX_CP_BIN_SIZE_ADDRESS 0x00000931	1162	#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
1182		1163
1183	#define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI 0x00000932	1164	#define REG_A6XX_CP_VSD_BASE 0x00000934
1184		1165
1185	#define REG_A6XX_CP_BIN_DATA_ADDR 0x00000934	1166	#define REG_A6XX_CP_VSD_BASE_HI 0x00000935
1186		1167
1187	#define REG_A6XX_CP_BIN_DATA_ADDR_HI 0x00000935	1168	#define REG_A6XX_CP_MRB_DWORDS 0x00000946
		1169
		1170	#define REG_A6XX_CP_VSD_DWORDS 0x00000947
1188		1171
1189	#define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949	1172	#define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
1190	#define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000	1173	#define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
@@ -1202,6 +1185,14 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) · 11 unmodified lines
1202	return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;	1185	return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1203	}	1186	}
1204		1187
		1188	#define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c
		1189	#define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000
		1190	#define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16
		1191	static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)
		1192	{
		1193	return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK;
		1194	}
		1195
1205	#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980	1196	#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
1206		1197
1207	#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981	1198	#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
@@ -1212,6 +1203,10 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) · 4 unmodified lines
1212		1203
1213	#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03	1204	#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1214		1205
		1206	#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
		1207
		1208	#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
		1209
1215	#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01	1210	#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1216		1211
1217	#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201	1212	#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
@@ -1247,505 +1242,37 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) · 29 unmodified lines
1247		1242
1248	#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215	1243	#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1249		1244
1250	#define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400	1245	static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
1251
1252	#define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401
1253
1254	#define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402
1255
1256	#define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403
1257
1258	#define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404
1259
1260	#define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405
1261
1262	#define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406
1263
1264	#define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407
1265
1266	#define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408
1267
1268	#define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409
1269
1270	#define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a
1271
1272	#define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b
1273
1274	#define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c
1275
1276	#define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d
1277
1278	#define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e
1279
1280	#define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f
1281
1282	#define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410
1283
1284	#define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411
1285
1286	#define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412
1287
1288	#define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413
1289
1290	#define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414
1291
1292	#define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415
1293
1294	#define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416
1295
1296	#define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417
1297
1298	#define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418
1299
1300	#define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419
1301
1302	#define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a
1303
1304	#define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b
1305
1306	#define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c
1307
1308	#define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d
1309
1310	#define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e
1311
1312	#define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f
1313
1314	#define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420
1315
1316	#define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421
1317
1318	#define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422
1319
1320	#define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423
1321
1322	#define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424
1323
1324	#define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425
1325
1326	#define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426
1327
1328	#define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427
1329
1330	#define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428
1331
1332	#define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429
1333
1334	#define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a
1335
1336	#define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b
1337
1338	#define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c
1339
1340	#define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d
1341
1342	#define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e
1343
1344	#define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f
1345
1346	#define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430
1347
1348	#define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431
1349
1350	#define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432
1351
1352	#define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433
1353
1354	#define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434
1355
1356	#define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435
1357
1358	#define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436
1359
1360	#define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437
1361
1362	#define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438
1363
1364	#define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439
1365
1366	#define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a
1367
1368	#define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b
1369
1370	#define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c
1371
1372	#define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d
1373
1374	#define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e
1375
1376	#define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f
1377
1378	#define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440
1379
1380	#define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441
1381
1382	#define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442
1383
1384	#define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443
1385
1386	#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444
1387
1388	#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445
1389
1390	#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446
1391
1392	#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447
1393
1394	#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448
1395
1396	#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449
1397
1398	#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a
1399
1400	#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b
1401
1402	#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c
1403
1404	#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d
1405
1406	#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e
1407
1408	#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f
1409
1410	#define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450
1411
1412	#define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451
1413
1414	#define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452
1415
1416	#define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453
1417
1418	#define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454
1419
1420	#define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455
1421
1422	#define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456
1423
1424	#define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457
1425
1426	#define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458
1427
1428	#define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459
1429
1430	#define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a
1431
1432	#define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b
1433
1434	#define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c
1435
1436	#define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d
1437
1438	#define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e
1439
1440	#define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f
1441
1442	#define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460
1443
1444	#define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461
1445
1446	#define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462
1447
1448	#define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463
1449
1450	#define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464
1451
1452	#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
1453
1454	#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
1455
1456	#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
1457
1458	#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
1459
1460	#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
1461
1462	#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
1463
1464	#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
1465
1466	#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
1467
1468	#define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d
1469
1470	#define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e
1471
1472	#define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f
1473
1474	#define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470
1475
1476	#define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471
1477
1478	#define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472
1479
1480	#define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473
1481
1482	#define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474
1483
1484	#define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475
1485
1486	#define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476
1487
1488	#define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477
1489
1490	#define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478
1491
1492	#define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479
1493
1494	#define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a
1495
1496	#define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b
1497
1498	#define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c
1499
1500	#define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d
1501
1502	#define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e
1503
1504	#define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f
1505
1506	#define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480
1507
1508	#define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481
1509
1510	#define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482
1511
1512	#define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483
1513
1514	#define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484
1515
1516	#define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485
1517
1518	#define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486
1519
1520	#define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487
1521
1522	#define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488
1523
1524	#define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489
1525
1526	#define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a
1527
1528	#define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b
1529
1530	#define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c
1531
1532	#define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d
1533
1534	#define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e
1535
1536	#define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f
1537
1538	#define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490
1539
1540	#define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491
1541
1542	#define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492
1543
1544	#define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493
1545
1546	#define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494
1547
1548	#define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495
1549
1550	#define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496
1551
1552	#define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497
1553
1554	#define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498
1555
1556	#define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499
1557
1558	#define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a
1559
1560	#define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b
1561
1562	#define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c
1563
1564	#define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d
1565
1566	#define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e
1567
1568	#define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f
1569		1246
1570	#define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0	1247	static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
1571		1248
1572	#define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1	1249	static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
1573		1250
1574	#define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2	1251	static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
1575		1252
1576	#define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3	1253	static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
1577		1254
1578	#define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4	1255	static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
1579		1256
1580	#define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5	1257	static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
1581		1258
1582	#define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6	1259	static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
1583		1260
1584	#define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7	1261	static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
1585		1262
1586	#define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8	1263	static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
1587		1264
1588	#define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9	1265	static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
1589		1266
1590	#define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa	1267	static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
1591		1268
1592	#define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab	1269	static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
1593		1270
1594	#define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac	1271	static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
1595		1272
1596	#define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad	1273	static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
1597		1274
1598	#define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae	1275	static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
1599
1600	#define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af
1601
1602	#define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0
1603
1604	#define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1
1605
1606	#define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2
1607
1608	#define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3
1609
1610	#define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4
1611
1612	#define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5
1613
1614	#define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6
1615
1616	#define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7
1617
1618	#define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8
1619
1620	#define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9
1621
1622	#define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba
1623
1624	#define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb
1625
1626	#define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc
1627
1628	#define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd
1629
1630	#define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be
1631
1632	#define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf
1633
1634	#define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0
1635
1636	#define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1
1637
1638	#define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2
1639
1640	#define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3
1641
1642	#define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4
1643
1644	#define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5
1645
1646	#define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6
1647
1648	#define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7
1649
1650	#define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8
1651
1652	#define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9
1653
1654	#define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca
1655
1656	#define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb
1657
1658	#define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc
1659
1660	#define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd
1661
1662	#define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce
1663
1664	#define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf
1665
1666	#define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0
1667
1668	#define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1
1669
1670	#define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2
1671
1672	#define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3
1673
1674	#define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4
1675
1676	#define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5
1677
1678	#define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6
1679
1680	#define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7
1681
1682	#define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8
1683
1684	#define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9
1685
1686	#define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da
1687
1688	#define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db
1689
1690	#define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc
1691
1692	#define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd
1693
1694	#define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de
1695
1696	#define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df
1697
1698	#define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0
1699
1700	#define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1
1701
1702	#define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2
1703
1704	#define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3
1705
1706	#define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4
1707
1708	#define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5
1709
1710	#define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6
1711
1712	#define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7
1713
1714	#define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8
1715
1716	#define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9
1717
1718	#define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea
1719
1720	#define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb
1721
1722	#define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec
1723
1724	#define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed
1725
1726	#define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee
1727
1728	#define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef
1729
1730	#define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0
1731
1732	#define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1
1733
1734	#define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2
1735
1736	#define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3
1737
1738	#define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4
1739
1740	#define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5
1741
1742	#define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6
1743
1744	#define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7
1745
1746	#define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8
1747
1748	#define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9
1749		1276
1750	#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500	1277	#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1751		1278
@@ -1761,13 +1288,7 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) · 9 unmodified lines
1761		1288
1762	#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506	1289	#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1763		1290
1764	#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507	1291	static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
1765
1766	#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508
1767
1768	#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509
1769
1770	#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a
1771		1292
1772	#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b	1293	#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1773		1294
@@ -2231,204 +1752,60 @@ static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) · 457 unmodified lines
2231	}	1752	}
2232	#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000	1753	#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
2233	#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28	1754	#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
2234	static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)	1755	static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
2235	{	1756	{
2236	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;	1757	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
2237	}	1758	}
2238
2239	#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
2240
2241	#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
2242
2243	#define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8
2244
2245	#define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9
2246
2247	#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
2248
2249	#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10
2250
2251	#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11
2252
2253	#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12
2254
2255	#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13
2256
2257	#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14
2258
2259	#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15
2260
2261	#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
2262
2263	#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
2264
2265	#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
2266
2267	#define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610
2268
2269	#define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611
2270
2271	#define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612
2272
2273	#define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613
2274
2275	#define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614
2276
2277	#define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615
2278
2279	#define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616
2280
2281	#define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617
2282
2283	#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
2284
2285	#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
2286
2287	#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
2288
2289	#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
2290
2291	#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
2292
2293	#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
2294
2295	#define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
2296
2297	#define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
2298
2299	#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
2300
2301	#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
2302
2303	#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
2304
2305	#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
2306
2307	#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
2308
2309	#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
2310
2311	#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
2312	#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
2313	#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
2314	static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
2315	{
2316	return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
2317	}
2318
2319	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c
2320
2321	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d
2322
2323	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e
2324
2325	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f
2326
2327	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20
2328
2329	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21
2330
2331	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22
2332
2333	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23
2334
2335	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24
2336
2337	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25
2338
2339	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26
2340
2341	#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27
2342
2343	#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
2344
2345	#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
2346
2347	#define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10
2348
2349	#define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11
2350
2351	#define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12
2352
2353	#define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13
2354
2355	#define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14
2356
2357	#define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15
2358
2359	#define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16
2360
2361	#define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17
2362
2363	#define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18
2364
2365	#define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19
2366
2367	#define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a
2368
2369	#define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b
2370
2371	#define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c
2372
2373	#define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d
2374
2375	#define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e
2376
2377	#define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f
2378
2379	#define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20
2380
2381	#define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21
2382
2383	#define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22
2384
2385	#define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23
2386
2387	#define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24
2388		1759
2389	#define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25	1760	#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
2390		1761
2391	#define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26	1762	#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
2392		1763
2393	#define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27	1764	static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
2394		1765
2395	#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601	1766	#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
2396		1767
2397	#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604	1768	#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
2398		1769
2399	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608	1770	#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
2400		1771
2401	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609	1772	#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
2402		1773
2403	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a	1774	#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
2404		1775
2405	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b	1776	#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
2406		1777
2407	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c	1778	#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
2408		1779
2409	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610	1780	#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
2410		1781
2411	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611	1782	#define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
2412		1783
2413	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612	1784	#define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
2414		1785
2415	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613	1786	#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
2416		1787
2417	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614	1788	#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
2418		1789
2419	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615	1790	#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
2420		1791
2421	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616	1792	#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
2422		1793
2423	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617	1794	#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
2424		1795
2425	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618	1796	#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
2426		1797
2427	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619	1798	#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
		1799	#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
		1800	#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
		1801	static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
		1802	{
		1803	return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
		1804	}
2428		1805
2429	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a	1806	static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
2430		1807
2431	#define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b	1808	#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
2432		1809
2433	#define REG_A6XX_VBIF_VERSION 0x00003000	1810	#define REG_A6XX_VBIF_VERSION 0x00003000
2434		1811
@@ -2507,6 +1884,8 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) · 72 unmodified lines
2507		1884
2508	#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a	1885	#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2509		1886
		1887	#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
		1888
2510	#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02	1889	#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
2511		1890
2512	#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03	1891	#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
@@ -2555,36 +1934,6 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) · 42 unmodified lines
2555		1934
2556	#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1	1935	#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
2557		1936
2558	#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
2559	#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2560	#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff
2561	#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
2562	static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
2563	{
2564	return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
2565	}
2566	#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2567	#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
2568	static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
2569	{
2570	return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
2571	}
2572
2573	#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
2574	#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2575	#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff
2576	#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
2577	static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
2578	{
2579	return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
2580	}
2581	#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2582	#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
2583	static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
2584	{
2585	return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
2586	}
2587
2588	#define REG_A6XX_VSC_BIN_SIZE 0x00000c02	1937	#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
2589	#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff	1938	#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2590	#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0	1939	#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
@@ -2599,10 +1948,6 @@ static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) · 8 unmodified lines
2599	return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;	1948	return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2600	}	1949	}
2601		1950
2602	#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO 0x00000c03
2603
2604	#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI 0x00000c04
2605
2606	#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03	1951	#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
2607		1952
2608	#define REG_A6XX_VSC_BIN_COUNT 0x00000c06	1953	#define REG_A6XX_VSC_BIN_COUNT 0x00000c06
@@ -2647,20 +1992,12 @@ static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) · 38 unmodified lines
2647	return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;	1992	return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2648	}	1993	}
2649		1994
2650	#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO 0x00000c30
2651
2652	#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI 0x00000c31
2653
2654	#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30	1995	#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
2655		1996
2656	#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32	1997	#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
2657		1998
2658	#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33	1999	#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
2659		2000
2660	#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO 0x00000c34
2661
2662	#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI 0x00000c35
2663
2664	#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34	2001	#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
2665		2002
2666	#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36	2003	#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
@@ -2849,12 +2186,20 @@ static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) · 182 unmodified lines
2849	return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;	2186	return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2850	}	2187	}
2851	#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000	2188	#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2852	#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x007f8000	2189	#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
2853	#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15	2190	#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
2854	static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)	2191	static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2855	{	2192	{
2856	return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;	2193	return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2857	}	2194	}
		2195	#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
		2196	#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
		2197	#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
		2198	#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
		2199	static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
		2200	{
		2201	return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
		2202	}
2858		2203
2859	#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091	2204	#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2860	#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff	2205	#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
@@ -3205,11 +2550,12 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) · 344 unmodified lines
3205	#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004	2550	#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
3206	#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008	2551	#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
3207	#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010	2552	#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
3208	#define A6XX_GRAS_LRZ_CNTL_UNK5__MASK 0x000003e0	2553	#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
3209	#define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT 5	2554	#define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0
3210	static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val)	2555	#define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6
		2556	static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
3211	{	2557	{
3212	return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK;	2558	return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
3213	}	2559	}
3214		2560
3215	#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101	2561	#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
@@ -3222,10 +2568,6 @@ static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val) · 6 unmodified lines
3222	return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;	2568	return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
3223	}	2569	}
3224		2570
3225	#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103
3226
3227	#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
3228
3229	#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103	2571	#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
3230	#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff	2572	#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
3231	#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0	2573	#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
@@ -3248,10 +2590,6 @@ static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) · 16 unmodified lines
3248	return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;	2590	return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
3249	}	2591	}
3250		2592
3251	#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106
3252
3253	#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
3254
3255	#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106	2593	#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
3256	#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff	2594	#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
3257	#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0	2595	#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
@@ -3406,29 +2744,11 @@ static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) · 148 unmodified lines
3406		2744
3407	#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601	2745	#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
3408		2746
3409	#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610	2747	static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
3410
3411	#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611
3412
3413	#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612
3414
3415	#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613
3416
3417	#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614
3418
3419	#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615
3420
3421	#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616
3422
3423	#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617
3424		2748
3425	#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618	2749	static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
3426		2750
3427	#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619	2751	static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
3428
3429	#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a
3430
3431	#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b
3432		2752
3433	#define REG_A6XX_RB_BIN_CONTROL 0x00008800	2753	#define REG_A6XX_RB_BIN_CONTROL 0x00008800
3434	#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f	2754	#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
@@ -3889,10 +3209,6 @@ static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) · 454 unmodified lines
3889	return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;	3209	return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3890	}	3210	}
3891		3211
3892	static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3893
3894	static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
3895
3896	static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }	3212	static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3897	#define A6XX_RB_MRT_BASE__MASK 0xffffffff	3213	#define A6XX_RB_MRT_BASE__MASK 0xffffffff
3898	#define A6XX_RB_MRT_BASE__SHIFT 0	3214	#define A6XX_RB_MRT_BASE__SHIFT 0
@@ -4025,10 +3341,6 @@ static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) · 126 unmodified lines
4025	return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;	3341	return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
4026	}	3342	}
4027		3343
4028	#define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875
4029
4030	#define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
4031
4032	#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875	3344	#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
4033	#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff	3345	#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
4034	#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0	3346	#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
@@ -4134,10 +3446,6 @@ static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) · 99 unmodified lines
4134	return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;	3446	return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
4135	}	3447	}
4136		3448
4137	#define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884
4138
4139	#define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
4140
4141	#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884	3449	#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
4142	#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff	3450	#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
4143	#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0	3451	#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
@@ -4355,10 +3663,6 @@ static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) · 211 unmodified lines
4355	return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;	3663	return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
4356	}	3664	}
4357		3665
4358	#define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
4359
4360	#define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
4361
4362	#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da	3666	#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
4363	#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff	3667	#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
4364	#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0	3668	#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
@@ -4383,10 +3687,6 @@ static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) · 18 unmodified lines
4383	return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;	3687	return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
4384	}	3688	}
4385		3689
4386	#define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
4387
4388	#define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
4389
4390	#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de	3690	#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
4391	#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff	3691	#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
4392	#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0	3692	#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
@@ -4412,7 +3712,7 @@ static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) · 19 unmodified lines
4412	#define REG_A6XX_RB_BLIT_INFO 0x000088e3	3712	#define REG_A6XX_RB_BLIT_INFO 0x000088e3
4413	#define A6XX_RB_BLIT_INFO_UNK0 0x00000001	3713	#define A6XX_RB_BLIT_INFO_UNK0 0x00000001
4414	#define A6XX_RB_BLIT_INFO_GMEM 0x00000002	3714	#define A6XX_RB_BLIT_INFO_GMEM 0x00000002
4415	#define A6XX_RB_BLIT_INFO_INTEGER 0x00000004	3715	#define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004
4416	#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008	3716	#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
4417	#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0	3717	#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
4418	#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4	3718	#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
@@ -4459,10 +3759,6 @@ static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) · 40 unmodified lines
4459		3759
4460	#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4	3760	#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
4461		3761
4462	#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900
4463
4464	#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
4465
4466	#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900	3762	#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
4467	#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff	3763	#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
4468	#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0	3764	#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
@@ -4493,10 +3789,6 @@ static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) · 24 unmodified lines
4493		3789
4494	static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }	3790	static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4495		3791
4496	static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4497
4498	static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
4499
4500	static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }	3792	static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4501	#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff	3793	#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
4502	#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0	3794	#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
@@ -4519,10 +3811,6 @@ static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) · 16 unmodified lines
4519	return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;	3811	return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4520	}	3812	}
4521		3813
4522	#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
4523
4524	#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
4525
4526	#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927	3814	#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
4527	#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff	3815	#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
4528	#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0	3816	#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
@@ -4608,13 +3896,19 @@ static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) · 79 unmodified lines
4608	return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;	3896	return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
4609	}	3897	}
4610	#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000	3898	#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
		3899	#define A6XX_RB_2D_DST_INFO_UNK17 0x00020000
4611	#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000	3900	#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
		3901	#define A6XX_RB_2D_DST_INFO_UNK19 0x00080000
4612	#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000	3902	#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
		3903	#define A6XX_RB_2D_DST_INFO_UNK21 0x00200000
4613	#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000	3904	#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
4614		3905	#define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000
4615	#define REG_A6XX_RB_2D_DST_LO 0x00008c18	3906	#define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23
4616		3907	static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
4617	#define REG_A6XX_RB_2D_DST_HI 0x00008c19	3908	{
		3909	return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
		3910	}
		3911	#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
4618		3912
4619	#define REG_A6XX_RB_2D_DST 0x00008c18	3913	#define REG_A6XX_RB_2D_DST 0x00008c18
4620	#define A6XX_RB_2D_DST__MASK 0xffffffff	3914	#define A6XX_RB_2D_DST__MASK 0xffffffff
@@ -4656,10 +3950,6 @@ static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) · 35 unmodified lines
4656	return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;	3950	return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
4657	}	3951	}
4658		3952
4659	#define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20
4660
4661	#define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
4662
4663	#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20	3953	#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
4664	#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff	3954	#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
4665	#define A6XX_RB_2D_DST_FLAGS__SHIFT 0	3955	#define A6XX_RB_2D_DST_FLAGS__SHIFT 0
@@ -4740,41 +4030,13 @@ static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) · 74 unmodified lines
4740	return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;	4030	return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4741	}	4031	}
4742		4032
4743	#define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10	4033	static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
4744
4745	#define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11
4746
4747	#define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12
4748
4749	#define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13
4750
4751	#define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14
4752
4753	#define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15
4754
4755	#define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16
4756
4757	#define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17
4758
4759	#define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18
4760		4034
4761	#define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19	4035	static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
4762
4763	#define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a
4764
4765	#define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b
4766
4767	#define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c
4768		4036
4769	#define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28	4037	#define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
4770		4038
4771	#define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c	4039	static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
4772
4773	#define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d
4774
4775	#define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e
4776
4777	#define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f
4778		4040
4779	#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b	4041	#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
4780		4042
@@ -4895,6 +4157,8 @@ static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) · 114 unmodified lines
4895	}	4157	}
4896		4158
4897	#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107	4159	#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
		4160	#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
		4161	#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
4898		4162
4899	#define REG_A6XX_VPC_POLYGON_MODE 0x00009108	4163	#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
4900	#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003	4164	#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
@@ -4921,13 +4185,13 @@ static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i · 20 unmodified lines
4921	static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }	4185	static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4922		4186
4923	#define REG_A6XX_VPC_SO_CNTL 0x00009216	4187	#define REG_A6XX_VPC_SO_CNTL 0x00009216
4924	#define A6XX_VPC_SO_CNTL_UNK0__MASK 0x000000ff	4188	#define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff
4925	#define A6XX_VPC_SO_CNTL_UNK0__SHIFT 0	4189	#define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0
4926	static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val)	4190	static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
4927	{	4191	{
4928	return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK;	4192	return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
4929	}	4193	}
4930	#define A6XX_VPC_SO_CNTL_ENABLE 0x00010000	4194	#define A6XX_VPC_SO_CNTL_RESET 0x00010000
4931		4195
4932	#define REG_A6XX_VPC_SO_PROG 0x00009217	4196	#define REG_A6XX_VPC_SO_PROG 0x00009217
4933	#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003	4197	#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
@@ -4957,10 +4221,6 @@ static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) · 23 unmodified lines
4957	}	4221	}
4958	#define A6XX_VPC_SO_PROG_B_EN 0x00800000	4222	#define A6XX_VPC_SO_PROG_B_EN 0x00800000
4959		4223
4960	#define REG_A6XX_VPC_SO_STREAM_COUNTS_LO 0x00009218
4961
4962	#define REG_A6XX_VPC_SO_STREAM_COUNTS_HI 0x00009219
4963
4964	#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218	4224	#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
4965	#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff	4225	#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
4966	#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0	4226	#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
@@ -4979,10 +4239,6 @@ static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) · 12 unmodified lines
4979	return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;	4239	return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4980	}	4240	}
4981		4241
4982	static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4983
4984	static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
4985
4986	static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }	4242	static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4987	#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc	4243	#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
4988	#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2	4244	#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
@@ -5009,10 +4265,6 @@ static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) · 20 unmodified lines
5009	return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;	4265	return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
5010	}	4266	}
5011		4267
5012	static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
5013
5014	static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
5015
5016	#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236	4268	#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
5017	#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001	4269	#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
5018		4270
@@ -5037,11 +4289,11 @@ static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) · 18 unmodified lines
5037	{	4289	{
5038	return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;	4290	return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
5039	}	4291	}
5040	#define A6XX_VPC_VS_PACK_UNK24__MASK 0x0f000000	4292	#define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000
5041	#define A6XX_VPC_VS_PACK_UNK24__SHIFT 24	4293	#define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24
5042	static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val)	4294	static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
5043	{	4295	{
5044	return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK;	4296	return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
5045	}	4297	}
5046		4298
5047	#define REG_A6XX_VPC_GS_PACK 0x00009302	4299	#define REG_A6XX_VPC_GS_PACK 0x00009302
@@ -5063,11 +4315,11 @@ static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) · 15 unmodified lines
5063	{	4315	{
5064	return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;	4316	return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
5065	}	4317	}
5066	#define A6XX_VPC_GS_PACK_UNK24__MASK 0x0f000000	4318	#define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000
5067	#define A6XX_VPC_GS_PACK_UNK24__SHIFT 24	4319	#define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24
5068	static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val)	4320	static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
5069	{	4321	{
5070	return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK;	4322	return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
5071	}	4323	}
5072		4324
5073	#define REG_A6XX_VPC_DS_PACK 0x00009303	4325	#define REG_A6XX_VPC_DS_PACK 0x00009303
@@ -5089,11 +4341,11 @@ static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) · 15 unmodified lines
5089	{	4341	{
5090	return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;	4342	return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
5091	}	4343	}
5092	#define A6XX_VPC_DS_PACK_UNK24__MASK 0x0f000000	4344	#define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000
5093	#define A6XX_VPC_DS_PACK_UNK24__SHIFT 24	4345	#define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24
5094	static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val)	4346	static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
5095	{	4347	{
5096	return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK;	4348	return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
5097	}	4349	}
5098		4350
5099	#define REG_A6XX_VPC_CNTL_0 0x00009304	4351	#define REG_A6XX_VPC_CNTL_0 0x00009304
@@ -5110,24 +4362,43 @@ static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) · 10 unmodified lines
5110	return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;	4362	return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
5111	}	4363	}
5112	#define A6XX_VPC_CNTL_0_VARYING 0x00010000	4364	#define A6XX_VPC_CNTL_0_VARYING 0x00010000
5113	#define A6XX_VPC_CNTL_0_UNKLOC__MASK 0xff000000	4365	#define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000
5114	#define A6XX_VPC_CNTL_0_UNKLOC__SHIFT 24	4366	#define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24
5115	static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)	4367	static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
5116	{	4368	{
5117	return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK;	4369	return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
5118	}	4370	}
5119		4371
5120	#define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305	4372	#define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305
5121	#define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001	4373	#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007
5122	#define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008	4374	#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0
5123	#define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040	4375	static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
5124	#define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200	4376	{
5125	#define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000	4377	return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
5126	#define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK 0x000f0000	4378	}
5127	#define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT 16	4379	#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038
5128	static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val)	4380	#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3
		4381	static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
		4382	{
		4383	return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
		4384	}
		4385	#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0
		4386	#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6
		4387	static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
5129	{	4388	{
5130	return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK;	4389	return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
		4390	}
		4391	#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00
		4392	#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9
		4393	static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
		4394	{
		4395	return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
		4396	}
		4397	#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
		4398	#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
		4399	static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
		4400	{
		4401	return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
5131	}	4402	}
5132		4403
5133	#define REG_A6XX_VPC_SO_DISABLE 0x00009306	4404	#define REG_A6XX_VPC_SO_DISABLE 0x00009306
@@ -5141,32 +4412,22 @@ static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val) · 7 unmodified lines
5141		4412
5142	#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603	4413	#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
5143		4414
5144	#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604	4415	static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
5145
5146	#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605
5147
5148	#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606
5149
5150	#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607
5151
5152	#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608
5153
5154	#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609
5155		4416
5156	#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800	4417	#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
5157		4418
5158	#define REG_A6XX_PC_UNKNOWN_9801 0x00009801	4419	#define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801
5159	#define A6XX_PC_UNKNOWN_9801_UNK0__MASK 0x000007ff	4420	#define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff
5160	#define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT 0	4421	#define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0
5161	static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val)	4422	static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
5162	{	4423	{
5163	return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK;	4424	return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
5164	}	4425	}
5165	#define A6XX_PC_UNKNOWN_9801_UNK13__MASK 0x00002000	4426	#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000
5166	#define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT 13	4427	#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13
5167	static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val)	4428	static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
5168	{	4429	{
5169	return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK;	4430	return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
5170	}	4431	}
5171		4432
5172	#define REG_A6XX_PC_TESS_CNTL 0x00009802	4433	#define REG_A6XX_PC_TESS_CNTL 0x00009802
@@ -5221,6 +4482,8 @@ static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) · 48 unmodified lines
5221	return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;	4482	return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
5222	}	4483	}
5223		4484
		4485	#define REG_A6XX_PC_MARKER 0x00009880
		4486
5224	#define REG_A6XX_PC_POLYGON_MODE 0x00009981	4487	#define REG_A6XX_PC_POLYGON_MODE 0x00009981
5225	#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003	4488	#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
5226	#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0	4489	#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
@@ -5229,7 +4492,14 @@ static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) · 2 unmodified lines
5229	return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;	4492	return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
5230	}	4493	}
5231		4494
5232	#define REG_A6XX_PC_UNKNOWN_9980 0x00009980	4495	#define REG_A6XX_PC_RASTER_CNTL 0x00009980
		4496	#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
		4497	#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
		4498	static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
		4499	{
		4500	return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
		4501	}
		4502	#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
5233		4503
5234	#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00	4504	#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
5235	#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001	4505	#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
@@ -5327,9 +4597,17 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) · 91 unmodified lines
5327	return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;	4597	return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
5328	}	4598	}
5329		4599
5330	#define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07	4600	#define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07
		4601	#define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001
		4602	#define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
		4603	#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
		4604	#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
		4605	static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
		4606	{
		4607	return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
		4608	}
5331		4609
5332	#define REG_A6XX_PC_UNKNOWN_9B08 0x00009b08	4610	#define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08
5333		4611
5334	#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00	4612	#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
5335	#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f	4613	#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
@@ -5349,9 +4627,11 @@ static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) · 13 unmodified lines
5349		4627
5350	#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01	4628	#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
5351		4629
5352	#define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08	4630	#define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04
5353		4631
5354	#define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09	4632	#define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06
		4633
		4634	#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
5355		4635
5356	#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08	4636	#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
5357	#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff	4637	#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
@@ -5361,6 +4641,44 @@ static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) · 3 unmodified lines
5361	return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;	4641	return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
5362	}	4642	}
5363		4643
		4644	#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
		4645	#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
		4646	#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
		4647	static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
		4648	{
		4649	return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
		4650	}
		4651	#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
		4652	#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
		4653	static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
		4654	{
		4655	return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
		4656	}
		4657	#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300
		4658	#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8
		4659	static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
		4660	{
		4661	return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
		4662	}
		4663	#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00
		4664	#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10
		4665	static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
		4666	{
		4667	return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
		4668	}
		4669	#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000
		4670	#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12
		4671	static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
		4672	{
		4673	return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
		4674	}
		4675	#define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000
		4676	#define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000
		4677
		4678	#define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c
		4679
		4680	#define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d
		4681
5364	#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11	4682	#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
5365	#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff	4683	#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
5366	#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0	4684	#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
@@ -5397,21 +4715,10 @@ static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) · 30 unmodified lines
5397	return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;	4715	return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
5398	}	4716	}
5399		4717
5400	#define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34	4718	#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
5401		4719	#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
5402	#define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35
5403
5404	#define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36
5405
5406	#define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37
5407
5408	#define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38
5409		4720
5410	#define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39	4721	static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
5411
5412	#define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a
5413
5414	#define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b
5415		4722
5416	#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72	4723	#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
5417		4724
@@ -5448,6 +4755,12 @@ static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) · 30 unmodified lines
5448	{	4755	{
5449	return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;	4756	return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
5450	}	4757	}
		4758	#define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000
		4759	#define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24
		4760	static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
		4761	{
		4762	return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
		4763	}
5451		4764
5452	#define REG_A6XX_VFD_CONTROL_2 0x0000a002	4765	#define REG_A6XX_VFD_CONTROL_2 0x0000a002
5453	#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff	4766	#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
@@ -5464,6 +4777,12 @@ static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) · 10 unmodified lines
5464	}	4777	}
5465		4778
5466	#define REG_A6XX_VFD_CONTROL_3 0x0000a003	4779	#define REG_A6XX_VFD_CONTROL_3 0x0000a003
		4780	#define A6XX_VFD_CONTROL_3_UNK0__MASK 0x000000ff
		4781	#define A6XX_VFD_CONTROL_3_UNK0__SHIFT 0
		4782	static inline uint32_t A6XX_VFD_CONTROL_3_UNK0(uint32_t val)
		4783	{
		4784	return ((val) << A6XX_VFD_CONTROL_3_UNK0__SHIFT) & A6XX_VFD_CONTROL_3_UNK0__MASK;
		4785	}
5467	#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00	4786	#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
5468	#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8	4787	#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
5469	static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)	4788	static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
@@ -5484,6 +4803,12 @@ static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) · 14 unmodified lines
5484	}	4803	}
5485		4804
5486	#define REG_A6XX_VFD_CONTROL_4 0x0000a004	4805	#define REG_A6XX_VFD_CONTROL_4 0x0000a004
		4806	#define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff
		4807	#define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0
		4808	static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
		4809	{
		4810	return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
		4811	}
5487		4812
5488	#define REG_A6XX_VFD_CONTROL_5 0x0000a005	4813	#define REG_A6XX_VFD_CONTROL_5 0x0000a005
5489	#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff	4814	#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
@@ -5492,14 +4817,30 @@ static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) · 2 unmodified lines
5492	{	4817	{
5493	return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;	4818	return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
5494	}	4819	}
		4820	#define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00
		4821	#define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8
		4822	static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
		4823	{
		4824	return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
		4825	}
5495		4826
5496	#define REG_A6XX_VFD_CONTROL_6 0x0000a006	4827	#define REG_A6XX_VFD_CONTROL_6 0x0000a006
5497	#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001	4828	#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
5498		4829
5499	#define REG_A6XX_VFD_MODE_CNTL 0x0000a007	4830	#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
5500	#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001	4831	#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
		4832	#define A6XX_VFD_MODE_CNTL_UNK1 0x00000002
		4833	#define A6XX_VFD_MODE_CNTL_UNK2 0x00000004
5501		4834
5502	#define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008	4835	#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
		4836	#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
		4837	#define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
		4838	#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
		4839	#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2
		4840	static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
		4841	{
		4842	return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
		4843	}
5503		4844
5504	#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009	4845	#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
5505	#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001	4846	#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
@@ -5512,10 +4853,12 @@ static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) · 6 unmodified lines
5512	static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }	4853	static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5513		4854
5514	static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }	4855	static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5515		4856	#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff
5516	static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }	4857	#define A6XX_VFD_FETCH_BASE__SHIFT 0
5517		4858	static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
5518	static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }	4859	{
		4860	return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
		4861	}
5519		4862
5520	static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }	4863	static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
5521		4864
@@ -5572,7 +4915,19 @@ static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) · 50 unmodified lines
5572		4915
5573	#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8	4916	#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
5574		4917
		4918	#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
		4919
		4920	static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
		4921
5575	#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800	4922	#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
		4923	#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
		4924	#define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000
		4925	#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
		4926	#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
		4927	static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
		4928	{
		4929	return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
		4930	}
5576	#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e	4931	#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5577	#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1	4932	#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5578	static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)	4933	static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -5585,22 +4940,13 @@ static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
5585	{	4940	{
5586	return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;	4941	return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5587	}	4942	}
		4943	#define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000
5588	#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000	4944	#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5589	#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14	4945	#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5590	static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)	4946	static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5591	{	4947	{
5592	return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;	4948	return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
5593	}	4949	}
5594	#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5595	#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
5596	static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5597	{
5598	return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
5599	}
5600	#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
5601	#define A6XX_SP_VS_CTRL_REG0_DIFF_FINE 0x00800000
5602	#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
5603	#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
5604		4950
5605	#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801	4951	#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
5606		4952
@@ -5611,6 +4957,12 @@ static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) · 4 unmodified lines
5611	{	4957	{
5612	return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;	4958	return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
5613	}	4959	}
		4960	#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
		4961	#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
		4962	static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
		4963	{
		4964	return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
		4965	}
5614		4966
5615	static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }	4967	static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5616		4968
@@ -5668,11 +5020,46 @@ static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) · 51 unmodified lines
5668	return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;	5020	return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5669	}	5021	}
5670		5022
5671	#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b	5023	#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
		5024
		5025	#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
		5026	#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff
		5027	#define A6XX_SP_VS_OBJ_START__SHIFT 0
		5028	static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
		5029	{
		5030	return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
		5031	}
		5032
		5033	#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
		5034	#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
		5035	#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
		5036	static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
		5037	{
		5038	return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
		5039	}
		5040	#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
		5041	#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
		5042	static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
		5043	{
		5044	return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
		5045	}
5672		5046
5673	#define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c	5047	#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
		5048	#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff
		5049	#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0
		5050	static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
		5051	{
		5052	return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
		5053	}
5674		5054
5675	#define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d	5055	#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
		5056	#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
		5057	#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
		5058	static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
		5059	{
		5060	return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
		5061	}
		5062	#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5676		5063
5677	#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822	5064	#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
5678		5065
@@ -5694,7 +5081,7 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) · 15 unmodified lines
5694	{	5081	{
5695	return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;	5082	return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5696	}	5083	}
5697	#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000	5084	#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000
5698	#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22	5085	#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
5699	static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)	5086	static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5700	{	5087	{
@@ -5703,7 +5090,22 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
5703		5090
5704	#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824	5091	#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
5705		5092
		5093	#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
		5094	#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
		5095	#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
		5096	static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
		5097	{
		5098	return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK;
		5099	}
		5100
5706	#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830	5101	#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
		5102	#define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000
		5103	#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
		5104	#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
		5105	static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
		5106	{
		5107	return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
		5108	}
5707	#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e	5109	#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5708	#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1	5110	#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5709	static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)	5111	static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -5716,30 +5118,58 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
5716	{	5118	{
5717	return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;	5119	return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5718	}	5120	}
		5121	#define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000
5719	#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000	5122	#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5720	#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14	5123	#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5721	static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)	5124	static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5722	{	5125	{
5723	return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;	5126	return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5724	}	5127	}
5725	#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000	5128
5726	#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20	5129	#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
5727	static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)	5130
		5131	#define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832
		5132
		5133	#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
		5134
		5135	#define REG_A6XX_SP_HS_OBJ_START 0x0000a834
		5136	#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff
		5137	#define A6XX_SP_HS_OBJ_START__SHIFT 0
		5138	static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
5728	{	5139	{
5729	return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;	5140	return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
5730	}	5141	}
5731	#define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
5732	#define A6XX_SP_HS_CTRL_REG0_DIFF_FINE 0x00800000
5733	#define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
5734	#define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
5735		5142
5736	#define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831	5143	#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
5737		5144	#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5738	#define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833	5145	#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
		5146	static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
		5147	{
		5148	return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
		5149	}
		5150	#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
		5151	#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
		5152	static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
		5153	{
		5154	return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
		5155	}
5739		5156
5740	#define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834	5157	#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
		5158	#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff
		5159	#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0
		5160	static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
		5161	{
		5162	return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
		5163	}
5741		5164
5742	#define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835	5165	#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
		5166	#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
		5167	#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
		5168	static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
		5169	{
		5170	return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
		5171	}
		5172	#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5743		5173
5744	#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a	5174	#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
5745		5175
@@ -5761,7 +5191,7 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) · 15 unmodified lines
5761	{	5191	{
5762	return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;	5192	return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5763	}	5193	}
5764	#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000	5194	#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000
5765	#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22	5195	#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
5766	static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)	5196	static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5767	{	5197	{
@@ -5770,7 +5200,22 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
5770		5200
5771	#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c	5201	#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
5772		5202
		5203	#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
		5204	#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
		5205	#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
		5206	static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
		5207	{
		5208	return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK;
		5209	}
		5210
5773	#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840	5211	#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
		5212	#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000
		5213	#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
		5214	#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
		5215	static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
		5216	{
		5217	return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
		5218	}
5774	#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e	5219	#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5775	#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1	5220	#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5776	static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)	5221	static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -5783,22 +5228,15 @@ static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
5783	{	5228	{
5784	return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;	5229	return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5785	}	5230	}
		5231	#define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000
5786	#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000	5232	#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5787	#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14	5233	#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5788	static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)	5234	static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5789	{	5235	{
5790	return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;	5236	return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5791	}	5237	}
5792	#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000	5238
5793	#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20	5239	#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
5794	static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5795	{
5796	return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
5797	}
5798	#define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
5799	#define A6XX_SP_DS_CTRL_REG0_DIFF_FINE 0x00800000
5800	#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
5801	#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
5802		5240
5803	#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842	5241	#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
5804	#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f	5242	#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
@@ -5807,6 +5245,12 @@ static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) · 2 unmodified lines
5807	{	5245	{
5808	return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;	5246	return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5809	}	5247	}
		5248	#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
		5249	#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
		5250	static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
		5251	{
		5252	return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
		5253	}
5810		5254
5811	static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }	5255	static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5812		5256
@@ -5864,11 +5308,46 @@ static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) · 51 unmodified lines
5864	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;	5308	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5865	}	5309	}
5866		5310
5867	#define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b	5311	#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
		5312
		5313	#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
		5314	#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff
		5315	#define A6XX_SP_DS_OBJ_START__SHIFT 0
		5316	static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
		5317	{
		5318	return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
		5319	}
		5320
		5321	#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
		5322	#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
		5323	#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
		5324	static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
		5325	{
		5326	return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
		5327	}
		5328	#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
		5329	#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
		5330	static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
		5331	{
		5332	return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
		5333	}
5868		5334
5869	#define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c	5335	#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
		5336	#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff
		5337	#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0
		5338	static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
		5339	{
		5340	return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
		5341	}
5870		5342
5871	#define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d	5343	#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
		5344	#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
		5345	#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
		5346	static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
		5347	{
		5348	return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
		5349	}
		5350	#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5872		5351
5873	#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862	5352	#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
5874		5353
@@ -5890,7 +5369,7 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) · 15 unmodified lines
5890	{	5369	{
5891	return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;	5370	return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5892	}	5371	}
5893	#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000	5372	#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000
5894	#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22	5373	#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
5895	static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)	5374	static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5896	{	5375	{
@@ -5899,7 +5378,22 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
5899		5378
5900	#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864	5379	#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
5901		5380
		5381	#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
		5382	#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
		5383	#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
		5384	static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
		5385	{
		5386	return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK;
		5387	}
		5388
5902	#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870	5389	#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
		5390	#define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000
		5391	#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
		5392	#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
		5393	static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
		5394	{
		5395	return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
		5396	}
5903	#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e	5397	#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5904	#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1	5398	#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5905	static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)	5399	static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -5912,22 +5406,13 @@ static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
5912	{	5406	{
5913	return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;	5407	return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5914	}	5408	}
		5409	#define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000
5915	#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000	5410	#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5916	#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14	5411	#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5917	static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)	5412	static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5918	{	5413	{
5919	return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;	5414	return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5920	}	5415	}
5921	#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5922	#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20
5923	static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5924	{
5925	return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
5926	}
5927	#define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
5928	#define A6XX_SP_GS_CTRL_REG0_DIFF_FINE 0x00800000
5929	#define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
5930	#define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
5931		5416
5932	#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871	5417	#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
5933		5418
@@ -6003,9 +5488,46 @@ static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) · 69 unmodified lines
6003	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;	5488	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
6004	}	5489	}
6005		5490
6006	#define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d	5491	#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
6007		5492
6008	#define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e	5493	#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
		5494	#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff
		5495	#define A6XX_SP_GS_OBJ_START__SHIFT 0
		5496	static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
		5497	{
		5498	return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
		5499	}
		5500
		5501	#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
		5502	#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
		5503	#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
		5504	static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
		5505	{
		5506	return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
		5507	}
		5508	#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
		5509	#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
		5510	static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
		5511	{
		5512	return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
		5513	}
		5514
		5515	#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
		5516	#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff
		5517	#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0
		5518	static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
		5519	{
		5520	return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
		5521	}
		5522
		5523	#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
		5524	#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
		5525	#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
		5526	static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
		5527	{
		5528	return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
		5529	}
		5530	#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6009		5531
6010	#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893	5532	#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
6011		5533
@@ -6027,7 +5549,7 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) · 15 unmodified lines
6027	{	5549	{
6028	return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;	5550	return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
6029	}	5551	}
6030	#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000	5552	#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000
6031	#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22	5553	#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
6032	static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)	5554	static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
6033	{	5555	{
@@ -6036,39 +5558,104 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
6036		5558
6037	#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895	5559	#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
6038		5560
6039	#define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0	5561	#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
6040		5562	#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
6041	#define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1	5563	#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
6042		5564	static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
6043	#define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2	5565	{
6044		5566	return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK;
6045	#define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3	5567	}
6046
6047	#define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4
6048
6049	#define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5
6050
6051	#define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6
6052
6053	#define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7
6054		5568
6055	#define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8	5569	#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
		5570	#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff
		5571	#define A6XX_SP_VS_TEX_SAMP__SHIFT 0
		5572	static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
		5573	{
		5574	return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
		5575	}
6056		5576
6057	#define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9	5577	#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
		5578	#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff
		5579	#define A6XX_SP_HS_TEX_SAMP__SHIFT 0
		5580	static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
		5581	{
		5582	return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
		5583	}
6058		5584
6059	#define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa	5585	#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
		5586	#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff
		5587	#define A6XX_SP_DS_TEX_SAMP__SHIFT 0
		5588	static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
		5589	{
		5590	return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
		5591	}
6060		5592
6061	#define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab	5593	#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
		5594	#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff
		5595	#define A6XX_SP_GS_TEX_SAMP__SHIFT 0
		5596	static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
		5597	{
		5598	return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
		5599	}
6062		5600
6063	#define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac	5601	#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
		5602	#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff
		5603	#define A6XX_SP_VS_TEX_CONST__SHIFT 0
		5604	static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
		5605	{
		5606	return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
		5607	}
6064		5608
6065	#define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad	5609	#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
		5610	#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff
		5611	#define A6XX_SP_HS_TEX_CONST__SHIFT 0
		5612	static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
		5613	{
		5614	return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
		5615	}
6066		5616
6067	#define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae	5617	#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
		5618	#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff
		5619	#define A6XX_SP_DS_TEX_CONST__SHIFT 0
		5620	static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
		5621	{
		5622	return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
		5623	}
6068		5624
6069	#define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af	5625	#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
		5626	#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff
		5627	#define A6XX_SP_GS_TEX_CONST__SHIFT 0
		5628	static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
		5629	{
		5630	return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
		5631	}
6070		5632
6071	#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980	5633	#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
		5634	#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
		5635	#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
		5636	static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
		5637	{
		5638	return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
		5639	}
		5640	#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
		5641	#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
		5642	#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
		5643	#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
		5644	#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
		5645	#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
		5646	#define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000
		5647	#define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27
		5648	static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val)
		5649	{
		5650	return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK;
		5651	}
		5652	#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
		5653	#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
		5654	#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
		5655	static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
		5656	{
		5657	return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
		5658	}
6072	#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e	5659	#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6073	#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1	5660	#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
6074	static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)	5661	static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -6081,33 +5668,64 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
6081	{	5668	{
6082	return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;	5669	return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6083	}	5670	}
		5671	#define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000
6084	#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000	5672	#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6085	#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14	5673	#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
6086	static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)	5674	static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6087	{	5675	{
6088	return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;	5676	return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
6089	}	5677	}
6090	#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6091	#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
6092	static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
6093	{
6094	return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
6095	}
6096	#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
6097	#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
6098	#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
6099	#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
6100		5678
6101	#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981	5679	#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
6102		5680
6103	#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982	5681	#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
		5682
		5683	#define REG_A6XX_SP_FS_OBJ_START 0x0000a983
		5684	#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff
		5685	#define A6XX_SP_FS_OBJ_START__SHIFT 0
		5686	static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
		5687	{
		5688	return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
		5689	}
		5690
		5691	#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
		5692	#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
		5693	#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
		5694	static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
		5695	{
		5696	return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
		5697	}
		5698	#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
		5699	#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
		5700	static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
		5701	{
		5702	return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
		5703	}
6104		5704
6105	#define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983	5705	#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
		5706	#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff
		5707	#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0
		5708	static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
		5709	{
		5710	return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
		5711	}
6106		5712
6107	#define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984	5713	#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
		5714	#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
		5715	#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
		5716	static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
		5717	{
		5718	return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
		5719	}
		5720	#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6108		5721
6109	#define REG_A6XX_SP_BLEND_CNTL 0x0000a989	5722	#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
6110	#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001	5723	#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
		5724	#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
		5725	static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
		5726	{
		5727	return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
		5728	}
6111	#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100	5729	#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
6112	#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200	5730	#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
6113	#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400	5731	#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
@@ -6201,6 +5819,17 @@ static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) · 87 unmodified lines
6201	return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;	5819	return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
6202	}	5820	}
6203		5821
		5822	static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
		5823
		5824	static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
		5825	#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
		5826	#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
		5827	static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
		5828	{
		5829	return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
		5830	}
		5831	#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
		5832
6204	static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }	5833	static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6205		5834
6206	static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }	5835	static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
@@ -6212,6 +5841,7 @@ static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) · 5 unmodified lines
6212	}	5841	}
6213	#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100	5842	#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
6214	#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200	5843	#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
		5844	#define A6XX_SP_FS_MRT_REG_UNK10 0x00000400
6215		5845
6216	#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e	5846	#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
6217	#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007	5847	#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
@@ -6227,6 +5857,12 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val) · 9 unmodified lines
6227	{	5857	{
6228	return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;	5858	return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
6229	}	5859	}
		5860	#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000
		5861	#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12
		5862	static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val)
		5863	{
		5864	return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK;
		5865	}
6230		5866
6231	static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }	5867	static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6232		5868
@@ -6272,13 +5908,13 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val) · 39 unmodified lines
6272	static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }	5908	static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6273		5909
6274	static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }	5910	static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6275	#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x000000ff	5911	#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
6276	#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0	5912	#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
6277	static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)	5913	static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6278	{	5914	{
6279	return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;	5915	return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
6280	}	5916	}
6281	#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0x00ff0000	5917	#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000
6282	#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16	5918	#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
6283	static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)	5919	static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
6284	{	5920	{
@@ -6289,50 +5925,31 @@ static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) · 4 unmodified lines
6289		5925
6290	#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8	5926	#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
6291		5927
6292	#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1	5928	#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
6293	#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK 0x00000001	5929	#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
6294	#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT 0	5930	#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
6295	static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val)	5931	static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
6296	{	5932	{
6297	return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK;	5933	return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK;
6298	}	5934	}
6299		5935
6300	#define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3	5936	#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
6301		5937	#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6302	#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba	5938	#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
6303		5939	static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
6304	#define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
6305
6306	#define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
6307
6308	#define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2
6309
6310	#define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3
6311
6312	#define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4
6313
6314	#define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5
6315
6316	#define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6
6317
6318	#define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
6319
6320	static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6321
6322	static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6323
6324	static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6325
6326	static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6327	#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
6328	#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
6329	static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
6330	{	5940	{
6331	return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;	5941	return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
		5942	}
		5943	#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
		5944	#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
		5945	#define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000
		5946	#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
		5947	#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
		5948	#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
		5949	static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
		5950	{
		5951	return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
6332	}	5952	}
6333	#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
6334
6335	#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
6336	#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e	5953	#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6337	#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1	5954	#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
6338	static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)	5955	static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
@@ -6345,26 +5962,68 @@ static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) · 6 unmodified lines
6345	{	5962	{
6346	return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;	5963	return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6347	}	5964	}
		5965	#define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000
6348	#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000	5966	#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6349	#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14	5967	#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
6350	static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)	5968	static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6351	{	5969	{
6352	return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;	5970	return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
6353	}	5971	}
6354	#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000	5972
6355	#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20	5973	#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
6356	static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)	5974	#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
		5975	#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0
		5976	static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
6357	{	5977	{
6358	return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;	5978	return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
		5979	}
		5980	#define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020
		5981	#define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040
		5982
		5983	#define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2
		5984
		5985	#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
		5986
		5987	#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
		5988	#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff
		5989	#define A6XX_SP_CS_OBJ_START__SHIFT 0
		5990	static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
		5991	{
		5992	return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
		5993	}
		5994
		5995	#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
		5996	#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
		5997	#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
		5998	static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
		5999	{
		6000	return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
		6001	}
		6002	#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
		6003	#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
		6004	static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
		6005	{
		6006	return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
		6007	}
		6008
		6009	#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
		6010	#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff
		6011	#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0
		6012	static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
		6013	{
		6014	return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
6359	}	6015	}
6360	#define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
6361	#define A6XX_SP_CS_CTRL_REG0_DIFF_FINE 0x00800000
6362	#define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
6363	#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
6364		6016
6365	#define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4	6017	#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
		6018	#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
		6019	#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
		6020	static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
		6021	{
		6022	return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
		6023	}
		6024	#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6366		6025
6367	#define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5	6026	#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
6368		6027
6369	#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb	6028	#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
6370	#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001	6029	#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
@@ -6384,7 +6043,7 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) · 13 unmodified lines
6384	{	6043	{
6385	return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;	6044	return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6386	}	6045	}
6387	#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000	6046	#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000
6388	#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22	6047	#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
6389	static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)	6048	static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6390	{	6049	{
@@ -6393,13 +6052,65 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) · 2 unmodified lines
6393		6052
6394	#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc	6053	#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
6395		6054
6396	#define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2	6055	#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
		6056	#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
		6057	#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
		6058	static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
		6059	{
		6060	return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK;
		6061	}
		6062
		6063	#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
		6064	#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
		6065	#define A6XX_SP_FS_TEX_SAMP__SHIFT 0
		6066	static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
		6067	{
		6068	return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
		6069	}
		6070
		6071	#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
		6072	#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff
		6073	#define A6XX_SP_CS_TEX_SAMP__SHIFT 0
		6074	static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
		6075	{
		6076	return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
		6077	}
		6078
		6079	#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
		6080	#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff
		6081	#define A6XX_SP_FS_TEX_CONST__SHIFT 0
		6082	static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
		6083	{
		6084	return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
		6085	}
		6086
		6087	#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
		6088	#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff
		6089	#define A6XX_SP_CS_TEX_CONST__SHIFT 0
		6090	static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
		6091	{
		6092	return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
		6093	}
		6094
		6095	static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6397		6096
6398	#define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3	6097	static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
		6098
		6099	#define REG_A6XX_SP_CS_IBO 0x0000a9f2
		6100	#define A6XX_SP_CS_IBO__MASK 0xffffffff
		6101	#define A6XX_SP_CS_IBO__SHIFT 0
		6102	static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
		6103	{
		6104	return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
		6105	}
6399		6106
6400	#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00	6107	#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
6401		6108
6402	#define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00	6109	#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
		6110	#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
		6111	#define A6XX_SP_MODE_CONTROL_UNK1 0x00000002
		6112	#define A6XX_SP_MODE_CONTROL_UNK2 0x00000004
		6113	#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
6403		6114
6404	#define REG_A6XX_SP_FS_CONFIG 0x0000ab04	6115	#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
6405	#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001	6116	#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
@@ -6419,7 +6130,7 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) · 13 unmodified lines
6419	{	6130	{
6420	return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;	6131	return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6421	}	6132	}
6422	#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000	6133	#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000
6423	#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22	6134	#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
6424	static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)	6135	static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6425	{	6136	{
@@ -6432,9 +6143,13 @@ static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab1 · 6 unmodified lines
6432		6143
6433	static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }	6144	static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6434		6145
6435	#define REG_A6XX_SP_IBO_LO 0x0000ab1a	6146	#define REG_A6XX_SP_IBO 0x0000ab1a
6436		6147	#define A6XX_SP_IBO__MASK 0xffffffff
6437	#define REG_A6XX_SP_IBO_HI 0x0000ab1b	6148	#define A6XX_SP_IBO__SHIFT 0
		6149	static inline uint32_t A6XX_SP_IBO(uint32_t val)
		6150	{
		6151	return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
		6152	}
6438		6153
6439	#define REG_A6XX_SP_IBO_COUNT 0x0000ab20	6154	#define REG_A6XX_SP_IBO_COUNT 0x0000ab20
6440		6155
@@ -6458,18 +6173,41 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) · 17 unmodified lines
6458		6173
6459	#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00	6174	#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
6460		6175
		6176	#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
		6177
		6178	#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
		6179
6461	#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03	6180	#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
6462		6181
6463	#define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04	6182	#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
		6183	#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
		6184
		6185	#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
		6186	#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
		6187	#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
		6188	#define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004
		6189	#define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008
		6190	#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
		6191	#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
6464		6192
6465	#define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f	6193	static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
6466		6194
6467	#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180	6195	#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
		6196	#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
		6197	#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
		6198	static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
		6199	{
		6200	return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
		6201	}
6468		6202
6469	#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182	6203	#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
6470		6204
6471	#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183	6205	#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
6472		6206
		6207	#define REG_A6XX_SP_UNKNOWN_B190 0x0000b190
		6208
		6209	#define REG_A6XX_SP_UNKNOWN_B191 0x0000b191
		6210
6473	#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300	6211	#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
6474	#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003	6212	#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
6475	#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0	6213	#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
@@ -6477,6 +6215,12 @@ static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples v · 1 unmodified line
6477	{	6215	{
6478	return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;	6216	return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6479	}	6217	}
		6218	#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c
		6219	#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2
		6220	static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
		6221	{
		6222	return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
		6223	}
6480		6224
6481	#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301	6225	#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
6482	#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003	6226	#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
@@ -6488,10 +6232,12 @@ static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples · 5 unmodified lines
6488	#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004	6232	#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
6489		6233
6490	#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302	6234	#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6491		6235	#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6492	#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302	6236	#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6493		6237	static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6494	#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303	6238	{
		6239	return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
		6240	}
6495		6241
6496	#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304	6242	#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
6497	#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001	6243	#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
@@ -6597,6 +6343,20 @@ static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) · 99 unmodified lines
6597	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;	6343	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6598	}	6344	}
6599		6345
		6346	#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
		6347	#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff
		6348	#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
		6349	static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
		6350	{
		6351	return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
		6352	}
		6353	#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000
		6354	#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
		6355	static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
		6356	{
		6357	return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
		6358	}
		6359
6600	#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309	6360	#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
6601		6361
6602	#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0	6362	#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
@@ -6627,9 +6387,19 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val · 24 unmodified lines
6627	return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;	6387	return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6628	}	6388	}
6629	#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000	6389	#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
		6390	#define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
6630	#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000	6391	#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
		6392	#define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
6631	#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000	6393	#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
		6394	#define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
6632	#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000	6395	#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
		6396	#define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
		6397	#define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
		6398	static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
		6399	{
		6400	return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
		6401	}
		6402	#define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
6633		6403
6634	#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1	6404	#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
6635	#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff	6405	#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
@@ -6645,43 +6415,131 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) · 9 unmodified lines
6645	return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;	6415	return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6646	}	6416	}
6647		6417
6648	#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
6649
6650	#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
6651
6652	#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2	6418	#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
		6419	#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff
		6420	#define A6XX_SP_PS_2D_SRC__SHIFT 0
		6421	static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
		6422	{
		6423	return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
		6424	}
6653		6425
6654	#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4	6426	#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
6655	#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00	6427	#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
		6428	#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
		6429	static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
		6430	{
		6431	return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
		6432	}
		6433	#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
6656	#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9	6434	#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
6657	static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)	6435	static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6658	{	6436	{
6659	return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;	6437	return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6660	}	6438	}
6661		6439
6662	#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca	6440	#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
		6441	#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff
		6442	#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0
		6443	static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
		6444	{
		6445	return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
		6446	}
		6447
		6448	#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
		6449	#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
		6450	#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
		6451	static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
		6452	{
		6453	return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
		6454	}
6663		6455
6664	#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb	6456	#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
		6457	#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff
		6458	#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0
		6459	static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
		6460	{
		6461	return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
		6462	}
6665		6463
6666	#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca	6464	#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
		6465	#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff
		6466	#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0
		6467	static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
		6468	{
		6469	return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
		6470	}
6667		6471
6668	#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc	6472	#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
6669	#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff	6473	#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
6670	#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0	6474	#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
6671	static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)	6475	static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
		6476	{
		6477	return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
		6478	}
		6479
		6480	#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
		6481
		6482	#define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce
		6483
		6484	#define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf
		6485
		6486	#define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0
		6487
		6488	#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
		6489	#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
		6490	#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
		6491	static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
		6492	{
		6493	return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
		6494	}
		6495	#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
		6496	#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
		6497	static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
		6498	{
		6499	return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
		6500	}
		6501
		6502	#define REG_A6XX_TPL1_UNKNOWN_B600 0x0000b600
		6503
		6504	#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
		6505
		6506	#define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602
		6507
		6508	#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
		6509	#define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001
		6510	#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
		6511	#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
		6512	static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
		6513	{
		6514	return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
		6515	}
		6516	#define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
		6517	#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010
		6518	#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4
		6519	static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
6672	{	6520	{
6673	return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;	6521	return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
6674	}	6522	}
6675	#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800	6523	#define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0
6676	#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11	6524	#define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6
6677	static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)	6525	static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
6678	{	6526	{
6679	return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;	6527	return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
6680	}	6528	}
6681		6529
6682	#define REG_A6XX_SP_UNKNOWN_B600 0x0000b600	6530	#define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605
		6531
		6532	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
		6533
		6534	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
		6535
		6536	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
		6537
		6538	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
		6539
		6540	#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
6683		6541
6684	#define REG_A6XX_SP_UNKNOWN_B605 0x0000b605	6542	static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
6685		6543
6686	#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800	6544	#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
6687	#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff	6545	#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
@@ -6722,10 +6580,31 @@ static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) · 34 unmodified lines
6722	#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820	6580	#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
6723		6581
6724	#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821	6582	#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
		6583	#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff
		6584	#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0
		6585	static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
		6586	{
		6587	return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
		6588	}
6725		6589
6726	#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823	6590	#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
6727		6591
6728	#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980	6592	#define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980
		6593	#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
		6594	#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
		6595	static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
		6596	{
		6597	return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
		6598	}
		6599	#define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
		6600	#define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
		6601	#define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
		6602	static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
		6603	{
		6604	return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
		6605	}
		6606
		6607	#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
6729		6608
6730	#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982	6609	#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
6731		6610
@@ -6808,6 +6687,18 @@ static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) · 76 unmodified lines
6808	}	6687	}
6809		6688
6810	#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986	6689	#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
		6690	#define A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK 0x000000ff
		6691	#define A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT 0
		6692	static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK0(uint32_t val)
		6693	{
		6694	return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK;
		6695	}
		6696	#define A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK 0x0000ff00
		6697	#define A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT 8
		6698	static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK8(uint32_t val)
		6699	{
		6700	return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK;
		6701	}
6811		6702
6812	#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987	6703	#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
6813	#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff	6704	#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
@@ -6899,17 +6790,17 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) · 85 unmodified lines
6899	{	6790	{
6900	return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;	6791	return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
6901	}	6792	}
6902	#define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00	6793	#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
6903	#define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8	6794	#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
6904	static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)	6795	static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
6905	{	6796	{
6906	return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;	6797	return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
6907	}	6798	}
6908	#define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000	6799	#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
6909	#define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16	6800	#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
6910	static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)	6801	static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
6911	{	6802	{
6912	return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;	6803	return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
6913	}	6804	}
6914	#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000	6805	#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
6915	#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24	6806	#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
@@ -6918,7 +6809,21 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) · 2 unmodified lines
6918	return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;	6809	return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
6919	}	6810	}
6920		6811
6921	#define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998	6812	#define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998
		6813	#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
		6814	#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
		6815	static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
		6816	{
		6817	return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
		6818	}
		6819	#define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
		6820	#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
		6821	#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
		6822	static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
		6823	{
		6824	return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
		6825	}
		6826	#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
6922		6827
6923	#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999	6828	#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
6924		6829
@@ -6929,6 +6834,12 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) · 4 unmodified lines
6929	#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0	6834	#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
6930		6835
6931	#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1	6836	#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
		6837	#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff
		6838	#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0
		6839	static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
		6840	{
		6841	return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
		6842	}
6932		6843
6933	#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3	6844	#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
6934		6845
@@ -7026,6 +6937,12 @@ static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) · 91 unmodified lines
7026		6937
7027	#define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04	6938	#define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
7028		6939
		6940	#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
		6941
		6942	#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
		6943
		6944	static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
		6945
7029	#define REG_A6XX_CP_EVENT_START 0x0000d600	6946	#define REG_A6XX_CP_EVENT_START 0x0000d600
7030	#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff	6947	#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
7031	#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0	6948	#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
@@ -7135,11 +7052,11 @@ static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode v · 103 unmodified lines
7135	return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;	7052	return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7136	}	7053	}
7137	#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020	7054	#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
7138	#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80	7055	#define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80
7139	#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7	7056	#define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7
7140	static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)	7057	static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
7141	{	7058	{
7142	return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;	7059	return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
7143	}	7060	}
7144		7061
7145	#define REG_A6XX_TEX_SAMP_3 0x00000003	7062	#define REG_A6XX_TEX_SAMP_3 0x00000003

drivers/gpu/drm/msm/adreno/a6xx_gmu.c+42−13

 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 	struct platform_device *pdev = to_platform_device(gmu->dev);
 	void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
-	void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
+	void __iomem *seqptr;
 	uint32_t pdc_address_offset;
+	bool pdc_in_aop = false;
-	if (!pdcptr || !seqptr)
+	if (!pdcptr)
 		goto err;
-	if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
+	if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
+		pdc_in_aop = true;
+	else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
 		pdc_address_offset = 0x30090;
-	else if (adreno_is_a650(adreno_gpu))
-		pdc_address_offset = 0x300a0;
 	else
 		pdc_address_offset = 0x30080;
+	if (!pdc_in_aop) {
+		seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
+		if (!seqptr)
+			goto err;
+	}
 	/* Disable SDE clock gating */
 	gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
 	/* Load RSC sequencer uCode for sleep and wakeup */
-	if (adreno_is_a650(adreno_gpu)) {
+	if (adreno_is_a650_family(adreno_gpu)) {
 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
 	}
+	if (pdc_in_aop)
+		goto setup_pdc;
 	/* Load PDC sequencer uCode for power up and power down sequence */
 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
-	if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
+	if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
 	else
 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
 	/* Setup GPU PDC */
+setup_pdc:
 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
 	u32 itcm_base = 0x00000000;
 	u32 dtcm_base = 0x00040000;
-	if (adreno_is_a650(adreno_gpu))
+	if (adreno_is_a650_family(adreno_gpu))
 		dtcm_base = 0x10004000;
 	if (gmu->legacy) {
 	int ret;
 	u32 chipid;
-	if (adreno_is_a650(adreno_gpu))
+	if (adreno_is_a650_family(adreno_gpu)) {
+		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
+	}
 	if (state == GMU_WARM_BOOT) {
 		ret = a6xx_rpmh_start(gmu);
 	 * The GMU handles its own frequency switching so build a list of
 	 * available frequencies to send during initialization
 	 */
-	ret = dev_pm_opp_of_add_table(gmu->dev);
+	ret = devm_pm_opp_of_add_table(gmu->dev);
 	if (ret) {
 		DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
 		return ret;
 	if (ret)
 		goto err_put_device;
+	/* A660 now requires handling "prealloc requests" in GMU firmware
+	 * For now just hardcode allocations based on the known firmware.
+	 * note: there is no indication that these correspond to "dummy" or
+	 * "debug" regions, but this "guess" allows reusing these BOs which
+	 * are otherwise unused by a660.
+	 */
+	gmu->dummy.size = SZ_4K;
+	if (adreno_is_a660(adreno_gpu)) {
+		ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000);
+		if (ret)
+			goto err_memory;
+		gmu->dummy.size = SZ_8K;
+	}
 	/* Allocate memory for the GMU dummy page */
-	ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
+	ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000);
 	if (ret)
 		goto err_memory;
-	if (adreno_is_a650(adreno_gpu)) {
+	if (adreno_is_a650_family(adreno_gpu)) {
 		ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
 			SZ_16M - SZ_16K, 0x04000);
 		if (ret)
 		goto err_memory;
 	}
-	if (adreno_is_a650(adreno_gpu)) {
+	if (adreno_is_a650_family(adreno_gpu)) {
 		gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
 		if (IS_ERR(gmu->rscc))
 			goto err_mmio;

drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h+19−15

@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16	- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17	- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18	- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19	- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20	- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22	- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23	- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24		24
25	Copyright (C) 2013-2020 by the following authors:	25	Copyright (C) 2013-2021 by the following authors:
26	- Rob Clark <robdclark@gmail.com> (robclark)	26	- Rob Clark <robdclark@gmail.com> (robclark)
27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28		28
@@ -292,6 +292,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) · 263 unmodified lines
292		292
293	#define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0	293	#define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0
294		294
		295	#define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1
		296
295	#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100	297	#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100
296		298
297	#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101	299	#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101
@@ -439,6 +441,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) · 141 unmodified lines
439		441
440	#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42	442	#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
441		443
		444	#define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001
		445
442	#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004	446	#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
443		447
444	#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008	448	#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008

drivers/gpu/drm/msm/adreno/a6xx_gpu.c+258−47

@@ -149,7 +149,7 @@ static void a6xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit) · 148 unmodified lines
149		149
150	a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);	150	a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
151		151
152	get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,	152	get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
153	rbmemptr_stats(ring, index, cpcycles_start));	153	rbmemptr_stats(ring, index, cpcycles_start));
154		154
155	/*	155	/*
@@ -185,7 +185,7 @@ static void a6xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit) · 29 unmodified lines
185	}	185	}
186	}	186	}
187		187
188	get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,	188	get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
189	rbmemptr_stats(ring, index, cpcycles_end));	189	rbmemptr_stats(ring, index, cpcycles_end));
190	get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,	190	get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
191	rbmemptr_stats(ring, index, alwayson_end));	191	rbmemptr_stats(ring, index, alwayson_end));
@@ -427,6 +427,59 @@ const struct adreno_reglist a650_hwcg[] = { · 235 unmodified lines
427	{},	427	{},
428	};	428	};
429		429
		430	const struct adreno_reglist a660_hwcg[] = {
		431	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
		432	{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
		433	{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
		434	{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
		435	{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
		436	{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
		437	{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
		438	{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
		439	{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
		440	{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
		441	{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
		442	{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
		443	{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
		444	{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
		445	{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
		446	{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
		447	{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
		448	{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
		449	{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
		450	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
		451	{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
		452	{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
		453	{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
		454	{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
		455	{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
		456	{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
		457	{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
		458	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
		459	{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
		460	{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
		461	{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
		462	{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
		463	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
		464	{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
		465	{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
		466	{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
		467	{REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
		468	{REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
		469	{REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
		470	{REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
		471	{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
		472	{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
		473	{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
		474	{REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
		475	{REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
		476	{REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
		477	{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
		478	{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
		479	{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
		480	{},
		481	};
		482
430	static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)	483	static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
431	{	484	{
432	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);	485	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -541,6 +594,51 @@ static const u32 a650_protect[] = { · 108 unmodified lines
541	A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */	594	A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
542	};	595	};
543		596
		597	/* These are for a635 and a660 */
		598	static const u32 a660_protect[] = {
		599	A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
		600	A6XX_PROTECT_RDONLY(0x00501, 0x0005),
		601	A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
		602	A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
		603	A6XX_PROTECT_NORDWR(0x00510, 0x0000),
		604	A6XX_PROTECT_NORDWR(0x00534, 0x0000),
		605	A6XX_PROTECT_NORDWR(0x00800, 0x0082),
		606	A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
		607	A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
		608	A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
		609	A6XX_PROTECT_NORDWR(0x00900, 0x004d),
		610	A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
		611	A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
		612	A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
		613	A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
		614	A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
		615	A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
		616	A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
		617	A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
		618	A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
		619	A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
		620	A6XX_PROTECT_NORDWR(0x09624, 0x01db),
		621	A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
		622	A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
		623	A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
		624	A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
		625	A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
		626	A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
		627	A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
		628	A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
		629	A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
		630	A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
		631	A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
		632	A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
		633	A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
		634	A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
		635	A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
		636	A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
		637	A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
		638	A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
		639	A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
		640	};
		641
544	static void a6xx_set_cp_protect(struct msm_gpu *gpu)	642	static void a6xx_set_cp_protect(struct msm_gpu *gpu)
545	{	643	{
546	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);	644	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -554,6 +652,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) · 7 unmodified lines
554	regs = a650_protect;	652	regs = a650_protect;
555	count = ARRAY_SIZE(a650_protect);	653	count = ARRAY_SIZE(a650_protect);
556	count_max = 48;	654	count_max = 48;
		655	} else if (adreno_is_a660(adreno_gpu)) {
		656	regs = a660_protect;
		657	count = ARRAY_SIZE(a660_protect);
		658	count_max = 48;
557	}	659	}
558		660
559	/*	661	/*
@@ -584,7 +686,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) · 24 unmodified lines
584	if (adreno_is_a640(adreno_gpu))	686	if (adreno_is_a640(adreno_gpu))
585	amsbc = 1;	687	amsbc = 1;
586		688
587	if (adreno_is_a650(adreno_gpu)) {	689	if (adreno_is_a650(adreno_gpu) \|\| adreno_is_a660(adreno_gpu)) {
588	/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */	690	/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
589	lower_bit = 3;	691	lower_bit = 3;
590	amsbc = 1;	692	amsbc = 1;
@@ -648,6 +750,11 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, · 57 unmodified lines
648	* Targets up to a640 (a618, a630 and a640) need to check for a	750	* Targets up to a640 (a618, a630 and a640) need to check for a
649	* microcode version that is patched to support the whereami opcode or	751	* microcode version that is patched to support the whereami opcode or
650	* one that is new enough to include it by default.	752	* one that is new enough to include it by default.
		753	*
		754	* a650 tier targets don't need whereami but still need to be
		755	* equal to or newer than 0.95 for other security fixes
		756	*
		757	* a660 targets have all the critical security fixes from the start
651	*/	758	*/
652	if (adreno_is_a618(adreno_gpu) \|\| adreno_is_a630(adreno_gpu) \|\|	759	if (adreno_is_a618(adreno_gpu) \|\| adreno_is_a630(adreno_gpu) \|\|
653	adreno_is_a640(adreno_gpu)) {	760	adreno_is_a640(adreno_gpu)) {
@@ -671,27 +778,20 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, · 17 unmodified lines
671	DRM_DEV_ERROR(&gpu->pdev->dev,	778	DRM_DEV_ERROR(&gpu->pdev->dev,
672	"a630 SQE ucode is too old. Have version %x need at least %x\n",	779	"a630 SQE ucode is too old. Have version %x need at least %x\n",
673	buf[0] & 0xfff, 0x190);	780	buf[0] & 0xfff, 0x190);
674	} else {	781	} else if (adreno_is_a650(adreno_gpu)) {
675	/*	782	if ((buf[0] & 0xfff) >= 0x095) {
676	* a650 tier targets don't need whereami but still need to be	783	ret = true;
677	* equal to or newer than 0.95 for other security fixes	784	goto out;
678	*/
679	if (adreno_is_a650(adreno_gpu)) {
680	if ((buf[0] & 0xfff) >= 0x095) {
681	ret = true;
682	goto out;
683	}
684
685	DRM_DEV_ERROR(&gpu->pdev->dev,
686	"a650 SQE ucode is too old. Have version %x need at least %x\n",
687	buf[0] & 0xfff, 0x095);
688	}	785	}
689		786
690	/*	787	DRM_DEV_ERROR(&gpu->pdev->dev,
691	* When a660 is added those targets should return true here	788	"a650 SQE ucode is too old. Have version %x need at least %x\n",
692	* since those have all the critical security fixes built in	789	buf[0] & 0xfff, 0x095);
693	* from the start	790	} else if (adreno_is_a660(adreno_gpu)) {
694	*/	791	ret = true;
		792	} else {
		793	DRM_DEV_ERROR(&gpu->pdev->dev,
		794	"unknown GPU, add it to a6xx_ucode_check_version()!!\n");
695	}	795	}
696	out:	796	out:
697	msm_gem_put_vaddr(obj);	797	msm_gem_put_vaddr(obj);
@@ -727,8 +827,8 @@ static int a6xx_ucode_init(struct msm_gpu *gpu) · 29 unmodified lines
727	}	827	}
728	}	828	}
729		829
730	gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,	830	gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE,
731	REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);	831	REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova);
732		832
733	return 0;	833	return 0;
734	}	834	}
@@ -797,7 +897,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 62 unmodified lines
797	a6xx_set_hwcg(gpu, true);	897	a6xx_set_hwcg(gpu, true);
798		898
799	/* VBIF/GBIF start*/	899	/* VBIF/GBIF start*/
800	if (adreno_is_a640(adreno_gpu) \|\| adreno_is_a650(adreno_gpu)) {	900	if (adreno_is_a640(adreno_gpu) \|\| adreno_is_a650_family(adreno_gpu)) {
801	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);	901	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
802	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);	902	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
803	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);	903	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
@@ -822,7 +922,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 18 unmodified lines
822	gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);	922	gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
823	gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);	923	gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
824		924
825	if (!adreno_is_a650(adreno_gpu)) {	925	if (!adreno_is_a650_family(adreno_gpu)) {
826	/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */	926	/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
827	gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,	927	gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
828	REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);	928	REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
@@ -835,22 +935,27 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 6 unmodified lines
835	gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);	935	gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
836	gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);	936	gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
837		937
838	if (adreno_is_a640(adreno_gpu) \|\| adreno_is_a650(adreno_gpu))	938	if (adreno_is_a640(adreno_gpu) \|\| adreno_is_a650_family(adreno_gpu))
839	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);	939	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
840	else	940	else
841	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);	941	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
842	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);	942	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
843		943
		944	if (adreno_is_a660(adreno_gpu))
		945	gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
		946
844	/* Setting the mem pool size */	947	/* Setting the mem pool size */
845	gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);	948	gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
846		949
847	/* Setting the primFifo thresholds default values */	950	/* Setting the primFifo thresholds default values,
848	if (adreno_is_a650(adreno_gpu))	951	* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
849	gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);	952	*/
		953	if (adreno_is_a650(adreno_gpu) \|\| adreno_is_a660(adreno_gpu))
		954	gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
850	else if (adreno_is_a640(adreno_gpu))	955	else if (adreno_is_a640(adreno_gpu))
851	gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);	956	gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
852	else	957	else
853	gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));	958	gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
854		959
855	/* Set the AHB default slave response to "ERROR" */	960	/* Set the AHB default slave response to "ERROR" */
856	gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);	961	gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
@@ -859,7 +964,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 2 unmodified lines
859	gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);	964	gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
860		965
861	/* Select CP0 to always count cycles */	966	/* Select CP0 to always count cycles */
862	gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);	967	gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
863		968
864	a6xx_set_ubwc_config(gpu);	969	a6xx_set_ubwc_config(gpu);
865		970
@@ -870,7 +975,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 4 unmodified lines
870	gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);	975	gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
871		976
872	/* Set weights for bicubic filtering */	977	/* Set weights for bicubic filtering */
873	if (adreno_is_a650(adreno_gpu)) {	978	if (adreno_is_a650_family(adreno_gpu)) {
874	gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);	979	gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
875	gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,	980	gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
876	0x3fe05ff4);	981	0x3fe05ff4);
@@ -885,6 +990,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 8 unmodified lines
885	/* Protect registers from the CP */	990	/* Protect registers from the CP */
886	a6xx_set_cp_protect(gpu);	991	a6xx_set_cp_protect(gpu);
887		992
		993	if (adreno_is_a660(adreno_gpu)) {
		994	gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
		995	gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
		996	/* Set dualQ + disable afull for A660 GPU but not for A635 */
		997	gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
		998	}
		999
888	/* Enable expanded apriv for targets that support it */	1000	/* Enable expanded apriv for targets that support it */
889	if (gpu->hw_apriv) {	1001	if (gpu->hw_apriv) {
890	gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,	1002	gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
@@ -925,7 +1037,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) · 34 unmodified lines
925	if (!a6xx_gpu->shadow_bo) {	1037	if (!a6xx_gpu->shadow_bo) {
926	a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev,	1038	a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev,
927	sizeof(u32) * gpu->nr_rings,	1039	sizeof(u32) * gpu->nr_rings,
928	MSM_BO_UNCACHED \| MSM_BO_MAP_PRIV,	1040	MSM_BO_WC \| MSM_BO_MAP_PRIV,
929	gpu->aspace, &a6xx_gpu->shadow_bo,	1041	gpu->aspace, &a6xx_gpu->shadow_bo,
930	&a6xx_gpu->shadow_iova);	1042	&a6xx_gpu->shadow_iova);
931		1043
@@ -1032,18 +1144,113 @@ static void a6xx_recover(struct msm_gpu *gpu) · 100 unmodified lines
1032	msm_gpu_hw_init(gpu);	1144	msm_gpu_hw_init(gpu);
1033	}	1145	}
1034		1146
1035	static int a6xx_fault_handler(void *arg, unsigned long iova, int flags)	1147	static const char a6xx_uche_fault_block(struct msm_gpu gpu, u32 mid)
		1148	{
		1149	static const char *uche_clients[7] = {
		1150	"VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",
		1151	};
		1152	u32 val;
		1153
		1154	if (mid < 1 \|\| mid > 3)
		1155	return "UNKNOWN";
		1156
		1157	/*
		1158	* The source of the data depends on the mid ID read from FSYNR1.
		1159	* and the client ID read from the UCHE block
		1160	*/
		1161	val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
		1162
		1163	/* mid = 3 is most precise and refers to only one block per client */
		1164	if (mid == 3)
		1165	return uche_clients[val & 7];
		1166
		1167	/* For mid=2 the source is TP or VFD except when the client id is 0 */
		1168	if (mid == 2)
		1169	return ((val & 7) == 0) ? "TP" : "TP\|VFD";
		1170
		1171	/* For mid=1 just return "UCHE" as a catchall for everything else */
		1172	return "UCHE";
		1173	}
		1174
		1175	static const char a6xx_fault_block(struct msm_gpu gpu, u32 id)
		1176	{
		1177	if (id == 0)
		1178	return "CP";
		1179	else if (id == 4)
		1180	return "CCU";
		1181	else if (id == 6)
		1182	return "CDP Prefetch";
		1183
		1184	return a6xx_uche_fault_block(gpu, id);
		1185	}
		1186
		1187	#define ARM_SMMU_FSR_TF BIT(1)
		1188	#define ARM_SMMU_FSR_PF BIT(3)
		1189	#define ARM_SMMU_FSR_EF BIT(4)
		1190
		1191	static int a6xx_fault_handler(void arg, unsigned long iova, int flags, void data)
1036	{	1192	{
1037	struct msm_gpu *gpu = arg;	1193	struct msm_gpu *gpu = arg;
		1194	struct adreno_smmu_fault_info *info = data;
		1195	const char *type = "UNKNOWN";
		1196	const char *block;
		1197	bool do_devcoredump = info && !READ_ONCE(gpu->crashstate);
		1198
		1199	/*
		1200	* If we aren't going to be resuming later from fault_worker, then do
		1201	* it now.
		1202	*/
		1203	if (!do_devcoredump) {
		1204	gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
		1205	}
1038		1206
1039	pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",	1207	/*
		1208	* Print a default message if we couldn't get the data from the
		1209	* adreno-smmu-priv
		1210	*/
		1211	if (!info) {
		1212	pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n",
1040	iova, flags,	1213	iova, flags,
1041	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),	1214	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1042	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),	1215	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1043	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),	1216	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1044	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));	1217	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1045		1218
1046	return -EFAULT;	1219	return 0;
		1220	}
		1221
		1222	if (info->fsr & ARM_SMMU_FSR_TF)
		1223	type = "TRANSLATION";
		1224	else if (info->fsr & ARM_SMMU_FSR_PF)
		1225	type = "PERMISSION";
		1226	else if (info->fsr & ARM_SMMU_FSR_EF)
		1227	type = "EXTERNAL";
		1228
		1229	block = a6xx_fault_block(gpu, info->fsynr1 & 0xff);
		1230
		1231	pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
		1232	info->ttbr0, iova,
		1233	flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ",
		1234	type, block,
		1235	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
		1236	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
		1237	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
		1238	gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
		1239
		1240	if (do_devcoredump) {
		1241	/* Turn off the hangcheck timer to keep it from bothering us */
		1242	del_timer(&gpu->hangcheck_timer);
		1243
		1244	gpu->fault_info.ttbr0 = info->ttbr0;
		1245	gpu->fault_info.iova = iova;
		1246	gpu->fault_info.flags = flags;
		1247	gpu->fault_info.type = type;
		1248	gpu->fault_info.block = block;
		1249
		1250	kthread_queue_work(gpu->worker, &gpu->fault_work);
		1251	}
		1252
		1253	return 0;
1047	}	1254	}
1048		1255
1049	static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)	1256	static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
@@ -1094,6 +1301,15 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) · 44 unmodified lines
1094	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);	1301	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1095	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);	1302	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1096		1303
		1304	/*
		1305	* If stalled on SMMU fault, we could trip the GPU's hang detection,
		1306	* but the fault handler will trigger the devcore dump, and we want
		1307	* to otherwise resume normally rather than killing the submit, so
		1308	* just bail.
		1309	*/
		1310	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)
		1311	return;
		1312
1097	/*	1313	/*
1098	* Force the GPU to stay on until after we finish	1314	* Force the GPU to stay on until after we finish
1099	* collecting information	1315	* collecting information
@@ -1339,9 +1555,6 @@ static void a6xx_destroy(struct msm_gpu *gpu) · 239 unmodified lines
1339		1555
1340	adreno_gpu_cleanup(adreno_gpu);	1556	adreno_gpu_cleanup(adreno_gpu);
1341		1557
1342	if (a6xx_gpu->opp_table)
1343	dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table);
1344
1345	kfree(a6xx_gpu);	1558	kfree(a6xx_gpu);
1346	}	1559	}
1347		1560
@@ -1474,7 +1687,6 @@ static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) · 126 unmodified lines
1474	static int a6xx_set_supported_hw(struct device dev, struct a6xx_gpu a6xx_gpu,	1687	static int a6xx_set_supported_hw(struct device dev, struct a6xx_gpu a6xx_gpu,
1475	u32 revn)	1688	u32 revn)
1476	{	1689	{
1477	struct opp_table *opp_table;
1478	u32 supp_hw = UINT_MAX;	1690	u32 supp_hw = UINT_MAX;
1479	u16 speedbin;	1691	u16 speedbin;
1480	int ret;	1692	int ret;
@@ -1497,11 +1709,10 @@ static int a6xx_set_supported_hw(struct device dev, struct a6xx_gpu a6xx_gpu, · 16 unmodified lines
1497	supp_hw = fuse_to_supp_hw(dev, revn, speedbin);	1709	supp_hw = fuse_to_supp_hw(dev, revn, speedbin);
1498		1710
1499	done:	1711	done:
1500	opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1);	1712	ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1501	if (IS_ERR(opp_table))	1713	if (ret)
1502	return PTR_ERR(opp_table);	1714	return ret;
1503		1715
1504	a6xx_gpu->opp_table = opp_table;
1505	return 0;	1716	return 0;
1506	}	1717	}
1507		1718
@@ -1561,7 +1772,7 @@ struct msm_gpu a6xx_gpu_init(struct drm_device dev) · 53 unmodified lines
1561	*/	1772	*/
1562	info = adreno_info(config->rev);	1773	info = adreno_info(config->rev);
1563		1774
1564	if (info && info->revn == 650)	1775	if (info && (info->revn == 650 \|\| info->revn == 660))
1565	adreno_gpu->base.hw_apriv = true;	1776	adreno_gpu->base.hw_apriv = true;
1566		1777
1567	a6xx_llc_slices_init(pdev, a6xx_gpu);	1778	a6xx_llc_slices_init(pdev, a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h+0−2

@@ -33,8 +33,6 @@ struct a6xx_gpu { · 32 unmodified lines
33	void *llc_slice;	33	void *llc_slice;
34	void *htw_llc_slice;	34	void *htw_llc_slice;
35	bool have_mmu500;	35	bool have_mmu500;
36
37	struct opp_table *opp_table;
38	};	36	};
39		37
40	#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)	38	#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c+35−9

 		struct a6xx_crashdumper *dumper)
 {
 	dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
-		SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
+		SZ_1M, MSM_BO_WC, gpu->aspace,
 		&dumper->bo, &dumper->iova);
 	if (!IS_ERR(dumper->ptr))
 		a6xx_get_ahb_gpu_registers(gpu,
 				a6xx_state, &a6xx_vbif_reglist,
 				&a6xx_state->registers[index++]);
+	if (!dumper) {
+		/*
+		 * We can't use the crashdumper when the SMMU is stalled,
+		 * because the GPU has no memory access until we resume
+		 * translation (but we don't want to do that until after
+		 * we have captured as much useful GPU state as possible).
+		 * So instead collect registers via the CPU:
+		 */
+		for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
+			a6xx_get_ahb_gpu_registers(gpu,
+				a6xx_state, &a6xx_reglist[i],
+				&a6xx_state->registers[index++]);
+		return;
+	}
 	for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
 		a6xx_get_crashdumper_registers(gpu,
 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
 {
-	struct a6xx_crashdumper dumper = { 0 };
+	struct a6xx_crashdumper _dumper = { 0 }, *dumper = NULL;
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 	struct a6xx_gpu_state *a6xx_state = kzalloc(sizeof(*a6xx_state),
 		GFP_KERNEL);
+	bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) &
+			A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT);
 	if (!a6xx_state)
 		return ERR_PTR(-ENOMEM);
 	/* Get the banks of indexed registers */
 	a6xx_get_indexed_registers(gpu, a6xx_state);
-	/* Try to initialize the crashdumper */
+	/*
-	if (!a6xx_crashdumper_init(gpu, &dumper)) {
+	 * Try to initialize the crashdumper, if we are not dumping state
-		a6xx_get_registers(gpu, a6xx_state, &dumper);
+	 * with the SMMU stalled.  The crashdumper needs memory access to
-		a6xx_get_shaders(gpu, a6xx_state, &dumper);
+	 * write out GPU state, so we need to skip this when the SMMU is
-		a6xx_get_clusters(gpu, a6xx_state, &dumper);
+	 * stalled in response to an iova fault
-		a6xx_get_dbgahb_clusters(gpu, a6xx_state, &dumper);
+	 */
+	if (!stalled && !a6xx_crashdumper_init(gpu, &_dumper)) {
+		dumper = &_dumper;
+	}
+	a6xx_get_registers(gpu, a6xx_state, dumper);
+	if (dumper) {
+		a6xx_get_shaders(gpu, a6xx_state, dumper);
+		a6xx_get_clusters(gpu, a6xx_state, dumper);
+		a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
-		msm_gem_kernel_put(dumper.bo, gpu->aspace, true);
+		msm_gem_kernel_put(dumper->bo, gpu->aspace, true);
 	}
 	if (snapshot_debugbus)

drivers/gpu/drm/msm/adreno/a6xx_hfi.c+33−0

@@ -351,6 +351,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) · 350 unmodified lines
351	msg->cnoc_cmds_data[1][0] = 0x60000001;	351	msg->cnoc_cmds_data[1][0] = 0x60000001;
352	}	352	}
353		353
		354	static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
		355	{
		356	/*
		357	* Send a single "off" entry just to get things running
		358	* TODO: bus scaling
		359	*/
		360	msg->bw_level_num = 1;
		361
		362	msg->ddr_cmds_num = 3;
		363	msg->ddr_wait_bitmask = 0x01;
		364
		365	msg->ddr_cmds_addrs[0] = 0x50004;
		366	msg->ddr_cmds_addrs[1] = 0x500a0;
		367	msg->ddr_cmds_addrs[2] = 0x50000;
		368
		369	msg->ddr_cmds_data[0][0] = 0x40000000;
		370	msg->ddr_cmds_data[0][1] = 0x40000000;
		371	msg->ddr_cmds_data[0][2] = 0x40000000;
		372
		373	/*
		374	* These are the CX (CNOC) votes - these are used by the GMU but the
		375	* votes are known and fixed for the target
		376	*/
		377	msg->cnoc_cmds_num = 1;
		378	msg->cnoc_wait_bitmask = 0x01;
		379
		380	msg->cnoc_cmds_addrs[0] = 0x50070;
		381	msg->cnoc_cmds_data[0][0] = 0x40000000;
		382	msg->cnoc_cmds_data[1][0] = 0x60000001;
		383	}
		384
354	static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)	385	static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
355	{	386	{
356	/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */	387	/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
@@ -401,6 +432,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) · 44 unmodified lines
401	a640_build_bw_table(&msg);	432	a640_build_bw_table(&msg);
402	else if (adreno_is_a650(adreno_gpu))	433	else if (adreno_is_a650(adreno_gpu))
403	a650_build_bw_table(&msg);	434	a650_build_bw_table(&msg);
		435	else if (adreno_is_a660(adreno_gpu))
		436	a660_build_bw_table(&msg);
404	else	437	else
405	a6xx_build_bw_table(&msg);	438	a6xx_build_bw_table(&msg);
406		439

drivers/gpu/drm/msm/adreno/adreno_common.xml.h+15−15

@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16	- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17	- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18	- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19	- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20	- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22	- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23	- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24		24
25	Copyright (C) 2013-2020 by the following authors:	25	Copyright (C) 2013-2021 by the following authors:
26	- Rob Clark <robdclark@gmail.com> (robclark)	26	- Rob Clark <robdclark@gmail.com> (robclark)
27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28		28

drivers/gpu/drm/msm/adreno/adreno_device.c+14−0

@@ -287,6 +287,19 @@ static const struct adreno_info gpulist[] = { · 286 unmodified lines
287	.init = a6xx_gpu_init,	287	.init = a6xx_gpu_init,
288	.zapfw = "a650_zap.mdt",	288	.zapfw = "a650_zap.mdt",
289	.hwcg = a650_hwcg,	289	.hwcg = a650_hwcg,
		290	}, {
		291	.rev = ADRENO_REV(6, 6, 0, ANY_ID),
		292	.revn = 660,
		293	.name = "A660",
		294	.fw = {
		295	[ADRENO_FW_SQE] = "a660_sqe.fw",
		296	[ADRENO_FW_GMU] = "a660_gmu.bin",
		297	},
		298	.gmem = SZ_1M + SZ_512K,
		299	.inactive_period = DRM_MSM_INACTIVE_PERIOD,
		300	.init = a6xx_gpu_init,
		301	.zapfw = "a660_zap.mdt",
		302	.hwcg = a660_hwcg,
290	},	303	},
291	};	304	};
292		305
@@ -466,6 +479,7 @@ static int adreno_bind(struct device dev, struct device master, void *data) · 173 unmodified lines
466	config.rev.minor, config.rev.patchid);	479	config.rev.minor, config.rev.patchid);
467		480
468	priv->is_a2xx = config.rev.core == 2;	481	priv->is_a2xx = config.rev.core == 2;
		482	priv->has_cached_coherent = config.rev.core >= 6;
469		483
470	gpu = info->init(drm);	484	gpu = info->init(drm);
471	if (IS_ERR(gpu)) {	485	if (IS_ERR(gpu)) {

drivers/gpu/drm/msm/adreno/adreno_gpu.c+19−7

 		*value = adreno_gpu->gmem;
 		return 0;
 	case MSM_PARAM_GMEM_BASE:
-		*value = !adreno_is_a650(adreno_gpu) ? 0x100000 : 0;
+		*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
 		return 0;
 	case MSM_PARAM_CHIP_ID:
 		*value = adreno_gpu->rev.patchid |
 	void *ptr;
 	ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
-		MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
+		MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
 	if (IS_ERR(ptr))
 		return ERR_CAST(ptr);
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 	int ret, i;
-	DBG("%s", gpu->name);
+	VERB("%s", gpu->name);
 	ret = adreno_load_fw(adreno_gpu);
 	if (ret)
 			adreno_gpu->info->revn, adreno_gpu->rev.core,
 			adreno_gpu->rev.major, adreno_gpu->rev.minor,
 			adreno_gpu->rev.patchid);
+	/*
+	 * If this is state collected due to iova fault, so fault related info
+	 *
+	 * TTBR0 would not be zero, so this is a good way to distinguish
+	 */
+	if (state->fault_info.ttbr0) {
+		const struct msm_gpu_fault_info *info = &state->fault_info;
+		drm_puts(p, "fault-info:\n");
+		drm_printf(p, "  - ttbr0=%.16llx\n", info->ttbr0);
+		drm_printf(p, "  - iova=%.16lx\n", info->iova);
+		drm_printf(p, "  - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
+		drm_printf(p, "  - type=%s\n", info->type);
+		drm_printf(p, "  - source=%s\n", info->block);
+	}
 	drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
 	if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
 		ret = adreno_get_legacy_pwrlevels(dev);
 	else {
-		ret = dev_pm_opp_of_add_table(dev);
+		ret = devm_pm_opp_of_add_table(dev);
 		if (ret)
 			DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
 	}
 	pm_runtime_disable(&priv->gpu_pdev->dev);
 	msm_gpu_cleanup(&adreno_gpu->base);
-	icc_put(gpu->icc_path);
-	icc_put(gpu->ocmem_icc_path);
 }

drivers/gpu/drm/msm/adreno/adreno_gpu.h+12−1

 	u32 value;
 };
-extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
+extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
 struct adreno_info {
 	struct adreno_rev rev;
        return gpu->revn == 650;
 }
+static inline int adreno_is_a660(struct adreno_gpu *gpu)
+{
+       return gpu->revn == 660;
+}
+/* check for a650, a660, or any derivatives */
+static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
+{
+       return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 660;
+}
 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
 		const char *fwname);

drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h+79−40

@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16	- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17	- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18	- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19	- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20	- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22	- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23	- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24		24
25	Copyright (C) 2013-2020 by the following authors:	25	Copyright (C) 2013-2021 by the following authors:
26	- Rob Clark <robdclark@gmail.com> (robclark)	26	- Rob Clark <robdclark@gmail.com> (robclark)
27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	27	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28		28
@@ -247,9 +247,9 @@ enum adreno_pm4_type3_packets { · 218 unmodified lines
247	CP_DRAW_INDX_INDIRECT = 41,	247	CP_DRAW_INDX_INDIRECT = 41,
248	CP_DRAW_INDIRECT_MULTI = 42,	248	CP_DRAW_INDIRECT_MULTI = 42,
249	CP_DRAW_AUTO = 36,	249	CP_DRAW_AUTO = 36,
250	CP_UNKNOWN_19 = 25,	250	CP_DRAW_PRED_ENABLE_GLOBAL = 25,
251	CP_UNKNOWN_1A = 26,	251	CP_DRAW_PRED_ENABLE_LOCAL = 26,
252	CP_UNKNOWN_4E = 78,	252	CP_DRAW_PRED_SET = 78,
253	CP_WIDE_REG_WRITE = 116,	253	CP_WIDE_REG_WRITE = 116,
254	CP_SCRATCH_TO_REG = 77,	254	CP_SCRATCH_TO_REG = 77,
255	CP_REG_TO_SCRATCH = 74,	255	CP_REG_TO_SCRATCH = 74,
@@ -267,6 +267,7 @@ enum adreno_pm4_type3_packets { · 11 unmodified lines
267	CP_SKIP_IB2_ENABLE_GLOBAL = 29,	267	CP_SKIP_IB2_ENABLE_GLOBAL = 29,
268	CP_SKIP_IB2_ENABLE_LOCAL = 35,	268	CP_SKIP_IB2_ENABLE_LOCAL = 35,
269	CP_SET_SUBDRAW_SIZE = 53,	269	CP_SET_SUBDRAW_SIZE = 53,
		270	CP_WHERE_AM_I = 98,
270	CP_SET_VISIBILITY_OVERRIDE = 100,	271	CP_SET_VISIBILITY_OVERRIDE = 100,
271	CP_PREEMPT_ENABLE_GLOBAL = 105,	272	CP_PREEMPT_ENABLE_GLOBAL = 105,
272	CP_PREEMPT_ENABLE_LOCAL = 106,	273	CP_PREEMPT_ENABLE_LOCAL = 106,
@@ -298,7 +299,6 @@ enum adreno_pm4_type3_packets { · 25 unmodified lines
298	CP_SET_BIN_DATA5_OFFSET = 46,	299	CP_SET_BIN_DATA5_OFFSET = 46,
299	CP_SET_CTXSWITCH_IB = 85,	300	CP_SET_CTXSWITCH_IB = 85,
300	CP_REG_WRITE = 109,	301	CP_REG_WRITE = 109,
301	CP_WHERE_AM_I = 98,
302	};	302	};
303		303
304	enum adreno_state_block {	304	enum adreno_state_block {
@@ -400,6 +400,17 @@ enum a6xx_patch_type { · 95 unmodified lines
400	enum a6xx_draw_indirect_opcode {	400	enum a6xx_draw_indirect_opcode {
401	INDIRECT_OP_NORMAL = 2,	401	INDIRECT_OP_NORMAL = 2,
402	INDIRECT_OP_INDEXED = 4,	402	INDIRECT_OP_INDEXED = 4,
		403	INDIRECT_OP_INDIRECT_COUNT = 6,
		404	INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
		405	};
		406
		407	enum cp_draw_pred_src {
		408	PRED_SRC_MEM = 5,
		409	};
		410
		411	enum cp_draw_pred_test {
		412	NE_0_PASS = 0,
		413	EQ_0_PASS = 1,
403	};	414	};
404		415
405	enum cp_cond_function {	416	enum cp_cond_function {
@@ -1040,33 +1051,61 @@ static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) · 634 unmodified lines
1040	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;	1051	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
1041	}	1052	}
1042		1053
1043	#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2 0x00000002	1054	#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
1044	#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK 0xffffffff
1045	#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT 0
1046	static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)
1047	{
1048	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK;
1049	}
1050		1055
1051	#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0 0x00000003
1052		1056
1053	#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5 0x00000005	1057	#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
1054	#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK 0xffffffff	1058
1055	#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT 0	1059	#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
1056	static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)	1060
1057	{	1061
1058	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK;	1062	#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003
1059	}	1063
		1064	#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005
		1065
		1066	#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006
1060		1067
1061	#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006	1068	#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008
1062		1069
1063	#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8 0x00000008	1070
1064	#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK 0xffffffff	1071	#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003
1065	#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT 0	1072
1066	static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)	1073	#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005
		1074
		1075	#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007
		1076
		1077
		1078	#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003
		1079
		1080	#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005
		1081
		1082	#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006
		1083
		1084	#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008
		1085
		1086	#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a
		1087
		1088	#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
		1089	#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
		1090
		1091	#define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000
		1092	#define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001
		1093
		1094	#define REG_CP_DRAW_PRED_SET_0 0x00000000
		1095	#define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0
		1096	#define CP_DRAW_PRED_SET_0_SRC__SHIFT 4
		1097	static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
1067	{	1098	{
1068	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK;	1099	return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
1069	}	1100	}
		1101	#define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100
		1102	#define CP_DRAW_PRED_SET_0_TEST__SHIFT 8
		1103	static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
		1104	{
		1105	return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
		1106	}
		1107
		1108	#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
1070		1109
1071	static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }	1110	static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1072		1111

drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c+42−188

@@ -22,165 +22,20 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx) · 21 unmodified lines
22	struct dpu_kms *dpu_kms = arg;	22	struct dpu_kms *dpu_kms = arg;
23	struct dpu_irq *irq_obj = &dpu_kms->irq_obj;	23	struct dpu_irq *irq_obj = &dpu_kms->irq_obj;
24	struct dpu_irq_callback *cb;	24	struct dpu_irq_callback *cb;
25	unsigned long irq_flags;
26		25
27	pr_debug("irq_idx=%d\n", irq_idx);	26	VERB("irq_idx=%d\n", irq_idx);
28		27
29	if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) {	28	if (list_empty(&irq_obj->irq_cb_tbl[irq_idx]))
30	DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx,	29	DRM_ERROR("no registered cb, idx:%d\n", irq_idx);
31	atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
32	}
33		30
34	atomic_inc(&irq_obj->irq_counts[irq_idx]);	31	atomic_inc(&irq_obj->irq_counts[irq_idx]);
35		32
36	/*	33	/*
37	* Perform registered function callback	34	* Perform registered function callback
38	*/	35	*/
39	spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
40	list_for_each_entry(cb, &irq_obj->irq_cb_tbl[irq_idx], list)	36	list_for_each_entry(cb, &irq_obj->irq_cb_tbl[irq_idx], list)
41	if (cb->func)	37	if (cb->func)
42	cb->func(cb->arg, irq_idx);	38	cb->func(cb->arg, irq_idx);
43	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
44
45	/*
46	* Clear pending interrupt status in HW.
47	* NOTE: dpu_core_irq_callback_handler is protected by top-level
48	* spinlock, so it is safe to clear any interrupt status here.
49	*/
50	dpu_kms->hw_intr->ops.clear_intr_status_nolock(
51	dpu_kms->hw_intr,
52	irq_idx);
53	}
54
55	int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
56	enum dpu_intr_type intr_type, u32 instance_idx)
57	{
58	if (!dpu_kms->hw_intr \|\| !dpu_kms->hw_intr->ops.irq_idx_lookup)
59	return -EINVAL;
60
61	return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr,
62	intr_type, instance_idx);
63	}
64
65	/**
66	* _dpu_core_irq_enable - enable core interrupt given by the index
67	* @dpu_kms: Pointer to dpu kms context
68	* @irq_idx: interrupt index
69	*/
70	static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
71	{
72	unsigned long irq_flags;
73	int ret = 0, enable_count;
74
75	if (!dpu_kms->hw_intr \|\|
76	!dpu_kms->irq_obj.enable_counts \|\|
77	!dpu_kms->irq_obj.irq_counts) {
78	DPU_ERROR("invalid params\n");
79	return -EINVAL;
80	}
81
82	if (irq_idx < 0 \|\| irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
83	DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
84	return -EINVAL;
85	}
86
87	enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
88	DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
89	trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
90
91	if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) {
92	ret = dpu_kms->hw_intr->ops.enable_irq(
93	dpu_kms->hw_intr,
94	irq_idx);
95	if (ret)
96	DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
97	irq_idx);
98
99	DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
100
101	spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
102	/* empty callback list but interrupt is enabled */
103	if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]))
104	DPU_ERROR("irq_idx=%d enabled with no callback\n",
105	irq_idx);
106	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
107	}
108
109	return ret;
110	}
111
112	int dpu_core_irq_enable(struct dpu_kms dpu_kms, int irq_idxs, u32 irq_count)
113	{
114	int i, ret = 0, counts;
115
116	if (!irq_idxs \|\| !irq_count) {
117	DPU_ERROR("invalid params\n");
118	return -EINVAL;
119	}
120
121	counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
122	if (counts)
123	DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
124
125	for (i = 0; (i < irq_count) && !ret; i++)
126	ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]);
127
128	return ret;
129	}
130
131	/**
132	* _dpu_core_irq_disable - disable core interrupt given by the index
133	* @dpu_kms: Pointer to dpu kms context
134	* @irq_idx: interrupt index
135	*/
136	static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
137	{
138	int ret = 0, enable_count;
139
140	if (!dpu_kms->hw_intr \|\| !dpu_kms->irq_obj.enable_counts) {
141	DPU_ERROR("invalid params\n");
142	return -EINVAL;
143	}
144
145	if (irq_idx < 0 \|\| irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
146	DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
147	return -EINVAL;
148	}
149
150	enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
151	DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
152	trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
153
154	if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) {
155	ret = dpu_kms->hw_intr->ops.disable_irq(
156	dpu_kms->hw_intr,
157	irq_idx);
158	if (ret)
159	DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
160	irq_idx);
161	DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
162	}
163
164	return ret;
165	}
166
167	int dpu_core_irq_disable(struct dpu_kms dpu_kms, int irq_idxs, u32 irq_count)
168	{
169	int i, ret = 0, counts;
170
171	if (!irq_idxs \|\| !irq_count) {
172	DPU_ERROR("invalid params\n");
173	return -EINVAL;
174	}
175
176	counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
177	if (counts == 2)
178	DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
179
180	for (i = 0; (i < irq_count) && !ret; i++)
181	ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]);
182
183	return ret;
184	}	39	}
185		40
186	u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear)	41	u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear)
@@ -217,19 +72,28 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx, · 30 unmodified lines
217	return -EINVAL;	72	return -EINVAL;
218	}	73	}
219		74
220	if (irq_idx < 0 \|\| irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {	75	if (irq_idx < 0 \|\| irq_idx >= dpu_kms->hw_intr->total_irqs) {
221	DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);	76	DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
222	return -EINVAL;	77	return -EINVAL;
223	}	78	}
224		79
225	DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);	80	VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
226		81
227	spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);	82	irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
228	trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb);	83	trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb);
229	list_del_init(&register_irq_cb->list);	84	list_del_init(&register_irq_cb->list);
230	list_add_tail(&register_irq_cb->list,	85	list_add_tail(&register_irq_cb->list,
231	&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]);	86	&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]);
232	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);	87	if (list_is_first(&register_irq_cb->list,
		88	&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
		89	int ret = dpu_kms->hw_intr->ops.enable_irq_locked(
		90	dpu_kms->hw_intr,
		91	irq_idx);
		92	if (ret)
		93	DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
		94	irq_idx);
		95	}
		96	dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
233		97
234	return 0;	98	return 0;
235	}	99	}
@@ -252,21 +116,27 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx, · 16 unmodified lines
252	return -EINVAL;	116	return -EINVAL;
253	}	117	}
254		118
255	if (irq_idx < 0 \|\| irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {	119	if (irq_idx < 0 \|\| irq_idx >= dpu_kms->hw_intr->total_irqs) {
256	DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);	120	DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
257	return -EINVAL;	121	return -EINVAL;
258	}	122	}
259		123
260	DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);	124	VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
261		125
262	spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);	126	irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
263	trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb);	127	trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb);
264	list_del_init(&register_irq_cb->list);	128	list_del_init(&register_irq_cb->list);
265	/* empty callback list but interrupt is still enabled */	129	/* empty callback list but interrupt is still enabled */
266	if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) &&	130	if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
267	atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]))	131	int ret = dpu_kms->hw_intr->ops.disable_irq_locked(
268	DPU_ERROR("irq_idx=%d enabled with no callback\n", irq_idx);	132	dpu_kms->hw_intr,
269	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);	133	irq_idx);
		134	if (ret)
		135	DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
		136	irq_idx);
		137	VERB("irq_idx=%d ret=%d\n", irq_idx, ret);
		138	}
		139	dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
270		140
271	return 0;	141	return 0;
272	}	142	}
@@ -290,26 +160,26 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms) · 17 unmodified lines
290	#ifdef CONFIG_DEBUG_FS	160	#ifdef CONFIG_DEBUG_FS
291	static int dpu_debugfs_core_irq_show(struct seq_file s, void v)	161	static int dpu_debugfs_core_irq_show(struct seq_file s, void v)
292	{	162	{
293	struct dpu_irq *irq_obj = s->private;	163	struct dpu_kms *dpu_kms = s->private;
		164	struct dpu_irq *irq_obj = &dpu_kms->irq_obj;
294	struct dpu_irq_callback *cb;	165	struct dpu_irq_callback *cb;
295	unsigned long irq_flags;	166	unsigned long irq_flags;
296	int i, irq_count, enable_count, cb_count;	167	int i, irq_count, cb_count;
297		168
298	if (WARN_ON(!irq_obj->enable_counts \|\| !irq_obj->irq_cb_tbl))	169	if (WARN_ON(!irq_obj->irq_cb_tbl))
299	return 0;	170	return 0;
300		171
301	for (i = 0; i < irq_obj->total_irqs; i++) {	172	for (i = 0; i < irq_obj->total_irqs; i++) {
302	spin_lock_irqsave(&irq_obj->cb_lock, irq_flags);	173	irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
303	cb_count = 0;	174	cb_count = 0;
304	irq_count = atomic_read(&irq_obj->irq_counts[i]);	175	irq_count = atomic_read(&irq_obj->irq_counts[i]);
305	enable_count = atomic_read(&irq_obj->enable_counts[i]);
306	list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list)	176	list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list)
307	cb_count++;	177	cb_count++;
308	spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags);	178	dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
309		179
310	if (irq_count \|\| enable_count \|\| cb_count)	180	if (irq_count \|\| cb_count)
311	seq_printf(s, "idx:%d irq:%d enable:%d cb:%d\n",	181	seq_printf(s, "idx:%d irq:%d cb:%d\n",
312	i, irq_count, enable_count, cb_count);	182	i, irq_count, cb_count);
313	}	183	}
314		184
315	return 0;	185	return 0;
@@ -320,7 +190,7 @@ DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_core_irq); · 4 unmodified lines
320	void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms,	190	void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms,
321	struct dentry *parent)	191	struct dentry *parent)
322	{	192	{
323	debugfs_create_file("core_irq", 0600, parent, &dpu_kms->irq_obj,	193	debugfs_create_file("core_irq", 0600, parent, dpu_kms,
324	&dpu_debugfs_core_irq_fops);	194	&dpu_debugfs_core_irq_fops);
325	}	195	}
326	#endif	196	#endif
@@ -334,19 +204,14 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms) · 7 unmodified lines
334	dpu_disable_all_irqs(dpu_kms);	204	dpu_disable_all_irqs(dpu_kms);
335	pm_runtime_put_sync(&dpu_kms->pdev->dev);	205	pm_runtime_put_sync(&dpu_kms->pdev->dev);
336		206
337	spin_lock_init(&dpu_kms->irq_obj.cb_lock);
338
339	/* Create irq callbacks for all possible irq_idx */	207	/* Create irq callbacks for all possible irq_idx */
340	dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;	208	dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
341	dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,	209	dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
342	sizeof(struct list_head), GFP_KERNEL);	210	sizeof(struct list_head), GFP_KERNEL);
343	dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
344	sizeof(atomic_t), GFP_KERNEL);
345	dpu_kms->irq_obj.irq_counts = kcalloc(dpu_kms->irq_obj.total_irqs,	211	dpu_kms->irq_obj.irq_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
346	sizeof(atomic_t), GFP_KERNEL);	212	sizeof(atomic_t), GFP_KERNEL);
347	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) {	213	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) {
348	INIT_LIST_HEAD(&dpu_kms->irq_obj.irq_cb_tbl[i]);	214	INIT_LIST_HEAD(&dpu_kms->irq_obj.irq_cb_tbl[i]);
349	atomic_set(&dpu_kms->irq_obj.enable_counts[i], 0);
350	atomic_set(&dpu_kms->irq_obj.irq_counts[i], 0);	215	atomic_set(&dpu_kms->irq_obj.irq_counts[i], 0);
351	}	216	}
352	}	217	}
@@ -357,8 +222,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) · 4 unmodified lines
357		222
358	pm_runtime_get_sync(&dpu_kms->pdev->dev);	223	pm_runtime_get_sync(&dpu_kms->pdev->dev);
359	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)	224	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
360	if (atomic_read(&dpu_kms->irq_obj.enable_counts[i]) \|\|	225	if (!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
361	!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
362	DPU_ERROR("irq_idx=%d still enabled/registered\n", i);	226	DPU_ERROR("irq_idx=%d still enabled/registered\n", i);
363		227
364	dpu_clear_all_irqs(dpu_kms);	228	dpu_clear_all_irqs(dpu_kms);
@@ -366,25 +230,14 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) · 1 unmodified line
366	pm_runtime_put_sync(&dpu_kms->pdev->dev);	230	pm_runtime_put_sync(&dpu_kms->pdev->dev);
367		231
368	kfree(dpu_kms->irq_obj.irq_cb_tbl);	232	kfree(dpu_kms->irq_obj.irq_cb_tbl);
369	kfree(dpu_kms->irq_obj.enable_counts);
370	kfree(dpu_kms->irq_obj.irq_counts);	233	kfree(dpu_kms->irq_obj.irq_counts);
371	dpu_kms->irq_obj.irq_cb_tbl = NULL;	234	dpu_kms->irq_obj.irq_cb_tbl = NULL;
372	dpu_kms->irq_obj.enable_counts = NULL;
373	dpu_kms->irq_obj.irq_counts = NULL;	235	dpu_kms->irq_obj.irq_counts = NULL;
374	dpu_kms->irq_obj.total_irqs = 0;	236	dpu_kms->irq_obj.total_irqs = 0;
375	}	237	}
376		238
377	irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)	239	irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
378	{	240	{
379	/*
380	* Read interrupt status from all sources. Interrupt status are
381	* stored within hw_intr.
382	* Function will also clear the interrupt status after reading.
383	* Individual interrupt status bit will only get stored if it
384	* is enabled.
385	*/
386	dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr);
387
388	/*	241	/*
389	* Dispatch to HW driver to handle interrupt lookup that is being	242	* Dispatch to HW driver to handle interrupt lookup that is being
390	* fired. When matching interrupt is located, HW driver will call to	243	* fired. When matching interrupt is located, HW driver will call to
@@ -392,6 +245,7 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) · 1 unmodified line
392	* dpu_core_irq_callback_handler will perform the registered function	245	* dpu_core_irq_callback_handler will perform the registered function
393	* callback, and do the interrupt status clearing once the registered	246	* callback, and do the interrupt status clearing once the registered
394	* callback is finished.	247	* callback is finished.
		248	* Function will also clear the interrupt status after reading.
395	*/	249	*/
396	dpu_kms->hw_intr->ops.dispatch_irqs(	250	dpu_kms->hw_intr->ops.dispatch_irqs(
397	dpu_kms->hw_intr,	251	dpu_kms->hw_intr,

drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h+0−43

@@ -29,49 +29,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms); · 28 unmodified lines
29	*/	29	*/
30	irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);	30	irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);
31		31
32	/**
33	* dpu_core_irq_idx_lookup - IRQ helper function for lookup irq_idx from HW
34	* interrupt mapping table.
35	* @dpu_kms: DPU handle
36	* @intr_type: DPU HW interrupt type for lookup
37	* @instance_idx: DPU HW block instance defined in dpu_hw_mdss.h
38	* @return: irq_idx or -EINVAL when fail to lookup
39	*/
40	int dpu_core_irq_idx_lookup(
41	struct dpu_kms *dpu_kms,
42	enum dpu_intr_type intr_type,
43	uint32_t instance_idx);
44
45	/**
46	* dpu_core_irq_enable - IRQ helper function for enabling one or more IRQs
47	* @dpu_kms: DPU handle
48	* @irq_idxs: Array of irq index
49	* @irq_count: Number of irq_idx provided in the array
50	* @return: 0 for success enabling IRQ, otherwise failure
51	*
52	* This function increments count on each enable and decrements on each
53	* disable. Interrupts is enabled if count is 0 before increment.
54	*/
55	int dpu_core_irq_enable(
56	struct dpu_kms *dpu_kms,
57	int *irq_idxs,
58	uint32_t irq_count);
59
60	/**
61	* dpu_core_irq_disable - IRQ helper function for disabling one of more IRQs
62	* @dpu_kms: DPU handle
63	* @irq_idxs: Array of irq index
64	* @irq_count: Number of irq_idx provided in the array
65	* @return: 0 for success disabling IRQ, otherwise failure
66	*
67	* This function increments count on each enable and decrements on each
68	* disable. Interrupts is disabled if count is 0 after decrement.
69	*/
70	int dpu_core_irq_disable(
71	struct dpu_kms *dpu_kms,
72	int *irq_idxs,
73	uint32_t irq_count);
74
75	/**	32	/**
76	* dpu_core_irq_read - IRQ helper function for reading IRQ status	33	* dpu_core_irq_read - IRQ helper function for reading IRQ status
77	* @dpu_kms: DPU handle	34	* @dpu_kms: DPU handle

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c+11−11

@@ -132,7 +132,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, · 131 unmodified lines
132	perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);	132	perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
133	}	133	}
134		134
135	DPU_DEBUG(	135	DRM_DEBUG_ATOMIC(
136	"crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",	136	"crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
137	crtc->base.id, perf->core_clk_rate,	137	crtc->base.id, perf->core_clk_rate,
138	perf->max_per_pipe_ib, perf->bw_ctl);	138	perf->max_per_pipe_ib, perf->bw_ctl);
@@ -178,7 +178,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, · 39 unmodified lines
178	struct dpu_crtc_state *tmp_cstate =	178	struct dpu_crtc_state *tmp_cstate =
179	to_dpu_crtc_state(tmp_crtc->state);	179	to_dpu_crtc_state(tmp_crtc->state);
180		180
181	DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",	181	DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n",
182	tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,	182	tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
183	tmp_cstate->bw_control);	183	tmp_cstate->bw_control);
184		184
@@ -187,11 +187,11 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, · 2 unmodified lines
187		187
188	/* convert bandwidth to kb */	188	/* convert bandwidth to kb */
189	bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);	189	bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
190	DPU_DEBUG("calculated bandwidth=%uk\n", bw);	190	DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw);
191		191
192	threshold = kms->catalog->perf.max_bw_high;	192	threshold = kms->catalog->perf.max_bw_high;
193		193
194	DPU_DEBUG("final threshold bw limit = %d\n", threshold);	194	DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold);
195		195
196	if (!threshold) {	196	if (!threshold) {
197	DPU_ERROR("no bandwidth limits specified\n");	197	DPU_ERROR("no bandwidth limits specified\n");
@@ -228,7 +228,7 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, · 30 unmodified lines
228		228
229	perf.bw_ctl += dpu_cstate->new_perf.bw_ctl;	229	perf.bw_ctl += dpu_cstate->new_perf.bw_ctl;
230		230
231	DPU_DEBUG("crtc=%d bw=%llu paths:%d\n",	231	DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n",
232	tmp_crtc->base.id,	232	tmp_crtc->base.id,
233	dpu_cstate->new_perf.bw_ctl, kms->num_paths);	233	dpu_cstate->new_perf.bw_ctl, kms->num_paths);
234	}	234	}
@@ -278,7 +278,7 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) · 43 unmodified lines
278	/* Release the bandwidth */	278	/* Release the bandwidth */
279	if (kms->perf.enable_bw_release) {	279	if (kms->perf.enable_bw_release) {
280	trace_dpu_cmd_release_bw(crtc->base.id);	280	trace_dpu_cmd_release_bw(crtc->base.id);
281	DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id);	281	DRM_DEBUG_ATOMIC("Release BW crtc=%d\n", crtc->base.id);
282	dpu_crtc->cur_perf.bw_ctl = 0;	282	dpu_crtc->cur_perf.bw_ctl = 0;
283	_dpu_core_perf_crtc_update_bus(kms, crtc);	283	_dpu_core_perf_crtc_update_bus(kms, crtc);
284	}	284	}
@@ -314,7 +314,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) · 29 unmodified lines
314	if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)	314	if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)
315	clk_rate = kms->perf.fix_core_clk_rate;	315	clk_rate = kms->perf.fix_core_clk_rate;
316		316
317	DPU_DEBUG("clk:%llu\n", clk_rate);	317	DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
318		318
319	return clk_rate;	319	return clk_rate;
320	}	320	}
@@ -344,7 +344,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, · 23 unmodified lines
344	dpu_crtc = to_dpu_crtc(crtc);	344	dpu_crtc = to_dpu_crtc(crtc);
345	dpu_cstate = to_dpu_crtc_state(crtc->state);	345	dpu_cstate = to_dpu_crtc_state(crtc->state);
346		346
347	DPU_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n",	347	DRM_DEBUG_ATOMIC("crtc:%d stop_req:%d core_clk:%llu\n",
348	crtc->base.id, stop_req, kms->perf.core_clk_rate);	348	crtc->base.id, stop_req, kms->perf.core_clk_rate);
349		349
350	old = &dpu_crtc->cur_perf;	350	old = &dpu_crtc->cur_perf;
@@ -362,7 +362,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, · 11 unmodified lines
362	(new->max_per_pipe_ib > old->max_per_pipe_ib))) \|\|	362	(new->max_per_pipe_ib > old->max_per_pipe_ib))) \|\|
363	(!params_changed && ((new->bw_ctl < old->bw_ctl) \|\|	363	(!params_changed && ((new->bw_ctl < old->bw_ctl) \|\|
364	(new->max_per_pipe_ib < old->max_per_pipe_ib)))) {	364	(new->max_per_pipe_ib < old->max_per_pipe_ib)))) {
365	DPU_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",	365	DRM_DEBUG_ATOMIC("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
366	crtc->base.id, params_changed,	366	crtc->base.id, params_changed,
367	new->bw_ctl, old->bw_ctl);	367	new->bw_ctl, old->bw_ctl);
368	old->bw_ctl = new->bw_ctl;	368	old->bw_ctl = new->bw_ctl;
@@ -378,7 +378,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, · 9 unmodified lines
378	update_clk = true;	378	update_clk = true;
379	}	379	}
380	} else {	380	} else {
381	DPU_DEBUG("crtc=%d disable\n", crtc->base.id);	381	DRM_DEBUG_ATOMIC("crtc=%d disable\n", crtc->base.id);
382	memset(old, 0, sizeof(*old));	382	memset(old, 0, sizeof(*old));
383	update_bus = true;	383	update_bus = true;
384	update_clk = true;	384	update_clk = true;
@@ -413,7 +413,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, · 28 unmodified lines
413	}	413	}
414		414
415	kms->perf.core_clk_rate = clk_rate;	415	kms->perf.core_clk_rate = clk_rate;
416	DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);	416	DRM_DEBUG_ATOMIC("update clk rate = %lld HZ\n", clk_rate);
417	}	417	}
418	return 0;	418	return 0;
419	}	419	}

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c+20−23

@@ -57,8 +57,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc) · 56 unmodified lines
57	{	57	{
58	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);	58	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
59		59
60	DPU_DEBUG("\n");
61
62	if (!crtc)	60	if (!crtc)
63	return;	61	return;
64		62
@@ -163,7 +161,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, · 98 unmodified lines
163	lm->ops.setup_blend_config(lm, pstate->stage,	161	lm->ops.setup_blend_config(lm, pstate->stage,
164	0xFF, 0, blend_op);	162	0xFF, 0, blend_op);
165		163
166	DPU_DEBUG("format:%p4cc, alpha_en:%u blend_op:0x%x\n",	164	DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
167	&format->base.pixel_format, format->alpha_enable, blend_op);	165	&format->base.pixel_format, format->alpha_enable, blend_op);
168	}	166	}
169		167
@@ -220,7 +218,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, · 50 unmodified lines
220		218
221	dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);	219	dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
222	set_bit(dpu_plane_pipe(plane), fetch_active);	220	set_bit(dpu_plane_pipe(plane), fetch_active);
223	DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",	221
		222	DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
224	crtc->base.id,	223	crtc->base.id,
225	pstate->stage,	224	pstate->stage,
226	plane->base.id,	225	plane->base.id,
@@ -278,7 +277,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) · 51 unmodified lines
278	struct dpu_hw_mixer *lm;	277	struct dpu_hw_mixer *lm;
279	int i;	278	int i;
280		279
281	DPU_DEBUG("%s\n", dpu_crtc->name);	280	DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
282		281
283	for (i = 0; i < cstate->num_mixers; i++) {	282	for (i = 0; i < cstate->num_mixers; i++) {
284	mixer[i].mixer_op_mode = 0;	283	mixer[i].mixer_op_mode = 0;
@@ -305,7 +304,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) · 20 unmodified lines
305	/* stage config flush mask */	304	/* stage config flush mask */
306	ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);	305	ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
307		306
308	DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",	307	DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
309	mixer[i].hw_lm->idx - LM_0,	308	mixer[i].hw_lm->idx - LM_0,
310	mixer[i].mixer_op_mode,	309	mixer[i].mixer_op_mode,
311	ctl->idx - CTL_0,	310	ctl->idx - CTL_0,
@@ -388,7 +387,7 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) · 76 unmodified lines
388		387
389	DPU_ATRACE_BEGIN("crtc_frame_event");	388	DPU_ATRACE_BEGIN("crtc_frame_event");
390		389
391	DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,	390	DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
392	ktime_to_ns(fevent->ts));	391	ktime_to_ns(fevent->ts));
393		392
394	if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE	393	if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
@@ -407,9 +406,6 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) · 12 unmodified lines
407	fevent->event);	406	fevent->event);
408	}	407	}
409		408
410	if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE)
411	dpu_core_perf_crtc_update(crtc, 0, false);
412
413	if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE	409	if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
414	\| DPU_ENCODER_FRAME_EVENT_ERROR))	410	\| DPU_ENCODER_FRAME_EVENT_ERROR))
415	frame_done = true;	411	frame_done = true;
@@ -477,6 +473,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event) · 61 unmodified lines
477	void dpu_crtc_complete_commit(struct drm_crtc *crtc)	473	void dpu_crtc_complete_commit(struct drm_crtc *crtc)
478	{	474	{
479	trace_dpu_crtc_complete_commit(DRMID(crtc));	475	trace_dpu_crtc_complete_commit(DRMID(crtc));
		476	dpu_core_perf_crtc_update(crtc, 0, false);
480	_dpu_crtc_complete_flip(crtc);	477	_dpu_crtc_complete_flip(crtc);
481	}	478	}
482		479
@@ -558,7 +555,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) · 75 unmodified lines
558	/* stage config flush mask */	555	/* stage config flush mask */
559	ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);	556	ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
560		557
561	DPU_DEBUG("lm %d, ctl %d, flush mask 0x%x\n",	558	DRM_DEBUG_ATOMIC("lm %d, ctl %d, flush mask 0x%x\n",
562	mixer[i].hw_lm->idx - DSPP_0,	559	mixer[i].hw_lm->idx - DSPP_0,
563	ctl->idx - CTL_0,	560	ctl->idx - CTL_0,
564	mixer[i].flush_mask);	561	mixer[i].flush_mask);
@@ -572,12 +569,12 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, · 7 unmodified lines
572	struct drm_encoder *encoder;	569	struct drm_encoder *encoder;
573		570
574	if (!crtc->state->enable) {	571	if (!crtc->state->enable) {
575	DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",	572	DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n",
576	crtc->base.id, crtc->state->enable);	573	crtc->base.id, crtc->state->enable);
577	return;	574	return;
578	}	575	}
579		576
580	DPU_DEBUG("crtc%d\n", crtc->base.id);	577	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
581		578
582	_dpu_crtc_setup_lm_bounds(crtc, crtc->state);	579	_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
583		580
@@ -617,12 +614,12 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, · 33 unmodified lines
617	struct dpu_crtc_state *cstate;	614	struct dpu_crtc_state *cstate;
618		615
619	if (!crtc->state->enable) {	616	if (!crtc->state->enable) {
620	DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",	617	DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n",
621	crtc->base.id, crtc->state->enable);	618	crtc->base.id, crtc->state->enable);
622	return;	619	return;
623	}	620	}
624		621
625	DPU_DEBUG("crtc%d\n", crtc->base.id);	622	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
626		623
627	dpu_crtc = to_dpu_crtc(crtc);	624	dpu_crtc = to_dpu_crtc(crtc);
628	cstate = to_dpu_crtc_state(crtc->state);	625	cstate = to_dpu_crtc_state(crtc->state);
@@ -675,7 +672,7 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc, · 46 unmodified lines
675	{	672	{
676	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);	673	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
677		674
678	DPU_DEBUG("crtc%d\n", crtc->base.id);	675	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
679		676
680	__drm_atomic_helper_crtc_destroy_state(state);	677	__drm_atomic_helper_crtc_destroy_state(state);
681		678
@@ -688,7 +685,7 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) · 6 unmodified lines
688	int ret, rc = 0;	685	int ret, rc = 0;
689		686
690	if (!atomic_read(&dpu_crtc->frame_pending)) {	687	if (!atomic_read(&dpu_crtc->frame_pending)) {
691	DPU_DEBUG("no frames pending\n");	688	DRM_DEBUG_ATOMIC("no frames pending\n");
692	return 0;	689	return 0;
693	}	690	}
694		691
@@ -731,9 +728,9 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) · 36 unmodified lines
731		728
732	if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {	729	if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
733	/* acquire bandwidth and other resources */	730	/* acquire bandwidth and other resources */
734	DPU_DEBUG("crtc%d first commit\n", crtc->base.id);	731	DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id);
735	} else	732	} else
736	DPU_DEBUG("crtc%d commit\n", crtc->base.id);	733	DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id);
737		734
738	dpu_crtc->play_count++;	735	dpu_crtc->play_count++;
739		736
@@ -908,7 +905,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, · 168 unmodified lines
908	pstates = kzalloc(sizeof(pstates) DPU_STAGE_MAX * 4, GFP_KERNEL);	905	pstates = kzalloc(sizeof(pstates) DPU_STAGE_MAX * 4, GFP_KERNEL);
909		906
910	if (!crtc_state->enable \|\| !crtc_state->active) {	907	if (!crtc_state->enable \|\| !crtc_state->active) {
911	DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",	908	DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
912	crtc->base.id, crtc_state->enable,	909	crtc->base.id, crtc_state->enable,
913	crtc_state->active);	910	crtc_state->active);
914	memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));	911	memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
@@ -916,7 +913,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, · 1 unmodified line
916	}	913	}
917		914
918	mode = &crtc_state->adjusted_mode;	915	mode = &crtc_state->adjusted_mode;
919	DPU_DEBUG("%s: check\n", dpu_crtc->name);	916	DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
920		917
921	/* force a full mode set if active state changed */	918	/* force a full mode set if active state changed */
922	if (crtc_state->active_changed)	919	if (crtc_state->active_changed)
@@ -1024,7 +1021,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, · 101 unmodified lines
1024	}	1021	}
1025		1022
1026	pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;	1023	pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
1027	DPU_DEBUG("%s: zpos %d\n", dpu_crtc->name, z_pos);	1024	DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
1028	}	1025	}
1029		1026
1030	for (i = 0; i < multirect_count; i++) {	1027	for (i = 0; i < multirect_count; i++) {
@@ -1376,6 +1373,6 @@ struct drm_crtc dpu_crtc_init(struct drm_device dev, struct drm_plane *plane, · 345 unmodified lines
1376	/* initialize event handling */	1373	/* initialize event handling */
1377	spin_lock_init(&dpu_crtc->event_lock);	1374	spin_lock_init(&dpu_crtc->event_lock);
1378		1375
1379	DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);	1376	DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
1380	return crtc;	1377	return crtc;
1381	}	1378	}

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c+39−71

 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  */
 #include "dpu_crtc.h"
 #include "dpu_trace.h"
 #include "dpu_core_irq.h"
+#include "disp/msm_disp_snapshot.h"
-#define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
+#define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
 		(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
 		(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
-#define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
+#define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\
 		(p) ? (p)->parent->base.id : -1, \
 		(p) ? (p)->intf_idx - INTF_0 : -1, \
 		(p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
 }
 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
-		int32_t hw_id, struct dpu_encoder_wait_info *info);
+		u32 irq_idx, struct dpu_encoder_wait_info *info);
 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 		enum dpu_intr_idx intr_idx,
 	/* return EWOULDBLOCK since we know the wait isn't necessary */
 	if (phys_enc->enable_state == DPU_ENC_DISABLED) {
-		DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
+		DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+			  DRMID(phys_enc->parent), intr_idx,
 			  irq->irq_idx);
 		return -EWOULDBLOCK;
 	}
 	if (irq->irq_idx < 0) {
-		DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
+		DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s",
-			      DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+			      DRMID(phys_enc->parent), intr_idx,
 			      irq->name);
 		return 0;
 	}
-	DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
+	DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d",
-		      DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+		      DRMID(phys_enc->parent), intr_idx,
 		      irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
 		      atomic_read(wait_info->atomic_cnt));
 	ret = dpu_encoder_helper_wait_event_timeout(
 			DRMID(phys_enc->parent),
-			irq->hw_idx,
+			irq->irq_idx,
 			wait_info);
 	if (ret <= 0) {
 			unsigned long flags;
 			DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
-				      "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+				      "irq=%d, pp=%d, atomic_cnt=%d",
 				      DRMID(phys_enc->parent), intr_idx,
-				      irq->hw_idx, irq->irq_idx,
+				      irq->irq_idx,
 				      phys_enc->hw_pp->idx - PINGPONG_0,
 				      atomic_read(wait_info->atomic_cnt));
 			local_irq_save(flags);
 		} else {
 			ret = -ETIMEDOUT;
 			DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
-				      "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+				      "irq=%d, pp=%d, atomic_cnt=%d",
 				      DRMID(phys_enc->parent), intr_idx,
-				      irq->hw_idx, irq->irq_idx,
+				      irq->irq_idx,
 				      phys_enc->hw_pp->idx - PINGPONG_0,
 				      atomic_read(wait_info->atomic_cnt));
 		}
 	} else {
 		ret = 0;
 		trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
-			intr_idx, irq->hw_idx, irq->irq_idx,
+			intr_idx, irq->irq_idx,
 			phys_enc->hw_pp->idx - PINGPONG_0,
 			atomic_read(wait_info->atomic_cnt));
 	}
 	}
 	irq = &phys_enc->irq[intr_idx];
-	if (irq->irq_idx >= 0) {
-		DPU_DEBUG_PHYS(phys_enc,
-				"skipping already registered irq %s type %d\n",
-				irq->name, irq->intr_type);
-		return 0;
-	}
-	irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
-			irq->intr_type, irq->hw_idx);
 	if (irq->irq_idx < 0) {
 		DPU_ERROR_PHYS(phys_enc,
-			"failed to lookup IRQ index for %s type:%d\n",
+			"invalid IRQ index:%d\n", irq->irq_idx);
-			irq->name, irq->intr_type);
 		return -EINVAL;
 	}
 		return ret;
 	}
-	ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
-	if (ret) {
-		DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
-			  irq->irq_idx);
-		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
-				irq->irq_idx, &irq->cb);
-		irq->irq_idx = -EINVAL;
-		return ret;
-	}
 	trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
-				irq->hw_idx, irq->irq_idx);
+				irq->irq_idx);
 	return ret;
 }
 	/* silently skip irqs that weren't registered */
 	if (irq->irq_idx < 0) {
-		DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
+		DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+			  DRMID(phys_enc->parent), intr_idx,
 			  irq->irq_idx);
 		return 0;
 	}
-	ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
-	if (ret) {
-		DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
-			  irq->irq_idx, ret);
-	}
 	ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 			&irq->cb);
 	if (ret) {
-		DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
+		DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+			  DRMID(phys_enc->parent), intr_idx,
 			  irq->irq_idx, ret);
 	}
 	trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
-					     irq->hw_idx, irq->irq_idx);
+					     irq->irq_idx);
-	irq->irq_idx = -EINVAL;
 	return 0;
 }
 		/* return if the resource control is already in ON state */
 		if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
-			DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
+			DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
 				      DRMID(drm_enc), sw_event);
 			mutex_unlock(&dpu_enc->rc_lock);
 			return 0;
 		} else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
 				dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
-			DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
+			DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
 				      DRMID(drm_enc), sw_event,
 				      dpu_enc->rc_state);
 			mutex_unlock(&dpu_enc->rc_lock);
 	DPU_ATRACE_BEGIN("encoder_underrun_callback");
 	atomic_inc(&phy_enc->underrun_cnt);
+	/* trigger dump only on the first underrun */
+	if (atomic_read(&phy_enc->underrun_cnt) == 1)
+		msm_disp_snapshot_state(drm_enc->dev);
 	trace_dpu_enc_underrun_cb(DRMID(drm_enc),
 				  atomic_read(&phy_enc->underrun_cnt));
 	DPU_ATRACE_END("encoder_underrun_callback");
 	struct dpu_encoder_virt *dpu_enc = container_of(work,
 			struct dpu_encoder_virt, delayed_off_work.work);
-	if (!dpu_enc) {
-		DPU_ERROR("invalid dpu encoder\n");
-		return;
-	}
 	dpu_encoder_resource_control(&dpu_enc->base,
 						DPU_ENC_RC_EVENT_ENTER_IDLE);
 static int dpu_encoder_helper_wait_event_timeout(
 		int32_t drm_id,
-		int32_t hw_id,
+		u32 irq_idx,
 		struct dpu_encoder_wait_info *info)
 {
 	int rc = 0;
 				atomic_read(info->atomic_cnt) == 0, jiffies);
 		time = ktime_to_ms(ktime_get());
-		trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
+		trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
 						 expected_time,
 						 atomic_read(info->atomic_cnt));
 	/* If we timed out, counter is valid and time is less, wait again */
 	struct dpu_encoder_virt *dpu_enc;
 	struct dpu_hw_ctl *ctl;
 	int rc;
+	struct drm_encoder *drm_enc;
 	dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
 	ctl = phys_enc->hw_ctl;
+	drm_enc = phys_enc->parent;
 	if (!ctl->ops.reset)
 		return;
-	DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
+	DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
 		      ctl->idx);
 	rc = ctl->ops.reset(ctl);
-	if (rc)
+	if (rc) {
 		DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
+		msm_disp_snapshot_state(drm_enc->dev);
+	}
 	phys_enc->enable_state = DPU_ENC_ENABLED;
 }
 			struct dpu_encoder_virt, vsync_event_work);
 	ktime_t wakeup_time;
-	if (!dpu_enc) {
-		DPU_ERROR("invalid dpu encoder\n");
-		return;
-	}
 	if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
 		return;
 	phys_params.parent_ops = &dpu_encoder_parent_ops;
 	phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
-	DPU_DEBUG("\n");
 	switch (disp_info->intf_type) {
 	case DRM_MODE_ENCODER_DSI:
 		intf_type = INTF_DSI;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h+0−4

 /**
  * dpu_encoder_irq - tracking structure for interrupts
  * @name:		string name of interrupt
- * @intr_type:		Encoder interrupt type
  * @intr_idx:		Encoder interrupt enumeration
- * @hw_idx:		HW Block ID
  * @irq_idx:		IRQ interface lookup index from DPU IRQ framework
  *			will be -EINVAL if IRQ is not registered
  * @irq_cb:		interrupt callback
  */
 struct dpu_encoder_irq {
 	const char *name;
-	enum dpu_intr_type intr_type;
 	enum dpu_intr_idx intr_idx;
-	int hw_idx;
 	int irq_idx;
 	struct dpu_irq_callback cb;
 };

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c+21−37

@@ -1,6 +1,6 @@
1	// SPDX-License-Identifier: GPL-2.0-only	1	// SPDX-License-Identifier: GPL-2.0-only
2	/*	2	/*
3	* Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.	3	* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
4	*/	4	*/
5		5
6	#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__	6	#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@@ -11,6 +11,7 @@ · 4 unmodified lines
11	#include "dpu_core_irq.h"	11	#include "dpu_core_irq.h"
12	#include "dpu_formats.h"	12	#include "dpu_formats.h"
13	#include "dpu_trace.h"	13	#include "dpu_trace.h"
		14	#include "disp/msm_disp_snapshot.h"
14		15
15	#define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \	16	#define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
16	(e) && (e)->base.parent ? \	17	(e) && (e)->base.parent ? \
@@ -143,28 +144,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx) · 126 unmodified lines
143	phys_enc);	144	phys_enc);
144	}	145	}
145		146
146	static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
147	struct dpu_encoder_phys *phys_enc)
148	{
149	struct dpu_encoder_irq *irq;
150
151	irq = &phys_enc->irq[INTR_IDX_CTL_START];
152	irq->hw_idx = phys_enc->hw_ctl->idx;
153	irq->irq_idx = -EINVAL;
154
155	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
156	irq->hw_idx = phys_enc->hw_pp->idx;
157	irq->irq_idx = -EINVAL;
158
159	irq = &phys_enc->irq[INTR_IDX_RDPTR];
160	irq->hw_idx = phys_enc->hw_pp->idx;
161	irq->irq_idx = -EINVAL;
162
163	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
164	irq->hw_idx = phys_enc->intf_idx;
165	irq->irq_idx = -EINVAL;
166	}
167
168	static void dpu_encoder_phys_cmd_mode_set(	147	static void dpu_encoder_phys_cmd_mode_set(
169	struct dpu_encoder_phys *phys_enc,	148	struct dpu_encoder_phys *phys_enc,
170	struct drm_display_mode *mode,	149	struct drm_display_mode *mode,
@@ -172,6 +151,7 @@ static void dpu_encoder_phys_cmd_mode_set( · 1 unmodified line
172	{	151	{
173	struct dpu_encoder_phys_cmd *cmd_enc =	152	struct dpu_encoder_phys_cmd *cmd_enc =
174	to_dpu_encoder_phys_cmd(phys_enc);	153	to_dpu_encoder_phys_cmd(phys_enc);
		154	struct dpu_encoder_irq *irq;
175		155
176	if (!mode \|\| !adj_mode) {	156	if (!mode \|\| !adj_mode) {
177	DPU_ERROR("invalid args\n");	157	DPU_ERROR("invalid args\n");
@@ -181,7 +161,17 @@ static void dpu_encoder_phys_cmd_mode_set( · 3 unmodified lines
181	DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");	161	DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
182	drm_mode_debug_printmodeline(adj_mode);	162	drm_mode_debug_printmodeline(adj_mode);
183		163
184	_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);	164	irq = &phys_enc->irq[INTR_IDX_CTL_START];
		165	irq->irq_idx = phys_enc->hw_ctl->caps->intr_start;
		166
		167	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
		168	irq->irq_idx = phys_enc->hw_pp->caps->intr_done;
		169
		170	irq = &phys_enc->irq[INTR_IDX_RDPTR];
		171	irq->irq_idx = phys_enc->hw_pp->caps->intr_rdptr;
		172
		173	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
		174	irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
185	}	175	}
186		176
187	static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(	177	static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
@@ -191,10 +181,13 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( · 3 unmodified lines
191	to_dpu_encoder_phys_cmd(phys_enc);	181	to_dpu_encoder_phys_cmd(phys_enc);
192	u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;	182	u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
193	bool do_log = false;	183	bool do_log = false;
		184	struct drm_encoder *drm_enc;
194		185
195	if (!phys_enc->hw_pp)	186	if (!phys_enc->hw_pp)
196	return -EINVAL;	187	return -EINVAL;
197		188
		189	drm_enc = phys_enc->parent;
		190
198	cmd_enc->pp_timeout_report_cnt++;	191	cmd_enc->pp_timeout_report_cnt++;
199	if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) {	192	if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) {
200	frame_event \|= DPU_ENCODER_FRAME_EVENT_PANEL_DEAD;	193	frame_event \|= DPU_ENCODER_FRAME_EVENT_PANEL_DEAD;
@@ -203,7 +196,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( · 2 unmodified lines
203	do_log = true;	196	do_log = true;
204	}	197	}
205		198
206	trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent),	199	trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(drm_enc),
207	phys_enc->hw_pp->idx - PINGPONG_0,	200	phys_enc->hw_pp->idx - PINGPONG_0,
208	cmd_enc->pp_timeout_report_cnt,	201	cmd_enc->pp_timeout_report_cnt,
209	atomic_read(&phys_enc->pending_kickoff_cnt),	202	atomic_read(&phys_enc->pending_kickoff_cnt),
@@ -212,12 +205,12 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( · 2 unmodified lines
212	/* to avoid flooding, only log first time, and "dead" time */	205	/* to avoid flooding, only log first time, and "dead" time */
213	if (do_log) {	206	if (do_log) {
214	DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",	207	DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",
215	DRMID(phys_enc->parent),	208	DRMID(drm_enc),
216	phys_enc->hw_pp->idx - PINGPONG_0,	209	phys_enc->hw_pp->idx - PINGPONG_0,
217	phys_enc->hw_ctl->idx - CTL_0,	210	phys_enc->hw_ctl->idx - CTL_0,
218	cmd_enc->pp_timeout_report_cnt,	211	cmd_enc->pp_timeout_report_cnt,
219	atomic_read(&phys_enc->pending_kickoff_cnt));	212	atomic_read(&phys_enc->pending_kickoff_cnt));
220		213	msm_disp_snapshot_state(drm_enc->dev);
221	dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);	214	dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
222	}	215	}
223		216
@@ -228,7 +221,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( · 4 unmodified lines
228		221
229	if (phys_enc->parent_ops->handle_frame_done)	222	if (phys_enc->parent_ops->handle_frame_done)
230	phys_enc->parent_ops->handle_frame_done(	223	phys_enc->parent_ops->handle_frame_done(
231	phys_enc->parent, phys_enc, frame_event);	224	drm_enc, phys_enc, frame_event);
232		225
233	return -ETIMEDOUT;	226	return -ETIMEDOUT;
234	}	227	}
@@ -685,10 +678,6 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete( · 450 unmodified lines
685	static int dpu_encoder_phys_cmd_wait_for_commit_done(	678	static int dpu_encoder_phys_cmd_wait_for_commit_done(
686	struct dpu_encoder_phys *phys_enc)	679	struct dpu_encoder_phys *phys_enc)
687	{	680	{
688	struct dpu_encoder_phys_cmd *cmd_enc;
689
690	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
691
692	/* only required for master controller */	681	/* only required for master controller */
693	if (!dpu_encoder_phys_cmd_is_master(phys_enc))	682	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
694	return 0;	683	return 0;
@@ -795,31 +784,26 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( · 100 unmodified lines
795	irq = &phys_enc->irq[i];	784	irq = &phys_enc->irq[i];
796	INIT_LIST_HEAD(&irq->cb.list);	785	INIT_LIST_HEAD(&irq->cb.list);
797	irq->irq_idx = -EINVAL;	786	irq->irq_idx = -EINVAL;
798	irq->hw_idx = -EINVAL;
799	irq->cb.arg = phys_enc;	787	irq->cb.arg = phys_enc;
800	}	788	}
801		789
802	irq = &phys_enc->irq[INTR_IDX_CTL_START];	790	irq = &phys_enc->irq[INTR_IDX_CTL_START];
803	irq->name = "ctl_start";	791	irq->name = "ctl_start";
804	irq->intr_type = DPU_IRQ_TYPE_CTL_START;
805	irq->intr_idx = INTR_IDX_CTL_START;	792	irq->intr_idx = INTR_IDX_CTL_START;
806	irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq;	793	irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq;
807		794
808	irq = &phys_enc->irq[INTR_IDX_PINGPONG];	795	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
809	irq->name = "pp_done";	796	irq->name = "pp_done";
810	irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP;
811	irq->intr_idx = INTR_IDX_PINGPONG;	797	irq->intr_idx = INTR_IDX_PINGPONG;
812	irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq;	798	irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq;
813		799
814	irq = &phys_enc->irq[INTR_IDX_RDPTR];	800	irq = &phys_enc->irq[INTR_IDX_RDPTR];
815	irq->name = "pp_rd_ptr";	801	irq->name = "pp_rd_ptr";
816	irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR;
817	irq->intr_idx = INTR_IDX_RDPTR;	802	irq->intr_idx = INTR_IDX_RDPTR;
818	irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq;	803	irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq;
819		804
820	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];	805	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
821	irq->name = "underrun";	806	irq->name = "underrun";
822	irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
823	irq->intr_idx = INTR_IDX_UNDERRUN;	807	irq->intr_idx = INTR_IDX_UNDERRUN;
824	irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;	808	irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;
825		809

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c+20−34

 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
  */
 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
 #include "dpu_core_irq.h"
 #include "dpu_formats.h"
 #include "dpu_trace.h"
+#include "disp/msm_disp_snapshot.h"
 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
 		(e) && (e)->parent ? \
 	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
 	if (phys_enc->hw_pp->merge_3d)
-		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
+		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
 	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 	phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
 				true,
 				phys_enc->hw_pp->idx);
-	if (phys_enc->hw_pp->merge_3d) {
+	if (phys_enc->hw_pp->merge_3d)
-		struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d);
+		phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
-		merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d);
-	}
 	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 	return phys_enc->split_role != ENC_ROLE_SOLO;
 }
-static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_irq *irq;
-	/*
-	 * Initialize irq->hw_idx only when irq is not registered.
-	 * Prevent invalidating irq->irq_idx as modeset may be
-	 * called many times during dfps.
-	 */
-	irq = &phys_enc->irq[INTR_IDX_VSYNC];
-	if (irq->irq_idx < 0)
-		irq->hw_idx = phys_enc->intf_idx;
-	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
-	if (irq->irq_idx < 0)
-		irq->hw_idx = phys_enc->intf_idx;
-}
 static void dpu_encoder_phys_vid_mode_set(
 		struct dpu_encoder_phys *phys_enc,
 		struct drm_display_mode *mode,
 		struct drm_display_mode *adj_mode)
 {
+	struct dpu_encoder_irq *irq;
 	if (adj_mode) {
 		phys_enc->cached_mode = *adj_mode;
 		drm_mode_debug_printmodeline(adj_mode);
 		DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
 	}
-	_dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
+	irq = &phys_enc->irq[INTR_IDX_VSYNC];
+	irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync;
+	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
+	irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
 }
 static int dpu_encoder_phys_vid_control_vblank_irq(
 		goto end;
 	}
-	DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
+	DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
 		      atomic_read(&phys_enc->vblank_refcount));
 	if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
 	ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
 	if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
-		ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id);
+		ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
 skip_flush:
 	DPU_DEBUG_VIDENC(phys_enc,
 		"update pending flush ctl %d intf %d\n",
 		ctl->idx - CTL_0, phys_enc->hw_intf->idx);
+	atomic_set(&phys_enc->underrun_cnt, 0);
 	/* ctl_flush & timing engine enable will be triggered by framework */
 	if (phys_enc->enable_state == DPU_ENC_DISABLED)
 {
 	struct dpu_hw_ctl *ctl;
 	int rc;
+	struct drm_encoder *drm_enc;
+	drm_enc = phys_enc->parent;
 	ctl = phys_enc->hw_ctl;
 	if (!ctl->ops.wait_reset_status)
 	if (rc) {
 		DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
 				ctl->idx, rc);
+		msm_disp_snapshot_state(drm_enc->dev);
 		dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
 	}
 }
 	if (enable) {
 		ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
-		if (ret)
+		if (WARN_ON(ret))
 			return;
 		dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
 		irq = &phys_enc->irq[i];
 		INIT_LIST_HEAD(&irq->cb.list);
 		irq->irq_idx = -EINVAL;
-		irq->hw_idx = -EINVAL;
 		irq->cb.arg = phys_enc;
 	}
 	irq = &phys_enc->irq[INTR_IDX_VSYNC];
 	irq->name = "vsync_irq";
-	irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
 	irq->intr_idx = INTR_IDX_VSYNC;
 	irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
 	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
 	irq->name = "underrun";
-	irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
 	irq->intr_idx = INTR_IDX_UNDERRUN;
 	irq->cb.func = dpu_encoder_phys_vid_underrun_irq;

drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c+3−3

@@ -992,7 +992,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( · 991 unmodified lines
992	* Currently only support exactly zero or one modifier.	992	* Currently only support exactly zero or one modifier.
993	* All planes use the same modifier.	993	* All planes use the same modifier.
994	*/	994	*/
995	DPU_DEBUG("plane format modifier 0x%llX\n", modifier);	995	DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier);
996		996
997	switch (modifier) {	997	switch (modifier) {
998	case 0:	998	case 0:
@@ -1002,7 +1002,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( · 3 unmodified lines
1002	case DRM_FORMAT_MOD_QCOM_COMPRESSED:	1002	case DRM_FORMAT_MOD_QCOM_COMPRESSED:
1003	map = dpu_format_map_ubwc;	1003	map = dpu_format_map_ubwc;
1004	map_size = ARRAY_SIZE(dpu_format_map_ubwc);	1004	map_size = ARRAY_SIZE(dpu_format_map_ubwc);
1005	DPU_DEBUG("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",	1005	DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
1006	(char *)&format);	1006	(char *)&format);
1007	break;	1007	break;
1008	default:	1008	default:
@@ -1021,7 +1021,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( · 12 unmodified lines
1021	DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",	1021	DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
1022	(char *)&format, modifier);	1022	(char *)&format, modifier);
1023	else	1023	else
1024	DPU_DEBUG("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",	1024	DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
1025	(char *)&format, modifier,	1025	(char *)&format, modifier,
1026	DPU_FORMAT_IS_UBWC(fmt),	1026	DPU_FORMAT_IS_UBWC(fmt),
1027	DPU_FORMAT_IS_YUV(fmt));	1027	DPU_FORMAT_IS_YUV(fmt));

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c+0−139

@@ -1,139 +0,0 @@
1	// SPDX-License-Identifier: GPL-2.0-only
2	/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3	*/
4
5	#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6
7	#include <linux/mutex.h>
8	#include <linux/errno.h>
9	#include <linux/slab.h>
10
11	#include "dpu_hw_mdss.h"
12	#include "dpu_hw_blk.h"
13
14	/* Serialization lock for dpu_hw_blk_list */
15	static DEFINE_MUTEX(dpu_hw_blk_lock);
16
17	/* List of all hw block objects */
18	static LIST_HEAD(dpu_hw_blk_list);
19
20	/**
21	* dpu_hw_blk_init - initialize hw block object
22	* @hw_blk: pointer to hw block object
23	* @type: hw block type - enum dpu_hw_blk_type
24	* @id: instance id of the hw block
25	* @ops: Pointer to block operations
26	*/
27	void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id,
28	struct dpu_hw_blk_ops *ops)
29	{
30	INIT_LIST_HEAD(&hw_blk->list);
31	hw_blk->type = type;
32	hw_blk->id = id;
33	atomic_set(&hw_blk->refcount, 0);
34
35	if (ops)
36	hw_blk->ops = *ops;
37
38	mutex_lock(&dpu_hw_blk_lock);
39	list_add(&hw_blk->list, &dpu_hw_blk_list);
40	mutex_unlock(&dpu_hw_blk_lock);
41	}
42
43	/**
44	* dpu_hw_blk_destroy - destroy hw block object.
45	* @hw_blk: pointer to hw block object
46	* return: none
47	*/
48	void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk)
49	{
50	if (!hw_blk) {
51	pr_err("invalid parameters\n");
52	return;
53	}
54
55	if (atomic_read(&hw_blk->refcount))
56	pr_err("hw_blk:%d.%d invalid refcount\n", hw_blk->type,
57	hw_blk->id);
58
59	mutex_lock(&dpu_hw_blk_lock);
60	list_del(&hw_blk->list);
61	mutex_unlock(&dpu_hw_blk_lock);
62	}
63
64	/**
65	* dpu_hw_blk_get - get hw_blk from free pool
66	* @hw_blk: if specified, increment reference count only
67	* @type: if hw_blk is not specified, allocate the next available of this type
68	* @id: if specified (>= 0), allocate the given instance of the above type
69	* return: pointer to hw block object
70	*/
71	struct dpu_hw_blk dpu_hw_blk_get(struct dpu_hw_blk hw_blk, u32 type, int id)
72	{
73	struct dpu_hw_blk *curr;
74	int rc, refcount;
75
76	if (!hw_blk) {
77	mutex_lock(&dpu_hw_blk_lock);
78	list_for_each_entry(curr, &dpu_hw_blk_list, list) {
79	if ((curr->type != type) \|\|
80	(id >= 0 && curr->id != id) \|\|
81	(id < 0 &&
82	atomic_read(&curr->refcount)))
83	continue;
84
85	hw_blk = curr;
86	break;
87	}
88	mutex_unlock(&dpu_hw_blk_lock);
89	}
90
91	if (!hw_blk) {
92	pr_debug("no hw_blk:%d\n", type);
93	return NULL;
94	}
95
96	refcount = atomic_inc_return(&hw_blk->refcount);
97
98	if (refcount == 1 && hw_blk->ops.start) {
99	rc = hw_blk->ops.start(hw_blk);
100	if (rc) {
101	pr_err("failed to start hw_blk:%d rc:%d\n", type, rc);
102	goto error_start;
103	}
104	}
105
106	pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type,
107	hw_blk->id, refcount);
108	return hw_blk;
109
110	error_start:
111	dpu_hw_blk_put(hw_blk);
112	return ERR_PTR(rc);
113	}
114
115	/**
116	* dpu_hw_blk_put - put hw_blk to free pool if decremented refcount is zero
117	* @hw_blk: hw block to be freed
118	*/
119	void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk)
120	{
121	if (!hw_blk) {
122	pr_err("invalid parameters\n");
123	return;
124	}
125
126	pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, hw_blk->id,
127	atomic_read(&hw_blk->refcount));
128
129	if (!atomic_read(&hw_blk->refcount)) {
130	pr_err("hw_blk:%d.%d invalid put\n", hw_blk->type, hw_blk->id);
131	return;
132	}
133
134	if (atomic_dec_return(&hw_blk->refcount))
135	return;
136
137	if (hw_blk->ops.stop)
138	hw_blk->ops.stop(hw_blk);
139	}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h+1−21

@@ -7,19 +7,9 @@ · 6 unmodified lines
7		7
8	#include <linux/types.h>	8	#include <linux/types.h>
9	#include <linux/list.h>	9	#include <linux/list.h>
10	#include <linux/atomic.h>
11		10
12	struct dpu_hw_blk;	11	struct dpu_hw_blk;
13		12
14	/**
15	* struct dpu_hw_blk_ops - common hardware block operations
16	* @start: start operation on first get
17	* @stop: stop operation on last put
18	*/
19	struct dpu_hw_blk_ops {
20	int (start)(struct dpu_hw_blk );
21	void (stop)(struct dpu_hw_blk );
22	};
23		13
24	/**	14	/**
25	* struct dpu_hw_blk - definition of hardware block object	15	* struct dpu_hw_blk - definition of hardware block object
@@ -29,17 +19,7 @@ struct dpu_hw_blk_ops { · 3 unmodified lines
29	* @refcount: reference/usage count	19	* @refcount: reference/usage count
30	*/	20	*/
31	struct dpu_hw_blk {	21	struct dpu_hw_blk {
32	struct list_head list;	22	/* opaque */
33	u32 type;
34	int id;
35	atomic_t refcount;
36	struct dpu_hw_blk_ops ops;
37	};	23	};
38		24
39	void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id,
40	struct dpu_hw_blk_ops *ops);
41	void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk);
42
43	struct dpu_hw_blk dpu_hw_blk_get(struct dpu_hw_blk hw_blk, u32 type, int id);
44	void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk);
45	#endif /_DPU_HW_BLK_H /	25	#endif /_DPU_HW_BLK_H /

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c+136−66

 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include "dpu_hw_mdss.h"
+#include "dpu_hw_interrupts.h"
 #include "dpu_hw_catalog.h"
 #include "dpu_kms.h"
 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
-#define INTR_SC7180_MASK \
+#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
-	(BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
+			 BIT(MDP_SSPP_TOP0_INTR2) | \
-	BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
+			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-	BIT(DPU_IRQ_TYPE_PING_PONG_AUTO_REF) |\
+			 BIT(MDP_INTF0_INTR) | \
-	BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\
+			 BIT(MDP_INTF1_INTR) | \
-	BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK))
+			 BIT(MDP_INTF2_INTR) | \
+			 BIT(MDP_INTF3_INTR) | \
+			 BIT(MDP_INTF4_INTR) | \
+			 BIT(MDP_AD4_0_INTR) | \
+			 BIT(MDP_AD4_1_INTR))
+#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+			 BIT(MDP_SSPP_TOP0_INTR2) | \
+			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+			 BIT(MDP_INTF0_INTR) | \
+			 BIT(MDP_INTF1_INTR))
+#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+			 BIT(MDP_SSPP_TOP0_INTR2) | \
+			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+			 BIT(MDP_INTF0_7xxx_INTR) | \
+			 BIT(MDP_INTF1_7xxx_INTR) | \
+			 BIT(MDP_INTF5_7xxx_INTR))
+#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+			 BIT(MDP_SSPP_TOP0_INTR2) | \
+			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+			 BIT(MDP_INTF0_INTR) | \
+			 BIT(MDP_INTF1_INTR) | \
+			 BIT(MDP_INTF2_INTR) | \
+			 BIT(MDP_INTF3_INTR) | \
+			 BIT(MDP_INTF4_INTR))
 #define DEFAULT_PIXEL_RAM_SIZE		(50 * 1024)
 #define DEFAULT_DPU_LINE_WIDTH		2048
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x1000, .len = 0xE4,
-	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
+	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
 	.base = 0x1200, .len = 0xE4,
-	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
+	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
 	.base = 0x1400, .len = 0xE4,
-	.features = 0
+	.features = 0,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	},
 	{
 	.name = "ctl_3", .id = CTL_3,
 	.base = 0x1600, .len = 0xE4,
-	.features = 0
+	.features = 0,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 	},
 	{
 	.name = "ctl_4", .id = CTL_4,
 	.base = 0x1800, .len = 0xE4,
-	.features = 0
+	.features = 0,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 	},
 };
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x1000, .len = 0xE4,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
 	.base = 0x1200, .len = 0xE4,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
 	.base = 0x1400, .len = 0xE4,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	},
 };
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x1000, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
+	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
 	.base = 0x1200, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
+	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
 	.base = 0x1400, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	},
 	{
 	.name = "ctl_3", .id = CTL_3,
 	.base = 0x1600, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 	},
 	{
 	.name = "ctl_4", .id = CTL_4,
 	.base = 0x1800, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 	},
 	{
 	.name = "ctl_5", .id = CTL_5,
 	.base = 0x1a00, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 	},
 };
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x15000, .len = 0x1E8,
-	.features = CTL_SC7280_MASK
+	.features = CTL_SC7280_MASK,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
 	.base = 0x16000, .len = 0x1E8,
-	.features = CTL_SC7280_MASK
+	.features = CTL_SC7280_MASK,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
 	.base = 0x17000, .len = 0x1E8,
-	.features = CTL_SC7280_MASK
+	.features = CTL_SC7280_MASK,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	},
 	{
 	.name = "ctl_3", .id = CTL_3,
 	.base = 0x18000, .len = 0x1E8,
-	.features = CTL_SC7280_MASK
+	.features = CTL_SC7280_MASK,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 	},
 };
 	.len = 0x20, .version = 0x20000},
 };
-#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \
+#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
 	{\
 	.name = _name, .id = _id, \
 	.base = _base, .len = 0xd4, \
 	.features = PINGPONG_SDM845_SPLIT_MASK, \
 	.merge_3d = _merge_3d, \
-	.sblk = &_sblk \
+	.sblk = &_sblk, \
+	.intr_done = _done, \
+	.intr_rdptr = _rdptr, \
 	}
-#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \
+#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
 	{\
 	.name = _name, .id = _id, \
 	.base = _base, .len = 0xd4, \
 	.features = PINGPONG_SDM845_MASK, \
 	.merge_3d = _merge_3d, \
-	.sblk = &_sblk \
+	.sblk = &_sblk, \
+	.intr_done = _done, \
+	.intr_rdptr = _rdptr, \
 	}
 static const struct dpu_pingpong_cfg sdm845_pp[] = {
-	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
+	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
-	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
-	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
-	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk),
+	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 };
 static struct dpu_pingpong_cfg sc7180_pp[] = {
-	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
+	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
-	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
+	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
 };
 static const struct dpu_pingpong_cfg sm8150_pp[] = {
-	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te),
+	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
-	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
-	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
-	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk),
+	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
-	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
-	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+			-1),
+	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+			-1),
 };
 /*************************************************************
 };
 static const struct dpu_pingpong_cfg sc7280_pp[] = {
-	PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk),
+	PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
-	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk),
+	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
-	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk),
+	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
-	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk),
+	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
 };
 /*************************************************************
  * INTF sub blocks config
  *************************************************************/
-#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features) \
+#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
 	{\
 	.name = _name, .id = _id, \
 	.base = _base, .len = 0x280, \
 	.features = _features, \
 	.type = _type, \
 	.controller_id = _ctrl_id, \
-	.prog_fetch_lines_worst_case = _progfetch \
+	.prog_fetch_lines_worst_case = _progfetch, \
+	.intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
+	.intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
 	}
 static const struct dpu_intf_cfg sdm845_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK),
+	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
-	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK),
+	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
-	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK),
+	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
-	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK),
+	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 };
 static const struct dpu_intf_cfg sc7180_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK),
+	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
-	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK),
+	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 };
 static const struct dpu_intf_cfg sm8150_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK),
+	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
-	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK),
+	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
-	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK),
+	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
-	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK),
+	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 };
 static const struct dpu_intf_cfg sc7280_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK),
+	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
-	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK),
+	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
-	INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK),
+	INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
 };
 /*************************************************************
 		.reg_dma_count = 1,
 		.dma_cfg = sdm845_regdma,
 		.perf = sdm845_perf_data,
-		.mdss_irqs = 0x3ff,
+		.mdss_irqs = IRQ_SDM845_MASK,
 	};
 }
 		.reg_dma_count = 1,
 		.dma_cfg = sdm845_regdma,
 		.perf = sc7180_perf_data,
-		.mdss_irqs = 0x3f,
+		.mdss_irqs = IRQ_SC7180_MASK,
-		.obsolete_irq = INTR_SC7180_MASK,
 	};
 }
 		.reg_dma_count = 1,
 		.dma_cfg = sm8150_regdma,
 		.perf = sm8150_perf_data,
-		.mdss_irqs = 0x3ff,
+		.mdss_irqs = IRQ_SDM845_MASK,
 	};
 }
 		.reg_dma_count = 1,
 		.dma_cfg = sm8250_regdma,
 		.perf = sm8250_perf_data,
-		.mdss_irqs = 0xff,
+		.mdss_irqs = IRQ_SM8250_MASK,
 	};
 }
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
 		.perf = sc7280_perf_data,
-		.mdss_irqs = 0x1c07,
+		.mdss_irqs = IRQ_SC7280_MASK,
-		.obsolete_irq = INTR_SC7180_MASK,
 	};
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h+12−4

 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  */
 #ifndef _DPU_HW_CATALOG_H
 	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
 };
-/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
+/* struct dpu_ctl_cfg : MDP CTL instance info
  * @id:                index identifying this block
  * @base:              register base offset to mdss
  * @features           bit mask identifying sub-blocks/features
+ * @intr_start:        interrupt index for CTL_START
  */
 struct dpu_ctl_cfg {
 	DPU_HW_BLK_INFO;
+	s32 intr_start;
 };
 /**
  * @id                 enum identifying this block
  * @base               register offset of this block
  * @features           bit mask identifying sub-blocks/features
+ * @intr_done:         index for PINGPONG done interrupt
+ * @intr_rdptr:        index for PINGPONG readpointer done interrupt
  * @sblk               sub-blocks information
  */
 struct dpu_pingpong_cfg  {
 	DPU_HW_BLK_INFO;
 	u32 merge_3d;
+	s32 intr_done;
+	s32 intr_rdptr;
 	const struct dpu_pingpong_sub_blks *sblk;
 };
  * @type:              Interface type(DSI, DP, HDMI)
  * @controller_id:     Controller Instance ID in case of multiple of intf type
  * @prog_fetch_lines_worst_case	Worst case latency num lines needed to prefetch
+ * @intr_underrun:	index for INTF underrun interrupt
+ * @intr_vsync:	        index for INTF VSYNC interrupt
  */
 struct dpu_intf_cfg  {
 	DPU_HW_BLK_INFO;
 	u32 type;   /* interface type*/
 	u32 controller_id;
 	u32 prog_fetch_lines_worst_case;
+	s32 intr_underrun;
+	s32 intr_vsync;
 };
 /**
  * @cursor_formats     Supported formats for cursor pipe
  * @vig_formats        Supported formats for vig pipe
  * @mdss_irqs:         Bitmap with the irqs supported by the target
- * @obsolete_irq:       Irq types that are obsolete for a particular target
  */
 struct dpu_mdss_cfg {
 	u32 hwversion;
 	const struct dpu_format_extended *vig_formats;
 	unsigned long mdss_irqs;
-	unsigned long obsolete_irq;
 };
 struct dpu_mdss_hw_cfg_handler {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c+0−6

 		ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active;
 };
-static struct dpu_hw_blk_ops dpu_hw_ops;
 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
 		void __iomem *addr,
 		const struct dpu_mdss_cfg *m)
 	c->mixer_count = m->mixer_count;
 	c->mixer_hw_caps = m->mixer;
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops);
 	return c;
 }
 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx)
 {
-	if (ctx)
-		dpu_hw_blk_destroy(&ctx->base);
 	kfree(ctx);
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c+0−7

 	return ERR_PTR(-EINVAL);
 }
-static struct dpu_hw_blk_ops dpu_hw_ops;
 struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
 			void __iomem *addr,
 			const struct dpu_mdss_cfg *m)
 	c->cap = cfg;
 	_setup_dspp_ops(c, c->cap->features);
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops);
 	return c;
 }
 void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)
 {
-	if (dspp)
-		dpu_hw_blk_destroy(&dspp->base);
 	kfree(dspp);
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c+110−1398

@@ -29,145 +29,6 @@ · 28 unmodified lines
29	#define MDP_INTF_1_OFF_REV_7xxx 0x35000	29	#define MDP_INTF_1_OFF_REV_7xxx 0x35000
30	#define MDP_INTF_5_OFF_REV_7xxx 0x39000	30	#define MDP_INTF_5_OFF_REV_7xxx 0x39000
31		31
32	/**
33	* WB interrupt status bit definitions
34	*/
35	#define DPU_INTR_WB_0_DONE BIT(0)
36	#define DPU_INTR_WB_1_DONE BIT(1)
37	#define DPU_INTR_WB_2_DONE BIT(4)
38
39	/**
40	* WDOG timer interrupt status bit definitions
41	*/
42	#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
43	#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
44	#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
45	#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
46	#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
47
48	/**
49	* Pingpong interrupt status bit definitions
50	*/
51	#define DPU_INTR_PING_PONG_0_DONE BIT(8)
52	#define DPU_INTR_PING_PONG_1_DONE BIT(9)
53	#define DPU_INTR_PING_PONG_2_DONE BIT(10)
54	#define DPU_INTR_PING_PONG_3_DONE BIT(11)
55	#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
56	#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
57	#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
58	#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
59	#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
60	#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
61	#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
62	#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
63	#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
64	#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
65	#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
66	#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23)
67
68	/**
69	* Interface interrupt status bit definitions
70	*/
71	#define DPU_INTR_INTF_0_UNDERRUN BIT(24)
72	#define DPU_INTR_INTF_1_UNDERRUN BIT(26)
73	#define DPU_INTR_INTF_2_UNDERRUN BIT(28)
74	#define DPU_INTR_INTF_3_UNDERRUN BIT(30)
75	#define DPU_INTR_INTF_5_UNDERRUN BIT(22)
76	#define DPU_INTR_INTF_0_VSYNC BIT(25)
77	#define DPU_INTR_INTF_1_VSYNC BIT(27)
78	#define DPU_INTR_INTF_2_VSYNC BIT(29)
79	#define DPU_INTR_INTF_3_VSYNC BIT(31)
80	#define DPU_INTR_INTF_5_VSYNC BIT(23)
81
82	/**
83	* Pingpong Secondary interrupt status bit definitions
84	*/
85	#define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0)
86	#define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4)
87	#define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8)
88	#define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22)
89	#define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28)
90
91	/**
92	* Pingpong TEAR detection interrupt status bit definitions
93	*/
94	#define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16)
95	#define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17)
96	#define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18)
97	#define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19)
98
99	/**
100	* Pingpong TE detection interrupt status bit definitions
101	*/
102	#define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24)
103	#define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25)
104	#define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26)
105	#define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27)
106
107	/**
108	* Ctl start interrupt status bit definitions
109	*/
110	#define DPU_INTR_CTL_0_START BIT(9)
111	#define DPU_INTR_CTL_1_START BIT(10)
112	#define DPU_INTR_CTL_2_START BIT(11)
113	#define DPU_INTR_CTL_3_START BIT(12)
114	#define DPU_INTR_CTL_4_START BIT(13)
115
116	/**
117	* Concurrent WB overflow interrupt status bit definitions
118	*/
119	#define DPU_INTR_CWB_2_OVERFLOW BIT(14)
120	#define DPU_INTR_CWB_3_OVERFLOW BIT(15)
121
122	/**
123	* Histogram VIG done interrupt status bit definitions
124	*/
125	#define DPU_INTR_HIST_VIG_0_DONE BIT(0)
126	#define DPU_INTR_HIST_VIG_1_DONE BIT(4)
127	#define DPU_INTR_HIST_VIG_2_DONE BIT(8)
128	#define DPU_INTR_HIST_VIG_3_DONE BIT(10)
129
130	/**
131	* Histogram VIG reset Sequence done interrupt status bit definitions
132	*/
133	#define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1)
134	#define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5)
135	#define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9)
136	#define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11)
137
138	/**
139	* Histogram DSPP done interrupt status bit definitions
140	*/
141	#define DPU_INTR_HIST_DSPP_0_DONE BIT(12)
142	#define DPU_INTR_HIST_DSPP_1_DONE BIT(16)
143	#define DPU_INTR_HIST_DSPP_2_DONE BIT(20)
144	#define DPU_INTR_HIST_DSPP_3_DONE BIT(22)
145
146	/**
147	* Histogram DSPP reset Sequence done interrupt status bit definitions
148	*/
149	#define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13)
150	#define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17)
151	#define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21)
152	#define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23)
153
154	/**
155	* INTF interrupt status bit definitions
156	*/
157	#define DPU_INTR_VIDEO_INTO_STATIC BIT(0)
158	#define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1)
159	#define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2)
160	#define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3)
161	#define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4)
162	#define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5)
163	#define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6)
164	#define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7)
165	#define DPU_INTR_PROG_LINE BIT(8)
166
167	/**
168	* AD4 interrupt status bit definitions
169	*/
170	#define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
171	/**	32	/**
172	* struct dpu_intr_reg - array of DPU register sets	33	* struct dpu_intr_reg - array of DPU register sets
173	* @clr_off: offset to CLEAR reg	34	* @clr_off: offset to CLEAR reg
@@ -180,22 +41,10 @@ struct dpu_intr_reg { · 6 unmodified lines
180	u32 status_off;	41	u32 status_off;
181	};	42	};
182		43
183	/**
184	* struct dpu_irq_type - maps each irq with i/f
185	* @intr_type: type of interrupt listed in dpu_intr_type
186	* @instance_idx: instance index of the associated HW block in DPU
187	* @irq_mask: corresponding bit in the interrupt status reg
188	* @reg_idx: which reg set to use
189	*/
190	struct dpu_irq_type {
191	u32 intr_type;
192	u32 instance_idx;
193	u32 irq_mask;
194	u32 reg_idx;
195	};
196
197	/*	44	/*
198	* struct dpu_intr_reg - List of DPU interrupt registers	45	* struct dpu_intr_reg - List of DPU interrupt registers
		46	*
		47	* When making changes be sure to sync with dpu_hw_intr_reg
199	*/	48	*/
200	static const struct dpu_intr_reg dpu_intr_set[] = {	49	static const struct dpu_intr_reg dpu_intr_set[] = {
201	{	50	{
@@ -265,1101 +114,22 @@ static const struct dpu_intr_reg dpu_intr_set[] = { · 63 unmodified lines
265	},	114	},
266	};	115	};
267		116
268	/*	117	#define DPU_IRQ_REG(irq_idx) (irq_idx / 32)
269	* struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this	118	#define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32))
270	* table that have a matching interface type and
271	* instance index.
272	*/
273	static const struct dpu_irq_type dpu_irq_map[] = {
274	/* BEGIN MAP_RANGE: 0-31, INTR */
275	/* irq_idx: 0-3 */
276	{ DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0},
277	{ DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0},
278	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0},
279	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0},
280	/* irq_idx: 4-7 */
281	{ DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0},
282	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0},
283	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0},
284	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0},
285	/* irq_idx: 8-11 */
286	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0,
287	DPU_INTR_PING_PONG_0_DONE, 0},
288	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1,
289	DPU_INTR_PING_PONG_1_DONE, 0},
290	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2,
291	DPU_INTR_PING_PONG_2_DONE, 0},
292	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3,
293	DPU_INTR_PING_PONG_3_DONE, 0},
294	/* irq_idx: 12-15 */
295	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0,
296	DPU_INTR_PING_PONG_0_RD_PTR, 0},
297	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1,
298	DPU_INTR_PING_PONG_1_RD_PTR, 0},
299	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2,
300	DPU_INTR_PING_PONG_2_RD_PTR, 0},
301	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3,
302	DPU_INTR_PING_PONG_3_RD_PTR, 0},
303	/* irq_idx: 16-19 */
304	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0,
305	DPU_INTR_PING_PONG_0_WR_PTR, 0},
306	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1,
307	DPU_INTR_PING_PONG_1_WR_PTR, 0},
308	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2,
309	DPU_INTR_PING_PONG_2_WR_PTR, 0},
310	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3,
311	DPU_INTR_PING_PONG_3_WR_PTR, 0},
312	/* irq_idx: 20-23 */
313	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0,
314	DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0},
315	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1,
316	DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0},
317	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2,
318	DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0},
319	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3,
320	DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0},
321	/* irq_idx: 24-27 */
322	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0},
323	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0},
324	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0},
325	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0},
326	/* irq_idx: 28-31 */
327	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0},
328	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0},
329	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0},
330	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0},
331	/* irq_idx:32-33 */
332	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0},
333	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0},
334	/* irq_idx:34-63 */
335	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
336	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
337	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
338	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
339	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
340	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
341	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
342	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
343	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
344	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
345	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
346	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
347	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
348	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
349	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
350	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
351	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
352	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
353	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
354	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
355	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
356	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
357	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
358	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
359	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
360	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
361	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
362	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
363	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
364	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
365	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
366	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
367	/* BEGIN MAP_RANGE: 64-95, INTR2 */
368	/* irq_idx: 64-67 */
369	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0,
370	DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1},
371	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
372	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
373	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
374	/* irq_idx: 68-71 */
375	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,
376	DPU_INTR_PING_PONG_S0_WR_PTR, 1},
377	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
378	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
379	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
380	/* irq_idx: 72 */
381	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
382	DPU_INTR_PING_PONG_S0_RD_PTR, 1},
383	/* irq_idx: 73-77 */
384	{ DPU_IRQ_TYPE_CTL_START, CTL_0,
385	DPU_INTR_CTL_0_START, 1},
386	{ DPU_IRQ_TYPE_CTL_START, CTL_1,
387	DPU_INTR_CTL_1_START, 1},
388	{ DPU_IRQ_TYPE_CTL_START, CTL_2,
389	DPU_INTR_CTL_2_START, 1},
390	{ DPU_IRQ_TYPE_CTL_START, CTL_3,
391	DPU_INTR_CTL_3_START, 1},
392	{ DPU_IRQ_TYPE_CTL_START, CTL_4,
393	DPU_INTR_CTL_4_START, 1},
394	/* irq_idx: 78-79 */
395	{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1},
396	{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1},
397	/* irq_idx: 80-83 */
398	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
399	DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1},
400	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
401	DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1},
402	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2,
403	DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1},
404	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
405	DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1},
406	/* irq_idx: 84-87 */
407	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
408	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
409	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
410	DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1},
411	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
412	/* irq_idx: 88-91 */
413	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
414	DPU_INTR_PING_PONG_0_TE_DETECTED, 1},
415	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1,
416	DPU_INTR_PING_PONG_1_TE_DETECTED, 1},
417	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2,
418	DPU_INTR_PING_PONG_2_TE_DETECTED, 1},
419	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3,
420	DPU_INTR_PING_PONG_3_TE_DETECTED, 1},
421	/* irq_idx: 92-95 */
422	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0,
423	DPU_INTR_PING_PONG_S0_TE_DETECTED, 1},
424	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
425	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
426	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
427	/* irq_idx: 96-127 */
428	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
429	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
430	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
431	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
432	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
433	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
434	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
435	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
436	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
437	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
438	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
439	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
440	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
441	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
442	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
443	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
444	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
445	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
446	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
447	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
448	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
449	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
450	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
451	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
452	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
453	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
454	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
455	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
456	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
457	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
458	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
459	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
460	/* BEGIN MAP_RANGE: 128-159 HIST */
461	/* irq_idx: 128-131 */
462	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2},
463	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
464	DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2},
465	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
466	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
467	/* irq_idx: 132-135 */
468	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2},
469	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
470	DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2},
471	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
472	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
473	/* irq_idx: 136-139 */
474	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2},
475	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
476	DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2},
477	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2},
478	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3,
479	DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2},
480	/* irq_idx: 140-143 */
481	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2},
482	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0,
483	DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2},
484	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
485	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
486	/* irq_idx: 144-147 */
487	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2},
488	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1,
489	DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2},
490	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
491	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
492	/* irq_idx: 148-151 */
493	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2},
494	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2,
495	DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2},
496	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2},
497	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3,
498	DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2},
499	/* irq_idx: 152-155 */
500	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
501	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
502	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
503	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
504	/* irq_idx: 156-159 */
505	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
506	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
507	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
508	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
509	/* irq_idx: 160-191 */
510	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
511	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
512	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
513	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
514	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
515	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
516	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
517	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
518	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
519	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
520	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
521	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
522	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
523	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
524	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
525	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
526	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
527	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
528	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
529	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
530	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
531	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
532	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
533	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
534	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
535	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
536	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
537	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
538	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
539	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
540	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
541	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
542	/* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */
543	/* irq_idx: 192-195 */
544	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
545	DPU_INTR_VIDEO_INTO_STATIC, 3},
546	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
547	DPU_INTR_VIDEO_OUTOF_STATIC, 3},
548	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
549	DPU_INTR_DSICMD_0_INTO_STATIC, 3},
550	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
551	DPU_INTR_DSICMD_0_OUTOF_STATIC, 3},
552	/* irq_idx: 196-199 */
553	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
554	DPU_INTR_DSICMD_1_INTO_STATIC, 3},
555	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
556	DPU_INTR_DSICMD_1_OUTOF_STATIC, 3},
557	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
558	DPU_INTR_DSICMD_2_INTO_STATIC, 3},
559	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
560	DPU_INTR_DSICMD_2_OUTOF_STATIC, 3},
561	/* irq_idx: 200-203 */
562	{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3},
563	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
564	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
565	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
566	/* irq_idx: 204-207 */
567	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
568	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
569	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
570	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
571	/* irq_idx: 208-211 */
572	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
573	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
574	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
575	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
576	/* irq_idx: 212-215 */
577	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
578	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
579	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
580	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
581	/* irq_idx: 216-219 */
582	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
583	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
584	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
585	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
586	/* irq_idx: 220-223 */
587	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
588	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
589	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
590	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
591	/* irq_idx: 224-255 */
592	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
593	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
594	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
595	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
596	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
597	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
598	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
599	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
600	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
601	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
602	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
603	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
604	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
605	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
606	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
607	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
608	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
609	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
610	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
611	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
612	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
613	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
614	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
615	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
616	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
617	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
618	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
619	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
620	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
621	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
622	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
623	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
624	/* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */
625	/* irq_idx: 256-259 */
626	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
627	DPU_INTR_VIDEO_INTO_STATIC, 4},
628	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
629	DPU_INTR_VIDEO_OUTOF_STATIC, 4},
630	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
631	DPU_INTR_DSICMD_0_INTO_STATIC, 4},
632	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
633	DPU_INTR_DSICMD_0_OUTOF_STATIC, 4},
634	/* irq_idx: 260-263 */
635	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
636	DPU_INTR_DSICMD_1_INTO_STATIC, 4},
637	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
638	DPU_INTR_DSICMD_1_OUTOF_STATIC, 4},
639	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
640	DPU_INTR_DSICMD_2_INTO_STATIC, 4},
641	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
642	DPU_INTR_DSICMD_2_OUTOF_STATIC, 4},
643	/* irq_idx: 264-267 */
644	{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4},
645	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
646	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
647	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
648	/* irq_idx: 268-271 */
649	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
650	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
651	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
652	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
653	/* irq_idx: 272-275 */
654	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
655	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
656	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
657	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
658	/* irq_idx: 276-279 */
659	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
660	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
661	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
662	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
663	/* irq_idx: 280-283 */
664	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
665	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
666	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
667	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
668	/* irq_idx: 284-287 */
669	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
670	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
671	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
672	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
673	/* irq_idx: 288-319 */
674	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
675	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
676	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
677	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
678	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
679	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
680	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
681	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
682	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
683	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
684	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
685	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
686	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
687	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
688	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
689	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
690	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
691	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
692	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
693	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
694	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
695	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
696	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
697	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
698	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
699	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
700	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
701	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
702	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
703	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
704	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
705	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
706	/* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */
707	/* irq_idx: 320-323 */
708	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2,
709	DPU_INTR_VIDEO_INTO_STATIC, 5},
710	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2,
711	DPU_INTR_VIDEO_OUTOF_STATIC, 5},
712	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2,
713	DPU_INTR_DSICMD_0_INTO_STATIC, 5},
714	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2,
715	DPU_INTR_DSICMD_0_OUTOF_STATIC, 5},
716	/* irq_idx: 324-327 */
717	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2,
718	DPU_INTR_DSICMD_1_INTO_STATIC, 5},
719	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2,
720	DPU_INTR_DSICMD_1_OUTOF_STATIC, 5},
721	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2,
722	DPU_INTR_DSICMD_2_INTO_STATIC, 5},
723	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2,
724	DPU_INTR_DSICMD_2_OUTOF_STATIC, 5},
725	/* irq_idx: 328-331 */
726	{ DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5},
727	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
728	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
729	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
730	/* irq_idx: 332-335 */
731	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
732	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
733	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
734	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
735	/* irq_idx: 336-339 */
736	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
737	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
738	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
739	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
740	/* irq_idx: 340-343 */
741	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
742	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
743	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
744	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
745	/* irq_idx: 344-347 */
746	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
747	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
748	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
749	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
750	/* irq_idx: 348-351 */
751	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
752	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
753	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
754	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
755	/* irq_idx: 352-383 */
756	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
757	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
758	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
759	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
760	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
761	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
762	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
763	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
764	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
765	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
766	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
767	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
768	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
769	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
770	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
771	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
772	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
773	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
774	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
775	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
776	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
777	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
778	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
779	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
780	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
781	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
782	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
783	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
784	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
785	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
786	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
787	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
788	/* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */
789	/* irq_idx: 384-387 */
790	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3,
791	DPU_INTR_VIDEO_INTO_STATIC, 6},
792	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3,
793	DPU_INTR_VIDEO_OUTOF_STATIC, 6},
794	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3,
795	DPU_INTR_DSICMD_0_INTO_STATIC, 6},
796	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3,
797	DPU_INTR_DSICMD_0_OUTOF_STATIC, 6},
798	/* irq_idx: 388-391 */
799	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3,
800	DPU_INTR_DSICMD_1_INTO_STATIC, 6},
801	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3,
802	DPU_INTR_DSICMD_1_OUTOF_STATIC, 6},
803	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3,
804	DPU_INTR_DSICMD_2_INTO_STATIC, 6},
805	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3,
806	DPU_INTR_DSICMD_2_OUTOF_STATIC, 6},
807	/* irq_idx: 392-395 */
808	{ DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6},
809	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
810	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
811	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
812	/* irq_idx: 396-399 */
813	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
814	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
815	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
816	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
817	/* irq_idx: 400-403 */
818	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
819	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
820	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
821	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
822	/* irq_idx: 404-407 */
823	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
824	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
825	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
826	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
827	/* irq_idx: 408-411 */
828	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
829	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
830	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
831	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
832	/* irq_idx: 412-415 */
833	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
834	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
835	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
836	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
837	/* irq_idx: 416-447*/
838	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
839	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
840	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
841	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
842	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
843	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
844	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
845	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
846	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
847	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
848	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
849	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
850	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
851	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
852	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
853	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
854	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
855	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
856	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
857	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
858	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
859	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
860	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
861	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
862	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
863	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
864	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
865	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
866	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
867	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
868	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
869	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
870	/* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */
871	/* irq_idx: 448-451 */
872	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4,
873	DPU_INTR_VIDEO_INTO_STATIC, 7},
874	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4,
875	DPU_INTR_VIDEO_OUTOF_STATIC, 7},
876	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4,
877	DPU_INTR_DSICMD_0_INTO_STATIC, 7},
878	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4,
879	DPU_INTR_DSICMD_0_OUTOF_STATIC, 7},
880	/* irq_idx: 452-455 */
881	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4,
882	DPU_INTR_DSICMD_1_INTO_STATIC, 7},
883	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4,
884	DPU_INTR_DSICMD_1_OUTOF_STATIC, 7},
885	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4,
886	DPU_INTR_DSICMD_2_INTO_STATIC, 7},
887	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4,
888	DPU_INTR_DSICMD_2_OUTOF_STATIC, 7},
889	/* irq_idx: 456-459 */
890	{ DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7},
891	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
892	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
893	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
894	/* irq_idx: 460-463 */
895	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
896	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
897	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
898	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
899	/* irq_idx: 464-467 */
900	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
901	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
902	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
903	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
904	/* irq_idx: 468-471 */
905	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
906	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
907	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
908	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
909	/* irq_idx: 472-475 */
910	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
911	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
912	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
913	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
914	/* irq_idx: 476-479 */
915	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
916	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
917	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
918	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
919	/* irq_idx: 480-511 */
920	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
921	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
922	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
923	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
924	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
925	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
926	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
927	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
928	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
929	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
930	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
931	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
932	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
933	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
934	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
935	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
936	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
937	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
938	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
939	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
940	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
941	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
942	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
943	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
944	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
945	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
946	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
947	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
948	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
949	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
950	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
951	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
952	/* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */
953	/* irq_idx: 512-515 */
954	{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8},
955	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
956	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
957	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
958	/* irq_idx: 516-519 */
959	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
960	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
961	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
962	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
963	/* irq_idx: 520-523 */
964	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
965	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
966	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
967	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
968	/* irq_idx: 524-527 */
969	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
970	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
971	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
972	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
973	/* irq_idx: 528-531 */
974	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
975	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
976	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
977	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
978	/* irq_idx: 532-535 */
979	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
980	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
981	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
982	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
983	/* irq_idx: 536-539 */
984	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
985	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
986	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
987	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
988	/* irq_idx: 540-543 */
989	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
990	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
991	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
992	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
993	/* irq_idx: 544-575*/
994	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
995	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
996	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
997	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
998	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
999	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1000	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1001	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1002	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1003	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1004	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1005	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1006	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1007	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1008	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1009	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1010	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1011	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1012	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1013	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1014	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1015	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1016	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1017	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1018	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1019	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1020	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1021	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1022	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1023	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1024	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1025	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
1026	/* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */
1027	/* irq_idx: 576-579 */
1028	{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9},
1029	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1030	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1031	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1032	/* irq_idx: 580-583 */
1033	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1034	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1035	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1036	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1037	/* irq_idx: 584-587 */
1038	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1039	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1040	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1041	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1042	/* irq_idx: 588-591 */
1043	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1044	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1045	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1046	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1047	/* irq_idx: 592-595 */
1048	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1049	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1050	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1051	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1052	/* irq_idx: 596-599 */
1053	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1054	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1055	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1056	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1057	/* irq_idx: 600-603 */
1058	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1059	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1060	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1061	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1062	/* irq_idx: 604-607 */
1063	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1064	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1065	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1066	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1067	/* irq_idx: 608-639 */
1068	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1069	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1070	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1071	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1072	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1073	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1074	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1075	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1076	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1077	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1078	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1079	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1080	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1081	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1082	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1083	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1084	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1085	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1086	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1087	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1088	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1089	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1090	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1091	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1092	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1093	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1094	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1095	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1096	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1097	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1098	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1099	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
1100	/* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */
1101	/* irq_idx: 640-643 */
1102	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
1103	DPU_INTR_VIDEO_INTO_STATIC, 10},
1104	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
1105	DPU_INTR_VIDEO_OUTOF_STATIC, 10},
1106	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
1107	DPU_INTR_DSICMD_0_INTO_STATIC, 10},
1108	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
1109	DPU_INTR_DSICMD_0_OUTOF_STATIC, 10},
1110	/* irq_idx: 644-647 */
1111	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
1112	DPU_INTR_DSICMD_1_INTO_STATIC, 10},
1113	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
1114	DPU_INTR_DSICMD_1_OUTOF_STATIC, 10},
1115	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
1116	DPU_INTR_DSICMD_2_INTO_STATIC, 10},
1117	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
1118	DPU_INTR_DSICMD_2_OUTOF_STATIC, 10},
1119	/* irq_idx: 648-651 */
1120	{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10},
1121	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1122	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1123	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1124	/* irq_idx: 652-655 */
1125	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1126	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1127	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1128	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1129	/* irq_idx: 656-659 */
1130	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1131	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1132	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1133	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1134	/* irq_idx: 660-663 */
1135	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1136	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1137	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1138	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1139	/* irq_idx: 664-667 */
1140	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1141	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1142	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1143	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1144	/* irq_idx: 668-671 */
1145	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1146	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1147	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1148	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1149	/* irq_idx: 672-703 */
1150	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1151	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1152	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1153	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1154	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1155	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1156	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1157	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1158	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1159	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1160	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1161	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1162	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1163	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1164	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1165	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1166	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1167	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1168	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1169	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1170	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1171	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1172	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1173	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1174	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1175	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1176	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1177	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1178	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1179	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1180	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1181	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1182	/* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */
1183	/* irq_idx: 704-707 */
1184	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
1185	DPU_INTR_VIDEO_INTO_STATIC, 11},
1186	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
1187	DPU_INTR_VIDEO_OUTOF_STATIC, 11},
1188	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
1189	DPU_INTR_DSICMD_0_INTO_STATIC, 11},
1190	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
1191	DPU_INTR_DSICMD_0_OUTOF_STATIC, 11},
1192	/* irq_idx: 708-711 */
1193	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
1194	DPU_INTR_DSICMD_1_INTO_STATIC, 11},
1195	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
1196	DPU_INTR_DSICMD_1_OUTOF_STATIC, 11},
1197	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
1198	DPU_INTR_DSICMD_2_INTO_STATIC, 11},
1199	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
1200	DPU_INTR_DSICMD_2_OUTOF_STATIC, 11},
1201	/* irq_idx: 712-715 */
1202	{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11},
1203	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1204	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1205	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1206	/* irq_idx: 716-719 */
1207	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1208	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1209	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1210	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1211	/* irq_idx: 720-723 */
1212	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1213	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1214	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1215	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1216	/* irq_idx: 724-727 */
1217	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1218	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1219	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1220	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1221	/* irq_idx: 728-731 */
1222	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1223	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1224	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1225	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1226	/* irq_idx: 732-735 */
1227	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1228	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1229	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1230	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1231	/* irq_idx: 736-767 */
1232	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1233	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1234	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1235	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1236	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1237	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1238	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1239	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1240	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1241	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1242	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1243	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1244	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1245	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1246	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1247	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1248	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1249	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1250	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1251	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1252	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1253	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1254	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1255	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1256	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1257	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1258	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1259	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1260	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1261	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1262	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1263	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1264	/* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */
1265	/* irq_idx: 768-771 */
1266	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5,
1267	DPU_INTR_VIDEO_INTO_STATIC, 12},
1268	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5,
1269	DPU_INTR_VIDEO_OUTOF_STATIC, 12},
1270	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5,
1271	DPU_INTR_DSICMD_0_INTO_STATIC, 12},
1272	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5,
1273	DPU_INTR_DSICMD_0_OUTOF_STATIC, 12},
1274	/* irq_idx: 772-775 */
1275	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5,
1276	DPU_INTR_DSICMD_1_INTO_STATIC, 12},
1277	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5,
1278	DPU_INTR_DSICMD_1_OUTOF_STATIC, 12},
1279	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5,
1280	DPU_INTR_DSICMD_2_INTO_STATIC, 12},
1281	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5,
1282	DPU_INTR_DSICMD_2_OUTOF_STATIC, 12},
1283	/* irq_idx: 776-779 */
1284	{ DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12},
1285	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1286	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1287	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1288	/* irq_idx: 780-783 */
1289	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1290	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1291	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1292	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1293	/* irq_idx: 784-787 */
1294	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1295	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1296	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1297	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1298	/* irq_idx: 788-791 */
1299	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1300	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1301	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1302	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1303	/* irq_idx: 792-795 */
1304	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1305	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1306	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1307	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1308	/* irq_idx: 796-799 */
1309	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1310	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1311	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1312	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1313	/* irq_idx: 800-831 */
1314	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1315	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1316	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1317	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1318	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1319	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1320	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1321	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1322	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1323	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1324	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1325	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1326	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1327	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1328	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1329	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1330	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1331	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1332	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1333	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1334	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1335	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1336	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1337	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1338	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1339	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1340	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1341	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1342	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1343	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1344	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1345	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1346	};
1347		119
1348	static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr,	120	static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
1349	enum dpu_intr_type intr_type, u32 instance_idx)	121	int irq_idx)
1350	{	122	{
1351	int i;	123	int reg_idx;
1352		124
1353	for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) {	125	if (!intr)
1354	if (intr_type == dpu_irq_map[i].intr_type &&	126	return;
1355	instance_idx == dpu_irq_map[i].instance_idx &&
1356	!(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type)))
1357	return i;
1358	}
1359		127
1360	pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n",	128	reg_idx = DPU_IRQ_REG(irq_idx);
1361	intr_type, instance_idx);	129	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx));
1362	return -EINVAL;	130
		131	/* ensure register writes go through */
		132	wmb();
1363	}	133	}
1364		134
1365	static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,	135	static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
@@ -1368,9 +138,9 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, · 2 unmodified lines
1368	{	138	{
1369	int reg_idx;	139	int reg_idx;
1370	int irq_idx;	140	int irq_idx;
1371	int start_idx;
1372	int end_idx;
1373	u32 irq_status;	141	u32 irq_status;
		142	u32 enable_mask;
		143	int bit;
1374	unsigned long irq_flags;	144	unsigned long irq_flags;
1375		145
1376	if (!intr)	146	if (!intr)
@@ -1383,86 +153,92 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, · 6 unmodified lines
1383	*/	153	*/
1384	spin_lock_irqsave(&intr->irq_lock, irq_flags);	154	spin_lock_irqsave(&intr->irq_lock, irq_flags);
1385	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {	155	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
1386	irq_status = intr->save_irq_status[reg_idx];	156	if (!test_bit(reg_idx, &intr->irq_mask))
		157	continue;
1387		158
1388	/*	159	/* Read interrupt status */
1389	* Each Interrupt register has a range of 64 indexes, and	160	irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
1390	* that is static for dpu_irq_map.	161
1391	*/	162	/* Read enable mask */
1392	start_idx = reg_idx * 64;	163	enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
1393	end_idx = start_idx + 64;	164
		165	/* and clear the interrupt */
		166	if (irq_status)
		167	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
		168	irq_status);
1394		169
1395	if (!test_bit(reg_idx, &intr->irq_mask) \|\|	170	/* Finally update IRQ status based on enable mask */
1396	start_idx >= ARRAY_SIZE(dpu_irq_map))	171	irq_status &= enable_mask;
		172
		173	if (!irq_status)
1397	continue;	174	continue;
1398		175
1399	/*	176	/*
1400	* Search through matching intr status from irq map.	177	* Search through matching intr status.
1401	* start_idx and end_idx defined the search range in
1402	* the dpu_irq_map.
1403	*/	178	*/
1404	for (irq_idx = start_idx;	179	while ((bit = ffs(irq_status)) != 0) {
1405	(irq_idx < end_idx) && irq_status;	180	irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
1406	irq_idx++)	181	/*
1407	if ((irq_status & dpu_irq_map[irq_idx].irq_mask) &&	182	* Once a match on irq mask, perform a callback
1408	(dpu_irq_map[irq_idx].reg_idx == reg_idx) &&	183	* to the given cbfunc. cbfunc will take care
1409	!(intr->obsolete_irq &	184	* the interrupt status clearing. If cbfunc is
1410	BIT(dpu_irq_map[irq_idx].intr_type))) {	185	* not provided, then the interrupt clearing
1411	/*	186	* is here.
1412	* Once a match on irq mask, perform a callback	187	*/
1413	* to the given cbfunc. cbfunc will take care	188	if (cbfunc)
1414	* the interrupt status clearing. If cbfunc is	189	cbfunc(arg, irq_idx);
1415	* not provided, then the interrupt clearing	190
1416	* is here.	191	dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
1417	*/	192
1418	if (cbfunc)	193	/*
1419	cbfunc(arg, irq_idx);	194	* When callback finish, clear the irq_status
1420	else	195	* with the matching mask. Once irq_status
1421	intr->ops.clear_intr_status_nolock(	196	* is all cleared, the search can be stopped.
1422	intr, irq_idx);	197	*/
1423		198	irq_status &= ~BIT(bit - 1);
1424	/*	199	}
1425	* When callback finish, clear the irq_status
1426	* with the matching mask. Once irq_status
1427	* is all cleared, the search can be stopped.
1428	*/
1429	irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
1430	}
1431	}	200	}
		201
		202	/* ensure register writes go through */
		203	wmb();
		204
1432	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);	205	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1433	}	206	}
1434		207
1435	static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)	208	static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
1436	{	209	{
1437	int reg_idx;	210	int reg_idx;
1438	unsigned long irq_flags;
1439	const struct dpu_intr_reg *reg;	211	const struct dpu_intr_reg *reg;
1440	const struct dpu_irq_type *irq;
1441	const char *dbgstr = NULL;	212	const char *dbgstr = NULL;
1442	uint32_t cache_irq_mask;	213	uint32_t cache_irq_mask;
1443		214
1444	if (!intr)	215	if (!intr)
1445	return -EINVAL;	216	return -EINVAL;
1446		217
1447	if (irq_idx < 0 \|\| irq_idx >= ARRAY_SIZE(dpu_irq_map)) {	218	if (irq_idx < 0 \|\| irq_idx >= intr->total_irqs) {
1448	pr_err("invalid IRQ index: [%d]\n", irq_idx);	219	pr_err("invalid IRQ index: [%d]\n", irq_idx);
1449	return -EINVAL;	220	return -EINVAL;
1450	}	221	}
1451		222
1452	irq = &dpu_irq_map[irq_idx];	223	/*
1453	reg_idx = irq->reg_idx;	224	* The cache_irq_mask and hardware RMW operations needs to be done
		225	* under irq_lock and it's the caller's responsibility to ensure that's
		226	* held.
		227	*/
		228	assert_spin_locked(&intr->irq_lock);
		229
		230	reg_idx = DPU_IRQ_REG(irq_idx);
1454	reg = &dpu_intr_set[reg_idx];	231	reg = &dpu_intr_set[reg_idx];
1455		232
1456	spin_lock_irqsave(&intr->irq_lock, irq_flags);
1457	cache_irq_mask = intr->cache_irq_mask[reg_idx];	233	cache_irq_mask = intr->cache_irq_mask[reg_idx];
1458	if (cache_irq_mask & irq->irq_mask) {	234	if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
1459	dbgstr = "DPU IRQ already set:";	235	dbgstr = "DPU IRQ already set:";
1460	} else {	236	} else {
1461	dbgstr = "DPU IRQ enabled:";	237	dbgstr = "DPU IRQ enabled:";
1462		238
1463	cache_irq_mask \|= irq->irq_mask;	239	cache_irq_mask \|= DPU_IRQ_MASK(irq_idx);
1464	/* Cleaning any pending interrupt */	240	/* Cleaning any pending interrupt */
1465	DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);	241	DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
1466	/* Enabling interrupts with the new mask */	242	/* Enabling interrupts with the new mask */
1467	DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);	243	DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
1468		244
@@ -1471,45 +247,49 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) · 2 unmodified lines
1471		247
1472	intr->cache_irq_mask[reg_idx] = cache_irq_mask;	248	intr->cache_irq_mask[reg_idx] = cache_irq_mask;
1473	}	249	}
1474	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1475		250
1476	pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,	251	pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
1477	irq->irq_mask, cache_irq_mask);	252	DPU_IRQ_MASK(irq_idx), cache_irq_mask);
1478		253
1479	return 0;	254	return 0;
1480	}	255	}
1481		256
1482	static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)	257	static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
1483	{	258	{
1484	int reg_idx;	259	int reg_idx;
1485	const struct dpu_intr_reg *reg;	260	const struct dpu_intr_reg *reg;
1486	const struct dpu_irq_type *irq;
1487	const char *dbgstr = NULL;	261	const char *dbgstr = NULL;
1488	uint32_t cache_irq_mask;	262	uint32_t cache_irq_mask;
1489		263
1490	if (!intr)	264	if (!intr)
1491	return -EINVAL;	265	return -EINVAL;
1492		266
1493	if (irq_idx < 0 \|\| irq_idx >= ARRAY_SIZE(dpu_irq_map)) {	267	if (irq_idx < 0 \|\| irq_idx >= intr->total_irqs) {
1494	pr_err("invalid IRQ index: [%d]\n", irq_idx);	268	pr_err("invalid IRQ index: [%d]\n", irq_idx);
1495	return -EINVAL;	269	return -EINVAL;
1496	}	270	}
1497		271
1498	irq = &dpu_irq_map[irq_idx];	272	/*
1499	reg_idx = irq->reg_idx;	273	* The cache_irq_mask and hardware RMW operations needs to be done
		274	* under irq_lock and it's the caller's responsibility to ensure that's
		275	* held.
		276	*/
		277	assert_spin_locked(&intr->irq_lock);
		278
		279	reg_idx = DPU_IRQ_REG(irq_idx);
1500	reg = &dpu_intr_set[reg_idx];	280	reg = &dpu_intr_set[reg_idx];
1501		281
1502	cache_irq_mask = intr->cache_irq_mask[reg_idx];	282	cache_irq_mask = intr->cache_irq_mask[reg_idx];
1503	if ((cache_irq_mask & irq->irq_mask) == 0) {	283	if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
1504	dbgstr = "DPU IRQ is already cleared:";	284	dbgstr = "DPU IRQ is already cleared:";
1505	} else {	285	} else {
1506	dbgstr = "DPU IRQ mask disable:";	286	dbgstr = "DPU IRQ mask disable:";
1507		287
1508	cache_irq_mask &= ~irq->irq_mask;	288	cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
1509	/* Disable interrupts based on the new mask */	289	/* Disable interrupts based on the new mask */
1510	DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);	290	DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
1511	/* Cleaning any pending interrupt */	291	/* Cleaning any pending interrupt */
1512	DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);	292	DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
1513		293
1514	/* ensure register write goes through */	294	/* ensure register write goes through */
1515	wmb();	295	wmb();
@@ -1517,27 +297,8 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) · 1 unmodified line
1517	intr->cache_irq_mask[reg_idx] = cache_irq_mask;	297	intr->cache_irq_mask[reg_idx] = cache_irq_mask;
1518	}	298	}
1519		299
1520	pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,	300	pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
1521	irq->irq_mask, cache_irq_mask);	301	DPU_IRQ_MASK(irq_idx), cache_irq_mask);
1522
1523	return 0;
1524	}
1525
1526	static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx)
1527	{
1528	unsigned long irq_flags;
1529
1530	if (!intr)
1531	return -EINVAL;
1532
1533	if (irq_idx < 0 \|\| irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
1534	pr_err("invalid IRQ index: [%d]\n", irq_idx);
1535	return -EINVAL;
1536	}
1537
1538	spin_lock_irqsave(&intr->irq_lock, irq_flags);
1539	dpu_hw_intr_disable_irq_nolock(intr, irq_idx);
1540	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1541		302
1542	return 0;	303	return 0;
1543	}	304	}
@@ -1580,58 +341,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) · 36 unmodified lines
1580	return 0;	341	return 0;
1581	}	342	}
1582		343
1583	static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
1584	{
1585	int i;
1586	u32 enable_mask;
1587	unsigned long irq_flags;
1588
1589	if (!intr)
1590	return;
1591
1592	spin_lock_irqsave(&intr->irq_lock, irq_flags);
1593	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
1594	if (!test_bit(i, &intr->irq_mask))
1595	continue;
1596
1597	/* Read interrupt status */
1598	intr->save_irq_status[i] = DPU_REG_READ(&intr->hw,
1599	dpu_intr_set[i].status_off);
1600
1601	/* Read enable mask */
1602	enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off);
1603
1604	/* and clear the interrupt */
1605	if (intr->save_irq_status[i])
1606	DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off,
1607	intr->save_irq_status[i]);
1608
1609	/* Finally update IRQ status based on enable mask */
1610	intr->save_irq_status[i] &= enable_mask;
1611	}
1612
1613	/* ensure register writes go through */
1614	wmb();
1615
1616	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1617	}
1618
1619	static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
1620	int irq_idx)
1621	{
1622	int reg_idx;
1623
1624	if (!intr)
1625	return;
1626
1627	reg_idx = dpu_irq_map[irq_idx].reg_idx;
1628	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
1629	dpu_irq_map[irq_idx].irq_mask);
1630
1631	/* ensure register writes go through */
1632	wmb();
1633	}
1634
1635	static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,	344	static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
1636	int irq_idx, bool clear)	345	int irq_idx, bool clear)
1637	{	346	{
@@ -1642,17 +351,17 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, · 4 unmodified lines
1642	if (!intr)	351	if (!intr)
1643	return 0;	352	return 0;
1644		353
1645	if (irq_idx >= ARRAY_SIZE(dpu_irq_map) \|\| irq_idx < 0) {	354	if (irq_idx < 0 \|\| irq_idx >= intr->total_irqs) {
1646	pr_err("invalid IRQ index: [%d]\n", irq_idx);	355	pr_err("invalid IRQ index: [%d]\n", irq_idx);
1647	return 0;	356	return 0;
1648	}	357	}
1649		358
1650	spin_lock_irqsave(&intr->irq_lock, irq_flags);	359	spin_lock_irqsave(&intr->irq_lock, irq_flags);
1651		360
1652	reg_idx = dpu_irq_map[irq_idx].reg_idx;	361	reg_idx = DPU_IRQ_REG(irq_idx);
1653	intr_status = DPU_REG_READ(&intr->hw,	362	intr_status = DPU_REG_READ(&intr->hw,
1654	dpu_intr_set[reg_idx].status_off) &	363	dpu_intr_set[reg_idx].status_off) &
1655	dpu_irq_map[irq_idx].irq_mask;	364	DPU_IRQ_MASK(irq_idx);
1656	if (intr_status && clear)	365	if (intr_status && clear)
1657	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,	366	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
1658	intr_status);	367	intr_status);
@@ -1665,17 +374,30 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, · 6 unmodified lines
1665	return intr_status;	374	return intr_status;
1666	}	375	}
1667		376
		377	static unsigned long dpu_hw_intr_lock(struct dpu_hw_intr *intr)
		378	{
		379	unsigned long irq_flags;
		380
		381	spin_lock_irqsave(&intr->irq_lock, irq_flags);
		382
		383	return irq_flags;
		384	}
		385
		386	static void dpu_hw_intr_unlock(struct dpu_hw_intr *intr, unsigned long irq_flags)
		387	{
		388	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
		389	}
		390
1668	static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)	391	static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
1669	{	392	{
1670	ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;	393	ops->enable_irq_locked = dpu_hw_intr_enable_irq_locked;
1671	ops->enable_irq = dpu_hw_intr_enable_irq;	394	ops->disable_irq_locked = dpu_hw_intr_disable_irq_locked;
1672	ops->disable_irq = dpu_hw_intr_disable_irq;
1673	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;	395	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
1674	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;	396	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
1675	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;	397	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
1676	ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
1677	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
1678	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;	398	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
		399	ops->lock = dpu_hw_intr_lock;
		400	ops->unlock = dpu_hw_intr_unlock;
1679	}	401	}
1680		402
1681	static void __intr_offset(struct dpu_mdss_cfg *m,	403	static void __intr_offset(struct dpu_mdss_cfg *m,
@@ -1701,7 +423,7 @@ struct dpu_hw_intr dpu_hw_intr_init(void __iomem addr, · 19 unmodified lines
1701	__intr_offset(m, addr, &intr->hw);	423	__intr_offset(m, addr, &intr->hw);
1702	__setup_intr_ops(&intr->ops);	424	__setup_intr_ops(&intr->ops);
1703		425
1704	intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);	426	intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32;
1705		427
1706	intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),	428	intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
1707	GFP_KERNEL);	429	GFP_KERNEL);
@@ -1710,16 +432,7 @@ struct dpu_hw_intr dpu_hw_intr_init(void __iomem addr, · 2 unmodified lines
1710	return ERR_PTR(-ENOMEM);	432	return ERR_PTR(-ENOMEM);
1711	}	433	}
1712		434
1713	intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
1714	GFP_KERNEL);
1715	if (intr->save_irq_status == NULL) {
1716	kfree(intr->cache_irq_mask);
1717	kfree(intr);
1718	return ERR_PTR(-ENOMEM);
1719	}
1720
1721	intr->irq_mask = m->mdss_irqs;	435	intr->irq_mask = m->mdss_irqs;
1722	intr->obsolete_irq = m->obsolete_irq;
1723		436
1724	spin_lock_init(&intr->irq_lock);	437	spin_lock_init(&intr->irq_lock);
1725		438
@@ -1730,7 +443,6 @@ void dpu_hw_intr_destroy(struct dpu_hw_intr *intr) · 4 unmodified lines
1730	{	443	{
1731	if (intr) {	444	if (intr) {
1732	kfree(intr->cache_irq_mask);	445	kfree(intr->cache_irq_mask);
1733	kfree(intr->save_irq_status);
1734	kfree(intr);	446	kfree(intr);
1735	}	447	}
1736	}	448	}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h+38−94

 #include "dpu_hw_util.h"
 #include "dpu_hw_mdss.h"
-/**
+/* When making changes be sure to sync with dpu_intr_set */
- * dpu_intr_type - HW Interrupt Type
+enum dpu_hw_intr_reg {
- * @DPU_IRQ_TYPE_WB_ROT_COMP:		WB rotator done
+	MDP_SSPP_TOP0_INTR,
- * @DPU_IRQ_TYPE_WB_WFD_COMP:		WB WFD done
+	MDP_SSPP_TOP0_INTR2,
- * @DPU_IRQ_TYPE_PING_PONG_COMP:	PingPong done
+	MDP_SSPP_TOP0_HIST_INTR,
- * @DPU_IRQ_TYPE_PING_PONG_RD_PTR:	PingPong read pointer
+	MDP_INTF0_INTR,
- * @DPU_IRQ_TYPE_PING_PONG_WR_PTR:	PingPong write pointer
+	MDP_INTF1_INTR,
- * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF:	PingPong auto refresh
+	MDP_INTF2_INTR,
- * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK:	PingPong Tear check
+	MDP_INTF3_INTR,
- * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK:	PingPong TE detection
+	MDP_INTF4_INTR,
- * @DPU_IRQ_TYPE_INTF_UNDER_RUN:	INTF underrun
+	MDP_AD4_0_INTR,
- * @DPU_IRQ_TYPE_INTF_VSYNC:		INTF VSYNC
+	MDP_AD4_1_INTR,
- * @DPU_IRQ_TYPE_CWB_OVERFLOW:		Concurrent WB overflow
+	MDP_INTF0_7xxx_INTR,
- * @DPU_IRQ_TYPE_HIST_VIG_DONE:		VIG Histogram done
+	MDP_INTF1_7xxx_INTR,
- * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ:	VIG Histogram reset
+	MDP_INTF5_7xxx_INTR,
- * @DPU_IRQ_TYPE_HIST_DSPP_DONE:	DSPP Histogram done
+	MDP_INTR_MAX,
- * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ:	DSPP Histogram reset
- * @DPU_IRQ_TYPE_WD_TIMER:		Watchdog timer
- * @DPU_IRQ_TYPE_SFI_VIDEO_IN:		Video static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_VIDEO_OUT:		Video static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_0_IN:		DSI CMD0 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_0_OUT:		DSI CMD0 static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_1_IN:		DSI CMD1 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_1_OUT:		DSI CMD1 static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_2_IN:		DSI CMD2 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_2_OUT:		DSI CMD2 static frame INTR out-of static
- * @DPU_IRQ_TYPE_PROG_LINE:		Programmable Line interrupt
- * @DPU_IRQ_TYPE_AD4_BL_DONE:		AD4 backlight
- * @DPU_IRQ_TYPE_CTL_START:		Control start
- * @DPU_IRQ_TYPE_RESERVED:		Reserved for expansion
- */
-enum dpu_intr_type {
-	DPU_IRQ_TYPE_WB_ROT_COMP,
-	DPU_IRQ_TYPE_WB_WFD_COMP,
-	DPU_IRQ_TYPE_PING_PONG_COMP,
-	DPU_IRQ_TYPE_PING_PONG_RD_PTR,
-	DPU_IRQ_TYPE_PING_PONG_WR_PTR,
-	DPU_IRQ_TYPE_PING_PONG_AUTO_REF,
-	DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK,
-	DPU_IRQ_TYPE_PING_PONG_TE_CHECK,
-	DPU_IRQ_TYPE_INTF_UNDER_RUN,
-	DPU_IRQ_TYPE_INTF_VSYNC,
-	DPU_IRQ_TYPE_CWB_OVERFLOW,
-	DPU_IRQ_TYPE_HIST_VIG_DONE,
-	DPU_IRQ_TYPE_HIST_VIG_RSTSEQ,
-	DPU_IRQ_TYPE_HIST_DSPP_DONE,
-	DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ,
-	DPU_IRQ_TYPE_WD_TIMER,
-	DPU_IRQ_TYPE_SFI_VIDEO_IN,
-	DPU_IRQ_TYPE_SFI_VIDEO_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_0_IN,
-	DPU_IRQ_TYPE_SFI_CMD_0_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_1_IN,
-	DPU_IRQ_TYPE_SFI_CMD_1_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_2_IN,
-	DPU_IRQ_TYPE_SFI_CMD_2_OUT,
-	DPU_IRQ_TYPE_PROG_LINE,
-	DPU_IRQ_TYPE_AD4_BL_DONE,
-	DPU_IRQ_TYPE_CTL_START,
-	DPU_IRQ_TYPE_RESERVED,
 };
+#define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
 struct dpu_hw_intr;
 /**
  * Interrupt operations.
  */
 struct dpu_hw_intr_ops {
-	/**
-	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
-	 *                 Used for all irq related ops
-	 * @intr:		HW interrupt handle
-	 * @intr_type:		Interrupt type defined in dpu_intr_type
-	 * @instance_idx:	HW interrupt block instance
-	 * @return:		irq_idx or -EINVAL for lookup fail
-	 */
-	int (*irq_idx_lookup)(struct dpu_hw_intr *intr,
-			enum dpu_intr_type intr_type,
-			u32 instance_idx);
 	/**
 	 * enable_irq - Enable IRQ based on lookup IRQ index
 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
 	 * @return:	0 for success, otherwise failure
 	 */
-	int (*enable_irq)(
+	int (*enable_irq_locked)(
 			struct dpu_hw_intr *intr,
 			int irq_idx);
 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
 	 * @return:	0 for success, otherwise failure
 	 */
-	int (*disable_irq)(
+	int (*disable_irq_locked)(
 			struct dpu_hw_intr *intr,
 			int irq_idx);
 			void (*cbfunc)(void *arg, int irq_idx),
 			void *arg);
-	/**
-	 * get_interrupt_statuses - Gets and store value from all interrupt
-	 *                          status registers that are currently fired.
-	 * @intr:	HW interrupt handle
-	 */
-	void (*get_interrupt_statuses)(
-			struct dpu_hw_intr *intr);
-	/**
-	 * clear_intr_status_nolock() - clears the HW interrupts without lock
-	 * @intr:	HW interrupt handle
-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
-	 */
-	void (*clear_intr_status_nolock)(
-			struct dpu_hw_intr *intr,
-			int irq_idx);
 	/**
 	 * get_interrupt_status - Gets HW interrupt status, and clear if set,
 	 *                        based on given lookup IRQ index.
 			struct dpu_hw_intr *intr,
 			int irq_idx,
 			bool clear);
+	/**
+	 * lock - take the IRQ lock
+	 * @intr:	HW interrupt handle
+	 * @return:	irq_flags for the taken spinlock
+	 */
+	unsigned long (*lock)(
+			struct dpu_hw_intr *intr);
+	/**
+	 * unlock - take the IRQ lock
+	 * @intr:	HW interrupt handle
+	 * @irq_flags:  the irq_flags returned from lock
+	 */
+	void (*unlock)(
+			struct dpu_hw_intr *intr, unsigned long irq_flags);
 };
 /**
  * @ops:              function pointer mapping for IRQ handling
  * @cache_irq_mask:   array of IRQ enable masks reg storage created during init
  * @save_irq_status:  array of IRQ status reg storage created during init
- * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
+ * @total_irqs: total number of irq_idx mapped in the hw_interrupts
  * @irq_lock:         spinlock for accessing IRQ resources
- * @obsolete_irq:      irq types that are obsolete for a particular target
  */
 struct dpu_hw_intr {
 	struct dpu_hw_blk_reg_map hw;
 	struct dpu_hw_intr_ops ops;
 	u32 *cache_irq_mask;
 	u32 *save_irq_status;
-	u32 irq_idx_tbl_size;
+	u32 total_irqs;
 	spinlock_t irq_lock;
 	unsigned long irq_mask;
-	unsigned long obsolete_irq;
 };
 /**

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c+0−6

 		ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
 }
-static struct dpu_hw_blk_ops dpu_hw_ops;
 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
 		void __iomem *addr,
 		const struct dpu_mdss_cfg *m)
 	c->mdss = m;
 	_setup_intf_ops(&c->ops, c->cap->features);
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
 	return c;
 }
 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
 {
-	if (intf)
-		dpu_hw_blk_destroy(&intf->base);
 	kfree(intf);
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c+0−6

 	ops->setup_border_color = dpu_hw_lm_setup_border_color;
 }
-static struct dpu_hw_blk_ops dpu_hw_ops;
 struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
 		void __iomem *addr,
 		const struct dpu_mdss_cfg *m)
 	c->cap = cfg;
 	_setup_mixer_ops(m, &c->ops, c->cap->features);
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops);
 	return c;
 }
 void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)
 {
-	if (lm)
-		dpu_hw_blk_destroy(&lm->base);
 	kfree(lm);
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h+1−1

@@ -343,7 +343,7 @@ enum dpu_3d_blend_mode { · 342 unmodified lines
343		343
344	/** struct dpu_format - defines the format configuration which	344	/** struct dpu_format - defines the format configuration which
345	* allows DPU HW to correctly fetch and decode the format	345	* allows DPU HW to correctly fetch and decode the format
346	* @base: base msm_format struture containing fourcc code	346	* @base: base msm_format structure containing fourcc code
347	* @fetch_planes: how the color components are packed in pixel format	347	* @fetch_planes: how the color components are packed in pixel format
348	* @element: element color ordering	348	* @element: element color ordering
349	* @bits: element bit widths	349	* @bits: element bit widths

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c+0−6

 	c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;
 };
-static struct dpu_hw_blk_ops dpu_hw_ops;
 struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx,
 		void __iomem *addr,
 		const struct dpu_mdss_cfg *m)
 	c->caps = cfg;
 	_setup_merge_3d_ops(c, c->caps->features);
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx, &dpu_hw_ops);
 	return c;
 }
 void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw)
 {
-	if (hw)
-		dpu_hw_blk_destroy(&hw->base);
 	kfree(hw);
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c+0−6

 		c->ops.setup_dither = dpu_hw_pp_setup_dither;
 };
-static struct dpu_hw_blk_ops dpu_hw_ops;
 struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
 		void __iomem *addr,
 		const struct dpu_mdss_cfg *m)
 	c->caps = cfg;
 	_setup_pingpong_ops(c, c->caps->features);
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops);
 	return c;
 }
 void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
 {
-	if (pp)
-		dpu_hw_blk_destroy(&pp->base);
 	kfree(pp);
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h+3−1

 			struct dpu_hw_dither_cfg *cfg);
 };
+struct dpu_hw_merge_3d;
 struct dpu_hw_pingpong {
 	struct dpu_hw_blk base;
 	struct dpu_hw_blk_reg_map hw;
 	/* pingpong */
 	enum dpu_pingpong idx;
 	const struct dpu_pingpong_cfg *caps;
-	struct dpu_hw_blk *merge_3d;
+	struct dpu_hw_merge_3d *merge_3d;
 	/* ops */
 	struct dpu_hw_pingpong_ops ops;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c+0−6

 	return ERR_PTR(-ENOMEM);
 }
-static struct dpu_hw_blk_ops dpu_hw_ops;
 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
 		void __iomem *addr, struct dpu_mdss_cfg *catalog,
 		bool is_virtual_pipe)
 	hw_pipe->cap = cfg;
 	_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
-	dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops);
 	return hw_pipe;
 }
 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
 {
-	if (ctx)
-		dpu_hw_blk_destroy(&ctx->base);
 	kfree(ctx);
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c+0−6

 	return ERR_PTR(-EINVAL);
 }
-static struct dpu_hw_blk_ops dpu_hw_ops;
 struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
 		void __iomem *addr,
 		const struct dpu_mdss_cfg *m)
 	mdp->caps = cfg;
 	_setup_mdp_ops(&mdp->ops, mdp->caps->features);
-	dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops);
 	return mdp;
 }
 void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)
 {
-	if (mdp)
-		dpu_hw_blk_destroy(&mdp->base);
 	kfree(mdp);
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c+55−15

@@ -19,6 +19,7 @@ · 18 unmodified lines
19	#include "msm_drv.h"	19	#include "msm_drv.h"
20	#include "msm_mmu.h"	20	#include "msm_mmu.h"
21	#include "msm_gem.h"	21	#include "msm_gem.h"
		22	#include "disp/msm_disp_snapshot.h"
22		23
23	#include "dpu_kms.h"	24	#include "dpu_kms.h"
24	#include "dpu_core_irq.h"	25	#include "dpu_core_irq.h"
@@ -798,6 +799,51 @@ static void dpu_irq_uninstall(struct msm_kms *kms) · 773 unmodified lines
798	dpu_core_irq_uninstall(dpu_kms);	799	dpu_core_irq_uninstall(dpu_kms);
799	}	800	}
800		801
		802	static void dpu_kms_mdp_snapshot(struct msm_disp_state disp_state, struct msm_kms kms)
		803	{
		804	int i;
		805	struct dpu_kms *dpu_kms;
		806	struct dpu_mdss_cfg *cat;
		807	struct dpu_hw_mdp *top;
		808
		809	dpu_kms = to_dpu_kms(kms);
		810
		811	cat = dpu_kms->catalog;
		812	top = dpu_kms->hw_mdp;
		813
		814	pm_runtime_get_sync(&dpu_kms->pdev->dev);
		815
		816	/* dump CTL sub-blocks HW regs info */
		817	for (i = 0; i < cat->ctl_count; i++)
		818	msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
		819	dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i);
		820
		821	/* dump DSPP sub-blocks HW regs info */
		822	for (i = 0; i < cat->dspp_count; i++)
		823	msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len,
		824	dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i);
		825
		826	/* dump INTF sub-blocks HW regs info */
		827	for (i = 0; i < cat->intf_count; i++)
		828	msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
		829	dpu_kms->mmio + cat->intf[i].base, "intf_%d", i);
		830
		831	/* dump PP sub-blocks HW regs info */
		832	for (i = 0; i < cat->pingpong_count; i++)
		833	msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len,
		834	dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i);
		835
		836	/* dump SSPP sub-blocks HW regs info */
		837	for (i = 0; i < cat->sspp_count; i++)
		838	msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len,
		839	dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i);
		840
		841	msm_disp_snapshot_add_block(disp_state, top->hw.length,
		842	dpu_kms->mmio + top->hw.blk_off, "top");
		843
		844	pm_runtime_put_sync(&dpu_kms->pdev->dev);
		845	}
		846
801	static const struct msm_kms_funcs kms_funcs = {	847	static const struct msm_kms_funcs kms_funcs = {
802	.hw_init = dpu_kms_hw_init,	848	.hw_init = dpu_kms_hw_init,
803	.irq_preinstall = dpu_irq_preinstall,	849	.irq_preinstall = dpu_irq_preinstall,
@@ -818,6 +864,7 @@ static const struct msm_kms_funcs kms_funcs = { · 14 unmodified lines
818	.round_pixclk = dpu_kms_round_pixclk,	864	.round_pixclk = dpu_kms_round_pixclk,
819	.destroy = dpu_kms_destroy,	865	.destroy = dpu_kms_destroy,
820	.set_encoder_mode = _dpu_kms_set_encoder_mode,	866	.set_encoder_mode = _dpu_kms_set_encoder_mode,
		867	.snapshot = dpu_kms_mdp_snapshot,
821	#ifdef CONFIG_DEBUG_FS	868	#ifdef CONFIG_DEBUG_FS
822	.debugfs_init = dpu_kms_debugfs_init,	869	.debugfs_init = dpu_kms_debugfs_init,
823	#endif	870	#endif
@@ -1089,21 +1136,21 @@ static int dpu_bind(struct device dev, struct device master, void *data) · 265 unmodified lines
1089	if (!dpu_kms)	1136	if (!dpu_kms)
1090	return -ENOMEM;	1137	return -ENOMEM;
1091		1138
1092	dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");	1139	ret = devm_pm_opp_set_clkname(dev, "core");
1093	if (IS_ERR(dpu_kms->opp_table))	1140	if (ret)
1094	return PTR_ERR(dpu_kms->opp_table);	1141	return ret;
1095	/* OPP table is optional */	1142	/* OPP table is optional */
1096	ret = dev_pm_opp_of_add_table(dev);	1143	ret = devm_pm_opp_of_add_table(dev);
1097	if (ret && ret != -ENODEV) {	1144	if (ret && ret != -ENODEV) {
1098	dev_err(dev, "invalid OPP table in device tree\n");	1145	dev_err(dev, "invalid OPP table in device tree\n");
1099	goto put_clkname;	1146	return ret;
1100	}	1147	}
1101		1148
1102	mp = &dpu_kms->mp;	1149	mp = &dpu_kms->mp;
1103	ret = msm_dss_parse_clock(pdev, mp);	1150	ret = msm_dss_parse_clock(pdev, mp);
1104	if (ret) {	1151	if (ret) {
1105	DPU_ERROR("failed to parse clocks, ret=%d\n", ret);	1152	DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1106	goto err;	1153	return ret;
1107	}	1154	}
1108		1155
1109	platform_set_drvdata(pdev, dpu_kms);	1156	platform_set_drvdata(pdev, dpu_kms);
@@ -1111,7 +1158,7 @@ static int dpu_bind(struct device dev, struct device master, void *data) · 1 unmodified line
1111	ret = msm_kms_init(&dpu_kms->base, &kms_funcs);	1158	ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1112	if (ret) {	1159	if (ret) {
1113	DPU_ERROR("failed to init kms, ret=%d\n", ret);	1160	DPU_ERROR("failed to init kms, ret=%d\n", ret);
1114	goto err;	1161	return ret;
1115	}	1162	}
1116	dpu_kms->dev = ddev;	1163	dpu_kms->dev = ddev;
1117	dpu_kms->pdev = pdev;	1164	dpu_kms->pdev = pdev;
@@ -1120,11 +1167,7 @@ static int dpu_bind(struct device dev, struct device master, void *data) · 2 unmodified lines
1120	dpu_kms->rpm_enabled = true;	1167	dpu_kms->rpm_enabled = true;
1121		1168
1122	priv->kms = &dpu_kms->base;	1169	priv->kms = &dpu_kms->base;
1123	return ret;	1170
1124	err:
1125	dev_pm_opp_of_remove_table(dev);
1126	put_clkname:
1127	dev_pm_opp_put_clkname(dpu_kms->opp_table);
1128	return ret;	1171	return ret;
1129	}	1172	}
1130		1173
@@ -1140,9 +1183,6 @@ static void dpu_unbind(struct device dev, struct device master, void *data) · 9 unmodified lines
1140		1183
1141	if (dpu_kms->rpm_enabled)	1184	if (dpu_kms->rpm_enabled)
1142	pm_runtime_disable(&pdev->dev);	1185	pm_runtime_disable(&pdev->dev);
1143
1144	dev_pm_opp_of_remove_table(dev);
1145	dev_pm_opp_put_clkname(dpu_kms->opp_table);
1146	}	1186	}
1147		1187
1148	static const struct component_ops dpu_ops = {	1188	static const struct component_ops dpu_ops = {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h+1−7

  * struct dpu_irq: IRQ structure contains callback registration info
  * @total_irq:    total number of irq_idx obtained from HW interrupts mapping
  * @irq_cb_tbl:   array of IRQ callbacks setting
- * @enable_counts array of IRQ enable counts
- * @cb_lock:      callback lock
  * @debugfs_file: debugfs file for irq statistics
  */
 struct dpu_irq {
 	u32 total_irqs;
 	struct list_head *irq_cb_tbl;
-	atomic_t *enable_counts;
 	atomic_t *irq_counts;
-	spinlock_t cb_lock;
 };
 struct dpu_kms {
 	struct platform_device *pdev;
 	bool rpm_enabled;
-	struct opp_table *opp_table;
 	struct dss_module_power mp;
 	/* reference count bandwidth requests, so we know when we can
 /**
  * dpu_kms_get_clk_rate() - get the clock rate
- * @dpu_kms:  poiner to dpu_kms structure
+ * @dpu_kms:  pointer to dpu_kms structure
  * @clock_name: clock name to get the rate
  *
  * Return: current clock rate

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c+5−3

 	struct msm_drm_private *priv = dev->dev_private;
 	struct dpu_mdss *dpu_mdss;
 	struct dss_module_power *mp;
-	int ret = 0;
+	int ret;
 	int irq;
 	dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
 		goto irq_domain_error;
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
+	if (irq < 0) {
+		ret = irq;
 		goto irq_error;
+	}
 	irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
 					 dpu_mdss);
 	pm_runtime_enable(dev->dev);
-	return ret;
+	return 0;
 irq_error:
 	_dpu_mdss_irq_domain_fini(dpu_mdss);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c+10−13

 #include "dpu_vbif.h"
 #include "dpu_plane.h"
-#define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\
+#define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
 		(pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
 		}
 	}
-	DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
+	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
-			plane->base.id, pdpu->pipe - SSPP_VIG0,
+			pdpu->pipe - SSPP_VIG0,
 			(char *)&fmt->base.pixel_format,
 			src_width, total_fl);
 			(fmt) ? fmt->base.pixel_format : 0,
 			pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
-	DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
+	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
-			plane->base.id,
 			pdpu->pipe - SSPP_VIG0,
 			fmt ? (char *)&fmt->base.pixel_format : NULL,
 			pdpu->is_rt_pipe, total_fl, qos_lut);
 }
 /**
- * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane
+ * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane
  * @plane:		Pointer to drm plane
  * @fb:			Pointer to framebuffer associated with the given plane
  */
 			pdpu->pipe_qos_cfg.danger_lut,
 			pdpu->pipe_qos_cfg.safe_lut);
-	DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
+	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
-		plane->base.id,
 		pdpu->pipe - SSPP_VIG0,
 		fmt ? (char *)&fmt->base.pixel_format : NULL,
 		fmt ? fmt->fetch_mode : -1,
 		pdpu->pipe_qos_cfg.danger_safe_en = false;
 	}
-	DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
+	DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
-		plane->base.id,
 		pdpu->pipe - SSPP_VIG0,
 		pdpu->pipe_qos_cfg.danger_safe_en,
 		pdpu->pipe_qos_cfg.vblank_en,
 }
 /**
- * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane
+ * _dpu_plane_set_qos_remap - set vbif QoS for the given plane
  * @plane:		Pointer to drm plane
  */
 static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
 	qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
 	qos_params.is_rt = pdpu->is_rt_pipe;
-	DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
+	DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
-			plane->base.id, qos_params.num,
+			qos_params.num,
 			qos_params.vbif_idx,
 			qos_params.xin_id, qos_params.is_rt,
 			qos_params.clk_ctrl);

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c+2−2

@@ -162,7 +162,7 @@ int dpu_rm_init(struct dpu_rm *rm, · 161 unmodified lines
162	goto fail;	162	goto fail;
163	}	163	}
164	if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX)	164	if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX)
165	hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0];	165	hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]);
166	rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base;	166	rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base;
167	}	167	}
168		168
@@ -428,7 +428,7 @@ static int _dpu_rm_reserve_ctls( · 259 unmodified lines
428	features = ctl->caps->features;	428	features = ctl->caps->features;
429	has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;	429	has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
430		430
431	DPU_DEBUG("ctl %d caps 0x%lX\n", rm->ctl_blks[j]->id, features);	431	DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
432		432
433	if (needs_split_display != has_split_display)	433	if (needs_split_display != has_split_display)
434	continue;	434	continue;

drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h+18−45

 );
 DECLARE_EVENT_CLASS(dpu_enc_irq_template,
-	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
 		 int irq_idx),
-	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx),
+	TP_ARGS(drm_id, intr_idx, irq_idx),
 	TP_STRUCT__entry(
 		__field(	uint32_t,		drm_id		)
 		__field(	enum dpu_intr_idx,	intr_idx	)
-		__field(	int,			hw_idx		)
 		__field(	int,			irq_idx		)
 	),
 	TP_fast_assign(
 		__entry->drm_id = drm_id;
 		__entry->intr_idx = intr_idx;
-		__entry->hw_idx = hw_idx;
 		__entry->irq_idx = irq_idx;
 	),
-	TP_printk("id=%u, intr=%d, hw=%d, irq=%d",
+	TP_printk("id=%u, intr=%d, irq=%d",
-		  __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
+		  __entry->drm_id, __entry->intr_idx,
 		  __entry->irq_idx)
 );
 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
-	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
 		 int irq_idx),
-	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
+	TP_ARGS(drm_id, intr_idx, irq_idx)
 );
 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
-	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
 		 int irq_idx),
-	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
+	TP_ARGS(drm_id, intr_idx, irq_idx)
 );
 TRACE_EVENT(dpu_enc_irq_wait_success,
-	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
 		 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
-	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
+	TP_ARGS(drm_id, intr_idx, irq_idx, pp_idx, atomic_cnt),
 	TP_STRUCT__entry(
 		__field(	uint32_t,		drm_id		)
 		__field(	enum dpu_intr_idx,	intr_idx	)
-		__field(	int,			hw_idx		)
 		__field(	int,			irq_idx		)
 		__field(	enum dpu_pingpong,	pp_idx		)
 		__field(	int,			atomic_cnt	)
 	TP_fast_assign(
 		__entry->drm_id = drm_id;
 		__entry->intr_idx = intr_idx;
-		__entry->hw_idx = hw_idx;
 		__entry->irq_idx = irq_idx;
 		__entry->pp_idx = pp_idx;
 		__entry->atomic_cnt = atomic_cnt;
 	),
-	TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+	TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d",
-		  __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
+		  __entry->drm_id, __entry->intr_idx,
 		  __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
 );
 );
 TRACE_EVENT(dpu_enc_wait_event_timeout,
-	TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
+	TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
 		 s64 expected_time, int atomic_cnt),
-	TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
+	TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
 	TP_STRUCT__entry(
 		__field(	uint32_t,	drm_id		)
-		__field(	int32_t,	hw_id		)
+		__field(	int,		irq_idx		)
 		__field(	int,		rc		)
 		__field(	s64,		time		)
 		__field(	s64,		expected_time	)
 	),
 	TP_fast_assign(
 		__entry->drm_id = drm_id;
-		__entry->hw_id = hw_id;
+		__entry->irq_idx = irq_idx;
 		__entry->rc = rc;
 		__entry->time = time;
 		__entry->expected_time = expected_time;
 		__entry->atomic_cnt = atomic_cnt;
 	),
-	TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
+	TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
-		  __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
+		  __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
 		  __entry->expected_time, __entry->atomic_cnt)
 );
 	TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
 );
-DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template,
-	TP_PROTO(int irq_idx, int enable_count),
-	TP_ARGS(irq_idx, enable_count),
-	TP_STRUCT__entry(
-		__field(	int,	irq_idx		)
-		__field(	int,	enable_count	)
-	),
-	TP_fast_assign(
-		__entry->irq_idx = irq_idx;
-		__entry->enable_count = enable_count;
-	),
-	TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx,
-		  __entry->enable_count)
-);
-DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx,
-	TP_PROTO(int irq_idx, int enable_count),
-	TP_ARGS(irq_idx, enable_count)
-);
-DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx,
-	TP_PROTO(int irq_idx, int enable_count),
-	TP_ARGS(irq_idx, enable_count)
-);
 DECLARE_EVENT_CLASS(dpu_core_irq_callback_template,
 	TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
 	TP_ARGS(irq_idx, callback),

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c+7−7

@@ -46,7 +46,7 @@ static int _dpu_vbif_wait_for_xin_halt(struct dpu_hw_vbif *vbif, u32 xin_id) · 45 unmodified lines
46	vbif->idx - VBIF_0, xin_id);	46	vbif->idx - VBIF_0, xin_id);
47	} else {	47	} else {
48	rc = 0;	48	rc = 0;
49	DPU_DEBUG("VBIF %d client %d is halted\n",	49	DRM_DEBUG_ATOMIC("VBIF %d client %d is halted\n",
50	vbif->idx - VBIF_0, xin_id);	50	vbif->idx - VBIF_0, xin_id);
51	}	51	}
52		52
@@ -87,7 +87,7 @@ static void _dpu_vbif_apply_dynamic_ot_limit(struct dpu_hw_vbif *vbif, · 34 unmodified lines
87	}	87	}
88	}	88	}
89		89
90	DPU_DEBUG("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n",	90	DRM_DEBUG_ATOMIC("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n",
91	vbif->idx - VBIF_0, params->xin_id,	91	vbif->idx - VBIF_0, params->xin_id,
92	params->width, params->height, params->frame_rate,	92	params->width, params->height, params->frame_rate,
93	pps, *ot_lim);	93	pps, *ot_lim);
@@ -133,7 +133,7 @@ static u32 _dpu_vbif_get_ot_limit(struct dpu_hw_vbif *vbif, · 39 unmodified lines
133	}	133	}
134		134
135	exit:	135	exit:
136	DPU_DEBUG("vbif:%d xin:%d ot_lim:%d\n",	136	DRM_DEBUG_ATOMIC("vbif:%d xin:%d ot_lim:%d\n",
137	vbif->idx - VBIF_0, params->xin_id, ot_lim);	137	vbif->idx - VBIF_0, params->xin_id, ot_lim);
138	return ot_lim;	138	return ot_lim;
139	}	139	}
@@ -163,7 +163,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, · 23 unmodified lines
163	}	163	}
164		164
165	if (!vbif \|\| !mdp) {	165	if (!vbif \|\| !mdp) {
166	DPU_DEBUG("invalid arguments vbif %d mdp %d\n",	166	DRM_DEBUG_ATOMIC("invalid arguments vbif %d mdp %d\n",
167	vbif != NULL, mdp != NULL);	167	vbif != NULL, mdp != NULL);
168	return;	168	return;
169	}	169	}
@@ -230,7 +230,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, · 60 unmodified lines
230	}	230	}
231		231
232	if (!vbif->ops.set_qos_remap \|\| !mdp->ops.setup_clk_force_ctrl) {	232	if (!vbif->ops.set_qos_remap \|\| !mdp->ops.setup_clk_force_ctrl) {
233	DPU_DEBUG("qos remap not supported\n");	233	DRM_DEBUG_ATOMIC("qos remap not supported\n");
234	return;	234	return;
235	}	235	}
236		236
@@ -238,14 +238,14 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, · 1 unmodified line
238	&vbif->cap->qos_nrt_tbl;	238	&vbif->cap->qos_nrt_tbl;
239		239
240	if (!qos_tbl->npriority_lvl \|\| !qos_tbl->priority_lvl) {	240	if (!qos_tbl->npriority_lvl \|\| !qos_tbl->priority_lvl) {
241	DPU_DEBUG("qos tbl not defined\n");	241	DRM_DEBUG_ATOMIC("qos tbl not defined\n");
242	return;	242	return;
243	}	243	}
244		244
245	forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);	245	forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);
246		246
247	for (i = 0; i < qos_tbl->npriority_lvl; i++) {	247	for (i = 0; i < qos_tbl->npriority_lvl; i++) {
248	DPU_DEBUG("vbif:%d xin:%d lvl:%d/%d\n",	248	DRM_DEBUG_ATOMIC("vbif:%d xin:%d lvl:%d/%d\n",
249	params->vbif_idx, params->xin_id, i,	249	params->vbif_idx, params->xin_id, i,
250	qos_tbl->priority_lvl[i]);	250	qos_tbl->priority_lvl[i]);
251	vbif->ops.set_qos_remap(vbif, params->xin_id, i,	251	vbif->ops.set_qos_remap(vbif, params->xin_id, i,

drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h+21−13

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34

drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h+25−13

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34
@@ -80,6 +88,10 @@ enum mdp5_pipe { · 53 unmodified lines
80	SSPP_CURSOR1 = 12,	88	SSPP_CURSOR1 = 12,
81	};	89	};
82		90
		91	enum mdp5_format {
		92	DUMMY = 0,
		93	};
		94
83	enum mdp5_ctl_mode {	95	enum mdp5_ctl_mode {
84	MODE_NONE = 0,	96	MODE_NONE = 0,
85	MODE_WB_0_BLOCK = 1,	97	MODE_WB_0_BLOCK = 1,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c+35−0

 			[3] = INTF_HDMI,
 		},
 	},
+	.perf = {
+		.ab_inefficiency = 200,
+		.ib_inefficiency = 120,
+		.clk_inefficiency = 125
+	},
 	.max_clk = 200000000,
 };
 			[3] = INTF_HDMI,
 		},
 	},
+	.perf = {
+		.ab_inefficiency = 200,
+		.ib_inefficiency = 120,
+		.clk_inefficiency = 125
+	},
 	.max_clk = 320000000,
 };
 			[3] = INTF_HDMI,
 		},
 	},
+	.perf = {
+		.ab_inefficiency = 200,
+		.ib_inefficiency = 120,
+		.clk_inefficiency = 105
+	},
 	.max_clk = 320000000,
 };
 			[1] = INTF_DSI,
 		},
 	},
+	.perf = {
+		.ab_inefficiency = 100,
+		.ib_inefficiency = 200,
+		.clk_inefficiency = 105
+	},
 	.max_clk = 320000000,
 };
 			[2] = INTF_DSI,
 		},
 	},
+	.perf = {
+		.ab_inefficiency = 100,
+		.ib_inefficiency = 200,
+		.clk_inefficiency = 105
+	},
 	.max_clk = 366670000,
 };
 			[3] = INTF_HDMI,
 		},
 	},
+	.perf = {
+		.ab_inefficiency = 100,
+		.ib_inefficiency = 100,
+		.clk_inefficiency = 105
+	},
 	.max_clk = 400000000,
 };
 			[3] = INTF_HDMI,
 		},
 	},
+	.perf = {
+		.ab_inefficiency = 100,
+		.ib_inefficiency = 200,
+		.clk_inefficiency = 105
+	},
 	.max_clk = 412500000,
 };

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h+7−0

 	u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
 };
+struct mdp5_perf_block {
+	u32 ab_inefficiency;
+	u32 ib_inefficiency;
+	u32 clk_inefficiency;
+};
 struct mdp5_cfg_hw {
 	char  *name;
 	struct mdp5_sub_block dsc;
 	struct mdp5_sub_block cdm;
 	struct mdp5_intf_block intf;
+	struct mdp5_perf_block perf;
 	uint32_t max_clk;
 };

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c+7−5

 		plane = pstates[i]->base.plane;
 		blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 			MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
-		fg_alpha = pstates[i]->alpha;
+		fg_alpha = pstates[i]->base.alpha >> 8;
-		bg_alpha = 0xFF - pstates[i]->alpha;
+		bg_alpha = 0xFF - fg_alpha;
 		if (!format->alpha_enable && bg_alpha_enabled)
 			mixer_op_mode = 0;
 		DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
-		if (format->alpha_enable && pstates[i]->premultiplied) {
+		if (format->alpha_enable &&
+		    pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
 			blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 				MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 			if (fg_alpha != 0xff) {
 			} else {
 				blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 			}
-		} else if (format->alpha_enable) {
+		} else if (format->alpha_enable &&
+			   pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
 			blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
 				MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 			if (fg_alpha != 0xff) {
 {
 	struct plane_state *pa = (struct plane_state *)a;
 	struct plane_state *pb = (struct plane_state *)b;
-	return pa->state->zpos - pb->state->zpos;
+	return pa->state->base.normalized_zpos - pb->state->base.normalized_zpos;
 }
 /* is there a helper for this? */

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h+0−5

 	struct mdp5_hw_pipe *hwpipe;
 	struct mdp5_hw_pipe *r_hwpipe;	/* right hwpipe */
-	/* aligned with property */
-	uint8_t premultiplied;
-	uint8_t zpos;
-	uint8_t alpha;
 	/* assigned by crtc blender */
 	enum mdp_mixer_stage_id stage;
 };

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c+19−116

@@ -44,8 +44,9 @@ static void mdp5_plane_destroy(struct drm_plane *plane) · 43 unmodified lines
44	kfree(mdp5_plane);	44	kfree(mdp5_plane);
45	}	45	}
46		46
47	static void mdp5_plane_install_rotation_property(struct drm_device *dev,	47	/* helper to install properties which are common to planes and crtcs */
48	struct drm_plane *plane)	48	static void mdp5_plane_install_properties(struct drm_plane *plane,
		49	struct drm_mode_object *obj)
49	{	50	{
50	drm_plane_create_rotation_property(plane,	51	drm_plane_create_rotation_property(plane,
51	DRM_MODE_ROTATE_0,	52	DRM_MODE_ROTATE_0,
@@ -53,104 +54,12 @@ static void mdp5_plane_install_rotation_property(struct drm_device *dev, · 1 unmodified line
53	DRM_MODE_ROTATE_180 \|	54	DRM_MODE_ROTATE_180 \|
54	DRM_MODE_REFLECT_X \|	55	DRM_MODE_REFLECT_X \|
55	DRM_MODE_REFLECT_Y);	56	DRM_MODE_REFLECT_Y);
56	}	57	drm_plane_create_alpha_property(plane);
57		58	drm_plane_create_blend_mode_property(plane,
58	/* helper to install properties which are common to planes and crtcs */	59	BIT(DRM_MODE_BLEND_PIXEL_NONE) \|
59	static void mdp5_plane_install_properties(struct drm_plane *plane,	60	BIT(DRM_MODE_BLEND_PREMULTI) \|
60	struct drm_mode_object *obj)	61	BIT(DRM_MODE_BLEND_COVERAGE));
61	{	62	drm_plane_create_zpos_property(plane, 1, 1, 255);
62	struct drm_device *dev = plane->dev;
63	struct msm_drm_private *dev_priv = dev->dev_private;
64	struct drm_property *prop;
65
66	#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
67	prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
68	if (!prop) { \
69	prop = drm_property_##fnc(dev, 0, #name, \
70	##__VA_ARGS__); \
71	if (!prop) { \
72	dev_warn(dev->dev, \
73	"Create property %s failed\n", \
74	#name); \
75	return; \
76	} \
77	dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
78	} \
79	drm_object_attach_property(&plane->base, prop, init_val); \
80	} while (0)
81
82	#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
83	INSTALL_PROPERTY(name, NAME, init_val, \
84	create_range, min, max)
85
86	#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
87	INSTALL_PROPERTY(name, NAME, init_val, \
88	create_enum, name##_prop_enum_list, \
89	ARRAY_SIZE(name##_prop_enum_list))
90
91	INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
92
93	mdp5_plane_install_rotation_property(dev, plane);
94
95	#undef INSTALL_RANGE_PROPERTY
96	#undef INSTALL_ENUM_PROPERTY
97	#undef INSTALL_PROPERTY
98	}
99
100	static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
101	struct drm_plane_state state, struct drm_property property,
102	uint64_t val)
103	{
104	struct drm_device *dev = plane->dev;
105	struct mdp5_plane_state *pstate;
106	struct msm_drm_private *dev_priv = dev->dev_private;
107	int ret = 0;
108
109	pstate = to_mdp5_plane_state(state);
110
111	#define SET_PROPERTY(name, NAME, type) do { \
112	if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
113	pstate->name = (type)val; \
114	DBG("Set property %s %d", #name, (type)val); \
115	goto done; \
116	} \
117	} while (0)
118
119	SET_PROPERTY(zpos, ZPOS, uint8_t);
120
121	DRM_DEV_ERROR(dev->dev, "Invalid property\n");
122	ret = -EINVAL;
123	done:
124	return ret;
125	#undef SET_PROPERTY
126	}
127
128	static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
129	const struct drm_plane_state *state,
130	struct drm_property property, uint64_t val)
131	{
132	struct drm_device *dev = plane->dev;
133	struct mdp5_plane_state *pstate;
134	struct msm_drm_private *dev_priv = dev->dev_private;
135	int ret = 0;
136
137	pstate = to_mdp5_plane_state(state);
138
139	#define GET_PROPERTY(name, NAME, type) do { \
140	if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
141	*val = pstate->name; \
142	DBG("Get property %s %lld", #name, *val); \
143	goto done; \
144	} \
145	} while (0)
146
147	GET_PROPERTY(zpos, ZPOS, uint8_t);
148
149	DRM_DEV_ERROR(dev->dev, "Invalid property\n");
150	ret = -EINVAL;
151	done:
152	return ret;
153	#undef SET_PROPERTY
154	}	63	}
155		64
156	static void	65	static void
@@ -166,9 +75,10 @@ mdp5_plane_atomic_print_state(struct drm_printer *p, · 9 unmodified lines
166	drm_printf(p, "\tright-hwpipe=%s\n",	75	drm_printf(p, "\tright-hwpipe=%s\n",
167	pstate->r_hwpipe ? pstate->r_hwpipe->name :	76	pstate->r_hwpipe ? pstate->r_hwpipe->name :
168	"(null)");	77	"(null)");
169	drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);	78	drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode);
170	drm_printf(p, "\tzpos=%u\n", pstate->zpos);	79	drm_printf(p, "\tzpos=%u\n", pstate->base.zpos);
171	drm_printf(p, "\talpha=%u\n", pstate->alpha);	80	drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos);
		81	drm_printf(p, "\talpha=%u\n", pstate->base.alpha);
172	drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));	82	drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
173	}	83	}
174		84
@@ -176,24 +86,19 @@ static void mdp5_plane_reset(struct drm_plane *plane) · 1 unmodified line
176	{	86	{
177	struct mdp5_plane_state *mdp5_state;	87	struct mdp5_plane_state *mdp5_state;
178		88
179	if (plane->state && plane->state->fb)	89	if (plane->state)
180	drm_framebuffer_put(plane->state->fb);	90	__drm_atomic_helper_plane_destroy_state(plane->state);
181		91
182	kfree(to_mdp5_plane_state(plane->state));	92	kfree(to_mdp5_plane_state(plane->state));
183	mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);	93	mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
184		94
185	/* assign default blend parameters */
186	mdp5_state->alpha = 255;
187	mdp5_state->premultiplied = 0;
188
189	if (plane->type == DRM_PLANE_TYPE_PRIMARY)	95	if (plane->type == DRM_PLANE_TYPE_PRIMARY)
190	mdp5_state->zpos = STAGE_BASE;	96	mdp5_state->base.zpos = STAGE_BASE;
191	else	97	else
192	mdp5_state->zpos = STAGE0 + drm_plane_index(plane);	98	mdp5_state->base.zpos = STAGE0 + drm_plane_index(plane);
193		99	mdp5_state->base.normalized_zpos = mdp5_state->base.zpos;
194	mdp5_state->base.plane = plane;
195		100
196	plane->state = &mdp5_state->base;	101	__drm_atomic_helper_plane_reset(plane, &mdp5_state->base);
197	}	102	}
198		103
199	static struct drm_plane_state *	104	static struct drm_plane_state *
@@ -229,8 +134,6 @@ static const struct drm_plane_funcs mdp5_plane_funcs = { · 29 unmodified lines
229	.update_plane = drm_atomic_helper_update_plane,	134	.update_plane = drm_atomic_helper_update_plane,
230	.disable_plane = drm_atomic_helper_disable_plane,	135	.disable_plane = drm_atomic_helper_disable_plane,
231	.destroy = mdp5_plane_destroy,	136	.destroy = mdp5_plane_destroy,
232	.atomic_set_property = mdp5_plane_atomic_set_property,
233	.atomic_get_property = mdp5_plane_atomic_get_property,
234	.reset = mdp5_plane_reset,	137	.reset = mdp5_plane_reset,
235	.atomic_duplicate_state = mdp5_plane_duplicate_state,	138	.atomic_duplicate_state = mdp5_plane_duplicate_state,
236	.atomic_destroy_state = mdp5_plane_destroy_state,	139	.atomic_destroy_state = mdp5_plane_destroy_state,

drivers/gpu/drm/msm/disp/mdp_common.xml.h+21−13

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34

drivers/gpu/drm/msm/disp/msm_disp_snapshot.c+125−0

@@ -0,0 +1,125 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
	7
	8	#include "msm_disp_snapshot.h"
	9
	10	static ssize_t __maybe_unused disp_devcoredump_read(char *buffer, loff_t offset,
	11	size_t count, void *data, size_t datalen)
	12	{
	13	struct drm_print_iterator iter;
	14	struct drm_printer p;
	15	struct msm_disp_state *disp_state;
	16
	17	disp_state = data;
	18
	19	iter.data = buffer;
	20	iter.offset = 0;
	21	iter.start = offset;
	22	iter.remain = count;
	23
	24	p = drm_coredump_printer(&iter);
	25
	26	msm_disp_state_print(disp_state, &p);
	27
	28	return count - iter.remain;
	29	}
	30
	31	static void _msm_disp_snapshot_work(struct kthread_work *work)
	32	{
	33	struct msm_kms *kms = container_of(work, struct msm_kms, dump_work);
	34	struct drm_device *drm_dev = kms->dev;
	35	struct msm_disp_state *disp_state;
	36	struct drm_printer p;
	37
	38	disp_state = kzalloc(sizeof(struct msm_disp_state), GFP_KERNEL);
	39	if (!disp_state)
	40	return;
	41
	42	disp_state->dev = drm_dev->dev;
	43	disp_state->drm_dev = drm_dev;
	44
	45	INIT_LIST_HEAD(&disp_state->blocks);
	46
	47	/* Serialize dumping here */
	48	mutex_lock(&kms->dump_mutex);
	49
	50	msm_disp_snapshot_capture_state(disp_state);
	51
	52	mutex_unlock(&kms->dump_mutex);
	53
	54	if (MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE) {
	55	p = drm_info_printer(disp_state->drm_dev->dev);
	56	msm_disp_state_print(disp_state, &p);
	57	}
	58
	59	/*
	60	* If COREDUMP is disabled, the stub will call the free function.
	61	* If there is a codedump pending for the device, the dev_coredumpm()
	62	* will also free new coredump state.
	63	*/
	64	dev_coredumpm(disp_state->dev, THIS_MODULE, disp_state, 0, GFP_KERNEL,
	65	disp_devcoredump_read, msm_disp_state_free);
	66	}
	67
	68	void msm_disp_snapshot_state(struct drm_device *drm_dev)
	69	{
	70	struct msm_drm_private *priv;
	71	struct msm_kms *kms;
	72
	73	if (!drm_dev) {
	74	DRM_ERROR("invalid params\n");
	75	return;
	76	}
	77
	78	priv = drm_dev->dev_private;
	79	kms = priv->kms;
	80
	81	kthread_queue_work(kms->dump_worker, &kms->dump_work);
	82	}
	83
	84	int msm_disp_snapshot_init(struct drm_device *drm_dev)
	85	{
	86	struct msm_drm_private *priv;
	87	struct msm_kms *kms;
	88
	89	if (!drm_dev) {
	90	DRM_ERROR("invalid params\n");
	91	return -EINVAL;
	92	}
	93
	94	priv = drm_dev->dev_private;
	95	kms = priv->kms;
	96
	97	mutex_init(&kms->dump_mutex);
	98
	99	kms->dump_worker = kthread_create_worker(0, "%s", "disp_snapshot");
	100	if (IS_ERR(kms->dump_worker))
	101	DRM_ERROR("failed to create disp state task\n");
	102
	103	kthread_init_work(&kms->dump_work, _msm_disp_snapshot_work);
	104
	105	return 0;
	106	}
	107
	108	void msm_disp_snapshot_destroy(struct drm_device *drm_dev)
	109	{
	110	struct msm_kms *kms;
	111	struct msm_drm_private *priv;
	112
	113	if (!drm_dev) {
	114	DRM_ERROR("invalid params\n");
	115	return;
	116	}
	117
	118	priv = drm_dev->dev_private;
	119	kms = priv->kms;
	120
	121	if (kms->dump_worker)
	122	kthread_destroy_worker(kms->dump_worker);
	123
	124	mutex_destroy(&kms->dump_mutex);
	125	}

drivers/gpu/drm/msm/disp/msm_disp_snapshot.h+136−0

@@ -0,0 +1,136 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#ifndef MSM_DISP_SNAPSHOT_H_
	7	#define MSM_DISP_SNAPSHOT_H_
	8
	9	#include <drm/drm_atomic_helper.h>
	10	#include <drm/drm_device.h>
	11	#include "../../../drm_crtc_internal.h"
	12	#include <drm/drm_print.h>
	13	#include <drm/drm_atomic.h>
	14	#include <linux/debugfs.h>
	15	#include <linux/list.h>
	16	#include <linux/delay.h>
	17	#include <linux/spinlock.h>
	18	#include <linux/ktime.h>
	19	#include <linux/debugfs.h>
	20	#include <linux/uaccess.h>
	21	#include <linux/dma-buf.h>
	22	#include <linux/slab.h>
	23	#include <linux/list_sort.h>
	24	#include <linux/pm.h>
	25	#include <linux/pm_runtime.h>
	26	#include <linux/kthread.h>
	27	#include <linux/devcoredump.h>
	28	#include <stdarg.h>
	29	#include "msm_kms.h"
	30
	31	#define MSM_DISP_SNAPSHOT_MAX_BLKS 10
	32
	33	/* debug option to print the registers in logs */
	34	#define MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE 0
	35
	36	/* print debug ranges in groups of 4 u32s */
	37	#define REG_DUMP_ALIGN 16
	38
	39	/**
	40	* struct msm_disp_state - structure to store current dpu state
	41	* @dev: device pointer
	42	* @drm_dev: drm device pointer
	43	* @atomic_state: atomic state duplicated at the time of the error
	44	* @timestamp: timestamp at which the coredump was captured
	45	*/
	46	struct msm_disp_state {
	47	struct device *dev;
	48	struct drm_device *drm_dev;
	49
	50	struct list_head blocks;
	51
	52	struct drm_atomic_state *atomic_state;
	53
	54	ktime_t timestamp;
	55	};
	56
	57	/**
	58	* struct msm_disp_state_block - structure to store each hardware block state
	59	* @name: name of the block
	60	* @drm_dev: handle to the linked list head
	61	* @size: size of the register space of this hardware block
	62	* @state: array holding the register dump of this hardware block
	63	* @base_addr: starting address of this hardware block's register space
	64	*/
	65	struct msm_disp_state_block {
	66	char name[SZ_128];
	67	struct list_head node;
	68	unsigned int size;
	69	u32 *state;
	70	void __iomem *base_addr;
	71	};
	72
	73	/**
	74	* msm_disp_snapshot_init - initialize display snapshot
	75	* @drm_dev: drm device handle
	76	*
	77	* Returns: 0 or -ERROR
	78	*/
	79	int msm_disp_snapshot_init(struct drm_device *drm_dev);
	80
	81	/**
	82	* msm_disp_snapshot_destroy - destroy the display snapshot
	83	* @drm_dev: drm device handle
	84	*
	85	* Returns: none
	86	*/
	87	void msm_disp_snapshot_destroy(struct drm_device *drm_dev);
	88
	89	/**
	90	* msm_disp_snapshot_state - trigger to dump the display snapshot
	91	* @drm_dev: handle to drm device
	92
	93	* Returns: none
	94	*/
	95	void msm_disp_snapshot_state(struct drm_device *drm_dev);
	96
	97	/**
	98	* msm_disp_state_print - print out the current dpu state
	99	* @disp_state: handle to drm device
	100	* @p: handle to drm printer
	101	*
	102	* Returns: none
	103	*/
	104	void msm_disp_state_print(struct msm_disp_state disp_state, struct drm_printer p);
	105
	106	/**
	107	* msm_disp_snapshot_capture_state - utility to capture atomic state and hw registers
	108	* @disp_state: handle to msm_disp_state struct
	109
	110	* Returns: none
	111	*/
	112	void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state);
	113
	114	/**
	115	* msm_disp_state_free - free the memory after the coredump has been read
	116	* @data: handle to struct msm_disp_state
	117
	118	* Returns: none
	119	*/
	120	void msm_disp_state_free(void *data);
	121
	122	/**
	123	* msm_disp_snapshot_add_block - add a hardware block with its register dump
	124	* @disp_state: handle to struct msm_disp_state
	125	* @name: name of the hardware block
	126	* @len: size of the register space of the hardware block
	127	* @base_addr: starting address of the register space of the hardware block
	128	* @fmt: format in which the block names need to be printed
	129	*
	130	* Returns: none
	131	*/
	132	__printf(4, 5)
	133	void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len,
	134	void __iomem base_addr, const char fmt, ...);
	135
	136	#endif /* MSM_DISP_SNAPSHOT_H_ */

drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c+187−0

@@ -0,0 +1,187 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
	7
	8	#include "msm_disp_snapshot.h"
	9
	10	static void msm_disp_state_dump_regs(u32 *reg, u32 aligned_len, void __iomem base_addr)
	11	{
	12	u32 len_padded;
	13	u32 num_rows;
	14	u32 x0, x4, x8, xc;
	15	void __iomem *addr;
	16	u32 *dump_addr = NULL;
	17	void __iomem *end_addr;
	18	int i;
	19
	20	len_padded = aligned_len * REG_DUMP_ALIGN;
	21	num_rows = aligned_len / REG_DUMP_ALIGN;
	22
	23	addr = base_addr;
	24	end_addr = base_addr + aligned_len;
	25
	26	if (!(*reg))
	27	*reg = kzalloc(len_padded, GFP_KERNEL);
	28
	29	if (*reg)
	30	dump_addr = *reg;
	31
	32	for (i = 0; i < num_rows; i++) {
	33	x0 = (addr < end_addr) ? readl_relaxed(addr + 0x0) : 0;
	34	x4 = (addr + 0x4 < end_addr) ? readl_relaxed(addr + 0x4) : 0;
	35	x8 = (addr + 0x8 < end_addr) ? readl_relaxed(addr + 0x8) : 0;
	36	xc = (addr + 0xc < end_addr) ? readl_relaxed(addr + 0xc) : 0;
	37
	38	if (dump_addr) {
	39	dump_addr[i * 4] = x0;
	40	dump_addr[i * 4 + 1] = x4;
	41	dump_addr[i * 4 + 2] = x8;
	42	dump_addr[i * 4 + 3] = xc;
	43	}
	44
	45	addr += REG_DUMP_ALIGN;
	46	}
	47	}
	48
	49	static void msm_disp_state_print_regs(u32 *reg, u32 len, void __iomem base_addr,
	50	struct drm_printer *p)
	51	{
	52	int i;
	53	u32 *dump_addr = NULL;
	54	void __iomem *addr;
	55	u32 num_rows;
	56
	57	addr = base_addr;
	58	num_rows = len / REG_DUMP_ALIGN;
	59
	60	if (*reg)
	61	dump_addr = *reg;
	62
	63	for (i = 0; i < num_rows; i++) {
	64	drm_printf(p, "0x%lx : %08x %08x %08x %08x\n",
	65	(unsigned long)(addr - base_addr),
	66	dump_addr[i * 4], dump_addr[i * 4 + 1],
	67	dump_addr[i * 4 + 2], dump_addr[i * 4 + 3]);
	68	addr += REG_DUMP_ALIGN;
	69	}
	70	}
	71
	72	void msm_disp_state_print(struct msm_disp_state state, struct drm_printer p)
	73	{
	74	struct msm_disp_state_block block, tmp;
	75
	76	if (!p) {
	77	DRM_ERROR("invalid drm printer\n");
	78	return;
	79	}
	80
	81	drm_printf(p, "---\n");
	82
	83	drm_printf(p, "module: " KBUILD_MODNAME "\n");
	84	drm_printf(p, "dpu devcoredump\n");
	85	drm_printf(p, "timestamp %lld\n", ktime_to_ns(state->timestamp));
	86
	87	list_for_each_entry_safe(block, tmp, &state->blocks, node) {
	88	drm_printf(p, "====================%s================\n", block->name);
	89	msm_disp_state_print_regs(&block->state, block->size, block->base_addr, p);
	90	}
	91
	92	drm_printf(p, "===================dpu drm state================\n");
	93
	94	if (state->atomic_state)
	95	drm_atomic_print_new_state(state->atomic_state, p);
	96	}
	97
	98	static void msm_disp_capture_atomic_state(struct msm_disp_state *disp_state)
	99	{
	100	struct drm_device *ddev;
	101	struct drm_modeset_acquire_ctx ctx;
	102
	103	disp_state->timestamp = ktime_get();
	104
	105	ddev = disp_state->drm_dev;
	106
	107	drm_modeset_acquire_init(&ctx, 0);
	108
	109	while (drm_modeset_lock_all_ctx(ddev, &ctx) != 0)
	110	drm_modeset_backoff(&ctx);
	111
	112	disp_state->atomic_state = drm_atomic_helper_duplicate_state(ddev,
	113	&ctx);
	114	drm_modeset_drop_locks(&ctx);
	115	drm_modeset_acquire_fini(&ctx);
	116	}
	117
	118	void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state)
	119	{
	120	struct msm_drm_private *priv;
	121	struct drm_device *drm_dev;
	122	struct msm_kms *kms;
	123	int i;
	124
	125	drm_dev = disp_state->drm_dev;
	126	priv = drm_dev->dev_private;
	127	kms = priv->kms;
	128
	129	if (priv->dp)
	130	msm_dp_snapshot(disp_state, priv->dp);
	131
	132	for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
	133	if (!priv->dsi[i])
	134	continue;
	135
	136	msm_dsi_snapshot(disp_state, priv->dsi[i]);
	137	}
	138
	139	if (kms->funcs->snapshot)
	140	kms->funcs->snapshot(disp_state, kms);
	141
	142	msm_disp_capture_atomic_state(disp_state);
	143	}
	144
	145	void msm_disp_state_free(void *data)
	146	{
	147	struct msm_disp_state *disp_state = data;
	148	struct msm_disp_state_block block, tmp;
	149
	150	if (disp_state->atomic_state) {
	151	drm_atomic_state_put(disp_state->atomic_state);
	152	disp_state->atomic_state = NULL;
	153	}
	154
	155	list_for_each_entry_safe(block, tmp, &disp_state->blocks, node) {
	156	list_del(&block->node);
	157	kfree(block->state);
	158	kfree(block);
	159	}
	160
	161	kfree(disp_state);
	162	}
	163
	164	void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len,
	165	void __iomem base_addr, const char fmt, ...)
	166	{
	167	struct msm_disp_state_block *new_blk;
	168	struct va_format vaf;
	169	va_list va;
	170
	171	new_blk = kzalloc(sizeof(struct msm_disp_state_block), GFP_KERNEL);
	172
	173	va_start(va, fmt);
	174
	175	vaf.fmt = fmt;
	176	vaf.va = &va;
	177	snprintf(new_blk->name, sizeof(new_blk->name), "%pV", &vaf);
	178
	179	va_end(va);
	180
	181	INIT_LIST_HEAD(&new_blk->node);
	182	new_blk->size = ALIGN(len, REG_DUMP_ALIGN);
	183	new_blk->base_addr = base_addr;
	184
	185	msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr);
	186	list_add(&new_blk->node, &disp_state->blocks);
	187	}

drivers/gpu/drm/msm/dp/dp_aux.c+78−103

 #include "dp_reg.h"
 #include "dp_aux.h"
-#define DP_AUX_ENUM_STR(x)		#x
+enum msm_dp_aux_err {
+	DP_AUX_ERR_NONE,
+	DP_AUX_ERR_ADDR,
+	DP_AUX_ERR_TOUT,
+	DP_AUX_ERR_NACK,
+	DP_AUX_ERR_DEFER,
+	DP_AUX_ERR_NACK_DEFER,
+	DP_AUX_ERR_PHY,
+};
 struct dp_aux_private {
 	struct device *dev;
 	struct mutex mutex;
 	struct completion comp;
-	u32 aux_error_num;
+	enum msm_dp_aux_err aux_error_num;
 	u32 retry_cnt;
 	bool cmd_busy;
 	bool native;
 	bool no_send_stop;
 	u32 offset;
 	u32 segment;
-	u32 isr;
 	struct drm_dp_aux dp_aux;
 };
 #define MAX_AUX_RETRIES			5
-static const char *dp_aux_get_error(u32 aux_error)
+static ssize_t dp_aux_write(struct dp_aux_private *aux,
-{
-	switch (aux_error) {
-	case DP_AUX_ERR_NONE:
-		return DP_AUX_ENUM_STR(DP_AUX_ERR_NONE);
-	case DP_AUX_ERR_ADDR:
-		return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR);
-	case DP_AUX_ERR_TOUT:
-		return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT);
-	case DP_AUX_ERR_NACK:
-		return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK);
-	case DP_AUX_ERR_DEFER:
-		return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER);
-	case DP_AUX_ERR_NACK_DEFER:
-		return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER);
-	default:
-		return "unknown";
-	}
-}
-static u32 dp_aux_write(struct dp_aux_private *aux,
 			struct drm_dp_aux_msg *msg)
 {
-	u32 data[4], reg, len;
+	u8 data[4];
+	u32 reg;
+	ssize_t len;
 	u8 *msgdata = msg->buffer;
 	int const AUX_CMD_FIFO_LEN = 128;
 	int i = 0;
 	if (aux->read)
-		len = 4;
+		len = 0;
 	else
-		len = msg->size + 4;
+		len = msg->size;
 	/*
 	 * cmd fifo only has depth of 144 bytes
 	 * limit buf length to 128 bytes here
 	 */
-	if (len > AUX_CMD_FIFO_LEN) {
+	if (len > AUX_CMD_FIFO_LEN - 4) {
 		DRM_ERROR("buf size greater than allowed size of 128 bytes\n");
-		return 0;
+		return -EINVAL;
 	}
 	/* Pack cmd and write to HW */
-	data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
+	data[0] = (msg->address >> 16) & 0xf;	/* addr[19:16] */
 	if (aux->read)
-		data[0] |=  BIT(4); /* R/W */
+		data[0] |=  BIT(4);		/* R/W */
-	data[1] = (msg->address >> 8) & 0xff;	/* addr[15:8] */
+	data[1] = msg->address >> 8;		/* addr[15:8] */
-	data[2] = msg->address & 0xff;		/* addr[7:0] */
+	data[2] = msg->address;			/* addr[7:0] */
-	data[3] = (msg->size - 1) & 0xff;	/* len[7:0] */
+	data[3] = msg->size - 1;		/* len[7:0] */
-	for (i = 0; i < len; i++) {
+	for (i = 0; i < len + 4; i++) {
 		reg = (i < 4) ? data[i] : msgdata[i - 4];
+		reg <<= DP_AUX_DATA_OFFSET;
+		reg &= DP_AUX_DATA_MASK;
+		reg |= DP_AUX_DATA_WRITE;
 		/* index = 0, write */
-		reg = (((reg) << DP_AUX_DATA_OFFSET)
-		       & DP_AUX_DATA_MASK) | DP_AUX_DATA_WRITE;
 		if (i == 0)
 			reg |= DP_AUX_DATA_INDEX_WRITE;
 		aux->catalog->aux_data = reg;
 	return len;
 }
-static int dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
+static ssize_t dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
 			      struct drm_dp_aux_msg *msg)
 {
-	u32 ret, len, timeout;
+	ssize_t ret;
-	int aux_timeout_ms = HZ/4;
+	unsigned long time_left;
 	reinit_completion(&aux->comp);
-	len = dp_aux_write(aux, msg);
+	ret = dp_aux_write(aux, msg);
-	if (len == 0) {
+	if (ret < 0)
-		DRM_ERROR("DP AUX write failed\n");
+		return ret;
-		return -EINVAL;
-	}
-	timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms);
+	time_left = wait_for_completion_timeout(&aux->comp,
-	if (!timeout) {
+						msecs_to_jiffies(250));
-		DRM_ERROR("aux %s timeout\n", (aux->read ? "read" : "write"));
+	if (!time_left)
 		return -ETIMEDOUT;
-	}
-	if (aux->aux_error_num == DP_AUX_ERR_NONE) {
-		ret = len;
-	} else {
-		DRM_ERROR_RATELIMITED("aux err: %s\n",
-			dp_aux_get_error(aux->aux_error_num));
-		ret = -EINVAL;
-	}
 	return ret;
 }
-static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
+static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
 		struct drm_dp_aux_msg *msg)
 {
 	u32 data;
 		actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF;
 		if (i != actual_i)
-			DRM_ERROR("Index mismatch: expected %d, found %d\n",
+			break;
-				i, actual_i);
 	}
+	return i;
 }
-static void dp_aux_native_handler(struct dp_aux_private *aux)
+static void dp_aux_native_handler(struct dp_aux_private *aux, u32 isr)
 {
-	u32 isr = aux->isr;
 	if (isr & DP_INTR_AUX_I2C_DONE)
 		aux->aux_error_num = DP_AUX_ERR_NONE;
 	else if (isr & DP_INTR_WRONG_ADDR)
 		aux->aux_error_num = DP_AUX_ERR_PHY;
 		dp_catalog_aux_clear_hw_interrupts(aux->catalog);
 	}
-	complete(&aux->comp);
 }
-static void dp_aux_i2c_handler(struct dp_aux_private *aux)
+static void dp_aux_i2c_handler(struct dp_aux_private *aux, u32 isr)
 {
-	u32 isr = aux->isr;
 	if (isr & DP_INTR_AUX_I2C_DONE) {
 		if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER))
 			aux->aux_error_num = DP_AUX_ERR_NACK;
 			dp_catalog_aux_clear_hw_interrupts(aux->catalog);
 		}
 	}
-	complete(&aux->comp);
 }
 static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux,
 	ssize_t ret;
 	int const aux_cmd_native_max = 16;
 	int const aux_cmd_i2c_max = 128;
-	struct dp_aux_private *aux = container_of(dp_aux,
+	struct dp_aux_private *aux;
-		struct dp_aux_private, dp_aux);
-	mutex_lock(&aux->mutex);
+	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
 	aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
 	/* Ignore address only message */
-	if ((msg->size == 0) || (msg->buffer == NULL)) {
+	if (msg->size == 0 || !msg->buffer) {
 		msg->reply = aux->native ?
 			DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
-		ret = msg->size;
+		return msg->size;
-		goto unlock_exit;
 	}
 	/* msg sanity check */
-	if ((aux->native && (msg->size > aux_cmd_native_max)) ||
+	if ((aux->native && msg->size > aux_cmd_native_max) ||
-		(msg->size > aux_cmd_i2c_max)) {
+	    msg->size > aux_cmd_i2c_max) {
 		DRM_ERROR("%s: invalid msg: size(%zu), request(%x)\n",
 			__func__, msg->size, msg->request);
-		ret = -EINVAL;
+		return -EINVAL;
-		goto unlock_exit;
 	}
+	mutex_lock(&aux->mutex);
 	dp_aux_update_offset_and_segment(aux, msg);
 	dp_aux_transfer_helper(aux, msg, true);
 	}
 	ret = dp_aux_cmd_fifo_tx(aux, msg);
 	if (ret < 0) {
 		if (aux->native) {
 			aux->retry_cnt++;
 			if (!(aux->retry_cnt % MAX_AUX_RETRIES))
 				dp_catalog_aux_update_cfg(aux->catalog);
 		}
-		usleep_range(400, 500); /* at least 400us to next try */
-		goto unlock_exit;
-	}
-	if (aux->aux_error_num == DP_AUX_ERR_NONE) {
-		if (aux->read)
-			dp_aux_cmd_fifo_rx(aux, msg);
-		msg->reply = aux->native ?
-			DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
 	} else {
-		/* Reply defer to retry */
+		aux->retry_cnt = 0;
-		msg->reply = aux->native ?
+		switch (aux->aux_error_num) {
-			DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
+		case DP_AUX_ERR_NONE:
+			if (aux->read)
+				ret = dp_aux_cmd_fifo_rx(aux, msg);
+			msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
+			break;
+		case DP_AUX_ERR_DEFER:
+			msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
+			break;
+		case DP_AUX_ERR_PHY:
+		case DP_AUX_ERR_ADDR:
+		case DP_AUX_ERR_NACK:
+		case DP_AUX_ERR_NACK_DEFER:
+			msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_NACK : DP_AUX_I2C_REPLY_NACK;
+			break;
+		case DP_AUX_ERR_TOUT:
+			ret = -ETIMEDOUT;
+			break;
+		}
 	}
-	/* Return requested size for success or retry */
-	ret = msg->size;
-	aux->retry_cnt = 0;
-unlock_exit:
 	aux->cmd_busy = false;
 	mutex_unlock(&aux->mutex);
 	return ret;
 }
 void dp_aux_isr(struct drm_dp_aux *dp_aux)
 {
+	u32 isr;
 	struct dp_aux_private *aux;
 	if (!dp_aux) {
 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
-	aux->isr = dp_catalog_aux_get_irq(aux->catalog);
+	isr = dp_catalog_aux_get_irq(aux->catalog);
 	if (!aux->cmd_busy)
 		return;
 	if (aux->native)
-		dp_aux_native_handler(aux);
+		dp_aux_native_handler(aux, isr);
 	else
-		dp_aux_i2c_handler(aux);
+		dp_aux_i2c_handler(aux, isr);
+	complete(&aux->comp);
 }
 void dp_aux_reconfig(struct drm_dp_aux *dp_aux)

drivers/gpu/drm/msm/dp/dp_aux.h+0−8

@@ -9,14 +9,6 @@ · 8 unmodified lines
9	#include "dp_catalog.h"	9	#include "dp_catalog.h"
10	#include <drm/drm_dp_helper.h>	10	#include <drm/drm_dp_helper.h>
11		11
12	#define DP_AUX_ERR_NONE 0
13	#define DP_AUX_ERR_ADDR -1
14	#define DP_AUX_ERR_TOUT -2
15	#define DP_AUX_ERR_NACK -3
16	#define DP_AUX_ERR_DEFER -4
17	#define DP_AUX_ERR_NACK_DEFER -5
18	#define DP_AUX_ERR_PHY -6
19
20	int dp_aux_register(struct drm_dp_aux *dp_aux);	12	int dp_aux_register(struct drm_dp_aux *dp_aux);
21	void dp_aux_unregister(struct drm_dp_aux *dp_aux);	13	void dp_aux_unregister(struct drm_dp_aux *dp_aux);
22	void dp_aux_isr(struct drm_dp_aux *dp_aux);	14	void dp_aux_isr(struct drm_dp_aux *dp_aux);

drivers/gpu/drm/msm/dp/dp_catalog.c+13−5

 	u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX];
 };
+void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state)
+{
+	struct dp_catalog_private *catalog = container_of(dp_catalog,
+			struct dp_catalog_private, dp_catalog);
+	msm_disp_snapshot_add_block(disp_state, catalog->io->dp_controller.len,
+			catalog->io->dp_controller.base, "dp_ctrl");
+}
 static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset)
 {
 	offset += MSM_DP_CONTROLLER_AUX_OFFSET;
 /**
  * dp_catalog_aux_reset() - reset AUX controller
  *
- * @aux: DP catalog structure
+ * @dp_catalog: DP catalog structure
  *
  * return: void
  *
 	dump_regs(catalog->io->dp_controller.base + offset, len);
 }
-int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
+u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
 {
 	struct dp_catalog_private *catalog = container_of(dp_catalog,
 				struct dp_catalog_private, dp_catalog);
 	u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
-	/* enable HPD interrupts */
+	/* enable HPD plug and unplug interrupts */
 	dp_catalog_hpd_config_intr(dp_catalog,
-		DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK
+		DP_DP_HPD_PLUG_INT_MASK | DP_DP_HPD_UNPLUG_INT_MASK, true);
-		| DP_DP_HPD_UNPLUG_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true);
 	/* Configure REFTIMER and enable it */
 	reftimer |= DP_DP_HPD_REFTIMER_ENABLE;

drivers/gpu/drm/msm/dp/dp_catalog.h+5−2

 #include <drm/drm_modes.h>
 #include "dp_parser.h"
+#include "disp/msm_disp_snapshot.h"
 /* interrupts */
 #define DP_INTR_HPD		BIT(0)
 	u32 audio_data;
 };
+/* Debug module */
+void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state);
 /* AUX APIs */
 u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog);
 int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog);
 void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
 void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
 void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog);
-int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
+u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
 /* DP Controller APIs */
 void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
 void dp_catalog_audio_set_header(struct dp_catalog *catalog);
 void dp_catalog_audio_config_acr(struct dp_catalog *catalog);
 void dp_catalog_audio_enable(struct dp_catalog *catalog);
-void dp_catalog_audio_enable(struct dp_catalog *catalog);
 void dp_catalog_audio_config_sdp(struct dp_catalog *catalog);
 void dp_catalog_audio_init(struct dp_catalog *catalog);
 void dp_catalog_audio_sfe_level(struct dp_catalog *catalog);

drivers/gpu/drm/msm/dp/dp_ctrl.c+63−24

@@ -77,8 +77,6 @@ struct dp_ctrl_private { · 76 unmodified lines
77	struct dp_parser *parser;	77	struct dp_parser *parser;
78	struct dp_catalog *catalog;	78	struct dp_catalog *catalog;
79		79
80	struct opp_table *opp_table;
81
82	struct completion idle_comp;	80	struct completion idle_comp;
83	struct completion video_comp;	81	struct completion video_comp;
84	};	82	};
@@ -1809,6 +1807,63 @@ end: · 1724 unmodified lines
1809	return ret;	1807	return ret;
1810	}	1808	}
1811		1809
		1810	int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
		1811	{
		1812	struct dp_ctrl_private *ctrl;
		1813	struct dp_io *dp_io;
		1814	struct phy *phy;
		1815	int ret;
		1816
		1817	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
		1818	dp_io = &ctrl->parser->io;
		1819	phy = dp_io->phy;
		1820
		1821	/* set dongle to D3 (power off) mode */
		1822	dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
		1823
		1824	dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
		1825
		1826	if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
		1827	ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
		1828	if (ret) {
		1829	DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
		1830	return ret;
		1831	}
		1832	}
		1833
		1834	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
		1835	if (ret) {
		1836	DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
		1837	return ret;
		1838	}
		1839
		1840	phy_power_off(phy);
		1841
		1842	/* aux channel down, reinit phy */
		1843	phy_exit(phy);
		1844	phy_init(phy);
		1845
		1846	DRM_DEBUG_DP("DP off link/stream done\n");
		1847	return ret;
		1848	}
		1849
		1850	void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl)
		1851	{
		1852	struct dp_ctrl_private *ctrl;
		1853	struct dp_io *dp_io;
		1854	struct phy *phy;
		1855
		1856	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
		1857	dp_io = &ctrl->parser->io;
		1858	phy = dp_io->phy;
		1859
		1860	dp_catalog_ctrl_reset(ctrl->catalog);
		1861
		1862	phy_exit(phy);
		1863
		1864	DRM_DEBUG_DP("DP off phy done\n");
		1865	}
		1866
1812	int dp_ctrl_off(struct dp_ctrl *dp_ctrl)	1867	int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
1813	{	1868	{
1814	struct dp_ctrl_private *ctrl;	1869	struct dp_ctrl_private *ctrl;
@@ -1886,20 +1941,17 @@ struct dp_ctrl dp_ctrl_get(struct device dev, struct dp_link *link, · 71 unmodified lines
1886	return ERR_PTR(-ENOMEM);	1941	return ERR_PTR(-ENOMEM);
1887	}	1942	}
1888		1943
1889	ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link");	1944	ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
1890	if (IS_ERR(ctrl->opp_table)) {	1945	if (ret) {
1891	dev_err(dev, "invalid DP OPP table in device tree\n");	1946	dev_err(dev, "invalid DP OPP table in device tree\n");
1892	/* caller do PTR_ERR(ctrl->opp_table) */	1947	/* caller do PTR_ERR(opp_table) */
1893	return (struct dp_ctrl *)ctrl->opp_table;	1948	return (struct dp_ctrl *)ERR_PTR(ret);
1894	}	1949	}
1895		1950
1896	/* OPP table is optional */	1951	/* OPP table is optional */
1897	ret = dev_pm_opp_of_add_table(dev);	1952	ret = devm_pm_opp_of_add_table(dev);
1898	if (ret) {	1953	if (ret)
1899	dev_err(dev, "failed to add DP OPP table\n");	1954	dev_err(dev, "failed to add DP OPP table\n");
1900	dev_pm_opp_put_clkname(ctrl->opp_table);
1901	ctrl->opp_table = NULL;
1902	}
1903		1955
1904	init_completion(&ctrl->idle_comp);	1956	init_completion(&ctrl->idle_comp);
1905	init_completion(&ctrl->video_comp);	1957	init_completion(&ctrl->video_comp);
@@ -1915,16 +1967,3 @@ struct dp_ctrl dp_ctrl_get(struct device dev, struct dp_link *link, · 9 unmodified lines
1915		1967
1916	return &ctrl->dp_ctrl;	1968	return &ctrl->dp_ctrl;
1917	}	1969	}
1918
1919	void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
1920	{
1921	struct dp_ctrl_private *ctrl;
1922
1923	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1924
1925	if (ctrl->opp_table) {
1926	dev_pm_opp_of_remove_table(ctrl->dev);
1927	dev_pm_opp_put_clkname(ctrl->opp_table);
1928	ctrl->opp_table = NULL;
1929	}
1930	}

drivers/gpu/drm/msm/dp/dp_ctrl.h+2−1

 void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl);
 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);
 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl);
+int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);
+void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl);
 int dp_ctrl_off(struct dp_ctrl *dp_ctrl);
 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl);
 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl);
 			struct dp_panel *panel,	struct drm_dp_aux *aux,
 			struct dp_power *power, struct dp_catalog *catalog,
 			struct dp_parser *parser);
-void dp_ctrl_put(struct dp_ctrl *dp_ctrl);
 #endif /* _DP_CTRL_H_ */

drivers/gpu/drm/msm/dp/dp_display.c+76−45

@@ -208,10 +208,6 @@ static int dp_display_bind(struct device dev, struct device master, · 207 unmodified lines
208		208
209	dp = container_of(g_dp_display,	209	dp = container_of(g_dp_display,
210	struct dp_display_private, dp_display);	210	struct dp_display_private, dp_display);
211	if (!dp) {
212	DRM_ERROR("DP driver bind failed. Invalid driver data\n");
213	return -EINVAL;
214	}
215		211
216	dp->dp_display.drm_dev = drm;	212	dp->dp_display.drm_dev = drm;
217	priv = drm->dev_private;	213	priv = drm->dev_private;
@@ -252,10 +248,6 @@ static void dp_display_unbind(struct device dev, struct device master, · 34 unmodified lines
252		248
253	dp = container_of(g_dp_display,	249	dp = container_of(g_dp_display,
254	struct dp_display_private, dp_display);	250	struct dp_display_private, dp_display);
255	if (!dp) {
256	DRM_ERROR("Invalid DP driver data\n");
257	return;
258	}
259		251
260	dp_power_client_deinit(dp->power);	252	dp_power_client_deinit(dp->power);
261	dp_aux_unregister(dp->aux);	253	dp_aux_unregister(dp->aux);
@@ -346,6 +338,12 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) · 84 unmodified lines
346	dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;	338	dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;
347	dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes;	339	dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes;
348		340
		341	/*
		342	* set sink to normal operation mode -- D0
		343	* before dpcd read
		344	*/
		345	dp_link_psm_config(dp->link, &dp->panel->link_info, false);
		346
349	dp_link_reset_phy_params_vx_px(dp->link);	347	dp_link_reset_phy_params_vx_px(dp->link);
350	rc = dp_ctrl_on_link(dp->ctrl);	348	rc = dp_ctrl_on_link(dp->ctrl);
351	if (rc) {	349	if (rc) {
@@ -406,19 +404,9 @@ static int dp_display_usbpd_configure_cb(struct device *dev) · 54 unmodified lines
406		404
407	dp = container_of(g_dp_display,	405	dp = container_of(g_dp_display,
408	struct dp_display_private, dp_display);	406	struct dp_display_private, dp_display);
409	if (!dp) {
410	DRM_ERROR("no driver data found\n");
411	rc = -ENODEV;
412	goto end;
413	}
414		407
415	dp_display_host_init(dp, false);	408	dp_display_host_init(dp, false);
416		409
417	/*
418	* set sink to normal operation mode -- D0
419	* before dpcd read
420	*/
421	dp_link_psm_config(dp->link, &dp->panel->link_info, false);
422	rc = dp_display_process_hpd_high(dp);	410	rc = dp_display_process_hpd_high(dp);
423	end:	411	end:
424	return rc;	412	return rc;
@@ -437,11 +425,6 @@ static int dp_display_usbpd_disconnect_cb(struct device *dev) · 12 unmodified lines
437		425
438	dp = container_of(g_dp_display,	426	dp = container_of(g_dp_display,
439	struct dp_display_private, dp_display);	427	struct dp_display_private, dp_display);
440	if (!dp) {
441	DRM_ERROR("no driver data found\n");
442	rc = -ENODEV;
443	return rc;
444	}
445		428
446	dp_add_event(dp, EV_USER_NOTIFICATION, false, 0);	429	dp_add_event(dp, EV_USER_NOTIFICATION, false, 0);
447		430
@@ -502,7 +485,6 @@ static int dp_display_usbpd_attention_cb(struct device *dev) · 54 unmodified lines
502	int rc = 0;	485	int rc = 0;
503	u32 sink_request;	486	u32 sink_request;
504	struct dp_display_private *dp;	487	struct dp_display_private *dp;
505	struct dp_usbpd *hpd;
506		488
507	if (!dev) {	489	if (!dev) {
508	DRM_ERROR("invalid dev\n");	490	DRM_ERROR("invalid dev\n");
@@ -511,12 +493,6 @@ static int dp_display_usbpd_attention_cb(struct device *dev) · 2 unmodified lines
511		493
512	dp = container_of(g_dp_display,	494	dp = container_of(g_dp_display,
513	struct dp_display_private, dp_display);	495	struct dp_display_private, dp_display);
514	if (!dp) {
515	DRM_ERROR("no driver data found\n");
516	return -ENODEV;
517	}
518
519	hpd = dp->usbpd;
520		496
521	/* check for any test request issued by sink */	497	/* check for any test request issued by sink */
522	rc = dp_link_process_request(dp->link);	498	rc = dp_link_process_request(dp->link);
@@ -579,6 +555,10 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) · 56 unmodified lines
579	dp_add_event(dp, EV_CONNECT_PENDING_TIMEOUT, 0, tout);	555	dp_add_event(dp, EV_CONNECT_PENDING_TIMEOUT, 0, tout);
580	}	556	}
581		557
		558	/* enable HDP irq_hpd/replug interrupt */
		559	dp_catalog_hpd_config_intr(dp->catalog,
		560	DP_DP_IRQ_HPD_INT_MASK \| DP_DP_HPD_REPLUG_INT_MASK, true);
		561
582	mutex_unlock(&dp->event_mutex);	562	mutex_unlock(&dp->event_mutex);
583		563
584	/* uevent will complete connection part */	564	/* uevent will complete connection part */
@@ -628,7 +608,26 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) · 43 unmodified lines
628	mutex_lock(&dp->event_mutex);	608	mutex_lock(&dp->event_mutex);
629		609
630	state = dp->hpd_state;	610	state = dp->hpd_state;
631	if (state == ST_DISCONNECT_PENDING \|\| state == ST_DISCONNECTED) {	611
		612	/* disable irq_hpd/replug interrupts */
		613	dp_catalog_hpd_config_intr(dp->catalog,
		614	DP_DP_IRQ_HPD_INT_MASK \| DP_DP_HPD_REPLUG_INT_MASK, false);
		615
		616	/* unplugged, no more irq_hpd handle */
		617	dp_del_event(dp, EV_IRQ_HPD_INT);
		618
		619	if (state == ST_DISCONNECTED) {
		620	/* triggered by irq_hdp with sink_count = 0 */
		621	if (dp->link->sink_count == 0) {
		622	dp_ctrl_off_phy(dp->ctrl);
		623	hpd->hpd_high = 0;
		624	dp->core_initialized = false;
		625	}
		626	mutex_unlock(&dp->event_mutex);
		627	return 0;
		628	}
		629
		630	if (state == ST_DISCONNECT_PENDING) {
632	mutex_unlock(&dp->event_mutex);	631	mutex_unlock(&dp->event_mutex);
633	return 0;	632	return 0;
634	}	633	}
@@ -642,9 +641,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) · 7 unmodified lines
642		641
643	dp->hpd_state = ST_DISCONNECT_PENDING;	642	dp->hpd_state = ST_DISCONNECT_PENDING;
644		643
645	/* disable HPD plug interrupt until disconnect is done */	644	/* disable HPD plug interrupts */
646	dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK	645	dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false);
647	\| DP_DP_IRQ_HPD_INT_MASK, false);
648		646
649	hpd->hpd_high = 0;	647	hpd->hpd_high = 0;
650		648
@@ -660,8 +658,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) · 9 unmodified lines
660	/* signal the disconnect event early to ensure proper teardown */	658	/* signal the disconnect event early to ensure proper teardown */
661	dp_display_handle_plugged_change(g_dp_display, false);	659	dp_display_handle_plugged_change(g_dp_display, false);
662		660
663	dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK \|	661	/* enable HDP plug interrupt to prepare for next plugin */
664	DP_DP_IRQ_HPD_INT_MASK, true);	662	dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, true);
665		663
666	/* uevent will complete disconnection part */	664	/* uevent will complete disconnection part */
667	mutex_unlock(&dp->event_mutex);	665	mutex_unlock(&dp->event_mutex);
@@ -692,7 +690,7 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) · 24 unmodified lines
692		690
693	/* irq_hpd can happen at either connected or disconnected state */	691	/* irq_hpd can happen at either connected or disconnected state */
694	state = dp->hpd_state;	692	state = dp->hpd_state;
695	if (state == ST_DISPLAY_OFF) {	693	if (state == ST_DISPLAY_OFF \|\| state == ST_SUSPENDED) {
696	mutex_unlock(&dp->event_mutex);	694	mutex_unlock(&dp->event_mutex);
697	return 0;	695	return 0;
698	}	696	}
@@ -724,7 +722,6 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) · 25 unmodified lines
724	static void dp_display_deinit_sub_modules(struct dp_display_private *dp)	722	static void dp_display_deinit_sub_modules(struct dp_display_private *dp)
725	{	723	{
726	dp_debug_put(dp->debug);	724	dp_debug_put(dp->debug);
727	dp_ctrl_put(dp->ctrl);
728	dp_panel_put(dp->panel);	725	dp_panel_put(dp->panel);
729	dp_aux_put(dp->aux);	726	dp_aux_put(dp->aux);
730	dp_audio_put(dp->audio);	727	dp_audio_put(dp->audio);
@@ -818,13 +815,11 @@ static int dp_init_sub_modules(struct dp_display_private *dp) · 87 unmodified lines
818	rc = PTR_ERR(dp->audio);	815	rc = PTR_ERR(dp->audio);
819	pr_err("failed to initialize audio, rc = %d\n", rc);	816	pr_err("failed to initialize audio, rc = %d\n", rc);
820	dp->audio = NULL;	817	dp->audio = NULL;
821	goto error_audio;	818	goto error_ctrl;
822	}	819	}
823		820
824	return rc;	821	return rc;
825		822
826	error_audio:
827	dp_ctrl_put(dp->ctrl);
828	error_ctrl:	823	error_ctrl:
829	dp_panel_put(dp->panel);	824	dp_panel_put(dp->panel);
830	error_link:	825	error_link:
@@ -910,9 +905,13 @@ static int dp_display_disable(struct dp_display_private *dp, u32 data) · 79 unmodified lines
910		905
911	dp_display->audio_enabled = false;	906	dp_display->audio_enabled = false;
912		907
913	dp_ctrl_off(dp->ctrl);	908	/* triggered by irq_hpd with sink_count = 0 */
914		909	if (dp->link->sink_count == 0) {
915	dp->core_initialized = false;	910	dp_ctrl_off_link_stream(dp->ctrl);
		911	} else {
		912	dp_ctrl_off(dp->ctrl);
		913	dp->core_initialized = false;
		914	}
916		915
917	dp_display->power_on = false;	916	dp_display->power_on = false;
918		917
@@ -1012,6 +1011,33 @@ int dp_display_get_test_bpp(struct msm_dp *dp) · 93 unmodified lines
1012	dp_display->link->test_video.test_bit_depth);	1011	dp_display->link->test_video.test_bit_depth);
1013	}	1012	}
1014		1013
		1014	void msm_dp_snapshot(struct msm_disp_state disp_state, struct msm_dp dp)
		1015	{
		1016	struct dp_display_private *dp_display;
		1017	struct drm_device *drm;
		1018
		1019	dp_display = container_of(dp, struct dp_display_private, dp_display);
		1020	drm = dp->drm_dev;
		1021
		1022	/*
		1023	* if we are reading registers we need the link clocks to be on
		1024	* however till DP cable is connected this will not happen as we
		1025	* do not know the resolution to power up with. Hence check the
		1026	* power_on status before dumping DP registers to avoid crash due
		1027	* to unclocked access
		1028	*/
		1029	mutex_lock(&dp_display->event_mutex);
		1030
		1031	if (!dp->power_on) {
		1032	mutex_unlock(&dp_display->event_mutex);
		1033	return;
		1034	}
		1035
		1036	dp_catalog_snapshot(dp_display->catalog, disp_state);
		1037
		1038	mutex_unlock(&dp_display->event_mutex);
		1039	}
		1040
1015	static void dp_display_config_hpd(struct dp_display_private *dp)	1041	static void dp_display_config_hpd(struct dp_display_private *dp)
1016	{	1042	{
1017		1043
@@ -1300,8 +1326,13 @@ static int dp_pm_suspend(struct device *dev) · 282 unmodified lines
1300		1326
1301	mutex_lock(&dp->event_mutex);	1327	mutex_lock(&dp->event_mutex);
1302		1328
1303	if (dp->core_initialized == true)	1329	if (dp->core_initialized == true) {
		1330	/* mainlink enabled */
		1331	if (dp_power_clk_status(dp->power, DP_CTRL_PM))
		1332	dp_ctrl_off_link_stream(dp->ctrl);
		1333
1304	dp_display_host_deinit(dp);	1334	dp_display_host_deinit(dp);
		1335	}
1305		1336
1306	dp->hpd_state = ST_SUSPENDED;	1337	dp->hpd_state = ST_SUSPENDED;
1307		1338

drivers/gpu/drm/msm/dp/dp_display.h+1−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8		8
9	#include "dp_panel.h"	9	#include "dp_panel.h"
10	#include <sound/hdmi-codec.h>	10	#include <sound/hdmi-codec.h>
		11	#include "disp/msm_disp_snapshot.h"
11		12
12	struct msm_dp {	13	struct msm_dp {
13	struct drm_device *drm_dev;	14	struct drm_device *drm_dev;

drivers/gpu/drm/msm/dp/dp_link.c+6−15

 }
 /**
- * dp_parse_video_pattern_params() - parses video pattern parameters from DPCD
+ * dp_link_parse_video_pattern_params() - parses video pattern parameters from DPCD
  * @link: Display Port Driver data
  *
  * Returns 0 if it successfully parses the video link pattern and the link
 }
 /**
- * dp_parse_phy_test_params() - parses the phy link parameters
+ * dp_link_parse_phy_test_params() - parses the phy link parameters
  * @link: Display Port Driver data
  *
  * Parses the DPCD (Byte 0x248) for the DP PHY link pattern that is being
 	return ret == 1;
 }
-static int dp_link_parse_vx_px(struct dp_link_private *link)
+static void dp_link_parse_vx_px(struct dp_link_private *link)
 {
-	int ret = 0;
 	DRM_DEBUG_DP("vx: 0=%d, 1=%d, 2=%d, 3=%d\n",
 		drm_dp_get_adjust_request_voltage(link->link_status, 0),
 		drm_dp_get_adjust_request_voltage(link->link_status, 1),
 	DRM_DEBUG_DP("Requested: v_level = 0x%x, p_level = 0x%x\n",
 			link->dp_link.phy_params.v_level,
 			link->dp_link.phy_params.p_level);
-	return ret;
 }
 /**
 static int dp_link_process_phy_test_pattern_request(
 		struct dp_link_private *link)
 {
-	int ret = 0;
 	if (!(link->request.test_requested & DP_TEST_LINK_PHY_TEST_PATTERN)) {
 		DRM_DEBUG_DP("no phy test\n");
 		return -EINVAL;
 	link->dp_link.link_params.rate =
 		drm_dp_bw_code_to_link_rate(link->request.test_link_rate);
-	ret = dp_link_parse_vx_px(link);
+	dp_link_parse_vx_px(link);
-	if (ret)
-		DRM_ERROR("parse_vx_px failed. ret=%d\n", ret);
-	return ret;
+	return 0;
 }
 static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
 }
 /**
- * dp_link_process_downstream_port_status_change() - process port status changes
+ * dp_link_process_ds_port_status_change() - process port status changes
  * @link: Display Port Driver data
  *
  * This function will handle downstream port updates that are initiated by

drivers/gpu/drm/msm/dp/dp_panel.c+1−3

 			return rc;
 		}
 		rc = drm_add_edid_modes(connector, edid);
-		DRM_DEBUG_DP("%s -", __func__);
 		return rc;
 	}
 int dp_panel_timing_cfg(struct dp_panel *dp_panel)
 {
-	int rc = 0;
 	u32 data, total_ver, total_hor;
 	struct dp_catalog *catalog;
 	struct dp_panel_private *panel;
 	dp_catalog_panel_timing_cfg(catalog);
 	panel->panel_on = true;
-	return rc;
+	return 0;
 }
 int dp_panel_init_panel_info(struct dp_panel *dp_panel)

drivers/gpu/drm/msm/dp/dp_power.h+2−2

@@ -88,7 +88,7 @@ int dp_power_client_init(struct dp_power *power); · 87 unmodified lines
88	* return: 0 for success, error for failure.	88	* return: 0 for success, error for failure.
89	*	89	*
90	* This API will de-initialize the DisplayPort's clocks and regulator	90	* This API will de-initialize the DisplayPort's clocks and regulator
91	* modueles.	91	* modules.
92	*/	92	*/
93	void dp_power_client_deinit(struct dp_power *power);	93	void dp_power_client_deinit(struct dp_power *power);
94		94
@@ -100,7 +100,7 @@ void dp_power_client_deinit(struct dp_power *power); · 5 unmodified lines
100	*	100	*
101	* This API will configure the DisplayPort's power module and provides	101	* This API will configure the DisplayPort's power module and provides
102	* methods to be called by the client to configure the power related	102	* methods to be called by the client to configure the power related
103	* modueles.	103	* modules.
104	*/	104	*/
105	struct dp_power dp_power_get(struct device dev, struct dp_parser *parser);	105	struct dp_power dp_power_get(struct device dev, struct dp_parser *parser);
106		106

drivers/gpu/drm/msm/dsi/dsi.c+6−0

@@ -266,3 +266,9 @@ fail: · 265 unmodified lines
266	return ret;	266	return ret;
267	}	267	}
268		268
		269	void msm_dsi_snapshot(struct msm_disp_state disp_state, struct msm_dsi msm_dsi)
		270	{
		271	msm_dsi_host_snapshot(disp_state, msm_dsi->host);
		272	msm_dsi_phy_snapshot(disp_state, msm_dsi->phy);
		273	}
		274

drivers/gpu/drm/msm/dsi/dsi.h+3−1

@@ -15,6 +15,7 @@ · 14 unmodified lines
15	#include <drm/drm_panel.h>	15	#include <drm/drm_panel.h>
16		16
17	#include "msm_drv.h"	17	#include "msm_drv.h"
		18	#include "disp/msm_disp_snapshot.h"
18		19
19	#define DSI_0 0	20	#define DSI_0 0
20	#define DSI_1 1	21	#define DSI_1 1
@@ -146,7 +147,7 @@ int dsi_clk_init_v2(struct msm_dsi_host *msm_host); · 125 unmodified lines
146	int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);	147	int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
147	int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi);	148	int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi);
148	int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi);	149	int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi);
149		150	void msm_dsi_host_snapshot(struct msm_disp_state disp_state, struct mipi_dsi_host host);
150	/* dsi phy */	151	/* dsi phy */
151	struct msm_dsi_phy;	152	struct msm_dsi_phy;
152	struct msm_dsi_phy_shared_timings {	153	struct msm_dsi_phy_shared_timings {
@@ -173,6 +174,7 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, · 20 unmodified lines
173	struct clk byte_clk_provider, struct clk pixel_clk_provider);	174	struct clk byte_clk_provider, struct clk pixel_clk_provider);
174	void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);	175	void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);
175	int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy);	176	int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy);
		177	void msm_dsi_phy_snapshot(struct msm_disp_state disp_state, struct msm_dsi_phy phy);
176		178
177	#endif /* __DSI_CONNECTOR_H__ */	179	#endif /* __DSI_CONNECTOR_H__ */
178		180

drivers/gpu/drm/msm/dsi/dsi.xml.h+22−1700

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34
@@ -621,1693 +629,7 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) · 594 unmodified lines
621	return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;	629	return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
622	}	630	}
623		631
624	#define REG_DSI_PHY_PLL_CTRL_0 0x00000200	632	#define REG_DSI_CPHY_MODE_CTRL 0x000002d4
625	#define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
626
627	#define REG_DSI_PHY_PLL_CTRL_1 0x00000204
628
629	#define REG_DSI_PHY_PLL_CTRL_2 0x00000208
630
631	#define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
632
633	#define REG_DSI_PHY_PLL_CTRL_4 0x00000210
634
635	#define REG_DSI_PHY_PLL_CTRL_5 0x00000214
636
637	#define REG_DSI_PHY_PLL_CTRL_6 0x00000218
638
639	#define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
640
641	#define REG_DSI_PHY_PLL_CTRL_8 0x00000220
642
643	#define REG_DSI_PHY_PLL_CTRL_9 0x00000224
644
645	#define REG_DSI_PHY_PLL_CTRL_10 0x00000228
646
647	#define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
648
649	#define REG_DSI_PHY_PLL_CTRL_12 0x00000230
650
651	#define REG_DSI_PHY_PLL_CTRL_13 0x00000234
652
653	#define REG_DSI_PHY_PLL_CTRL_14 0x00000238
654
655	#define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
656
657	#define REG_DSI_PHY_PLL_CTRL_16 0x00000240
658
659	#define REG_DSI_PHY_PLL_CTRL_17 0x00000244
660
661	#define REG_DSI_PHY_PLL_CTRL_18 0x00000248
662
663	#define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
664
665	#define REG_DSI_PHY_PLL_CTRL_20 0x00000250
666
667	#define REG_DSI_PHY_PLL_STATUS 0x00000280
668	#define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
669
670	#define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
671
672	#define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
673
674	#define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
675
676	#define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
677
678	#define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
679
680	#define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
681
682	#define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
683
684	#define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
685
686	#define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
687
688	#define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
689
690	#define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
691
692	#define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
693
694	#define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
695
696	#define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
697
698	#define REG_DSI_8x60_PHY_CTRL_0 0x00000290
699
700	#define REG_DSI_8x60_PHY_CTRL_1 0x00000294
701
702	#define REG_DSI_8x60_PHY_CTRL_2 0x00000298
703
704	#define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
705
706	#define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
707
708	#define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
709
710	#define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
711
712	#define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
713
714	#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
715
716	#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
717
718	#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
719
720	#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
721
722	#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
723
724	#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
725
726	#define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
727
728	#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
729	#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
730
731	static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
732
733	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
734
735	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
736
737	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
738
739	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
740
741	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
742
743	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
744
745	#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
746
747	#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
748
749	#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
750
751	#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
752
753	#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
754
755	#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
756
757	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
758	#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
759	#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
760	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
761	{
762	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
763	}
764
765	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
766	#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
767	#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
768	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
769	{
770	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
771	}
772
773	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
774	#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
775	#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
776	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
777	{
778	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
779	}
780
781	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
782
783	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
784	#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
785	#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
786	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
787	{
788	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
789	}
790
791	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
792	#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
793	#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
794	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
795	{
796	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
797	}
798
799	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
800	#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
801	#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
802	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
803	{
804	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
805	}
806
807	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
808	#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
809	#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
810	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
811	{
812	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
813	}
814
815	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
816	#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
817	#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
818	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
819	{
820	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
821	}
822
823	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
824	#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
825	#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
826	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
827	{
828	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
829	}
830	#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
831	#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
832	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
833	{
834	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
835	}
836
837	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
838	#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
839	#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
840	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
841	{
842	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
843	}
844
845	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
846	#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
847	#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
848	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
849	{
850	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
851	}
852
853	#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
854
855	#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
856
857	#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
858
859	#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
860
861	#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
862
863	#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
864
865	#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
866
867	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
868
869	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
870
871	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
872
873	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
874
875	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
876
877	#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
878
879	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
880
881	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
882
883	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
884
885	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
886
887	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
888
889	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
890
891	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
892
893	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
894
895	#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
896
897	#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
898
899	#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
900
901	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
902
903	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
904
905	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
906
907	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
908
909	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
910
911	#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
912	#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
913
914	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
915	#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
916
917	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
918
919	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
920
921	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
922
923	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
924
925	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
926
927	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
928
929	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
930
931	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
932
933	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
934
935	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
936
937	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
938
939	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
940
941	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
942
943	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
944
945	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
946
947	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
948
949	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
950
951	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
952
953	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
954
955	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
956
957	#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
958	#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
959
960	static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
961
962	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
963
964	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
965
966	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
967
968	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
969
970	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
971
972	static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
973
974	static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
975
976	static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
977
978	static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
979
980	#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
981
982	#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
983
984	#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
985
986	#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
987
988	#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
989
990	#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
991
992	#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
993
994	#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
995
996	#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
997
998	#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
999	#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1000	#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1001	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1002	{
1003	return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1004	}
1005
1006	#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
1007	#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1008	#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1009	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1010	{
1011	return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1012	}
1013
1014	#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
1015	#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1016	#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1017	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1018	{
1019	return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1020	}
1021
1022	#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
1023	#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1024
1025	#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
1026	#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1027	#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1028	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1029	{
1030	return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1031	}
1032
1033	#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
1034	#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1035	#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1036	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1037	{
1038	return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1039	}
1040
1041	#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
1042	#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1043	#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1044	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1045	{
1046	return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1047	}
1048
1049	#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
1050	#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1051	#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1052	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1053	{
1054	return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1055	}
1056
1057	#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
1058	#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1059	#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1060	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1061	{
1062	return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1063	}
1064
1065	#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
1066	#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1067	#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1068	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1069	{
1070	return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1071	}
1072	#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1073	#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1074	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1075	{
1076	return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1077	}
1078
1079	#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
1080	#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1081	#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1082	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1083	{
1084	return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1085	}
1086
1087	#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
1088	#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1089	#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1090	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1091	{
1092	return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1093	}
1094
1095	#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
1096
1097	#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
1098
1099	#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
1100
1101	#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
1102
1103	#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
1104
1105	#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
1106
1107	#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
1108
1109	#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
1110
1111	#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
1112
1113	#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
1114
1115	#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
1116
1117	#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
1118
1119	#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
1120
1121	#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
1122	#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1123
1124	#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
1125
1126	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
1127
1128	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
1129
1130	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
1131
1132	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
1133
1134	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
1135
1136	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
1137
1138	#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1139
1140	#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
1141	#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
1142
1143	#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
1144
1145	#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
1146
1147	#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
1148
1149	#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
1150	#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
1151
1152	#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
1153
1154	#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
1155
1156	#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
1157
1158	#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
1159	#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
1160	#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
1161	#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
1162	#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
1163
1164	#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
1165
1166	#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
1167
1168	#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
1169
1170	#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
1171
1172	#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
1173
1174	#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
1175	#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
1176	#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
1177	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
1178	{
1179	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
1180	}
1181	#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
1182
1183	#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
1184	#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
1185	#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
1186	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
1187	{
1188	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
1189	}
1190	#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
1191	#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
1192	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
1193	{
1194	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
1195	}
1196
1197	#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
1198	#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
1199	#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
1200	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
1201	{
1202	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
1203	}
1204
1205	#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
1206	#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
1207	#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
1208	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
1209	{
1210	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
1211	}
1212
1213	#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
1214
1215	#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
1216
1217	#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
1218
1219	#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
1220
1221	#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
1222
1223	#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
1224
1225	#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
1226
1227	#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
1228
1229	#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
1230	#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
1231
1232	#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
1233
1234	#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
1235
1236	#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
1237
1238	#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
1239
1240	#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
1241
1242	#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
1243
1244	#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
1245
1246	#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
1247
1248	#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
1249
1250	#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
1251
1252	#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
1253
1254	#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
1255
1256	#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
1257
1258	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
1259
1260	#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
1261
1262	#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
1263
1264	#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
1265
1266	#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
1267
1268	#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
1269
1270	#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
1271
1272	#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
1273
1274	#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
1275	#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
1276
1277	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
1278
1279	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
1280
1281	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
1282
1283	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
1284
1285	#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
1286
1287	static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1288
1289	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1290
1291	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
1292
1293	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
1294
1295	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
1296
1297	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
1298
1299	static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
1300
1301	static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
1302
1303	static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
1304
1305	static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
1306
1307	#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
1308
1309	#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
1310
1311	#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
1312
1313	#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
1314
1315	#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
1316
1317	#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
1318
1319	#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
1320
1321	#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
1322
1323	#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
1324
1325	#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
1326	#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1327	#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1328	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1329	{
1330	return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1331	}
1332
1333	#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
1334	#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1335	#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1336	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1337	{
1338	return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1339	}
1340
1341	#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
1342	#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1343	#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1344	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1345	{
1346	return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1347	}
1348
1349	#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
1350	#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1351
1352	#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
1353	#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1354	#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1355	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1356	{
1357	return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1358	}
1359
1360	#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
1361	#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1362	#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1363	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1364	{
1365	return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1366	}
1367
1368	#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
1369	#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1370	#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1371	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1372	{
1373	return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1374	}
1375
1376	#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
1377	#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1378	#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1379	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1380	{
1381	return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1382	}
1383
1384	#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
1385	#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1386	#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1387	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1388	{
1389	return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1390	}
1391
1392	#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
1393	#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1394	#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1395	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1396	{
1397	return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1398	}
1399	#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1400	#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1401	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1402	{
1403	return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1404	}
1405
1406	#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
1407	#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1408	#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1409	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1410	{
1411	return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1412	}
1413
1414	#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
1415	#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1416	#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1417	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1418	{
1419	return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1420	}
1421
1422	#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
1423
1424	#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
1425
1426	#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
1427
1428	#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
1429
1430	#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
1431
1432	#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
1433
1434	#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
1435
1436	#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
1437
1438	#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
1439
1440	#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
1441
1442	#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
1443
1444	#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
1445
1446	#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
1447
1448	#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
1449	#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1450
1451	#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
1452
1453	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
1454
1455	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
1456
1457	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
1458
1459	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
1460
1461	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
1462
1463	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
1464
1465	#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1466
1467	#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
1468
1469	#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
1470
1471	#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
1472
1473	#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
1474
1475	#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
1476	#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
1477	#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
1478	static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
1479	{
1480	return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
1481	}
1482	#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
1483	#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
1484	static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
1485	{
1486	return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
1487	}
1488
1489	#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
1490	#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
1491
1492	#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
1493	#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
1494
1495	#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
1496
1497	#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
1498
1499	#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
1500
1501	#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
1502
1503	#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
1504
1505	#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
1506
1507	#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
1508
1509	#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
1510
1511	#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
1512
1513	#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
1514
1515	#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
1516
1517	#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
1518	#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
1519
1520	#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
1521	#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
1522	#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
1523	static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
1524	{
1525	return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
1526	}
1527
1528	static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1529
1530	static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1531	#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
1532	#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
1533	static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
1534	{
1535	return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
1536	}
1537
1538	static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1539	#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
1540
1541	static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1542
1543	static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1544
1545	static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1546
1547	static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1548
1549	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1550	#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1551	#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1552	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1553	{
1554	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
1555	}
1556
1557	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1558	#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1559	#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1560	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1561	{
1562	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
1563	}
1564
1565	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1566	#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1567	#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1568	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1569	{
1570	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
1571	}
1572
1573	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1574	#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1575	#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1576	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1577	{
1578	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
1579	}
1580
1581	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1582	#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1583	#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
1584	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
1585	{
1586	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
1587	}
1588
1589	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1590	#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1591	#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
1592	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
1593	{
1594	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
1595	}
1596	#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1597	#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
1598	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
1599	{
1600	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
1601	}
1602
1603	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
1604	#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1605	#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
1606	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
1607	{
1608	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
1609	}
1610
1611	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
1612	#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1613	#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1614	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1615	{
1616	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
1617	}
1618
1619	static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
1620
1621	static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
1622
1623	static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
1624
1625	#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
1626
1627	#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
1628
1629	#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
1630
1631	#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
1632
1633	#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
1634
1635	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
1636
1637	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
1638
1639	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
1640
1641	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
1642
1643	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
1644
1645	#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
1646
1647	#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
1648
1649	#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
1650
1651	#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
1652
1653	#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
1654
1655	#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
1656
1657	#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
1658
1659	#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
1660
1661	#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
1662
1663	#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
1664
1665	#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
1666
1667	#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
1668
1669	#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
1670
1671	#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
1672
1673	#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
1674
1675	#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
1676
1677	#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
1678
1679	#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
1680
1681	#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
1682
1683	#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
1684
1685	#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
1686
1687	#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
1688
1689	#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
1690
1691	#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
1692
1693	#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
1694
1695	#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
1696
1697	#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
1698
1699	#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
1700
1701	#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
1702
1703	#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
1704
1705	#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
1706
1707	#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
1708
1709	#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
1710
1711	#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
1712
1713	#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
1714
1715	#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
1716
1717	#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
1718
1719	#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
1720
1721	#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
1722
1723	#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
1724
1725	#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
1726
1727	#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
1728
1729	#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
1730
1731	#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
1732
1733	#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
1734
1735	#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
1736
1737	#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
1738
1739	#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
1740
1741	#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
1742
1743	#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
1744
1745	#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
1746
1747	#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
1748
1749	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
1750
1751	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
1752
1753	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
1754
1755	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
1756
1757	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
1758
1759	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
1760
1761	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
1762
1763	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
1764
1765	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
1766
1767	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
1768
1769	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
1770
1771	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
1772
1773	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
1774
1775	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
1776
1777	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
1778
1779	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
1780
1781	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
1782
1783	#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
1784
1785	#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
1786
1787	#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
1788
1789	static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1790
1791	static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1792
1793	static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1794
1795	static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1796
1797	static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1798
1799	static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1800
1801	static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1802
1803	static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1804
1805	static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1806
1807	static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1808
1809	static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1810
1811	static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1812
1813	static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1814
1815	#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
1816
1817	#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
1818
1819	#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
1820
1821	#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
1822
1823	#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
1824
1825	#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
1826
1827	#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
1828
1829	#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
1830
1831	#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
1832
1833	#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
1834
1835	#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
1836
1837	#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
1838
1839	#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
1840
1841	#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
1842
1843	#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
1844
1845	#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
1846
1847	#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
1848
1849	#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
1850
1851	#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
1852
1853	#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
1854
1855	#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
1856
1857	#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
1858
1859	#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
1860
1861	#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
1862
1863	#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
1864
1865	#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
1866
1867	#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
1868
1869	#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
1870
1871	#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
1872
1873	#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
1874
1875	#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
1876
1877	#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
1878
1879	#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
1880
1881	#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
1882
1883	#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
1884
1885	#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
1886
1887	#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
1888
1889	#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
1890
1891	#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
1892
1893	#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
1894
1895	#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
1896
1897	#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
1898
1899	#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
1900
1901	#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
1902
1903	#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
1904
1905	#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
1906
1907	#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
1908
1909	#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
1910
1911	#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
1912
1913	#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
1914
1915	#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
1916
1917	#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
1918
1919	#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
1920
1921	#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
1922
1923	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
1924
1925	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
1926
1927	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
1928
1929	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
1930
1931	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
1932
1933	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
1934
1935	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
1936
1937	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
1938
1939	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
1940
1941	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
1942
1943	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
1944
1945	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
1946
1947	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
1948
1949	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
1950
1951	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
1952
1953	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
1954
1955	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
1956
1957	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
1958
1959	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
1960
1961	#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
1962
1963	#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
1964
1965	#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
1966
1967	#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
1968
1969	#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
1970
1971	#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
1972
1973	#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
1974
1975	#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
1976
1977	#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
1978
1979	#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
1980
1981	#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
1982
1983	#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
1984
1985	#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
1986
1987	#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
1988
1989	#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
1990
1991	static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1992
1993	static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1994
1995	static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1996
1997	static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1998
1999	static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
2000
2001	static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
2002
2003	static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
2004
2005	static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
2006
2007	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
2008
2009	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
2010
2011	#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
2012
2013	#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
2014
2015	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
2016
2017	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
2018
2019	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
2020
2021	#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
2022
2023	#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
2024
2025	#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
2026
2027	#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
2028
2029	#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
2030
2031	#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
2032
2033	#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
2034
2035	#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
2036
2037	#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
2038
2039	#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
2040
2041	#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
2042
2043	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
2044
2045	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
2046
2047	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
2048
2049	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
2050
2051	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
2052
2053	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
2054
2055	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
2056
2057	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
2058
2059	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
2060
2061	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
2062
2063	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
2064
2065	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
2066
2067	#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
2068
2069	#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
2070
2071	#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
2072
2073	#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
2074
2075	#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
2076
2077	#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
2078
2079	#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
2080
2081	#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
2082
2083	#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
2084
2085	#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
2086
2087	#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
2088
2089	#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
2090
2091	#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
2092
2093	#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
2094
2095	#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
2096
2097	#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
2098
2099	#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
2100
2101	#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
2102
2103	#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
2104
2105	#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
2106
2107	#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
2108
2109	#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
2110
2111	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
2112
2113	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
2114
2115	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
2116
2117	#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
2118
2119	#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
2120
2121	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
2122
2123	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
2124
2125	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
2126
2127	#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
2128
2129	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
2130
2131	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
2132
2133	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
2134
2135	#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
2136
2137	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
2138
2139	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
2140
2141	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
2142
2143	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
2144
2145	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
2146
2147	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
2148
2149	#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
2150
2151	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
2152
2153	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
2154
2155	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
2156
2157	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
2158
2159	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
2160
2161	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
2162
2163	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
2164
2165	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
2166
2167	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
2168
2169	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
2170
2171	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
2172
2173	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
2174
2175	#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
2176
2177	#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
2178
2179	#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
2180
2181	#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
2182
2183	#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
2184
2185	#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
2186
2187	#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
2188
2189	#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
2190
2191	#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
2192
2193	#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
2194
2195	#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
2196
2197	#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
2198
2199	#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
2200
2201	#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
2202
2203	#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
2204
2205	#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
2206
2207	#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
2208
2209	#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
2210
2211	#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
2212
2213	#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
2214
2215	#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
2216
2217	#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
2218
2219	#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
2220
2221	#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
2222
2223	#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
2224
2225	#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
2226
2227	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
2228
2229	#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
2230
2231	#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
2232
2233	#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
2234
2235	#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
2236
2237	#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
2238
2239	#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
2240
2241	#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
2242
2243	#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
2244
2245	#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
2246
2247	#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
2248
2249	#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
2250
2251	#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
2252
2253	#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
2254
2255	#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
2256
2257	#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
2258
2259	#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
2260
2261	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
2262
2263	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
2264
2265	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
2266
2267	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
2268
2269	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
2270
2271	#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
2272
2273	#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
2274
2275	#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
2276
2277	#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
2278
2279	#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
2280
2281	#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
2282
2283	#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
2284
2285	#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
2286
2287	#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
2288
2289	#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
2290
2291	#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
2292
2293	#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
2294
2295	#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
2296
2297	#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
2298
2299	#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
2300
2301	#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
2302
2303	#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
2304
2305	#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
2306
2307	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
2308
2309	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
2310		633
2311	#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
2312		634
2313	#endif /* DSI_XML */	635	#endif /* DSI_XML */

drivers/gpu/drm/msm/dsi/dsi_host.c+19−11

 	int id;
 	void __iomem *ctrl_base;
+	phys_addr_t ctrl_size;
 	struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
 	struct clk *bus_clks[DSI_BUS_CLK_MAX];
 	struct clk *pixel_clk_src;
 	struct clk *byte_intf_clk;
-	struct opp_table *opp_table;
 	u32 byte_clk_rate;
 	u32 pixel_clk_rate;
 	u32 esc_clk_rate;
 	uint64_t iova;
 	u8 *data;
-	data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED,
+	data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
 					priv->kms->aspace,
 					&msm_host->tx_gem_obj, &iova);
 		goto fail;
 	}
-	msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
+	msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", "DSI CTRL", &msm_host->ctrl_size);
 	if (IS_ERR(msm_host->ctrl_base)) {
 		pr_err("%s: unable to map Dsi ctrl base\n", __func__);
 		ret = PTR_ERR(msm_host->ctrl_base);
 		goto fail;
 	}
-	msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte");
+	ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
-	if (IS_ERR(msm_host->opp_table))
+	if (ret)
-		return PTR_ERR(msm_host->opp_table);
+		return ret;
 	/* OPP table is optional */
-	ret = dev_pm_opp_of_add_table(&pdev->dev);
+	ret = devm_pm_opp_of_add_table(&pdev->dev);
 	if (ret && ret != -ENODEV) {
 		dev_err(&pdev->dev, "invalid OPP table in device tree\n");
-		dev_pm_opp_put_clkname(msm_host->opp_table);
 		return ret;
 	}
 	mutex_destroy(&msm_host->cmd_mutex);
 	mutex_destroy(&msm_host->dev_mutex);
-	dev_pm_opp_of_remove_table(&msm_host->pdev->dev);
-	dev_pm_opp_put_clkname(msm_host->opp_table);
 	pm_runtime_disable(&msm_host->pdev->dev);
 }
 	return of_drm_find_bridge(msm_host->device_node);
 }
+void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
+{
+	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+	pm_runtime_get_sync(&msm_host->pdev->dev);
+	msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
+			msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
+	pm_runtime_put_sync(&msm_host->pdev->dev);
+}

drivers/gpu/drm/msm/dsi/dsi_manager.c+6−6

 	if (!msm_dsi_device_connected(msm_dsi))
 		return;
-	ret = dsi_mgr_phy_enable(id, phy_shared_timings);
-	if (ret)
-		goto phy_en_fail;
 	/* Do nothing with the host if it is slave-DSI in case of dual DSI */
 	if (is_dual_dsi && !IS_MASTER_DSI_LINK(id))
 		return;
+	ret = dsi_mgr_phy_enable(id, phy_shared_timings);
+	if (ret)
+		goto phy_en_fail;
 	ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi);
 	if (ret) {
 		pr_err("%s: power on host %d failed, %d\n", __func__, id, ret);
 	ret = dsi_mgr_setup_components(id);
 	if (ret) {
-		pr_err("%s: failed to register mipi dsi host for DSI %d\n",
+		pr_err("%s: failed to register mipi dsi host for DSI %d: %d\n",
-			__func__, id);
+			__func__, id, ret);
 		goto fail;
 	}

drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h+228−0

@@ -0,0 +1,228 @@
	1	#ifndef DSI_PHY_10NM_XML
	2	#define DSI_PHY_10NM_XML
	3
	4	/* Autogenerated file, DO NOT EDIT manually!
	5
	6	This file was generated by the rules-ng-ng headergen tool in this git repository:
	7	http://github.com/freedreno/envytools/
	8	git clone https://github.com/freedreno/envytools.git
	9
	10	The rules-ng-ng source files this header was generated from are:
	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
	24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
	25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
	26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
	27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
	28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
	29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
	30
	31	Copyright (C) 2013-2021 by the following authors:
	32	- Rob Clark <robdclark@gmail.com> (robclark)
	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
	34
	35	Permission is hereby granted, free of charge, to any person obtaining
	36	a copy of this software and associated documentation files (the
	37	"Software"), to deal in the Software without restriction, including
	38	without limitation the rights to use, copy, modify, merge, publish,
	39	distribute, sublicense, and/or sell copies of the Software, and to
	40	permit persons to whom the Software is furnished to do so, subject to
	41	the following conditions:
	42
	43	The above copyright notice and this permission notice (including the
	44	next paragraph) shall be included in all copies or substantial
	45	portions of the Software.
	46
	47	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	48	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	49	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	50	IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	51	LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	52	OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	53	WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	54	*/
	55
	56
	57	#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
	58
	59	#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
	60
	61	#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
	62
	63	#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
	64
	65	#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
	66
	67	#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
	68
	69	#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
	70
	71	#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
	72
	73	#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
	74
	75	#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
	76
	77	#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
	78
	79	#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
	80
	81	#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
	82
	83	#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
	84
	85	#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
	86
	87	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
	88
	89	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
	90
	91	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
	92
	93	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
	94
	95	#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
	96
	97	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
	98
	99	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
	100
	101	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
	102
	103	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
	104
	105	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
	106
	107	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
	108
	109	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
	110
	111	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
	112
	113	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
	114
	115	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
	116
	117	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
	118
	119	#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
	120
	121	#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
	122
	123	#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
	124
	125	#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
	126
	127	static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
	128
	129	static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
	130
	131	static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
	132
	133	static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
	134
	135	static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
	136
	137	static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
	138
	139	static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
	140
	141	static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
	142
	143	static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
	144
	145	static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
	146
	147	static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
	148
	149	static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
	150
	151	static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
	152
	153	#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
	154
	155	#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
	156
	157	#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
	158
	159	#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
	160
	161	#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
	162
	163	#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
	164
	165	#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
	166
	167	#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
	168
	169	#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
	170
	171	#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
	172
	173	#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
	174
	175	#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
	176
	177	#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
	178
	179	#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
	180
	181	#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
	182
	183	#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
	184
	185	#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
	186
	187	#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
	188
	189	#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
	190
	191	#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
	192
	193	#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
	194
	195	#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
	196
	197	#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
	198
	199	#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
	200
	201	#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
	202
	203	#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
	204
	205	#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
	206
	207	#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
	208
	209	#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
	210
	211	#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
	212
	213	#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
	214
	215	#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
	216
	217	#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
	218
	219	#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
	220
	221	#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
	222
	223	#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
	224
	225	#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
	226
	227
	228	#endif /* DSI_PHY_10NM_XML */

drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h+310−0

@@ -0,0 +1,310 @@
	1	#ifndef DSI_PHY_14NM_XML
	2	#define DSI_PHY_14NM_XML
	3
	4	/* Autogenerated file, DO NOT EDIT manually!
	5
	6	This file was generated by the rules-ng-ng headergen tool in this git repository:
	7	http://github.com/freedreno/envytools/
	8	git clone https://github.com/freedreno/envytools.git
	9
	10	The rules-ng-ng source files this header was generated from are:
	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
	24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
	25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
	26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
	27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
	28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
	29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
	30
	31	Copyright (C) 2013-2021 by the following authors:
	32	- Rob Clark <robdclark@gmail.com> (robclark)
	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
	34
	35	Permission is hereby granted, free of charge, to any person obtaining
	36	a copy of this software and associated documentation files (the
	37	"Software"), to deal in the Software without restriction, including
	38	without limitation the rights to use, copy, modify, merge, publish,
	39	distribute, sublicense, and/or sell copies of the Software, and to
	40	permit persons to whom the Software is furnished to do so, subject to
	41	the following conditions:
	42
	43	The above copyright notice and this permission notice (including the
	44	next paragraph) shall be included in all copies or substantial
	45	portions of the Software.
	46
	47	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	48	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	49	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	50	IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	51	LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	52	OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	53	WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	54	*/
	55
	56
	57	#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
	58
	59	#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
	60
	61	#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
	62
	63	#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
	64
	65	#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
	66	#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
	67	#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
	68	static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
	69	{
	70	return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
	71	}
	72	#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
	73	#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
	74	static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
	75	{
	76	return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
	77	}
	78
	79	#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
	80	#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
	81
	82	#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
	83	#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
	84
	85	#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
	86
	87	#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
	88
	89	#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
	90
	91	#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
	92
	93	#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
	94
	95	#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
	96
	97	#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
	98
	99	#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
	100
	101	#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
	102
	103	#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
	104
	105	#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
	106
	107	#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
	108	#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
	109
	110	#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
	111	#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
	112	#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
	113	static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
	114	{
	115	return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
	116	}
	117
	118	static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
	119
	120	static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
	121	#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
	122	#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
	123	static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
	124	{
	125	return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
	126	}
	127
	128	static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
	129	#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
	130
	131	static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
	132
	133	static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
	134
	135	static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
	136
	137	static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
	138
	139	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
	140	#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
	141	#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
	142	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
	143	{
	144	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
	145	}
	146
	147	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
	148	#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
	149	#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
	150	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
	151	{
	152	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
	153	}
	154
	155	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
	156	#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
	157	#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
	158	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
	159	{
	160	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
	161	}
	162
	163	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
	164	#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
	165	#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
	166	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
	167	{
	168	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
	169	}
	170
	171	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
	172	#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
	173	#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
	174	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
	175	{
	176	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
	177	}
	178
	179	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
	180	#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
	181	#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
	182	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
	183	{
	184	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
	185	}
	186	#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
	187	#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
	188	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
	189	{
	190	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
	191	}
	192
	193	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
	194	#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
	195	#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
	196	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
	197	{
	198	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
	199	}
	200
	201	static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
	202	#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
	203	#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
	204	static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
	205	{
	206	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
	207	}
	208
	209	static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
	210
	211	static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
	212
	213	static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
	214
	215	#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
	216
	217	#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
	218
	219	#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
	220
	221	#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
	222
	223	#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
	224
	225	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
	226
	227	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
	228
	229	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
	230
	231	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
	232
	233	#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
	234
	235	#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
	236
	237	#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
	238
	239	#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
	240
	241	#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
	242
	243	#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
	244
	245	#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
	246
	247	#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
	248
	249	#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
	250
	251	#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
	252
	253	#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
	254
	255	#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
	256
	257	#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
	258
	259	#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
	260
	261	#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
	262
	263	#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
	264
	265	#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
	266
	267	#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
	268
	269	#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
	270
	271	#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
	272
	273	#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
	274
	275	#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
	276
	277	#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
	278
	279	#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
	280
	281	#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
	282
	283	#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
	284
	285	#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
	286
	287	#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
	288
	289	#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
	290
	291	#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
	292
	293	#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
	294
	295	#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
	296
	297	#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
	298
	299	#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
	300
	301	#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
	302
	303	#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
	304
	305	#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
	306
	307	#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
	308
	309
	310	#endif /* DSI_PHY_14NM_XML */

drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h+238−0

@@ -0,0 +1,238 @@
	1	#ifndef DSI_PHY_20NM_XML
	2	#define DSI_PHY_20NM_XML
	3
	4	/* Autogenerated file, DO NOT EDIT manually!
	5
	6	This file was generated by the rules-ng-ng headergen tool in this git repository:
	7	http://github.com/freedreno/envytools/
	8	git clone https://github.com/freedreno/envytools.git
	9
	10	The rules-ng-ng source files this header was generated from are:
	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
	24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
	25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
	26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
	27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
	28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
	29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
	30
	31	Copyright (C) 2013-2021 by the following authors:
	32	- Rob Clark <robdclark@gmail.com> (robclark)
	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
	34
	35	Permission is hereby granted, free of charge, to any person obtaining
	36	a copy of this software and associated documentation files (the
	37	"Software"), to deal in the Software without restriction, including
	38	without limitation the rights to use, copy, modify, merge, publish,
	39	distribute, sublicense, and/or sell copies of the Software, and to
	40	permit persons to whom the Software is furnished to do so, subject to
	41	the following conditions:
	42
	43	The above copyright notice and this permission notice (including the
	44	next paragraph) shall be included in all copies or substantial
	45	portions of the Software.
	46
	47	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	48	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	49	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	50	IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	51	LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	52	OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	53	WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	54	*/
	55
	56
	57	static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
	58
	59	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
	60
	61	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
	62
	63	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
	64
	65	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
	66
	67	static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
	68
	69	static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
	70
	71	static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
	72
	73	static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
	74
	75	static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
	76
	77	#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
	78
	79	#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
	80
	81	#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
	82
	83	#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
	84
	85	#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
	86
	87	#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
	88
	89	#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
	90
	91	#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
	92
	93	#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
	94
	95	#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
	96	#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
	97	#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
	98	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
	99	{
	100	return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
	101	}
	102
	103	#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
	104	#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
	105	#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
	106	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
	107	{
	108	return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
	109	}
	110
	111	#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
	112	#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
	113	#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
	114	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
	115	{
	116	return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
	117	}
	118
	119	#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
	120	#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
	121
	122	#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
	123	#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
	124	#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
	125	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
	126	{
	127	return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
	128	}
	129
	130	#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
	131	#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
	132	#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
	133	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
	134	{
	135	return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
	136	}
	137
	138	#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
	139	#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
	140	#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
	141	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
	142	{
	143	return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
	144	}
	145
	146	#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
	147	#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
	148	#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
	149	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
	150	{
	151	return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
	152	}
	153
	154	#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
	155	#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
	156	#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
	157	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
	158	{
	159	return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
	160	}
	161
	162	#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
	163	#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
	164	#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
	165	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
	166	{
	167	return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
	168	}
	169	#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
	170	#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
	171	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
	172	{
	173	return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
	174	}
	175
	176	#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
	177	#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
	178	#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
	179	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
	180	{
	181	return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
	182	}
	183
	184	#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
	185	#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
	186	#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
	187	static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
	188	{
	189	return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
	190	}
	191
	192	#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
	193
	194	#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
	195
	196	#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
	197
	198	#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
	199
	200	#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
	201
	202	#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
	203
	204	#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
	205
	206	#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
	207
	208	#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
	209
	210	#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
	211
	212	#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
	213
	214	#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
	215
	216	#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
	217
	218	#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
	219	#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
	220
	221	#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
	222
	223	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
	224
	225	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
	226
	227	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
	228
	229	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
	230
	231	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
	232
	233	#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
	234
	235	#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
	236
	237
	238	#endif /* DSI_PHY_20NM_XML */

drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h+385−0

@@ -0,0 +1,385 @@
	1	#ifndef DSI_PHY_28NM_XML
	2	#define DSI_PHY_28NM_XML
	3
	4	/* Autogenerated file, DO NOT EDIT manually!
	5
	6	This file was generated by the rules-ng-ng headergen tool in this git repository:
	7	http://github.com/freedreno/envytools/
	8	git clone https://github.com/freedreno/envytools.git
	9
	10	The rules-ng-ng source files this header was generated from are:
	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
	24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
	25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
	26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
	27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
	28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
	29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
	30
	31	Copyright (C) 2013-2021 by the following authors:
	32	- Rob Clark <robdclark@gmail.com> (robclark)
	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
	34
	35	Permission is hereby granted, free of charge, to any person obtaining
	36	a copy of this software and associated documentation files (the
	37	"Software"), to deal in the Software without restriction, including
	38	without limitation the rights to use, copy, modify, merge, publish,
	39	distribute, sublicense, and/or sell copies of the Software, and to
	40	permit persons to whom the Software is furnished to do so, subject to
	41	the following conditions:
	42
	43	The above copyright notice and this permission notice (including the
	44	next paragraph) shall be included in all copies or substantial
	45	portions of the Software.
	46
	47	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	48	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	49	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	50	IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	51	LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	52	OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	53	WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	54	*/
	55
	56
	57	static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
	58
	59	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
	60
	61	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
	62
	63	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
	64
	65	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
	66
	67	static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
	68
	69	static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
	70
	71	static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
	72
	73	static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
	74
	75	static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
	76
	77	#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
	78
	79	#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
	80
	81	#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
	82
	83	#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
	84
	85	#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
	86
	87	#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
	88
	89	#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
	90
	91	#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
	92
	93	#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
	94
	95	#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
	96	#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
	97	#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
	98	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
	99	{
	100	return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
	101	}
	102
	103	#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
	104	#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
	105	#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
	106	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
	107	{
	108	return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
	109	}
	110
	111	#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
	112	#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
	113	#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
	114	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
	115	{
	116	return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
	117	}
	118
	119	#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
	120	#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
	121
	122	#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
	123	#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
	124	#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
	125	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
	126	{
	127	return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
	128	}
	129
	130	#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
	131	#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
	132	#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
	133	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
	134	{
	135	return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
	136	}
	137
	138	#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
	139	#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
	140	#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
	141	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
	142	{
	143	return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
	144	}
	145
	146	#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
	147	#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
	148	#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
	149	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
	150	{
	151	return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
	152	}
	153
	154	#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
	155	#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
	156	#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
	157	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
	158	{
	159	return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
	160	}
	161
	162	#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
	163	#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
	164	#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
	165	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
	166	{
	167	return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
	168	}
	169	#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
	170	#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
	171	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
	172	{
	173	return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
	174	}
	175
	176	#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
	177	#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
	178	#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
	179	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
	180	{
	181	return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
	182	}
	183
	184	#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
	185	#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
	186	#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
	187	static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
	188	{
	189	return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
	190	}
	191
	192	#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
	193
	194	#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
	195
	196	#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
	197
	198	#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
	199
	200	#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
	201
	202	#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
	203
	204	#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
	205
	206	#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
	207
	208	#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
	209
	210	#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
	211
	212	#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
	213
	214	#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
	215
	216	#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
	217
	218	#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
	219	#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
	220
	221	#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
	222
	223	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
	224
	225	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
	226
	227	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
	228
	229	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
	230
	231	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
	232
	233	#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
	234
	235	#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
	236
	237	#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
	238	#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
	239
	240	#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
	241
	242	#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
	243
	244	#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
	245
	246	#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
	247	#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
	248
	249	#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
	250
	251	#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
	252
	253	#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
	254
	255	#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
	256	#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
	257	#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
	258	#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
	259	#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
	260
	261	#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
	262
	263	#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
	264
	265	#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
	266
	267	#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
	268
	269	#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
	270
	271	#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
	272	#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
	273	#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
	274	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
	275	{
	276	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
	277	}
	278	#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
	279
	280	#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
	281	#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
	282	#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
	283	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
	284	{
	285	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
	286	}
	287	#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
	288	#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
	289	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
	290	{
	291	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
	292	}
	293
	294	#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
	295	#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
	296	#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
	297	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
	298	{
	299	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
	300	}
	301
	302	#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
	303	#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
	304	#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
	305	static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
	306	{
	307	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
	308	}
	309
	310	#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
	311
	312	#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
	313
	314	#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
	315
	316	#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
	317
	318	#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
	319
	320	#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
	321
	322	#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
	323
	324	#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
	325
	326	#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
	327	#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
	328
	329	#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
	330
	331	#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
	332
	333	#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
	334
	335	#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
	336
	337	#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
	338
	339	#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
	340
	341	#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
	342
	343	#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
	344
	345	#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
	346
	347	#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
	348
	349	#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
	350
	351	#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
	352
	353	#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
	354
	355	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
	356
	357	#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
	358
	359	#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
	360
	361	#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
	362
	363	#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
	364
	365	#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
	366
	367	#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
	368
	369	#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
	370
	371	#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
	372	#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
	373
	374	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
	375
	376	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
	377
	378	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
	379
	380	#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
	381
	382	#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
	383
	384
	385	#endif /* DSI_PHY_28NM_XML */

drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h+287−0

@@ -0,0 +1,287 @@
	1	#ifndef DSI_PHY_28NM_8960_XML
	2	#define DSI_PHY_28NM_8960_XML
	3
	4	/* Autogenerated file, DO NOT EDIT manually!
	5
	6	This file was generated by the rules-ng-ng headergen tool in this git repository:
	7	http://github.com/freedreno/envytools/
	8	git clone https://github.com/freedreno/envytools.git
	9
	10	The rules-ng-ng source files this header was generated from are:
	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
	24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
	25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
	26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
	27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
	28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
	29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
	30
	31	Copyright (C) 2013-2021 by the following authors:
	32	- Rob Clark <robdclark@gmail.com> (robclark)
	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
	34
	35	Permission is hereby granted, free of charge, to any person obtaining
	36	a copy of this software and associated documentation files (the
	37	"Software"), to deal in the Software without restriction, including
	38	without limitation the rights to use, copy, modify, merge, publish,
	39	distribute, sublicense, and/or sell copies of the Software, and to
	40	permit persons to whom the Software is furnished to do so, subject to
	41	the following conditions:
	42
	43	The above copyright notice and this permission notice (including the
	44	next paragraph) shall be included in all copies or substantial
	45	portions of the Software.
	46
	47	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	48	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	49	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	50	IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	51	LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	52	OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	53	WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	54	*/
	55
	56
	57	static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
	58
	59	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
	60
	61	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
	62
	63	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
	64
	65	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
	66
	67	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
	68
	69	static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
	70
	71	#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
	72
	73	#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
	74
	75	#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
	76
	77	#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
	78
	79	#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
	80
	81	#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
	82
	83	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
	84	#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
	85	#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
	86	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
	87	{
	88	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
	89	}
	90
	91	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
	92	#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
	93	#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
	94	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
	95	{
	96	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
	97	}
	98
	99	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
	100	#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
	101	#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
	102	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
	103	{
	104	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
	105	}
	106
	107	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
	108
	109	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
	110	#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
	111	#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
	112	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
	113	{
	114	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
	115	}
	116
	117	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
	118	#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
	119	#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
	120	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
	121	{
	122	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
	123	}
	124
	125	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
	126	#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
	127	#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
	128	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
	129	{
	130	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
	131	}
	132
	133	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
	134	#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
	135	#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
	136	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
	137	{
	138	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
	139	}
	140
	141	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
	142	#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
	143	#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
	144	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
	145	{
	146	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
	147	}
	148
	149	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
	150	#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
	151	#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
	152	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
	153	{
	154	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
	155	}
	156	#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
	157	#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
	158	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
	159	{
	160	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
	161	}
	162
	163	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
	164	#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
	165	#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
	166	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
	167	{
	168	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
	169	}
	170
	171	#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
	172	#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
	173	#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
	174	static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
	175	{
	176	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
	177	}
	178
	179	#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
	180
	181	#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
	182
	183	#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
	184
	185	#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
	186
	187	#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
	188
	189	#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
	190
	191	#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
	192
	193	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
	194
	195	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
	196
	197	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
	198
	199	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
	200
	201	#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
	202
	203	#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
	204
	205	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
	206
	207	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
	208
	209	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
	210
	211	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
	212
	213	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
	214
	215	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
	216
	217	#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
	218
	219	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
	220
	221	#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
	222
	223	#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
	224
	225	#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
	226
	227	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
	228
	229	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
	230
	231	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
	232
	233	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
	234
	235	#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
	236
	237	#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
	238	#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
	239
	240	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
	241	#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
	242
	243	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
	244
	245	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
	246
	247	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
	248
	249	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
	250
	251	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
	252
	253	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
	254
	255	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
	256
	257	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
	258
	259	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
	260
	261	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
	262
	263	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
	264
	265	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
	266
	267	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
	268
	269	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
	270
	271	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
	272
	273	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
	274
	275	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
	276
	277	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
	278
	279	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
	280
	281	#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
	282
	283	#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
	284	#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
	285
	286
	287	#endif /* DSI_PHY_28NM_8960_XML */

drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h+480−0

@@ -0,0 +1,480 @@
	1	#ifndef DSI_PHY_5NM_XML
	2	#define DSI_PHY_5NM_XML
	3
	4	/* Autogenerated file, DO NOT EDIT manually!
	5
	6	This file was generated by the rules-ng-ng headergen tool in this git repository:
	7	http://github.com/freedreno/envytools/
	8	git clone https://github.com/freedreno/envytools.git
	9
	10	The rules-ng-ng source files this header was generated from are:
	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
	24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
	25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
	26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
	27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
	28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
	29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
	30
	31	Copyright (C) 2013-2021 by the following authors:
	32	- Rob Clark <robdclark@gmail.com> (robclark)
	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
	34
	35	Permission is hereby granted, free of charge, to any person obtaining
	36	a copy of this software and associated documentation files (the
	37	"Software"), to deal in the Software without restriction, including
	38	without limitation the rights to use, copy, modify, merge, publish,
	39	distribute, sublicense, and/or sell copies of the Software, and to
	40	permit persons to whom the Software is furnished to do so, subject to
	41	the following conditions:
	42
	43	The above copyright notice and this permission notice (including the
	44	next paragraph) shall be included in all copies or substantial
	45	portions of the Software.
	46
	47	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	48	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	49	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	50	IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	51	LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	52	OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	53	WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	54	*/
	55
	56
	57	#define REG_DSI_5nm_PHY_CMN_REVISION_ID0 0x00000000
	58
	59	#define REG_DSI_5nm_PHY_CMN_REVISION_ID1 0x00000004
	60
	61	#define REG_DSI_5nm_PHY_CMN_REVISION_ID2 0x00000008
	62
	63	#define REG_DSI_5nm_PHY_CMN_REVISION_ID3 0x0000000c
	64
	65	#define REG_DSI_5nm_PHY_CMN_CLK_CFG0 0x00000010
	66
	67	#define REG_DSI_5nm_PHY_CMN_CLK_CFG1 0x00000014
	68
	69	#define REG_DSI_5nm_PHY_CMN_GLBL_CTRL 0x00000018
	70
	71	#define REG_DSI_5nm_PHY_CMN_RBUF_CTRL 0x0000001c
	72
	73	#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_0 0x00000020
	74
	75	#define REG_DSI_5nm_PHY_CMN_CTRL_0 0x00000024
	76
	77	#define REG_DSI_5nm_PHY_CMN_CTRL_1 0x00000028
	78
	79	#define REG_DSI_5nm_PHY_CMN_CTRL_2 0x0000002c
	80
	81	#define REG_DSI_5nm_PHY_CMN_CTRL_3 0x00000030
	82
	83	#define REG_DSI_5nm_PHY_CMN_LANE_CFG0 0x00000034
	84
	85	#define REG_DSI_5nm_PHY_CMN_LANE_CFG1 0x00000038
	86
	87	#define REG_DSI_5nm_PHY_CMN_PLL_CNTRL 0x0000003c
	88
	89	#define REG_DSI_5nm_PHY_CMN_DPHY_SOT 0x00000040
	90
	91	#define REG_DSI_5nm_PHY_CMN_LANE_CTRL0 0x000000a0
	92
	93	#define REG_DSI_5nm_PHY_CMN_LANE_CTRL1 0x000000a4
	94
	95	#define REG_DSI_5nm_PHY_CMN_LANE_CTRL2 0x000000a8
	96
	97	#define REG_DSI_5nm_PHY_CMN_LANE_CTRL3 0x000000ac
	98
	99	#define REG_DSI_5nm_PHY_CMN_LANE_CTRL4 0x000000b0
	100
	101	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
	102
	103	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
	104
	105	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
	106
	107	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
	108
	109	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
	110
	111	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
	112
	113	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
	114
	115	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
	116
	117	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
	118
	119	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
	120
	121	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
	122
	123	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
	124
	125	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
	126
	127	#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
	128
	129	#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
	130
	131	#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
	132
	133	#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
	134
	135	#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
	136
	137	#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
	138
	139	#define REG_DSI_5nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
	140
	141	#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
	142
	143	#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
	144
	145	#define REG_DSI_5nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
	146
	147	#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_1 0x00000110
	148
	149	#define REG_DSI_5nm_PHY_CMN_CTRL_4 0x00000114
	150
	151	#define REG_DSI_5nm_PHY_CMN_PHY_STATUS 0x00000140
	152
	153	#define REG_DSI_5nm_PHY_CMN_LANE_STATUS0 0x00000148
	154
	155	#define REG_DSI_5nm_PHY_CMN_LANE_STATUS1 0x0000014c
	156
	157	static inline uint32_t REG_DSI_5nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
	158
	159	static inline uint32_t REG_DSI_5nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
	160
	161	static inline uint32_t REG_DSI_5nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
	162
	163	static inline uint32_t REG_DSI_5nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
	164
	165	static inline uint32_t REG_DSI_5nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
	166
	167	static inline uint32_t REG_DSI_5nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
	168
	169	static inline uint32_t REG_DSI_5nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
	170
	171	static inline uint32_t REG_DSI_5nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
	172
	173	#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
	174
	175	#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
	176
	177	#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
	178
	179	#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
	180
	181	#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
	182
	183	#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
	184
	185	#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
	186
	187	#define REG_DSI_5nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
	188
	189	#define REG_DSI_5nm_PHY_PLL_DSM_DIVIDER 0x00000020
	190
	191	#define REG_DSI_5nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
	192
	193	#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES 0x00000028
	194
	195	#define REG_DSI_5nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
	196
	197	#define REG_DSI_5nm_PHY_PLL_CMODE 0x00000030
	198
	199	#define REG_DSI_5nm_PHY_PLL_PSM_CTRL 0x00000034
	200
	201	#define REG_DSI_5nm_PHY_PLL_RSM_CTRL 0x00000038
	202
	203	#define REG_DSI_5nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
	204
	205	#define REG_DSI_5nm_PHY_PLL_PLL_CNTRL 0x00000040
	206
	207	#define REG_DSI_5nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
	208
	209	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
	210
	211	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
	212
	213	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
	214
	215	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MIN 0x00000054
	216
	217	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MAX 0x00000058
	218
	219	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
	220
	221	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
	222
	223	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
	224
	225	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
	226
	227	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
	228
	229	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
	230
	231	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
	232
	233	#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
	234
	235	#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
	236
	237	#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
	238
	239	#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
	240
	241	#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
	242
	243	#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
	244
	245	#define REG_DSI_5nm_PHY_PLL_PFILT 0x00000090
	246
	247	#define REG_DSI_5nm_PHY_PLL_IFILT 0x00000094
	248
	249	#define REG_DSI_5nm_PHY_PLL_PLL_GAIN 0x00000098
	250
	251	#define REG_DSI_5nm_PHY_PLL_ICODE_LOW 0x0000009c
	252
	253	#define REG_DSI_5nm_PHY_PLL_ICODE_HIGH 0x000000a0
	254
	255	#define REG_DSI_5nm_PHY_PLL_LOCKDET 0x000000a4
	256
	257	#define REG_DSI_5nm_PHY_PLL_OUTDIV 0x000000a8
	258
	259	#define REG_DSI_5nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
	260
	261	#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
	262
	263	#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
	264
	265	#define REG_DSI_5nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
	266
	267	#define REG_DSI_5nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
	268
	269	#define REG_DSI_5nm_PHY_PLL_RATE_CHANGE 0x000000c0
	270
	271	#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
	272
	273	#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
	274
	275	#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
	276
	277	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
	278
	279	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
	280
	281	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
	282
	283	#define REG_DSI_5nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
	284
	285	#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
	286
	287	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
	288
	289	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
	290
	291	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
	292
	293	#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
	294
	295	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
	296
	297	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
	298
	299	#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
	300
	301	#define REG_DSI_5nm_PHY_PLL_MASH_CONTROL 0x00000100
	302
	303	#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
	304
	305	#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
	306
	307	#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
	308
	309	#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
	310
	311	#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
	312
	313	#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
	314
	315	#define REG_DSI_5nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
	316
	317	#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
	318
	319	#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
	320
	321	#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
	322
	323	#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
	324
	325	#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
	326
	327	#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
	328
	329	#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
	330
	331	#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
	332
	333	#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
	334
	335	#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
	336
	337	#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
	338
	339	#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
	340
	341	#define REG_DSI_5nm_PHY_PLL_SSC_CONTROL 0x00000150
	342
	343	#define REG_DSI_5nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
	344
	345	#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
	346
	347	#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
	348
	349	#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
	350
	351	#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
	352
	353	#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
	354
	355	#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
	356
	357	#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
	358
	359	#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
	360
	361	#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
	362
	363	#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
	364
	365	#define REG_DSI_5nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
	366
	367	#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
	368
	369	#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
	370
	371	#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
	372
	373	#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
	374
	375	#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
	376
	377	#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
	378
	379	#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
	380
	381	#define REG_DSI_5nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
	382
	383	#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
	384
	385	#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
	386
	387	#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
	388
	389	#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
	390
	391	#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
	392
	393	#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
	394
	395	#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
	396
	397	#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
	398
	399	#define REG_DSI_5nm_PHY_PLL_FD_OUT_LOW 0x000001c4
	400
	401	#define REG_DSI_5nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
	402
	403	#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
	404
	405	#define REG_DSI_5nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
	406
	407	#define REG_DSI_5nm_PHY_PLL_FLL_CONFIG 0x000001d4
	408
	409	#define REG_DSI_5nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
	410
	411	#define REG_DSI_5nm_PHY_PLL_FLL_CODE0 0x000001dc
	412
	413	#define REG_DSI_5nm_PHY_PLL_FLL_CODE1 0x000001e0
	414
	415	#define REG_DSI_5nm_PHY_PLL_FLL_GAIN0 0x000001e4
	416
	417	#define REG_DSI_5nm_PHY_PLL_FLL_GAIN1 0x000001e8
	418
	419	#define REG_DSI_5nm_PHY_PLL_SW_RESET 0x000001ec
	420
	421	#define REG_DSI_5nm_PHY_PLL_FAST_PWRUP 0x000001f0
	422
	423	#define REG_DSI_5nm_PHY_PLL_LOCKTIME0 0x000001f4
	424
	425	#define REG_DSI_5nm_PHY_PLL_LOCKTIME1 0x000001f8
	426
	427	#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
	428
	429	#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS0 0x00000200
	430
	431	#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS1 0x00000204
	432
	433	#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS2 0x00000208
	434
	435	#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS3 0x0000020c
	436
	437	#define REG_DSI_5nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
	438
	439	#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG 0x00000214
	440
	441	#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
	442
	443	#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
	444
	445	#define REG_DSI_5nm_PHY_PLL_RESET_SM_STATUS 0x00000220
	446
	447	#define REG_DSI_5nm_PHY_PLL_TDC_OFFSET 0x00000224
	448
	449	#define REG_DSI_5nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
	450
	451	#define REG_DSI_5nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
	452
	453	#define REG_DSI_5nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
	454
	455	#define REG_DSI_5nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
	456
	457	#define REG_DSI_5nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
	458
	459	#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
	460
	461	#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_1 0x00000240
	462
	463	#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_2 0x00000244
	464
	465	#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
	466
	467	#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
	468
	469	#define REG_DSI_5nm_PHY_PLL_CMODE_1 0x00000250
	470
	471	#define REG_DSI_5nm_PHY_PLL_CMODE_2 0x00000254
	472
	473	#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
	474
	475	#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
	476
	477	#define REG_DSI_5nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
	478
	479
	480	#endif /* DSI_PHY_5NM_XML */

drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h+482−0

@@ -0,0 +1,482 @@
	1	#ifndef DSI_PHY_7NM_XML
	2	#define DSI_PHY_7NM_XML
	3
	4	/* Autogenerated file, DO NOT EDIT manually!
	5
	6	This file was generated by the rules-ng-ng headergen tool in this git repository:
	7	http://github.com/freedreno/envytools/
	8	git clone https://github.com/freedreno/envytools.git
	9
	10	The rules-ng-ng source files this header was generated from are:
	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
	22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
	24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
	25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
	26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
	27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
	28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
	29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
	30
	31	Copyright (C) 2013-2021 by the following authors:
	32	- Rob Clark <robdclark@gmail.com> (robclark)
	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
	34
	35	Permission is hereby granted, free of charge, to any person obtaining
	36	a copy of this software and associated documentation files (the
	37	"Software"), to deal in the Software without restriction, including
	38	without limitation the rights to use, copy, modify, merge, publish,
	39	distribute, sublicense, and/or sell copies of the Software, and to
	40	permit persons to whom the Software is furnished to do so, subject to
	41	the following conditions:
	42
	43	The above copyright notice and this permission notice (including the
	44	next paragraph) shall be included in all copies or substantial
	45	portions of the Software.
	46
	47	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	48	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	49	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	50	IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	51	LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	52	OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	53	WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	54	*/
	55
	56
	57	#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
	58
	59	#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
	60
	61	#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
	62
	63	#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
	64
	65	#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
	66
	67	#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
	68
	69	#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
	70
	71	#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
	72
	73	#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
	74
	75	#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
	76
	77	#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
	78
	79	#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
	80
	81	#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
	82
	83	#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
	84
	85	#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
	86
	87	#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
	88
	89	#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
	90
	91	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
	92
	93	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
	94
	95	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
	96
	97	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
	98
	99	#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
	100
	101	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
	102
	103	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
	104
	105	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
	106
	107	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
	108
	109	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
	110
	111	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
	112
	113	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
	114
	115	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
	116
	117	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
	118
	119	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
	120
	121	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
	122
	123	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
	124
	125	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
	126
	127	#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
	128
	129	#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
	130
	131	#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
	132
	133	#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
	134
	135	#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
	136
	137	#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
	138
	139	#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
	140
	141	#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
	142
	143	#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
	144
	145	#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
	146
	147	#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
	148
	149	#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
	150
	151	#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
	152
	153	#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
	154
	155	#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
	156
	157	#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
	158
	159	static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
	160
	161	static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
	162
	163	static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
	164
	165	static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
	166
	167	static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
	168
	169	static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
	170
	171	static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
	172
	173	static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
	174
	175	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
	176
	177	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
	178
	179	#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
	180
	181	#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
	182
	183	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
	184
	185	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
	186
	187	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
	188
	189	#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
	190
	191	#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
	192
	193	#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
	194
	195	#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
	196
	197	#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
	198
	199	#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
	200
	201	#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
	202
	203	#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
	204
	205	#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
	206
	207	#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
	208
	209	#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
	210
	211	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
	212
	213	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
	214
	215	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
	216
	217	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
	218
	219	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
	220
	221	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
	222
	223	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
	224
	225	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
	226
	227	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
	228
	229	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
	230
	231	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
	232
	233	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
	234
	235	#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
	236
	237	#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
	238
	239	#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
	240
	241	#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
	242
	243	#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
	244
	245	#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
	246
	247	#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
	248
	249	#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
	250
	251	#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
	252
	253	#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
	254
	255	#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
	256
	257	#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
	258
	259	#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
	260
	261	#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
	262
	263	#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
	264
	265	#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
	266
	267	#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
	268
	269	#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
	270
	271	#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
	272
	273	#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
	274
	275	#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
	276
	277	#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
	278
	279	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
	280
	281	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
	282
	283	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
	284
	285	#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
	286
	287	#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
	288
	289	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
	290
	291	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
	292
	293	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
	294
	295	#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
	296
	297	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
	298
	299	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
	300
	301	#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
	302
	303	#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
	304
	305	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
	306
	307	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
	308
	309	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
	310
	311	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
	312
	313	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
	314
	315	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
	316
	317	#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
	318
	319	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
	320
	321	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
	322
	323	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
	324
	325	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
	326
	327	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
	328
	329	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
	330
	331	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
	332
	333	#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
	334
	335	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
	336
	337	#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
	338
	339	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
	340
	341	#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
	342
	343	#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
	344
	345	#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
	346
	347	#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
	348
	349	#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
	350
	351	#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
	352
	353	#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
	354
	355	#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
	356
	357	#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
	358
	359	#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
	360
	361	#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
	362
	363	#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
	364
	365	#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
	366
	367	#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
	368
	369	#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
	370
	371	#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
	372
	373	#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
	374
	375	#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
	376
	377	#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
	378
	379	#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
	380
	381	#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
	382
	383	#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
	384
	385	#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
	386
	387	#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
	388
	389	#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
	390
	391	#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
	392
	393	#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
	394
	395	#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
	396
	397	#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
	398
	399	#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
	400
	401	#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
	402
	403	#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
	404
	405	#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
	406
	407	#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
	408
	409	#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
	410
	411	#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
	412
	413	#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
	414
	415	#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
	416
	417	#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
	418
	419	#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
	420
	421	#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
	422
	423	#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
	424
	425	#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
	426
	427	#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
	428
	429	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
	430
	431	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
	432
	433	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
	434
	435	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
	436
	437	#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
	438
	439	#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
	440
	441	#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
	442
	443	#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
	444
	445	#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
	446
	447	#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
	448
	449	#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
	450
	451	#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
	452
	453	#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
	454
	455	#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
	456
	457	#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
	458
	459	#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
	460
	461	#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
	462
	463	#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
	464
	465	#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
	466
	467	#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
	468
	469	#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
	470
	471	#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
	472
	473	#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
	474
	475	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
	476
	477	#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
	478
	479	#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
	480
	481
	482	#endif /* DSI_PHY_7NM_XML */

drivers/gpu/drm/msm/dsi/mmss_cc.xml.h+21−13

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c+27−4

 	phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
 				"qcom,dsi-phy-regulator-ldo-mode");
-	phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
+	phy->base = msm_ioremap_size(pdev, "dsi_phy", "DSI_PHY", &phy->base_size);
 	if (IS_ERR(phy->base)) {
 		DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
 		ret = -ENOMEM;
 		goto fail;
 	}
-	phy->pll_base = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
+	phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", "DSI_PLL", &phy->pll_size);
 	if (IS_ERR(phy->pll_base)) {
 		DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
 		ret = -ENOMEM;
 	}
 	if (phy->cfg->has_phy_lane) {
-		phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");
+		phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", "DSI_PHY_LANE", &phy->lane_size);
 		if (IS_ERR(phy->lane_base)) {
 			DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__);
 			ret = -ENOMEM;
 	}
 	if (phy->cfg->has_phy_regulator) {
-		phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG");
+		phy->reg_base = msm_ioremap_size(pdev, "dsi_phy_regulator", "DSI_PHY_REG", &phy->reg_size);
 		if (IS_ERR(phy->reg_base)) {
 			DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__);
 			ret = -ENOMEM;
 	return 0;
 }
+void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy)
+{
+	msm_disp_snapshot_add_block(disp_state,
+			phy->base_size, phy->base,
+			"dsi%d_phy", phy->id);
+	/* Do not try accessing PLL registers if it is switched off */
+	if (phy->pll_on)
+		msm_disp_snapshot_add_block(disp_state,
+			phy->pll_size, phy->pll_base,
+			"dsi%d_pll", phy->id);
+	if (phy->lane_base)
+		msm_disp_snapshot_add_block(disp_state,
+			phy->lane_size, phy->lane_base,
+			"dsi%d_lane", phy->id);
+	if (phy->reg_base)
+		msm_disp_snapshot_add_block(disp_state,
+			phy->reg_size, phy->reg_base,
+			"dsi%d_reg", phy->id);
+}

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h+4−0

 	void __iomem *pll_base;
 	void __iomem *reg_base;
 	void __iomem *lane_base;
+	phys_addr_t base_size;
+	phys_addr_t pll_size;
+	phys_addr_t reg_size;
+	phys_addr_t lane_size;
 	int id;
 	struct clk *ahb_clk;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c+1−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9		9
10	#include "dsi_phy.h"	10	#include "dsi_phy.h"
11	#include "dsi.xml.h"	11	#include "dsi.xml.h"
		12	#include "dsi_phy_10nm.xml.h"
12		13
13	/*	14	/*
14	* DSI PLL 10nm - clock diagram (eg: DSI0):	15	* DSI PLL 10nm - clock diagram (eg: DSI0):

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c+1−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9		9
10	#include "dsi_phy.h"	10	#include "dsi_phy.h"
11	#include "dsi.xml.h"	11	#include "dsi.xml.h"
		12	#include "dsi_phy_14nm.xml.h"
12		13
13	#define PHY_14NM_CKLN_IDX 4	14	#define PHY_14NM_CKLN_IDX 4
14		15

drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c+1−0

@@ -5,6 +5,7 @@ · 4 unmodified lines
5		5
6	#include "dsi_phy.h"	6	#include "dsi_phy.h"
7	#include "dsi.xml.h"	7	#include "dsi.xml.h"
		8	#include "dsi_phy_20nm.xml.h"
8		9
9	static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy,	10	static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy,
10	struct msm_dsi_dphy_timing *timing)	11	struct msm_dsi_dphy_timing *timing)

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c+1−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8		8
9	#include "dsi_phy.h"	9	#include "dsi_phy.h"
10	#include "dsi.xml.h"	10	#include "dsi.xml.h"
		11	#include "dsi_phy_28nm.xml.h"
11		12
12	/*	13	/*
13	* DSI PLL 28nm - clock diagram (eg: DSI0):	14	* DSI PLL 28nm - clock diagram (eg: DSI0):

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c+1−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8		8
9	#include "dsi_phy.h"	9	#include "dsi_phy.h"
10	#include "dsi.xml.h"	10	#include "dsi.xml.h"
		11	#include "dsi_phy_28nm_8960.xml.h"
11		12
12	/*	13	/*
13	* DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1):	14	* DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1):

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c+6−1

 #include "dsi_phy.h"
 #include "dsi.xml.h"
+#include "dsi_phy_7nm.xml.h"
 /*
  * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
 		.restore_pll_state = dsi_7nm_pll_restore_state,
 	},
 	.min_pll_rate = 600000000UL,
-	.max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
+#ifdef CONFIG_64BIT
+	.max_pll_rate = 5000000000UL,
+#else
+	.max_pll_rate = ULONG_MAX,
+#endif
 	.io_start = { 0xae94400, 0xae96400 },
 	.num_dsi_phy = 2,
 	.quirks = DSI_PHY_7NM_QUIRK_V4_1,

drivers/gpu/drm/msm/dsi/sfpb.xml.h+21−13

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34

drivers/gpu/drm/msm/edp/edp.xml.h+21−13

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34

drivers/gpu/drm/msm/hdmi/hdmi.xml.h+21−13

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34

drivers/gpu/drm/msm/hdmi/qfprom.xml.h+21−13

@@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ · 7 unmodified lines
8	git clone https://github.com/freedreno/envytools.git	8	git clone https://github.com/freedreno/envytools.git
9		9
10	The rules-ng-ng source files this header was generated from are:	10	The rules-ng-ng source files this header was generated from are:
11	- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)	11	- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12	- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)	12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13	- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)	13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14	- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)	14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15	- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)	15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16	- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)	16	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17	- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)	17	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18	- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)	18	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19	- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)	19	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20	- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)	20	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21	- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)	21	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22		22	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23	Copyright (C) 2013-2020 by the following authors:	23	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
		24	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
		25	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
		26	- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
		27	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
		28	- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
		29	- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
		30
		31	Copyright (C) 2013-2021 by the following authors:
24	- Rob Clark <robdclark@gmail.com> (robclark)	32	- Rob Clark <robdclark@gmail.com> (robclark)
25	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)	33	- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26		34

drivers/gpu/drm/msm/msm_debugfs.c+31−0

@@ -108,6 +108,31 @@ static const struct file_operations msm_gpu_fops = { · 107 unmodified lines
108	.release = msm_gpu_release,	108	.release = msm_gpu_release,
109	};	109	};
110		110
		111	static unsigned long last_shrink_freed;
		112
		113	static int
		114	shrink_get(void data, u64 val)
		115	{
		116	*val = last_shrink_freed;
		117
		118	return 0;
		119	}
		120
		121	static int
		122	shrink_set(void *data, u64 val)
		123	{
		124	struct drm_device *dev = data;
		125
		126	last_shrink_freed = msm_gem_shrinker_shrink(dev, val);
		127
		128	return 0;
		129	}
		130
		131	DEFINE_SIMPLE_ATTRIBUTE(shrink_fops,
		132	shrink_get, shrink_set,
		133	"0x%08llx\n");
		134
		135
111	static int msm_gem_show(struct drm_device dev, struct seq_file m)	136	static int msm_gem_show(struct drm_device dev, struct seq_file m)
112	{	137	{
113	struct msm_drm_private *priv = dev->dev_private;	138	struct msm_drm_private *priv = dev->dev_private;
@@ -226,6 +251,12 @@ void msm_debugfs_init(struct drm_minor *minor) · 112 unmodified lines
226	debugfs_create_file("gpu", S_IRUSR, minor->debugfs_root,	251	debugfs_create_file("gpu", S_IRUSR, minor->debugfs_root,
227	dev, &msm_gpu_fops);	252	dev, &msm_gpu_fops);
228		253
		254	debugfs_create_u32("hangcheck_period_ms", 0600, minor->debugfs_root,
		255	&priv->hangcheck_period);
		256
		257	debugfs_create_file("shrink", S_IRWXU, minor->debugfs_root,
		258	dev, &shrink_fops);
		259
229	if (priv->kms && priv->kms->funcs->debugfs_init)	260	if (priv->kms && priv->kms->funcs->debugfs_init)
230	priv->kms->funcs->debugfs_init(priv->kms, minor);	261	priv->kms->funcs->debugfs_init(priv->kms, minor);
231	}	262	}

drivers/gpu/drm/msm/msm_drv.c+26−7

 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  */
 #include <drm/drm_of.h>
 #include <drm/drm_vblank.h>
+#include "disp/msm_disp_snapshot.h"
 #include "msm_drv.h"
 #include "msm_debugfs.h"
 #include "msm_fence.h"
  * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
  * - 1.6.0 - Syncobj support
  * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
+ * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
  */
 #define MSM_VERSION_MAJOR	1
-#define MSM_VERSION_MINOR	7
+#define MSM_VERSION_MINOR	8
 #define MSM_VERSION_PATCHLEVEL	0
 static const struct drm_mode_config_funcs mode_config_funcs = {
 }
 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
-				  const char *dbgname, bool quiet)
+				  const char *dbgname, bool quiet, phys_addr_t *psize)
 {
 	struct resource *res;
 	unsigned long size;
 	if (reglog)
 		printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
+	if (psize)
+		*psize = size;
 	return ptr;
 }
 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
 			  const char *dbgname)
 {
-	return _msm_ioremap(pdev, name, dbgname, false);
+	return _msm_ioremap(pdev, name, dbgname, false, NULL);
 }
 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
 				const char *dbgname)
 {
-	return _msm_ioremap(pdev, name, dbgname, true);
+	return _msm_ioremap(pdev, name, dbgname, true, NULL);
+}
+void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
+			  const char *dbgname, phys_addr_t *psize)
+{
+	return _msm_ioremap(pdev, name, dbgname, false, psize);
 }
 void msm_writel(u32 data, void __iomem *addr)
 		msm_fbdev_free(ddev);
 #endif
+	msm_disp_snapshot_destroy(ddev);
 	drm_mode_config_cleanup(ddev);
 	pm_runtime_get_sync(dev);
 	mdss = priv->mdss;
 	priv->wq = alloc_ordered_workqueue("msm", 0);
+	priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
 	INIT_LIST_HEAD(&priv->objects);
 	mutex_init(&priv->obj_lock);
 		priv->event_thread[i].worker = kthread_create_worker(0,
 			"crtc_event:%d", priv->event_thread[i].crtc_id);
 		if (IS_ERR(priv->event_thread[i].worker)) {
+			ret = PTR_ERR(priv->event_thread[i].worker);
 			DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
 			goto err_msm_uninit;
 		}
 	if (ret)
 		goto err_msm_uninit;
+	ret = msm_disp_snapshot_init(ddev);
+	if (ret)
+		DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
 	drm_mode_config_reset(ddev);
 #ifdef CONFIG_DRM_FBDEV_EMULATION
 	struct msm_kms *kms = priv->kms;
 	if (!kms)
 		return -ENXIO;
-	DBG("dev=%p, crtc=%u", dev, pipe);
+	drm_dbg_vbl(dev, "crtc=%u", pipe);
 	return vblank_ctrl_queue_work(priv, pipe, true);
 }
 	struct msm_kms *kms = priv->kms;
 	if (!kms)
 		return;
-	DBG("dev=%p, crtc=%u", dev, pipe);
+	drm_dbg_vbl(dev, "crtc=%u", pipe);
 	vblank_ctrl_queue_work(priv, pipe, false);
 }

drivers/gpu/drm/msm/msm_drv.h+23−1

 struct msm_fence_context;
 struct msm_gem_address_space;
 struct msm_gem_vma;
+struct msm_disp_state;
 #define MAX_CRTCS      8
 #define MAX_PLANES     20
 	struct msm_file_private *lastctx;
 	/* gpu is only set on open(), but we need this info earlier */
 	bool is_a2xx;
+	bool has_cached_coherent;
 	struct drm_fb_helper *fbdev;
 	struct shrinker shrinker;
 	struct drm_atomic_state *pm_state;
+	/* For hang detection, in ms */
+	unsigned int hangcheck_period;
 };
 struct msm_format {
 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
 		struct drm_file *file);
+#ifdef CONFIG_DEBUG_FS
+unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
+#endif
 void msm_gem_shrinker_init(struct drm_device *dev);
 void msm_gem_shrinker_cleanup(struct drm_device *dev);
 void __exit msm_dsi_unregister(void);
 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
 			 struct drm_encoder *encoder);
+void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
 #else
 static inline void __init msm_dsi_register(void)
 {
 {
 	return -EINVAL;
 }
+static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
+{
+}
 #endif
 #ifdef CONFIG_DRM_MSM_DP
 				struct drm_display_mode *mode,
 				struct drm_display_mode *adjusted_mode);
 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
+void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
 {
 }
+static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
+{
+}
 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
 		struct drm_minor *minor)
 {
 	const char *name);
 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
 		const char *dbgname);
+void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
+		const char *dbgname, phys_addr_t *size);
 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
 		const char *dbgname);
 void msm_writel(u32 data, void __iomem *addr);
 /* for the generated headers: */
 #define INVALID_IDX(idx) ({BUG(); 0;})
 #define fui(x)                ({BUG(); 0;})
-#define util_float_to_half(x) ({BUG(); 0;})
+#define _mesa_float_to_half(x) ({BUG(); 0;})
 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)

drivers/gpu/drm/msm/msm_fb.c+4−4

@@ -61,7 +61,7 @@ int msm_framebuffer_prepare(struct drm_framebuffer *fb, · 60 unmodified lines
61		61
62	for (i = 0; i < n; i++) {	62	for (i = 0; i < n; i++) {
63	ret = msm_gem_get_and_pin_iova(fb->obj[i], aspace, &iova);	63	ret = msm_gem_get_and_pin_iova(fb->obj[i], aspace, &iova);
64	DBG("FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret);	64	drm_dbg_state(fb->dev, "FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret);
65	if (ret)	65	if (ret)
66	return ret;	66	return ret;
67	}	67	}
@@ -140,8 +140,8 @@ static struct drm_framebuffer msm_framebuffer_init(struct drm_device dev, · 72 unmodified lines
140	const struct msm_format *format;	140	const struct msm_format *format;
141	int ret, i, n;	141	int ret, i, n;
142		142
143	DBG("create framebuffer: dev=%p, mode_cmd=%p (%dx%d@%4.4s)",	143	drm_dbg_state(dev, "create framebuffer: mode_cmd=%p (%dx%d@%4.4s)",
144	dev, mode_cmd, mode_cmd->width, mode_cmd->height,	144	mode_cmd, mode_cmd->width, mode_cmd->height,
145	(char *)&mode_cmd->pixel_format);	145	(char *)&mode_cmd->pixel_format);
146		146
147	n = info->num_planes;	147	n = info->num_planes;
@@ -194,7 +194,7 @@ static struct drm_framebuffer msm_framebuffer_init(struct drm_device dev, · 46 unmodified lines
194	goto fail;	194	goto fail;
195	}	195	}
196		196
197	DBG("create: FB ID: %d (%p)", fb->base.id, fb);	197	drm_dbg_state(dev, "create: FB ID: %d (%p)", fb->base.id, fb);
198		198
199	return fb;	199	return fb;
200		200

drivers/gpu/drm/msm/msm_gem.c+19−19

@@ -211,6 +211,13 @@ void msm_gem_put_pages(struct drm_gem_object *obj) · 210 unmodified lines
211	msm_gem_unlock(obj);	211	msm_gem_unlock(obj);
212	}	212	}
213		213
		214	static pgprot_t msm_gem_pgprot(struct msm_gem_object *msm_obj, pgprot_t prot)
		215	{
		216	if (msm_obj->flags & (MSM_BO_WC\|MSM_BO_UNCACHED))
		217	return pgprot_writecombine(prot);
		218	return prot;
		219	}
		220
214	int msm_gem_mmap_obj(struct drm_gem_object *obj,	221	int msm_gem_mmap_obj(struct drm_gem_object *obj,
215	struct vm_area_struct *vma)	222	struct vm_area_struct *vma)
216	{	223	{
@@ -218,22 +225,7 @@ int msm_gem_mmap_obj(struct drm_gem_object *obj, · 1 unmodified line
218		225
219	vma->vm_flags &= ~VM_PFNMAP;	226	vma->vm_flags &= ~VM_PFNMAP;
220	vma->vm_flags \|= VM_MIXEDMAP;	227	vma->vm_flags \|= VM_MIXEDMAP;
221		228	vma->vm_page_prot = msm_gem_pgprot(msm_obj, vm_get_page_prot(vma->vm_flags));
222	if (msm_obj->flags & MSM_BO_WC) {
223	vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
224	} else if (msm_obj->flags & MSM_BO_UNCACHED) {
225	vma->vm_page_prot = pgprot_noncached(vm_get_page_prot(vma->vm_flags));
226	} else {
227	/*
228	* Shunt off cached objs to shmem file so they have their own
229	* address_space (so unmap_mapping_range does what we want,
230	* in particular in the case of mmap'd dmabufs)
231	*/
232	vma->vm_pgoff = 0;
233	vma_set_file(vma, obj->filp);
234
235	vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
236	}
237		229
238	return 0;	230	return 0;
239	}	231	}
@@ -372,7 +364,7 @@ static void del_vma(struct msm_gem_vma *vma) · 132 unmodified lines
372	kfree(vma);	364	kfree(vma);
373	}	365	}
374		366
375	/**	367	/*
376	* If close is true, this also closes the VMA (releasing the allocated	368	* If close is true, this also closes the VMA (releasing the allocated
377	* iova range) in addition to removing the iommu mapping. In the eviction	369	* iova range) in addition to removing the iommu mapping. In the eviction
378	* case (!close), we keep the iova allocated, but only remove the iommu	370	* case (!close), we keep the iova allocated, but only remove the iommu
@@ -451,6 +443,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj, · 72 unmodified lines
451	if (msm_obj->flags & MSM_BO_MAP_PRIV)	443	if (msm_obj->flags & MSM_BO_MAP_PRIV)
452	prot \|= IOMMU_PRIV;	444	prot \|= IOMMU_PRIV;
453		445
		446	if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
		447	prot \|= IOMMU_CACHE;
		448
454	GEM_WARN_ON(!msm_gem_is_locked(obj));	449	GEM_WARN_ON(!msm_gem_is_locked(obj));
455		450
456	if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))	451	if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
@@ -653,7 +648,7 @@ static void get_vaddr(struct drm_gem_object obj, unsigned madv) · 196 unmodified lines
653	goto fail;	648	goto fail;
654	}	649	}
655	msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT,	650	msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT,
656	VM_MAP, pgprot_writecombine(PAGE_KERNEL));	651	VM_MAP, msm_gem_pgprot(msm_obj, PAGE_KERNEL));
657	if (msm_obj->vaddr == NULL) {	652	if (msm_obj->vaddr == NULL) {
658	ret = -ENOMEM;	653	ret = -ENOMEM;
659	goto fail;	654	goto fail;
@@ -773,7 +768,7 @@ void msm_gem_purge(struct drm_gem_object *obj) · 113 unmodified lines
773	0, (loff_t)-1);	768	0, (loff_t)-1);
774	}	769	}
775		770
776	/**	771	/*
777	* Unpin the backing pages and make them available to be swapped out.	772	* Unpin the backing pages and make them available to be swapped out.
778	*/	773	*/
779	void msm_gem_evict(struct drm_gem_object *obj)	774	void msm_gem_evict(struct drm_gem_object *obj)
@@ -1163,6 +1158,7 @@ static int msm_gem_new_impl(struct drm_device *dev, · 383 unmodified lines
1163	uint32_t size, uint32_t flags,	1158	uint32_t size, uint32_t flags,
1164	struct drm_gem_object **obj)	1159	struct drm_gem_object **obj)
1165	{	1160	{
		1161	struct msm_drm_private *priv = dev->dev_private;
1166	struct msm_gem_object *msm_obj;	1162	struct msm_gem_object *msm_obj;
1167		1163
1168	switch (flags & MSM_BO_CACHE_MASK) {	1164	switch (flags & MSM_BO_CACHE_MASK) {
@@ -1170,6 +1166,10 @@ static int msm_gem_new_impl(struct drm_device *dev, · 1 unmodified line
1170	case MSM_BO_CACHED:	1166	case MSM_BO_CACHED:
1171	case MSM_BO_WC:	1167	case MSM_BO_WC:
1172	break;	1168	break;
		1169	case MSM_BO_CACHED_COHERENT:
		1170	if (priv->has_cached_coherent)
		1171	break;
		1172	/* fallthrough */
1173	default:	1173	default:
1174	DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",	1174	DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
1175	(flags & MSM_BO_CACHE_MASK));	1175	(flags & MSM_BO_CACHE_MASK));

drivers/gpu/drm/msm/msm_gem.h+1−0

@@ -328,6 +328,7 @@ struct msm_gem_submit { · 327 unmodified lines
328	struct dma_fence *fence;	328	struct dma_fence *fence;
329	struct msm_gpu_submitqueue *queue;	329	struct msm_gpu_submitqueue *queue;
330	struct pid pid; / submitting process */	330	struct pid pid; / submitting process */
		331	bool fault_dumped; /* Limit devcoredump dumping to one per submit */
331	bool valid; /* true if no cmdstream patching needed */	332	bool valid; /* true if no cmdstream patching needed */
332	bool in_rb; /* "sudo" mode, copy cmds into RB */	333	bool in_rb; /* "sudo" mode, copy cmds into RB */
333	struct msm_ringbuffer *ring;	334	struct msm_ringbuffer *ring;

drivers/gpu/drm/msm/msm_gem_shrinker.c+18−0

@@ -145,6 +145,24 @@ msm_gem_shrinker_scan(struct shrinker shrinker, struct shrink_control sc) · 144 unmodified lines
145	return (freed > 0) ? freed : SHRINK_STOP;	145	return (freed > 0) ? freed : SHRINK_STOP;
146	}	146	}
147		147
		148	#ifdef CONFIG_DEBUG_FS
		149	unsigned long
		150	msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan)
		151	{
		152	struct msm_drm_private *priv = dev->dev_private;
		153	struct shrink_control sc = {
		154	.nr_to_scan = nr_to_scan,
		155	};
		156	int ret;
		157
		158	fs_reclaim_acquire(GFP_KERNEL);
		159	ret = msm_gem_shrinker_scan(&priv->shrinker, &sc);
		160	fs_reclaim_release(GFP_KERNEL);
		161
		162	return ret;
		163	}
		164	#endif
		165
148	/* since we don't know any better, lets bail after a few	166	/* since we don't know any better, lets bail after a few
149	* and if necessary the shrinker will be invoked again.	167	* and if necessary the shrinker will be invoked again.
150	* Seems better than unmapping everything	168	* Seems better than unmapping everything

drivers/gpu/drm/msm/msm_gem_submit.c+1−0

@@ -50,6 +50,7 @@ static struct msm_gem_submit submit_create(struct drm_device dev, · 49 unmodified lines
50	submit->cmd = (void *)&submit->bos[nr_bos];	50	submit->cmd = (void *)&submit->bos[nr_bos];
51	submit->queue = queue;	51	submit->queue = queue;
52	submit->ring = gpu->rb[queue->prio];	52	submit->ring = gpu->rb[queue->prio];
		53	submit->fault_dumped = false;
53		54
54	/* initially, until copy_from_user() and bo lookup succeeds: */	55	/* initially, until copy_from_user() and bo lookup succeeds: */
55	submit->nr_bos = 0;	56	submit->nr_bos = 0;

drivers/gpu/drm/msm/msm_gpu.c+50−1

@@ -387,6 +387,7 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, · 386 unmodified lines
387	/* Fill in the additional crash state information */	387	/* Fill in the additional crash state information */
388	state->comm = kstrdup(comm, GFP_KERNEL);	388	state->comm = kstrdup(comm, GFP_KERNEL);
389	state->cmd = kstrdup(cmd, GFP_KERNEL);	389	state->cmd = kstrdup(cmd, GFP_KERNEL);
		390	state->fault_info = gpu->fault_info;
390		391
391	if (submit) {	392	if (submit) {
392	int i, nr = 0;	393	int i, nr = 0;
@@ -559,10 +560,57 @@ static void recover_worker(struct kthread_work *work) · 166 unmodified lines
559	msm_gpu_retire(gpu);	560	msm_gpu_retire(gpu);
560	}	561	}
561		562
		563	static void fault_worker(struct kthread_work *work)
		564	{
		565	struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
		566	struct drm_device *dev = gpu->dev;
		567	struct msm_gem_submit *submit;
		568	struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
		569	char comm = NULL, cmd = NULL;
		570
		571	mutex_lock(&dev->struct_mutex);
		572
		573	submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
		574	if (submit && submit->fault_dumped)
		575	goto resume_smmu;
		576
		577	if (submit) {
		578	struct task_struct *task;
		579
		580	task = get_pid_task(submit->pid, PIDTYPE_PID);
		581	if (task) {
		582	comm = kstrdup(task->comm, GFP_KERNEL);
		583	cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
		584	put_task_struct(task);
		585	}
		586
		587	/*
		588	* When we get GPU iova faults, we can get 1000s of them,
		589	* but we really only want to log the first one.
		590	*/
		591	submit->fault_dumped = true;
		592	}
		593
		594	/* Record the crash state */
		595	pm_runtime_get_sync(&gpu->pdev->dev);
		596	msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
		597	pm_runtime_put_sync(&gpu->pdev->dev);
		598
		599	kfree(cmd);
		600	kfree(comm);
		601
		602	resume_smmu:
		603	memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
		604	gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
		605
		606	mutex_unlock(&dev->struct_mutex);
		607	}
		608
562	static void hangcheck_timer_reset(struct msm_gpu *gpu)	609	static void hangcheck_timer_reset(struct msm_gpu *gpu)
563	{	610	{
		611	struct msm_drm_private *priv = gpu->dev->dev_private;
564	mod_timer(&gpu->hangcheck_timer,	612	mod_timer(&gpu->hangcheck_timer,
565	round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));	613	round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
566	}	614	}
567		615
568	static void hangcheck_handler(struct timer_list *t)	616	static void hangcheck_handler(struct timer_list *t)
@@ -922,6 +970,7 @@ int msm_gpu_init(struct drm_device drm, struct platform_device pdev, · 353 unmodified lines
922	INIT_LIST_HEAD(&gpu->active_list);	970	INIT_LIST_HEAD(&gpu->active_list);
923	kthread_init_work(&gpu->retire_work, retire_worker);	971	kthread_init_work(&gpu->retire_work, retire_worker);
924	kthread_init_work(&gpu->recover_work, recover_worker);	972	kthread_init_work(&gpu->recover_work, recover_worker);
		973	kthread_init_work(&gpu->fault_work, fault_worker);
925		974
926	timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);	975	timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
927		976

drivers/gpu/drm/msm/msm_gpu.h+18−11

 	uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
 };
+/* Additional state for iommu faults: */
+struct msm_gpu_fault_info {
+	u64 ttbr0;
+	unsigned long iova;
+	int flags;
+	const char *type;
+	const char *block;
+};
 struct msm_gpu {
 	const char *name;
 	struct drm_device *dev;
 	struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
 	uint32_t fast_rate;
-	/* The gfx-mem interconnect path that's used by all GPU types. */
-	struct icc_path *icc_path;
-	/*
-	 * Second interconnect path for some A3xx and all A4xx GPUs to the
-	 * On Chip MEMory (OCMEM).
-	 */
-	struct icc_path *ocmem_icc_path;
 	/* Hang and Inactivity Detection:
 	 */
 #define DRM_MSM_INACTIVE_PERIOD   66 /* in ms (roughly four frames) */
-#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
+#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
-#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
 	struct timer_list hangcheck_timer;
+	/* Fault info for most recent iova fault: */
+	struct msm_gpu_fault_info fault_info;
+	/* work for handling GPU ioval faults: */
+	struct kthread_work fault_work;
 	/* work for handling GPU recovery: */
 	struct kthread_work recover_work;
 	char *comm;
 	char *cmd;
+	struct msm_gpu_fault_info fault_info;
 	int nr_bos;
 	struct msm_gpu_state_bo *bos;
 };

drivers/gpu/drm/msm/msm_gpummu.c+5−0

 	return 0;
 }
+static void msm_gpummu_resume_translation(struct msm_mmu *mmu)
+{
+}
 static void msm_gpummu_destroy(struct msm_mmu *mmu)
 {
 	struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
 		.map = msm_gpummu_map,
 		.unmap = msm_gpummu_unmap,
 		.destroy = msm_gpummu_destroy,
+		.resume_translation = msm_gpummu_resume_translation,
 };
 struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)

drivers/gpu/drm/msm/msm_iommu.c+21−1

 	 * the arm-smmu driver as a trigger to set up TTBR0
 	 */
 	if (atomic_inc_return(&iommu->pagetables) == 1) {
+		/* Enable stall on iommu fault: */
+		adreno_smmu->set_stall(adreno_smmu->cookie, true);
 		ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg);
 		if (ret) {
 			free_io_pgtable_ops(pagetable->pgtbl_ops);
 		unsigned long iova, int flags, void *arg)
 {
 	struct msm_iommu *iommu = arg;
+	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev);
+	struct adreno_smmu_fault_info info, *ptr = NULL;
+	if (adreno_smmu->get_fault_info) {
+		adreno_smmu->get_fault_info(adreno_smmu->cookie, &info);
+		ptr = &info;
+	}
 	if (iommu->base.handler)
-		return iommu->base.handler(iommu->base.arg, iova, flags);
+		return iommu->base.handler(iommu->base.arg, iova, flags, ptr);
 	pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags);
 	return 0;
 }
+static void msm_iommu_resume_translation(struct msm_mmu *mmu)
+{
+	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev);
+	adreno_smmu->resume_translation(adreno_smmu->cookie, true);
+}
 static void msm_iommu_detach(struct msm_mmu *mmu)
 {
 	struct msm_iommu *iommu = to_msm_iommu(mmu);
 		.map = msm_iommu_map,
 		.unmap = msm_iommu_unmap,
 		.destroy = msm_iommu_destroy,
+		.resume_translation = msm_iommu_resume_translation,
 };
 struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)

drivers/gpu/drm/msm/msm_kms.h+9−0

 				 bool cmd_mode);
 	/* cleanup: */
 	void (*destroy)(struct msm_kms *kms);
+	/* snapshot: */
+	void (*snapshot)(struct msm_disp_state *disp_state, struct msm_kms *kms);
 #ifdef CONFIG_DEBUG_FS
 	/* debugfs: */
 	int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor);
 	/* mapper-id used to request GEM buffer mapped for scanout: */
 	struct msm_gem_address_space *aspace;
+	/* disp snapshot support */
+	struct kthread_worker *dump_worker;
+	struct kthread_work dump_work;
+	struct mutex dump_mutex;
 	/*
 	 * For async commit, where ->flush_commit() and later happens
 	 * from the crtc's pending_timer close to end of the frame:

drivers/gpu/drm/msm/msm_mmu.h+3−2

 			size_t len, int prot);
 	int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len);
 	void (*destroy)(struct msm_mmu *mmu);
+	void (*resume_translation)(struct msm_mmu *mmu);
 };
 enum msm_mmu_type {
 struct msm_mmu {
 	const struct msm_mmu_funcs *funcs;
 	struct device *dev;
-	int (*handler)(void *arg, unsigned long iova, int flags);
+	int (*handler)(void *arg, unsigned long iova, int flags, void *data);
 	void *arg;
 	enum msm_mmu_type type;
 };
 struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
 static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
-		int (*handler)(void *arg, unsigned long iova, int flags))
+		int (*handler)(void *arg, unsigned long iova, int flags, void *data))
 {
 	mmu->arg = arg;
 	mmu->handler = handler;

drivers/gpu/drm/selftests/test-drm_framebuffer.c+1−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8	#include <drm/drm_device.h>	8	#include <drm/drm_device.h>
9	#include <drm/drm_mode.h>	9	#include <drm/drm_mode.h>
10	#include <drm/drm_fourcc.h>	10	#include <drm/drm_fourcc.h>
		11	#include <drm/drm_print.h>
11		12
12	#include "../drm_crtc_internal.h"	13	#include "../drm_crtc_internal.h"
13		14

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c+50−0

@@ -13,6 +13,7 @@ struct qcom_smmu { · 12 unmodified lines
13	struct arm_smmu_device smmu;	13	struct arm_smmu_device smmu;
14	bool bypass_quirk;	14	bool bypass_quirk;
15	u8 bypass_cbndx;	15	u8 bypass_cbndx;
		16	u32 stall_enabled;
16	};	17	};
17		18
18	static struct qcom_smmu to_qcom_smmu(struct arm_smmu_device smmu)	19	static struct qcom_smmu to_qcom_smmu(struct arm_smmu_device smmu)
@@ -23,15 +24,61 @@ static struct qcom_smmu to_qcom_smmu(struct arm_smmu_device smmu) · 4 unmodified lines
23	static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,	24	static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
24	u32 reg)	25	u32 reg)
25	{	26	{
		27	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
		28
26	/*	29	/*
27	* On the GPU device we want to process subsequent transactions after a	30	* On the GPU device we want to process subsequent transactions after a
28	* fault to keep the GPU from hanging	31	* fault to keep the GPU from hanging
29	*/	32	*/
30	reg \|= ARM_SMMU_SCTLR_HUPCF;	33	reg \|= ARM_SMMU_SCTLR_HUPCF;
31		34
		35	if (qsmmu->stall_enabled & BIT(idx))
		36	reg \|= ARM_SMMU_SCTLR_CFCFG;
		37
32	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);	38	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
33	}	39	}
34		40
		41	static void qcom_adreno_smmu_get_fault_info(const void *cookie,
		42	struct adreno_smmu_fault_info *info)
		43	{
		44	struct arm_smmu_domain smmu_domain = (void )cookie;
		45	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
		46	struct arm_smmu_device *smmu = smmu_domain->smmu;
		47
		48	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
		49	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
		50	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
		51	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
		52	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
		53	info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
		54	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
		55	}
		56
		57	static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
		58	{
		59	struct arm_smmu_domain smmu_domain = (void )cookie;
		60	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
		61	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
		62
		63	if (enabled)
		64	qsmmu->stall_enabled \|= BIT(cfg->cbndx);
		65	else
		66	qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
		67	}
		68
		69	static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate)
		70	{
		71	struct arm_smmu_domain smmu_domain = (void )cookie;
		72	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
		73	struct arm_smmu_device *smmu = smmu_domain->smmu;
		74	u32 reg = 0;
		75
		76	if (terminate)
		77	reg \|= ARM_SMMU_RESUME_TERMINATE;
		78
		79	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
		80	}
		81
35	#define QCOM_ADRENO_SMMU_GPU_SID 0	82	#define QCOM_ADRENO_SMMU_GPU_SID 0
36		83
37	static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)	84	static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
@@ -156,6 +203,9 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, · 118 unmodified lines
156	priv->cookie = smmu_domain;	203	priv->cookie = smmu_domain;
157	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;	204	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
158	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;	205	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
		206	priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
		207	priv->set_stall = qcom_adreno_smmu_set_stall;
		208	priv->resume_translation = qcom_adreno_smmu_resume_translation;
159		209
160	return 0;	210	return 0;
161	}	211	}

drivers/iommu/arm/arm-smmu/arm-smmu.c+7−2

 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 	struct arm_smmu_device *smmu = smmu_domain->smmu;
 	int idx = smmu_domain->cfg.cbndx;
+	int ret;
 	fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
 	if (!(fsr & ARM_SMMU_FSR_FAULT))
 	iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
 	cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
-	dev_err_ratelimited(smmu->dev,
+	ret = report_iommu_fault(domain, NULL, iova,
-	"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
+		fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+	if (ret == -ENOSYS)
+		dev_err_ratelimited(smmu->dev,
+		"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
 			    fsr, iova, fsynr, cbfrsynra, idx);
 	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);

drivers/iommu/arm/arm-smmu/arm-smmu.h+2−0

@@ -224,6 +224,8 @@ enum arm_smmu_cbar_type { · 223 unmodified lines
224	#define ARM_SMMU_CB_FSYNR0 0x68	224	#define ARM_SMMU_CB_FSYNR0 0x68
225	#define ARM_SMMU_FSYNR0_WNR BIT(4)	225	#define ARM_SMMU_FSYNR0_WNR BIT(4)
226		226
		227	#define ARM_SMMU_CB_FSYNR1 0x6c
		228
227	#define ARM_SMMU_CB_S1_TLBIVA 0x600	229	#define ARM_SMMU_CB_S1_TLBIVA 0x600
228	#define ARM_SMMU_CB_S1_TLBIASID 0x610	230	#define ARM_SMMU_CB_S1_TLBIASID 0x610
229	#define ARM_SMMU_CB_S1_TLBIVAL 0x620	231	#define ARM_SMMU_CB_S1_TLBIVAL 0x620

include/linux/adreno-smmu-priv.h+37−1

@@ -8,6 +8,32 @@ · 7 unmodified lines
8		8
9	#include <linux/io-pgtable.h>	9	#include <linux/io-pgtable.h>
10		10
		11	/**
		12	* struct adreno_smmu_fault_info - container for key fault information
		13	*
		14	* @far: The faulting IOVA from ARM_SMMU_CB_FAR
		15	* @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0
		16	* @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR
		17	* @fsr: The fault status from ARM_SMMU_CB_FSR
		18	* @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0
		19	* @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0
		20	* @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx)
		21	*
		22	* This struct passes back key page fault information to the GPU driver
		23	* through the get_fault_info function pointer.
		24	* The GPU driver can use this information to print informative
		25	* log messages and provide deeper GPU specific insight into the fault.
		26	*/
		27	struct adreno_smmu_fault_info {
		28	u64 far;
		29	u64 ttbr0;
		30	u32 contextidr;
		31	u32 fsr;
		32	u32 fsynr0;
		33	u32 fsynr1;
		34	u32 cbfrsynra;
		35	};
		36
11	/**	37	/**
12	* struct adreno_smmu_priv - private interface between adreno-smmu and GPU	38	* struct adreno_smmu_priv - private interface between adreno-smmu and GPU
13	*	39	*
@@ -17,6 +43,13 @@ · 3 unmodified lines
17	* @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A	43	* @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A
18	* NULL config disables TTBR0 translation, otherwise	44	* NULL config disables TTBR0 translation, otherwise
19	* TTBR0 translation is enabled with the specified cfg	45	* TTBR0 translation is enabled with the specified cfg
		46	* @get_fault_info: Called by the GPU fault handler to get information about
		47	* the fault
		48	* @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call
		49	* before set_ttbr0_cfg(). If stalling on fault is enabled,
		50	* the GPU driver must call resume_translation()
		51	* @resume_translation: Resume translation after a fault
		52	*
20	*	53	*
21	* The GPU driver (drm/msm) and adreno-smmu work together for controlling	54	* The GPU driver (drm/msm) and adreno-smmu work together for controlling
22	* the GPU's SMMU instance. This is by necessity, as the GPU is directly	55	* the GPU's SMMU instance. This is by necessity, as the GPU is directly
@@ -31,6 +64,9 @@ struct adreno_smmu_priv { · 8 unmodified lines
31	const void *cookie;	64	const void *cookie;
32	const struct io_pgtable_cfg (get_ttbr1_cfg)(const void *cookie);	65	const struct io_pgtable_cfg (get_ttbr1_cfg)(const void *cookie);
33	int (set_ttbr0_cfg)(const void cookie, const struct io_pgtable_cfg *cfg);	66	int (set_ttbr0_cfg)(const void cookie, const struct io_pgtable_cfg *cfg);
		67	void (get_fault_info)(const void cookie, struct adreno_smmu_fault_info *info);
		68	void (set_stall)(const void cookie, bool enabled);
		69	void (resume_translation)(const void cookie, bool terminate);
34	};	70	};
35		71
36	#endif /* __ADRENO_SMMU_PRIV_H */	72	#endif /* __ADRENO_SMMU_PRIV_H */

include/uapi/drm/msm_drm.h+3−4

 /* cache modes */
 #define MSM_BO_CACHED        0x00010000
 #define MSM_BO_WC            0x00020000
-#define MSM_BO_UNCACHED      0x00040000
+#define MSM_BO_UNCACHED      0x00040000 /* deprecated, use MSM_BO_WC */
+#define MSM_BO_CACHED_COHERENT 0x080000
 #define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
                               MSM_BO_GPU_READONLY | \
-                              MSM_BO_CACHED | \
+                              MSM_BO_CACHE_MASK)
-                              MSM_BO_WC | \
-                              MSM_BO_UNCACHED)
 struct drm_msm_gem_new {
 	__u64 size;           /* in */