linux/platform_data/dma-atmel.h is only used by the at_hdmac driver. Move the CFG bits definitions back in at_hdmac_regs.h and the remaining definitions in the driver.
Unified · Split
| @@ -11604,7 +11604,6 @@ F: drivers/dma/at_hdmac.c · 11603 unmodified lines | |||
| 11604 | F: drivers/dma/at_hdmac_regs.h | 11604 | F: drivers/dma/at_hdmac_regs.h |
| 11605 | F: drivers/dma/at_xdmac.c | 11605 | F: drivers/dma/at_xdmac.c |
| 11606 | F: include/dt-bindings/dma/at91.h | 11606 | F: include/dt-bindings/dma/at91.h |
| 11607 | F: include/linux/platform_data/dma-atmel.h | ||
| 11608 | 11607 | ||
| 11609 | MICROCHIP AT91 SERIAL DRIVER | 11608 | MICROCHIP AT91 SERIAL DRIVER |
| 11610 | M: Richard Genoud <richard.genoud@gmail.com> | 11609 | M: Richard Genoud <richard.genoud@gmail.com> |
| @@ -54,6 +54,25 @@ module_param(init_nr_desc_per_channel, uint, 0644); · 53 unmodified lines | |||
| 54 | MODULE_PARM_DESC(init_nr_desc_per_channel, | 54 | MODULE_PARM_DESC(init_nr_desc_per_channel, |
| 55 | "initial descriptors per channel (default: 64)"); | 55 | "initial descriptors per channel (default: 64)"); |
| 56 | 56 | ||
| 57 | /** | ||
| 58 | * struct at_dma_platform_data - Controller configuration parameters | ||
| 59 | * @nr_channels: Number of channels supported by hardware (max 8) | ||
| 60 | * @cap_mask: dma_capability flags supported by the platform | ||
| 61 | */ | ||
| 62 | struct at_dma_platform_data { | ||
| 63 | unsigned int nr_channels; | ||
| 64 | dma_cap_mask_t cap_mask; | ||
| 65 | }; | ||
| 66 | |||
| 67 | /** | ||
| 68 | * struct at_dma_slave - Controller-specific information about a slave | ||
| 69 | * @dma_dev: required DMA master device | ||
| 70 | * @cfg: Platform-specific initializer for the CFG register | ||
| 71 | */ | ||
| 72 | struct at_dma_slave { | ||
| 73 | struct device *dma_dev; | ||
| 74 | u32 cfg; | ||
| 75 | }; | ||
| 57 | 76 | ||
| 58 | /* prototypes */ | 77 | /* prototypes */ |
| 59 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | 78 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); |
| @@ -7,8 +7,6 @@ · 6 unmodified lines | |||
| 7 | #ifndef AT_HDMAC_REGS_H | 7 | #ifndef AT_HDMAC_REGS_H |
| 8 | #define AT_HDMAC_REGS_H | 8 | #define AT_HDMAC_REGS_H |
| 9 | 9 | ||
| 10 | #include <linux/platform_data/dma-atmel.h> | ||
| 11 | |||
| 12 | #define AT_DMA_MAX_NR_CHANNELS 8 | 10 | #define AT_DMA_MAX_NR_CHANNELS 8 |
| 13 | 11 | ||
| 14 | 12 | ||
| @@ -148,7 +146,31 @@ · 133 unmodified lines | |||
| 148 | #define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */ | 146 | #define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */ |
| 149 | 147 | ||
| 150 | /* Bitfields in CFG */ | 148 | /* Bitfields in CFG */ |
| 151 | /* are in at_hdmac.h */ | 149 | #define ATC_PER_MSB(h) ((0x30U & (h)) >> 4) /* Extract most significant bits of a handshaking identifier */ |
| 150 | |||
| 151 | #define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */ | ||
| 152 | #define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */ | ||
| 153 | #define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */ | ||
| 154 | #define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */ | ||
| 155 | #define ATC_SRC_H2SEL_SW (0x0 << 9) | ||
| 156 | #define ATC_SRC_H2SEL_HW (0x1 << 9) | ||
| 157 | #define ATC_SRC_PER_MSB(h) (ATC_PER_MSB(h) << 10) /* Channel src rq (most significant bits) */ | ||
| 158 | #define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */ | ||
| 159 | #define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */ | ||
| 160 | #define ATC_DST_H2SEL_SW (0x0 << 13) | ||
| 161 | #define ATC_DST_H2SEL_HW (0x1 << 13) | ||
| 162 | #define ATC_DST_PER_MSB(h) (ATC_PER_MSB(h) << 14) /* Channel dst rq (most significant bits) */ | ||
| 163 | #define ATC_SOD (0x1 << 16) /* Stop On Done */ | ||
| 164 | #define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */ | ||
| 165 | #define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */ | ||
| 166 | #define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */ | ||
| 167 | #define ATC_LOCK_IF_L_CHUNK (0x0 << 22) | ||
| 168 | #define ATC_LOCK_IF_L_BUFFER (0x1 << 22) | ||
| 169 | #define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */ | ||
| 170 | #define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */ | ||
| 171 | #define ATC_FIFOCFG_LARGESTBURST (0x0 << 28) | ||
| 172 | #define ATC_FIFOCFG_HALFFIFO (0x1 << 28) | ||
| 173 | #define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28) | ||
| 152 | 174 | ||
| 153 | /* Bitfields in SPIP */ | 175 | /* Bitfields in SPIP */ |
| 154 | #define ATC_SPIP_HOLE(x) (0xFFFFU & (x)) | 176 | #define ATC_SPIP_HOLE(x) (0xFFFFU & (x)) |
| @@ -1,61 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
| 2 | /* | ||
| 3 | * Header file for the Atmel AHB DMA Controller driver | ||
| 4 | * | ||
| 5 | * Copyright (C) 2008 Atmel Corporation | ||
| 6 | */ | ||
| 7 | #ifndef AT_HDMAC_H | ||
| 8 | #define AT_HDMAC_H | ||
| 9 | |||
| 10 | #include <linux/dmaengine.h> | ||
| 11 | |||
| 12 | /** | ||
| 13 | * struct at_dma_platform_data - Controller configuration parameters | ||
| 14 | * @nr_channels: Number of channels supported by hardware (max 8) | ||
| 15 | * @cap_mask: dma_capability flags supported by the platform | ||
| 16 | */ | ||
| 17 | struct at_dma_platform_data { | ||
| 18 | unsigned int nr_channels; | ||
| 19 | dma_cap_mask_t cap_mask; | ||
| 20 | }; | ||
| 21 | |||
| 22 | /** | ||
| 23 | * struct at_dma_slave - Controller-specific information about a slave | ||
| 24 | * @dma_dev: required DMA master device | ||
| 25 | * @cfg: Platform-specific initializer for the CFG register | ||
| 26 | */ | ||
| 27 | struct at_dma_slave { | ||
| 28 | struct device *dma_dev; | ||
| 29 | u32 cfg; | ||
| 30 | }; | ||
| 31 | |||
| 32 | |||
| 33 | /* Platform-configurable bits in CFG */ | ||
| 34 | #define ATC_PER_MSB(h) ((0x30U & (h)) >> 4) /* Extract most significant bits of a handshaking identifier */ | ||
| 35 | |||
| 36 | #define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */ | ||
| 37 | #define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */ | ||
| 38 | #define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */ | ||
| 39 | #define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */ | ||
| 40 | #define ATC_SRC_H2SEL_SW (0x0 << 9) | ||
| 41 | #define ATC_SRC_H2SEL_HW (0x1 << 9) | ||
| 42 | #define ATC_SRC_PER_MSB(h) (ATC_PER_MSB(h) << 10) /* Channel src rq (most significant bits) */ | ||
| 43 | #define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */ | ||
| 44 | #define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */ | ||
| 45 | #define ATC_DST_H2SEL_SW (0x0 << 13) | ||
| 46 | #define ATC_DST_H2SEL_HW (0x1 << 13) | ||
| 47 | #define ATC_DST_PER_MSB(h) (ATC_PER_MSB(h) << 14) /* Channel dst rq (most significant bits) */ | ||
| 48 | #define ATC_SOD (0x1 << 16) /* Stop On Done */ | ||
| 49 | #define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */ | ||
| 50 | #define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */ | ||
| 51 | #define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */ | ||
| 52 | #define ATC_LOCK_IF_L_CHUNK (0x0 << 22) | ||
| 53 | #define ATC_LOCK_IF_L_BUFFER (0x1 << 22) | ||
| 54 | #define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */ | ||
| 55 | #define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */ | ||
| 56 | #define ATC_FIFOCFG_LARGESTBURST (0x0 << 28) | ||
| 57 | #define ATC_FIFOCFG_HALFFIFO (0x1 << 28) | ||
| 58 | #define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28) | ||
| 59 | |||
| 60 | |||
| 61 | #endif /* AT_HDMAC_H */ | ||