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dmaengine: at_hdmac: remove platform data header

linux/platform_data/dma-atmel.h is only used by the at_hdmac driver. Move the CFG bits definitions back in at_hdmac_regs.h and the remaining definitions in the driver.

Alexandre Belloni committed 5 years ago

Commit 33cb6d11 parent c518a2f4 files · +44 −65Browse files

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include/linux/platform_data/dma-atmel.h+0−61
@@ -1,61 +0,0 @@
1−/* SPDX-License-Identifier: GPL-2.0-or-later */
2−/*
3− * Header file for the Atmel AHB DMA Controller driver
4− *
5− * Copyright (C) 2008 Atmel Corporation
6− */
7−#ifndef AT_HDMAC_H
8−#define AT_HDMAC_H
9−
10−#include <linux/dmaengine.h>
11−
12−/**
13− * struct at_dma_platform_data - Controller configuration parameters
14− * @nr_channels: Number of channels supported by hardware (max 8)
15− * @cap_mask: dma_capability flags supported by the platform
16− */
17−struct at_dma_platform_data {
18− unsigned int nr_channels;
19− dma_cap_mask_t cap_mask;
20−};
21−
22−/**
23− * struct at_dma_slave - Controller-specific information about a slave
24− * @dma_dev: required DMA master device
25− * @cfg: Platform-specific initializer for the CFG register
26− */
27−struct at_dma_slave {
28− struct device *dma_dev;
29− u32 cfg;
30−};
31−
32−
33−/* Platform-configurable bits in CFG */
34−#define ATC_PER_MSB(h) ((0x30U & (h)) >> 4) /* Extract most significant bits of a handshaking identifier */
35−
36−#define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */
37−#define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */
38−#define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */
39−#define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */
40−#define ATC_SRC_H2SEL_SW (0x0 << 9)
41−#define ATC_SRC_H2SEL_HW (0x1 << 9)
42−#define ATC_SRC_PER_MSB(h) (ATC_PER_MSB(h) << 10) /* Channel src rq (most significant bits) */
43−#define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */
44−#define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */
45−#define ATC_DST_H2SEL_SW (0x0 << 13)
46−#define ATC_DST_H2SEL_HW (0x1 << 13)
47−#define ATC_DST_PER_MSB(h) (ATC_PER_MSB(h) << 14) /* Channel dst rq (most significant bits) */
48−#define ATC_SOD (0x1 << 16) /* Stop On Done */
49−#define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */
50−#define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */
51−#define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */
52−#define ATC_LOCK_IF_L_CHUNK (0x0 << 22)
53−#define ATC_LOCK_IF_L_BUFFER (0x1 << 22)
54−#define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */
55−#define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */
56−#define ATC_FIFOCFG_LARGESTBURST (0x0 << 28)
57−#define ATC_FIFOCFG_HALFFIFO (0x1 << 28)
58−#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28)
59−
60−
61−#endif /* AT_HDMAC_H */