Unified · Split
| @@ -55,12 +55,12 @@ Description: Interface for making ib_srp connect to a new target. · 54 unmodified lines | ||
| 55 | 55 | only safe with partial memory descriptor list support enabled |
| 56 | 56 | (allow_ext_sg=1). |
| 57 | 57 | * comp_vector, a number in the range 0..n-1 specifying the |
| 58 | − MSI-X completion vector. Some HCA's allocate multiple (n) | |
| 59 | − MSI-X vectors per HCA port. If the IRQ affinity masks of | |
| 60 | − these interrupts have been configured such that each MSI-X | |
| 61 | − interrupt is handled by a different CPU then the comp_vector | |
| 62 | − parameter can be used to spread the SRP completion workload | |
| 63 | − over multiple CPU's. | |
| 58 | + MSI-X completion vector of the first RDMA channel. Some | |
| 59 | + HCA's allocate multiple (n) MSI-X vectors per HCA port. If | |
| 60 | + the IRQ affinity masks of these interrupts have been | |
| 61 | + configured such that each MSI-X interrupt is handled by a | |
| 62 | + different CPU then the comp_vector parameter can be used to | |
| 63 | + spread the SRP completion workload over multiple CPU's. | |
| 64 | 64 | * tl_retry_count, a number in the range 2..7 specifying the |
| 65 | 65 | IB RC retry count. |
| 66 | 66 | * queue_size, the maximum number of commands that the |
| @@ -88,6 +88,13 @@ Description: Whether ib_srp is allowed to include a partial memory · 21 unmodified lines | ||
| 88 | 88 | descriptor list in an SRP_CMD when communicating with an SRP |
| 89 | 89 | target. |
| 90 | 90 | |
| 91 | +What: /sys/class/scsi_host/host<n>/ch_count | |
| 92 | +Date: April 1, 2015 | |
| 93 | +KernelVersion: 3.19 | |
| 94 | +Contact: linux-rdma@vger.kernel.org | |
| 95 | +Description: Number of RDMA channels used for communication with the SRP | |
| 96 | + target. | |
| 97 | + | |
| 91 | 98 | What: /sys/class/scsi_host/host<n>/cmd_sg_entries |
| 92 | 99 | Date: May 19, 2011 |
| 93 | 100 | KernelVersion: 2.6.39 |
| @@ -95,6 +102,12 @@ Contact: linux-rdma@vger.kernel.org · 1 unmodified line | ||
| 95 | 102 | Description: Maximum number of data buffer descriptors that may be sent to |
| 96 | 103 | the target in a single SRP_CMD request. |
| 97 | 104 | |
| 105 | +What: /sys/class/scsi_host/host<n>/comp_vector | |
| 106 | +Date: September 2, 2013 | |
| 107 | +KernelVersion: 3.11 | |
| 108 | +Contact: linux-rdma@vger.kernel.org | |
| 109 | +Description: Completion vector used for the first RDMA channel. | |
| 110 | + | |
| 98 | 111 | What: /sys/class/scsi_host/host<n>/dgid |
| 99 | 112 | Date: June 17, 2006 |
| 100 | 113 | KernelVersion: 2.6.17 |
| @@ -36,7 +36,7 @@ o How can the updater tell when a grace period has completed · 35 unmodified lines | ||
| 36 | 36 | executed in user mode, or executed in the idle loop, we can |
| 37 | 37 | safely free up that item. |
| 38 | 38 | |
| 39 | − Preemptible variants of RCU (CONFIG_TREE_PREEMPT_RCU) get the | |
| 39 | + Preemptible variants of RCU (CONFIG_PREEMPT_RCU) get the | |
| 40 | 40 | same effect, but require that the readers manipulate CPU-local |
| 41 | 41 | counters. These counters allow limited types of blocking within |
| 42 | 42 | RCU read-side critical sections. SRCU also uses CPU-local |
| @@ -81,7 +81,7 @@ o I hear that RCU is patented? What is with that? · 38 unmodified lines | ||
| 81 | 81 | o I hear that RCU needs work in order to support realtime kernels? |
| 82 | 82 | |
| 83 | 83 | This work is largely completed. Realtime-friendly RCU can be |
| 84 | − enabled via the CONFIG_TREE_PREEMPT_RCU kernel configuration | |
| 84 | + enabled via the CONFIG_PREEMPT_RCU kernel configuration | |
| 85 | 85 | parameter. However, work is in progress for enabling priority |
| 86 | 86 | boosting of preempted RCU read-side critical sections. This is |
| 87 | 87 | needed if you have CPU-bound realtime threads. |
| @@ -26,12 +26,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT · 25 unmodified lines | ||
| 26 | 26 | Stall-warning messages may be enabled and disabled completely via |
| 27 | 27 | /sys/module/rcupdate/parameters/rcu_cpu_stall_suppress. |
| 28 | 28 | |
| 29 | −CONFIG_RCU_CPU_STALL_VERBOSE | |
| 30 | − | |
| 31 | − This kernel configuration parameter causes the stall warning to | |
| 32 | − also dump the stacks of any tasks that are blocking the current | |
| 33 | − RCU-preempt grace period. | |
| 34 | − | |
| 35 | 29 | CONFIG_RCU_CPU_STALL_INFO |
| 36 | 30 | |
| 37 | 31 | This kernel configuration parameter causes the stall warning to |
| @@ -77,7 +71,7 @@ This message indicates that CPU 5 detected that it was causing a stall, · 39 unmodified lines | ||
| 77 | 71 | and that the stall was affecting RCU-sched. This message will normally be |
| 78 | 72 | followed by a stack dump of the offending CPU. On TREE_RCU kernel builds, |
| 79 | 73 | RCU and RCU-sched are implemented by the same underlying mechanism, |
| 80 | −while on TREE_PREEMPT_RCU kernel builds, RCU is instead implemented | |
| 74 | +while on PREEMPT_RCU kernel builds, RCU is instead implemented | |
| 81 | 75 | by rcu_preempt_state. |
| 82 | 76 | |
| 83 | 77 | On the other hand, if the offending CPU fails to print out a stall-warning |
| @@ -89,7 +83,7 @@ INFO: rcu_bh_state detected stalls on CPUs/tasks: { 3 5 } (detected by 2, 2502 j · 5 unmodified lines | ||
| 89 | 83 | This message indicates that CPU 2 detected that CPUs 3 and 5 were both |
| 90 | 84 | causing stalls, and that the stall was affecting RCU-bh. This message |
| 91 | 85 | will normally be followed by stack dumps for each CPU. Please note that |
| 92 | −TREE_PREEMPT_RCU builds can be stalled by tasks as well as by CPUs, | |
| 86 | +PREEMPT_RCU builds can be stalled by tasks as well as by CPUs, | |
| 93 | 87 | and that the tasks will be indicated by PID, for example, "P3421". |
| 94 | 88 | It is even possible for a rcu_preempt_state stall to be caused by both |
| 95 | 89 | CPUs -and- tasks, in which case the offending CPUs and tasks will all |
| @@ -205,10 +199,10 @@ o A CPU-bound real-time task in a CONFIG_PREEMPT kernel, which might · 109 unmodified lines | ||
| 205 | 199 | o A CPU-bound real-time task in a CONFIG_PREEMPT_RT kernel that |
| 206 | 200 | is running at a higher priority than the RCU softirq threads. |
| 207 | 201 | This will prevent RCU callbacks from ever being invoked, |
| 208 | − and in a CONFIG_TREE_PREEMPT_RCU kernel will further prevent | |
| 202 | + and in a CONFIG_PREEMPT_RCU kernel will further prevent | |
| 209 | 203 | RCU grace periods from ever completing. Either way, the |
| 210 | 204 | system will eventually run out of memory and hang. In the |
| 211 | − CONFIG_TREE_PREEMPT_RCU case, you might see stall-warning | |
| 205 | + CONFIG_PREEMPT_RCU case, you might see stall-warning | |
| 212 | 206 | messages. |
| 213 | 207 | |
| 214 | 208 | o A hardware or software issue shuts off the scheduler-clock |
| @@ -8,7 +8,7 @@ The following sections describe the debugfs files and formats, first · 7 unmodified lines | ||
| 8 | 8 | for rcutree and next for rcutiny. |
| 9 | 9 | |
| 10 | 10 | |
| 11 | −CONFIG_TREE_RCU and CONFIG_TREE_PREEMPT_RCU debugfs Files and Formats | |
| 11 | +CONFIG_TREE_RCU and CONFIG_PREEMPT_RCU debugfs Files and Formats | |
| 12 | 12 | |
| 13 | 13 | These implementations of RCU provide several debugfs directories under the |
| 14 | 14 | top-level directory "rcu": |
| @@ -18,7 +18,7 @@ rcu/rcu_preempt · 3 unmodified lines | ||
| 18 | 18 | rcu/rcu_sched |
| 19 | 19 | |
| 20 | 20 | Each directory contains files for the corresponding flavor of RCU. |
| 21 | −Note that rcu/rcu_preempt is only present for CONFIG_TREE_PREEMPT_RCU. | |
| 21 | +Note that rcu/rcu_preempt is only present for CONFIG_PREEMPT_RCU. | |
| 22 | 22 | For CONFIG_TREE_RCU, the RCU flavor maps onto the RCU-sched flavor, |
| 23 | 23 | so that activity for both appears in rcu/rcu_sched. |
| 24 | 24 | |
| @@ -137,7 +137,7 @@ rcu_read_lock() · 136 unmodified lines | ||
| 137 | 137 | Used by a reader to inform the reclaimer that the reader is |
| 138 | 138 | entering an RCU read-side critical section. It is illegal |
| 139 | 139 | to block while in an RCU read-side critical section, though |
| 140 | − kernels built with CONFIG_TREE_PREEMPT_RCU can preempt RCU | |
| 140 | + kernels built with CONFIG_PREEMPT_RCU can preempt RCU | |
| 141 | 141 | read-side critical sections. Any RCU-protected data structure |
| 142 | 142 | accessed during an RCU read-side critical section is guaranteed to |
| 143 | 143 | remain unreclaimed for the full duration of that critical section. |
| @@ -7,32 +7,14 @@ world, which changes the way some things have to be initialized. This makes · 6 unmodified lines | ||
| 7 | 7 | a need to provide an interface for such platforms to specify available firmware |
| 8 | 8 | operations and call them when needed. |
| 9 | 9 | |
| 10 | −Firmware operations can be specified using struct firmware_ops | |
| 11 | − | |
| 12 | − struct firmware_ops { | |
| 13 | − /* | |
| 14 | − * Enters CPU idle mode | |
| 15 | − */ | |
| 16 | − int (*do_idle)(void); | |
| 17 | − /* | |
| 18 | − * Sets boot address of specified physical CPU | |
| 19 | − */ | |
| 20 | − int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr); | |
| 21 | − /* | |
| 22 | − * Boots specified physical CPU | |
| 23 | − */ | |
| 24 | − int (*cpu_boot)(int cpu); | |
| 25 | − /* | |
| 26 | − * Initializes L2 cache | |
| 27 | − */ | |
| 28 | − int (*l2x0_init)(void); | |
| 29 | − }; | |
| 30 | − | |
| 31 | −and then registered with register_firmware_ops function | |
| 10 | +Firmware operations can be specified by filling in a struct firmware_ops | |
| 11 | +with appropriate callbacks and then registering it with register_firmware_ops() | |
| 12 | +function. | |
| 32 | 13 | |
| 33 | 14 | void register_firmware_ops(const struct firmware_ops *ops) |
| 34 | 15 | |
| 35 | −the ops pointer must be non-NULL. | |
| 16 | +The ops pointer must be non-NULL. More information about struct firmware_ops | |
| 17 | +and its members can be found in arch/arm/include/asm/firmware.h header. | |
| 36 | 18 | |
| 37 | 19 | There is a default, empty set of operations provided, so there is no need to |
| 38 | 20 | set anything if platform does not require firmware operations. |
| @@ -37,16 +37,26 @@ SunXi family · 36 unmodified lines | ||
| 37 | 37 | http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf |
| 38 | 38 | |
| 39 | 39 | - Allwinner A23 |
| 40 | − + Not Supported | |
| 40 | + + Datasheet | |
| 41 | + http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf | |
| 42 | + + User Manual | |
| 43 | + http://dl.linux-sunxi.org/A23/A23%20User%20Manual%20V1.0%2020130830.pdf | |
| 41 | 44 | |
| 42 | 45 | * Quad ARM Cortex-A7 based SoCs |
| 43 | 46 | - Allwinner A31 (sun6i) |
| 44 | 47 | + Datasheet |
| 45 | − http://dl.linux-sunxi.org/A31/A31%20Datasheet%20-%20v1.00%20(2012-12-24).pdf | |
| 48 | + http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf | |
| 49 | + + User Manual | |
| 50 | + http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20user%20manual%20V1.1%2020130630.pdf | |
| 46 | 51 | |
| 47 | 52 | - Allwinner A31s (sun6i) |
| 48 | 53 | + Not Supported |
| 54 | + + Datasheet | |
| 55 | + http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20datasheet%20V1.3%2020131106.pdf | |
| 56 | + + User Manual | |
| 57 | + http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%2020130322.pdf | |
| 49 | 58 | |
| 50 | 59 | * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs |
| 51 | 60 | - Allwinner A80 |
| 52 | − + Not Supported | |
| 61 | + + Datasheet | |
| 62 | + http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf | |
| @@ -0,0 +1,45 @@ | ||
| 1 | +The arm64 port of the Linux kernel provides infrastructure to support | |
| 2 | +emulation of instructions which have been deprecated, or obsoleted in | |
| 3 | +the architecture. The infrastructure code uses undefined instruction | |
| 4 | +hooks to support emulation. Where available it also allows turning on | |
| 5 | +the instruction execution in hardware. | |
| 6 | + | |
| 7 | +The emulation mode can be controlled by writing to sysctl nodes | |
| 8 | +(/proc/sys/abi). The following explains the different execution | |
| 9 | +behaviours and the corresponding values of the sysctl nodes - | |
| 10 | + | |
| 11 | +* Undef | |
| 12 | + Value: 0 | |
| 13 | + Generates undefined instruction abort. Default for instructions that | |
| 14 | + have been obsoleted in the architecture, e.g., SWP | |
| 15 | + | |
| 16 | +* Emulate | |
| 17 | + Value: 1 | |
| 18 | + Uses software emulation. To aid migration of software, in this mode | |
| 19 | + usage of emulated instruction is traced as well as rate limited | |
| 20 | + warnings are issued. This is the default for deprecated | |
| 21 | + instructions, .e.g., CP15 barriers | |
| 22 | + | |
| 23 | +* Hardware Execution | |
| 24 | + Value: 2 | |
| 25 | + Although marked as deprecated, some implementations may support the | |
| 26 | + enabling/disabling of hardware support for the execution of these | |
| 27 | + instructions. Using hardware execution generally provides better | |
| 28 | + performance, but at the loss of ability to gather runtime statistics | |
| 29 | + about the use of the deprecated instructions. | |
| 30 | + | |
| 31 | +The default mode depends on the status of the instruction in the | |
| 32 | +architecture. Deprecated instructions should default to emulation | |
| 33 | +while obsolete instructions must be undefined by default. | |
| 34 | + | |
| 35 | +Supported legacy instructions | |
| 36 | +----------------------------- | |
| 37 | +* SWP{B} | |
| 38 | +Node: /proc/sys/abi/swp | |
| 39 | +Status: Obsolete | |
| 40 | +Default: Undef (0) | |
| 41 | + | |
| 42 | +* CP15 Barriers | |
| 43 | +Node: /proc/sys/abi/cp15_barrier | |
| 44 | +Status: Deprecated | |
| 45 | +Default: Emulate (1) | |
| @@ -7,12 +7,13 @@ · 6 unmodified lines | ||
| 7 | 7 | maintainers on how to implement atomic counter, bitops, and spinlock |
| 8 | 8 | interfaces properly. |
| 9 | 9 | |
| 10 | − The atomic_t type should be defined as a signed integer. | |
| 11 | −Also, it should be made opaque such that any kind of cast to a normal | |
| 12 | −C integer type will fail. Something like the following should | |
| 13 | −suffice: | |
| 10 | + The atomic_t type should be defined as a signed integer and | |
| 11 | +the atomic_long_t type as a signed long integer. Also, they should | |
| 12 | +be made opaque such that any kind of cast to a normal C integer type | |
| 13 | +will fail. Something like the following should suffice: | |
| 14 | 14 | |
| 15 | 15 | typedef struct { int counter; } atomic_t; |
| 16 | + typedef struct { long counter; } atomic_long_t; | |
| 16 | 17 | |
| 17 | 18 | Historically, counter has been declared volatile. This is now discouraged. |
| 18 | 19 | See Documentation/volatile-considered-harmful.txt for the complete rationale. |
| @@ -37,6 +38,9 @@ initializer is used before runtime. If the initializer is used at runtime, a · 18 unmodified lines | ||
| 37 | 38 | proper implicit or explicit read memory barrier is needed before reading the |
| 38 | 39 | value with atomic_read from another thread. |
| 39 | 40 | |
| 41 | +As with all of the atomic_ interfaces, replace the leading "atomic_" | |
| 42 | +with "atomic_long_" to operate on atomic_long_t. | |
| 43 | + | |
| 40 | 44 | The second interface can be used at runtime, as in: |
| 41 | 45 | |
| 42 | 46 | struct foo { atomic_t counter; }; |
| @@ -827,10 +827,6 @@ but in the event of any barrier requests in the tag queue we need to ensure · 826 unmodified lines | ||
| 827 | 827 | that requests are restarted in the order they were queue. This may happen |
| 828 | 828 | if the driver needs to use blk_queue_invalidate_tags(). |
| 829 | 829 | |
| 830 | −Tagging also defines a new request flag, REQ_QUEUED. This is set whenever | |
| 831 | −a request is currently tagged. You should not use this flag directly, | |
| 832 | −blk_rq_tagged(rq) is the portable way to do so. | |
| 833 | − | |
| 834 | 830 | 3.3 I/O Submission |
| 835 | 831 | |
| 836 | 832 | The routine submit_bio() is used to submit a single io. Higher level i/o |
| @@ -47,20 +47,26 @@ Message and constructor argument pairs are: · 46 unmodified lines | ||
| 47 | 47 | 'discard_promote_adjustment <value>' |
| 48 | 48 | |
| 49 | 49 | The sequential threshold indicates the number of contiguous I/Os |
| 50 | −required before a stream is treated as sequential. The random threshold | |
| 50 | +required before a stream is treated as sequential. Once a stream is | |
| 51 | +considered sequential it will bypass the cache. The random threshold | |
| 51 | 52 | is the number of intervening non-contiguous I/Os that must be seen |
| 52 | 53 | before the stream is treated as random again. |
| 53 | 54 | |
| 54 | 55 | The sequential and random thresholds default to 512 and 4 respectively. |
| 55 | 56 | |
| 56 | −Large, sequential ios are probably better left on the origin device | |
| 57 | −since spindles tend to have good bandwidth. The io_tracker counts | |
| 58 | −contiguous I/Os to try to spot when the io is in one of these sequential | |
| 59 | −modes. | |
| 60 | − | |
| 61 | −Internally the mq policy maintains a promotion threshold variable. If | |
| 62 | −the hit count of a block not in the cache goes above this threshold it | |
| 63 | −gets promoted to the cache. The read, write and discard promote adjustment | |
| 57 | +Large, sequential I/Os are probably better left on the origin device | |
| 58 | +since spindles tend to have good sequential I/O bandwidth. The | |
| 59 | +io_tracker counts contiguous I/Os to try to spot when the I/O is in one | |
| 60 | +of these sequential modes. But there are use-cases for wanting to | |
| 61 | +promote sequential blocks to the cache (e.g. fast application startup). | |
| 62 | +If sequential threshold is set to 0 the sequential I/O detection is | |
| 63 | +disabled and sequential I/O will no longer implicitly bypass the cache. | |
| 64 | +Setting the random threshold to 0 does _not_ disable the random I/O | |
| 65 | +stream detection. | |
| 66 | + | |
| 67 | +Internally the mq policy determines a promotion threshold. If the hit | |
| 68 | +count of a block not in the cache goes above this threshold it gets | |
| 69 | +promoted to the cache. The read, write and discard promote adjustment | |
| 64 | 70 | tunables allow you to tweak the promotion threshold by adding a small |
| 65 | 71 | value based on the io type. They default to 4, 8 and 1 respectively. |
| 66 | 72 | If you're trying to quickly warm a new cache device you may wish to |
| @@ -2,7 +2,9 @@ Amlogic MesonX device tree bindings · 1 unmodified line | ||
| 2 | 2 | ------------------------------------------- |
| 3 | 3 | |
| 4 | 4 | Boards with the Amlogic Meson6 SoC shall have the following properties: |
| 5 | + Required root node property: | |
| 6 | + compatible: "amlogic,meson6" | |
| 5 | 7 | |
| 6 | −Required root node property: | |
| 7 | − | |
| 8 | −compatible = "amlogic,meson6"; | |
| 8 | +Boards with the Amlogic Meson8 SoC shall have the following properties: | |
| 9 | + Required root node property: | |
| 10 | + compatible: "amlogic,meson8"; | |
| @@ -22,6 +22,14 @@ to deliver its interrupts via SPIs. · 21 unmodified lines | ||
| 22 | 22 | - always-on : a boolean property. If present, the timer is powered through an |
| 23 | 23 | always-on power domain, therefore it never loses context. |
| 24 | 24 | |
| 25 | +** Optional properties: | |
| 26 | + | |
| 27 | +- arm,cpu-registers-not-fw-configured : Firmware does not initialize | |
| 28 | + any of the generic timer CPU registers, which contain their | |
| 29 | + architecturally-defined reset values. Only supported for 32-bit | |
| 30 | + systems which follow the ARMv7 architected reset values. | |
| 31 | + | |
| 32 | + | |
| 25 | 33 | Example: |
| 26 | 34 | |
| 27 | 35 | timer { |
| @@ -92,3 +92,68 @@ Required nodes: · 91 unmodified lines | ||
| 92 | 92 | - core-module: the root node to the Versatile platforms must have |
| 93 | 93 | a core-module with regs and the compatible strings |
| 94 | 94 | "arm,core-module-versatile", "syscon" |
| 95 | + | |
| 96 | +ARM RealView Boards | |
| 97 | +------------------- | |
| 98 | +The RealView boards cover tailored evaluation boards that are used to explore | |
| 99 | +the ARM11 and Cortex A-8 and Cortex A-9 processors. | |
| 100 | + | |
| 101 | +Required properties (in root node): | |
| 102 | + /* RealView Emulation Baseboard */ | |
| 103 | + compatible = "arm,realview-eb"; | |
| 104 | + /* RealView Platform Baseboard for ARM1176JZF-S */ | |
| 105 | + compatible = "arm,realview-pb1176"; | |
| 106 | + /* RealView Platform Baseboard for ARM11 MPCore */ | |
| 107 | + compatible = "arm,realview-pb11mp"; | |
| 108 | + /* RealView Platform Baseboard for Cortex A-8 */ | |
| 109 | + compatible = "arm,realview-pba8"; | |
| 110 | + /* RealView Platform Baseboard Explore for Cortex A-9 */ | |
| 111 | + compatible = "arm,realview-pbx"; | |
| 112 | + | |
| 113 | +Required nodes: | |
| 114 | + | |
| 115 | +- soc: some node of the RealView platforms must be the SoC | |
| 116 | + node that contain the SoC-specific devices, withe the compatible | |
| 117 | + string set to one of these tuples: | |
| 118 | + "arm,realview-eb-soc", "simple-bus" | |
| 119 | + "arm,realview-pb1176-soc", "simple-bus" | |
| 120 | + "arm,realview-pb11mp-soc", "simple-bus" | |
| 121 | + "arm,realview-pba8-soc", "simple-bus" | |
| 122 | + "arm,realview-pbx-soc", "simple-bus" | |
| 123 | + | |
| 124 | +- syscon: some subnode of the RealView SoC node must be a | |
| 125 | + system controller node pointing to the control registers, | |
| 126 | + with the compatible string set to one of these tuples: | |
| 127 | + "arm,realview-eb-syscon", "syscon" | |
| 128 | + "arm,realview-pb1176-syscon", "syscon" | |
| 129 | + "arm,realview-pb11mp-syscon", "syscon" | |
| 130 | + "arm,realview-pba8-syscon", "syscon" | |
| 131 | + "arm,realview-pbx-syscon", "syscon" | |
| 132 | + | |
| 133 | + Required properties for the system controller: | |
| 134 | + - regs: the location and size of the system controller registers, | |
| 135 | + one range of 0x1000 bytes. | |
| 136 | + | |
| 137 | +Example: | |
| 138 | + | |
| 139 | +/dts-v1/; | |
| 140 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 141 | +#include "skeleton.dtsi" | |
| 142 | + | |
| 143 | +/ { | |
| 144 | + model = "ARM RealView PB1176 with device tree"; | |
| 145 | + compatible = "arm,realview-pb1176"; | |
| 146 | + | |
| 147 | + soc { | |
| 148 | + #address-cells = <1>; | |
| 149 | + #size-cells = <1>; | |
| 150 | + compatible = "arm,realview-pb1176-soc", "simple-bus"; | |
| 151 | + ranges; | |
| 152 | + | |
| 153 | + syscon: syscon@10000000 { | |
| 154 | + compatible = "arm,realview-syscon", "syscon"; | |
| 155 | + reg = <0x10000000 0x1000>; | |
| 156 | + }; | |
| 157 | + | |
| 158 | + }; | |
| 159 | +}; | |
| @@ -0,0 +1,31 @@ | ||
| 1 | +Broadcom Cygnus device tree bindings | |
| 2 | +------------------------------------ | |
| 3 | + | |
| 4 | + | |
| 5 | +Boards with Cygnus SoCs shall have the following properties: | |
| 6 | + | |
| 7 | +Required root node property: | |
| 8 | + | |
| 9 | +BCM11300 | |
| 10 | +compatible = "brcm,bcm11300", "brcm,cygnus"; | |
| 11 | + | |
| 12 | +BCM11320 | |
| 13 | +compatible = "brcm,bcm11320", "brcm,cygnus"; | |
| 14 | + | |
| 15 | +BCM11350 | |
| 16 | +compatible = "brcm,bcm11350", "brcm,cygnus"; | |
| 17 | + | |
| 18 | +BCM11360 | |
| 19 | +compatible = "brcm,bcm11360", "brcm,cygnus"; | |
| 20 | + | |
| 21 | +BCM58300 | |
| 22 | +compatible = "brcm,bcm58300", "brcm,cygnus"; | |
| 23 | + | |
| 24 | +BCM58302 | |
| 25 | +compatible = "brcm,bcm58302", "brcm,cygnus"; | |
| 26 | + | |
| 27 | +BCM58303 | |
| 28 | +compatible = "brcm,bcm58303", "brcm,cygnus"; | |
| 29 | + | |
| 30 | +BCM58305 | |
| 31 | +compatible = "brcm,bcm58305", "brcm,cygnus"; | |
| @@ -227,6 +227,15 @@ nodes to be present and contain the properties described below. · 226 unmodified lines | ||
| 227 | 227 | # List of phandles to idle state nodes supported |
| 228 | 228 | by this cpu [3]. |
| 229 | 229 | |
| 230 | + - rockchip,pmu | |
| 231 | + Usage: optional for systems that have an "enable-method" | |
| 232 | + property value of "rockchip,rk3066-smp" | |
| 233 | + While optional, it is the preferred way to get access to | |
| 234 | + the cpu-core power-domains. | |
| 235 | + Value type: <phandle> | |
| 236 | + Definition: Specifies the syscon node controlling the cpu core | |
| 237 | + power domains. | |
| 238 | + | |
| 230 | 239 | Example 1 (dual-cluster big.LITTLE system 32-bit): |
| 231 | 240 | |
| 232 | 241 | cpus { |
| @@ -74,3 +74,41 @@ Required root node properties: · 73 unmodified lines | ||
| 74 | 74 | i.MX6q generic board |
| 75 | 75 | Required root node properties: |
| 76 | 76 | - compatible = "fsl,imx6q"; |
| 77 | + | |
| 78 | + | |
| 79 | +Freescale LS1021A Platform Device Tree Bindings | |
| 80 | +------------------------------------------------ | |
| 81 | + | |
| 82 | +Required root node compatible properties: | |
| 83 | + - compatible = "fsl,ls1021a"; | |
| 84 | + | |
| 85 | +Freescale LS1021A SoC-specific Device Tree Bindings | |
| 86 | +------------------------------------------- | |
| 87 | + | |
| 88 | +Freescale SCFG | |
| 89 | + SCFG is the supplemental configuration unit, that provides SoC specific | |
| 90 | +configuration and status registers for the chip. Such as getting PEX port | |
| 91 | +status. | |
| 92 | + Required properties: | |
| 93 | + - compatible: should be "fsl,ls1021a-scfg" | |
| 94 | + - reg: should contain base address and length of SCFG memory-mapped registers | |
| 95 | + | |
| 96 | +Example: | |
| 97 | + scfg: scfg@1570000 { | |
| 98 | + compatible = "fsl,ls1021a-scfg"; | |
| 99 | + reg = <0x0 0x1570000 0x0 0x10000>; | |
| 100 | + }; | |
| 101 | + | |
| 102 | +Freescale DCFG | |
| 103 | + DCFG is the device configuration unit, that provides general purpose | |
| 104 | +configuration and status for the device. Such as setting the secondary | |
| 105 | +core start address and release the secondary core from holdoff and startup. | |
| 106 | + Required properties: | |
| 107 | + - compatible: should be "fsl,ls1021a-dcfg" | |
| 108 | + - reg : should contain base address and length of DCFG memory-mapped registers | |
| 109 | + | |
| 110 | +Example: | |
| 111 | + dcfg: dcfg@1ee0000 { | |
| 112 | + compatible = "fsl,ls1021a-dcfg"; | |
| 113 | + reg = <0x0 0x1ee0000 0x0 0x10000>; | |
| 114 | + }; | |
| @@ -17,6 +17,7 @@ Main node required properties: · 16 unmodified lines | ||
| 17 | 17 | "arm,cortex-a7-gic" |
| 18 | 18 | "arm,arm11mp-gic" |
| 19 | 19 | "brcm,brahma-b15-gic" |
| 20 | + "arm,arm1176jzf-devchip-gic" | |
| 20 | 21 | - interrupt-controller : Identifies the node as an interrupt controller |
| 21 | 22 | - #interrupt-cells : Specifies the number of cells needed to encode an |
| 22 | 23 | interrupt source. The type shall be a <u32> and the value shall be 3. |
| @@ -106,11 +106,21 @@ Required subnode-properties: · 105 unmodified lines | ||
| 106 | 106 | - groups: a list of strings describing the group names. |
| 107 | 107 | - function: a string describing the function used to mux the groups. |
| 108 | 108 | |
| 109 | +* Reset controller binding | |
| 110 | + | |
| 111 | +A reset controller is part of the chip control registers set. The chip control | |
| 112 | +node also provides the reset. The register set is not at the same offset between | |
| 113 | +Berlin SoCs. | |
| 114 | + | |
| 115 | +Required property: | |
| 116 | +- #reset-cells: must be set to 2 | |
| 117 | + | |
| 109 | 118 | Example: |
| 110 | 119 | |
| 111 | 120 | chip: chip-control@ea0000 { |
| 112 | 121 | compatible = "marvell,berlin2-chip-ctrl"; |
| 113 | 122 | #clock-cells = <1>; |
| 123 | + #reset-cells = <2>; | |
| 114 | 124 | reg = <0xea0000 0x400>; |
| 115 | 125 | clocks = <&refclk>, <&externaldev 0>; |
| 116 | 126 | clock-names = "refclk", "video_ext0"; |
| @@ -1,10 +1,14 @@ | ||
| 1 | −Mediatek MT6589 Platforms Device Tree Bindings | |
| 1 | +MediaTek mt65xx & mt81xx Platforms Device Tree Bindings | |
| 2 | 2 | |
| 3 | −Boards with a SoC of the Mediatek MT6589 shall have the following property: | |
| 3 | +Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property: | |
| 4 | 4 | |
| 5 | 5 | Required root node property: |
| 6 | 6 | |
| 7 | −compatible: must contain "mediatek,mt6589" | |
| 7 | +compatible: Must contain one of | |
| 8 | + "mediatek,mt6589" | |
| 9 | + "mediatek,mt6592" | |
| 10 | + "mediatek,mt8127" | |
| 11 | + "mediatek,mt8135" | |
| 8 | 12 | |
| 9 | 13 | |
| 10 | 14 | Supported boards: |
| @@ -12,3 +16,12 @@ Supported boards: · 1 unmodified line | ||
| 12 | 16 | - bq Aquaris5 smart phone: |
| 13 | 17 | Required root node properties: |
| 14 | 18 | - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; |
| 19 | +- Evaluation board for MT6592: | |
| 20 | + Required root node properties: | |
| 21 | + - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; | |
| 22 | +- MTK mt8127 tablet moose EVB: | |
| 23 | + Required root node properties: | |
| 24 | + - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; | |
| 25 | +- MTK mt8135 tablet EVB: | |
| 26 | + Required root node properties: | |
| 27 | + - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; | |
| @@ -132,6 +132,9 @@ Boards: · 131 unmodified lines | ||
| 132 | 132 | - AM335X Bone : Low cost community board |
| 133 | 133 | compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3" |
| 134 | 134 | |
| 135 | +- AM335X OrionLXm : Substation Automation Platform | |
| 136 | + compatible = "novatech,am335x-lxm", "ti,am33xx" | |
| 137 | + | |
| 135 | 138 | - OMAP5 EVM : Evaluation Module |
| 136 | 139 | compatible = "ti,omap5-evm", "ti,omap5" |
| 137 | 140 | |
| @@ -1,6 +1,10 @@ | ||
| 1 | 1 | Rockchip platforms device tree bindings |
| 2 | 2 | --------------------------------------- |
| 3 | 3 | |
| 4 | +- MarsBoard RK3066 board: | |
| 5 | + Required root node properties: | |
| 6 | + - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; | |
| 7 | + | |
| 4 | 8 | - bq Curie 2 tablet: |
| 5 | 9 | Required root node properties: |
| 6 | 10 | - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; |
| @@ -1,11 +1,20 @@ | ||
| 1 | −* Samsung's Exynos4210 based SMDKV310 evaluation board | |
| 2 | − | |
| 3 | −SMDKV310 evaluation board is based on Samsung's Exynos4210 SoC. | |
| 1 | +* Samsung's Exynos SoC based boards | |
| 4 | 2 | |
| 5 | 3 | Required root node properties: |
| 6 | 4 | - compatible = should be one or more of the following. |
| 7 | − (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. | |
| 8 | − (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC. | |
| 5 | + - "samsung,monk" - for Exynos3250-based Samsung Simband board. | |
| 6 | + - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board. | |
| 7 | + - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board. | |
| 8 | + - "samsung,trats" - for Exynos4210-based Tizen Reference board. | |
| 9 | + - "samsung,universal_c210" - for Exynos4210-based Samsung board. | |
| 10 | + - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board. | |
| 11 | + - "samsung,trats2" - for Exynos4412-based Tizen Reference board. | |
| 12 | + - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board. | |
| 13 | + - "samsung,xyref5260" - for Exynos5260-based Samsung board. | |
| 14 | + - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. | |
| 15 | + - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. | |
| 16 | + - "samsung,sd5v1" - for Exynos5440-based Samsung board. | |
| 17 | + - "samsung,ssdk5440" - for Exynos5440-based Samsung board. | |
| 9 | 18 | |
| 10 | 19 | Optional: |
| 11 | 20 | - firmware node, specifying presence and type of secure firmware: |
| @@ -10,6 +10,12 @@ Required root node property: src · 9 unmodified lines | ||
| 10 | 10 | |
| 11 | 11 | Boards with the Nomadik SoC include: |
| 12 | 12 | |
| 13 | +Nomadik NHK-15 board manufactured by ST Microelectronics: | |
| 14 | + | |
| 15 | +Required root node property: | |
| 16 | + | |
| 17 | +compatible="st,nomadik-nhk-15"; | |
| 18 | + | |
| 13 | 19 | S8815 "MiniKit" manufactured by Calao Systems: |
| 14 | 20 | |
| 15 | 21 | Required root node property: |
| @@ -0,0 +1,12 @@ | ||
| 1 | +Allwinner sunXi Platforms Device Tree Bindings | |
| 2 | + | |
| 3 | +Each device tree must specify which Allwinner SoC it uses, | |
| 4 | +using one of the following compatible strings: | |
| 5 | + | |
| 6 | + allwinner,sun4i-a10 | |
| 7 | + allwinner,sun5i-a10s | |
| 8 | + allwinner,sun5i-a13 | |
| 9 | + allwinner,sun6i-a31 | |
| 10 | + allwinner,sun7i-a20 | |
| 11 | + allwinner,sun8i-a23 | |
| 12 | + allwinner,sun9i-a80 | |
| @@ -0,0 +1,35 @@ | ||
| 1 | +* ST-Ericsson UX500 PM Domains | |
| 2 | + | |
| 3 | +UX500 supports multiple PM domains which are used to gate power to one or | |
| 4 | +more peripherals on the SOC. | |
| 5 | + | |
| 6 | +The implementation of PM domains for UX500 are based upon the generic PM domain | |
| 7 | +and use the corresponding DT bindings. | |
| 8 | + | |
| 9 | +==PM domain providers== | |
| 10 | + | |
| 11 | +Required properties: | |
| 12 | + - compatible: Must be "stericsson,ux500-pm-domains". | |
| 13 | + - #power-domain-cells : Number of cells in a power domain specifier, must be 1. | |
| 14 | + | |
| 15 | +Example: | |
| 16 | + pm_domains: pm_domains0 { | |
| 17 | + compatible = "stericsson,ux500-pm-domains"; | |
| 18 | + #power-domain-cells = <1>; | |
| 19 | + }; | |
| 20 | + | |
| 21 | +==PM domain consumers== | |
| 22 | + | |
| 23 | +Required properties: | |
| 24 | + - power-domains: A phandle and PM domain specifier. Below are the list of | |
| 25 | + valid specifiers: | |
| 26 | + | |
| 27 | + Index Specifier | |
| 28 | + ----- --------- | |
| 29 | + 0 DOMAIN_VAPE | |
| 30 | + | |
| 31 | +Example: | |
| 32 | + sdi0_per1@80126000 { | |
| 33 | + compatible = "arm,pl18x", "arm,primecell"; | |
| 34 | + power-domains = <&pm_domains DOMAIN_VAPE> | |
| 35 | + }; | |
| @@ -2,7 +2,11 @@ Broadcom GISB bus Arbiter controller · 1 unmodified line | ||
| 2 | 2 | |
| 3 | 3 | Required properties: |
| 4 | 4 | |
| 5 | −- compatible: should be "brcm,gisb-arb" | |
| 5 | +- compatible: | |
| 6 | + "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips | |
| 7 | + "brcm,bcm7435-gisb-arb" for newer 40nm chips | |
| 8 | + "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips | |
| 9 | + "brcm,bcm7038-gisb-arb" for 130nm chips | |
| 6 | 10 | - reg: specifies the base physical address and size of the registers |
| 7 | 11 | - interrupt-parent: specifies the phandle to the parent interrupt controller |
| 8 | 12 | this arbiter gets interrupt line from |
| @@ -48,9 +48,12 @@ Required properties: · 47 unmodified lines | ||
| 48 | 48 | - compatible: Should be set to "marvell,mbus-controller". |
| 49 | 49 | |
| 50 | 50 | - reg: Device's register space. |
| 51 | − Two entries are expected (see the examples below): | |
| 52 | − the first one controls the devices decoding window and | |
| 53 | − the second one controls the SDRAM decoding window. | |
| 51 | + Two or three entries are expected (see the examples below): | |
| 52 | + the first one controls the devices decoding window, | |
| 53 | + the second one controls the SDRAM decoding window and | |
| 54 | + the third controls the MBus bridge (only with the | |
| 55 | + marvell,armada370-mbus and marvell,armadaxp-mbus | |
| 56 | + compatible strings) | |
| 54 | 57 | |
| 55 | 58 | Example: |
| 56 | 59 | |
| @@ -67,7 +70,7 @@ Example: · 10 unmodified lines | ||
| 67 | 70 | |
| 68 | 71 | mbusc: mbus-controller@20000 { |
| 69 | 72 | compatible = "marvell,mbus-controller"; |
| 70 | − reg = <0x20000 0x100>, <0x20180 0x20>; | |
| 73 | + reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; | |
| 71 | 74 | }; |
| 72 | 75 | |
| 73 | 76 | /* more children ...*/ |
| @@ -126,7 +129,7 @@ are skipped. · 52 unmodified lines | ||
| 126 | 129 | |
| 127 | 130 | mbusc: mbus-controller@20000 { |
| 128 | 131 | compatible = "marvell,mbus-controller"; |
| 129 | − reg = <0x20000 0x100>, <0x20180 0x20>; | |
| 132 | + reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; | |
| 130 | 133 | }; |
| 131 | 134 | |
| 132 | 135 | /* more children ...*/ |
| @@ -170,7 +173,7 @@ Using this macro, the above example would be: · 37 unmodified lines | ||
| 170 | 173 | |
| 171 | 174 | mbusc: mbus-controller@20000 { |
| 172 | 175 | compatible = "marvell,mbus-controller"; |
| 173 | − reg = <0x20000 0x100>, <0x20180 0x20>; | |
| 176 | + reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; | |
| 174 | 177 | }; |
| 175 | 178 | |
| 176 | 179 | /* other children */ |
| @@ -266,7 +269,7 @@ See the example below, where a more complete device tree is shown: · 89 unmodified lines | ||
| 266 | 269 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; |
| 267 | 270 | |
| 268 | 271 | mbusc: mbus-controller@20000 { |
| 269 | − reg = <0x20000 0x100>, <0x20180 0x20>; | |
| 272 | + reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; | |
| 270 | 273 | }; |
| 271 | 274 | |
| 272 | 275 | interrupt-controller@20000 { |
| @@ -0,0 +1,34 @@ | ||
| 1 | +Broadcom Cygnus Clocks | |
| 2 | + | |
| 3 | +This binding uses the common clock binding: | |
| 4 | +Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| 5 | + | |
| 6 | +Currently various "fixed" clocks are declared for peripheral drivers that use | |
| 7 | +the common clock framework to reference their core clocks. Proper support of | |
| 8 | +these clocks will be added later | |
| 9 | + | |
| 10 | +Device tree example: | |
| 11 | + | |
| 12 | + clocks { | |
| 13 | + #address-cells = <1>; | |
| 14 | + #size-cells = <1>; | |
| 15 | + ranges; | |
| 16 | + | |
| 17 | + osc: oscillator { | |
| 18 | + compatible = "fixed-clock"; | |
| 19 | + #clock-cells = <1>; | |
| 20 | + clock-frequency = <25000000>; | |
| 21 | + }; | |
| 22 | + | |
| 23 | + apb_clk: apb_clk { | |
| 24 | + compatible = "fixed-clock"; | |
| 25 | + #clock-cells = <0>; | |
| 26 | + clock-frequency = <1000000000>; | |
| 27 | + }; | |
| 28 | + | |
| 29 | + periph_clk: periph_clk { | |
| 30 | + compatible = "fixed-clock"; | |
| 31 | + #clock-cells = <0>; | |
| 32 | + clock-frequency = <500000000>; | |
| 33 | + }; | |
| 34 | + }; | |
| @@ -5,6 +5,19 @@ Required properties: · 4 unmodified lines | ||
| 5 | 5 | - reg: Address and length of the register set |
| 6 | 6 | - #clock-cells: Should be <1> |
| 7 | 7 | |
| 8 | +Optional properties: | |
| 9 | +- clocks: list of clock identifiers which are external input clocks to the | |
| 10 | + given clock controller. Please refer the next section to find | |
| 11 | + the input clocks for a given controller. | |
| 12 | +- clock-names: list of names of clocks which are exteral input clocks to the | |
| 13 | + given clock controller. | |
| 14 | + | |
| 15 | +Input clocks for top clock controller: | |
| 16 | + - sxosc (external crystal oscillator 32KHz, recommended) | |
| 17 | + - fxosc (external crystal oscillator 24MHz, recommended) | |
| 18 | + - audio_ext | |
| 19 | + - enet_ext | |
| 20 | + | |
| 8 | 21 | The clock consumer should specify the desired clock by having the clock |
| 9 | 22 | ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h |
| 10 | 23 | for the full list of VF610 clock IDs. |
| @@ -15,6 +28,8 @@ clks: ccm@4006b000 { · 4 unmodified lines | ||
| 15 | 28 | compatible = "fsl,vf610-ccm"; |
| 16 | 29 | reg = <0x4006b000 0x1000>; |
| 17 | 30 | #clock-cells = <1>; |
| 31 | + clocks = <&sxosc>, <&fxosc>; | |
| 32 | + clock-names = "sxosc", "fxosc"; | |
| 18 | 33 | }; |
| 19 | 34 | |
| 20 | 35 | uart1: serial@40028000 { |
| @@ -25,7 +25,7 @@ Required child node properties: · 24 unmodified lines | ||
| 25 | 25 | - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or |
| 26 | 26 | "xlnx,axi-vdma-s2mm-channel". |
| 27 | 27 | - interrupts: Should contain per channel VDMA interrupts. |
| 28 | −- xlnx,data-width: Should contain the stream data width, take values | |
| 28 | +- xlnx,datawidth: Should contain the stream data width, take values | |
| 29 | 29 | {32,64...1024}. |
| 30 | 30 | |
| 31 | 31 | Optional child node properties: |
| @@ -0,0 +1,39 @@ | ||
| 1 | +ltc2978 | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: should contain one of: | |
| 5 | + * "lltc,ltc2974" | |
| 6 | + * "lltc,ltc2977" | |
| 7 | + * "lltc,ltc2978" | |
| 8 | + * "lltc,ltc3880" | |
| 9 | + * "lltc,ltc3883" | |
| 10 | + * "lltc,ltm4676" | |
| 11 | +- reg: I2C slave address | |
| 12 | + | |
| 13 | +Optional properties: | |
| 14 | +- regulators: A node that houses a sub-node for each regulator controlled by | |
| 15 | + the device. Each sub-node is identified using the node's name, with valid | |
| 16 | + values listed below. The content of each sub-node is defined by the | |
| 17 | + standard binding for regulators; see regulator.txt. | |
| 18 | + | |
| 19 | +Valid names of regulators depend on number of supplies supported per device: | |
| 20 | + * ltc2974 : vout0 - vout3 | |
| 21 | + * ltc2977 : vout0 - vout7 | |
| 22 | + * ltc2978 : vout0 - vout7 | |
| 23 | + * ltc3880 : vout0 - vout1 | |
| 24 | + * ltc3883 : vout0 | |
| 25 | + * ltm4676 : vout0 - vout1 | |
| 26 | + | |
| 27 | +Example: | |
| 28 | +ltc2978@5e { | |
| 29 | + compatible = "lltc,ltc2978"; | |
| 30 | + reg = <0x5e>; | |
| 31 | + regulators { | |
| 32 | + vout0 { | |
| 33 | + regulator-name = "FPGA-2.5V"; | |
| 34 | + }; | |
| 35 | + vout2 { | |
| 36 | + regulator-name = "FPGA-1.5V"; | |
| 37 | + }; | |
| 38 | + }; | |
| 39 | +}; | |
| @@ -32,6 +32,7 @@ Optional properties: · 31 unmodified lines | ||
| 32 | 32 | specified, default value is 0. |
| 33 | 33 | - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not |
| 34 | 34 | specified, the default value in Hz is 100000. |
| 35 | + - samsung,sysreg-phandle - handle to syscon used to control the system registers | |
| 35 | 36 | |
| 36 | 37 | Example: |
| 37 | 38 | |
| @@ -56,6 +56,8 @@ gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire In · 55 unmodified lines | ||
| 56 | 56 | infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) |
| 57 | 57 | infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) |
| 58 | 58 | isl,isl12057 Intersil ISL12057 I2C RTC Chip |
| 59 | +isil,isl29028 (deprecated, use isl) | |
| 60 | +isl,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor | |
| 59 | 61 | maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator |
| 60 | 62 | maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
| 61 | 63 | maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface |
| @@ -0,0 +1,21 @@ | ||
| 1 | +Device Tree bindings for MVEBU SDRAM controllers | |
| 2 | + | |
| 3 | +The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller | |
| 4 | +differs from one SoC variant to another, but they also share a number | |
| 5 | +of commonalities. | |
| 6 | + | |
| 7 | +For now, this Device Tree binding documentation only documents the | |
| 8 | +Armada XP SDRAM controller. | |
| 9 | + | |
| 10 | +Required properties: | |
| 11 | + | |
| 12 | + - compatible: for Armada XP, "marvell,armada-xp-sdram-controller" | |
| 13 | + - reg: a resource specifier for the register space, which should | |
| 14 | + include all SDRAM controller registers as per the datasheet. | |
| 15 | + | |
| 16 | +Example: | |
| 17 | + | |
| 18 | +sdramc@1400 { | |
| 19 | + compatible = "marvell,armada-xp-sdram-controller"; | |
| 20 | + reg = <0x1400 0x500>; | |
| 21 | +}; | |
| @@ -0,0 +1,36 @@ | ||
| 1 | +NVIDIA Tegra Memory Controller device tree bindings | |
| 2 | +=================================================== | |
| 3 | + | |
| 4 | +Required properties: | |
| 5 | +- compatible: Should be "nvidia,tegra<chip>-mc" | |
| 6 | +- reg: Physical base address and length of the controller's registers. | |
| 7 | +- clocks: Must contain an entry for each entry in clock-names. | |
| 8 | + See ../clocks/clock-bindings.txt for details. | |
| 9 | +- clock-names: Must include the following entries: | |
| 10 | + - mc: the module's clock input | |
| 11 | +- interrupts: The interrupt outputs from the controller. | |
| 12 | +- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines | |
| 13 | + the SWGROUP of the master. | |
| 14 | + | |
| 15 | +This device implements an IOMMU that complies with the generic IOMMU binding. | |
| 16 | +See ../iommu/iommu.txt for details. | |
| 17 | + | |
| 18 | +Example: | |
| 19 | +-------- | |
| 20 | + | |
| 21 | + mc: memory-controller@0,70019000 { | |
| 22 | + compatible = "nvidia,tegra124-mc"; | |
| 23 | + reg = <0x0 0x70019000 0x0 0x1000>; | |
| 24 | + clocks = <&tegra_car TEGRA124_CLK_MC>; | |
| 25 | + clock-names = "mc"; | |
| 26 | + | |
| 27 | + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 28 | + | |
| 29 | + #iommu-cells = <1>; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + sdhci@0,700b0000 { | |
| 33 | + compatible = "nvidia,tegra124-sdhci"; | |
| 34 | + ... | |
| 35 | + iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; | |
| 36 | + }; | |
| @@ -0,0 +1,51 @@ | ||
| 1 | +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | + - compatible: value should be one of the following: | |
| 5 | + "atmel,sama5d3-hlcdc" | |
| 6 | + - reg: base address and size of the HLCDC device registers. | |
| 7 | + - clock-names: the name of the 3 clocks requested by the HLCDC device. | |
| 8 | + Should contain "periph_clk", "sys_clk" and "slow_clk". | |
| 9 | + - clocks: should contain the 3 clocks requested by the HLCDC device. | |
| 10 | + - interrupts: should contain the description of the HLCDC interrupt line | |
| 11 | + | |
| 12 | +The HLCDC IP exposes two subdevices: | |
| 13 | + - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt | |
| 14 | + - a Display Controller: see ../drm/atmel-hlcdc-dc.txt | |
| 15 | + | |
| 16 | +Example: | |
| 17 | + | |
| 18 | + hlcdc: hlcdc@f0030000 { | |
| 19 | + compatible = "atmel,sama5d3-hlcdc"; | |
| 20 | + reg = <0xf0030000 0x2000>; | |
| 21 | + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; | |
| 22 | + clock-names = "periph_clk","sys_clk", "slow_clk"; | |
| 23 | + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 24 | + status = "disabled"; | |
| 25 | + | |
| 26 | + hlcdc-display-controller { | |
| 27 | + compatible = "atmel,hlcdc-display-controller"; | |
| 28 | + pinctrl-names = "default"; | |
| 29 | + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; | |
| 30 | + #address-cells = <1>; | |
| 31 | + #size-cells = <0>; | |
| 32 | + | |
| 33 | + port@0 { | |
| 34 | + #address-cells = <1>; | |
| 35 | + #size-cells = <0>; | |
| 36 | + reg = <0>; | |
| 37 | + | |
| 38 | + hlcdc_panel_output: endpoint@0 { | |
| 39 | + reg = <0>; | |
| 40 | + remote-endpoint = <&panel_input>; | |
| 41 | + }; | |
| 42 | + }; | |
| 43 | + }; | |
| 44 | + | |
| 45 | + hlcdc_pwm: hlcdc-pwm { | |
| 46 | + compatible = "atmel,hlcdc-pwm"; | |
| 47 | + pinctrl-names = "default"; | |
| 48 | + pinctrl-0 = <&pinctrl_lcd_pwm>; | |
| 49 | + #pwm-cells = <3>; | |
| 50 | + }; | |
| 51 | + }; | |
| @@ -34,6 +34,12 @@ to get matched with their hardware counterparts as follow: · 33 unmodified lines | ||
| 34 | 34 | -BUCKn : for BUCKs, where n can lie in range 1 to 9. |
| 35 | 35 | example: BUCK1, BUCK5, BUCK9. |
| 36 | 36 | |
| 37 | + Regulators which can be turned off during system suspend: | |
| 38 | + -LDOn : 2, 6-8, 10-12, 14-16, | |
| 39 | + -BUCKn : 1-4. | |
| 40 | + Use standard regulator bindings for it ('regulator-off-in-suspend'). | |
| 41 | + | |
| 42 | + | |
| 37 | 43 | Example: |
| 38 | 44 | |
| 39 | 45 | max77686@09 { |
| @@ -27,6 +27,20 @@ Optional properties: · 26 unmodified lines | ||
| 27 | 27 | |
| 28 | 28 | [*] refer Documentation/devicetree/bindings/regulator/regulator.txt |
| 29 | 29 | |
| 30 | +- haptic : The MAX77693 haptic device utilises a PWM controlled motor to provide | |
| 31 | + users with tactile feedback. PWM period and duty-cycle are varied in | |
| 32 | + order to provide the approprite level of feedback. | |
| 33 | + | |
| 34 | + Required properties: | |
| 35 | + - compatible : Must be "maxim,max77693-hpatic" | |
| 36 | + - haptic-supply : power supply for the haptic motor | |
| 37 | + [*] refer Documentation/devicetree/bindings/regulator/regulator.txt | |
| 38 | + - pwms : phandle to the physical PWM(Pulse Width Modulation) device. | |
| 39 | + PWM properties should be named "pwms". And number of cell is different | |
| 40 | + for each pwm device. | |
| 41 | + To get more informations, please refer to documentaion. | |
| 42 | + [*] refer Documentation/devicetree/bindings/pwm/pwm.txt | |
| 43 | + | |
| 30 | 44 | Example: |
| 31 | 45 | max77693@66 { |
| 32 | 46 | compatible = "maxim,max77693"; |
| @@ -52,4 +66,11 @@ Example: · 19 unmodified lines | ||
| 52 | 66 | regulator-boot-on; |
| 53 | 67 | }; |
| 54 | 68 | }; |
| 69 | + | |
| 70 | + haptic { | |
| 71 | + compatible = "maxim,max77693-haptic"; | |
| 72 | + haptic-supply = <&haptic_supply>; | |
| 73 | + pwms = <&pwm 0 40000 0>; | |
| 74 | + pwm-names = "haptic"; | |
| 75 | + }; | |
| 55 | 76 | }; |
| @@ -1,5 +1,5 @@ | ||
| 1 | 1 | |
| 2 | −* Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator | |
| 2 | +* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator | |
| 3 | 3 | |
| 4 | 4 | The Samsung S2MPS11 is a multi-function device which includes voltage and |
| 5 | 5 | current regulators, RTC, charger controller and other sub-blocks. It is |
| @@ -7,8 +7,8 @@ interfaced to the host controller using an I2C interface. Each sub-block is · 1 unmodified line | ||
| 7 | 7 | addressed by the host system using different I2C slave addresses. |
| 8 | 8 | |
| 9 | 9 | Required properties: |
| 10 | −- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic" | |
| 11 | − or "samsung,s2mpu02-pmic". | |
| 10 | +- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" | |
| 11 | + or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". | |
| 12 | 12 | - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. |
| 13 | 13 | |
| 14 | 14 | Optional properties: |
| @@ -17,8 +17,8 @@ Optional properties: · 2 unmodified lines | ||
| 17 | 17 | - interrupts: Interrupt specifiers for interrupt sources. |
| 18 | 18 | |
| 19 | 19 | Optional nodes: |
| 20 | −- clocks: s2mps11 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz | |
| 21 | − outputs, so to register these as clocks with common clock framework | |
| 20 | +- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 | |
| 21 | + KHz outputs, so to register these as clocks with common clock framework | |
| 22 | 22 | instantiate a sub-node named "clocks". It uses the common clock binding |
| 23 | 23 | documented in : |
| 24 | 24 | [Documentation/devicetree/bindings/clock/clock-bindings.txt] |
| @@ -30,12 +30,12 @@ Optional nodes: · 5 unmodified lines | ||
| 30 | 30 | the clock which they consume. |
| 31 | 31 | Clock ID Devices |
| 32 | 32 | ---------------------------------------------------------- |
| 33 | − 32KhzAP 0 S2MPS11, S2MPS14, S5M8767 | |
| 34 | − 32KhzCP 1 S2MPS11, S5M8767 | |
| 35 | − 32KhzBT 2 S2MPS11, S2MPS14, S5M8767 | |
| 33 | + 32KhzAP 0 S2MPS11, S2MPS13, S2MPS14, S5M8767 | |
| 34 | + 32KhzCP 1 S2MPS11, S2MPS13, S5M8767 | |
| 35 | + 32KhzBT 2 S2MPS11, S2MPS13, S2MPS14, S5M8767 | |
| 36 | 36 | |
| 37 | − - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps14-clk", | |
| 38 | − "samsung,s5m8767-clk" | |
| 37 | + - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", | |
| 38 | + "samsung,s2mps14-clk", "samsung,s5m8767-clk" | |
| 39 | 39 | |
| 40 | 40 | - regulators: The regulators of s2mps11 that have to be instantiated should be |
| 41 | 41 | included in a sub-node named 'regulators'. Regulator nodes included in this |
| @@ -81,12 +81,14 @@ as per the datasheet of s2mps11. · 39 unmodified lines | ||
| 81 | 81 | - LDOn |
| 82 | 82 | - valid values for n are: |
| 83 | 83 | - S2MPS11: 1 to 38 |
| 84 | + - S2MPS13: 1 to 40 | |
| 84 | 85 | - S2MPS14: 1 to 25 |
| 85 | 86 | - S2MPU02: 1 to 28 |
| 86 | 87 | - Example: LDO1, LDO2, LDO28 |
| 87 | 88 | - BUCKn |
| 88 | 89 | - valid values for n are: |
| 89 | 90 | - S2MPS11: 1 to 10 |
| 91 | + - S2MPS13: 1 to 10 | |
| 90 | 92 | - S2MPS14: 1 to 5 |
| 91 | 93 | - S2MPU02: 1 to 7 |
| 92 | 94 | - Example: BUCK1, BUCK2, BUCK9 |
| @@ -18,6 +18,10 @@ Required Properties: · 17 unmodified lines | ||
| 18 | 18 | specific extensions. |
| 19 | 19 | - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 |
| 20 | 20 | specific extensions. |
| 21 | + - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7 | |
| 22 | + specific extensions. | |
| 23 | + - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 | |
| 24 | + specific extensions having an SMU. | |
| 21 | 25 | |
| 22 | 26 | * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface |
| 23 | 27 | unit (ciu) clock. This property is applicable only for Exynos5 SoC's and |
| @@ -0,0 +1,29 @@ | ||
| 1 | +* Imagination specific extensions to the Synopsys Designware Mobile Storage | |
| 2 | + Host Controller | |
| 3 | + | |
| 4 | +The Synopsys designware mobile storage host controller is used to interface | |
| 5 | +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents | |
| 6 | +differences between the core Synopsys dw mshc controller properties described | |
| 7 | +by synopsys-dw-mshc.txt and the properties used by the Imagination specific | |
| 8 | +extensions to the Synopsys Designware Mobile Storage Host Controller. | |
| 9 | + | |
| 10 | +Required Properties: | |
| 11 | + | |
| 12 | +* compatible: should be | |
| 13 | + - "img,pistachio-dw-mshc": for Pistachio SoCs | |
| 14 | + | |
| 15 | +Example: | |
| 16 | + | |
| 17 | + mmc@18142000 { | |
| 18 | + compatible = "img,pistachio-dw-mshc"; | |
| 19 | + reg = <0x18142000 0x400>; | |
| 20 | + interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>; | |
| 21 | + | |
| 22 | + clocks = <&system_clk>, <&sdhost_clk>; | |
| 23 | + clock-names = "biu", "ciu"; | |
| 24 | + | |
| 25 | + fifo-depth = <0x20>; | |
| 26 | + bus-width = <4>; | |
| 27 | + num-slots = <1>; | |
| 28 | + disable-wp; | |
| 29 | + }; | |
| @@ -12,6 +12,10 @@ Required properties: · 11 unmodified lines | ||
| 12 | 12 | * for "marvell,armada-380-sdhci", two register areas. The first one |
| 13 | 13 | for the SDHCI registers themselves, and the second one for the |
| 14 | 14 | AXI/Mbus bridge registers of the SDHCI unit. |
| 15 | +- clocks: Array of clocks required for SDHCI; requires at least one for | |
| 16 | + I/O clock. | |
| 17 | +- clock-names: Array of names corresponding to clocks property; shall be | |
| 18 | + "io" for I/O clock and "core" for optional core clock. | |
| 15 | 19 | |
| 16 | 20 | Optional properties: |
| 17 | 21 | - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning. |
| @@ -23,6 +27,8 @@ sdhci@d4280800 { · 5 unmodified lines | ||
| 23 | 27 | reg = <0xd4280800 0x800>; |
| 24 | 28 | bus-width = <8>; |
| 25 | 29 | interrupts = <27>; |
| 30 | + clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; | |
| 31 | + clock-names = "io", "core"; | |
| 26 | 32 | non-removable; |
| 27 | 33 | mrvl,clk-delay-cycles = <31>; |
| 28 | 34 | }; |
| @@ -32,5 +38,6 @@ sdhci@d8000 { · 3 unmodified lines | ||
| 32 | 38 | reg = <0xd8000 0x1000>, <0xdc000 0x100>; |
| 33 | 39 | interrupts = <0 25 0x4>; |
| 34 | 40 | clocks = <&gateclk 17>; |
| 41 | + clock-names = "io"; | |
| 35 | 42 | mrvl,clk-delay-cycles = <0x1F>; |
| 36 | 43 | }; |
| @@ -0,0 +1,62 @@ | ||
| 1 | +* Nios II Processor Binding | |
| 2 | + | |
| 3 | +This binding specifies what properties available in the device tree | |
| 4 | +representation of a Nios II Processor Core. | |
| 5 | + | |
| 6 | +Users can use sopc2dts tool for generating device tree sources (dts) from a | |
| 7 | +Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts | |
| 8 | + | |
| 9 | +Required properties: | |
| 10 | + | |
| 11 | +- compatible: Compatible property value should be "altr,nios2-1.0". | |
| 12 | +- reg: Contains CPU index. | |
| 13 | +- interrupt-controller: Specifies that the node is an interrupt controller | |
| 14 | +- #interrupt-cells: Specifies the number of cells needed to encode an | |
| 15 | + interrupt source, should be 1. | |
| 16 | +- clock-frequency: Contains the clock frequency for CPU, in Hz. | |
| 17 | +- dcache-line-size: Contains data cache line size. | |
| 18 | +- icache-line-size: Contains instruction line size. | |
| 19 | +- dcache-size: Contains data cache size. | |
| 20 | +- icache-size: Contains instruction cache size. | |
| 21 | +- altr,pid-num-bits: Specifies the number of bits to use to represent the process | |
| 22 | + identifier (PID). | |
| 23 | +- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. | |
| 24 | +- altr,tlb-num-entries: Specifies the number of entries in the TLB. | |
| 25 | +- altr,tlb-ptr-sz: Specifies size of TLB pointer. | |
| 26 | +- altr,has-mul: Specifies CPU hardware multipy support, should be 1. | |
| 27 | +- altr,has-mmu: Specifies CPU support MMU support, should be 1. | |
| 28 | +- altr,has-initda: Specifies CPU support initda instruction, should be 1. | |
| 29 | +- altr,reset-addr: Specifies CPU reset address | |
| 30 | +- altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address | |
| 31 | +- altr,exception-addr: Specifies CPU exception address | |
| 32 | + | |
| 33 | +Optional properties: | |
| 34 | +- altr,has-div: Specifies CPU hardware divide support | |
| 35 | +- altr,implementation: Nios II core implementation, this should be "fast"; | |
| 36 | + | |
| 37 | +Example: | |
| 38 | + | |
| 39 | +cpu@0x0 { | |
| 40 | + device_type = "cpu"; | |
| 41 | + compatible = "altr,nios2-1.0"; | |
| 42 | + reg = <0>; | |
| 43 | + interrupt-controller; | |
| 44 | + #interrupt-cells = <1>; | |
| 45 | + clock-frequency = <125000000>; | |
| 46 | + dcache-line-size = <32>; | |
| 47 | + icache-line-size = <32>; | |
| 48 | + dcache-size = <32768>; | |
| 49 | + icache-size = <32768>; | |
| 50 | + altr,implementation = "fast"; | |
| 51 | + altr,pid-num-bits = <8>; | |
| 52 | + altr,tlb-num-ways = <16>; | |
| 53 | + altr,tlb-num-entries = <128>; | |
| 54 | + altr,tlb-ptr-sz = <7>; | |
| 55 | + altr,has-div = <1>; | |
| 56 | + altr,has-mul = <1>; | |
| 57 | + altr,reset-addr = <0xc2800000>; | |
| 58 | + altr,fast-tlb-miss-addr = <0xc7fff400>; | |
| 59 | + altr,exception-addr = <0xd0000020>; | |
| 60 | + altr,has-initda = <1>; | |
| 61 | + altr,has-mmu = <1>; | |
| 62 | +}; | |
| @@ -0,0 +1,19 @@ | ||
| 1 | +Altera Timer | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | + | |
| 5 | +- compatible : should be "altr,timer-1.0" | |
| 6 | +- reg : Specifies base physical address and size of the registers. | |
| 7 | +- interrupt-parent: phandle of the interrupt controller | |
| 8 | +- interrupts : Should contain the timer interrupt number | |
| 9 | +- clock-frequency : The frequency of the clock that drives the counter, in Hz. | |
| 10 | + | |
| 11 | +Example: | |
| 12 | + | |
| 13 | +timer { | |
| 14 | + compatible = "altr,timer-1.0"; | |
| 15 | + reg = <0x00400000 0x00000020>; | |
| 16 | + interrupt-parent = <&cpu>; | |
| 17 | + interrupts = <11>; | |
| 18 | + clock-frequency = <125000000>; | |
| 19 | +}; | |
| @@ -0,0 +1,18 @@ | ||
| 1 | +* Generic system power control capability | |
| 2 | + | |
| 3 | +Power-management integrated circuits or miscellaneous hardware components are | |
| 4 | +sometimes able to control the system power. The device driver associated with these | |
| 5 | +components might need to define this capability, which tells the kernel that | |
| 6 | +it can be used to switch off the system. The corresponding device must have the | |
| 7 | +standard property "system-power-controller" in its device node. This property | |
| 8 | +marks the device as able to control the system power. In order to test if this | |
| 9 | +property is found programmatically, use the helper function | |
| 10 | +"of_device_is_system_power_controller" from of.h . | |
| 11 | + | |
| 12 | +Example: | |
| 13 | + | |
| 14 | +act8846: act8846@5 { | |
| 15 | + compatible = "active-semi,act8846"; | |
| 16 | + status = "okay"; | |
| 17 | + system-power-controller; | |
| 18 | +} | |
| @@ -0,0 +1,23 @@ | ||
| 1 | +i.mx6 Poweroff Driver | |
| 2 | + | |
| 3 | +SNVS_LPCR in SNVS module can power off the whole system by pull | |
| 4 | +PMIC_ON_REQ low if PMIC_ON_REQ is connected with external PMIC. | |
| 5 | +If you don't want to use PMIC_ON_REQ as power on/off control, | |
| 6 | +please set status='disabled' to disable this driver. | |
| 7 | + | |
| 8 | +Required Properties: | |
| 9 | +-compatible: "fsl,sec-v4.0-poweroff" | |
| 10 | +-reg: Specifies the physical address of the SNVS_LPCR register | |
| 11 | + | |
| 12 | +Example: | |
| 13 | + snvs@020cc000 { | |
| 14 | + compatible = "fsl,sec-v4.0-mon", "simple-bus"; | |
| 15 | + #address-cells = <1>; | |
| 16 | + #size-cells = <1>; | |
| 17 | + ranges = <0 0x020cc000 0x4000>; | |
| 18 | + ..... | |
| 19 | + snvs_poweroff: snvs-poweroff@38 { | |
| 20 | + compatible = "fsl,sec-v4.0-poweroff"; | |
| 21 | + reg = <0x38 0x4>; | |
| 22 | + }; | |
| 23 | + } | |
| @@ -5,6 +5,10 @@ Required properties: · 4 unmodified lines | ||
| 5 | 5 | - compatible: "active-semi,act8846" or "active-semi,act8865" |
| 6 | 6 | - reg: I2C slave address |
| 7 | 7 | |
| 8 | +Optional properties: | |
| 9 | +- system-power-controller: Telling whether or not this pmic is controlling | |
| 10 | + the system power. See Documentation/devicetree/bindings/power/power-controller.txt . | |
| 11 | + | |
| 8 | 12 | Any standard regulator properties can be used to configure the single regulator. |
| 9 | 13 | |
| 10 | 14 | The valid names for regulators are: |
| @@ -25,6 +25,29 @@ with their hardware counterparts as follow. The valid names are: · 24 unmodified lines | ||
| 25 | 25 | example: LDO1, LDO2, LDO35. |
| 26 | 26 | -BUCKn : for BUCKs, where n can lie in range 1 to 10. |
| 27 | 27 | example: BUCK1, BUCK5, BUCK10. |
| 28 | + | |
| 29 | +The max77802 regulator supports two different operating modes: Normal and Low | |
| 30 | +Power Mode. Some regulators support the modes to be changed at startup or by | |
| 31 | +the consumers during normal operation while others only support to change the | |
| 32 | +mode during system suspend. The standard regulator suspend states binding can | |
| 33 | +be used to configure the regulator operating mode. | |
| 34 | + | |
| 35 | +The regulators that support the standard "regulator-initial-mode" property, | |
| 36 | +changing their mode during normal operation are: LDOs 1, 3, 20 and 21. | |
| 37 | + | |
| 38 | +The possible values for "regulator-initial-mode" and "regulator-mode" are: | |
| 39 | + 1: Normal regulator voltage output mode. | |
| 40 | + 3: Low Power which reduces the quiescent current down to only 1uA | |
| 41 | + | |
| 42 | +The list of valid modes are defined in the dt-bindings/clock/maxim,max77802.h | |
| 43 | +header and can be included by device tree source files. | |
| 44 | + | |
| 45 | +The standard "regulator-mode" property can only be used for regulators that | |
| 46 | +support changing their mode to Low Power Mode during suspend. These regulators | |
| 47 | +are: BUCKs 2-4 and LDOs 1-35. Also, it only takes effect if the regulator has | |
| 48 | +been enabled for the given suspend state using "regulator-on-in-suspend" and | |
| 49 | +has not been disabled for that state using "regulator-off-in-suspend". | |
| 50 | + | |
| 28 | 51 | Example: |
| 29 | 52 | |
| 30 | 53 | max77802@09 { |
| @@ -36,11 +59,23 @@ Example: · 5 unmodified lines | ||
| 36 | 59 | #size-cells = <0>; |
| 37 | 60 | |
| 38 | 61 | regulators { |
| 62 | + ldo1_reg: LDO1 { | |
| 63 | + regulator-name = "vdd_1v0"; | |
| 64 | + regulator-min-microvolt = <1000000>; | |
| 65 | + regulator-max-microvolt = <1000000>; | |
| 66 | + regulator-always-on; | |
| 67 | + regulator-initial-mode = <MAX77802_OPMODE_LP>; | |
| 68 | + }; | |
| 69 | + | |
| 39 | 70 | ldo11_reg: LDO11 { |
| 40 | 71 | regulator-name = "vdd_ldo11"; |
| 41 | 72 | regulator-min-microvolt = <1900000>; |
| 42 | 73 | regulator-max-microvolt = <1900000>; |
| 43 | 74 | regulator-always-on; |
| 75 | + regulator-state-mem { | |
| 76 | + regulator-on-in-suspend; | |
| 77 | + regulator-mode = <MAX77802_OPMODE_LP>; | |
| 78 | + }; | |
| 44 | 79 | }; |
| 45 | 80 | |
| 46 | 81 | buck1_reg: BUCK1 { |
| @@ -19,6 +19,24 @@ Optional properties: · 18 unmodified lines | ||
| 19 | 19 | design requires. This property describes the total system ramp time |
| 20 | 20 | required due to the combination of internal ramping of the regulator itself, |
| 21 | 21 | and board design issues such as trace capacitance and load on the supply. |
| 22 | +- regulator-state-mem sub-root node for Suspend-to-RAM mode | |
| 23 | + : suspend to memory, the device goes to sleep, but all data stored in memory, | |
| 24 | + only some external interrupt can wake the device. | |
| 25 | +- regulator-state-disk sub-root node for Suspend-to-DISK mode | |
| 26 | + : suspend to disk, this state operates similarly to Suspend-to-RAM, | |
| 27 | + but includes a final step of writing memory contents to disk. | |
| 28 | +- regulator-state-[mem/disk] node has following common properties: | |
| 29 | + - regulator-on-in-suspend: regulator should be on in suspend state. | |
| 30 | + - regulator-off-in-suspend: regulator should be off in suspend state. | |
| 31 | + - regulator-suspend-microvolt: regulator should be set to this voltage | |
| 32 | + in suspend. | |
| 33 | + - regulator-mode: operating mode in the given suspend state. | |
| 34 | + The set of possible operating modes depends on the capabilities of | |
| 35 | + every hardware so the valid modes are documented on each regulator | |
| 36 | + device tree binding document. | |
| 37 | +- regulator-initial-mode: initial operating mode. The set of possible operating | |
| 38 | + modes depends on the capabilities of every hardware so each device binding | |
| 39 | + documentation explains which values the regulator supports. | |
| 22 | 40 | |
| 23 | 41 | Deprecated properties: |
| 24 | 42 | - regulator-compatible: If a regulator chip contains multiple |
| @@ -34,6 +52,10 @@ Example: · 9 unmodified lines | ||
| 34 | 52 | regulator-max-microvolt = <2500000>; |
| 35 | 53 | regulator-always-on; |
| 36 | 54 | vin-supply = <&vin>; |
| 55 | + | |
| 56 | + regulator-state-mem { | |
| 57 | + regulator-on-in-suspend; | |
| 58 | + }; | |
| 37 | 59 | }; |
| 38 | 60 | |
| 39 | 61 | Regulator Consumers: |
| @@ -1,6 +1,7 @@ | ||
| 1 | 1 | SKY81452 voltage regulator |
| 2 | 2 | |
| 3 | 3 | Required properties: |
| 4 | +- regulator node named lout. | |
| 4 | 5 | - any required generic properties defined in regulator.txt |
| 5 | 6 | |
| 6 | 7 | Optional properties: |
| @@ -9,8 +10,9 @@ Optional properties: · 2 unmodified lines | ||
| 9 | 10 | Example: |
| 10 | 11 | |
| 11 | 12 | regulator { |
| 12 | − /* generic regulator properties */ | |
| 13 | − regulator-name = "touch_en"; | |
| 14 | − regulator-min-microvolt = <4500000>; | |
| 15 | − regulator-max-microvolt = <8000000>; | |
| 13 | + lout { | |
| 14 | + regulator-name = "sky81452-lout"; | |
| 15 | + regulator-min-microvolt = <4500000>; | |
| 16 | + regulator-max-microvolt = <8000000>; | |
| 17 | + }; | |
| 16 | 18 | }; |
| @@ -0,0 +1,42 @@ | ||
| 1 | +STMicroelectronics STi family Sysconfig Picophy SoftReset Controller | |
| 2 | +============================================================================= | |
| 3 | + | |
| 4 | +This binding describes a reset controller device that is used to enable and | |
| 5 | +disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in | |
| 6 | +the STi family SoC system configuration registers. | |
| 7 | + | |
| 8 | +The actual action taken when softreset is asserted is hardware dependent. | |
| 9 | +However, when asserted it may not be possible to access the hardware's | |
| 10 | +registers and after an assert/deassert sequence the hardware's previous state | |
| 11 | +may no longer be valid. | |
| 12 | + | |
| 13 | +Please refer to Documentation/devicetree/bindings/reset/reset.txt | |
| 14 | +for common reset controller binding usage. | |
| 15 | + | |
| 16 | +Required properties: | |
| 17 | +- compatible: Should be "st,stih407-picophyreset" | |
| 18 | +- #reset-cells: 1, see below | |
| 19 | + | |
| 20 | +Example: | |
| 21 | + | |
| 22 | + picophyreset: picophyreset-controller { | |
| 23 | + compatible = "st,stih407-picophyreset"; | |
| 24 | + #reset-cells = <1>; | |
| 25 | + }; | |
| 26 | + | |
| 27 | +Specifying picophyreset control of devices | |
| 28 | +======================================= | |
| 29 | + | |
| 30 | +Device nodes should specify the reset channel required in their "resets" | |
| 31 | +property, containing a phandle to the picophyreset device node and an | |
| 32 | +index specifying which channel to use, as described in | |
| 33 | +Documentation/devicetree/bindings/reset/reset.txt. | |
| 34 | + | |
| 35 | +Example: | |
| 36 | + | |
| 37 | + usb2_picophy0: usbpicophy@0 { | |
| 38 | + resets = <&picophyreset STIH407_PICOPHY0_RESET>; | |
| 39 | + }; | |
| 40 | + | |
| 41 | +Macro definitions for the supported reset channels can be found in: | |
| 42 | +include/dt-bindings/reset-controller/stih407-resets.h | |
| @@ -0,0 +1,23 @@ | ||
| 1 | +Atmel AT91SAM9260 Real Time Timer | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: should be: "atmel,at91sam9260-rtt" | |
| 5 | +- reg: should encode the memory region of the RTT controller | |
| 6 | +- interrupts: rtt alarm/event interrupt | |
| 7 | +- clocks: should contain the 32 KHz slow clk that will drive the RTT block. | |
| 8 | +- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store | |
| 9 | + the time base when the RTT is used as an RTC. | |
| 10 | + The first cell should point to the GPBR node and the second one | |
| 11 | + encode the offset within the GPBR block (or in other words, the | |
| 12 | + GPBR register used to store the time base). | |
| 13 | + | |
| 14 | + | |
| 15 | +Example: | |
| 16 | + | |
| 17 | +rtt@fffffd20 { | |
| 18 | + compatible = "atmel,at91sam9260-rtt"; | |
| 19 | + reg = <0xfffffd20 0x10>; | |
| 20 | + interrupts = <1 4 7>; | |
| 21 | + clocks = <&clk32k>; | |
| 22 | + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; | |
| 23 | +}; | |
| @@ -1,4 +1,4 @@ | ||
| 1 | −* Renesas R-Car Multi-Function Timer Pulse Unit 2 (MTU2) | |
| 1 | +* Renesas Multi-Function Timer Pulse Unit 2 (MTU2) | |
| 2 | 2 | |
| 3 | 3 | The MTU2 is a multi-purpose, multi-channel timer/counter with configurable |
| 4 | 4 | clock inputs and programmable compare match. |
| @@ -1,4 +1,4 @@ | ||
| 1 | −* Renesas R-Car Timer Unit (TMU) | |
| 1 | +* Renesas R-Mobile/R-Car Timer Unit (TMU) | |
| 2 | 2 | |
| 3 | 3 | The TMU is a 32-bit timer/counter with configurable clock inputs and |
| 4 | 4 | programmable compare match. |
| @@ -9,6 +9,8 @@ are independent. The TMU hardware supports up to three channels. · 4 unmodified lines | ||
| 9 | 9 | Required Properties: |
| 10 | 10 | |
| 11 | 11 | - compatible: must contain one or more of the following: |
| 12 | + - "renesas,tmu-r8a7740" for the r8a7740 TMU | |
| 13 | + - "renesas,tmu-r8a7778" for the r8a7778 TMU | |
| 12 | 14 | - "renesas,tmu-r8a7779" for the r8a7779 TMU |
| 13 | 15 | - "renesas,tmu" for any TMU. |
| 14 | 16 | This is a fallback for the above renesas,tmu-* entries |
| @@ -41,6 +41,7 @@ dallas Maxim Integrated Products (formerly Dallas Semiconductor) · 40 unmodified lines | ||
| 41 | 41 | davicom DAVICOM Semiconductor, Inc. |
| 42 | 42 | denx Denx Software Engineering |
| 43 | 43 | digi Digi International Inc. |
| 44 | +digilent Diglent, Inc. | |
| 44 | 45 | dlg Dialog Semiconductor |
| 45 | 46 | dlink D-Link Corporation |
| 46 | 47 | dmo Data Modul AG |
| @@ -78,6 +79,7 @@ innolux Innolux Corporation · 31 unmodified lines | ||
| 78 | 79 | intel Intel Corporation |
| 79 | 80 | intercontrol Inter Control Group |
| 80 | 81 | isee ISEE 2007 S.L. |
| 82 | +isil Intersil (deprecated, use isl) | |
| 81 | 83 | isl Intersil |
| 82 | 84 | karo Ka-Ro electronics GmbH |
| 83 | 85 | keymile Keymile GmbH |
| @@ -91,6 +93,7 @@ lltc Linear Technology Corporation · 7 unmodified lines | ||
| 91 | 93 | marvell Marvell Technology Group Ltd. |
| 92 | 94 | maxim Maxim Integrated Products |
| 93 | 95 | mediatek MediaTek Inc. |
| 96 | +merrii Merrii Technology Co., Ltd. | |
| 94 | 97 | micrel Micrel Inc. |
| 95 | 98 | microchip Microchip Technology Inc. |
| 96 | 99 | micron Micron Technology Inc. |
| @@ -149,6 +152,7 @@ st STMicroelectronics · 52 unmodified lines | ||
| 149 | 152 | ste ST-Ericsson |
| 150 | 153 | stericsson ST-Ericsson |
| 151 | 154 | synology Synology, Inc. |
| 155 | +tbs TBS Technologies | |
| 152 | 156 | thine THine Electronics, Inc. |
| 153 | 157 | ti Texas Instruments |
| 154 | 158 | tlm Trusted Logic Mobility |
| @@ -0,0 +1,17 @@ | ||
| 1 | +* OMAP HDQ One wire bus master controller | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible : should be "ti,omap3-1w" | |
| 5 | +- reg : Address and length of the register set for the device | |
| 6 | +- interrupts : interrupt line. | |
| 7 | +- ti,hwmods : "hdq1w" | |
| 8 | + | |
| 9 | +Example: | |
| 10 | + | |
| 11 | +- From omap3.dtsi | |
| 12 | + hdqw1w: 1w@480b2000 { | |
| 13 | + compatible = "ti,omap3-1w"; | |
| 14 | + reg = <0x480b2000 0x1000>; | |
| 15 | + interrupts = <58>; | |
| 16 | + ti,hwmods = "hdq1w"; | |
| 17 | + }; | |
| @@ -53,6 +53,11 @@ Supported chips: · 52 unmodified lines | ||
| 53 | 53 | http://www.ti.com/product/tmp75 |
| 54 | 54 | http://www.ti.com/product/tmp175 |
| 55 | 55 | http://www.ti.com/product/tmp275 |
| 56 | + * NXP LM75B | |
| 57 | + Prefix: 'lm75b' | |
| 58 | + Addresses scanned: none | |
| 59 | + Datasheet: Publicly available at the NXP website | |
| 60 | + http://www.nxp.com/documents/data_sheet/LM75B.pdf | |
| 56 | 61 | |
| 57 | 62 | Author: Frodo Looijaard <frodol@dds.nl> |
| 58 | 63 | |
| @@ -2,6 +2,10 @@ Kernel driver lm95234 · 1 unmodified line | ||
| 2 | 2 | ===================== |
| 3 | 3 | |
| 4 | 4 | Supported chips: |
| 5 | + * National Semiconductor / Texas Instruments LM95233 | |
| 6 | + Addresses scanned: I2C 0x18, 0x2a, 0x2b | |
| 7 | + Datasheet: Publicly available at the Texas Instruments website | |
| 8 | + http://www.ti.com/product/lm95233 | |
| 5 | 9 | * National Semiconductor / Texas Instruments LM95234 |
| 6 | 10 | Addresses scanned: I2C 0x18, 0x4d, 0x4e |
| 7 | 11 | Datasheet: Publicly available at the Texas Instruments website |
| @@ -13,11 +17,12 @@ Author: Guenter Roeck <linux@roeck-us.net> · 5 unmodified lines | ||
| 13 | 17 | Description |
| 14 | 18 | ----------- |
| 15 | 19 | |
| 16 | −LM95234 is an 11-bit digital temperature sensor with a 2-wire System Management | |
| 17 | −Bus (SMBus) interface and TrueTherm technology that can very accurately monitor | |
| 18 | −the temperature of four remote diodes as well as its own temperature. | |
| 19 | −The four remote diodes can be external devices such as microprocessors, | |
| 20 | −graphics processors or diode-connected 2N3904s. The LM95234's TruTherm | |
| 20 | +LM95233 and LM95234 are 11-bit digital temperature sensors with a 2-wire | |
| 21 | +System Management Bus (SMBus) interface and TrueTherm technology | |
| 22 | +that can very accurately monitor the temperature of two (LM95233) | |
| 23 | +or four (LM95234) remote diodes as well as its own temperature. | |
| 24 | +The remote diodes can be external devices such as microprocessors, | |
| 25 | +graphics processors or diode-connected 2N3904s. The chip's TruTherm | |
| 21 | 26 | beta compensation technology allows sensing of 90 nm or 65 nm process |
| 22 | 27 | thermal diodes accurately. |
| 23 | 28 | |
| @@ -2,10 +2,14 @@ Kernel driver lm95245 · 1 unmodified line | ||
| 2 | 2 | ================== |
| 3 | 3 | |
| 4 | 4 | Supported chips: |
| 5 | − * National Semiconductor LM95245 | |
| 5 | + * TI LM95235 | |
| 6 | + Addresses scanned: I2C 0x18, 0x29, 0x4c | |
| 7 | + Datasheet: Publicly available at the TI website | |
| 8 | + http://www.ti.com/lit/ds/symlink/lm95235.pdf | |
| 9 | + * TI / National Semiconductor LM95245 | |
| 6 | 10 | Addresses scanned: I2C 0x18, 0x19, 0x29, 0x4c, 0x4d |
| 7 | − Datasheet: Publicly available at the National Semiconductor website | |
| 8 | − http://www.national.com/mpf/LM/LM95245.html | |
| 11 | + Datasheet: Publicly available at the TI website | |
| 12 | + http://www.ti.com/lit/ds/symlink/lm95245.pdf | |
| 9 | 13 | |
| 10 | 14 | |
| 11 | 15 | Author: Alexander Stein <alexander.stein@systec-electronic.com> |
| @@ -13,10 +17,10 @@ Author: Alexander Stein <alexander.stein@systec-electronic.com> · 1 unmodified line | ||
| 13 | 17 | Description |
| 14 | 18 | ----------- |
| 15 | 19 | |
| 16 | −The LM95245 is an 11-bit digital temperature sensor with a 2-wire System | |
| 20 | +LM95235 and LM95245 are 11-bit digital temperature sensors with a 2-wire System | |
| 17 | 21 | Management Bus (SMBus) interface and TruTherm technology that can monitor |
| 18 | 22 | the temperature of a remote diode as well as its own temperature. |
| 19 | −The LM95245 can be used to very accurately monitor the temperature of | |
| 23 | +The chips can be used to very accurately monitor the temperature of | |
| 20 | 24 | external devices such as microprocessors. |
| 21 | 25 | |
| 22 | 26 | All temperature values are given in millidegrees Celsius. Local temperature |
| @@ -8,11 +8,15 @@ Kernel driver NCT6775 · 7 unmodified lines | ||
| 8 | 8 | ===================== |
| 9 | 9 | |
| 10 | 10 | Supported chips: |
| 11 | + * Nuvoton NCT6102D/NCT6104D/NCT6106D | |
| 12 | + Prefix: 'nct6106' | |
| 13 | + Addresses scanned: ISA address retrieved from Super I/O registers | |
| 14 | + Datasheet: Available from the Nuvoton web site | |
| 11 | 15 | * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I |
| 12 | 16 | Prefix: 'nct6775' |
| 13 | 17 | Addresses scanned: ISA address retrieved from Super I/O registers |
| 14 | 18 | Datasheet: Available from Nuvoton upon request |
| 15 | − * Nuvoton NCT5577D/NCT6776D/NCT6776F | |
| 19 | + * Nuvoton NCT5573D/NCT5577D/NCT6776D/NCT6776F | |
| 16 | 20 | Prefix: 'nct6776' |
| 17 | 21 | Addresses scanned: ISA address retrieved from Super I/O registers |
| 18 | 22 | Datasheet: Available from Nuvoton upon request |
| @@ -20,6 +24,14 @@ Supported chips: · 1 unmodified line | ||
| 20 | 24 | Prefix: 'nct6779' |
| 21 | 25 | Addresses scanned: ISA address retrieved from Super I/O registers |
| 22 | 26 | Datasheet: Available from Nuvoton upon request |
| 27 | + * Nuvoton NCT6791D | |
| 28 | + Prefix: 'nct6791' | |
| 29 | + Addresses scanned: ISA address retrieved from Super I/O registers | |
| 30 | + Datasheet: Available from Nuvoton upon request | |
| 31 | + * Nuvoton NCT6792D | |
| 32 | + Prefix: 'nct6792' | |
| 33 | + Addresses scanned: ISA address retrieved from Super I/O registers | |
| 34 | + Datasheet: Available from Nuvoton upon request | |
| 23 | 35 | |
| 24 | 36 | Authors: |
| 25 | 37 | Guenter Roeck <linux@roeck-us.net> |
| @@ -0,0 +1,32 @@ | ||
| 1 | +Kernel driver nct7802 | |
| 2 | +===================== | |
| 3 | + | |
| 4 | +Supported chips: | |
| 5 | + * Nuvoton NCT7802Y | |
| 6 | + Prefix: 'nct7802' | |
| 7 | + Addresses scanned: I2C 0x28..0x2f | |
| 8 | + Datasheet: Available from Nuvoton web site | |
| 9 | + | |
| 10 | +Authors: | |
| 11 | + Guenter Roeck <linux@roeck-us.net> | |
| 12 | + | |
| 13 | +Description | |
| 14 | +----------- | |
| 15 | + | |
| 16 | +This driver implements support for the Nuvoton NCT7802Y hardware monitoring | |
| 17 | +chip. NCT7802Y supports 6 temperature sensors, 5 voltage sensors, and 3 fan | |
| 18 | +speed sensors. | |
| 19 | + | |
| 20 | +The chip also supports intelligent fan speed control. This functionality is | |
| 21 | +not currently supported by the driver. | |
| 22 | + | |
| 23 | +Tested Boards and BIOS Versions | |
| 24 | +------------------------------- | |
| 25 | + | |
| 26 | +The driver has been reported to work with the following boards and | |
| 27 | +BIOS versions. | |
| 28 | + | |
| 29 | +Board BIOS version | |
| 30 | +--------------------------------------------------------------- | |
| 31 | +Kontron COMe-bSC2 CHR2E934.001.GGO | |
| 32 | +Kontron COMe-bIP2 CCR2E212 | |
| @@ -18,6 +18,10 @@ Supported chips: · 17 unmodified lines | ||
| 18 | 18 | Prefix: 'tmp432' |
| 19 | 19 | Addresses scanned: I2C 0x4c, 0x4d |
| 20 | 20 | Datasheet: http://focus.ti.com/docs/prod/folders/print/tmp432.html |
| 21 | + * Texas Instruments TMP435 | |
| 22 | + Prefix: 'tmp435' | |
| 23 | + Addresses scanned: I2C 0x37, 0x48 - 0x4f | |
| 24 | + Datasheet: http://focus.ti.com/docs/prod/folders/print/tmp435.html | |
| 21 | 25 | |
| 22 | 26 | Authors: |
| 23 | 27 | Hans de Goede <hdegoede@redhat.com> |
| @@ -27,8 +31,8 @@ Description · 3 unmodified lines | ||
| 27 | 31 | ----------- |
| 28 | 32 | |
| 29 | 33 | This driver implements support for Texas Instruments TMP401, TMP411, |
| 30 | −TMP431, and TMP432 chips. These chips implement one or two remote and | |
| 31 | −one local temperature sensors. Temperature is measured in degrees | |
| 34 | +TMP431, TMP432 and TMP435 chips. These chips implement one or two remote | |
| 35 | +and one local temperature sensors. Temperature is measured in degrees | |
| 32 | 36 | Celsius. Resolution of the remote sensor is 0.0625 degree. Local |
| 33 | 37 | sensor resolution can be set to 0.5, 0.25, 0.125 or 0.0625 degree (not |
| 34 | 38 | supported by the driver so far, so using the default resolution of 0.5 |
| @@ -2940,6 +2940,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 2939 unmodified lines | ||
| 2940 | 2940 | quiescent states. Units are jiffies, minimum |
| 2941 | 2941 | value is one, and maximum value is HZ. |
| 2942 | 2942 | |
| 2943 | + rcutree.kthread_prio= [KNL,BOOT] | |
| 2944 | + Set the SCHED_FIFO priority of the RCU | |
| 2945 | + per-CPU kthreads (rcuc/N). This value is also | |
| 2946 | + used for the priority of the RCU boost threads | |
| 2947 | + (rcub/N). Valid values are 1-99 and the default | |
| 2948 | + is 1 (the least-favored priority). | |
| 2949 | + | |
| 2943 | 2950 | rcutree.rcu_nocb_leader_stride= [KNL] |
| 2944 | 2951 | Set the number of NOCB kthread groups, which |
| 2945 | 2952 | defaults to the square root of the number of |
| @@ -3089,6 +3096,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 143 unmodified lines | ||
| 3089 | 3096 | messages. Disable with a value less than or equal |
| 3090 | 3097 | to zero. |
| 3091 | 3098 | |
| 3099 | + rcupdate.rcu_self_test= [KNL] | |
| 3100 | + Run the RCU early boot self tests | |
| 3101 | + | |
| 3102 | + rcupdate.rcu_self_test_bh= [KNL] | |
| 3103 | + Run the RCU bh early boot self tests | |
| 3104 | + | |
| 3105 | + rcupdate.rcu_self_test_sched= [KNL] | |
| 3106 | + Run the RCU sched early boot self tests | |
| 3107 | + | |
| 3092 | 3108 | rdinit= [KNL] |
| 3093 | 3109 | Format: <full_path> |
| 3094 | 3110 | Run specified binary instead of /init from the ramdisk, |
| @@ -0,0 +1,166 @@ | ||
| 1 | +lglock - local/global locks for mostly local access patterns | |
| 2 | +------------------------------------------------------------ | |
| 3 | + | |
| 4 | +Origin: Nick Piggin's VFS scalability series introduced during | |
| 5 | + 2.6.35++ [1] [2] | |
| 6 | +Location: kernel/locking/lglock.c | |
| 7 | + include/linux/lglock.h | |
| 8 | +Users: currently only the VFS and stop_machine related code | |
| 9 | + | |
| 10 | +Design Goal: | |
| 11 | +------------ | |
| 12 | + | |
| 13 | +Improve scalability of globally used large data sets that are | |
| 14 | +distributed over all CPUs as per_cpu elements. | |
| 15 | + | |
| 16 | +To manage global data structures that are partitioned over all CPUs | |
| 17 | +as per_cpu elements but can be mostly handled by CPU local actions | |
| 18 | +lglock will be used where the majority of accesses are cpu local | |
| 19 | +reading and occasional cpu local writing with very infrequent | |
| 20 | +global write access. | |
| 21 | + | |
| 22 | + | |
| 23 | +* deal with things locally whenever possible | |
| 24 | + - very fast access to the local per_cpu data | |
| 25 | + - reasonably fast access to specific per_cpu data on a different | |
| 26 | + CPU | |
| 27 | +* while making global action possible when needed | |
| 28 | + - by expensive access to all CPUs locks - effectively | |
| 29 | + resulting in a globally visible critical section. | |
| 30 | + | |
| 31 | +Design: | |
| 32 | +------- | |
| 33 | + | |
| 34 | +Basically it is an array of per_cpu spinlocks with the | |
| 35 | +lg_local_lock/unlock accessing the local CPUs lock object and the | |
| 36 | +lg_local_lock_cpu/unlock_cpu accessing a remote CPUs lock object | |
| 37 | +the lg_local_lock has to disable preemption as migration protection so | |
| 38 | +that the reference to the local CPUs lock does not go out of scope. | |
| 39 | +Due to the lg_local_lock/unlock only touching cpu-local resources it | |
| 40 | +is fast. Taking the local lock on a different CPU will be more | |
| 41 | +expensive but still relatively cheap. | |
| 42 | + | |
| 43 | +One can relax the migration constraints by acquiring the current | |
| 44 | +CPUs lock with lg_local_lock_cpu, remember the cpu, and release that | |
| 45 | +lock at the end of the critical section even if migrated. This should | |
| 46 | +give most of the performance benefits without inhibiting migration | |
| 47 | +though needs careful considerations for nesting of lglocks and | |
| 48 | +consideration of deadlocks with lg_global_lock. | |
| 49 | + | |
| 50 | +The lg_global_lock/unlock locks all underlying spinlocks of all | |
| 51 | +possible CPUs (including those off-line). The preemption disable/enable | |
| 52 | +are needed in the non-RT kernels to prevent deadlocks like: | |
| 53 | + | |
| 54 | + on cpu 1 | |
| 55 | + | |
| 56 | + task A task B | |
| 57 | + lg_global_lock | |
| 58 | + got cpu 0 lock | |
| 59 | + <<<< preempt <<<< | |
| 60 | + lg_local_lock_cpu for cpu 0 | |
| 61 | + spin on cpu 0 lock | |
| 62 | + | |
| 63 | +On -RT this deadlock scenario is resolved by the arch_spin_locks in the | |
| 64 | +lglocks being replaced by rt_mutexes which resolve the above deadlock | |
| 65 | +by boosting the lock-holder. | |
| 66 | + | |
| 67 | + | |
| 68 | +Implementation: | |
| 69 | +--------------- | |
| 70 | + | |
| 71 | +The initial lglock implementation from Nick Piggin used some complex | |
| 72 | +macros to generate the lglock/brlock in lglock.h - they were later | |
| 73 | +turned into a set of functions by Andi Kleen [7]. The change to functions | |
| 74 | +was motivated by the presence of multiple lock users and also by them | |
| 75 | +being easier to maintain than the generating macros. This change to | |
| 76 | +functions is also the basis to eliminated the restriction of not | |
| 77 | +being initializeable in kernel modules (the remaining problem is that | |
| 78 | +locks are not explicitly initialized - see lockdep-design.txt) | |
| 79 | + | |
| 80 | +Declaration and initialization: | |
| 81 | +------------------------------- | |
| 82 | + | |
| 83 | + #include <linux/lglock.h> | |
| 84 | + | |
| 85 | + DEFINE_LGLOCK(name) | |
| 86 | + or: | |
| 87 | + DEFINE_STATIC_LGLOCK(name); | |
| 88 | + | |
| 89 | + lg_lock_init(&name, "lockdep_name_string"); | |
| 90 | + | |
| 91 | + on UP this is mapped to DEFINE_SPINLOCK(name) in both cases, note | |
| 92 | + also that as of 3.18-rc6 all declaration in use are of the _STATIC_ | |
| 93 | + variant (and it seems that the non-static was never in use). | |
| 94 | + lg_lock_init is initializing the lockdep map only. | |
| 95 | + | |
| 96 | +Usage: | |
| 97 | +------ | |
| 98 | + | |
| 99 | +From the locking semantics it is a spinlock. It could be called a | |
| 100 | +locality aware spinlock. lg_local_* behaves like a per_cpu | |
| 101 | +spinlock and lg_global_* like a global spinlock. | |
| 102 | +No surprises in the API. | |
| 103 | + | |
| 104 | + lg_local_lock(*lglock); | |
| 105 | + access to protected per_cpu object on this CPU | |
| 106 | + lg_local_unlock(*lglock); | |
| 107 | + | |
| 108 | + lg_local_lock_cpu(*lglock, cpu); | |
| 109 | + access to protected per_cpu object on other CPU cpu | |
| 110 | + lg_local_unlock_cpu(*lglock, cpu); | |
| 111 | + | |
| 112 | + lg_global_lock(*lglock); | |
| 113 | + access all protected per_cpu objects on all CPUs | |
| 114 | + lg_global_unlock(*lglock); | |
| 115 | + | |
| 116 | + There are no _trylock variants of the lglocks. | |
| 117 | + | |
| 118 | +Note that the lg_global_lock/unlock has to iterate over all possible | |
| 119 | +CPUs rather than the actually present CPUs or a CPU could go off-line | |
| 120 | +with a held lock [4] and that makes it very expensive. A discussion on | |
| 121 | +these issues can be found at [5] | |
| 122 | + | |
| 123 | +Constraints: | |
| 124 | +------------ | |
| 125 | + | |
| 126 | + * currently the declaration of lglocks in kernel modules is not | |
| 127 | + possible, though this should be doable with little change. | |
| 128 | + * lglocks are not recursive. | |
| 129 | + * suitable for code that can do most operations on the CPU local | |
| 130 | + data and will very rarely need the global lock | |
| 131 | + * lg_global_lock/unlock is *very* expensive and does not scale | |
| 132 | + * on UP systems all lg_* primitives are simply spinlocks | |
| 133 | + * in PREEMPT_RT the spinlock becomes an rt-mutex and can sleep but | |
| 134 | + does not change the tasks state while sleeping [6]. | |
| 135 | + * in PREEMPT_RT the preempt_disable/enable in lg_local_lock/unlock | |
| 136 | + is downgraded to a migrate_disable/enable, the other | |
| 137 | + preempt_disable/enable are downgraded to barriers [6]. | |
| 138 | + The deadlock noted for non-RT above is resolved due to rt_mutexes | |
| 139 | + boosting the lock-holder in this case which arch_spin_locks do | |
| 140 | + not do. | |
| 141 | + | |
| 142 | +lglocks were designed for very specific problems in the VFS and probably | |
| 143 | +only are the right answer in these corner cases. Any new user that looks | |
| 144 | +at lglocks probably wants to look at the seqlock and RCU alternatives as | |
| 145 | +her first choice. There are also efforts to resolve the RCU issues that | |
| 146 | +currently prevent using RCU in place of view remaining lglocks. | |
| 147 | + | |
| 148 | +Note on brlock history: | |
| 149 | +----------------------- | |
| 150 | + | |
| 151 | +The 'Big Reader' read-write spinlocks were originally introduced by | |
| 152 | +Ingo Molnar in 2000 (2.4/2.5 kernel series) and removed in 2003. They | |
| 153 | +later were introduced by the VFS scalability patch set in 2.6 series | |
| 154 | +again as the "big reader lock" brlock [2] variant of lglock which has | |
| 155 | +been replaced by seqlock primitives or by RCU based primitives in the | |
| 156 | +3.13 kernel series as was suggested in [3] in 2003. The brlock was | |
| 157 | +entirely removed in the 3.13 kernel series. | |
| 158 | + | |
| 159 | +Link: 1 http://lkml.org/lkml/2010/8/2/81 | |
| 160 | +Link: 2 http://lwn.net/Articles/401738/ | |
| 161 | +Link: 3 http://lkml.org/lkml/2003/3/9/205 | |
| 162 | +Link: 4 https://lkml.org/lkml/2011/8/24/185 | |
| 163 | +Link: 5 http://lkml.org/lkml/2011/12/18/189 | |
| 164 | +Link: 6 https://www.kernel.org/pub/linux/kernel/projects/rt/ | |
| 165 | + patch series - lglocks-rt.patch.patch | |
| 166 | +Link: 7 http://lkml.org/lkml/2012/3/5/26 | |
| @@ -121,22 +121,22 @@ For example, consider the following sequence of events: · 120 unmodified lines | ||
| 121 | 121 | The set of accesses as seen by the memory system in the middle can be arranged |
| 122 | 122 | in 24 different combinations: |
| 123 | 123 | |
| 124 | − STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4 | |
| 125 | − STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3 | |
| 126 | − STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4 | |
| 127 | − STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4 | |
| 128 | − STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3 | |
| 129 | − STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4 | |
| 130 | − STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4 | |
| 124 | + STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4 | |
| 125 | + STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3 | |
| 126 | + STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4 | |
| 127 | + STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4 | |
| 128 | + STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3 | |
| 129 | + STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4 | |
| 130 | + STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4 | |
| 131 | 131 | STORE B=4, ... |
| 132 | 132 | ... |
| 133 | 133 | |
| 134 | 134 | and can thus result in four different combinations of values: |
| 135 | 135 | |
| 136 | − x == 1, y == 2 | |
| 137 | − x == 1, y == 4 | |
| 138 | − x == 3, y == 2 | |
| 139 | − x == 3, y == 4 | |
| 136 | + x == 2, y == 1 | |
| 137 | + x == 2, y == 3 | |
| 138 | + x == 4, y == 1 | |
| 139 | + x == 4, y == 3 | |
| 140 | 140 | |
| 141 | 141 | |
| 142 | 142 | Furthermore, the stores committed by a CPU to the memory system may not be |
| @@ -694,6 +694,24 @@ Please note once again that the stores to 'b' differ. If they were · 551 unmodified lines | ||
| 694 | 694 | identical, as noted earlier, the compiler could pull this store outside |
| 695 | 695 | of the 'if' statement. |
| 696 | 696 | |
| 697 | +You must also be careful not to rely too much on boolean short-circuit | |
| 698 | +evaluation. Consider this example: | |
| 699 | + | |
| 700 | + q = ACCESS_ONCE(a); | |
| 701 | + if (a || 1 > 0) | |
| 702 | + ACCESS_ONCE(b) = 1; | |
| 703 | + | |
| 704 | +Because the second condition is always true, the compiler can transform | |
| 705 | +this example as following, defeating control dependency: | |
| 706 | + | |
| 707 | + q = ACCESS_ONCE(a); | |
| 708 | + ACCESS_ONCE(b) = 1; | |
| 709 | + | |
| 710 | +This example underscores the need to ensure that the compiler cannot | |
| 711 | +out-guess your code. More generally, although ACCESS_ONCE() does force | |
| 712 | +the compiler to actually emit code for a given load, it does not force | |
| 713 | +the compiler to use the results. | |
| 714 | + | |
| 697 | 715 | Finally, control dependencies do -not- provide transitivity. This is |
| 698 | 716 | demonstrated by two related examples, with the initial values of |
| 699 | 717 | x and y both being zero: |
| @@ -2465,10 +2483,15 @@ functions: · 1765 unmodified lines | ||
| 2465 | 2483 | Please refer to the PCI specification for more information on interactions |
| 2466 | 2484 | between PCI transactions. |
| 2467 | 2485 | |
| 2468 | − (*) readX_relaxed() | |
| 2486 | + (*) readX_relaxed(), writeX_relaxed() | |
| 2469 | 2487 | |
| 2470 | − These are similar to readX(), but are not guaranteed to be ordered in any | |
| 2471 | − way. Be aware that there is no I/O read barrier available. | |
| 2488 | + These are similar to readX() and writeX(), but provide weaker memory | |
| 2489 | + ordering guarantees. Specifically, they do not guarantee ordering with | |
| 2490 | + respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee | |
| 2491 | + ordering with respect to LOCK or UNLOCK operations. If the latter is | |
| 2492 | + required, an mmiowb() barrier can be used. Note that relaxed accesses to | |
| 2493 | + the same peripheral are guaranteed to be ordered with respect to each | |
| 2494 | + other. | |
| 2472 | 2495 | |
| 2473 | 2496 | (*) ioreadX(), iowriteX() |
| 2474 | 2497 | |
| @@ -136,7 +136,7 @@ SOF_TIMESTAMPING_OPT_ID: · 135 unmodified lines | ||
| 136 | 136 | |
| 137 | 137 | This option is implemented only for transmit timestamps. There, the |
| 138 | 138 | timestamp is always looped along with a struct sock_extended_err. |
| 139 | − The option modifies field ee_info to pass an id that is unique | |
| 139 | + The option modifies field ee_data to pass an id that is unique | |
| 140 | 140 | among all possibly concurrently outstanding timestamp requests for |
| 141 | 141 | that socket. In practice, it is a monotonically increasing u32 |
| 142 | 142 | (that wraps). |
| @@ -0,0 +1,23 @@ | ||
| 1 | +Linux on the Nios II architecture | |
| 2 | +================================= | |
| 3 | + | |
| 4 | +This is a port of Linux to Nios II (nios2) processor. | |
| 5 | + | |
| 6 | +In order to compile for Nios II, you need a version of GCC with support for the generic | |
| 7 | +system call ABI. Please see this link for more information on how compiling and booting | |
| 8 | +software for the Nios II platform: | |
| 9 | +http://www.rocketboards.org/foswiki/Documentation/NiosIILinuxUserManual | |
| 10 | + | |
| 11 | +For reference, please see the following link: | |
| 12 | +http://www.altera.com/literature/lit-nio2.jsp | |
| 13 | + | |
| 14 | +What is Nios II? | |
| 15 | +================ | |
| 16 | +Nios II is a 32-bit embedded-processor architecture designed specifically for the | |
| 17 | +Altera family of FPGAs. In order to support Linux, Nios II needs to be configured | |
| 18 | +with MMU and hardware multiplier enabled. | |
| 19 | + | |
| 20 | +Nios II ABI | |
| 21 | +=========== | |
| 22 | +Please refer to chapter "Application Binary Interface" in Nios II Processor Reference | |
| 23 | +Handbook. | |
| @@ -226,9 +226,6 @@ static int register_sas_ha(struct my_sas_ha *my_ha) · 225 unmodified lines | ||
| 226 | 226 | my_ha->sas_ha.lldd_dev_found = my_dev_found; |
| 227 | 227 | my_ha->sas_ha.lldd_dev_gone = my_dev_gone; |
| 228 | 228 | |
| 229 | − my_ha->sas_ha.lldd_max_execute_num = lldd_max_execute_num; (1) | |
| 230 | − | |
| 231 | − my_ha->sas_ha.lldd_queue_size = ha_can_queue; | |
| 232 | 229 | my_ha->sas_ha.lldd_execute_task = my_execute_task; |
| 233 | 230 | |
| 234 | 231 | my_ha->sas_ha.lldd_abort_task = my_abort_task; |
| @@ -247,28 +244,6 @@ static int register_sas_ha(struct my_sas_ha *my_ha) · 12 unmodified lines | ||
| 247 | 244 | return sas_register_ha(&my_ha->sas_ha); |
| 248 | 245 | } |
| 249 | 246 | |
| 250 | −(1) This is normally a LLDD parameter, something of the | |
| 251 | −lines of a task collector. What it tells the SAS Layer is | |
| 252 | −whether the SAS layer should run in Direct Mode (default: | |
| 253 | −value 0 or 1) or Task Collector Mode (value greater than 1). | |
| 254 | − | |
| 255 | −In Direct Mode, the SAS Layer calls Execute Task as soon as | |
| 256 | −it has a command to send to the SDS, _and_ this is a single | |
| 257 | −command, i.e. not linked. | |
| 258 | − | |
| 259 | −Some hardware (e.g. aic94xx) has the capability to DMA more | |
| 260 | −than one task at a time (interrupt) from host memory. Task | |
| 261 | −Collector Mode is an optional feature for HAs which support | |
| 262 | −this in their hardware. (Again, it is completely optional | |
| 263 | −even if your hardware supports it.) | |
| 264 | − | |
| 265 | −In Task Collector Mode, the SAS Layer would do _natural_ | |
| 266 | −coalescing of tasks and at the appropriate moment it would | |
| 267 | −call your driver to DMA more than one task in a single HA | |
| 268 | −interrupt. DMBS may want to use this by insmod/modprobe | |
| 269 | −setting the lldd_max_execute_num to something greater than | |
| 270 | −1. | |
| 271 | − | |
| 272 | 247 | (2) SAS 1.1 does not define I_T Nexus Reset TMF. |
| 273 | 248 | |
| 274 | 249 | Events |
| @@ -325,71 +300,22 @@ PHYE_SPINUP_HOLD -- SATA is present, COMWAKE not sent. · 50 unmodified lines | ||
| 325 | 300 | |
| 326 | 301 | The Execute Command SCSI RPC: |
| 327 | 302 | |
| 328 | − int (*lldd_execute_task)(struct sas_task *, int num, | |
| 329 | − unsigned long gfp_flags); | |
| 303 | + int (*lldd_execute_task)(struct sas_task *, gfp_t gfp_flags); | |
| 330 | 304 | |
| 331 | −Used to queue a task to the SAS LLDD. @task is the tasks to | |
| 332 | −be executed. @num should be the number of tasks being | |
| 333 | −queued at this function call (they are linked listed via | |
| 334 | −task::list), @gfp_mask should be the gfp_mask defining the | |
| 335 | −context of the caller. | |
| 305 | +Used to queue a task to the SAS LLDD. @task is the task to be executed. | |
| 306 | +@gfp_mask is the gfp_mask defining the context of the caller. | |
| 336 | 307 | |
| 337 | 308 | This function should implement the Execute Command SCSI RPC, |
| 338 | −or if you're sending a SCSI Task as linked commands, you | |
| 339 | −should also use this function. | |
| 340 | 309 | |
| 341 | −That is, when lldd_execute_task() is called, the command(s) | |
| 310 | +That is, when lldd_execute_task() is called, the command | |
| 342 | 311 | go out on the transport *immediately*. There is *no* |
| 343 | 312 | queuing of any sort and at any level in a SAS LLDD. |
| 344 | 313 | |
| 345 | −The use of task::list is two-fold, one for linked commands, | |
| 346 | −the other discussed below. | |
| 347 | − | |
| 348 | −It is possible to queue up more than one task at a time, by | |
| 349 | −initializing the list element of struct sas_task, and | |
| 350 | −passing the number of tasks enlisted in this manner in num. | |
| 351 | − | |
| 352 | 314 | Returns: -SAS_QUEUE_FULL, -ENOMEM, nothing was queued; |
| 353 | 315 | 0, the task(s) were queued. |
| 354 | 316 | |
| 355 | −If you want to pass num > 1, then either | |
| 356 | −A) you're the only caller of this function and keep track | |
| 357 | − of what you've queued to the LLDD, or | |
| 358 | −B) you know what you're doing and have a strategy of | |
| 359 | − retrying. | |
| 360 | − | |
| 361 | −As opposed to queuing one task at a time (function call), | |
| 362 | −batch queuing of tasks, by having num > 1, greatly | |
| 363 | −simplifies LLDD code, sequencer code, and _hardware design_, | |
| 364 | −and has some performance advantages in certain situations | |
| 365 | −(DBMS). | |
| 366 | − | |
| 367 | −The LLDD advertises if it can take more than one command at | |
| 368 | −a time at lldd_execute_task(), by setting the | |
| 369 | −lldd_max_execute_num parameter (controlled by "collector" | |
| 370 | −module parameter in aic94xx SAS LLDD). | |
| 371 | − | |
| 372 | −You should leave this to the default 1, unless you know what | |
| 373 | −you're doing. | |
| 374 | − | |
| 375 | −This is a function of the LLDD, to which the SAS layer can | |
| 376 | −cater to. | |
| 377 | − | |
| 378 | −int lldd_queue_size | |
| 379 | − The host adapter's queue size. This is the maximum | |
| 380 | −number of commands the lldd can have pending to domain | |
| 381 | −devices on behalf of all upper layers submitting through | |
| 382 | −lldd_execute_task(). | |
| 383 | − | |
| 384 | −You really want to set this to something (much) larger than | |
| 385 | −1. | |
| 386 | − | |
| 387 | −This _really_ has absolutely nothing to do with queuing. | |
| 388 | −There is no queuing in SAS LLDDs. | |
| 389 | − | |
| 390 | 317 | struct sas_task { |
| 391 | 318 | dev -- the device this task is destined to |
| 392 | − list -- must be initialized (INIT_LIST_HEAD) | |
| 393 | 319 | task_proto -- _one_ of enum sas_proto |
| 394 | 320 | scatter -- pointer to scatter gather list array |
| 395 | 321 | num_scatter -- number of elements in scatter |
| @@ -149,7 +149,7 @@ scsi_add_host() ----> · 148 unmodified lines | ||
| 149 | 149 | scsi_scan_host() -------+ |
| 150 | 150 | | |
| 151 | 151 | slave_alloc() |
| 152 | − slave_configure() --> scsi_adjust_queue_depth() | |
| 152 | + slave_configure() --> scsi_change_queue_depth() | |
| 153 | 153 | | |
| 154 | 154 | slave_alloc() |
| 155 | 155 | slave_configure() |
| @@ -159,7 +159,7 @@ scsi_scan_host() -------+ · 3 unmodified lines | ||
| 159 | 159 | ------------------------------------------------------------ |
| 160 | 160 | |
| 161 | 161 | If the LLD wants to adjust the default queue settings, it can invoke |
| 162 | −scsi_adjust_queue_depth() in its slave_configure() routine. | |
| 162 | +scsi_change_queue_depth() in its slave_configure() routine. | |
| 163 | 163 | |
| 164 | 164 | *** For scsi devices that the mid level tries to scan but do not |
| 165 | 165 | respond, a slave_alloc(), slave_destroy() pair is called. |
| @@ -203,7 +203,7 @@ LLD mid level LLD · 37 unmodified lines | ||
| 203 | 203 | scsi_add_device() ------+ |
| 204 | 204 | | |
| 205 | 205 | slave_alloc() |
| 206 | − slave_configure() [--> scsi_adjust_queue_depth()] | |
| 206 | + slave_configure() [--> scsi_change_queue_depth()] | |
| 207 | 207 | ------------------------------------------------------------ |
| 208 | 208 | |
| 209 | 209 | In a similar fashion, an LLD may become aware that a SCSI device has been |
| @@ -261,7 +261,7 @@ init_this_scsi_driver() ----+ · 51 unmodified lines | ||
| 261 | 261 | | scsi_register() |
| 262 | 262 | | |
| 263 | 263 | slave_alloc() |
| 264 | − slave_configure() --> scsi_adjust_queue_depth() | |
| 264 | + slave_configure() --> scsi_change_queue_depth() | |
| 265 | 265 | slave_alloc() *** |
| 266 | 266 | slave_destroy() *** |
| 267 | 267 | | |
| @@ -271,9 +271,9 @@ init_this_scsi_driver() ----+ · 3 unmodified lines | ||
| 271 | 271 | slave_destroy() *** |
| 272 | 272 | ------------------------------------------------------------ |
| 273 | 273 | |
| 274 | −The mid level invokes scsi_adjust_queue_depth() with tagged queuing off and | |
| 275 | −"cmd_per_lun" for that host as the queue length. These settings can be | |
| 276 | −overridden by a slave_configure() supplied by the LLD. | |
| 274 | +The mid level invokes scsi_change_queue_depth() with "cmd_per_lun" for that | |
| 275 | +host as the queue length. These settings can be overridden by a | |
| 276 | +slave_configure() supplied by the LLD. | |
| 277 | 277 | |
| 278 | 278 | *** For scsi devices that the mid level tries to scan but do not |
| 279 | 279 | respond, a slave_alloc(), slave_destroy() pair is called. |
| @@ -366,13 +366,11 @@ is initialized. The functions below are listed alphabetically and their · 86 unmodified lines | ||
| 366 | 366 | names all start with "scsi_". |
| 367 | 367 | |
| 368 | 368 | Summary: |
| 369 | − scsi_activate_tcq - turn on tag command queueing | |
| 370 | 369 | scsi_add_device - creates new scsi device (lu) instance |
| 371 | 370 | scsi_add_host - perform sysfs registration and set up transport class |
| 372 | − scsi_adjust_queue_depth - change the queue depth on a SCSI device | |
| 371 | + scsi_change_queue_depth - change the queue depth on a SCSI device | |
| 373 | 372 | scsi_bios_ptable - return copy of block device's partition table |
| 374 | 373 | scsi_block_requests - prevent further commands being queued to given host |
| 375 | − scsi_deactivate_tcq - turn off tag command queueing | |
| 376 | 374 | scsi_host_alloc - return a new scsi_host instance whose refcount==1 |
| 377 | 375 | scsi_host_get - increments Scsi_Host instance's refcount |
| 378 | 376 | scsi_host_put - decrements Scsi_Host instance's refcount (free if 0) |
| @@ -389,24 +387,6 @@ Summary: · 10 unmodified lines | ||
| 389 | 387 | |
| 390 | 388 | Details: |
| 391 | 389 | |
| 392 | −/** | |
| 393 | − * scsi_activate_tcq - turn on tag command queueing ("ordered" task attribute) | |
| 394 | − * @sdev: device to turn on TCQ for | |
| 395 | − * @depth: queue depth | |
| 396 | − * | |
| 397 | − * Returns nothing | |
| 398 | − * | |
| 399 | − * Might block: no | |
| 400 | − * | |
| 401 | − * Notes: Eventually, it is hoped depth would be the maximum depth | |
| 402 | − * the device could cope with and the real queue depth | |
| 403 | − * would be adjustable from 0 to depth. | |
| 404 | − * | |
| 405 | − * Defined (inline) in: include/scsi/scsi_tcq.h | |
| 406 | − **/ | |
| 407 | −void scsi_activate_tcq(struct scsi_device *sdev, int depth) | |
| 408 | − | |
| 409 | − | |
| 410 | 390 | /** |
| 411 | 391 | * scsi_add_device - creates new scsi device (lu) instance |
| 412 | 392 | * @shost: pointer to scsi host instance |
| @@ -456,11 +436,8 @@ int scsi_add_host(struct Scsi_Host *shost, struct device * dev) · 43 unmodified lines | ||
| 456 | 436 | |
| 457 | 437 | |
| 458 | 438 | /** |
| 459 | − * scsi_adjust_queue_depth - allow LLD to change queue depth on a SCSI device | |
| 439 | + * scsi_change_queue_depth - allow LLD to change queue depth on a SCSI device | |
| 460 | 440 | * @sdev: pointer to SCSI device to change queue depth on |
| 461 | − * @tagged: 0 - no tagged queuing | |
| 462 | − * MSG_SIMPLE_TAG - simple tagged queuing | |
| 463 | − * MSG_ORDERED_TAG - ordered tagged queuing | |
| 464 | 441 | * @tags Number of tags allowed if tagged queuing enabled, |
| 465 | 442 | * or number of commands the LLD can queue up |
| 466 | 443 | * in non-tagged mode (as per cmd_per_lun). |
| @@ -471,15 +448,12 @@ int scsi_add_host(struct Scsi_Host *shost, struct device * dev) · 4 unmodified lines | ||
| 471 | 448 | * |
| 472 | 449 | * Notes: Can be invoked any time on a SCSI device controlled by this |
| 473 | 450 | * LLD. [Specifically during and after slave_configure() and prior to |
| 474 | − * slave_destroy().] Can safely be invoked from interrupt code. Actual | |
| 475 | − * queue depth change may be delayed until the next command is being | |
| 476 | − * processed. See also scsi_activate_tcq() and scsi_deactivate_tcq(). | |
| 451 | + * slave_destroy().] Can safely be invoked from interrupt code. | |
| 477 | 452 | * |
| 478 | 453 | * Defined in: drivers/scsi/scsi.c [see source code for more notes] |
| 479 | 454 | * |
| 480 | 455 | **/ |
| 481 | −void scsi_adjust_queue_depth(struct scsi_device * sdev, int tagged, | |
| 482 | − int tags) | |
| 456 | +int scsi_change_queue_depth(struct scsi_device *sdev, int tags) | |
| 483 | 457 | |
| 484 | 458 | |
| 485 | 459 | /** |
| @@ -514,20 +488,6 @@ unsigned char *scsi_bios_ptable(struct block_device *dev) · 28 unmodified lines | ||
| 514 | 488 | void scsi_block_requests(struct Scsi_Host * shost) |
| 515 | 489 | |
| 516 | 490 | |
| 517 | −/** | |
| 518 | − * scsi_deactivate_tcq - turn off tag command queueing | |
| 519 | − * @sdev: device to turn off TCQ for | |
| 520 | − * @depth: queue depth (stored in sdev) | |
| 521 | − * | |
| 522 | − * Returns nothing | |
| 523 | − * | |
| 524 | − * Might block: no | |
| 525 | − * | |
| 526 | − * Defined (inline) in: include/scsi/scsi_tcq.h | |
| 527 | − **/ | |
| 528 | −void scsi_deactivate_tcq(struct scsi_device *sdev, int depth) | |
| 529 | − | |
| 530 | − | |
| 531 | 491 | /** |
| 532 | 492 | * scsi_host_alloc - create a scsi host adapter instance and perform basic |
| 533 | 493 | * initialization. |
| @@ -1254,7 +1214,7 @@ of interest: · 720 unmodified lines | ||
| 1254 | 1214 | for disk firmware uploads. |
| 1255 | 1215 | cmd_per_lun - maximum number of commands that can be queued on devices |
| 1256 | 1216 | controlled by the host. Overridden by LLD calls to |
| 1257 | − scsi_adjust_queue_depth(). | |
| 1217 | + scsi_change_queue_depth(). | |
| 1258 | 1218 | unchecked_isa_dma - 1=>only use bottom 16 MB of ram (ISA DMA addressing |
| 1259 | 1219 | restriction), 0=>can use full 32 bit (or better) DMA |
| 1260 | 1220 | address space |
| @@ -1294,7 +1254,7 @@ struct scsi_cmnd · 33 unmodified lines | ||
| 1294 | 1254 | Instances of this structure convey SCSI commands to the LLD and responses |
| 1295 | 1255 | back to the mid level. The SCSI mid level will ensure that no more SCSI |
| 1296 | 1256 | commands become queued against the LLD than are indicated by |
| 1297 | −scsi_adjust_queue_depth() (or struct Scsi_Host::cmd_per_lun). There will | |
| 1257 | +scsi_change_queue_depth() (or struct Scsi_Host::cmd_per_lun). There will | |
| 1298 | 1258 | be at least one instance of struct scsi_cmnd available for each SCSI device. |
| 1299 | 1259 | Members of interest: |
| 1300 | 1260 | cmnd - array containing SCSI command |
| @@ -506,9 +506,11 @@ user does not request data that far.) · 505 unmodified lines | ||
| 506 | 506 | |
| 507 | 507 | DEBUGGING HINTS |
| 508 | 508 | |
| 509 | −To enable debugging messages, edit st.c and #define DEBUG 1. As seen | |
| 510 | −above, debugging can be switched off with an ioctl if debugging is | |
| 511 | −compiled into the driver. The debugging output is not voluminous. | |
| 509 | +Debugging code is now compiled in by default but debugging is turned off | |
| 510 | +with the kernel module parameter debug_flag defaulting to 0. Debugging | |
| 511 | +can still be switched on and off with an ioctl. To enable debug at | |
| 512 | +module load time add debug_flag=1 to the module load options, the | |
| 513 | +debugging output is not voluminous. | |
| 512 | 514 | |
| 513 | 515 | If the tape seems to hang, I would be very interested to hear where |
| 514 | 516 | the driver is waiting. With the command 'ps -l' you can see the state |
| @@ -0,0 +1,21 @@ | ||
| 1 | +Driver for Western Digital WD7193, WD7197 and WD7296 SCSI cards | |
| 2 | +--------------------------------------------------------------- | |
| 3 | + | |
| 4 | +The card requires firmware that can be cut out of the Windows NT driver that | |
| 5 | +can be downloaded from WD at: | |
| 6 | +http://support.wdc.com/product/download.asp?groupid=801&sid=27&lang=en | |
| 7 | + | |
| 8 | +There is no license anywhere in the file or on the page - so the firmware | |
| 9 | +probably cannot be added to linux-firmware. | |
| 10 | + | |
| 11 | +This script downloads and extracts the firmware, creating wd719x-risc.bin and | |
| 12 | +d719x-wcs.bin files. Put them in /lib/firmware/. | |
| 13 | + | |
| 14 | +#!/bin/sh | |
| 15 | +wget http://support.wdc.com/download/archive/pciscsi.exe | |
| 16 | +lha xi pciscsi.exe pci-scsi.exe | |
| 17 | +lha xi pci-scsi.exe nt/wd7296a.sys | |
| 18 | +rm pci-scsi.exe | |
| 19 | +dd if=wd7296a.sys of=wd719x-risc.bin bs=1 skip=5760 count=14336 | |
| 20 | +dd if=wd7296a.sys of=wd719x-wcs.bin bs=1 skip=20096 count=514 | |
| 21 | +rm wd7296a.sys | |
| @@ -861,6 +861,7 @@ W: http://maxim.org.za/at91_26.html · 860 unmodified lines | ||
| 861 | 861 | W: http://www.linux4sam.org |
| 862 | 862 | S: Supported |
| 863 | 863 | F: arch/arm/mach-at91/ |
| 864 | +F: include/soc/at91/ | |
| 864 | 865 | F: arch/arm/boot/dts/at91*.dts |
| 865 | 866 | F: arch/arm/boot/dts/at91*.dtsi |
| 866 | 867 | F: arch/arm/boot/dts/sama*.dts |
| @@ -1308,30 +1309,22 @@ F: drivers/*/*rockchip* · 441 unmodified lines | ||
| 1308 | 1309 | F: drivers/*/*/*rockchip* |
| 1309 | 1310 | F: sound/soc/rockchip/ |
| 1310 | 1311 | |
| 1311 | −ARM/SAMSUNG ARM ARCHITECTURES | |
| 1312 | −M: Ben Dooks <ben-linux@fluff.org> | |
| 1313 | −M: Kukjin Kim <kgene.kim@samsung.com> | |
| 1312 | +ARM/SAMSUNG EXYNOS ARM ARCHITECTURES | |
| 1313 | +M: Kukjin Kim <kgene@kernel.org> | |
| 1314 | 1314 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 1315 | 1315 | L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) |
| 1316 | −W: http://www.fluff.org/ben/linux/ | |
| 1317 | 1316 | S: Maintained |
| 1318 | 1317 | F: arch/arm/boot/dts/s3c* |
| 1319 | 1318 | F: arch/arm/boot/dts/exynos* |
| 1320 | 1319 | F: arch/arm/plat-samsung/ |
| 1321 | 1320 | F: arch/arm/mach-s3c24*/ |
| 1322 | 1321 | F: arch/arm/mach-s3c64xx/ |
| 1322 | +F: arch/arm/mach-s5p*/ | |
| 1323 | +F: arch/arm/mach-exynos*/ | |
| 1323 | 1324 | F: drivers/*/*s3c2410* |
| 1324 | 1325 | F: drivers/*/*/*s3c2410* |
| 1325 | 1326 | F: drivers/spi/spi-s3c* |
| 1326 | 1327 | F: sound/soc/samsung/* |
| 1327 | − | |
| 1328 | −ARM/S5P EXYNOS ARM ARCHITECTURES | |
| 1329 | −M: Kukjin Kim <kgene.kim@samsung.com> | |
| 1330 | −L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |
| 1331 | −L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) | |
| 1332 | −S: Maintained | |
| 1333 | −F: arch/arm/mach-s5p*/ | |
| 1334 | −F: arch/arm/mach-exynos*/ | |
| 1335 | 1328 | N: exynos |
| 1336 | 1329 | |
| 1337 | 1330 | ARM/SAMSUNG MOBILE MACHINE SUPPORT |
| @@ -1381,12 +1374,12 @@ F: arch/arm/boot/dts/sh* · 43 unmodified lines | ||
| 1381 | 1374 | F: arch/arm/configs/ape6evm_defconfig |
| 1382 | 1375 | F: arch/arm/configs/armadillo800eva_defconfig |
| 1383 | 1376 | F: arch/arm/configs/bockw_defconfig |
| 1384 | −F: arch/arm/configs/koelsch_defconfig | |
| 1385 | 1377 | F: arch/arm/configs/kzm9g_defconfig |
| 1386 | 1378 | F: arch/arm/configs/lager_defconfig |
| 1387 | 1379 | F: arch/arm/configs/mackerel_defconfig |
| 1388 | 1380 | F: arch/arm/configs/marzen_defconfig |
| 1389 | 1381 | F: arch/arm/configs/shmobile_defconfig |
| 1382 | +F: arch/arm/include/debug/renesas-scif.S | |
| 1390 | 1383 | F: arch/arm/mach-shmobile/ |
| 1391 | 1384 | F: drivers/sh/ |
| 1392 | 1385 | |
| @@ -1430,6 +1423,7 @@ F: drivers/tty/serial/st-asc.c · 37 unmodified lines | ||
| 1430 | 1423 | F: drivers/usb/dwc3/dwc3-st.c |
| 1431 | 1424 | F: drivers/usb/host/ehci-st.c |
| 1432 | 1425 | F: drivers/usb/host/ohci-st.c |
| 1426 | +F: drivers/ata/ahci_st.c | |
| 1433 | 1427 | |
| 1434 | 1428 | ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT |
| 1435 | 1429 | M: Lennert Buytenhek <kernel@wantstofly.org> |
| @@ -1503,6 +1497,19 @@ S: Maintained · 67 unmodified lines | ||
| 1503 | 1497 | F: drivers/clk/ux500/ |
| 1504 | 1498 | F: include/linux/platform_data/clk-ux500.h |
| 1505 | 1499 | |
| 1500 | +ARM/VERSATILE EXPRESS PLATFORM | |
| 1501 | +M: Liviu Dudau <liviu.dudau@arm.com> | |
| 1502 | +M: Sudeep Holla <sudeep.holla@arm.com> | |
| 1503 | +M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | |
| 1504 | +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |
| 1505 | +S: Maintained | |
| 1506 | +F: arch/arm/boot/dts/vexpress* | |
| 1507 | +F: arch/arm/mach-vexpress/ | |
| 1508 | +F: */*/vexpress* | |
| 1509 | +F: */*/*/vexpress* | |
| 1510 | +F: drivers/clk/versatile/clk-vexpress-osc.c | |
| 1511 | +F: drivers/clocksource/versatile.c | |
| 1512 | + | |
| 1506 | 1513 | ARM/VFP SUPPORT |
| 1507 | 1514 | M: Russell King <linux@arm.linux.org.uk> |
| 1508 | 1515 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| @@ -1828,7 +1835,7 @@ F: include/net/ax25.h · 319 unmodified lines | ||
| 1828 | 1835 | F: net/ax25/ |
| 1829 | 1836 | |
| 1830 | 1837 | AZ6007 DVB DRIVER |
| 1831 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 1838 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 1832 | 1839 | L: linux-media@vger.kernel.org |
| 1833 | 1840 | W: http://linuxtv.org |
| 1834 | 1841 | T: git git://linuxtv.org/media_tree.git |
| @@ -2097,10 +2104,13 @@ F: arch/arm/include/debug/bcm63xx.S · 262 unmodified lines | ||
| 2097 | 2104 | BROADCOM BCM7XXX ARM ARCHITECTURE |
| 2098 | 2105 | M: Marc Carino <marc.ceeeee@gmail.com> |
| 2099 | 2106 | M: Brian Norris <computersforpeace@gmail.com> |
| 2107 | +M: Gregory Fong <gregory.0xf0@gmail.com> | |
| 2108 | +M: Florian Fainelli <f.fainelli@gmail.com> | |
| 2100 | 2109 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 2101 | 2110 | S: Maintained |
| 2102 | 2111 | F: arch/arm/mach-bcm/*brcmstb* |
| 2103 | 2112 | F: arch/arm/boot/dts/bcm7*.dts* |
| 2113 | +F: drivers/bus/brcmstb_gisb.c | |
| 2104 | 2114 | |
| 2105 | 2115 | BROADCOM TG3 GIGABIT ETHERNET DRIVER |
| 2106 | 2116 | M: Prashant Sreedharan <prashant@broadcom.com> |
| @@ -2131,6 +2141,20 @@ L: linux-scsi@vger.kernel.org · 24 unmodified lines | ||
| 2131 | 2141 | S: Supported |
| 2132 | 2142 | F: drivers/scsi/bnx2i/ |
| 2133 | 2143 | |
| 2144 | +BROADCOM CYGNUS/IPROC ARM ARCHITECTURE | |
| 2145 | +M: Ray Jui <rjui@broadcom.com> | |
| 2146 | +M: Scott Branden <sbranden@broadcom.com> | |
| 2147 | +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |
| 2148 | +L: bcm-kernel-feedback-list@broadcom.com | |
| 2149 | +T: git git://git.github.com/brcm/linux.git | |
| 2150 | +S: Maintained | |
| 2151 | +N: iproc | |
| 2152 | +N: cygnus | |
| 2153 | +N: bcm9113* | |
| 2154 | +N: bcm9583* | |
| 2155 | +N: bcm583* | |
| 2156 | +N: bcm113* | |
| 2157 | + | |
| 2134 | 2158 | BROADCOM KONA GPIO DRIVER |
| 2135 | 2159 | M: Ray Jui <rjui@broadcom.com> |
| 2136 | 2160 | L: bcm-kernel-feedback-list@broadcom.com |
| @@ -2198,7 +2222,7 @@ F: Documentation/filesystems/btrfs.txt · 61 unmodified lines | ||
| 2198 | 2222 | F: fs/btrfs/ |
| 2199 | 2223 | |
| 2200 | 2224 | BTTV VIDEO4LINUX DRIVER |
| 2201 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 2225 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 2202 | 2226 | L: linux-media@vger.kernel.org |
| 2203 | 2227 | W: http://linuxtv.org |
| 2204 | 2228 | T: git git://linuxtv.org/media_tree.git |
| @@ -2719,7 +2743,7 @@ F: drivers/media/common/cx2341x* · 514 unmodified lines | ||
| 2719 | 2743 | F: include/media/cx2341x* |
| 2720 | 2744 | |
| 2721 | 2745 | CX88 VIDEO4LINUX DRIVER |
| 2722 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 2746 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 2723 | 2747 | L: linux-media@vger.kernel.org |
| 2724 | 2748 | W: http://linuxtv.org |
| 2725 | 2749 | T: git git://linuxtv.org/media_tree.git |
| @@ -2862,11 +2886,10 @@ F: Documentation/networking/dmfe.txt · 136 unmodified lines | ||
| 2862 | 2886 | F: drivers/net/ethernet/dec/tulip/dmfe.c |
| 2863 | 2887 | |
| 2864 | 2888 | DC390/AM53C974 SCSI driver |
| 2865 | −M: Kurt Garloff <garloff@suse.de> | |
| 2866 | −W: http://www.garloff.de/kurt/linux/dc390/ | |
| 2867 | −M: Guennadi Liakhovetski <g.liakhovetski@gmx.de> | |
| 2889 | +M: Hannes Reinecke <hare@suse.de> | |
| 2890 | +L: linux-scsi@vger.kernel.org | |
| 2868 | 2891 | S: Maintained |
| 2869 | −F: drivers/scsi/tmscsim.* | |
| 2892 | +F: drivers/scsi/am53c974.c | |
| 2870 | 2893 | |
| 2871 | 2894 | DC395x SCSI driver |
| 2872 | 2895 | M: Oliver Neukum <oliver@neukum.org> |
| @@ -3402,7 +3425,7 @@ F: fs/ecryptfs/ · 529 unmodified lines | ||
| 3402 | 3425 | EDAC-CORE |
| 3403 | 3426 | M: Doug Thompson <dougthompson@xmission.com> |
| 3404 | 3427 | M: Borislav Petkov <bp@alien8.de> |
| 3405 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 3428 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 3406 | 3429 | L: linux-edac@vger.kernel.org |
| 3407 | 3430 | W: bluesmoke.sourceforge.net |
| 3408 | 3431 | S: Supported |
| @@ -3451,7 +3474,7 @@ S: Maintained · 42 unmodified lines | ||
| 3451 | 3474 | F: drivers/edac/e7xxx_edac.c |
| 3452 | 3475 | |
| 3453 | 3476 | EDAC-GHES |
| 3454 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 3477 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 3455 | 3478 | L: linux-edac@vger.kernel.org |
| 3456 | 3479 | W: bluesmoke.sourceforge.net |
| 3457 | 3480 | S: Maintained |
| @@ -3479,21 +3502,21 @@ S: Maintained · 21 unmodified lines | ||
| 3479 | 3502 | F: drivers/edac/i5000_edac.c |
| 3480 | 3503 | |
| 3481 | 3504 | EDAC-I5400 |
| 3482 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 3505 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 3483 | 3506 | L: linux-edac@vger.kernel.org |
| 3484 | 3507 | W: bluesmoke.sourceforge.net |
| 3485 | 3508 | S: Maintained |
| 3486 | 3509 | F: drivers/edac/i5400_edac.c |
| 3487 | 3510 | |
| 3488 | 3511 | EDAC-I7300 |
| 3489 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 3512 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 3490 | 3513 | L: linux-edac@vger.kernel.org |
| 3491 | 3514 | W: bluesmoke.sourceforge.net |
| 3492 | 3515 | S: Maintained |
| 3493 | 3516 | F: drivers/edac/i7300_edac.c |
| 3494 | 3517 | |
| 3495 | 3518 | EDAC-I7CORE |
| 3496 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 3519 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 3497 | 3520 | L: linux-edac@vger.kernel.org |
| 3498 | 3521 | W: bluesmoke.sourceforge.net |
| 3499 | 3522 | S: Maintained |
| @@ -3536,7 +3559,7 @@ S: Maintained · 36 unmodified lines | ||
| 3536 | 3559 | F: drivers/edac/r82600_edac.c |
| 3537 | 3560 | |
| 3538 | 3561 | EDAC-SBRIDGE |
| 3539 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 3562 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 3540 | 3563 | L: linux-edac@vger.kernel.org |
| 3541 | 3564 | W: bluesmoke.sourceforge.net |
| 3542 | 3565 | S: Maintained |
| @@ -3596,7 +3619,7 @@ S: Maintained · 53 unmodified lines | ||
| 3596 | 3619 | F: drivers/net/ethernet/ibm/ehea/ |
| 3597 | 3620 | |
| 3598 | 3621 | EM28XX VIDEO4LINUX DRIVER |
| 3599 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 3622 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 3600 | 3623 | L: linux-media@vger.kernel.org |
| 3601 | 3624 | W: http://linuxtv.org |
| 3602 | 3625 | T: git git://linuxtv.org/media_tree.git |
| @@ -5962,7 +5985,7 @@ S: Maintained · 2359 unmodified lines | ||
| 5962 | 5985 | F: drivers/media/radio/radio-maxiradio* |
| 5963 | 5986 | |
| 5964 | 5987 | MEDIA INPUT INFRASTRUCTURE (V4L/DVB) |
| 5965 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 5988 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 5966 | 5989 | P: LinuxTV.org Project |
| 5967 | 5990 | L: linux-media@vger.kernel.org |
| 5968 | 5991 | W: http://linuxtv.org |
| @@ -5991,10 +6014,13 @@ W: http://linuxtv.org · 22 unmodified lines | ||
| 5991 | 6014 | S: Odd Fixes |
| 5992 | 6015 | F: drivers/media/parport/pms* |
| 5993 | 6016 | |
| 5994 | −MEGARAID SCSI DRIVERS | |
| 5995 | −M: Neela Syam Kolli <megaraidlinux@lsi.com> | |
| 6017 | +MEGARAID SCSI/SAS DRIVERS | |
| 6018 | +M: Kashyap Desai <kashyap.desai@avagotech.com> | |
| 6019 | +M: Sumit Saxena <sumit.saxena@avagotech.com> | |
| 6020 | +M: Uday Lingala <uday.lingala@avagotech.com> | |
| 6021 | +L: megaraidlinux.pdl@avagotech.com | |
| 5996 | 6022 | L: linux-scsi@vger.kernel.org |
| 5997 | −W: http://megaraid.lsilogic.com | |
| 6023 | +W: http://www.lsi.com | |
| 5998 | 6024 | S: Maintained |
| 5999 | 6025 | F: Documentation/scsi/megaraid.txt |
| 6000 | 6026 | F: drivers/scsi/megaraid.* |
| @@ -6305,7 +6331,6 @@ F: drivers/scsi/g_NCR5380.* · 304 unmodified lines | ||
| 6305 | 6331 | F: drivers/scsi/g_NCR5380_mmio.c |
| 6306 | 6332 | F: drivers/scsi/mac_scsi.* |
| 6307 | 6333 | F: drivers/scsi/pas16.* |
| 6308 | −F: drivers/scsi/sun3_NCR5380.c | |
| 6309 | 6334 | F: drivers/scsi/sun3_scsi.* |
| 6310 | 6335 | F: drivers/scsi/sun3_scsi_vme.c |
| 6311 | 6336 | F: drivers/scsi/t128.* |
| @@ -6561,6 +6586,13 @@ S: Maintained · 249 unmodified lines | ||
| 6561 | 6586 | F: Documentation/scsi/NinjaSCSI.txt |
| 6562 | 6587 | F: drivers/scsi/nsp32* |
| 6563 | 6588 | |
| 6589 | +NIOS2 ARCHITECTURE | |
| 6590 | +M: Ley Foon Tan <lftan@altera.com> | |
| 6591 | +L: nios2-dev@lists.rocketboards.org (moderated for non-subscribers) | |
| 6592 | +T: git git://git.rocketboards.org/linux-socfpga.git | |
| 6593 | +S: Maintained | |
| 6594 | +F: arch/nios2/ | |
| 6595 | + | |
| 6564 | 6596 | NTB DRIVER |
| 6565 | 6597 | M: Jon Mason <jdmason@kudzu.us> |
| 6566 | 6598 | M: Dave Jiang <dave.jiang@intel.com> |
| @@ -6670,6 +6702,14 @@ L: linux-omap@vger.kernel.org · 103 unmodified lines | ||
| 6670 | 6702 | S: Maintained |
| 6671 | 6703 | F: sound/soc/omap/ |
| 6672 | 6704 | |
| 6705 | +OMAP GENERAL PURPOSE MEMORY CONTROLLER SUPPORT | |
| 6706 | +M: Roger Quadros <rogerq@ti.com> | |
| 6707 | +M: Tony Lindgren <tony@atomide.com> | |
| 6708 | +L: linux-omap@vger.kernel.org | |
| 6709 | +S: Maintained | |
| 6710 | +F: drivers/memory/omap-gpmc.c | |
| 6711 | +F: arch/arm/mach-omap2/*gpmc* | |
| 6712 | + | |
| 6673 | 6713 | OMAP FRAMEBUFFER SUPPORT |
| 6674 | 6714 | M: Tomi Valkeinen <tomi.valkeinen@ti.com> |
| 6675 | 6715 | L: linux-fbdev@vger.kernel.org |
| @@ -8013,7 +8053,7 @@ S: Odd Fixes · 1337 unmodified lines | ||
| 8013 | 8053 | F: drivers/media/i2c/saa6588* |
| 8014 | 8054 | |
| 8015 | 8055 | SAA7134 VIDEO4LINUX DRIVER |
| 8016 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 8056 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 8017 | 8057 | L: linux-media@vger.kernel.org |
| 8018 | 8058 | W: http://linuxtv.org |
| 8019 | 8059 | T: git git://linuxtv.org/media_tree.git |
| @@ -8471,7 +8511,7 @@ S: Maintained · 451 unmodified lines | ||
| 8471 | 8511 | F: drivers/media/radio/si4713/radio-usb-si4713.c |
| 8472 | 8512 | |
| 8473 | 8513 | SIANO DVB DRIVER |
| 8474 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 8514 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 8475 | 8515 | L: linux-media@vger.kernel.org |
| 8476 | 8516 | W: http://linuxtv.org |
| 8477 | 8517 | T: git git://linuxtv.org/media_tree.git |
| @@ -8682,7 +8722,9 @@ S: Maintained · 204 unmodified lines | ||
| 8682 | 8722 | F: drivers/leds/leds-net48xx.c |
| 8683 | 8723 | |
| 8684 | 8724 | SOFTLOGIC 6x10 MPEG CODEC |
| 8685 | −M: Ismael Luceno <ismael.luceno@corp.bluecherry.net> | |
| 8725 | +M: Bluecherry Maintainers <maintainers@bluecherrydvr.com> | |
| 8726 | +M: Andrey Utkin <andrey.utkin@corp.bluecherry.net> | |
| 8727 | +M: Andrey Utkin <andrey.krieger.utkin@gmail.com> | |
| 8686 | 8728 | L: linux-media@vger.kernel.org |
| 8687 | 8729 | S: Supported |
| 8688 | 8730 | F: drivers/media/pci/solo6x10/ |
| @@ -9156,7 +9198,7 @@ S: Maintained · 467 unmodified lines | ||
| 9156 | 9198 | F: drivers/media/i2c/tda9840* |
| 9157 | 9199 | |
| 9158 | 9200 | TEA5761 TUNER DRIVER |
| 9159 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 9201 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 9160 | 9202 | L: linux-media@vger.kernel.org |
| 9161 | 9203 | W: http://linuxtv.org |
| 9162 | 9204 | T: git git://linuxtv.org/media_tree.git |
| @@ -9164,7 +9206,7 @@ S: Odd fixes · 1 unmodified line | ||
| 9164 | 9206 | F: drivers/media/tuners/tea5761.* |
| 9165 | 9207 | |
| 9166 | 9208 | TEA5767 TUNER DRIVER |
| 9167 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 9209 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 9168 | 9210 | L: linux-media@vger.kernel.org |
| 9169 | 9211 | W: http://linuxtv.org |
| 9170 | 9212 | T: git git://linuxtv.org/media_tree.git |
| @@ -9476,7 +9518,7 @@ F: include/linux/shmem_fs.h · 305 unmodified lines | ||
| 9476 | 9518 | F: mm/shmem.c |
| 9477 | 9519 | |
| 9478 | 9520 | TM6000 VIDEO4LINUX DRIVER |
| 9479 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 9521 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 9480 | 9522 | L: linux-media@vger.kernel.org |
| 9481 | 9523 | W: http://linuxtv.org |
| 9482 | 9524 | T: git git://linuxtv.org/media_tree.git |
| @@ -10297,7 +10339,7 @@ S: Maintained · 814 unmodified lines | ||
| 10297 | 10339 | F: arch/x86/kernel/cpu/mcheck/* |
| 10298 | 10340 | |
| 10299 | 10341 | XC2028/3028 TUNER DRIVER |
| 10300 | −M: Mauro Carvalho Chehab <m.chehab@samsung.com> | |
| 10342 | +M: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 10301 | 10343 | L: linux-media@vger.kernel.org |
| 10302 | 10344 | W: http://linuxtv.org |
| 10303 | 10345 | T: git git://linuxtv.org/media_tree.git |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | VERSION = 3 |
| 2 | 2 | PATCHLEVEL = 18 |
| 3 | 3 | SUBLEVEL = 0 |
| 4 | −EXTRAVERSION = -rc6 | |
| 4 | +EXTRAVERSION = | |
| 5 | 5 | NAME = Diseased Newt |
| 6 | 6 | |
| 7 | 7 | # *DOCUMENTATION* |
| @@ -13,8 +13,6 @@ · 12 unmodified lines | ||
| 13 | 13 | #include <asm/byteorder.h> |
| 14 | 14 | #include <asm/page.h> |
| 15 | 15 | |
| 16 | −#define PCI_IOBASE ((void __iomem *)0) | |
| 17 | − | |
| 18 | 16 | extern void __iomem *ioremap(unsigned long physaddr, unsigned long size); |
| 19 | 17 | extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, |
| 20 | 18 | unsigned long flags); |
| @@ -320,24 +320,6 @@ config ARCH_MULTIPLATFORM · 319 unmodified lines | ||
| 320 | 320 | select SPARSE_IRQ |
| 321 | 321 | select USE_OF |
| 322 | 322 | |
| 323 | −config ARCH_INTEGRATOR | |
| 324 | − bool "ARM Ltd. Integrator family" | |
| 325 | − select ARM_AMBA | |
| 326 | − select ARM_PATCH_PHYS_VIRT if MMU | |
| 327 | − select AUTO_ZRELADDR | |
| 328 | − select COMMON_CLK | |
| 329 | − select COMMON_CLK_VERSATILE | |
| 330 | − select GENERIC_CLOCKEVENTS | |
| 331 | − select HAVE_TCM | |
| 332 | − select ICST | |
| 333 | − select MULTI_IRQ_HANDLER | |
| 334 | − select PLAT_VERSATILE | |
| 335 | − select SPARSE_IRQ | |
| 336 | − select USE_OF | |
| 337 | − select VERSATILE_FPGA_IRQ | |
| 338 | − help | |
| 339 | − Support for ARM's Integrator platform. | |
| 340 | − | |
| 341 | 323 | config ARCH_REALVIEW |
| 342 | 324 | bool "ARM Ltd. RealView family" |
| 343 | 325 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| @@ -350,6 +332,7 @@ config ARCH_REALVIEW · 6 unmodified lines | ||
| 350 | 332 | select ICST |
| 351 | 333 | select NEED_MACH_MEMORY_H |
| 352 | 334 | select PLAT_VERSATILE |
| 335 | + select PLAT_VERSATILE_SCHED_CLOCK | |
| 353 | 336 | help |
| 354 | 337 | This enables support for ARM Ltd RealView boards. |
| 355 | 338 | |
| @@ -365,6 +348,7 @@ config ARCH_VERSATILE · 9 unmodified lines | ||
| 365 | 348 | select ICST |
| 366 | 349 | select PLAT_VERSATILE |
| 367 | 350 | select PLAT_VERSATILE_CLOCK |
| 351 | + select PLAT_VERSATILE_SCHED_CLOCK | |
| 368 | 352 | select VERSATILE_FPGA_IRQ |
| 369 | 353 | help |
| 370 | 354 | This enables support for ARM Ltd Versatile board. |
| @@ -376,10 +360,11 @@ config ARCH_AT91 · 5 unmodified lines | ||
| 376 | 360 | select IRQ_DOMAIN |
| 377 | 361 | select NEED_MACH_IO_H if PCCARD |
| 378 | 362 | select PINCTRL |
| 379 | − select PINCTRL_AT91 if USE_OF | |
| 363 | + select PINCTRL_AT91 | |
| 364 | + select USE_OF | |
| 380 | 365 | help |
| 381 | 366 | This enables support for systems based on Atmel |
| 382 | − AT91RM9200 and AT91SAM9* processors. | |
| 367 | + AT91RM9200, AT91SAM9 and SAMA5 processors. | |
| 383 | 368 | |
| 384 | 369 | config ARCH_CLPS711X |
| 385 | 370 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" |
| @@ -854,6 +839,8 @@ config ARCH_VIRT · 468 unmodified lines | ||
| 854 | 839 | # |
| 855 | 840 | source "arch/arm/mach-mvebu/Kconfig" |
| 856 | 841 | |
| 842 | +source "arch/arm/mach-asm9260/Kconfig" | |
| 843 | + | |
| 857 | 844 | source "arch/arm/mach-at91/Kconfig" |
| 858 | 845 | |
| 859 | 846 | source "arch/arm/mach-axxia/Kconfig" |
| @@ -1259,9 +1246,6 @@ source "arch/arm/common/Kconfig" · 399 unmodified lines | ||
| 1259 | 1246 | |
| 1260 | 1247 | menu "Bus support" |
| 1261 | 1248 | |
| 1262 | −config ARM_AMBA | |
| 1263 | − bool | |
| 1264 | − | |
| 1265 | 1249 | config ISA |
| 1266 | 1250 | bool |
| 1267 | 1251 | help |
| @@ -93,6 +93,27 @@ choice · 92 unmodified lines | ||
| 93 | 93 | prompt "Kernel low-level debugging port" |
| 94 | 94 | depends on DEBUG_LL |
| 95 | 95 | |
| 96 | + config DEBUG_ASM9260_UART | |
| 97 | + bool "Kernel low-level debugging via asm9260 UART" | |
| 98 | + depends on MACH_ASM9260 | |
| 99 | + help | |
| 100 | + Say Y here if you want the debug print routines to direct | |
| 101 | + their output to an UART or USART port on asm9260 based | |
| 102 | + machines. | |
| 103 | + | |
| 104 | + DEBUG_UART_PHYS | DEBUG_UART_VIRT | |
| 105 | + | |
| 106 | + 0x80000000 | 0xf0000000 | UART0 | |
| 107 | + 0x80004000 | 0xf0004000 | UART1 | |
| 108 | + 0x80008000 | 0xf0008000 | UART2 | |
| 109 | + 0x8000c000 | 0xf000c000 | UART3 | |
| 110 | + 0x80010000 | 0xf0010000 | UART4 | |
| 111 | + 0x80014000 | 0xf0014000 | UART5 | |
| 112 | + 0x80018000 | 0xf0018000 | UART6 | |
| 113 | + 0x8001c000 | 0xf001c000 | UART7 | |
| 114 | + 0x80020000 | 0xf0020000 | UART8 | |
| 115 | + 0x80024000 | 0xf0024000 | UART9 | |
| 116 | + | |
| 96 | 117 | config AT91_DEBUG_LL_DBGU0 |
| 97 | 118 | bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl" |
| 98 | 119 | depends on HAVE_AT91_DBGU0 |
| @@ -113,7 +134,7 @@ choice · 14 unmodified lines | ||
| 113 | 134 | config DEBUG_BCM_5301X |
| 114 | 135 | bool "Kernel low-level debugging on BCM5301X UART1" |
| 115 | 136 | depends on ARCH_BCM_5301X |
| 116 | − select DEBUG_UART_PL01X | |
| 137 | + select DEBUG_UART_8250 | |
| 117 | 138 | |
| 118 | 139 | config DEBUG_BCM_KONA_UART |
| 119 | 140 | bool "Kernel low-level debugging messages via BCM KONA UART" |
| @@ -139,6 +160,17 @@ choice · 19 unmodified lines | ||
| 139 | 160 | Say Y here if you want kernel low-level debugging support |
| 140 | 161 | on Marvell Berlin SoC based platforms. |
| 141 | 162 | |
| 163 | + config DEBUG_BRCMSTB_UART | |
| 164 | + bool "Use BRCMSTB UART for low-level debug" | |
| 165 | + depends on ARCH_BRCMSTB | |
| 166 | + select DEBUG_UART_8250 | |
| 167 | + help | |
| 168 | + Say Y here if you want the debug print routines to direct | |
| 169 | + their output to the first serial port on these devices. | |
| 170 | + | |
| 171 | + If you have a Broadcom STB chip and would like early print | |
| 172 | + messages to appear over the UART, select this option. | |
| 173 | + | |
| 142 | 174 | config DEBUG_CLPS711X_UART1 |
| 143 | 175 | bool "Kernel low-level debugging messages via UART1" |
| 144 | 176 | depends on ARCH_CLPS711X |
| @@ -653,6 +685,64 @@ choice · 508 unmodified lines | ||
| 653 | 685 | Say Y here if you want kernel low-level debugging support |
| 654 | 686 | on Rockchip RK32xx based platforms. |
| 655 | 687 | |
| 688 | + config DEBUG_R7S72100_SCIF2 | |
| 689 | + bool "Kernel low-level debugging messages via SCIF2 on R7S72100" | |
| 690 | + depends on ARCH_R7S72100 | |
| 691 | + help | |
| 692 | + Say Y here if you want kernel low-level debugging support | |
| 693 | + via SCIF2 on Renesas RZ/A1H (R7S72100). | |
| 694 | + | |
| 695 | + config DEBUG_RCAR_GEN1_SCIF0 | |
| 696 | + bool "Kernel low-level debugging messages via SCIF0 on R8A7778" | |
| 697 | + depends on ARCH_R8A7778 | |
| 698 | + help | |
| 699 | + Say Y here if you want kernel low-level debugging support | |
| 700 | + via SCIF0 on Renesas R-Car M1A (R8A7778). | |
| 701 | + | |
| 702 | + config DEBUG_RCAR_GEN1_SCIF2 | |
| 703 | + bool "Kernel low-level debugging messages via SCIF2 on R8A7779" | |
| 704 | + depends on ARCH_R8A7779 | |
| 705 | + help | |
| 706 | + Say Y here if you want kernel low-level debugging support | |
| 707 | + via SCIF2 on Renesas R-Car H1 (R8A7779). | |
| 708 | + | |
| 709 | + config DEBUG_RCAR_GEN2_SCIF0 | |
| 710 | + bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7793)" | |
| 711 | + depends on ARCH_R8A7790 || ARCH_R8A7791 || ARCH_R8A7793 | |
| 712 | + help | |
| 713 | + Say Y here if you want kernel low-level debugging support | |
| 714 | + via SCIF0 on Renesas R-Car H2 (R8A7790), M2-W (R8A7791), or | |
| 715 | + M2-N (R8A7793). | |
| 716 | + | |
| 717 | + config DEBUG_RCAR_GEN2_SCIF2 | |
| 718 | + bool "Kernel low-level debugging messages via SCIF2 on R8A7794" | |
| 719 | + depends on ARCH_R8A7794 | |
| 720 | + help | |
| 721 | + Say Y here if you want kernel low-level debugging support | |
| 722 | + via SCIF2 on Renesas R-Car E2 (R8A7794). | |
| 723 | + | |
| 724 | + config DEBUG_RMOBILE_SCIFA0 | |
| 725 | + bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4/SH7372" | |
| 726 | + depends on ARCH_R8A73A4 || ARCH_SH7372 | |
| 727 | + help | |
| 728 | + Say Y here if you want kernel low-level debugging support | |
| 729 | + via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4) or SH-Mobile | |
| 730 | + AP4 (SH7372). | |
| 731 | + | |
| 732 | + config DEBUG_RMOBILE_SCIFA1 | |
| 733 | + bool "Kernel low-level debugging messages via SCIFA1 on R8A7740" | |
| 734 | + depends on ARCH_R8A7740 | |
| 735 | + help | |
| 736 | + Say Y here if you want kernel low-level debugging support | |
| 737 | + via SCIFA1 on Renesas R-Mobile A1 (R8A7740). | |
| 738 | + | |
| 739 | + config DEBUG_RMOBILE_SCIFA4 | |
| 740 | + bool "Kernel low-level debugging messages via SCIFA4 on SH73A0" | |
| 741 | + depends on ARCH_SH73A0 | |
| 742 | + help | |
| 743 | + Say Y here if you want kernel low-level debugging support | |
| 744 | + via SCIFA4 on Renesas SH-Mobile AG5 (SH73A0). | |
| 745 | + | |
| 656 | 746 | config DEBUG_S3C_UART0 |
| 657 | 747 | depends on PLAT_SAMSUNG |
| 658 | 748 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS |
| @@ -723,6 +813,14 @@ choice · 64 unmodified lines | ||
| 723 | 813 | their output to UART 2. The port must have been initialised |
| 724 | 814 | by the boot-loader before use. |
| 725 | 815 | |
| 816 | + config DEBUG_SA1100 | |
| 817 | + depends on ARCH_SA1100 | |
| 818 | + bool "Use SA1100 UARTs for low-level debug" | |
| 819 | + help | |
| 820 | + Say Y here if you want kernel low-level debugging support | |
| 821 | + on SA-11x0 UART ports. The kernel will check for the first | |
| 822 | + enabled UART in a sequence 3-1-2. | |
| 823 | + | |
| 726 | 824 | config DEBUG_SOCFPGA_UART |
| 727 | 825 | depends on ARCH_SOCFPGA |
| 728 | 826 | bool "Use SOCFPGA UART for low-level debug" |
| @@ -731,6 +829,14 @@ choice · 2 unmodified lines | ||
| 731 | 829 | Say Y here if you want kernel low-level debugging support |
| 732 | 830 | on SOCFPGA based platforms. |
| 733 | 831 | |
| 832 | + config DEBUG_SUN9I_UART0 | |
| 833 | + bool "Kernel low-level debugging messages via sun9i UART0" | |
| 834 | + depends on MACH_SUN9I | |
| 835 | + select DEBUG_UART_8250 | |
| 836 | + help | |
| 837 | + Say Y here if you want kernel low-level debugging support | |
| 838 | + on Allwinner A80 based platforms on the UART0. | |
| 839 | + | |
| 734 | 840 | config DEBUG_SUNXI_UART0 |
| 735 | 841 | bool "Kernel low-level debugging messages via sunXi UART0" |
| 736 | 842 | depends on ARCH_SUNXI |
| @@ -866,6 +972,22 @@ choice · 129 unmodified lines | ||
| 866 | 972 | Say Y here if you want kernel low-level debugging support |
| 867 | 973 | for Mediatek mt6589 based platforms on UART0. |
| 868 | 974 | |
| 975 | + config DEBUG_MT8127_UART0 | |
| 976 | + bool "Mediatek mt8127 UART0" | |
| 977 | + depends on ARCH_MEDIATEK | |
| 978 | + select DEBUG_UART_8250 | |
| 979 | + help | |
| 980 | + Say Y here if you want kernel low-level debugging support | |
| 981 | + for Mediatek mt8127 based platforms on UART0. | |
| 982 | + | |
| 983 | + config DEBUG_MT8135_UART3 | |
| 984 | + bool "Mediatek mt8135 UART3" | |
| 985 | + depends on ARCH_MEDIATEK | |
| 986 | + select DEBUG_UART_8250 | |
| 987 | + help | |
| 988 | + Say Y here if you want kernel low-level debugging support | |
| 989 | + for Mediatek mt8135 based platforms on UART3. | |
| 990 | + | |
| 869 | 991 | config DEBUG_VEXPRESS_UART0_DETECT |
| 870 | 992 | bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" |
| 871 | 993 | depends on ARCH_VEXPRESS && CPU_CP15_MMU |
| @@ -1041,7 +1163,9 @@ config DEBUG_STI_UART · 169 unmodified lines | ||
| 1041 | 1163 | |
| 1042 | 1164 | config DEBUG_LL_INCLUDE |
| 1043 | 1165 | string |
| 1166 | + default "debug/sa1100.S" if DEBUG_SA1100 | |
| 1044 | 1167 | default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 |
| 1168 | + default "debug/asm9260.S" if DEBUG_ASM9260_UART | |
| 1045 | 1169 | default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2 |
| 1046 | 1170 | default "debug/meson.S" if DEBUG_MESON_UARTAO |
| 1047 | 1171 | default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X |
| @@ -1061,6 +1185,14 @@ config DEBUG_LL_INCLUDE · 13 unmodified lines | ||
| 1061 | 1185 | DEBUG_IMX6SX_UART |
| 1062 | 1186 | default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM |
| 1063 | 1187 | default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART |
| 1188 | + default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2 | |
| 1189 | + default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0 | |
| 1190 | + default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2 | |
| 1191 | + default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0 | |
| 1192 | + default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2 | |
| 1193 | + default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0 | |
| 1194 | + default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1 | |
| 1195 | + default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4 | |
| 1064 | 1196 | default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART |
| 1065 | 1197 | default "debug/s5pv210.S" if DEBUG_S5PV210_UART |
| 1066 | 1198 | default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 |
| @@ -1106,6 +1238,7 @@ config DEBUG_UART_PHYS · 39 unmodified lines | ||
| 1106 | 1238 | default 0x02530c00 if DEBUG_KEYSTONE_UART0 |
| 1107 | 1239 | default 0x02531000 if DEBUG_KEYSTONE_UART1 |
| 1108 | 1240 | default 0x03010fe0 if ARCH_RPC |
| 1241 | + default 0x07000000 if DEBUG_SUN9I_UART0 | |
| 1109 | 1242 | default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \ |
| 1110 | 1243 | DEBUG_VEXPRESS_UART0_CA9 |
| 1111 | 1244 | default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT |
| @@ -1113,7 +1246,9 @@ config DEBUG_UART_PHYS · 1 unmodified line | ||
| 1113 | 1246 | default 0x10126000 if DEBUG_RK3X_UART1 |
| 1114 | 1247 | default 0x101f1000 if ARCH_VERSATILE |
| 1115 | 1248 | default 0x101fb000 if DEBUG_NOMADIK_UART |
| 1249 | + default 0x11002000 if DEBUG_MT8127_UART0 | |
| 1116 | 1250 | default 0x11006000 if DEBUG_MT6589_UART0 |
| 1251 | + default 0x11009000 if DEBUG_MT8135_UART3 | |
| 1117 | 1252 | default 0x16000000 if ARCH_INTEGRATOR |
| 1118 | 1253 | default 0x18000300 if DEBUG_BCM_5301X |
| 1119 | 1254 | default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 |
| @@ -1135,6 +1270,7 @@ config DEBUG_UART_PHYS · 15 unmodified lines | ||
| 1135 | 1270 | default 0x78000000 if DEBUG_CNS3XXX |
| 1136 | 1271 | default 0x7c0003f8 if FOOTBRIDGE |
| 1137 | 1272 | default 0x78000000 if DEBUG_CNS3XXX |
| 1273 | + default 0x80010000 if DEBUG_ASM9260_UART | |
| 1138 | 1274 | default 0x80070000 if DEBUG_IMX23_UART |
| 1139 | 1275 | default 0x80074000 if DEBUG_IMX28_UART |
| 1140 | 1276 | default 0x80230000 if DEBUG_PICOXCELL_UART |
| @@ -1152,7 +1288,14 @@ config DEBUG_UART_PHYS · 11 unmodified lines | ||
| 1152 | 1288 | default 0xd4018000 if DEBUG_MMP_UART3 |
| 1153 | 1289 | default 0xe0000000 if ARCH_SPEAR13XX |
| 1154 | 1290 | default 0xe4007000 if DEBUG_HIP04_UART |
| 1291 | + default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0 | |
| 1292 | + default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1 | |
| 1293 | + default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4 | |
| 1294 | + default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2 | |
| 1295 | + default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0 | |
| 1296 | + default 0xe8008000 if DEBUG_R7S72100_SCIF2 | |
| 1155 | 1297 | default 0xf0000be0 if ARCH_EBSA110 |
| 1298 | + default 0xf040ab00 if DEBUG_BRCMSTB_UART | |
| 1156 | 1299 | default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE |
| 1157 | 1300 | default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \ |
| 1158 | 1301 | ARCH_ORION5X |
| @@ -1164,24 +1307,33 @@ config DEBUG_UART_PHYS · 5 unmodified lines | ||
| 1164 | 1307 | default 0xff690000 if DEBUG_RK32_UART2 |
| 1165 | 1308 | default 0xffc02000 if DEBUG_SOCFPGA_UART |
| 1166 | 1309 | default 0xffd82340 if ARCH_IOP13XX |
| 1310 | + default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 | |
| 1311 | + default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 | |
| 1167 | 1312 | default 0xfff36000 if DEBUG_HIGHBANK_UART |
| 1168 | 1313 | default 0xfffe8600 if DEBUG_UART_BCM63XX |
| 1169 | 1314 | default 0xfffff700 if ARCH_IOP33X |
| 1170 | 1315 | depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ |
| 1171 | 1316 | DEBUG_LL_UART_EFM32 || \ |
| 1172 | 1317 | DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ |
| 1173 | − DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ | |
| 1174 | − DEBUG_UART_BCM63XX | |
| 1318 | + DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ | |
| 1319 | + DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ | |
| 1320 | + DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \ | |
| 1321 | + DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \ | |
| 1322 | + DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \ | |
| 1323 | + DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART | |
| 1175 | 1324 | |
| 1176 | 1325 | config DEBUG_UART_VIRT |
| 1177 | 1326 | hex "Virtual base address of debug UART" |
| 1178 | 1327 | default 0xe0010fe0 if ARCH_RPC |
| 1179 | 1328 | default 0xe1000000 if DEBUG_MSM_UART |
| 1180 | 1329 | default 0xf0000be0 if ARCH_EBSA110 |
| 1330 | + default 0xf0010000 if DEBUG_ASM9260_UART | |
| 1181 | 1331 | default 0xf01fb000 if DEBUG_NOMADIK_UART |
| 1182 | 1332 | default 0xf0201000 if DEBUG_BCM2835 |
| 1183 | 1333 | default 0xf1000300 if DEBUG_BCM_5301X |
| 1334 | + default 0xf1002000 if DEBUG_MT8127_UART0 | |
| 1184 | 1335 | default 0xf1006000 if DEBUG_MT6589_UART0 |
| 1336 | + default 0xf1009000 if DEBUG_MT8135_UART3 | |
| 1185 | 1337 | default 0xf11f1000 if ARCH_VERSATILE |
| 1186 | 1338 | default 0xf1600000 if ARCH_INTEGRATOR |
| 1187 | 1339 | default 0xf1c28000 if DEBUG_SUNXI_UART0 |
| @@ -1190,6 +1342,7 @@ config DEBUG_UART_VIRT · 2 unmodified lines | ||
| 1190 | 1342 | default 0xf6200000 if DEBUG_PXA_UART1 |
| 1191 | 1343 | default 0xf4090000 if ARCH_LPC32XX |
| 1192 | 1344 | default 0xf4200000 if ARCH_GEMINI |
| 1345 | + default 0xf7000000 if DEBUG_SUN9I_UART0 | |
| 1193 | 1346 | default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \ |
| 1194 | 1347 | DEBUG_S3C2410_UART0) |
| 1195 | 1348 | default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \ |
| @@ -1204,6 +1357,7 @@ config DEBUG_UART_VIRT · 8 unmodified lines | ||
| 1204 | 1357 | default 0xfb002000 if DEBUG_CNS3XXX |
| 1205 | 1358 | default 0xfb009000 if DEBUG_REALVIEW_STD_PORT |
| 1206 | 1359 | default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT |
| 1360 | + default 0xfc40ab00 if DEBUG_BRCMSTB_UART | |
| 1207 | 1361 | default 0xfcfe8600 if DEBUG_UART_BCM63XX |
| 1208 | 1362 | default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX |
| 1209 | 1363 | default 0xfd000000 if ARCH_SPEAR13XX |
| @@ -1244,12 +1398,12 @@ config DEBUG_UART_VIRT · 34 unmodified lines | ||
| 1244 | 1398 | depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ |
| 1245 | 1399 | DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ |
| 1246 | 1400 | DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ |
| 1247 | − DEBUG_UART_BCM63XX | |
| 1401 | + DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART | |
| 1248 | 1402 | |
| 1249 | 1403 | config DEBUG_UART_8250_SHIFT |
| 1250 | 1404 | int "Register offset shift for the 8250 debug UART" |
| 1251 | 1405 | depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 |
| 1252 | − default 0 if FOOTBRIDGE || ARCH_IOP32X | |
| 1406 | + default 0 if FOOTBRIDGE || ARCH_IOP32X || DEBUG_BCM_5301X | |
| 1253 | 1407 | default 2 |
| 1254 | 1408 | |
| 1255 | 1409 | config DEBUG_UART_8250_WORD |
| @@ -1260,7 +1414,8 @@ config DEBUG_UART_8250_WORD · 4 unmodified lines | ||
| 1260 | 1414 | ARCH_KEYSTONE || \ |
| 1261 | 1415 | DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ |
| 1262 | 1416 | DEBUG_DAVINCI_DA8XX_UART2 || \ |
| 1263 | − DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 | |
| 1417 | + DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \ | |
| 1418 | + DEBUG_BRCMSTB_UART | |
| 1264 | 1419 | |
| 1265 | 1420 | config DEBUG_UART_8250_FLOW_CONTROL |
| 1266 | 1421 | bool "Enable flow control for 8250 UART" |
| @@ -312,8 +312,12 @@ $(INSTALL_TARGETS): · 311 unmodified lines | ||
| 312 | 312 | $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@ |
| 313 | 313 | |
| 314 | 314 | PHONY += dtbs dtbs_install |
| 315 | −dtbs dtbs_install: prepare scripts | |
| 316 | − $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $@ | |
| 315 | + | |
| 316 | +dtbs: prepare scripts | |
| 317 | + $(Q)$(MAKE) $(build)=$(boot)/dts | |
| 318 | + | |
| 319 | +dtbs_install: | |
| 320 | + $(Q)$(MAKE) $(dtbinst)=$(boot)/dts | |
| 317 | 321 | |
| 318 | 322 | # We use MRPROPER_FILES and CLEAN_FILES now |
| 319 | 323 | archclean: |
| @@ -54,8 +54,17 @@ dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb · 53 unmodified lines | ||
| 54 | 54 | dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb |
| 55 | 55 | dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb |
| 56 | 56 | dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb |
| 57 | −dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb | |
| 57 | +dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb | |
| 58 | +dtb-$(CONFIG_ARCH_BCM_5301X) += \ | |
| 59 | + bcm4708-buffalo-wzr-1750dhp.dtb \ | |
| 60 | + bcm4708-netgear-r6250.dtb \ | |
| 61 | + bcm4708-netgear-r6300-v2.dtb \ | |
| 62 | + bcm47081-asus-rt-n18u.dtb \ | |
| 63 | + bcm47081-buffalo-wzr-600dhp2.dtb | |
| 58 | 64 | dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb |
| 65 | +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \ | |
| 66 | + bcm911360k.dtb \ | |
| 67 | + bcm958300k.dtb | |
| 59 | 68 | dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ |
| 60 | 69 | bcm21664-garnet.dtb |
| 61 | 70 | dtb-$(CONFIG_ARCH_BERLIN) += \ |
| @@ -67,7 +76,9 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \ · 5 unmodified lines | ||
| 67 | 76 | dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ |
| 68 | 77 | da850-evm.dtb |
| 69 | 78 | dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb |
| 70 | −dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ | |
| 79 | +dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \ | |
| 80 | + exynos3250-rinato.dtb \ | |
| 81 | + exynos4210-origen.dtb \ | |
| 71 | 82 | exynos4210-smdkv310.dtb \ |
| 72 | 83 | exynos4210-trats.dtb \ |
| 73 | 84 | exynos4210-universal_c210.dtb \ |
| @@ -81,6 +92,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ · 7 unmodified lines | ||
| 81 | 92 | exynos5250-arndale.dtb \ |
| 82 | 93 | exynos5250-smdk5250.dtb \ |
| 83 | 94 | exynos5250-snow.dtb \ |
| 95 | + exynos5250-spring.dtb \ | |
| 84 | 96 | exynos5260-xyref5260.dtb \ |
| 85 | 97 | exynos5410-smdk5410.dtb \ |
| 86 | 98 | exynos5420-arndale-octa.dtb \ |
| @@ -104,6 +116,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ · 17 unmodified lines | ||
| 104 | 116 | kirkwood-d2net.dtb \ |
| 105 | 117 | kirkwood-db-88f6281.dtb \ |
| 106 | 118 | kirkwood-db-88f6282.dtb \ |
| 119 | + kirkwood-dir665.dtb \ | |
| 107 | 120 | kirkwood-dns320.dtb \ |
| 108 | 121 | kirkwood-dns325.dtb \ |
| 109 | 122 | kirkwood-dockstar.dtb \ |
| @@ -240,6 +253,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ · 130 unmodified lines | ||
| 240 | 253 | imx6q-sabrelite.dtb \ |
| 241 | 254 | imx6q-sabresd.dtb \ |
| 242 | 255 | imx6q-sbc6x.dtb \ |
| 256 | + imx6q-tbs2910.dtb \ | |
| 243 | 257 | imx6q-udoo.dtb \ |
| 244 | 258 | imx6q-wandboard.dtb \ |
| 245 | 259 | imx6q-wandboard-revb1.dtb \ |
| @@ -250,6 +264,9 @@ dtb-$(CONFIG_ARCH_MXC) += \ · 4 unmodified lines | ||
| 250 | 264 | imx6q-tx6q-1110.dtb \ |
| 251 | 265 | imx6sl-evk.dtb \ |
| 252 | 266 | imx6sx-sdb.dtb \ |
| 267 | + ls1021a-qds.dtb \ | |
| 268 | + ls1021a-twr.dtb \ | |
| 269 | + vf500-colibri-eval-v3.dtb \ | |
| 253 | 270 | vf610-colibri-eval-v3.dtb \ |
| 254 | 271 | vf610-cosmic.dtb \ |
| 255 | 272 | vf610-twr.dtb |
| @@ -274,7 +291,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ · 18 unmodified lines | ||
| 274 | 291 | imx28-m28evk.dtb \ |
| 275 | 292 | imx28-sps1.dtb \ |
| 276 | 293 | imx28-tx28.dtb |
| 277 | −dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb | |
| 294 | +dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \ | |
| 295 | + ste-nomadik-nhk15.dtb | |
| 278 | 296 | dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ |
| 279 | 297 | nspire-tp.dtb \ |
| 280 | 298 | nspire-clp.dtb |
| @@ -302,7 +320,9 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ · 21 unmodified lines | ||
| 302 | 320 | omap3-ha.dtb \ |
| 303 | 321 | omap3-ha-lcd.dtb \ |
| 304 | 322 | omap3-igep0020.dtb \ |
| 323 | + omap3-igep0020-rev-f.dtb \ | |
| 305 | 324 | omap3-igep0030.dtb \ |
| 325 | + omap3-igep0030-rev-g.dtb \ | |
| 306 | 326 | omap3-ldp.dtb \ |
| 307 | 327 | omap3-lilly-dbb056.dtb \ |
| 308 | 328 | omap3-n900.dtb \ |
| @@ -331,7 +351,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ · 22 unmodified lines | ||
| 331 | 351 | am335x-evm.dtb \ |
| 332 | 352 | am335x-evmsk.dtb \ |
| 333 | 353 | am335x-nano.dtb \ |
| 334 | − am335x-pepper.dtb | |
| 354 | + am335x-pepper.dtb \ | |
| 355 | + am335x-lxm.dtb | |
| 335 | 356 | dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ |
| 336 | 357 | omap4-panda.dtb \ |
| 337 | 358 | omap4-panda-a4.dtb \ |
| @@ -347,6 +368,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ · 9 unmodified lines | ||
| 347 | 368 | omap5-sbc-t54.dtb \ |
| 348 | 369 | omap5-uevm.dtb |
| 349 | 370 | dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ |
| 371 | + am57xx-beagle-x15.dtb \ | |
| 350 | 372 | dra72-evm.dtb |
| 351 | 373 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ |
| 352 | 374 | orion5x-lacie-ethernet-disk-mini-v2.dtb \ |
| @@ -363,8 +385,10 @@ dtb-$(CONFIG_ARCH_QCOM) += \ · 10 unmodified lines | ||
| 363 | 385 | qcom-msm8660-surf.dtb \ |
| 364 | 386 | qcom-msm8960-cdp.dtb \ |
| 365 | 387 | qcom-msm8974-sony-xperia-honami.dtb |
| 388 | +dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb | |
| 366 | 389 | dtb-$(CONFIG_ARCH_ROCKCHIP) += \ |
| 367 | 390 | rk3066a-bqcurie2.dtb \ |
| 391 | + rk3066a-marsboard.dtb \ | |
| 368 | 392 | rk3188-radxarock.dtb \ |
| 369 | 393 | rk3288-evb-act8846.dtb \ |
| 370 | 394 | rk3288-evb-rk808.dtb |
| @@ -376,27 +400,27 @@ dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \ · 5 unmodified lines | ||
| 376 | 400 | s5pv210-smdkc110.dtb \ |
| 377 | 401 | s5pv210-smdkv210.dtb \ |
| 378 | 402 | s5pv210-torbreck.dtb |
| 379 | −dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ | |
| 403 | +dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ | |
| 404 | + r8a73a4-ape6evm.dtb \ | |
| 405 | + r8a73a4-ape6evm-reference.dtb \ | |
| 380 | 406 | r8a7740-armadillo800eva.dtb \ |
| 381 | 407 | r8a7778-bockw.dtb \ |
| 382 | 408 | r8a7778-bockw-reference.dtb \ |
| 383 | 409 | r8a7779-marzen.dtb \ |
| 384 | − r8a7791-koelsch.dtb \ | |
| 385 | 410 | r8a7790-lager.dtb \ |
| 411 | + sh7372-mackerel.dtb \ | |
| 386 | 412 | sh73a0-kzm9g.dtb \ |
| 387 | − sh73a0-kzm9g-reference.dtb \ | |
| 388 | − r8a73a4-ape6evm.dtb \ | |
| 389 | − r8a73a4-ape6evm-reference.dtb \ | |
| 390 | − sh7372-mackerel.dtb | |
| 413 | + sh73a0-kzm9g-reference.dtb | |
| 391 | 414 | dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ |
| 392 | 415 | r7s72100-genmai.dtb \ |
| 393 | 416 | r8a7740-armadillo800eva.dtb \ |
| 417 | + r8a7779-marzen.dtb \ | |
| 418 | + r8a7790-lager.dtb \ | |
| 394 | 419 | r8a7791-henninger.dtb \ |
| 395 | 420 | r8a7791-koelsch.dtb \ |
| 396 | − r8a7790-lager.dtb \ | |
| 397 | − r8a7779-marzen.dtb \ | |
| 398 | 421 | r8a7794-alt.dtb |
| 399 | 422 | dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ |
| 423 | + socfpga_arria10_socdk.dtb \ | |
| 400 | 424 | socfpga_cyclone5_socdk.dtb \ |
| 401 | 425 | socfpga_cyclone5_sockit.dtb \ |
| 402 | 426 | socfpga_cyclone5_socrates.dtb \ |
| @@ -409,6 +433,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ · 6 unmodified lines | ||
| 409 | 433 | spear320-hmi.dtb |
| 410 | 434 | dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb |
| 411 | 435 | dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ |
| 436 | + stih410-b2120.dtb \ | |
| 412 | 437 | stih415-b2000.dtb \ |
| 413 | 438 | stih415-b2020.dtb \ |
| 414 | 439 | stih416-b2000.dtb \ |
| @@ -435,15 +460,20 @@ dtb-$(CONFIG_MACH_SUN6I) += \ · 20 unmodified lines | ||
| 435 | 460 | sun6i-a31-hummingbird.dtb \ |
| 436 | 461 | sun6i-a31-m9.dtb |
| 437 | 462 | dtb-$(CONFIG_MACH_SUN7I) += \ |
| 463 | + sun7i-a20-bananapi.dtb \ | |
| 438 | 464 | sun7i-a20-cubieboard2.dtb \ |
| 439 | 465 | sun7i-a20-cubietruck.dtb \ |
| 440 | 466 | sun7i-a20-hummingbird.dtb \ |
| 441 | 467 | sun7i-a20-i12-tvbox.dtb \ |
| 468 | + sun7i-a20-m3.dtb \ | |
| 442 | 469 | sun7i-a20-olinuxino-lime.dtb \ |
| 470 | + sun7i-a20-olinuxino-lime2.dtb \ | |
| 443 | 471 | sun7i-a20-olinuxino-micro.dtb \ |
| 444 | 472 | sun7i-a20-pcduino3.dtb |
| 445 | 473 | dtb-$(CONFIG_MACH_SUN8I) += \ |
| 446 | 474 | sun8i-a23-ippo-q8h-v5.dtb |
| 475 | +dtb-$(CONFIG_MACH_SUN9I) += \ | |
| 476 | + sun9i-a80-optimus.dtb | |
| 447 | 477 | dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ |
| 448 | 478 | tegra20-iris-512.dtb \ |
| 449 | 479 | tegra20-medcom-wide.dtb \ |
| @@ -489,13 +519,15 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ · 39 unmodified lines | ||
| 489 | 519 | zynq-parallella.dtb \ |
| 490 | 520 | zynq-zc702.dtb \ |
| 491 | 521 | zynq-zc706.dtb \ |
| 492 | − zynq-zed.dtb | |
| 522 | + zynq-zed.dtb \ | |
| 523 | + zynq-zybo.dtb | |
| 493 | 524 | dtb-$(CONFIG_MACH_ARMADA_370) += \ |
| 494 | 525 | armada-370-db.dtb \ |
| 495 | 526 | armada-370-mirabox.dtb \ |
| 496 | 527 | armada-370-netgear-rn102.dtb \ |
| 497 | 528 | armada-370-netgear-rn104.dtb \ |
| 498 | − armada-370-rd.dtb | |
| 529 | + armada-370-rd.dtb \ | |
| 530 | + armada-370-synology-ds213j.dtb | |
| 499 | 531 | dtb-$(CONFIG_MACH_ARMADA_375) += \ |
| 500 | 532 | armada-375-db.dtb |
| 501 | 533 | dtb-$(CONFIG_MACH_ARMADA_38X) += \ |
| @@ -508,24 +540,20 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ · 6 unmodified lines | ||
| 508 | 540 | armada-xp-lenovo-ix4-300d.dtb \ |
| 509 | 541 | armada-xp-matrix.dtb \ |
| 510 | 542 | armada-xp-netgear-rn2120.dtb \ |
| 511 | − armada-xp-openblocks-ax3-4.dtb | |
| 543 | + armada-xp-openblocks-ax3-4.dtb \ | |
| 544 | + armada-xp-synology-ds414.dtb | |
| 512 | 545 | dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ |
| 513 | 546 | dove-cubox.dtb \ |
| 514 | 547 | dove-cubox-es.dtb \ |
| 515 | 548 | dove-d2plug.dtb \ |
| 516 | 549 | dove-d3plug.dtb \ |
| 517 | 550 | dove-dove-db.dtb |
| 518 | −dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb | |
| 551 | +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \ | |
| 552 | + mt6592-evb.dtb \ | |
| 553 | + mt8127-moose.dtb \ | |
| 554 | + mt8135-evbp1.dtb | |
| 519 | 555 | |
| 520 | −targets += dtbs dtbs_install | |
| 521 | −targets += $(dtb-y) | |
| 522 | 556 | endif |
| 523 | 557 | |
| 524 | −# *.dtb used to be generated in the directory above. Clean out the | |
| 525 | −# old build results so people don't accidentally use them. | |
| 526 | −dtbs: $(addprefix $(obj)/, $(dtb-y)) | |
| 527 | − $(Q)rm -f $(obj)/../*.dtb | |
| 528 | − | |
| 529 | −clean-files := *.dtb | |
| 530 | − | |
| 531 | −dtbs_install: $(addsuffix _dtbinst_, $(dtb-y)) | |
| 558 | +always := $(dtb-y) | |
| 559 | +clean-files := *.dtb | |
| @@ -307,6 +307,13 @@ · 306 unmodified lines | ||
| 307 | 307 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ |
| 308 | 308 | >; |
| 309 | 309 | }; |
| 310 | + | |
| 311 | + dcan1_pins_default: dcan1_pins_default { | |
| 312 | + pinctrl-single,pins = < | |
| 313 | + 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ | |
| 314 | + 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ | |
| 315 | + >; | |
| 316 | + }; | |
| 310 | 317 | }; |
| 311 | 318 | |
| 312 | 319 | &uart0 { |
| @@ -437,9 +444,9 @@ · 124 unmodified lines | ||
| 437 | 444 | status = "okay"; |
| 438 | 445 | pinctrl-names = "default"; |
| 439 | 446 | pinctrl-0 = <&nandflash_pins_s0>; |
| 440 | − ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ | |
| 447 | + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ | |
| 441 | 448 | nand@0,0 { |
| 442 | − reg = <0 0 0>; /* CS0, offset 0 */ | |
| 449 | + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
| 443 | 450 | ti,nand-ecc-opt = "bch8"; |
| 444 | 451 | ti,elm-id = <&elm>; |
| 445 | 452 | nand-bus-width = <8>; |
| @@ -664,3 +671,9 @@ · 218 unmodified lines | ||
| 664 | 671 | &aes { |
| 665 | 672 | status = "okay"; |
| 666 | 673 | }; |
| 674 | + | |
| 675 | +&dcan1 { | |
| 676 | + status = "disabled"; /* Enable only if Profile 1 is selected */ | |
| 677 | + pinctrl-names = "default"; | |
| 678 | + pinctrl-0 = <&dcan1_pins_default>; | |
| 679 | +}; | |
| @@ -126,10 +126,10 @@ · 125 unmodified lines | ||
| 126 | 126 | pinctrl-names = "default"; |
| 127 | 127 | pinctrl-0 = <&nandflash_pins>; |
| 128 | 128 | |
| 129 | − ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ | |
| 129 | + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ | |
| 130 | 130 | |
| 131 | 131 | nand@0,0 { |
| 132 | − reg = <0 0 0>; /* CS0, offset 0 */ | |
| 132 | + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
| 133 | 133 | nand-bus-width = <8>; |
| 134 | 134 | ti,nand-ecc-opt = "bch8"; |
| 135 | 135 | gpmc,device-width = <1>; |
| @@ -0,0 +1,362 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com | |
| 3 | + * | |
| 4 | + * This program is free software; you can redistribute it and/or modify | |
| 5 | + * it under the terms of the GNU General Public License version 2 as | |
| 6 | + * published by the Free Software Foundation. | |
| 7 | + */ | |
| 8 | +/dts-v1/; | |
| 9 | + | |
| 10 | +#include "am33xx.dtsi" | |
| 11 | + | |
| 12 | +/ { | |
| 13 | + model = "NovaTech OrionLXm"; | |
| 14 | + compatible = "novatech,am335x-lxm", "ti,am33xx"; | |
| 15 | + | |
| 16 | + cpus { | |
| 17 | + cpu@0 { | |
| 18 | + cpu0-supply = <&vdd1_reg>; | |
| 19 | + }; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + device_type = "memory"; | |
| 24 | + reg = <0x80000000 0x20000000>; /* 512 MB */ | |
| 25 | + }; | |
| 26 | + | |
| 27 | + /* Power supply provides a fixed 5V @2A */ | |
| 28 | + vbat: fixedregulator@0 { | |
| 29 | + compatible = "regulator-fixed"; | |
| 30 | + regulator-name = "vbat"; | |
| 31 | + regulator-min-microvolt = <5000000>; | |
| 32 | + regulator-max-microvolt = <5000000>; | |
| 33 | + regulator-boot-on; | |
| 34 | + }; | |
| 35 | + | |
| 36 | + /* Power supply provides a fixed 3.3V @3A */ | |
| 37 | + vmmcsd_fixed: fixedregulator@1 { | |
| 38 | + compatible = "regulator-fixed"; | |
| 39 | + regulator-name = "vmmcsd_fixed"; | |
| 40 | + regulator-min-microvolt = <3300000>; | |
| 41 | + regulator-max-microvolt = <3300000>; | |
| 42 | + regulator-boot-on; | |
| 43 | + }; | |
| 44 | +}; | |
| 45 | + | |
| 46 | +&am33xx_pinmux { | |
| 47 | + mmc1_pins: pinmux_mmc1_pins { | |
| 48 | + pinctrl-single,pins = < | |
| 49 | + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ | |
| 50 | + 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ | |
| 51 | + 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ | |
| 52 | + 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ | |
| 53 | + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ | |
| 54 | + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ | |
| 55 | + >; | |
| 56 | + }; | |
| 57 | + | |
| 58 | + i2c0_pins: pinmux_i2c0_pins { | |
| 59 | + pinctrl-single,pins = < | |
| 60 | + 0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | |
| 61 | + 0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
| 62 | + >; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + cpsw_default: cpsw_default { | |
| 66 | + pinctrl-single,pins = < | |
| 67 | + /* Slave 1 */ | |
| 68 | + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ | |
| 69 | + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */ | |
| 70 | + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */ | |
| 71 | + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */ | |
| 72 | + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */ | |
| 73 | + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */ | |
| 74 | + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */ | |
| 75 | + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */ | |
| 76 | + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */ | |
| 77 | + | |
| 78 | + /* Slave 2 */ | |
| 79 | + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */ | |
| 80 | + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */ | |
| 81 | + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */ | |
| 82 | + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */ | |
| 83 | + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */ | |
| 84 | + 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */ | |
| 85 | + 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */ | |
| 86 | + 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ | |
| 87 | + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */ | |
| 88 | + >; | |
| 89 | + }; | |
| 90 | + | |
| 91 | + cpsw_sleep: cpsw_sleep { | |
| 92 | + pinctrl-single,pins = < | |
| 93 | + /* Slave 1 reset value */ | |
| 94 | + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ | |
| 95 | + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */ | |
| 96 | + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */ | |
| 97 | + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */ | |
| 98 | + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */ | |
| 99 | + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */ | |
| 100 | + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */ | |
| 101 | + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */ | |
| 102 | + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */ | |
| 103 | + | |
| 104 | + /* Slave 2 reset value*/ | |
| 105 | + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */ | |
| 106 | + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */ | |
| 107 | + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */ | |
| 108 | + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */ | |
| 109 | + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */ | |
| 110 | + 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */ | |
| 111 | + 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */ | |
| 112 | + 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ | |
| 113 | + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */ | |
| 114 | + >; | |
| 115 | + }; | |
| 116 | + | |
| 117 | + davinci_mdio_default: davinci_mdio_default { | |
| 118 | + pinctrl-single,pins = < | |
| 119 | + /* MDIO */ | |
| 120 | + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | |
| 121 | + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
| 122 | + >; | |
| 123 | + }; | |
| 124 | + | |
| 125 | + davinci_mdio_sleep: davinci_mdio_sleep { | |
| 126 | + pinctrl-single,pins = < | |
| 127 | + /* MDIO reset value */ | |
| 128 | + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 129 | + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
| 130 | + >; | |
| 131 | + }; | |
| 132 | + | |
| 133 | + emmc_pins: pinmux_emmc_pins { | |
| 134 | + pinctrl-single,pins = < | |
| 135 | + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ | |
| 136 | + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ | |
| 137 | + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ | |
| 138 | + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ | |
| 139 | + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ | |
| 140 | + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ | |
| 141 | + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ | |
| 142 | + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ | |
| 143 | + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ | |
| 144 | + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ | |
| 145 | + >; | |
| 146 | + }; | |
| 147 | + | |
| 148 | + uart0_pins: pinmux_uart0_pins { | |
| 149 | + pinctrl-single,pins = < | |
| 150 | + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | |
| 151 | + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | |
| 152 | + >; | |
| 153 | + }; | |
| 154 | +}; | |
| 155 | + | |
| 156 | +&i2c0 { | |
| 157 | + pinctrl-names = "default"; | |
| 158 | + pinctrl-0 = <&i2c0_pins>; | |
| 159 | + | |
| 160 | + status = "okay"; | |
| 161 | + clock-frequency = <400000>; | |
| 162 | + | |
| 163 | + serial_config1: serial_config1@20 { | |
| 164 | + compatible = "nxp,pca9539"; | |
| 165 | + reg = <0x20>; | |
| 166 | + }; | |
| 167 | + | |
| 168 | + serial_config2: serial_config2@21 { | |
| 169 | + compatible = "nxp,pca9539"; | |
| 170 | + reg = <0x21>; | |
| 171 | + }; | |
| 172 | + | |
| 173 | + tps: tps@2d { | |
| 174 | + compatible = "ti,tps65910"; | |
| 175 | + reg = <0x2d>; | |
| 176 | + }; | |
| 177 | +}; | |
| 178 | + | |
| 179 | +/include/ "tps65910.dtsi" | |
| 180 | + | |
| 181 | +&tps { | |
| 182 | + vcc1-supply = <&vbat>; | |
| 183 | + vcc2-supply = <&vbat>; | |
| 184 | + vcc3-supply = <&vbat>; | |
| 185 | + vcc4-supply = <&vbat>; | |
| 186 | + vcc5-supply = <&vbat>; | |
| 187 | + vcc6-supply = <&vbat>; | |
| 188 | + vcc7-supply = <&vbat>; | |
| 189 | + vccio-supply = <&vbat>; | |
| 190 | + | |
| 191 | + regulators { | |
| 192 | + /* vrtc - unused */ | |
| 193 | + | |
| 194 | + vio_reg: regulator@1 { | |
| 195 | + regulator-name = "vio_1v5,ddr"; | |
| 196 | + regulator-min-microvolt = <1500000>; | |
| 197 | + regulator-max-microvolt = <1500000>; | |
| 198 | + regulator-boot-on; | |
| 199 | + regulator-always-on; | |
| 200 | + }; | |
| 201 | + | |
| 202 | + vdd1_reg: regulator@2 { | |
| 203 | + regulator-name = "vdd1,mpu"; | |
| 204 | + regulator-min-microvolt = <600000>; | |
| 205 | + regulator-max-microvolt = <1500000>; | |
| 206 | + regulator-boot-on; | |
| 207 | + regulator-always-on; | |
| 208 | + }; | |
| 209 | + | |
| 210 | + vdd2_reg: regulator@3 { | |
| 211 | + regulator-name = "vdd2_1v1,core"; | |
| 212 | + regulator-min-microvolt = <1100000>; | |
| 213 | + regulator-max-microvolt = <1100000>; | |
| 214 | + regulator-boot-on; | |
| 215 | + regulator-always-on; | |
| 216 | + }; | |
| 217 | + | |
| 218 | + /* vdd3 - unused */ | |
| 219 | + | |
| 220 | + /* vdig1 - unused */ | |
| 221 | + | |
| 222 | + vdig2_reg: regulator@6 { | |
| 223 | + regulator-name = "vdig2_1v8,vdds_pll"; | |
| 224 | + regulator-min-microvolt = <1800000>; | |
| 225 | + regulator-max-microvolt = <1800000>; | |
| 226 | + regulator-boot-on; | |
| 227 | + regulator-always-on; | |
| 228 | + }; | |
| 229 | + | |
| 230 | + /* vpll - unused */ | |
| 231 | + | |
| 232 | + vdac_reg: regulator@8 { | |
| 233 | + regulator-name = "vdac_1v8,vdds"; | |
| 234 | + regulator-min-microvolt = <1800000>; | |
| 235 | + regulator-max-microvolt = <1800000>; | |
| 236 | + regulator-boot-on; | |
| 237 | + regulator-always-on; | |
| 238 | + }; | |
| 239 | + | |
| 240 | + vaux1_reg: regulator@9 { | |
| 241 | + regulator-name = "vaux1_1v8,usb"; | |
| 242 | + regulator-min-microvolt = <1800000>; | |
| 243 | + regulator-max-microvolt = <1800000>; | |
| 244 | + regulator-boot-on; | |
| 245 | + regulator-always-on; | |
| 246 | + }; | |
| 247 | + | |
| 248 | + vaux2_reg: regulator@10 { | |
| 249 | + regulator-name = "vaux2_3v3,io"; | |
| 250 | + regulator-min-microvolt = <3300000>; | |
| 251 | + regulator-max-microvolt = <3300000>; | |
| 252 | + regulator-boot-on; | |
| 253 | + regulator-always-on; | |
| 254 | + }; | |
| 255 | + | |
| 256 | + vaux33_reg: regulator@11 { | |
| 257 | + regulator-name = "vaux33_3v3,usb"; | |
| 258 | + regulator-min-microvolt = <3300000>; | |
| 259 | + regulator-max-microvolt = <3300000>; | |
| 260 | + regulator-boot-on; | |
| 261 | + regulator-always-on; | |
| 262 | + }; | |
| 263 | + | |
| 264 | + vmmc_reg: regulator@12 { | |
| 265 | + regulator-name = "vmmc_3v3,io"; | |
| 266 | + regulator-min-microvolt = <3300000>; | |
| 267 | + regulator-max-microvolt = <3300000>; | |
| 268 | + regulator-boot-on; | |
| 269 | + regulator-always-on; | |
| 270 | + }; | |
| 271 | + }; | |
| 272 | +}; | |
| 273 | + | |
| 274 | +&sham { | |
| 275 | + status = "okay"; | |
| 276 | +}; | |
| 277 | + | |
| 278 | +&aes { | |
| 279 | + status = "okay"; | |
| 280 | +}; | |
| 281 | + | |
| 282 | +&uart0 { | |
| 283 | + pinctrl-names = "default"; | |
| 284 | + pinctrl-0 = <&uart0_pins>; | |
| 285 | + | |
| 286 | + status = "okay"; | |
| 287 | +}; | |
| 288 | + | |
| 289 | +&usb { | |
| 290 | + status = "okay"; | |
| 291 | +}; | |
| 292 | + | |
| 293 | +&usb_ctrl_mod { | |
| 294 | + status = "okay"; | |
| 295 | +}; | |
| 296 | + | |
| 297 | +&usb0_phy { | |
| 298 | + status = "okay"; | |
| 299 | +}; | |
| 300 | + | |
| 301 | +&usb1_phy { | |
| 302 | + status = "okay"; | |
| 303 | +}; | |
| 304 | + | |
| 305 | +&usb0 { | |
| 306 | + status = "okay"; | |
| 307 | + dr_mode = "host"; | |
| 308 | +}; | |
| 309 | + | |
| 310 | +&usb1 { | |
| 311 | + status = "okay"; | |
| 312 | + dr_mode = "host"; | |
| 313 | +}; | |
| 314 | + | |
| 315 | +&cppi41dma { | |
| 316 | + status = "okay"; | |
| 317 | +}; | |
| 318 | + | |
| 319 | +&cpsw_emac0 { | |
| 320 | + phy_id = <&davinci_mdio>, <5>; | |
| 321 | + phy-mode = "rmii"; | |
| 322 | + dual_emac_res_vlan = <2>; | |
| 323 | +}; | |
| 324 | + | |
| 325 | +&cpsw_emac1 { | |
| 326 | + phy_id = <&davinci_mdio>, <4>; | |
| 327 | + phy-mode = "rmii"; | |
| 328 | + dual_emac_res_vlan = <3>; | |
| 329 | +}; | |
| 330 | + | |
| 331 | +&mac { | |
| 332 | + pinctrl-names = "default", "sleep"; | |
| 333 | + pinctrl-0 = <&cpsw_default>; | |
| 334 | + pinctrl-1 = <&cpsw_sleep>; | |
| 335 | + dual_emac = <1>; | |
| 336 | + status = "okay"; | |
| 337 | +}; | |
| 338 | + | |
| 339 | +&davinci_mdio { | |
| 340 | + pinctrl-names = "default", "sleep"; | |
| 341 | + pinctrl-0 = <&davinci_mdio_default>; | |
| 342 | + pinctrl-1 = <&davinci_mdio_sleep>; | |
| 343 | + status = "okay"; | |
| 344 | +}; | |
| 345 | + | |
| 346 | +&mmc1 { | |
| 347 | + pinctrl-names = "default"; | |
| 348 | + pinctrl-0 = <&mmc1_pins>; | |
| 349 | + vmmc-supply = <&vmmcsd_fixed>; | |
| 350 | + bus-width = <4>; | |
| 351 | + status = "okay"; | |
| 352 | +}; | |
| 353 | + | |
| 354 | +&mmc2 { | |
| 355 | + pinctrl-names = "default"; | |
| 356 | + pinctrl-0 = <&emmc_pins>; | |
| 357 | + vmmc-supply = <&vmmcsd_fixed>; | |
| 358 | + bus-width = <8>; | |
| 359 | + ti,non-removable; | |
| 360 | + status = "okay"; | |
| 361 | +}; | |
| 362 | + | |
| @@ -83,6 +83,11 @@ · 82 unmodified lines | ||
| 83 | 83 | }; |
| 84 | 84 | }; |
| 85 | 85 | |
| 86 | + am33xx_control_module: control_module@4a002000 { | |
| 87 | + compatible = "syscon"; | |
| 88 | + reg = <0x44e10000 0x7fc>; | |
| 89 | + }; | |
| 90 | + | |
| 86 | 91 | am33xx_pinmux: pinmux@44e10800 { |
| 87 | 92 | compatible = "pinctrl-single"; |
| 88 | 93 | reg = <0x44e10800 0x0238>; |
| @@ -204,6 +209,8 @@ · 115 unmodified lines | ||
| 204 | 209 | reg = <0x44e09000 0x2000>; |
| 205 | 210 | interrupts = <72>; |
| 206 | 211 | status = "disabled"; |
| 212 | + dmas = <&edma 26>, <&edma 27>; | |
| 213 | + dma-names = "tx", "rx"; | |
| 207 | 214 | }; |
| 208 | 215 | |
| 209 | 216 | uart1: serial@48022000 { |
| @@ -213,6 +220,8 @@ · 3 unmodified lines | ||
| 213 | 220 | reg = <0x48022000 0x2000>; |
| 214 | 221 | interrupts = <73>; |
| 215 | 222 | status = "disabled"; |
| 223 | + dmas = <&edma 28>, <&edma 29>; | |
| 224 | + dma-names = "tx", "rx"; | |
| 216 | 225 | }; |
| 217 | 226 | |
| 218 | 227 | uart2: serial@48024000 { |
| @@ -222,6 +231,8 @@ · 3 unmodified lines | ||
| 222 | 231 | reg = <0x48024000 0x2000>; |
| 223 | 232 | interrupts = <74>; |
| 224 | 233 | status = "disabled"; |
| 234 | + dmas = <&edma 30>, <&edma 31>; | |
| 235 | + dma-names = "tx", "rx"; | |
| 225 | 236 | }; |
| 226 | 237 | |
| 227 | 238 | uart3: serial@481a6000 { |
| @@ -333,20 +344,24 @@ · 105 unmodified lines | ||
| 333 | 344 | interrupts = <91>; |
| 334 | 345 | }; |
| 335 | 346 | |
| 336 | − dcan0: d_can@481cc000 { | |
| 337 | − compatible = "bosch,d_can"; | |
| 347 | + dcan0: can@481cc000 { | |
| 348 | + compatible = "ti,am3352-d_can"; | |
| 338 | 349 | ti,hwmods = "d_can0"; |
| 339 | − reg = <0x481cc000 0x2000 | |
| 340 | − 0x44e10644 0x4>; | |
| 350 | + reg = <0x481cc000 0x2000>; | |
| 351 | + clocks = <&dcan0_fck>; | |
| 352 | + clock-names = "fck"; | |
| 353 | + syscon-raminit = <&am33xx_control_module 0x644 0>; | |
| 341 | 354 | interrupts = <52>; |
| 342 | 355 | status = "disabled"; |
| 343 | 356 | }; |
| 344 | 357 | |
| 345 | − dcan1: d_can@481d0000 { | |
| 346 | − compatible = "bosch,d_can"; | |
| 358 | + dcan1: can@481d0000 { | |
| 359 | + compatible = "ti,am3352-d_can"; | |
| 347 | 360 | ti,hwmods = "d_can1"; |
| 348 | − reg = <0x481d0000 0x2000 | |
| 349 | − 0x44e10644 0x4>; | |
| 361 | + reg = <0x481d0000 0x2000>; | |
| 362 | + clocks = <&dcan1_fck>; | |
| 363 | + clock-names = "fck"; | |
| 364 | + syscon-raminit = <&am33xx_control_module 0x644 1>; | |
| 350 | 365 | interrupts = <55>; |
| 351 | 366 | status = "disabled"; |
| 352 | 367 | }; |
| @@ -356,6 +371,7 @@ · 3 unmodified lines | ||
| 356 | 371 | reg = <0x480C8000 0x200>; |
| 357 | 372 | interrupts = <77>; |
| 358 | 373 | ti,hwmods = "mailbox"; |
| 374 | + #mbox-cells = <1>; | |
| 359 | 375 | ti,mbox-num-users = <4>; |
| 360 | 376 | ti,mbox-num-fifos = <8>; |
| 361 | 377 | mbox_wkupm3: wkup_m3 { |
| @@ -57,6 +57,11 @@ · 56 unmodified lines | ||
| 57 | 57 | cache-level = <2>; |
| 58 | 58 | }; |
| 59 | 59 | |
| 60 | + am43xx_control_module: control_module@4a002000 { | |
| 61 | + compatible = "syscon"; | |
| 62 | + reg = <0x44e10000 0x7f4>; | |
| 63 | + }; | |
| 64 | + | |
| 60 | 65 | am43xx_pinmux: pinmux@44e10800 { |
| 61 | 66 | compatible = "ti,am437-padconf", "pinctrl-single"; |
| 62 | 67 | reg = <0x44e10800 0x31c>; |
| @@ -168,6 +173,7 @@ · 105 unmodified lines | ||
| 168 | 173 | reg = <0x480C8000 0x200>; |
| 169 | 174 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 170 | 175 | ti,hwmods = "mailbox"; |
| 176 | + #mbox-cells = <1>; | |
| 171 | 177 | ti,mbox-num-users = <4>; |
| 172 | 178 | ti,mbox-num-fifos = <8>; |
| 173 | 179 | mbox_wkupm3: wkup_m3 { |
| @@ -667,6 +673,26 @@ · 493 unmodified lines | ||
| 667 | 673 | }; |
| 668 | 674 | }; |
| 669 | 675 | |
| 676 | + tscadc: tscadc@44e0d000 { | |
| 677 | + compatible = "ti,am3359-tscadc"; | |
| 678 | + reg = <0x44e0d000 0x1000>; | |
| 679 | + ti,hwmods = "adc_tsc"; | |
| 680 | + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 681 | + clocks = <&adc_tsc_fck>; | |
| 682 | + clock-names = "fck"; | |
| 683 | + status = "disabled"; | |
| 684 | + | |
| 685 | + tsc { | |
| 686 | + compatible = "ti,am3359-tsc"; | |
| 687 | + }; | |
| 688 | + | |
| 689 | + adc { | |
| 690 | + #io-channel-cells = <1>; | |
| 691 | + compatible = "ti,am3359-adc"; | |
| 692 | + }; | |
| 693 | + | |
| 694 | + }; | |
| 695 | + | |
| 670 | 696 | sham: sham@53100000 { |
| 671 | 697 | compatible = "ti,omap5-sham"; |
| 672 | 698 | ti,hwmods = "sham"; |
| @@ -896,6 +922,28 @@ · 223 unmodified lines | ||
| 896 | 922 | compatible = "mmio-sram"; |
| 897 | 923 | reg = <0x40300000 0x40000>; /* 256k */ |
| 898 | 924 | }; |
| 925 | + | |
| 926 | + dcan0: can@481cc000 { | |
| 927 | + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; | |
| 928 | + ti,hwmods = "d_can0"; | |
| 929 | + clocks = <&dcan0_fck>; | |
| 930 | + clock-names = "fck"; | |
| 931 | + reg = <0x481cc000 0x2000>; | |
| 932 | + syscon-raminit = <&am43xx_control_module 0x644 0>; | |
| 933 | + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
| 934 | + status = "disabled"; | |
| 935 | + }; | |
| 936 | + | |
| 937 | + dcan1: can@481d0000 { | |
| 938 | + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; | |
| 939 | + ti,hwmods = "d_can1"; | |
| 940 | + clocks = <&dcan1_fck>; | |
| 941 | + clock-names = "fck"; | |
| 942 | + reg = <0x481d0000 0x2000>; | |
| 943 | + syscon-raminit = <&am43xx_control_module 0x644 1>; | |
| 944 | + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
| 945 | + status = "disabled"; | |
| 946 | + }; | |
| 899 | 947 | }; |
| 900 | 948 | }; |
| 901 | 949 | |
| @@ -254,6 +254,20 @@ · 253 unmodified lines | ||
| 254 | 254 | 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) |
| 255 | 255 | >; |
| 256 | 256 | }; |
| 257 | + | |
| 258 | + dcan0_default: dcan0_default_pins { | |
| 259 | + pinctrl-single,pins = < | |
| 260 | + 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ | |
| 261 | + 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ | |
| 262 | + >; | |
| 263 | + }; | |
| 264 | + | |
| 265 | + dcan1_default: dcan1_default_pins { | |
| 266 | + pinctrl-single,pins = < | |
| 267 | + 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ | |
| 268 | + 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ | |
| 269 | + >; | |
| 270 | + }; | |
| 257 | 271 | }; |
| 258 | 272 | |
| 259 | 273 | &i2c0 { |
| @@ -343,6 +357,14 @@ · 83 unmodified lines | ||
| 343 | 357 | status = "okay"; |
| 344 | 358 | }; |
| 345 | 359 | |
| 360 | +&tscadc { | |
| 361 | + status = "okay"; | |
| 362 | + | |
| 363 | + adc { | |
| 364 | + ti,adc-channels = <0 1 2 3 4 5 6 7>; | |
| 365 | + }; | |
| 366 | +}; | |
| 367 | + | |
| 346 | 368 | &ecap0 { |
| 347 | 369 | status = "okay"; |
| 348 | 370 | pinctrl-names = "default"; |
| @@ -511,3 +533,15 @@ · 162 unmodified lines | ||
| 511 | 533 | }; |
| 512 | 534 | }; |
| 513 | 535 | }; |
| 536 | + | |
| 537 | +&dcan0 { | |
| 538 | + pinctrl-names = "default"; | |
| 539 | + pinctrl-0 = <&dcan0_default>; | |
| 540 | + status = "okay"; | |
| 541 | +}; | |
| 542 | + | |
| 543 | +&dcan1 { | |
| 544 | + pinctrl-names = "default"; | |
| 545 | + pinctrl-0 = <&dcan1_default>; | |
| 546 | + status = "okay"; | |
| 547 | +}; | |
| @@ -438,9 +438,9 @@ · 437 unmodified lines | ||
| 438 | 438 | status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ |
| 439 | 439 | pinctrl-names = "default"; |
| 440 | 440 | pinctrl-0 = <&nand_flash_x8>; |
| 441 | − ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ | |
| 441 | + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ | |
| 442 | 442 | nand@0,0 { |
| 443 | − reg = <0 0 0>; /* CS0, offset 0 */ | |
| 443 | + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
| 444 | 444 | ti,nand-ecc-opt = "bch16"; |
| 445 | 445 | ti,elm-id = <&elm>; |
| 446 | 446 | nand-bus-width = <8>; |
| @@ -519,6 +519,14 @@ · 72 unmodified lines | ||
| 519 | 519 | status = "okay"; |
| 520 | 520 | }; |
| 521 | 521 | |
| 522 | +&tscadc { | |
| 523 | + status = "okay"; | |
| 524 | + | |
| 525 | + adc { | |
| 526 | + ti,adc-channels = <0 1 2 3 4 5 6 7>; | |
| 527 | + }; | |
| 528 | +}; | |
| 529 | + | |
| 522 | 530 | &ecap0 { |
| 523 | 531 | status = "okay"; |
| 524 | 532 | pinctrl-names = "default"; |
| @@ -0,0 +1,405 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | |
| 3 | + * | |
| 4 | + * This program is free software; you can redistribute it and/or modify | |
| 5 | + * it under the terms of the GNU General Public License version 2 as | |
| 6 | + * published by the Free Software Foundation. | |
| 7 | + */ | |
| 8 | +/dts-v1/; | |
| 9 | + | |
| 10 | +#include "dra74x.dtsi" | |
| 11 | +#include <dt-bindings/clk/ti-dra7-atl.h> | |
| 12 | +#include <dt-bindings/gpio/gpio.h> | |
| 13 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 14 | + | |
| 15 | +/ { | |
| 16 | + model = "TI AM5728 BeagleBoard-X15"; | |
| 17 | + compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; | |
| 18 | + | |
| 19 | + aliases { | |
| 20 | + rtc0 = &mcp_rtc; | |
| 21 | + rtc1 = &tps659038_rtc; | |
| 22 | + }; | |
| 23 | + | |
| 24 | + memory { | |
| 25 | + device_type = "memory"; | |
| 26 | + reg = <0x80000000 0x80000000>; | |
| 27 | + }; | |
| 28 | + | |
| 29 | + vdd_3v3: fixedregulator-vdd_3v3 { | |
| 30 | + compatible = "regulator-fixed"; | |
| 31 | + regulator-name = "vdd_3v3"; | |
| 32 | + vin-supply = <®en1>; | |
| 33 | + regulator-min-microvolt = <3300000>; | |
| 34 | + regulator-max-microvolt = <3300000>; | |
| 35 | + }; | |
| 36 | + | |
| 37 | + vtt_fixed: fixedregulator-vtt { | |
| 38 | + /* TPS51200 */ | |
| 39 | + compatible = "regulator-fixed"; | |
| 40 | + regulator-name = "vtt_fixed"; | |
| 41 | + vin-supply = <&smps3_reg>; | |
| 42 | + regulator-min-microvolt = <3300000>; | |
| 43 | + regulator-max-microvolt = <3300000>; | |
| 44 | + regulator-always-on; | |
| 45 | + regulator-boot-on; | |
| 46 | + enable-active-high; | |
| 47 | + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + leds { | |
| 51 | + compatible = "gpio-leds"; | |
| 52 | + pinctrl-names = "default"; | |
| 53 | + pinctrl-0 = <&leds_pins_default>; | |
| 54 | + | |
| 55 | + led@0 { | |
| 56 | + label = "beagle-x15:usr0"; | |
| 57 | + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; | |
| 58 | + linux,default-trigger = "heartbeat"; | |
| 59 | + default-state = "off"; | |
| 60 | + }; | |
| 61 | + | |
| 62 | + led@1 { | |
| 63 | + label = "beagle-x15:usr1"; | |
| 64 | + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; | |
| 65 | + linux,default-trigger = "cpu0"; | |
| 66 | + default-state = "off"; | |
| 67 | + }; | |
| 68 | + | |
| 69 | + led@2 { | |
| 70 | + label = "beagle-x15:usr2"; | |
| 71 | + gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; | |
| 72 | + linux,default-trigger = "mmc0"; | |
| 73 | + default-state = "off"; | |
| 74 | + }; | |
| 75 | + | |
| 76 | + led@3 { | |
| 77 | + label = "beagle-x15:usr3"; | |
| 78 | + gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; | |
| 79 | + linux,default-trigger = "ide-disk"; | |
| 80 | + default-state = "off"; | |
| 81 | + }; | |
| 82 | + }; | |
| 83 | +}; | |
| 84 | + | |
| 85 | +&dra7_pmx_core { | |
| 86 | + leds_pins_default: leds_pins_default { | |
| 87 | + pinctrl-single,pins = < | |
| 88 | + 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */ | |
| 89 | + 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */ | |
| 90 | + 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */ | |
| 91 | + 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */ | |
| 92 | + >; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + i2c1_pins_default: i2c1_pins_default { | |
| 96 | + pinctrl-single,pins = < | |
| 97 | + 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ | |
| 98 | + 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ | |
| 99 | + >; | |
| 100 | + }; | |
| 101 | + | |
| 102 | + i2c3_pins_default: i2c3_pins_default { | |
| 103 | + pinctrl-single,pins = < | |
| 104 | + 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ | |
| 105 | + 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ | |
| 106 | + >; | |
| 107 | + }; | |
| 108 | + | |
| 109 | + uart3_pins_default: uart3_pins_default { | |
| 110 | + pinctrl-single,pins = < | |
| 111 | + 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */ | |
| 112 | + 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */ | |
| 113 | + >; | |
| 114 | + }; | |
| 115 | + | |
| 116 | + mmc1_pins_default: mmc1_pins_default { | |
| 117 | + pinctrl-single,pins = < | |
| 118 | + 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ | |
| 119 | + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | |
| 120 | + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | |
| 121 | + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | |
| 122 | + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | |
| 123 | + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | |
| 124 | + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | |
| 125 | + >; | |
| 126 | + }; | |
| 127 | + | |
| 128 | + mmc2_pins_default: mmc2_pins_default { | |
| 129 | + pinctrl-single,pins = < | |
| 130 | + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | |
| 131 | + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | |
| 132 | + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | |
| 133 | + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | |
| 134 | + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | |
| 135 | + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | |
| 136 | + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | |
| 137 | + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | |
| 138 | + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | |
| 139 | + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | |
| 140 | + >; | |
| 141 | + }; | |
| 142 | + | |
| 143 | + tps659038_pins_default: tps659038_pins_default { | |
| 144 | + pinctrl-single,pins = < | |
| 145 | + 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ | |
| 146 | + >; | |
| 147 | + }; | |
| 148 | + | |
| 149 | + tmp102_pins_default: tmp102_pins_default { | |
| 150 | + pinctrl-single,pins = < | |
| 151 | + 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */ | |
| 152 | + >; | |
| 153 | + }; | |
| 154 | + | |
| 155 | + mcp79410_pins_default: mcp79410_pins_default { | |
| 156 | + pinctrl-single,pins = < | |
| 157 | + 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ | |
| 158 | + >; | |
| 159 | + }; | |
| 160 | + | |
| 161 | + usb1_pins: pinmux_usb1_pins { | |
| 162 | + pinctrl-single,pins = < | |
| 163 | + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ | |
| 164 | + >; | |
| 165 | + }; | |
| 166 | + | |
| 167 | +}; | |
| 168 | + | |
| 169 | +&i2c1 { | |
| 170 | + status = "okay"; | |
| 171 | + pinctrl-names = "default"; | |
| 172 | + pinctrl-0 = <&i2c1_pins_default>; | |
| 173 | + clock-frequency = <400000>; | |
| 174 | + | |
| 175 | + tps659038: tps659038@58 { | |
| 176 | + compatible = "ti,tps659038"; | |
| 177 | + reg = <0x58>; | |
| 178 | + interrupt-parent = <&gpio1>; | |
| 179 | + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | |
| 180 | + | |
| 181 | + pinctrl-names = "default"; | |
| 182 | + pinctrl-0 = <&tps659038_pins_default>; | |
| 183 | + | |
| 184 | + #interrupt-cells = <2>; | |
| 185 | + interrupt-controller; | |
| 186 | + | |
| 187 | + ti,system-power-controller; | |
| 188 | + | |
| 189 | + tps659038_pmic { | |
| 190 | + compatible = "ti,tps659038-pmic"; | |
| 191 | + | |
| 192 | + regulators { | |
| 193 | + smps12_reg: smps12 { | |
| 194 | + /* VDD_MPU */ | |
| 195 | + regulator-name = "smps12"; | |
| 196 | + regulator-min-microvolt = < 850000>; | |
| 197 | + regulator-max-microvolt = <1250000>; | |
| 198 | + regulator-always-on; | |
| 199 | + regulator-boot-on; | |
| 200 | + }; | |
| 201 | + | |
| 202 | + smps3_reg: smps3 { | |
| 203 | + /* VDD_DDR */ | |
| 204 | + regulator-name = "smps3"; | |
| 205 | + regulator-min-microvolt = <1350000>; | |
| 206 | + regulator-max-microvolt = <1350000>; | |
| 207 | + regulator-always-on; | |
| 208 | + regulator-boot-on; | |
| 209 | + }; | |
| 210 | + | |
| 211 | + smps45_reg: smps45 { | |
| 212 | + /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ | |
| 213 | + regulator-name = "smps45"; | |
| 214 | + regulator-min-microvolt = < 850000>; | |
| 215 | + regulator-max-microvolt = <1150000>; | |
| 216 | + regulator-always-on; | |
| 217 | + regulator-boot-on; | |
| 218 | + }; | |
| 219 | + | |
| 220 | + smps6_reg: smps6 { | |
| 221 | + /* VDD_CORE */ | |
| 222 | + regulator-name = "smps6"; | |
| 223 | + regulator-min-microvolt = <850000>; | |
| 224 | + regulator-max-microvolt = <1030000>; | |
| 225 | + regulator-always-on; | |
| 226 | + regulator-boot-on; | |
| 227 | + }; | |
| 228 | + | |
| 229 | + /* SMPS7 unused */ | |
| 230 | + | |
| 231 | + smps8_reg: smps8 { | |
| 232 | + /* VDD_1V8 */ | |
| 233 | + regulator-name = "smps8"; | |
| 234 | + regulator-min-microvolt = <1800000>; | |
| 235 | + regulator-max-microvolt = <1800000>; | |
| 236 | + regulator-always-on; | |
| 237 | + regulator-boot-on; | |
| 238 | + }; | |
| 239 | + | |
| 240 | + /* SMPS9 unused */ | |
| 241 | + | |
| 242 | + ldo1_reg: ldo1 { | |
| 243 | + /* VDD_SD */ | |
| 244 | + regulator-name = "ldo1"; | |
| 245 | + regulator-min-microvolt = <1800000>; | |
| 246 | + regulator-max-microvolt = <3300000>; | |
| 247 | + regulator-boot-on; | |
| 248 | + }; | |
| 249 | + | |
| 250 | + ldo2_reg: ldo2 { | |
| 251 | + /* VDD_SHV5 */ | |
| 252 | + regulator-name = "ldo2"; | |
| 253 | + regulator-min-microvolt = <3300000>; | |
| 254 | + regulator-max-microvolt = <3300000>; | |
| 255 | + regulator-always-on; | |
| 256 | + regulator-boot-on; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + ldo3_reg: ldo3 { | |
| 260 | + /* VDDA_1V8_PHY */ | |
| 261 | + regulator-name = "ldo3"; | |
| 262 | + regulator-min-microvolt = <1800000>; | |
| 263 | + regulator-max-microvolt = <1800000>; | |
| 264 | + regulator-always-on; | |
| 265 | + regulator-boot-on; | |
| 266 | + }; | |
| 267 | + | |
| 268 | + ldo9_reg: ldo9 { | |
| 269 | + /* VDD_RTC */ | |
| 270 | + regulator-name = "ldo9"; | |
| 271 | + regulator-min-microvolt = <1050000>; | |
| 272 | + regulator-max-microvolt = <1050000>; | |
| 273 | + regulator-always-on; | |
| 274 | + regulator-boot-on; | |
| 275 | + }; | |
| 276 | + | |
| 277 | + ldoln_reg: ldoln { | |
| 278 | + /* VDDA_1V8_PLL */ | |
| 279 | + regulator-name = "ldoln"; | |
| 280 | + regulator-min-microvolt = <1800000>; | |
| 281 | + regulator-max-microvolt = <1800000>; | |
| 282 | + regulator-always-on; | |
| 283 | + regulator-boot-on; | |
| 284 | + }; | |
| 285 | + | |
| 286 | + ldousb_reg: ldousb { | |
| 287 | + /* VDDA_3V_USB: VDDA_USBHS33 */ | |
| 288 | + regulator-name = "ldousb"; | |
| 289 | + regulator-min-microvolt = <3300000>; | |
| 290 | + regulator-max-microvolt = <3300000>; | |
| 291 | + regulator-boot-on; | |
| 292 | + }; | |
| 293 | + | |
| 294 | + regen1: regen1 { | |
| 295 | + /* VDD_3V3_ON */ | |
| 296 | + regulator-name = "regen1"; | |
| 297 | + regulator-boot-on; | |
| 298 | + regulator-always-on; | |
| 299 | + }; | |
| 300 | + }; | |
| 301 | + }; | |
| 302 | + | |
| 303 | + tps659038_rtc: tps659038_rtc { | |
| 304 | + compatible = "ti,palmas-rtc"; | |
| 305 | + interrupt-parent = <&tps659038>; | |
| 306 | + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; | |
| 307 | + wakeup-source; | |
| 308 | + }; | |
| 309 | + | |
| 310 | + tps659038_pwr_button: tps659038_pwr_button { | |
| 311 | + compatible = "ti,palmas-pwrbutton"; | |
| 312 | + interrupt-parent = <&tps659038>; | |
| 313 | + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; | |
| 314 | + wakeup-source; | |
| 315 | + ti,palmas-long-press-seconds = <12>; | |
| 316 | + }; | |
| 317 | + }; | |
| 318 | + | |
| 319 | + tmp102: tmp102@48 { | |
| 320 | + compatible = "ti,tmp102"; | |
| 321 | + reg = <0x48>; | |
| 322 | + pinctrl-names = "default"; | |
| 323 | + pinctrl-0 = <&tmp102_pins_default>; | |
| 324 | + interrupt-parent = <&gpio7>; | |
| 325 | + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; | |
| 326 | + }; | |
| 327 | +}; | |
| 328 | + | |
| 329 | +&i2c3 { | |
| 330 | + status = "okay"; | |
| 331 | + pinctrl-names = "default"; | |
| 332 | + pinctrl-0 = <&i2c3_pins_default>; | |
| 333 | + clock-frequency = <400000>; | |
| 334 | + | |
| 335 | + mcp_rtc: rtc@6f { | |
| 336 | + compatible = "microchip,mcp7941x"; | |
| 337 | + reg = <0x6f>; | |
| 338 | + interrupt-parent = <&gic>; | |
| 339 | + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */ | |
| 340 | + | |
| 341 | + pinctrl-names = "default"; | |
| 342 | + pinctrl-0 = <&mcp79410_pins_default>; | |
| 343 | + | |
| 344 | + vcc-supply = <&vdd_3v3>; | |
| 345 | + wakeup-source; | |
| 346 | + }; | |
| 347 | +}; | |
| 348 | + | |
| 349 | +&gpio7 { | |
| 350 | + ti,no-reset-on-init; | |
| 351 | + ti,no-idle-on-init; | |
| 352 | +}; | |
| 353 | + | |
| 354 | +&cpu0 { | |
| 355 | + cpu0-supply = <&smps12_reg>; | |
| 356 | + voltage-tolerance = <1>; | |
| 357 | +}; | |
| 358 | + | |
| 359 | +&uart3 { | |
| 360 | + status = "okay"; | |
| 361 | + interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, | |
| 362 | + <&dra7_pmx_core 0x248>; | |
| 363 | + | |
| 364 | + pinctrl-names = "default"; | |
| 365 | + pinctrl-0 = <&uart3_pins_default>; | |
| 366 | +}; | |
| 367 | + | |
| 368 | +&mmc1 { | |
| 369 | + status = "okay"; | |
| 370 | + | |
| 371 | + pinctrl-names = "default"; | |
| 372 | + pinctrl-0 = <&mmc1_pins_default>; | |
| 373 | + | |
| 374 | + vmmc-supply = <&ldo1_reg>; | |
| 375 | + vmmc_aux-supply = <&vdd_3v3>; | |
| 376 | + pbias-supply = <&pbias_mmc_reg>; | |
| 377 | + bus-width = <4>; | |
| 378 | + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ | |
| 379 | +}; | |
| 380 | + | |
| 381 | +&mmc2 { | |
| 382 | + status = "okay"; | |
| 383 | + | |
| 384 | + pinctrl-names = "default"; | |
| 385 | + pinctrl-0 = <&mmc2_pins_default>; | |
| 386 | + | |
| 387 | + vmmc-supply = <&vdd_3v3>; | |
| 388 | + bus-width = <8>; | |
| 389 | + ti,non-removable; | |
| 390 | + cap-mmc-dual-data-rate; | |
| 391 | +}; | |
| 392 | + | |
| 393 | +&sata { | |
| 394 | + status = "okay"; | |
| 395 | +}; | |
| 396 | + | |
| 397 | +&usb2_phy1 { | |
| 398 | + phy-supply = <&ldousb_reg>; | |
| 399 | +}; | |
| 400 | + | |
| 401 | +&usb1 { | |
| 402 | + dr_mode = "host"; | |
| 403 | + pinctrl-names = "default"; | |
| 404 | + pinctrl-0 = <&usb1_pins>; | |
| 405 | +}; | |
| @@ -0,0 +1,412 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2014 Linaro Ltd | |
| 3 | + * | |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 5 | + * of this software and associated documentation files (the "Software"), to deal | |
| 6 | + * in the Software without restriction, including without limitation the rights | |
| 7 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 8 | + * copies of the Software, and to permit persons to whom the Software is | |
| 9 | + * furnished to do so, subject to the following conditions: | |
| 10 | + * | |
| 11 | + * The above copyright notice and this permission notice shall be included in | |
| 12 | + * all copies or substantial portions of the Software. | |
| 13 | + * | |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 18 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 19 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 20 | + * THE SOFTWARE. | |
| 21 | + */ | |
| 22 | + | |
| 23 | +/dts-v1/; | |
| 24 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 25 | +#include <dt-bindings/gpio/gpio.h> | |
| 26 | +#include "skeleton.dtsi" | |
| 27 | + | |
| 28 | +/ { | |
| 29 | + model = "ARM RealView PB1176"; | |
| 30 | + compatible = "arm,realview-pb1176"; | |
| 31 | + | |
| 32 | + chosen { }; | |
| 33 | + | |
| 34 | + aliases { | |
| 35 | + serial0 = &pb1176_serial0; | |
| 36 | + serial1 = &pb1176_serial1; | |
| 37 | + serial2 = &pb1176_serial2; | |
| 38 | + serial3 = &pb1176_serial3; | |
| 39 | + serial4 = &fpga_serial; | |
| 40 | + }; | |
| 41 | + | |
| 42 | + memory { | |
| 43 | + /* 128 MiB memory @ 0x0 */ | |
| 44 | + reg = <0x00000000 0x08000000>; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + /* The voltage to the MMC card is hardwired at 3.3V */ | |
| 48 | + vmmc: fixedregulator@0 { | |
| 49 | + compatible = "regulator-fixed"; | |
| 50 | + regulator-name = "vmmc"; | |
| 51 | + regulator-min-microvolt = <3300000>; | |
| 52 | + regulator-max-microvolt = <3300000>; | |
| 53 | + regulator-boot-on; | |
| 54 | + }; | |
| 55 | + | |
| 56 | + xtal24mhz: xtal24mhz@24M { | |
| 57 | + #clock-cells = <0>; | |
| 58 | + compatible = "fixed-clock"; | |
| 59 | + clock-frequency = <24000000>; | |
| 60 | + }; | |
| 61 | + | |
| 62 | + timclk: timclk@1M { | |
| 63 | + #clock-cells = <0>; | |
| 64 | + compatible = "fixed-factor-clock"; | |
| 65 | + clock-div = <24>; | |
| 66 | + clock-mult = <1>; | |
| 67 | + clocks = <&xtal24mhz>; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + mclk: mclk@24M { | |
| 71 | + #clock-cells = <0>; | |
| 72 | + compatible = "fixed-factor-clock"; | |
| 73 | + clock-div = <1>; | |
| 74 | + clock-mult = <1>; | |
| 75 | + clocks = <&xtal24mhz>; | |
| 76 | + }; | |
| 77 | + | |
| 78 | + kmiclk: kmiclk@24M { | |
| 79 | + #clock-cells = <0>; | |
| 80 | + compatible = "fixed-factor-clock"; | |
| 81 | + clock-div = <1>; | |
| 82 | + clock-mult = <1>; | |
| 83 | + clocks = <&xtal24mhz>; | |
| 84 | + }; | |
| 85 | + | |
| 86 | + sspclk: sspclk@24M { | |
| 87 | + #clock-cells = <0>; | |
| 88 | + compatible = "fixed-factor-clock"; | |
| 89 | + clock-div = <1>; | |
| 90 | + clock-mult = <1>; | |
| 91 | + clocks = <&xtal24mhz>; | |
| 92 | + }; | |
| 93 | + | |
| 94 | + uartclk: uartclk@24M { | |
| 95 | + #clock-cells = <0>; | |
| 96 | + compatible = "fixed-factor-clock"; | |
| 97 | + clock-div = <1>; | |
| 98 | + clock-mult = <1>; | |
| 99 | + clocks = <&xtal24mhz>; | |
| 100 | + }; | |
| 101 | + | |
| 102 | + /* FIXME: this actually hangs off the PLL clocks */ | |
| 103 | + pclk: pclk@0 { | |
| 104 | + #clock-cells = <0>; | |
| 105 | + compatible = "fixed-clock"; | |
| 106 | + clock-frequency = <0>; | |
| 107 | + }; | |
| 108 | + | |
| 109 | + soc { | |
| 110 | + #address-cells = <1>; | |
| 111 | + #size-cells = <1>; | |
| 112 | + compatible = "arm,realview-pb1176-soc", "simple-bus"; | |
| 113 | + regmap = <&syscon>; | |
| 114 | + ranges; | |
| 115 | + | |
| 116 | + syscon: syscon@10000000 { | |
| 117 | + compatible = "arm,realview-pb1176-syscon", "syscon"; | |
| 118 | + reg = <0x10000000 0x1000>; | |
| 119 | + | |
| 120 | + led@08.0 { | |
| 121 | + compatible = "register-bit-led"; | |
| 122 | + offset = <0x08>; | |
| 123 | + mask = <0x01>; | |
| 124 | + label = "versatile:0"; | |
| 125 | + linux,default-trigger = "heartbeat"; | |
| 126 | + default-state = "on"; | |
| 127 | + }; | |
| 128 | + led@08.1 { | |
| 129 | + compatible = "register-bit-led"; | |
| 130 | + offset = <0x08>; | |
| 131 | + mask = <0x02>; | |
| 132 | + label = "versatile:1"; | |
| 133 | + linux,default-trigger = "mmc0"; | |
| 134 | + default-state = "off"; | |
| 135 | + }; | |
| 136 | + led@08.2 { | |
| 137 | + compatible = "register-bit-led"; | |
| 138 | + offset = <0x08>; | |
| 139 | + mask = <0x04>; | |
| 140 | + label = "versatile:2"; | |
| 141 | + linux,default-trigger = "cpu0"; | |
| 142 | + default-state = "off"; | |
| 143 | + }; | |
| 144 | + led@08.3 { | |
| 145 | + compatible = "register-bit-led"; | |
| 146 | + offset = <0x08>; | |
| 147 | + mask = <0x08>; | |
| 148 | + label = "versatile:3"; | |
| 149 | + default-state = "off"; | |
| 150 | + }; | |
| 151 | + led@08.4 { | |
| 152 | + compatible = "register-bit-led"; | |
| 153 | + offset = <0x08>; | |
| 154 | + mask = <0x10>; | |
| 155 | + label = "versatile:4"; | |
| 156 | + default-state = "off"; | |
| 157 | + }; | |
| 158 | + led@08.5 { | |
| 159 | + compatible = "register-bit-led"; | |
| 160 | + offset = <0x08>; | |
| 161 | + mask = <0x20>; | |
| 162 | + label = "versatile:5"; | |
| 163 | + default-state = "off"; | |
| 164 | + }; | |
| 165 | + led@08.6 { | |
| 166 | + compatible = "register-bit-led"; | |
| 167 | + offset = <0x08>; | |
| 168 | + mask = <0x40>; | |
| 169 | + label = "versatile:6"; | |
| 170 | + default-state = "off"; | |
| 171 | + }; | |
| 172 | + led@08.7 { | |
| 173 | + compatible = "register-bit-led"; | |
| 174 | + offset = <0x08>; | |
| 175 | + mask = <0x80>; | |
| 176 | + label = "versatile:7"; | |
| 177 | + default-state = "off"; | |
| 178 | + }; | |
| 179 | + }; | |
| 180 | + | |
| 181 | + /* Primary DevChip GIC synthesized with the CPU */ | |
| 182 | + intc_dc1176: interrupt-controller@10120000 { | |
| 183 | + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; | |
| 184 | + #interrupt-cells = <3>; | |
| 185 | + #address-cells = <1>; | |
| 186 | + interrupt-controller; | |
| 187 | + reg = <0x10121000 0x1000>, | |
| 188 | + <0x10120000 0x100>; | |
| 189 | + }; | |
| 190 | + | |
| 191 | + L2: l2-cache { | |
| 192 | + compatible = "arm,l220-cache"; | |
| 193 | + reg = <0x10110000 0x1000>; | |
| 194 | + interrupt-parent = <&intc_dc1176>; | |
| 195 | + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
| 196 | + cache-unified; | |
| 197 | + cache-level = <2>; | |
| 198 | + /* | |
| 199 | + * Override default cache size, sets and | |
| 200 | + * associativity as these may be erroneously set | |
| 201 | + * up by boot loader(s). | |
| 202 | + */ | |
| 203 | + arm,override-auxreg; | |
| 204 | + cache-size = <131072>; // 128kB | |
| 205 | + cache-sets = <512>; | |
| 206 | + cache-line-size = <32>; | |
| 207 | + }; | |
| 208 | + | |
| 209 | + pmu { | |
| 210 | + compatible = "arm,arm1176-pmu"; | |
| 211 | + interrupt-parent = <&intc_dc1176>; | |
| 212 | + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 213 | + }; | |
| 214 | + | |
| 215 | + timer01: timer@10104000 { | |
| 216 | + compatible = "arm,sp804", "arm,primecell"; | |
| 217 | + reg = <0x10104000 0x1000>; | |
| 218 | + interrupt-parent = <&intc_dc1176>; | |
| 219 | + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 220 | + clocks = <&timclk>, <&timclk>, <&pclk>; | |
| 221 | + clock-names = "timer1", "timer2", "apb_pclk"; | |
| 222 | + }; | |
| 223 | + | |
| 224 | + timer23: timer@10105000 { | |
| 225 | + compatible = "arm,sp804", "arm,primecell"; | |
| 226 | + reg = <0x10105000 0x1000>; | |
| 227 | + interrupt-parent = <&intc_dc1176>; | |
| 228 | + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 229 | + arm,sp804-has-irq = <1>; | |
| 230 | + clocks = <&timclk>, <&timclk>, <&pclk>; | |
| 231 | + clock-names = "timer1", "timer2", "apb_pclk"; | |
| 232 | + }; | |
| 233 | + | |
| 234 | + pb1176_rtc: rtc@10108000 { | |
| 235 | + compatible = "arm,pl031", "arm,primecell"; | |
| 236 | + reg = <0x10108000 0x1000>; | |
| 237 | + interrupt-parent = <&intc_dc1176>; | |
| 238 | + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 239 | + clocks = <&pclk>; | |
| 240 | + clock-names = "apb_pclk"; | |
| 241 | + }; | |
| 242 | + | |
| 243 | + pb1176_gpio0: gpio@1010a000 { | |
| 244 | + compatible = "arm,pl061", "arm,primecell"; | |
| 245 | + reg = <0x1010a000 0x1000>; | |
| 246 | + gpio-controller; | |
| 247 | + interrupt-parent = <&intc_dc1176>; | |
| 248 | + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 249 | + #gpio-cells = <2>; | |
| 250 | + interrupt-controller; | |
| 251 | + #interrupt-cells = <2>; | |
| 252 | + clocks = <&pclk>; | |
| 253 | + clock-names = "apb_pclk"; | |
| 254 | + }; | |
| 255 | + | |
| 256 | + pb1176_ssp: ssp@1010b000 { | |
| 257 | + compatible = "arm,pl022", "arm,primecell"; | |
| 258 | + reg = <0x1010b000 0x1000>; | |
| 259 | + interrupt-parent = <&intc_dc1176>; | |
| 260 | + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 261 | + clocks = <&sspclk>, <&pclk>; | |
| 262 | + clock-names = "SSPCLK", "apb_pclk"; | |
| 263 | + }; | |
| 264 | + | |
| 265 | + pb1176_serial0: serial@1010c000 { | |
| 266 | + compatible = "arm,pl011", "arm,primecell"; | |
| 267 | + reg = <0x1010c000 0x1000>; | |
| 268 | + interrupt-parent = <&intc_dc1176>; | |
| 269 | + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; | |
| 270 | + clocks = <&uartclk>, <&pclk>; | |
| 271 | + clock-names = "uartclk", "apb_pclk"; | |
| 272 | + }; | |
| 273 | + | |
| 274 | + pb1176_serial1: serial@1010d000 { | |
| 275 | + compatible = "arm,pl011", "arm,primecell"; | |
| 276 | + reg = <0x1010d000 0x1000>; | |
| 277 | + interrupt-parent = <&intc_dc1176>; | |
| 278 | + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | |
| 279 | + clocks = <&uartclk>, <&pclk>; | |
| 280 | + clock-names = "uartclk", "apb_pclk"; | |
| 281 | + }; | |
| 282 | + | |
| 283 | + pb1176_serial2: serial@1010e000 { | |
| 284 | + compatible = "arm,pl011", "arm,primecell"; | |
| 285 | + reg = <0x1010e000 0x1000>; | |
| 286 | + interrupt-parent = <&intc_dc1176>; | |
| 287 | + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 288 | + clocks = <&uartclk>, <&pclk>; | |
| 289 | + clock-names = "uartclk", "apb_pclk"; | |
| 290 | + }; | |
| 291 | + | |
| 292 | + pb1176_serial3: serial@1010f000 { | |
| 293 | + compatible = "arm,pl011", "arm,primecell"; | |
| 294 | + reg = <0x1010f000 0x1000>; | |
| 295 | + interrupt-parent = <&intc_dc1176>; | |
| 296 | + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
| 297 | + clocks = <&uartclk>, <&pclk>; | |
| 298 | + clock-names = "uartclk", "apb_pclk"; | |
| 299 | + }; | |
| 300 | + }; | |
| 301 | + | |
| 302 | + /* These peripherals are inside the FPGA rather than the DevChip */ | |
| 303 | + fpga { | |
| 304 | + #address-cells = <1>; | |
| 305 | + #size-cells = <1>; | |
| 306 | + compatible = "simple-bus"; | |
| 307 | + ranges; | |
| 308 | + | |
| 309 | + fpga_mci: mmcsd@10005000 { | |
| 310 | + compatible = "arm,pl18x", "arm,primecell"; | |
| 311 | + reg = <0x10005000 0x1000>; | |
| 312 | + interrupt-parent = <&intc_fpga1176>; | |
| 313 | + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 314 | + <0 2 IRQ_TYPE_LEVEL_HIGH>; | |
| 315 | + /* Due to frequent FIFO overruns, use just 500 kHz */ | |
| 316 | + max-frequency = <500000>; | |
| 317 | + bus-width = <4>; | |
| 318 | + cap-sd-highspeed; | |
| 319 | + cap-mmc-highspeed; | |
| 320 | + clocks = <&mclk>, <&pclk>; | |
| 321 | + clock-names = "mclk", "apb_pclk"; | |
| 322 | + vmmc-supply = <&vmmc>; | |
| 323 | + cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; | |
| 324 | + wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; | |
| 325 | + }; | |
| 326 | + | |
| 327 | + fpga_kmi0: kmi@10006000 { | |
| 328 | + compatible = "arm,pl050", "arm,primecell"; | |
| 329 | + reg = <0x10006000 0x1000>; | |
| 330 | + interrupt-parent = <&intc_fpga1176>; | |
| 331 | + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
| 332 | + clocks = <&kmiclk>, <&pclk>; | |
| 333 | + clock-names = "KMIREFCLK", "apb_pclk"; | |
| 334 | + }; | |
| 335 | + | |
| 336 | + fpga_kmi1: kmi@10007000 { | |
| 337 | + compatible = "arm,pl050", "arm,primecell"; | |
| 338 | + reg = <0x10007000 0x1000>; | |
| 339 | + interrupt-parent = <&intc_fpga1176>; | |
| 340 | + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; | |
| 341 | + clocks = <&kmiclk>, <&pclk>; | |
| 342 | + clock-names = "KMIREFCLK", "apb_pclk"; | |
| 343 | + }; | |
| 344 | + | |
| 345 | + fpga_charlcd: charlcd@10008000 { | |
| 346 | + compatible = "arm,versatile-lcd"; | |
| 347 | + reg = <0x10008000 0x1000>; | |
| 348 | + interrupt-parent = <&intc_fpga1176>; | |
| 349 | + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 350 | + clocks = <&pclk>; | |
| 351 | + clock-names = "apb_pclk"; | |
| 352 | + }; | |
| 353 | + | |
| 354 | + fpga_serial: serial@10009000 { | |
| 355 | + compatible = "arm,pl011", "arm,primecell"; | |
| 356 | + reg = <0x10009000 0x1000>; | |
| 357 | + interrupt-parent = <&intc_fpga1176>; | |
| 358 | + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 359 | + clocks = <&uartclk>, <&pclk>; | |
| 360 | + clock-names = "uartclk", "apb_pclk"; | |
| 361 | + }; | |
| 362 | + | |
| 363 | + /* This GIC on the board is cascaded off the DevChip GIC */ | |
| 364 | + intc_fpga1176: interrupt-controller@10040000 { | |
| 365 | + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; | |
| 366 | + #interrupt-cells = <3>; | |
| 367 | + #address-cells = <1>; | |
| 368 | + interrupt-controller; | |
| 369 | + reg = <0x10041000 0x1000>, | |
| 370 | + <0x10040000 0x100>; | |
| 371 | + interrupt-parent = <&intc_dc1176>; | |
| 372 | + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
| 373 | + }; | |
| 374 | + | |
| 375 | + fpga_gpio0: gpio@10014000 { | |
| 376 | + compatible = "arm,pl061", "arm,primecell"; | |
| 377 | + reg = <0x10014000 0x1000>; | |
| 378 | + gpio-controller; | |
| 379 | + interrupt-parent = <&intc_fpga1176>; | |
| 380 | + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 381 | + #gpio-cells = <2>; | |
| 382 | + interrupt-controller; | |
| 383 | + #interrupt-cells = <2>; | |
| 384 | + clocks = <&pclk>; | |
| 385 | + clock-names = "apb_pclk"; | |
| 386 | + }; | |
| 387 | + | |
| 388 | + fpga_gpio1: gpio@10015000 { | |
| 389 | + compatible = "arm,pl061", "arm,primecell"; | |
| 390 | + reg = <0x10015000 0x1000>; | |
| 391 | + gpio-controller; | |
| 392 | + interrupt-parent = <&intc_fpga1176>; | |
| 393 | + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 394 | + #gpio-cells = <2>; | |
| 395 | + interrupt-controller; | |
| 396 | + #interrupt-cells = <2>; | |
| 397 | + clocks = <&pclk>; | |
| 398 | + clock-names = "apb_pclk"; | |
| 399 | + }; | |
| 400 | + | |
| 401 | + fpga_rtc: rtc@10017000 { | |
| 402 | + compatible = "arm,pl031", "arm,primecell"; | |
| 403 | + reg = <0x10017000 0x1000>; | |
| 404 | + interrupt-parent = <&intc_fpga1176>; | |
| 405 | + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
| 406 | + clocks = <&pclk>; | |
| 407 | + clock-names = "apb_pclk"; | |
| 408 | + }; | |
| 409 | + | |
| 410 | + | |
| 411 | + }; | |
| 412 | +}; | |
| @@ -75,6 +75,7 @@ · 74 unmodified lines | ||
| 75 | 75 | clock-frequency = <100000>; |
| 76 | 76 | status = "okay"; |
| 77 | 77 | audio_codec: audio-codec@4a { |
| 78 | + #sound-dai-cells = <0>; | |
| 78 | 79 | compatible = "cirrus,cs42l51"; |
| 79 | 80 | reg = <0x4a>; |
| 80 | 81 | }; |
| @@ -102,30 +103,6 @@ · 21 unmodified lines | ||
| 102 | 103 | broken-cd; |
| 103 | 104 | }; |
| 104 | 105 | |
| 105 | − pinctrl { | |
| 106 | − /* | |
| 107 | − * These pins might be muxed as I2S by | |
| 108 | − * the bootloader, but it conflicts | |
| 109 | − * with the real I2S pins that are | |
| 110 | − * muxed using i2s_pins. We must mux | |
| 111 | − * those pins to a function other than | |
| 112 | − * I2S. | |
| 113 | − */ | |
| 114 | − pinctrl-0 = <&hog_pins1 &hog_pins2>; | |
| 115 | − pinctrl-names = "default"; | |
| 116 | − | |
| 117 | − hog_pins1: hog-pins1 { | |
| 118 | − marvell,pins = "mpp6", "mpp8", "mpp10", | |
| 119 | − "mpp12", "mpp13"; | |
| 120 | − marvell,function = "gpio"; | |
| 121 | − }; | |
| 122 | − | |
| 123 | − hog_pins2: hog-pins2 { | |
| 124 | − marvell,pins = "mpp5", "mpp7", "mpp9"; | |
| 125 | − marvell,function = "gpo"; | |
| 126 | − }; | |
| 127 | − }; | |
| 128 | − | |
| 129 | 106 | usb@50000 { |
| 130 | 107 | status = "okay"; |
| 131 | 108 | }; |
| @@ -135,6 +112,8 @@ · 3 unmodified lines | ||
| 135 | 112 | }; |
| 136 | 113 | |
| 137 | 114 | spi0: spi@10600 { |
| 115 | + pinctrl-0 = <&spi0_pins2>; | |
| 116 | + pinctrl-names = "default"; | |
| 138 | 117 | status = "okay"; |
| 139 | 118 | |
| 140 | 119 | spi-flash@0 { |
| @@ -167,17 +146,84 @@ · 26 unmodified lines | ||
| 167 | 146 | }; |
| 168 | 147 | |
| 169 | 148 | sound { |
| 170 | − compatible = "marvell,a370db-audio"; | |
| 171 | − marvell,audio-controller = <&audio_controller>; | |
| 172 | − marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>; | |
| 173 | − status = "okay"; | |
| 149 | + compatible = "simple-audio-card"; | |
| 150 | + simple-audio-card,name = "Armada 370 DB Audio"; | |
| 151 | + simple-audio-card,mclk-fs = <256>; | |
| 152 | + simple-audio-card,widgets = | |
| 153 | + "Headphone", "Out Jack", | |
| 154 | + "Line", "In Jack"; | |
| 155 | + simple-audio-card,routing = | |
| 156 | + "Out Jack", "HPL", | |
| 157 | + "Out Jack", "HPR", | |
| 158 | + "AIN1L", "In Jack", | |
| 159 | + "AIN1L", "In Jack"; | |
| 160 | + status = "okay"; | |
| 161 | + | |
| 162 | + simple-audio-card,dai-link@0 { | |
| 163 | + format = "i2s"; | |
| 164 | + cpu { | |
| 165 | + sound-dai = <&audio_controller 0>; | |
| 166 | + }; | |
| 167 | + | |
| 168 | + codec { | |
| 169 | + sound-dai = <&audio_codec>; | |
| 170 | + }; | |
| 171 | + }; | |
| 172 | + | |
| 173 | + simple-audio-card,dai-link@1 { | |
| 174 | + format = "i2s"; | |
| 175 | + cpu { | |
| 176 | + sound-dai = <&audio_controller 1>; | |
| 177 | + }; | |
| 178 | + | |
| 179 | + codec { | |
| 180 | + sound-dai = <&spdif_out>; | |
| 181 | + }; | |
| 182 | + }; | |
| 183 | + | |
| 184 | + simple-audio-card,dai-link@2 { | |
| 185 | + format = "i2s"; | |
| 186 | + cpu { | |
| 187 | + sound-dai = <&audio_controller 1>; | |
| 188 | + }; | |
| 189 | + | |
| 190 | + codec { | |
| 191 | + sound-dai = <&spdif_in>; | |
| 192 | + }; | |
| 193 | + }; | |
| 174 | 194 | }; |
| 175 | 195 | |
| 176 | 196 | spdif_out: spdif-out { |
| 177 | − compatible = "linux,spdif-dit"; | |
| 197 | + #sound-dai-cells = <0>; | |
| 198 | + compatible = "linux,spdif-dit"; | |
| 178 | 199 | }; |
| 179 | 200 | |
| 180 | 201 | spdif_in: spdif-in { |
| 181 | − compatible = "linux,spdif-dir"; | |
| 202 | + #sound-dai-cells = <0>; | |
| 203 | + compatible = "linux,spdif-dir"; | |
| 204 | + }; | |
| 205 | +}; | |
| 206 | + | |
| 207 | +&pinctrl { | |
| 208 | + /* | |
| 209 | + * These pins might be muxed as I2S by | |
| 210 | + * the bootloader, but it conflicts | |
| 211 | + * with the real I2S pins that are | |
| 212 | + * muxed using i2s_pins. We must mux | |
| 213 | + * those pins to a function other than | |
| 214 | + * I2S. | |
| 215 | + */ | |
| 216 | + pinctrl-0 = <&hog_pins1 &hog_pins2>; | |
| 217 | + pinctrl-names = "default"; | |
| 218 | + | |
| 219 | + hog_pins1: hog-pins1 { | |
| 220 | + marvell,pins = "mpp6", "mpp8", "mpp10", | |
| 221 | + "mpp12", "mpp13"; | |
| 222 | + marvell,function = "gpio"; | |
| 223 | + }; | |
| 224 | + | |
| 225 | + hog_pins2: hog-pins2 { | |
| 226 | + marvell,pins = "mpp5", "mpp7", "mpp9"; | |
| 227 | + marvell,function = "gpo"; | |
| 182 | 228 | }; |
| 183 | 229 | }; |
| @@ -54,18 +54,6 @@ · 53 unmodified lines | ||
| 54 | 54 | status = "okay"; |
| 55 | 55 | }; |
| 56 | 56 | |
| 57 | − pinctrl { | |
| 58 | − pwr_led_pin: pwr-led-pin { | |
| 59 | − marvell,pins = "mpp63"; | |
| 60 | − marvell,function = "gpo"; | |
| 61 | − }; | |
| 62 | − | |
| 63 | − stat_led_pins: stat-led-pins { | |
| 64 | − marvell,pins = "mpp64", "mpp65"; | |
| 65 | − marvell,function = "gpio"; | |
| 66 | − }; | |
| 67 | − }; | |
| 68 | − | |
| 69 | 57 | gpio_leds { |
| 70 | 58 | compatible = "gpio-leds"; |
| 71 | 59 | pinctrl-names = "default"; |
| @@ -169,3 +157,16 @@ · 97 unmodified lines | ||
| 169 | 157 | }; |
| 170 | 158 | }; |
| 171 | 159 | }; |
| 160 | + | |
| 161 | +&pinctrl { | |
| 162 | + pwr_led_pin: pwr-led-pin { | |
| 163 | + marvell,pins = "mpp63"; | |
| 164 | + marvell,function = "gpo"; | |
| 165 | + }; | |
| 166 | + | |
| 167 | + stat_led_pins: stat-led-pins { | |
| 168 | + marvell,pins = "mpp64", "mpp65"; | |
| 169 | + marvell,function = "gpio"; | |
| 170 | + }; | |
| 171 | +}; | |
| 172 | + | |
| @@ -35,7 +35,7 @@ · 34 unmodified lines | ||
| 35 | 35 | pcie-controller { |
| 36 | 36 | status = "okay"; |
| 37 | 37 | |
| 38 | − /* Connected to Marvell SATA controller */ | |
| 38 | + /* Connected to Marvell 88SE9170 SATA controller */ | |
| 39 | 39 | pcie@1,0 { |
| 40 | 40 | /* Port 0, Lane 0 */ |
| 41 | 41 | status = "okay"; |
| @@ -53,53 +53,12 @@ · 11 unmodified lines | ||
| 53 | 53 | status = "okay"; |
| 54 | 54 | }; |
| 55 | 55 | |
| 56 | + /* eSATA interface */ | |
| 56 | 57 | sata@a0000 { |
| 57 | − nr-ports = <2>; | |
| 58 | + nr-ports = <1>; | |
| 58 | 59 | status = "okay"; |
| 59 | 60 | }; |
| 60 | 61 | |
| 61 | − pinctrl { | |
| 62 | − power_led_pin: power-led-pin { | |
| 63 | − marvell,pins = "mpp57"; | |
| 64 | − marvell,function = "gpio"; | |
| 65 | − }; | |
| 66 | − | |
| 67 | − sata1_led_pin: sata1-led-pin { | |
| 68 | − marvell,pins = "mpp15"; | |
| 69 | − marvell,function = "gpio"; | |
| 70 | − }; | |
| 71 | − | |
| 72 | − sata2_led_pin: sata2-led-pin { | |
| 73 | − marvell,pins = "mpp14"; | |
| 74 | − marvell,function = "gpio"; | |
| 75 | − }; | |
| 76 | − | |
| 77 | − backup_led_pin: backup-led-pin { | |
| 78 | − marvell,pins = "mpp56"; | |
| 79 | − marvell,function = "gpio"; | |
| 80 | − }; | |
| 81 | − | |
| 82 | − backup_button_pin: backup-button-pin { | |
| 83 | − marvell,pins = "mpp58"; | |
| 84 | − marvell,function = "gpio"; | |
| 85 | − }; | |
| 86 | − | |
| 87 | − power_button_pin: power-button-pin { | |
| 88 | − marvell,pins = "mpp62"; | |
| 89 | − marvell,function = "gpio"; | |
| 90 | − }; | |
| 91 | − | |
| 92 | − reset_button_pin: reset-button-pin { | |
| 93 | − marvell,pins = "mpp6"; | |
| 94 | − marvell,function = "gpio"; | |
| 95 | − }; | |
| 96 | − | |
| 97 | − poweroff: poweroff { | |
| 98 | − marvell,pins = "mpp8"; | |
| 99 | − marvell,function = "gpio"; | |
| 100 | − }; | |
| 101 | − }; | |
| 102 | − | |
| 103 | 62 | mdio { |
| 104 | 63 | pinctrl-0 = <&mdio_pins>; |
| 105 | 64 | pinctrl-names = "default"; |
| @@ -204,20 +163,20 @@ · 98 unmodified lines | ||
| 204 | 163 | default-state = "keep"; |
| 205 | 164 | }; |
| 206 | 165 | |
| 207 | − green-sata1-led { | |
| 208 | − label = "rn102:green:sata1"; | |
| 166 | + blue-sata1-led { | |
| 167 | + label = "rn102:blue:sata1"; | |
| 209 | 168 | gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; |
| 210 | 169 | default-state = "on"; |
| 211 | 170 | }; |
| 212 | 171 | |
| 213 | − green-sata2-led { | |
| 214 | − label = "rn102:green:sata2"; | |
| 172 | + blue-sata2-led { | |
| 173 | + label = "rn102:blue:sata2"; | |
| 215 | 174 | gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; |
| 216 | 175 | default-state = "on"; |
| 217 | 176 | }; |
| 218 | 177 | |
| 219 | − green-backup-led { | |
| 220 | − label = "rn102:green:backup"; | |
| 178 | + blue-backup-led { | |
| 179 | + label = "rn102:blue:backup"; | |
| 221 | 180 | gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; |
| 222 | 181 | default-state = "on"; |
| 223 | 182 | }; |
| @@ -256,3 +215,45 @@ · 32 unmodified lines | ||
| 256 | 215 | gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; |
| 257 | 216 | }; |
| 258 | 217 | }; |
| 218 | + | |
| 219 | +&pinctrl { | |
| 220 | + power_led_pin: power-led-pin { | |
| 221 | + marvell,pins = "mpp57"; | |
| 222 | + marvell,function = "gpio"; | |
| 223 | + }; | |
| 224 | + | |
| 225 | + sata1_led_pin: sata1-led-pin { | |
| 226 | + marvell,pins = "mpp15"; | |
| 227 | + marvell,function = "gpio"; | |
| 228 | + }; | |
| 229 | + | |
| 230 | + sata2_led_pin: sata2-led-pin { | |
| 231 | + marvell,pins = "mpp14"; | |
| 232 | + marvell,function = "gpio"; | |
| 233 | + }; | |
| 234 | + | |
| 235 | + backup_led_pin: backup-led-pin { | |
| 236 | + marvell,pins = "mpp56"; | |
| 237 | + marvell,function = "gpio"; | |
| 238 | + }; | |
| 239 | + | |
| 240 | + backup_button_pin: backup-button-pin { | |
| 241 | + marvell,pins = "mpp58"; | |
| 242 | + marvell,function = "gpio"; | |
| 243 | + }; | |
| 244 | + | |
| 245 | + power_button_pin: power-button-pin { | |
| 246 | + marvell,pins = "mpp62"; | |
| 247 | + marvell,function = "gpio"; | |
| 248 | + }; | |
| 249 | + | |
| 250 | + reset_button_pin: reset-button-pin { | |
| 251 | + marvell,pins = "mpp6"; | |
| 252 | + marvell,function = "gpio"; | |
| 253 | + }; | |
| 254 | + | |
| 255 | + poweroff: poweroff { | |
| 256 | + marvell,pins = "mpp8"; | |
| 257 | + marvell,function = "gpio"; | |
| 258 | + }; | |
| 259 | +}; | |
| @@ -53,38 +53,6 @@ · 52 unmodified lines | ||
| 53 | 53 | status = "okay"; |
| 54 | 54 | }; |
| 55 | 55 | |
| 56 | − pinctrl { | |
| 57 | − poweroff: poweroff { | |
| 58 | − marvell,pins = "mpp60"; | |
| 59 | − marvell,function = "gpio"; | |
| 60 | − }; | |
| 61 | − | |
| 62 | − backup_button_pin: backup-button-pin { | |
| 63 | − marvell,pins = "mpp52"; | |
| 64 | − marvell,function = "gpio"; | |
| 65 | − }; | |
| 66 | − | |
| 67 | − power_button_pin: power-button-pin { | |
| 68 | − marvell,pins = "mpp62"; | |
| 69 | − marvell,function = "gpio"; | |
| 70 | − }; | |
| 71 | − | |
| 72 | − backup_led_pin: backup-led-pin { | |
| 73 | − marvell,pins = "mpp63"; | |
| 74 | − marvell,function = "gpo"; | |
| 75 | − }; | |
| 76 | − | |
| 77 | − power_led_pin: power-led-pin { | |
| 78 | − marvell,pins = "mpp64"; | |
| 79 | − marvell,function = "gpio"; | |
| 80 | − }; | |
| 81 | − | |
| 82 | − reset_button_pin: reset-button-pin { | |
| 83 | − marvell,pins = "mpp65"; | |
| 84 | − marvell,function = "gpio"; | |
| 85 | − }; | |
| 86 | − }; | |
| 87 | − | |
| 88 | 56 | mdio { |
| 89 | 57 | pinctrl-0 = <&mdio_pins>; |
| 90 | 58 | pinctrl-names = "default"; |
| @@ -269,3 +237,35 @@ · 178 unmodified lines | ||
| 269 | 237 | gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; |
| 270 | 238 | }; |
| 271 | 239 | }; |
| 240 | + | |
| 241 | +&pinctrl { | |
| 242 | + poweroff: poweroff { | |
| 243 | + marvell,pins = "mpp60"; | |
| 244 | + marvell,function = "gpio"; | |
| 245 | + }; | |
| 246 | + | |
| 247 | + backup_button_pin: backup-button-pin { | |
| 248 | + marvell,pins = "mpp52"; | |
| 249 | + marvell,function = "gpio"; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + power_button_pin: power-button-pin { | |
| 253 | + marvell,pins = "mpp62"; | |
| 254 | + marvell,function = "gpio"; | |
| 255 | + }; | |
| 256 | + | |
| 257 | + backup_led_pin: backup-led-pin { | |
| 258 | + marvell,pins = "mpp63"; | |
| 259 | + marvell,function = "gpo"; | |
| 260 | + }; | |
| 261 | + | |
| 262 | + power_led_pin: power-led-pin { | |
| 263 | + marvell,pins = "mpp64"; | |
| 264 | + marvell,function = "gpio"; | |
| 265 | + }; | |
| 266 | + | |
| 267 | + reset_button_pin: reset-button-pin { | |
| 268 | + marvell,pins = "mpp65"; | |
| 269 | + marvell,function = "gpio"; | |
| 270 | + }; | |
| 271 | +}; | |
| @@ -59,18 +59,6 @@ · 58 unmodified lines | ||
| 59 | 59 | }; |
| 60 | 60 | |
| 61 | 61 | internal-regs { |
| 62 | − pinctrl { | |
| 63 | − fan_pins: fan-pins { | |
| 64 | − marvell,pins = "mpp8"; | |
| 65 | − marvell,function = "gpio"; | |
| 66 | − }; | |
| 67 | − | |
| 68 | − led_pins: led-pins { | |
| 69 | − marvell,pins = "mpp32"; | |
| 70 | − marvell,function = "gpio"; | |
| 71 | − }; | |
| 72 | − }; | |
| 73 | − | |
| 74 | 62 | serial@12000 { |
| 75 | 63 | status = "okay"; |
| 76 | 64 | }; |
| @@ -85,10 +73,6 @@ · 8 unmodified lines | ||
| 85 | 73 | phy0: ethernet-phy@0 { |
| 86 | 74 | reg = <0>; |
| 87 | 75 | }; |
| 88 | − | |
| 89 | − phy1: ethernet-phy@1 { | |
| 90 | − reg = <1>; | |
| 91 | − }; | |
| 92 | 76 | }; |
| 93 | 77 | |
| 94 | 78 | ethernet@70000 { |
| @@ -100,8 +84,11 @@ · 5 unmodified lines | ||
| 100 | 84 | pinctrl-0 = <&ge1_rgmii_pins>; |
| 101 | 85 | pinctrl-names = "default"; |
| 102 | 86 | status = "okay"; |
| 103 | − phy = <&phy1>; | |
| 104 | 87 | phy-mode = "rgmii-id"; |
| 88 | + fixed-link { | |
| 89 | + speed = <1000>; | |
| 90 | + full-duplex; | |
| 91 | + }; | |
| 105 | 92 | }; |
| 106 | 93 | |
| 107 | 94 | mvsdio@d4000 { |
| @@ -173,4 +160,56 @@ · 65 unmodified lines | ||
| 173 | 160 | }; |
| 174 | 161 | }; |
| 175 | 162 | }; |
| 163 | + | |
| 164 | + dsa@0 { | |
| 165 | + compatible = "marvell,dsa"; | |
| 166 | + #address-cells = <2>; | |
| 167 | + #size-cells = <0>; | |
| 168 | + | |
| 169 | + dsa,ethernet = <ð1>; | |
| 170 | + dsa,mii-bus = <&mdio>; | |
| 171 | + | |
| 172 | + switch@0 { | |
| 173 | + #address-cells = <1>; | |
| 174 | + #size-cells = <0>; | |
| 175 | + reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */ | |
| 176 | + | |
| 177 | + port@0 { | |
| 178 | + reg = <0>; | |
| 179 | + label = "lan0"; | |
| 180 | + }; | |
| 181 | + | |
| 182 | + port@1 { | |
| 183 | + reg = <1>; | |
| 184 | + label = "lan1"; | |
| 185 | + }; | |
| 186 | + | |
| 187 | + port@2 { | |
| 188 | + reg = <2>; | |
| 189 | + label = "lan2"; | |
| 190 | + }; | |
| 191 | + | |
| 192 | + port@3 { | |
| 193 | + reg = <3>; | |
| 194 | + label = "lan3"; | |
| 195 | + }; | |
| 196 | + | |
| 197 | + port@5 { | |
| 198 | + reg = <5>; | |
| 199 | + label = "cpu"; | |
| 200 | + }; | |
| 201 | + }; | |
| 202 | + }; | |
| 176 | 203 | }; |
| 204 | + | |
| 205 | +&pinctrl { | |
| 206 | + fan_pins: fan-pins { | |
| 207 | + marvell,pins = "mpp8"; | |
| 208 | + marvell,function = "gpio"; | |
| 209 | + }; | |
| 210 | + | |
| 211 | + led_pins: led-pins { | |
| 212 | + marvell,pins = "mpp32"; | |
| 213 | + marvell,function = "gpio"; | |
| 214 | + }; | |
| 215 | +}; | |
| @@ -0,0 +1,316 @@ | ||
| 1 | +/* | |
| 2 | + * Device Tree file for Synology DS213j | |
| 3 | + * | |
| 4 | + * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> | |
| 5 | + * | |
| 6 | + * This program is free software; you can redistribute it and/or | |
| 7 | + * modify it under the terms of the GNU General Public License | |
| 8 | + * as published by the Free Software Foundation; either version | |
| 9 | + * 2 of the License, or (at your option) any later version. | |
| 10 | + * | |
| 11 | + * Note: this Device Tree assumes that the bootloader has remapped the | |
| 12 | + * internal registers to 0xf1000000 (instead of the old 0xd0000000). | |
| 13 | + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot | |
| 14 | + * bootloaders provided by Marvell. It is used in recent versions of | |
| 15 | + * DSM software provided by Synology. Nonetheless, some earlier boards | |
| 16 | + * were delivered with an older version of u-boot that left internal | |
| 17 | + * registers mapped at 0xd0000000. If you have such a device you will | |
| 18 | + * not be able to directly boot a kernel based on this Device Tree. In | |
| 19 | + * that case, the preferred solution is to update your bootloader (e.g. | |
| 20 | + * by upgrading to latest version of DSM, or building a new one and | |
| 21 | + * installing it from u-boot prompt) or adjust the Devive Tree | |
| 22 | + * (s/0xf1000000/0xd0000000/ in 'ranges' below). | |
| 23 | + */ | |
| 24 | + | |
| 25 | +/dts-v1/; | |
| 26 | + | |
| 27 | +#include <dt-bindings/input/input.h> | |
| 28 | +#include <dt-bindings/gpio/gpio.h> | |
| 29 | +#include "armada-370.dtsi" | |
| 30 | + | |
| 31 | +/ { | |
| 32 | + model = "Synology DS213j"; | |
| 33 | + compatible = "synology,ds213j", "marvell,armada370", | |
| 34 | + "marvell,armada-370-xp"; | |
| 35 | + | |
| 36 | + chosen { | |
| 37 | + bootargs = "console=ttyS0,115200 earlyprintk"; | |
| 38 | + stdout-path = &uart0; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + memory { | |
| 42 | + device_type = "memory"; | |
| 43 | + reg = <0x00000000 0x20000000>; /* 512 MB */ | |
| 44 | + }; | |
| 45 | + | |
| 46 | + soc { | |
| 47 | + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | |
| 48 | + MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; | |
| 49 | + | |
| 50 | + internal-regs { | |
| 51 | + | |
| 52 | + /* RTC provided by Seiko S-35390A I2C RTC chip below */ | |
| 53 | + rtc@10300 { | |
| 54 | + status = "disabled"; | |
| 55 | + }; | |
| 56 | + | |
| 57 | + spi0: spi@10600 { | |
| 58 | + status = "okay"; | |
| 59 | + | |
| 60 | + spi-flash@0 { | |
| 61 | + #address-cells = <1>; | |
| 62 | + #size-cells = <1>; | |
| 63 | + compatible = "micron,n25q064"; | |
| 64 | + reg = <0>; /* Chip select 0 */ | |
| 65 | + spi-max-frequency = <20000000>; | |
| 66 | + | |
| 67 | + /* | |
| 68 | + * Warning! | |
| 69 | + * | |
| 70 | + * Synology u-boot uses its compiled-in environment | |
| 71 | + * and it seems Synology did not care to change u-boot | |
| 72 | + * default configuration in order to allow saving a | |
| 73 | + * modified environment at a sensible location. So, | |
| 74 | + * if you do a 'saveenv' under u-boot, your modified | |
| 75 | + * environment will be saved at 1MB after the start | |
| 76 | + * of the flash, i.e. in the middle of the uImage. | |
| 77 | + * For that reason, it is strongly advised not to | |
| 78 | + * change the default environment, unless you know | |
| 79 | + * what you are doing. | |
| 80 | + */ | |
| 81 | + partition@00000000 { /* u-boot */ | |
| 82 | + label = "RedBoot"; | |
| 83 | + reg = <0x00000000 0x000c0000>; /* 768KB */ | |
| 84 | + }; | |
| 85 | + | |
| 86 | + partition@000c0000 { /* uImage */ | |
| 87 | + label = "zImage"; | |
| 88 | + reg = <0x000c0000 0x002d0000>; /* 2880KB */ | |
| 89 | + }; | |
| 90 | + | |
| 91 | + partition@00390000 { /* uInitramfs */ | |
| 92 | + label = "rd.gz"; | |
| 93 | + reg = <0x00390000 0x00440000>; /* 4250KB */ | |
| 94 | + }; | |
| 95 | + | |
| 96 | + partition@007d0000 { /* MAC address and serial number */ | |
| 97 | + label = "vendor"; | |
| 98 | + reg = <0x007d0000 0x00010000>; /* 64KB */ | |
| 99 | + }; | |
| 100 | + | |
| 101 | + partition@007e0000 { | |
| 102 | + label = "RedBoot config"; | |
| 103 | + reg = <0x007e0000 0x00010000>; /* 64KB */ | |
| 104 | + }; | |
| 105 | + | |
| 106 | + partition@007f0000 { | |
| 107 | + label = "FIS directory"; | |
| 108 | + reg = <0x007f0000 0x00010000>; /* 64KB */ | |
| 109 | + }; | |
| 110 | + }; | |
| 111 | + }; | |
| 112 | + | |
| 113 | + i2c@11000 { | |
| 114 | + compatible = "marvell,mv64xxx-i2c"; | |
| 115 | + pinctrl-0 = <&i2c0_pins>; | |
| 116 | + pinctrl-names = "default"; | |
| 117 | + clock-frequency = <400000>; | |
| 118 | + status = "okay"; | |
| 119 | + | |
| 120 | + /* Main device RTC chip */ | |
| 121 | + s35390a: s35390a@30 { | |
| 122 | + compatible = "sii,s35390a"; | |
| 123 | + reg = <0x30>; | |
| 124 | + }; | |
| 125 | + }; | |
| 126 | + | |
| 127 | + /* Connected to a header on device's PCB */ | |
| 128 | + serial@12000 { | |
| 129 | + status = "okay"; | |
| 130 | + }; | |
| 131 | + | |
| 132 | + /* Connected to a TI MSP430F2111 for power control */ | |
| 133 | + serial@12100 { | |
| 134 | + status = "okay"; | |
| 135 | + }; | |
| 136 | + | |
| 137 | + poweroff@12100 { | |
| 138 | + compatible = "synology,power-off"; | |
| 139 | + reg = <0x12100 0x100>; | |
| 140 | + clocks = <&coreclk 0>; | |
| 141 | + }; | |
| 142 | + | |
| 143 | + /* rear USB port, near reset button */ | |
| 144 | + usb@50000 { | |
| 145 | + status = "okay"; | |
| 146 | + }; | |
| 147 | + | |
| 148 | + /* rear USB port, near RJ45 port */ | |
| 149 | + usb@51000 { | |
| 150 | + status = "okay"; | |
| 151 | + }; | |
| 152 | + | |
| 153 | + mdio { | |
| 154 | + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ | |
| 155 | + reg = <1>; | |
| 156 | + }; | |
| 157 | + }; | |
| 158 | + | |
| 159 | + ethernet@70000 { | |
| 160 | + status = "okay"; | |
| 161 | + phy = <&phy1>; | |
| 162 | + phy-mode = "sgmii"; | |
| 163 | + }; | |
| 164 | + | |
| 165 | + sata@a0000 { | |
| 166 | + nr-ports = <2>; | |
| 167 | + status = "okay"; | |
| 168 | + }; | |
| 169 | + }; | |
| 170 | + }; | |
| 171 | + | |
| 172 | + gpio-fan-32-38 { | |
| 173 | + status = "okay"; | |
| 174 | + compatible = "gpio-fan"; | |
| 175 | + pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin | |
| 176 | + &fan_ctrl_high_pin &fan_alarm_pin>; | |
| 177 | + pinctrl-names = "default"; | |
| 178 | + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH | |
| 179 | + &gpio2 0 GPIO_ACTIVE_HIGH | |
| 180 | + &gpio2 1 GPIO_ACTIVE_HIGH>; | |
| 181 | + alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; | |
| 182 | + gpio-fan,speed-map = < 0 0 | |
| 183 | + 1000 1 | |
| 184 | + 1150 2 | |
| 185 | + 1350 4 | |
| 186 | + 1500 3 | |
| 187 | + 1650 5 | |
| 188 | + 1750 6 | |
| 189 | + 1900 7 >; | |
| 190 | + }; | |
| 191 | + | |
| 192 | + gpio-leds { | |
| 193 | + compatible = "gpio-leds"; | |
| 194 | + pinctrl-0 = <&disk1_led_pin | |
| 195 | + &disk2_led_pin>; | |
| 196 | + pinctrl-names = "default"; | |
| 197 | + | |
| 198 | + disk1-led-amber { | |
| 199 | + label = "synology:amber:disk1"; | |
| 200 | + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; | |
| 201 | + default-state = "keep"; | |
| 202 | + }; | |
| 203 | + | |
| 204 | + disk2-led-amber { | |
| 205 | + label = "synology:amber:disk2"; | |
| 206 | + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; | |
| 207 | + default-state = "keep"; | |
| 208 | + }; | |
| 209 | + }; | |
| 210 | + | |
| 211 | + regulators { | |
| 212 | + compatible = "simple-bus"; | |
| 213 | + #address-cells = <1>; | |
| 214 | + #size-cells = <0>; | |
| 215 | + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; | |
| 216 | + pinctrl-names = "default"; | |
| 217 | + | |
| 218 | + sata1_regulator: sata1-regulator { | |
| 219 | + compatible = "regulator-fixed"; | |
| 220 | + reg = <1>; | |
| 221 | + regulator-name = "SATA1 Power"; | |
| 222 | + regulator-min-microvolt = <5000000>; | |
| 223 | + regulator-max-microvolt = <5000000>; | |
| 224 | + startup-delay-us = <2000000>; | |
| 225 | + enable-active-high; | |
| 226 | + regulator-always-on; | |
| 227 | + regulator-boot-on; | |
| 228 | + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; | |
| 229 | + }; | |
| 230 | + | |
| 231 | + sata2_regulator: sata2-regulator { | |
| 232 | + compatible = "regulator-fixed"; | |
| 233 | + reg = <2>; | |
| 234 | + regulator-name = "SATA2 Power"; | |
| 235 | + regulator-min-microvolt = <5000000>; | |
| 236 | + regulator-max-microvolt = <5000000>; | |
| 237 | + startup-delay-us = <4000000>; | |
| 238 | + enable-active-high; | |
| 239 | + regulator-always-on; | |
| 240 | + regulator-boot-on; | |
| 241 | + gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; | |
| 242 | + }; | |
| 243 | + }; | |
| 244 | +}; | |
| 245 | + | |
| 246 | +&pinctrl { | |
| 247 | + disk1_led_pin: disk1-led-pin { | |
| 248 | + marvell,pins = "mpp31"; | |
| 249 | + marvell,function = "gpio"; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + disk2_led_pin: disk2-led-pin { | |
| 253 | + marvell,pins = "mpp32"; | |
| 254 | + marvell,function = "gpio"; | |
| 255 | + }; | |
| 256 | + | |
| 257 | + sata1_pwr_pin: sata1-pwr-pin { | |
| 258 | + marvell,pins = "mpp37"; | |
| 259 | + marvell,function = "gpio"; | |
| 260 | + }; | |
| 261 | + | |
| 262 | + sata2_pwr_pin: sata2-pwr-pin { | |
| 263 | + marvell,pins = "mpp62"; | |
| 264 | + marvell,function = "gpio"; | |
| 265 | + }; | |
| 266 | + | |
| 267 | + sata1_pres_pin: sata1-pres-pin { | |
| 268 | + marvell,pins = "mpp60"; | |
| 269 | + marvell,function = "gpio"; | |
| 270 | + }; | |
| 271 | + | |
| 272 | + sata2_pres_pin: sata2-pres-pin { | |
| 273 | + marvell,pins = "mpp48"; | |
| 274 | + marvell,function = "gpio"; | |
| 275 | + }; | |
| 276 | + | |
| 277 | + syno_id_bit0_pin: syno-id-bit0-pin { | |
| 278 | + marvell,pins = "mpp55"; | |
| 279 | + marvell,function = "gpio"; | |
| 280 | + }; | |
| 281 | + | |
| 282 | + syno_id_bit1_pin: syno-id-bit1-pin { | |
| 283 | + marvell,pins = "mpp56"; | |
| 284 | + marvell,function = "gpio"; | |
| 285 | + }; | |
| 286 | + | |
| 287 | + syno_id_bit2_pin: syno-id-bit2-pin { | |
| 288 | + marvell,pins = "mpp57"; | |
| 289 | + marvell,function = "gpio"; | |
| 290 | + }; | |
| 291 | + | |
| 292 | + syno_id_bit3_pin: syno-id-bit3-pin { | |
| 293 | + marvell,pins = "mpp58"; | |
| 294 | + marvell,function = "gpio"; | |
| 295 | + }; | |
| 296 | + | |
| 297 | + fan_ctrl_low_pin: fan-ctrl-low-pin { | |
| 298 | + marvell,pins = "mpp65"; | |
| 299 | + marvell,function = "gpio"; | |
| 300 | + }; | |
| 301 | + | |
| 302 | + fan_ctrl_mid_pin: fan-ctrl-mid-pin { | |
| 303 | + marvell,pins = "mpp64"; | |
| 304 | + marvell,function = "gpio"; | |
| 305 | + }; | |
| 306 | + | |
| 307 | + fan_ctrl_high_pin: fan-ctrl-high-pin { | |
| 308 | + marvell,pins = "mpp63"; | |
| 309 | + marvell,function = "gpo"; | |
| 310 | + }; | |
| 311 | + | |
| 312 | + fan_alarm_pin: fan-alarm-pin { | |
| 313 | + marvell,pins = "mpp38"; | |
| 314 | + marvell,function = "gpio"; | |
| 315 | + }; | |
| 316 | +}; | |
| @@ -151,7 +151,7 @@ · 150 unmodified lines | ||
| 151 | 151 | status = "disabled"; |
| 152 | 152 | }; |
| 153 | 153 | |
| 154 | − serial@12000 { | |
| 154 | + uart0: serial@12000 { | |
| 155 | 155 | compatible = "snps,dw-apb-uart"; |
| 156 | 156 | reg = <0x12000 0x100>; |
| 157 | 157 | reg-shift = <2>; |
| @@ -160,7 +160,8 @@ · 2 unmodified lines | ||
| 160 | 160 | clocks = <&coreclk 0>; |
| 161 | 161 | status = "disabled"; |
| 162 | 162 | }; |
| 163 | − serial@12100 { | |
| 163 | + | |
| 164 | + uart1: serial@12100 { | |
| 164 | 165 | compatible = "snps,dw-apb-uart"; |
| 165 | 166 | reg = <0x12100 0x100>; |
| 166 | 167 | reg-shift = <2>; |
| @@ -170,6 +171,10 @@ · 3 unmodified lines | ||
| 170 | 171 | status = "disabled"; |
| 171 | 172 | }; |
| 172 | 173 | |
| 174 | + pinctrl: pin-ctrl@18000 { | |
| 175 | + reg = <0x18000 0x38>; | |
| 176 | + }; | |
| 177 | + | |
| 173 | 178 | coredivclk: corediv-clock@18740 { |
| 174 | 179 | compatible = "marvell,armada-370-corediv-clock"; |
| 175 | 180 | reg = <0x18740 0xc>; |
| @@ -180,7 +185,8 @@ · 4 unmodified lines | ||
| 180 | 185 | |
| 181 | 186 | mbusc: mbus-controller@20000 { |
| 182 | 187 | compatible = "marvell,mbus-controller"; |
| 183 | − reg = <0x20000 0x100>, <0x20180 0x20>; | |
| 188 | + reg = <0x20000 0x100>, <0x20180 0x20>, | |
| 189 | + <0x20250 0x8>; | |
| 184 | 190 | }; |
| 185 | 191 | |
| 186 | 192 | mpic: interrupt-controller@20000 { |
| @@ -232,7 +238,7 @@ · 45 unmodified lines | ||
| 232 | 238 | status = "disabled"; |
| 233 | 239 | }; |
| 234 | 240 | |
| 235 | − mdio { | |
| 241 | + mdio: mdio { | |
| 236 | 242 | #address-cells = <1>; |
| 237 | 243 | #size-cells = <0>; |
| 238 | 244 | compatible = "marvell,orion-mdio"; |
| @@ -95,81 +95,30 @@ · 94 unmodified lines | ||
| 95 | 95 | compatible = "marvell,aurora-outer-cache"; |
| 96 | 96 | reg = <0x08000 0x1000>; |
| 97 | 97 | cache-id-part = <0x100>; |
| 98 | + cache-unified; | |
| 98 | 99 | wt-override; |
| 99 | 100 | }; |
| 100 | 101 | |
| 101 | − i2c0: i2c@11000 { | |
| 102 | − reg = <0x11000 0x20>; | |
| 102 | + /* | |
| 103 | + * Default SPI pinctrl setting, can be overwritten on | |
| 104 | + * board level if a different configuration is used. | |
| 105 | + */ | |
| 106 | + spi0: spi@10600 { | |
| 107 | + pinctrl-0 = <&spi0_pins1>; | |
| 108 | + pinctrl-names = "default"; | |
| 103 | 109 | }; |
| 104 | 110 | |
| 105 | − i2c1: i2c@11100 { | |
| 106 | − reg = <0x11100 0x20>; | |
| 111 | + spi1: spi@10680 { | |
| 112 | + pinctrl-0 = <&spi1_pins>; | |
| 113 | + pinctrl-names = "default"; | |
| 107 | 114 | }; |
| 108 | 115 | |
| 109 | − system-controller@18200 { | |
| 110 | − compatible = "marvell,armada-370-xp-system-controller"; | |
| 111 | − reg = <0x18200 0x100>; | |
| 116 | + i2c0: i2c@11000 { | |
| 117 | + reg = <0x11000 0x20>; | |
| 112 | 118 | }; |
| 113 | 119 | |
| 114 | − pinctrl { | |
| 115 | − compatible = "marvell,mv88f6710-pinctrl"; | |
| 116 | − reg = <0x18000 0x38>; | |
| 117 | − | |
| 118 | − sdio_pins1: sdio-pins1 { | |
| 119 | − marvell,pins = "mpp9", "mpp11", "mpp12", | |
| 120 | − "mpp13", "mpp14", "mpp15"; | |
| 121 | − marvell,function = "sd0"; | |
| 122 | − }; | |
| 123 | − | |
| 124 | − sdio_pins2: sdio-pins2 { | |
| 125 | − marvell,pins = "mpp47", "mpp48", "mpp49", | |
| 126 | − "mpp50", "mpp51", "mpp52"; | |
| 127 | − marvell,function = "sd0"; | |
| 128 | − }; | |
| 129 | − | |
| 130 | − sdio_pins3: sdio-pins3 { | |
| 131 | − marvell,pins = "mpp48", "mpp49", "mpp50", | |
| 132 | − "mpp51", "mpp52", "mpp53"; | |
| 133 | − marvell,function = "sd0"; | |
| 134 | − }; | |
| 135 | − | |
| 136 | − i2c0_pins: i2c0-pins { | |
| 137 | − marvell,pins = "mpp2", "mpp3"; | |
| 138 | − marvell,function = "i2c0"; | |
| 139 | − }; | |
| 140 | − | |
| 141 | − i2s_pins1: i2s-pins1 { | |
| 142 | − marvell,pins = "mpp5", "mpp6", "mpp7", | |
| 143 | − "mpp8", "mpp9", "mpp10", | |
| 144 | − "mpp12", "mpp13"; | |
| 145 | − marvell,function = "audio"; | |
| 146 | − }; | |
| 147 | − | |
| 148 | − i2s_pins2: i2s-pins2 { | |
| 149 | − marvell,pins = "mpp49", "mpp47", "mpp50", | |
| 150 | − "mpp59", "mpp57", "mpp61", | |
| 151 | − "mpp62", "mpp60", "mpp58"; | |
| 152 | − marvell,function = "audio"; | |
| 153 | − }; | |
| 154 | − | |
| 155 | − mdio_pins: mdio-pins { | |
| 156 | − marvell,pins = "mpp17", "mpp18"; | |
| 157 | − marvell,function = "ge"; | |
| 158 | − }; | |
| 159 | − | |
| 160 | − ge0_rgmii_pins: ge0-rgmii-pins { | |
| 161 | − marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", | |
| 162 | − "mpp9", "mpp10", "mpp11", "mpp12", | |
| 163 | − "mpp13", "mpp14", "mpp15", "mpp16"; | |
| 164 | − marvell,function = "ge0"; | |
| 165 | − }; | |
| 166 | − | |
| 167 | − ge1_rgmii_pins: ge1-rgmii-pins { | |
| 168 | − marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", | |
| 169 | − "mpp23", "mpp24", "mpp25", "mpp26", | |
| 170 | − "mpp27", "mpp28", "mpp29", "mpp30"; | |
| 171 | − marvell,function = "ge1"; | |
| 172 | − }; | |
| 120 | + i2c1: i2c@11100 { | |
| 121 | + reg = <0x11100 0x20>; | |
| 173 | 122 | }; |
| 174 | 123 | |
| 175 | 124 | gpio0: gpio@18100 { |
| @@ -205,6 +154,26 @@ · 29 unmodified lines | ||
| 205 | 154 | interrupts = <91>; |
| 206 | 155 | }; |
| 207 | 156 | |
| 157 | + /* | |
| 158 | + * Default UART pinctrl setting without RTS/CTS, can | |
| 159 | + * be overwritten on board level if a different | |
| 160 | + * configuration is used. | |
| 161 | + */ | |
| 162 | + uart0: serial@12000 { | |
| 163 | + pinctrl-0 = <&uart0_pins>; | |
| 164 | + pinctrl-names = "default"; | |
| 165 | + }; | |
| 166 | + | |
| 167 | + uart1: serial@12100 { | |
| 168 | + pinctrl-0 = <&uart1_pins>; | |
| 169 | + pinctrl-names = "default"; | |
| 170 | + }; | |
| 171 | + | |
| 172 | + system-controller@18200 { | |
| 173 | + compatible = "marvell,armada-370-xp-system-controller"; | |
| 174 | + reg = <0x18200 0x100>; | |
| 175 | + }; | |
| 176 | + | |
| 208 | 177 | gateclk: clock-gating-control@18220 { |
| 209 | 178 | compatible = "marvell,armada-370-gating-clock"; |
| 210 | 179 | reg = <0x18220 0x4>; |
| @@ -249,6 +218,7 @@ · 38 unmodified lines | ||
| 249 | 218 | }; |
| 250 | 219 | |
| 251 | 220 | audio_controller: audio-controller@30000 { |
| 221 | + #sound-dai-cells = <1>; | |
| 252 | 222 | compatible = "marvell,armada370-audio"; |
| 253 | 223 | reg = <0x30000 0x4000>; |
| 254 | 224 | interrupts = <93>; |
| @@ -305,3 +275,91 @@ · 50 unmodified lines | ||
| 305 | 275 | }; |
| 306 | 276 | }; |
| 307 | 277 | }; |
| 278 | + | |
| 279 | +&pinctrl { | |
| 280 | + compatible = "marvell,mv88f6710-pinctrl"; | |
| 281 | + | |
| 282 | + spi0_pins1: spi0-pins1 { | |
| 283 | + marvell,pins = "mpp33", "mpp34", | |
| 284 | + "mpp35", "mpp36"; | |
| 285 | + marvell,function = "spi0"; | |
| 286 | + }; | |
| 287 | + | |
| 288 | + spi0_pins2: spi0_pins2 { | |
| 289 | + marvell,pins = "mpp32", "mpp63", | |
| 290 | + "mpp64", "mpp65"; | |
| 291 | + marvell,function = "spi0"; | |
| 292 | + }; | |
| 293 | + | |
| 294 | + spi1_pins: spi1-pins { | |
| 295 | + marvell,pins = "mpp49", "mpp50", | |
| 296 | + "mpp51", "mpp52"; | |
| 297 | + marvell,function = "spi1"; | |
| 298 | + }; | |
| 299 | + | |
| 300 | + uart0_pins: uart0-pins { | |
| 301 | + marvell,pins = "mpp0", "mpp1"; | |
| 302 | + marvell,function = "uart0"; | |
| 303 | + }; | |
| 304 | + | |
| 305 | + uart1_pins: uart1-pins { | |
| 306 | + marvell,pins = "mpp41", "mpp42"; | |
| 307 | + marvell,function = "uart1"; | |
| 308 | + }; | |
| 309 | + | |
| 310 | + sdio_pins1: sdio-pins1 { | |
| 311 | + marvell,pins = "mpp9", "mpp11", "mpp12", | |
| 312 | + "mpp13", "mpp14", "mpp15"; | |
| 313 | + marvell,function = "sd0"; | |
| 314 | + }; | |
| 315 | + | |
| 316 | + sdio_pins2: sdio-pins2 { | |
| 317 | + marvell,pins = "mpp47", "mpp48", "mpp49", | |
| 318 | + "mpp50", "mpp51", "mpp52"; | |
| 319 | + marvell,function = "sd0"; | |
| 320 | + }; | |
| 321 | + | |
| 322 | + sdio_pins3: sdio-pins3 { | |
| 323 | + marvell,pins = "mpp48", "mpp49", "mpp50", | |
| 324 | + "mpp51", "mpp52", "mpp53"; | |
| 325 | + marvell,function = "sd0"; | |
| 326 | + }; | |
| 327 | + | |
| 328 | + i2c0_pins: i2c0-pins { | |
| 329 | + marvell,pins = "mpp2", "mpp3"; | |
| 330 | + marvell,function = "i2c0"; | |
| 331 | + }; | |
| 332 | + | |
| 333 | + i2s_pins1: i2s-pins1 { | |
| 334 | + marvell,pins = "mpp5", "mpp6", "mpp7", | |
| 335 | + "mpp8", "mpp9", "mpp10", | |
| 336 | + "mpp12", "mpp13"; | |
| 337 | + marvell,function = "audio"; | |
| 338 | + }; | |
| 339 | + | |
| 340 | + i2s_pins2: i2s-pins2 { | |
| 341 | + marvell,pins = "mpp49", "mpp47", "mpp50", | |
| 342 | + "mpp59", "mpp57", "mpp61", | |
| 343 | + "mpp62", "mpp60", "mpp58"; | |
| 344 | + marvell,function = "audio"; | |
| 345 | + }; | |
| 346 | + | |
| 347 | + mdio_pins: mdio-pins { | |
| 348 | + marvell,pins = "mpp17", "mpp18"; | |
| 349 | + marvell,function = "ge"; | |
| 350 | + }; | |
| 351 | + | |
| 352 | + ge0_rgmii_pins: ge0-rgmii-pins { | |
| 353 | + marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", | |
| 354 | + "mpp9", "mpp10", "mpp11", "mpp12", | |
| 355 | + "mpp13", "mpp14", "mpp15", "mpp16"; | |
| 356 | + marvell,function = "ge0"; | |
| 357 | + }; | |
| 358 | + | |
| 359 | + ge1_rgmii_pins: ge1-rgmii-pins { | |
| 360 | + marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", | |
| 361 | + "mpp23", "mpp24", "mpp25", "mpp26", | |
| 362 | + "mpp27", "mpp28", "mpp29", "mpp30"; | |
| 363 | + marvell,function = "ge1"; | |
| 364 | + }; | |
| 365 | +}; | |
| @@ -36,6 +36,12 @@ · 35 unmodified lines | ||
| 36 | 36 | #clock-cells = <0>; |
| 37 | 37 | clock-frequency = <2000000000>; |
| 38 | 38 | }; |
| 39 | + /* 25 MHz reference crystal */ | |
| 40 | + refclk: oscillator { | |
| 41 | + compatible = "fixed-clock"; | |
| 42 | + #clock-cells = <0>; | |
| 43 | + clock-frequency = <25000000>; | |
| 44 | + }; | |
| 39 | 45 | }; |
| 40 | 46 | |
| 41 | 47 | cpus { |
| @@ -366,13 +372,15 @@ · 324 unmodified lines | ||
| 366 | 372 | <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| 367 | 373 | <&mpic 5>, |
| 368 | 374 | <&mpic 6>; |
| 369 | − clocks = <&coreclk 0>; | |
| 375 | + clocks = <&coreclk 0>, <&refclk>; | |
| 376 | + clock-names = "nbclk", "fixed"; | |
| 370 | 377 | }; |
| 371 | 378 | |
| 372 | 379 | watchdog@20300 { |
| 373 | 380 | compatible = "marvell,armada-375-wdt"; |
| 374 | 381 | reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; |
| 375 | − clocks = <&coreclk 0>; | |
| 382 | + clocks = <&coreclk 0>, <&refclk>; | |
| 383 | + clock-names = "nbclk", "fixed"; | |
| 376 | 384 | }; |
| 377 | 385 | |
| 378 | 386 | cpurst@20800 { |
| @@ -116,11 +116,11 @@ · 115 unmodified lines | ||
| 116 | 116 | }; |
| 117 | 117 | |
| 118 | 118 | sdhci@d8000 { |
| 119 | − clock-frequency = <200000000>; | |
| 120 | 119 | broken-cd; |
| 121 | 120 | wp-inverted; |
| 122 | 121 | bus-width = <8>; |
| 123 | 122 | status = "okay"; |
| 123 | + no-1-8-v; | |
| 124 | 124 | }; |
| 125 | 125 | |
| 126 | 126 | usb3@f0000 { |
| @@ -25,9 +25,9 @@ · 24 unmodified lines | ||
| 25 | 25 | aliases { |
| 26 | 26 | gpio0 = &gpio0; |
| 27 | 27 | gpio1 = &gpio1; |
| 28 | − eth0 = ð0; | |
| 29 | − eth1 = ð1; | |
| 30 | − eth2 = ð2; | |
| 28 | + ethernet0 = ð0; | |
| 29 | + ethernet1 = ð1; | |
| 30 | + ethernet2 = ð2; | |
| 31 | 31 | }; |
| 32 | 32 | |
| 33 | 33 | soc { |
| @@ -60,40 +60,6 @@ · 59 unmodified lines | ||
| 60 | 60 | }; |
| 61 | 61 | |
| 62 | 62 | internal-regs { |
| 63 | − pinctrl { | |
| 64 | − pinctrl-0 = <&pmx_phy_int>; | |
| 65 | − pinctrl-names = "default"; | |
| 66 | − | |
| 67 | − pmx_ge0: pmx-ge0 { | |
| 68 | − marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | |
| 69 | − "mpp4", "mpp5", "mpp6", "mpp7", | |
| 70 | − "mpp8", "mpp9", "mpp10", "mpp11"; | |
| 71 | − marvell,function = "ge0"; | |
| 72 | − }; | |
| 73 | − | |
| 74 | − pmx_ge1: pmx-ge1 { | |
| 75 | − marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", | |
| 76 | − "mpp16", "mpp17", "mpp18", "mpp19", | |
| 77 | − "mpp20", "mpp21", "mpp22", "mpp23"; | |
| 78 | − marvell,function = "ge1"; | |
| 79 | − }; | |
| 80 | − | |
| 81 | − pmx_keys: pmx-keys { | |
| 82 | − marvell,pins = "mpp33"; | |
| 83 | − marvell,function = "gpio"; | |
| 84 | − }; | |
| 85 | − | |
| 86 | − pmx_spi: pmx-spi { | |
| 87 | − marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; | |
| 88 | − marvell,function = "spi"; | |
| 89 | − }; | |
| 90 | − | |
| 91 | − pmx_phy_int: pmx-phy-int { | |
| 92 | − marvell,pins = "mpp32"; | |
| 93 | − marvell,function = "gpio"; | |
| 94 | − }; | |
| 95 | − }; | |
| 96 | − | |
| 97 | 63 | serial@12000 { |
| 98 | 64 | status = "okay"; |
| 99 | 65 | }; |
| @@ -118,14 +84,14 @@ · 18 unmodified lines | ||
| 118 | 84 | }; |
| 119 | 85 | |
| 120 | 86 | ethernet@70000 { |
| 121 | − pinctrl-0 = <&pmx_ge0>; | |
| 87 | + pinctrl-0 = <&ge0_rgmii_pins>; | |
| 122 | 88 | pinctrl-names = "default"; |
| 123 | 89 | status = "okay"; |
| 124 | 90 | phy = <&phy0>; |
| 125 | 91 | phy-mode = "rgmii-id"; |
| 126 | 92 | }; |
| 127 | 93 | ethernet@74000 { |
| 128 | − pinctrl-0 = <&pmx_ge1>; | |
| 94 | + pinctrl-0 = <&ge1_rgmii_pins>; | |
| 129 | 95 | pinctrl-names = "default"; |
| 130 | 96 | status = "okay"; |
| 131 | 97 | phy = <&phy1>; |
| @@ -134,8 +100,6 @@ · 2 unmodified lines | ||
| 134 | 100 | |
| 135 | 101 | spi0: spi@10600 { |
| 136 | 102 | status = "okay"; |
| 137 | − pinctrl-0 = <&pmx_spi>; | |
| 138 | − pinctrl-names = "default"; | |
| 139 | 103 | |
| 140 | 104 | spi-flash@0 { |
| 141 | 105 | #address-cells = <1>; |
| @@ -152,7 +116,7 @@ · 10 unmodified lines | ||
| 152 | 116 | compatible = "gpio-keys"; |
| 153 | 117 | #address-cells = <1>; |
| 154 | 118 | #size-cells = <0>; |
| 155 | − pinctrl-0 = <&pmx_keys>; | |
| 119 | + pinctrl-0 = <&keys_pin>; | |
| 156 | 120 | pinctrl-names = "default"; |
| 157 | 121 | |
| 158 | 122 | button@1 { |
| @@ -162,3 +126,18 @@ · 3 unmodified lines | ||
| 162 | 126 | }; |
| 163 | 127 | }; |
| 164 | 128 | }; |
| 129 | + | |
| 130 | +&pinctrl { | |
| 131 | + pinctrl-0 = <&phy_int_pin>; | |
| 132 | + pinctrl-names = "default"; | |
| 133 | + | |
| 134 | + keys_pin: keys-pin { | |
| 135 | + marvell,pins = "mpp33"; | |
| 136 | + marvell,function = "gpio"; | |
| 137 | + }; | |
| 138 | + | |
| 139 | + phy_int_pin: phy-int-pin { | |
| 140 | + marvell,pins = "mpp32"; | |
| 141 | + marvell,function = "gpio"; | |
| 142 | + }; | |
| 143 | +}; | |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | */ |
| 24 | 24 | |
| 25 | 25 | /dts-v1/; |
| 26 | +#include <dt-bindings/gpio/gpio.h> | |
| 26 | 27 | #include "armada-xp-mv78460.dtsi" |
| 27 | 28 | |
| 28 | 29 | / { |
| @@ -48,6 +49,14 @@ · 19 unmodified lines | ||
| 48 | 49 | <0x00000001 0x00000000 0x00000001 0x00000000>; |
| 49 | 50 | }; |
| 50 | 51 | |
| 52 | + cpus { | |
| 53 | + pm_pic { | |
| 54 | + ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, | |
| 55 | + <&gpio0 17 GPIO_ACTIVE_LOW>, | |
| 56 | + <&gpio0 18 GPIO_ACTIVE_LOW>; | |
| 57 | + }; | |
| 58 | + }; | |
| 59 | + | |
| 51 | 60 | soc { |
| 52 | 61 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
| 53 | 62 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
| @@ -115,7 +124,15 @@ · 61 unmodified lines | ||
| 115 | 124 | serial@12300 { |
| 116 | 125 | status = "okay"; |
| 117 | 126 | }; |
| 118 | − | |
| 127 | + pinctrl { | |
| 128 | + pinctrl-0 = <&pic_pins>; | |
| 129 | + pinctrl-names = "default"; | |
| 130 | + pic_pins: pic-pins-0 { | |
| 131 | + marvell,pins = "mpp16", "mpp17", | |
| 132 | + "mpp18"; | |
| 133 | + marvell,function = "gpio"; | |
| 134 | + }; | |
| 135 | + }; | |
| 119 | 136 | sata@a0000 { |
| 120 | 137 | nr-ports = <2>; |
| 121 | 138 | status = "okay"; |
| @@ -22,7 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | |
| 23 | 23 | chosen { |
| 24 | 24 | bootargs = "console=ttyS0,115200 earlyprintk"; |
| 25 | − stdout-path = "/soc/internal-regs/serial@12000"; | |
| 25 | + stdout-path = &uart0; | |
| 26 | 26 | }; |
| 27 | 27 | |
| 28 | 28 | memory { |
| @@ -51,37 +51,6 @@ · 22 unmodified lines | ||
| 51 | 51 | }; |
| 52 | 52 | |
| 53 | 53 | internal-regs { |
| 54 | − pinctrl { | |
| 55 | − poweroff_pin: poweroff-pin { | |
| 56 | − marvell,pins = "mpp24"; | |
| 57 | − marvell,function = "gpio"; | |
| 58 | − }; | |
| 59 | − | |
| 60 | − power_button_pin: power-button-pin { | |
| 61 | − marvell,pins = "mpp44"; | |
| 62 | − marvell,function = "gpio"; | |
| 63 | − }; | |
| 64 | − | |
| 65 | − reset_button_pin: reset-button-pin { | |
| 66 | − marvell,pins = "mpp45"; | |
| 67 | − marvell,function = "gpio"; | |
| 68 | − }; | |
| 69 | − select_button_pin: select-button-pin { | |
| 70 | − marvell,pins = "mpp41"; | |
| 71 | − marvell,function = "gpio"; | |
| 72 | − }; | |
| 73 | − | |
| 74 | − scroll_button_pin: scroll-button-pin { | |
| 75 | − marvell,pins = "mpp42"; | |
| 76 | − marvell,function = "gpio"; | |
| 77 | − }; | |
| 78 | − | |
| 79 | − hdd_led_pin: hdd-led-pin { | |
| 80 | − marvell,pins = "mpp26"; | |
| 81 | − marvell,function = "gpio"; | |
| 82 | − }; | |
| 83 | − }; | |
| 84 | − | |
| 85 | 54 | serial@12000 { |
| 86 | 55 | status = "okay"; |
| 87 | 56 | }; |
| @@ -97,12 +66,16 @@ · 9 unmodified lines | ||
| 97 | 66 | }; |
| 98 | 67 | |
| 99 | 68 | ethernet@70000 { |
| 69 | + pinctrl-0 = <&ge0_rgmii_pins>; | |
| 70 | + pinctrl-names = "default"; | |
| 100 | 71 | status = "okay"; |
| 101 | 72 | phy = <&phy0>; |
| 102 | 73 | phy-mode = "rgmii-id"; |
| 103 | 74 | }; |
| 104 | 75 | |
| 105 | 76 | ethernet@74000 { |
| 77 | + pinctrl-0 = <&ge1_rgmii_pins>; | |
| 78 | + pinctrl-names = "default"; | |
| 106 | 79 | status = "okay"; |
| 107 | 80 | phy = <&phy1>; |
| 108 | 81 | phy-mode = "rgmii-id"; |
| @@ -125,6 +98,11 @@ · 16 unmodified lines | ||
| 125 | 98 | reg = <0x2e>; |
| 126 | 99 | }; |
| 127 | 100 | |
| 101 | + eeprom@50 { | |
| 102 | + compatible = "atmel,24c64"; | |
| 103 | + reg = <0x50>; | |
| 104 | + }; | |
| 105 | + | |
| 128 | 106 | pcf8563@51 { |
| 129 | 107 | compatible = "nxp,pcf8563"; |
| 130 | 108 | reg = <0x51>; |
| @@ -226,7 +204,7 @@ · 95 unmodified lines | ||
| 226 | 204 | gpio-controller; |
| 227 | 205 | #gpio-cells = <2>; |
| 228 | 206 | reg = <0>; |
| 229 | − registers-number = <2>; | |
| 207 | + registers-number = <1>; | |
| 230 | 208 | spi-max-frequency = <100000>; |
| 231 | 209 | }; |
| 232 | 210 | }; |
| @@ -282,3 +260,34 @@ · 49 unmodified lines | ||
| 282 | 260 | gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; |
| 283 | 261 | }; |
| 284 | 262 | }; |
| 263 | + | |
| 264 | +&pinctrl { | |
| 265 | + poweroff_pin: poweroff-pin { | |
| 266 | + marvell,pins = "mpp24"; | |
| 267 | + marvell,function = "gpio"; | |
| 268 | + }; | |
| 269 | + | |
| 270 | + power_button_pin: power-button-pin { | |
| 271 | + marvell,pins = "mpp44"; | |
| 272 | + marvell,function = "gpio"; | |
| 273 | + }; | |
| 274 | + | |
| 275 | + reset_button_pin: reset-button-pin { | |
| 276 | + marvell,pins = "mpp45"; | |
| 277 | + marvell,function = "gpio"; | |
| 278 | + }; | |
| 279 | + select_button_pin: select-button-pin { | |
| 280 | + marvell,pins = "mpp41"; | |
| 281 | + marvell,function = "gpio"; | |
| 282 | + }; | |
| 283 | + | |
| 284 | + scroll_button_pin: scroll-button-pin { | |
| 285 | + marvell,pins = "mpp42"; | |
| 286 | + marvell,function = "gpio"; | |
| 287 | + }; | |
| 288 | + | |
| 289 | + hdd_led_pin: hdd-led-pin { | |
| 290 | + marvell,pins = "mpp26"; | |
| 291 | + marvell,function = "gpio"; | |
| 292 | + }; | |
| 293 | +}; | |
| @@ -167,17 +167,6 @@ · 166 unmodified lines | ||
| 167 | 167 | }; |
| 168 | 168 | |
| 169 | 169 | internal-regs { |
| 170 | − pinctrl { | |
| 171 | − compatible = "marvell,mv78230-pinctrl"; | |
| 172 | − reg = <0x18000 0x38>; | |
| 173 | − | |
| 174 | − sdio_pins: sdio-pins { | |
| 175 | − marvell,pins = "mpp30", "mpp31", "mpp32", | |
| 176 | − "mpp33", "mpp34", "mpp35"; | |
| 177 | − marvell,function = "sd0"; | |
| 178 | − }; | |
| 179 | − }; | |
| 180 | − | |
| 181 | 170 | gpio0: gpio@18100 { |
| 182 | 171 | compatible = "marvell,orion-gpio"; |
| 183 | 172 | reg = <0x18100 0x40>; |
| @@ -202,3 +191,7 @@ · 18 unmodified lines | ||
| 202 | 191 | }; |
| 203 | 192 | }; |
| 204 | 193 | }; |
| 194 | + | |
| 195 | +&pinctrl { | |
| 196 | + compatible = "marvell,mv78230-pinctrl"; | |
| 197 | +}; | |
| @@ -251,17 +251,6 @@ · 250 unmodified lines | ||
| 251 | 251 | }; |
| 252 | 252 | |
| 253 | 253 | internal-regs { |
| 254 | − pinctrl { | |
| 255 | − compatible = "marvell,mv78260-pinctrl"; | |
| 256 | − reg = <0x18000 0x38>; | |
| 257 | − | |
| 258 | − sdio_pins: sdio-pins { | |
| 259 | − marvell,pins = "mpp30", "mpp31", "mpp32", | |
| 260 | − "mpp33", "mpp34", "mpp35"; | |
| 261 | − marvell,function = "sd0"; | |
| 262 | − }; | |
| 263 | − }; | |
| 264 | − | |
| 265 | 254 | gpio0: gpio@18100 { |
| 266 | 255 | compatible = "marvell,orion-gpio"; |
| 267 | 256 | reg = <0x18100 0x40>; |
| @@ -305,3 +294,7 @@ · 37 unmodified lines | ||
| 305 | 294 | }; |
| 306 | 295 | }; |
| 307 | 296 | }; |
| 297 | + | |
| 298 | +&pinctrl { | |
| 299 | + compatible = "marvell,mv78260-pinctrl"; | |
| 300 | +}; | |
| @@ -289,17 +289,6 @@ · 288 unmodified lines | ||
| 289 | 289 | }; |
| 290 | 290 | |
| 291 | 291 | internal-regs { |
| 292 | − pinctrl { | |
| 293 | − compatible = "marvell,mv78460-pinctrl"; | |
| 294 | − reg = <0x18000 0x38>; | |
| 295 | − | |
| 296 | − sdio_pins: sdio-pins { | |
| 297 | − marvell,pins = "mpp30", "mpp31", "mpp32", | |
| 298 | − "mpp33", "mpp34", "mpp35"; | |
| 299 | − marvell,function = "sd0"; | |
| 300 | − }; | |
| 301 | − }; | |
| 302 | − | |
| 303 | 292 | gpio0: gpio@18100 { |
| 304 | 293 | compatible = "marvell,orion-gpio"; |
| 305 | 294 | reg = <0x18100 0x40>; |
| @@ -343,3 +332,7 @@ · 37 unmodified lines | ||
| 343 | 332 | }; |
| 344 | 333 | }; |
| 345 | 334 | }; |
| 335 | + | |
| 336 | +&pinctrl { | |
| 337 | + compatible = "marvell,mv78460-pinctrl"; | |
| 338 | +}; | |
| @@ -55,86 +55,10 @@ · 54 unmodified lines | ||
| 55 | 55 | }; |
| 56 | 56 | |
| 57 | 57 | internal-regs { |
| 58 | − pinctrl { | |
| 59 | − poweroff: poweroff { | |
| 60 | − marvell,pins = "mpp42"; | |
| 61 | − marvell,function = "gpio"; | |
| 62 | − }; | |
| 63 | − | |
| 64 | − power_button_pin: power-button-pin { | |
| 65 | − marvell,pins = "mpp27"; | |
| 66 | − marvell,function = "gpio"; | |
| 67 | − }; | |
| 68 | − | |
| 69 | − reset_button_pin: reset-button-pin { | |
| 70 | − marvell,pins = "mpp41"; | |
| 71 | − marvell,function = "gpio"; | |
| 72 | − }; | |
| 73 | − | |
| 74 | − sata1_led_pin: sata1-led-pin { | |
| 75 | − marvell,pins = "mpp31"; | |
| 76 | − marvell,function = "gpio"; | |
| 77 | − }; | |
| 78 | − | |
| 79 | − sata2_led_pin: sata2-led-pin { | |
| 80 | − marvell,pins = "mpp40"; | |
| 81 | − marvell,function = "gpio"; | |
| 82 | − }; | |
| 83 | − | |
| 84 | − sata3_led_pin: sata3-led-pin { | |
| 85 | − marvell,pins = "mpp44"; | |
| 86 | − marvell,function = "gpio"; | |
| 87 | − }; | |
| 88 | − | |
| 89 | − sata4_led_pin: sata4-led-pin { | |
| 90 | − marvell,pins = "mpp47"; | |
| 91 | − marvell,function = "gpio"; | |
| 92 | − }; | |
| 93 | − | |
| 94 | − sata1_power_pin: sata1-power-pin { | |
| 95 | − marvell,pins = "mpp24"; | |
| 96 | − marvell,function = "gpio"; | |
| 97 | − }; | |
| 98 | − | |
| 99 | − sata2_power_pin: sata2-power-pin { | |
| 100 | − marvell,pins = "mpp25"; | |
| 101 | − marvell,function = "gpio"; | |
| 102 | − }; | |
| 103 | − | |
| 104 | − sata3_power_pin: sata3-power-pin { | |
| 105 | − marvell,pins = "mpp26"; | |
| 106 | − marvell,function = "gpio"; | |
| 107 | − }; | |
| 108 | − | |
| 109 | − sata4_power_pin: sata4-power-pin { | |
| 110 | − marvell,pins = "mpp28"; | |
| 111 | − marvell,function = "gpio"; | |
| 112 | − }; | |
| 113 | − | |
| 114 | − sata1_pres_pin: sata1-pres-pin { | |
| 115 | − marvell,pins = "mpp32"; | |
| 116 | − marvell,function = "gpio"; | |
| 117 | − }; | |
| 118 | − | |
| 119 | − sata2_pres_pin: sata2-pres-pin { | |
| 120 | − marvell,pins = "mpp33"; | |
| 121 | − marvell,function = "gpio"; | |
| 122 | − }; | |
| 123 | − | |
| 124 | − sata3_pres_pin: sata3-pres-pin { | |
| 125 | − marvell,pins = "mpp34"; | |
| 126 | − marvell,function = "gpio"; | |
| 127 | − }; | |
| 128 | − | |
| 129 | − sata4_pres_pin: sata4-pres-pin { | |
| 130 | − marvell,pins = "mpp35"; | |
| 131 | − marvell,function = "gpio"; | |
| 132 | − }; | |
| 133 | − | |
| 134 | − err_led_pin: err-led-pin { | |
| 135 | − marvell,pins = "mpp45"; | |
| 136 | − marvell,function = "gpio"; | |
| 137 | − }; | |
| 58 | + /* Two rear eSATA ports */ | |
| 59 | + sata@a0000 { | |
| 60 | + nr-ports = <2>; | |
| 61 | + status = "okay"; | |
| 138 | 62 | }; |
| 139 | 63 | |
| 140 | 64 | serial@12000 { |
| @@ -328,3 +252,85 @@ · 187 unmodified lines | ||
| 328 | 252 | gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; |
| 329 | 253 | }; |
| 330 | 254 | }; |
| 255 | + | |
| 256 | +&pinctrl { | |
| 257 | + poweroff: poweroff { | |
| 258 | + marvell,pins = "mpp42"; | |
| 259 | + marvell,function = "gpio"; | |
| 260 | + }; | |
| 261 | + | |
| 262 | + power_button_pin: power-button-pin { | |
| 263 | + marvell,pins = "mpp27"; | |
| 264 | + marvell,function = "gpio"; | |
| 265 | + }; | |
| 266 | + | |
| 267 | + reset_button_pin: reset-button-pin { | |
| 268 | + marvell,pins = "mpp41"; | |
| 269 | + marvell,function = "gpio"; | |
| 270 | + }; | |
| 271 | + | |
| 272 | + sata1_led_pin: sata1-led-pin { | |
| 273 | + marvell,pins = "mpp31"; | |
| 274 | + marvell,function = "gpio"; | |
| 275 | + }; | |
| 276 | + | |
| 277 | + sata2_led_pin: sata2-led-pin { | |
| 278 | + marvell,pins = "mpp40"; | |
| 279 | + marvell,function = "gpio"; | |
| 280 | + }; | |
| 281 | + | |
| 282 | + sata3_led_pin: sata3-led-pin { | |
| 283 | + marvell,pins = "mpp44"; | |
| 284 | + marvell,function = "gpio"; | |
| 285 | + }; | |
| 286 | + | |
| 287 | + sata4_led_pin: sata4-led-pin { | |
| 288 | + marvell,pins = "mpp47"; | |
| 289 | + marvell,function = "gpio"; | |
| 290 | + }; | |
| 291 | + | |
| 292 | + sata1_power_pin: sata1-power-pin { | |
| 293 | + marvell,pins = "mpp24"; | |
| 294 | + marvell,function = "gpio"; | |
| 295 | + }; | |
| 296 | + | |
| 297 | + sata2_power_pin: sata2-power-pin { | |
| 298 | + marvell,pins = "mpp25"; | |
| 299 | + marvell,function = "gpio"; | |
| 300 | + }; | |
| 301 | + | |
| 302 | + sata3_power_pin: sata3-power-pin { | |
| 303 | + marvell,pins = "mpp26"; | |
| 304 | + marvell,function = "gpio"; | |
| 305 | + }; | |
| 306 | + | |
| 307 | + sata4_power_pin: sata4-power-pin { | |
| 308 | + marvell,pins = "mpp28"; | |
| 309 | + marvell,function = "gpio"; | |
| 310 | + }; | |
| 311 | + | |
| 312 | + sata1_pres_pin: sata1-pres-pin { | |
| 313 | + marvell,pins = "mpp32"; | |
| 314 | + marvell,function = "gpio"; | |
| 315 | + }; | |
| 316 | + | |
| 317 | + sata2_pres_pin: sata2-pres-pin { | |
| 318 | + marvell,pins = "mpp33"; | |
| 319 | + marvell,function = "gpio"; | |
| 320 | + }; | |
| 321 | + | |
| 322 | + sata3_pres_pin: sata3-pres-pin { | |
| 323 | + marvell,pins = "mpp34"; | |
| 324 | + marvell,function = "gpio"; | |
| 325 | + }; | |
| 326 | + | |
| 327 | + sata4_pres_pin: sata4-pres-pin { | |
| 328 | + marvell,pins = "mpp35"; | |
| 329 | + marvell,function = "gpio"; | |
| 330 | + }; | |
| 331 | + | |
| 332 | + err_led_pin: err-led-pin { | |
| 333 | + marvell,pins = "mpp45"; | |
| 334 | + marvell,function = "gpio"; | |
| 335 | + }; | |
| 336 | +}; | |
| @@ -77,12 +77,7 @@ · 76 unmodified lines | ||
| 77 | 77 | serial@12100 { |
| 78 | 78 | status = "okay"; |
| 79 | 79 | }; |
| 80 | − pinctrl { | |
| 81 | − led_pins: led-pins-0 { | |
| 82 | − marvell,pins = "mpp49", "mpp51", "mpp53"; | |
| 83 | − marvell,function = "gpio"; | |
| 84 | − }; | |
| 85 | − }; | |
| 80 | + | |
| 86 | 81 | leds { |
| 87 | 82 | compatible = "gpio-leds"; |
| 88 | 83 | pinctrl-names = "default"; |
| @@ -187,3 +182,10 @@ · 98 unmodified lines | ||
| 187 | 182 | }; |
| 188 | 183 | }; |
| 189 | 184 | }; |
| 185 | + | |
| 186 | +&pinctrl { | |
| 187 | + led_pins: led-pins-0 { | |
| 188 | + marvell,pins = "mpp49", "mpp51", "mpp53"; | |
| 189 | + marvell,function = "gpio"; | |
| 190 | + }; | |
| 191 | +}; | |
| @@ -0,0 +1,330 @@ | ||
| 1 | +/* | |
| 2 | + * Device Tree file for Synology DS414 | |
| 3 | + * | |
| 4 | + * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> | |
| 5 | + * | |
| 6 | + * This program is free software; you can redistribute it and/or | |
| 7 | + * modify it under the terms of the GNU General Public License | |
| 8 | + * as published by the Free Software Foundation; either version | |
| 9 | + * 2 of the License, or (at your option) any later version. | |
| 10 | + * | |
| 11 | + * Note: this Device Tree assumes that the bootloader has remapped the | |
| 12 | + * internal registers to 0xf1000000 (instead of the old 0xd0000000). | |
| 13 | + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot | |
| 14 | + * bootloaders provided by Marvell. It is used in recent versions of | |
| 15 | + * DSM software provided by Synology. Nonetheless, some earlier boards | |
| 16 | + * were delivered with an older version of u-boot that left internal | |
| 17 | + * registers mapped at 0xd0000000. If you have such a device you will | |
| 18 | + * not be able to directly boot a kernel based on this Device Tree. In | |
| 19 | + * that case, the preferred solution is to update your bootloader (e.g. | |
| 20 | + * by upgrading to latest version of DSM, or building a new one and | |
| 21 | + * installing it from u-boot prompt) or adjust the Devive Tree | |
| 22 | + * (s/0xf1000000/0xd0000000/ in 'ranges' below). | |
| 23 | + */ | |
| 24 | + | |
| 25 | +/dts-v1/; | |
| 26 | + | |
| 27 | +#include <dt-bindings/input/input.h> | |
| 28 | +#include <dt-bindings/gpio/gpio.h> | |
| 29 | +#include "armada-xp-mv78230.dtsi" | |
| 30 | + | |
| 31 | +/ { | |
| 32 | + model = "Synology DS414"; | |
| 33 | + compatible = "synology,ds414", "marvell,armadaxp-mv78230", | |
| 34 | + "marvell,armadaxp", "marvell,armada-370-xp"; | |
| 35 | + | |
| 36 | + chosen { | |
| 37 | + bootargs = "console=ttyS0,115200 earlyprintk"; | |
| 38 | + stdout-path = &uart0; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + memory { | |
| 42 | + device_type = "memory"; | |
| 43 | + reg = <0 0x00000000 0 0x40000000>; /* 1GB */ | |
| 44 | + }; | |
| 45 | + | |
| 46 | + soc { | |
| 47 | + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 | |
| 48 | + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; | |
| 49 | + | |
| 50 | + pcie-controller { | |
| 51 | + status = "okay"; | |
| 52 | + | |
| 53 | + /* | |
| 54 | + * Connected to Marvell 88SX7042 SATA-II controller | |
| 55 | + * handling the four disks. | |
| 56 | + */ | |
| 57 | + pcie@1,0 { | |
| 58 | + /* Port 0, Lane 0 */ | |
| 59 | + status = "okay"; | |
| 60 | + }; | |
| 61 | + | |
| 62 | + /* | |
| 63 | + * Connected to EtronTech EJ168A XHCI controller | |
| 64 | + * providing the two rear USB 3.0 ports. | |
| 65 | + */ | |
| 66 | + pcie@5,0 { | |
| 67 | + /* Port 1, Lane 0 */ | |
| 68 | + status = "okay"; | |
| 69 | + }; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + internal-regs { | |
| 73 | + | |
| 74 | + /* RTC is provided by Seiko S-35390A below */ | |
| 75 | + rtc@10300 { | |
| 76 | + status = "disabled"; | |
| 77 | + }; | |
| 78 | + | |
| 79 | + spi0: spi@10600 { | |
| 80 | + status = "okay"; | |
| 81 | + | |
| 82 | + spi-flash@0 { | |
| 83 | + #address-cells = <1>; | |
| 84 | + #size-cells = <1>; | |
| 85 | + compatible = "micron,n25q064"; | |
| 86 | + reg = <0>; /* Chip select 0 */ | |
| 87 | + spi-max-frequency = <20000000>; | |
| 88 | + | |
| 89 | + /* | |
| 90 | + * Warning! | |
| 91 | + * | |
| 92 | + * Synology u-boot uses its compiled-in environment | |
| 93 | + * and it seems Synology did not care to change u-boot | |
| 94 | + * default configuration in order to allow saving a | |
| 95 | + * modified environment at a sensible location. So, | |
| 96 | + * if you do a 'saveenv' under u-boot, your modified | |
| 97 | + * environment will be saved at 1MB after the start | |
| 98 | + * of the flash, i.e. in the middle of the uImage. | |
| 99 | + * For that reason, it is strongly advised not to | |
| 100 | + * change the default environment, unless you know | |
| 101 | + * what you are doing. | |
| 102 | + */ | |
| 103 | + partition@00000000 { /* u-boot */ | |
| 104 | + label = "RedBoot"; | |
| 105 | + reg = <0x00000000 0x000d0000>; /* 832KB */ | |
| 106 | + }; | |
| 107 | + | |
| 108 | + partition@000c0000 { /* uImage */ | |
| 109 | + label = "zImage"; | |
| 110 | + reg = <0x000d0000 0x002d0000>; /* 2880KB */ | |
| 111 | + }; | |
| 112 | + | |
| 113 | + partition@003a0000 { /* uInitramfs */ | |
| 114 | + label = "rd.gz"; | |
| 115 | + reg = <0x003a0000 0x00430000>; /* 4250KB */ | |
| 116 | + }; | |
| 117 | + | |
| 118 | + partition@007d0000 { /* MAC address and serial number */ | |
| 119 | + label = "vendor"; | |
| 120 | + reg = <0x007d0000 0x00010000>; /* 64KB */ | |
| 121 | + }; | |
| 122 | + | |
| 123 | + partition@007e0000 { | |
| 124 | + label = "RedBoot config"; | |
| 125 | + reg = <0x007e0000 0x00010000>; /* 64KB */ | |
| 126 | + }; | |
| 127 | + | |
| 128 | + partition@007f0000 { | |
| 129 | + label = "FIS directory"; | |
| 130 | + reg = <0x007f0000 0x00010000>; /* 64KB */ | |
| 131 | + }; | |
| 132 | + }; | |
| 133 | + }; | |
| 134 | + | |
| 135 | + i2c@11000 { | |
| 136 | + clock-frequency = <400000>; | |
| 137 | + status = "okay"; | |
| 138 | + | |
| 139 | + s35390a: s35390a@30 { | |
| 140 | + compatible = "sii,s35390a"; | |
| 141 | + reg = <0x30>; | |
| 142 | + }; | |
| 143 | + }; | |
| 144 | + | |
| 145 | + /* Connected to a header on device's PCB. This | |
| 146 | + * provides the main console for the device. | |
| 147 | + * | |
| 148 | + * Warning: the device may not boot with a 3.3V | |
| 149 | + * USB-serial converter connected when the power | |
| 150 | + * button is pressed. The converter needs to be | |
| 151 | + * connected a few seconds after pressing the | |
| 152 | + * power button. This is possibly due to UART0_TXD | |
| 153 | + * pin being sampled at reset (bit 0 of SAR). | |
| 154 | + */ | |
| 155 | + serial@12000 { | |
| 156 | + status = "okay"; | |
| 157 | + }; | |
| 158 | + | |
| 159 | + /* Connected to a Microchip PIC16F883 for power control */ | |
| 160 | + serial@12100 { | |
| 161 | + status = "okay"; | |
| 162 | + }; | |
| 163 | + | |
| 164 | + poweroff@12100 { | |
| 165 | + compatible = "synology,power-off"; | |
| 166 | + reg = <0x12100 0x100>; | |
| 167 | + clocks = <&coreclk 0>; | |
| 168 | + }; | |
| 169 | + | |
| 170 | + /* Front USB 2.0 port */ | |
| 171 | + usb@50000 { | |
| 172 | + status = "okay"; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + mdio { | |
| 176 | + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ | |
| 177 | + reg = <0>; | |
| 178 | + }; | |
| 179 | + | |
| 180 | + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ | |
| 181 | + reg = <1>; | |
| 182 | + }; | |
| 183 | + }; | |
| 184 | + | |
| 185 | + ethernet@70000 { | |
| 186 | + status = "okay"; | |
| 187 | + pinctrl-0 = <&ge0_rgmii_pins>; | |
| 188 | + pinctrl-names = "default"; | |
| 189 | + phy = <&phy1>; | |
| 190 | + phy-mode = "rgmii-id"; | |
| 191 | + }; | |
| 192 | + | |
| 193 | + ethernet@74000 { | |
| 194 | + pinctrl-0 = <&ge1_rgmii_pins>; | |
| 195 | + pinctrl-names = "default"; | |
| 196 | + status = "okay"; | |
| 197 | + phy = <&phy0>; | |
| 198 | + phy-mode = "rgmii-id"; | |
| 199 | + }; | |
| 200 | + }; | |
| 201 | + }; | |
| 202 | + | |
| 203 | + regulators { | |
| 204 | + compatible = "simple-bus"; | |
| 205 | + #address-cells = <1>; | |
| 206 | + #size-cells = <0>; | |
| 207 | + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin | |
| 208 | + &sata3_pwr_pin &sata4_pwr_pin>; | |
| 209 | + pinctrl-names = "default"; | |
| 210 | + | |
| 211 | + sata1_regulator: sata1-regulator { | |
| 212 | + compatible = "regulator-fixed"; | |
| 213 | + reg = <1>; | |
| 214 | + regulator-name = "SATA1 Power"; | |
| 215 | + regulator-min-microvolt = <5000000>; | |
| 216 | + regulator-max-microvolt = <5000000>; | |
| 217 | + startup-delay-us = <2000000>; | |
| 218 | + enable-active-high; | |
| 219 | + regulator-always-on; | |
| 220 | + regulator-boot-on; | |
| 221 | + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; | |
| 222 | + }; | |
| 223 | + | |
| 224 | + sata2_regulator: sata2-regulator { | |
| 225 | + compatible = "regulator-fixed"; | |
| 226 | + reg = <2>; | |
| 227 | + regulator-name = "SATA2 Power"; | |
| 228 | + regulator-min-microvolt = <5000000>; | |
| 229 | + regulator-max-microvolt = <5000000>; | |
| 230 | + startup-delay-us = <4000000>; | |
| 231 | + enable-active-high; | |
| 232 | + regulator-always-on; | |
| 233 | + regulator-boot-on; | |
| 234 | + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; | |
| 235 | + }; | |
| 236 | + | |
| 237 | + sata3_regulator: sata3-regulator { | |
| 238 | + compatible = "regulator-fixed"; | |
| 239 | + reg = <3>; | |
| 240 | + regulator-name = "SATA3 Power"; | |
| 241 | + regulator-min-microvolt = <5000000>; | |
| 242 | + regulator-max-microvolt = <5000000>; | |
| 243 | + startup-delay-us = <6000000>; | |
| 244 | + enable-active-high; | |
| 245 | + regulator-always-on; | |
| 246 | + regulator-boot-on; | |
| 247 | + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; | |
| 248 | + }; | |
| 249 | + | |
| 250 | + sata4_regulator: sata4-regulator { | |
| 251 | + compatible = "regulator-fixed"; | |
| 252 | + reg = <4>; | |
| 253 | + regulator-name = "SATA4 Power"; | |
| 254 | + regulator-min-microvolt = <5000000>; | |
| 255 | + regulator-max-microvolt = <5000000>; | |
| 256 | + startup-delay-us = <8000000>; | |
| 257 | + enable-active-high; | |
| 258 | + regulator-always-on; | |
| 259 | + regulator-boot-on; | |
| 260 | + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; | |
| 261 | + }; | |
| 262 | + }; | |
| 263 | +}; | |
| 264 | + | |
| 265 | +&pinctrl { | |
| 266 | + sata1_pwr_pin: sata1-pwr-pin { | |
| 267 | + marvell,pins = "mpp42"; | |
| 268 | + marvell,function = "gpio"; | |
| 269 | + }; | |
| 270 | + | |
| 271 | + sata2_pwr_pin: sata2-pwr-pin { | |
| 272 | + marvell,pins = "mpp44"; | |
| 273 | + marvell,function = "gpio"; | |
| 274 | + }; | |
| 275 | + | |
| 276 | + sata3_pwr_pin: sata3-pwr-pin { | |
| 277 | + marvell,pins = "mpp45"; | |
| 278 | + marvell,function = "gpio"; | |
| 279 | + }; | |
| 280 | + | |
| 281 | + sata4_pwr_pin: sata4-pwr-pin { | |
| 282 | + marvell,pins = "mpp46"; | |
| 283 | + marvell,function = "gpio"; | |
| 284 | + }; | |
| 285 | + | |
| 286 | + sata1_pres_pin: sata1-pres-pin { | |
| 287 | + marvell,pins = "mpp34"; | |
| 288 | + marvell,function = "gpio"; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + sata2_pres_pin: sata2-pres-pin { | |
| 292 | + marvell,pins = "mpp35"; | |
| 293 | + marvell,function = "gpio"; | |
| 294 | + }; | |
| 295 | + | |
| 296 | + sata3_pres_pin: sata3-pres-pin { | |
| 297 | + marvell,pins = "mpp40"; | |
| 298 | + marvell,function = "gpio"; | |
| 299 | + }; | |
| 300 | + | |
| 301 | + sata4_pres_pin: sata4-pres-pin { | |
| 302 | + marvell,pins = "mpp41"; | |
| 303 | + marvell,function = "gpio"; | |
| 304 | + }; | |
| 305 | + | |
| 306 | + syno_id_bit0_pin: syno-id-bit0-pin { | |
| 307 | + marvell,pins = "mpp26"; | |
| 308 | + marvell,function = "gpio"; | |
| 309 | + }; | |
| 310 | + | |
| 311 | + syno_id_bit1_pin: syno-id-bit1-pin { | |
| 312 | + marvell,pins = "mpp28"; | |
| 313 | + marvell,function = "gpio"; | |
| 314 | + }; | |
| 315 | + | |
| 316 | + syno_id_bit2_pin: syno-id-bit2-pin { | |
| 317 | + marvell,pins = "mpp29"; | |
| 318 | + marvell,function = "gpio"; | |
| 319 | + }; | |
| 320 | + | |
| 321 | + fan1_alarm_pin: fan1-alarm-pin { | |
| 322 | + marvell,pins = "mpp33"; | |
| 323 | + marvell,function = "gpio"; | |
| 324 | + }; | |
| 325 | + | |
| 326 | + fan2_alarm_pin: fan2-alarm-pin { | |
| 327 | + marvell,pins = "mpp32"; | |
| 328 | + marvell,function = "gpio"; | |
| 329 | + }; | |
| 330 | +}; | |
| @@ -35,13 +35,24 @@ · 34 unmodified lines | ||
| 35 | 35 | }; |
| 36 | 36 | |
| 37 | 37 | internal-regs { |
| 38 | + sdramc@1400 { | |
| 39 | + compatible = "marvell,armada-xp-sdram-controller"; | |
| 40 | + reg = <0x1400 0x500>; | |
| 41 | + }; | |
| 42 | + | |
| 38 | 43 | L2: l2-cache { |
| 39 | 44 | compatible = "marvell,aurora-system-cache"; |
| 40 | 45 | reg = <0x08000 0x1000>; |
| 41 | 46 | cache-id-part = <0x100>; |
| 47 | + cache-unified; | |
| 42 | 48 | wt-override; |
| 43 | 49 | }; |
| 44 | 50 | |
| 51 | + spi0: spi@10600 { | |
| 52 | + pinctrl-0 = <&spi0_pins>; | |
| 53 | + pinctrl-names = "default"; | |
| 54 | + }; | |
| 55 | + | |
| 45 | 56 | i2c0: i2c@11000 { |
| 46 | 57 | compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; |
| 47 | 58 | reg = <0x11000 0x100>; |
| @@ -52,8 +63,10 @@ · 4 unmodified lines | ||
| 52 | 63 | reg = <0x11100 0x100>; |
| 53 | 64 | }; |
| 54 | 65 | |
| 55 | − serial@12200 { | |
| 66 | + uart2: serial@12200 { | |
| 56 | 67 | compatible = "snps,dw-apb-uart"; |
| 68 | + pinctrl-0 = <&uart2_pins>; | |
| 69 | + pinctrl-names = "default"; | |
| 57 | 70 | reg = <0x12200 0x100>; |
| 58 | 71 | reg-shift = <2>; |
| 59 | 72 | interrupts = <43>; |
| @@ -61,8 +74,11 @@ · 1 unmodified line | ||
| 61 | 74 | clocks = <&coreclk 0>; |
| 62 | 75 | status = "disabled"; |
| 63 | 76 | }; |
| 64 | − serial@12300 { | |
| 77 | + | |
| 78 | + uart3: serial@12300 { | |
| 65 | 79 | compatible = "snps,dw-apb-uart"; |
| 80 | + pinctrl-0 = <&uart3_pins>; | |
| 81 | + pinctrl-names = "default"; | |
| 66 | 82 | reg = <0x12300 0x100>; |
| 67 | 83 | reg-shift = <2>; |
| 68 | 84 | interrupts = <44>; |
| @@ -199,3 +215,54 @@ · 130 unmodified lines | ||
| 199 | 215 | }; |
| 200 | 216 | }; |
| 201 | 217 | }; |
| 218 | + | |
| 219 | +&pinctrl { | |
| 220 | + ge0_gmii_pins: ge0-gmii-pins { | |
| 221 | + marvell,pins = | |
| 222 | + "mpp0", "mpp1", "mpp2", "mpp3", | |
| 223 | + "mpp4", "mpp5", "mpp6", "mpp7", | |
| 224 | + "mpp8", "mpp9", "mpp10", "mpp11", | |
| 225 | + "mpp12", "mpp13", "mpp14", "mpp15", | |
| 226 | + "mpp16", "mpp17", "mpp18", "mpp19", | |
| 227 | + "mpp20", "mpp21", "mpp22", "mpp23"; | |
| 228 | + marvell,function = "ge0"; | |
| 229 | + }; | |
| 230 | + | |
| 231 | + ge0_rgmii_pins: ge0-rgmii-pins { | |
| 232 | + marvell,pins = | |
| 233 | + "mpp0", "mpp1", "mpp2", "mpp3", | |
| 234 | + "mpp4", "mpp5", "mpp6", "mpp7", | |
| 235 | + "mpp8", "mpp9", "mpp10", "mpp11"; | |
| 236 | + marvell,function = "ge0"; | |
| 237 | + }; | |
| 238 | + | |
| 239 | + ge1_rgmii_pins: ge1-rgmii-pins { | |
| 240 | + marvell,pins = | |
| 241 | + "mpp12", "mpp13", "mpp14", "mpp15", | |
| 242 | + "mpp16", "mpp17", "mpp18", "mpp19", | |
| 243 | + "mpp20", "mpp21", "mpp22", "mpp23"; | |
| 244 | + marvell,function = "ge1"; | |
| 245 | + }; | |
| 246 | + | |
| 247 | + sdio_pins: sdio-pins { | |
| 248 | + marvell,pins = "mpp30", "mpp31", "mpp32", | |
| 249 | + "mpp33", "mpp34", "mpp35"; | |
| 250 | + marvell,function = "sd0"; | |
| 251 | + }; | |
| 252 | + | |
| 253 | + spi0_pins: spi0-pins { | |
| 254 | + marvell,pins = "mpp36", "mpp37", | |
| 255 | + "mpp38", "mpp39"; | |
| 256 | + marvell,function = "spi"; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + uart2_pins: uart2-pins { | |
| 260 | + marvell,pins = "mpp42", "mpp43"; | |
| 261 | + marvell,function = "uart2"; | |
| 262 | + }; | |
| 263 | + | |
| 264 | + uart3_pins: uart3-pins { | |
| 265 | + marvell,pins = "mpp44", "mpp45"; | |
| 266 | + marvell,function = "uart3"; | |
| 267 | + }; | |
| 268 | +}; | |
| @@ -677,6 +677,14 @@ · 676 unmodified lines | ||
| 677 | 677 | }; |
| 678 | 678 | }; |
| 679 | 679 | |
| 680 | + can { | |
| 681 | + pinctrl_can_rx_tx: can_rx_tx { | |
| 682 | + atmel,pins = | |
| 683 | + <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */ | |
| 684 | + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */ | |
| 685 | + }; | |
| 686 | + }; | |
| 687 | + | |
| 680 | 688 | pioA: gpio@fffff200 { |
| 681 | 689 | compatible = "atmel,at91rm9200-gpio"; |
| 682 | 690 | reg = <0xfffff200 0x200>; |
| @@ -905,6 +913,17 @@ · 222 unmodified lines | ||
| 905 | 913 | clock-names = "pwm_clk"; |
| 906 | 914 | status = "disabled"; |
| 907 | 915 | }; |
| 916 | + | |
| 917 | + can: can@fffac000 { | |
| 918 | + compatible = "atmel,at91sam9263-can"; | |
| 919 | + reg = <0xfffac000 0x300>; | |
| 920 | + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; | |
| 921 | + pinctrl-names = "default"; | |
| 922 | + pinctrl-0 = <&pinctrl_can_rx_tx>; | |
| 923 | + clocks = <&can_clk>; | |
| 924 | + clock-names = "can_clk"; | |
| 925 | + status = "disabled"; | |
| 926 | + }; | |
| 908 | 927 | }; |
| 909 | 928 | |
| 910 | 929 | fb0: fb@0x00700000 { |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | ||
| 10 | 10 | #include "at91sam9x5_usart3.dtsi" |
| 11 | 11 | #include "at91sam9x5_macb0.dtsi" |
| 12 | 12 | #include "at91sam9x5_macb1.dtsi" |
| 13 | +#include "at91sam9x5_can.dtsi" | |
| 13 | 14 | |
| 14 | 15 | / { |
| 15 | 16 | model = "Atmel AT91SAM9X25 SoC"; |
| @@ -8,6 +8,7 @@ · 7 unmodified lines | ||
| 8 | 8 | |
| 9 | 9 | #include "at91sam9x5.dtsi" |
| 10 | 10 | #include "at91sam9x5_macb0.dtsi" |
| 11 | +#include "at91sam9x5_can.dtsi" | |
| 11 | 12 | |
| 12 | 13 | / { |
| 13 | 14 | model = "Atmel AT91SAM9X35 SoC"; |
| @@ -860,6 +860,9 @@ · 859 unmodified lines | ||
| 860 | 860 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 861 | 861 | pinctrl-names = "default"; |
| 862 | 862 | pinctrl-0 = <&pinctrl_dbgu>; |
| 863 | + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, | |
| 864 | + <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; | |
| 865 | + dma-names = "tx", "rx"; | |
| 863 | 866 | clocks = <&mck>; |
| 864 | 867 | clock-names = "usart"; |
| 865 | 868 | status = "disabled"; |
| @@ -871,6 +874,9 @@ · 5 unmodified lines | ||
| 871 | 874 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
| 872 | 875 | pinctrl-names = "default"; |
| 873 | 876 | pinctrl-0 = <&pinctrl_usart0>; |
| 877 | + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, | |
| 878 | + <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; | |
| 879 | + dma-names = "tx", "rx"; | |
| 874 | 880 | clocks = <&usart0_clk>; |
| 875 | 881 | clock-names = "usart"; |
| 876 | 882 | status = "disabled"; |
| @@ -882,6 +888,9 @@ · 5 unmodified lines | ||
| 882 | 888 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| 883 | 889 | pinctrl-names = "default"; |
| 884 | 890 | pinctrl-0 = <&pinctrl_usart1>; |
| 891 | + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, | |
| 892 | + <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; | |
| 893 | + dma-names = "tx", "rx"; | |
| 885 | 894 | clocks = <&usart1_clk>; |
| 886 | 895 | clock-names = "usart"; |
| 887 | 896 | status = "disabled"; |
| @@ -893,6 +902,9 @@ · 5 unmodified lines | ||
| 893 | 902 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| 894 | 903 | pinctrl-names = "default"; |
| 895 | 904 | pinctrl-0 = <&pinctrl_usart2>; |
| 905 | + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, | |
| 906 | + <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; | |
| 907 | + dma-names = "tx", "rx"; | |
| 896 | 908 | clocks = <&usart2_clk>; |
| 897 | 909 | clock-names = "usart"; |
| 898 | 910 | status = "disabled"; |
| @@ -1,5 +1,5 @@ | ||
| 1 | 1 | /* |
| 2 | − * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 | |
| 2 | + * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 | |
| 3 | 3 | * Ethernet interface. |
| 4 | 4 | * |
| 5 | 5 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> |
| @@ -20,10 +20,50 @@ · 14 unmodified lines | ||
| 20 | 20 | reg = <29>; |
| 21 | 21 | }; |
| 22 | 22 | |
| 23 | − can1_clk: can1_clk { | |
| 24 | − #clock-cells = <0>; | |
| 25 | − reg = <30>; | |
| 26 | − }; | |
| 23 | + can1_clk: can1_clk { | |
| 24 | + #clock-cells = <0>; | |
| 25 | + reg = <30>; | |
| 26 | + }; | |
| 27 | + }; | |
| 28 | + }; | |
| 29 | + | |
| 30 | + can0: can@f8000000 { | |
| 31 | + compatible = "atmel,at91sam9x5-can"; | |
| 32 | + reg = <0xf8000000 0x300>; | |
| 33 | + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; | |
| 34 | + pinctrl-names = "default"; | |
| 35 | + pinctrl-0 = <&pinctrl_can0_rx_tx>; | |
| 36 | + clocks = <&can0_clk>; | |
| 37 | + clock-names = "can_clk"; | |
| 38 | + status = "disabled"; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + can1: can@f8004000 { | |
| 42 | + compatible = "atmel,at91sam9x5-can"; | |
| 43 | + reg = <0xf8004000 0x300>; | |
| 44 | + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; | |
| 45 | + pinctrl-names = "default"; | |
| 46 | + pinctrl-0 = <&pinctrl_can1_rx_tx>; | |
| 47 | + clocks = <&can1_clk>; | |
| 48 | + clock-names = "can_clk"; | |
| 49 | + status = "disabled"; | |
| 50 | + }; | |
| 51 | + | |
| 52 | + pinctrl@fffff400 { | |
| 53 | + can0 { | |
| 54 | + pinctrl_can0_rx_tx: can0_rx_tx { | |
| 55 | + atmel,pins = | |
| 56 | + <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */ | |
| 57 | + AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */ | |
| 58 | + }; | |
| 59 | + }; | |
| 60 | + | |
| 61 | + can1 { | |
| 62 | + pinctrl_can1_rx_tx: can1_rx_tx { | |
| 63 | + atmel,pins = | |
| 64 | + <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */ | |
| 65 | + AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */ | |
| 66 | + }; | |
| 27 | 67 | }; |
| 28 | 68 | }; |
| 29 | 69 | }; |
| @@ -57,6 +57,9 @@ · 56 unmodified lines | ||
| 57 | 57 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| 58 | 58 | pinctrl-names = "default"; |
| 59 | 59 | pinctrl-0 = <&pinctrl_usart3>; |
| 60 | + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, | |
| 61 | + <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; | |
| 62 | + dma-names = "tx", "rx"; | |
| 60 | 63 | clocks = <&usart3_clk>; |
| 61 | 64 | clock-names = "usart"; |
| 62 | 65 | status = "disabled"; |
| @@ -131,6 +131,7 @@ · 130 unmodified lines | ||
| 131 | 131 | reg = <0x90020000 0x10000>; |
| 132 | 132 | interrupts = <31>; |
| 133 | 133 | clocks = <&clks 35>; |
| 134 | + resets = <&rstc 6>; | |
| 134 | 135 | }; |
| 135 | 136 | }; |
| 136 | 137 | |
| @@ -312,6 +313,7 @@ · 175 unmodified lines | ||
| 312 | 313 | #address-cells = <1>; |
| 313 | 314 | #size-cells = <0>; |
| 314 | 315 | clocks = <&clks 19>; |
| 316 | + resets = <&rstc 26>; | |
| 315 | 317 | status = "disabled"; |
| 316 | 318 | }; |
| 317 | 319 | |
| @@ -327,6 +329,7 @@ · 9 unmodified lines | ||
| 327 | 329 | #address-cells = <1>; |
| 328 | 330 | #size-cells = <0>; |
| 329 | 331 | clocks = <&clks 20>; |
| 332 | + resets = <&rstc 27>; | |
| 330 | 333 | status = "disabled"; |
| 331 | 334 | }; |
| 332 | 335 | |
| @@ -522,6 +525,18 @@ · 189 unmodified lines | ||
| 522 | 525 | sirf,function = "sdmmc5"; |
| 523 | 526 | }; |
| 524 | 527 | }; |
| 528 | + i2s_mclk_pins_a: i2s_mclk@0 { | |
| 529 | + i2s_mclk { | |
| 530 | + sirf,pins = "i2smclkgrp"; | |
| 531 | + sirf,function = "i2s_mclk"; | |
| 532 | + }; | |
| 533 | + }; | |
| 534 | + i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { | |
| 535 | + i2s_ext_clk_input { | |
| 536 | + sirf,pins = "i2s_ext_clk_inputgrp"; | |
| 537 | + sirf,function = "i2s_ext_clk_input"; | |
| 538 | + }; | |
| 539 | + }; | |
| 525 | 540 | i2s_pins_a: i2s@0 { |
| 526 | 541 | i2s { |
| 527 | 542 | sirf,pins = "i2sgrp"; |
| @@ -0,0 +1,91 @@ | ||
| 1 | +/* | |
| 2 | + * BSD LICENSE | |
| 3 | + * | |
| 4 | + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. | |
| 5 | + * | |
| 6 | + * Redistribution and use in source and binary forms, with or without | |
| 7 | + * modification, are permitted provided that the following conditions | |
| 8 | + * are met: | |
| 9 | + * | |
| 10 | + * * Redistributions of source code must retain the above copyright | |
| 11 | + * notice, this list of conditions and the following disclaimer. | |
| 12 | + * * Redistributions in binary form must reproduce the above copyright | |
| 13 | + * notice, this list of conditions and the following disclaimer in | |
| 14 | + * the documentation and/or other materials provided with the | |
| 15 | + * distribution. | |
| 16 | + * * Neither the name of Broadcom Corporation nor the names of its | |
| 17 | + * contributors may be used to endorse or promote products derived | |
| 18 | + * from this software without specific prior written permission. | |
| 19 | + * | |
| 20 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 23 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 24 | + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 25 | + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 27 | + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 28 | + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 30 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | + */ | |
| 32 | + | |
| 33 | +clocks { | |
| 34 | + #address-cells = <1>; | |
| 35 | + #size-cells = <1>; | |
| 36 | + ranges; | |
| 37 | + | |
| 38 | + osc: oscillator { | |
| 39 | + compatible = "fixed-clock"; | |
| 40 | + #clock-cells = <1>; | |
| 41 | + clock-frequency = <25000000>; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + apb_clk: apb_clk { | |
| 45 | + compatible = "fixed-clock"; | |
| 46 | + #clock-cells = <0>; | |
| 47 | + clock-frequency = <1000000000>; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + periph_clk: periph_clk { | |
| 51 | + compatible = "fixed-clock"; | |
| 52 | + #clock-cells = <0>; | |
| 53 | + clock-frequency = <500000000>; | |
| 54 | + }; | |
| 55 | + | |
| 56 | + sdio_clk: lcpll_ch2 { | |
| 57 | + compatible = "fixed-clock"; | |
| 58 | + #clock-cells = <0>; | |
| 59 | + clock-frequency = <200000000>; | |
| 60 | + }; | |
| 61 | + | |
| 62 | + axi81_clk: axi81_clk { | |
| 63 | + compatible = "fixed-clock"; | |
| 64 | + #clock-cells = <0>; | |
| 65 | + clock-frequency = <100000000>; | |
| 66 | + }; | |
| 67 | + | |
| 68 | + keypad_clk: keypad_clk { | |
| 69 | + compatible = "fixed-clock"; | |
| 70 | + #clock-cells = <0>; | |
| 71 | + clock-frequency = <31806>; | |
| 72 | + }; | |
| 73 | + | |
| 74 | + adc_clk: adc_clk { | |
| 75 | + compatible = "fixed-clock"; | |
| 76 | + #clock-cells = <0>; | |
| 77 | + clock-frequency = <1562500>; | |
| 78 | + }; | |
| 79 | + | |
| 80 | + pwm_clk: pwm_clk { | |
| 81 | + compatible = "fixed-clock"; | |
| 82 | + #clock-cells = <0>; | |
| 83 | + clock-frequency = <1000000>; | |
| 84 | + }; | |
| 85 | + | |
| 86 | + lcd_clk: mipipll_ch1 { | |
| 87 | + compatible = "fixed-clock"; | |
| 88 | + #clock-cells = <0>; | |
| 89 | + clock-frequency = <100000000>; | |
| 90 | + }; | |
| 91 | +}; | |
| @@ -0,0 +1,140 @@ | ||
| 1 | +/* | |
| 2 | + * BSD LICENSE | |
| 3 | + * | |
| 4 | + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. | |
| 5 | + * | |
| 6 | + * Redistribution and use in source and binary forms, with or without | |
| 7 | + * modification, are permitted provided that the following conditions | |
| 8 | + * are met: | |
| 9 | + * | |
| 10 | + * * Redistributions of source code must retain the above copyright | |
| 11 | + * notice, this list of conditions and the following disclaimer. | |
| 12 | + * * Redistributions in binary form must reproduce the above copyright | |
| 13 | + * notice, this list of conditions and the following disclaimer in | |
| 14 | + * the documentation and/or other materials provided with the | |
| 15 | + * distribution. | |
| 16 | + * * Neither the name of Broadcom Corporation nor the names of its | |
| 17 | + * contributors may be used to endorse or promote products derived | |
| 18 | + * from this software without specific prior written permission. | |
| 19 | + * | |
| 20 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 23 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 24 | + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 25 | + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 27 | + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 28 | + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 30 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | + */ | |
| 32 | + | |
| 33 | +#include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 34 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 35 | + | |
| 36 | +#include "skeleton.dtsi" | |
| 37 | + | |
| 38 | +/ { | |
| 39 | + compatible = "brcm,cygnus"; | |
| 40 | + model = "Broadcom Cygnus SoC"; | |
| 41 | + interrupt-parent = <&gic>; | |
| 42 | + | |
| 43 | + cpus { | |
| 44 | + #address-cells = <1>; | |
| 45 | + #size-cells = <0>; | |
| 46 | + | |
| 47 | + cpu@0 { | |
| 48 | + device_type = "cpu"; | |
| 49 | + compatible = "arm,cortex-a9"; | |
| 50 | + next-level-cache = <&L2>; | |
| 51 | + reg = <0x0>; | |
| 52 | + }; | |
| 53 | + }; | |
| 54 | + | |
| 55 | + /include/ "bcm-cygnus-clock.dtsi" | |
| 56 | + | |
| 57 | + amba { | |
| 58 | + #address-cells = <1>; | |
| 59 | + #size-cells = <1>; | |
| 60 | + compatible = "arm,amba-bus", "simple-bus"; | |
| 61 | + interrupt-parent = <&gic>; | |
| 62 | + ranges; | |
| 63 | + | |
| 64 | + wdt@18009000 { | |
| 65 | + compatible = "arm,sp805" , "arm,primecell"; | |
| 66 | + reg = <0x18009000 0x1000>; | |
| 67 | + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
| 68 | + clocks = <&axi81_clk>; | |
| 69 | + clock-names = "apb_pclk"; | |
| 70 | + }; | |
| 71 | + }; | |
| 72 | + | |
| 73 | + uart0: serial@18020000 { | |
| 74 | + compatible = "snps,dw-apb-uart"; | |
| 75 | + reg = <0x18020000 0x100>; | |
| 76 | + reg-shift = <2>; | |
| 77 | + reg-io-width = <4>; | |
| 78 | + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 79 | + clocks = <&axi81_clk>; | |
| 80 | + clock-frequency = <100000000>; | |
| 81 | + status = "disabled"; | |
| 82 | + }; | |
| 83 | + | |
| 84 | + uart1: serial@18021000 { | |
| 85 | + compatible = "snps,dw-apb-uart"; | |
| 86 | + reg = <0x18021000 0x100>; | |
| 87 | + reg-shift = <2>; | |
| 88 | + reg-io-width = <4>; | |
| 89 | + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
| 90 | + clocks = <&axi81_clk>; | |
| 91 | + clock-frequency = <100000000>; | |
| 92 | + status = "disabled"; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + uart2: serial@18022000 { | |
| 96 | + compatible = "snps,dw-apb-uart"; | |
| 97 | + reg = <0x18020000 0x100>; | |
| 98 | + reg-shift = <2>; | |
| 99 | + reg-io-width = <4>; | |
| 100 | + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 101 | + clocks = <&axi81_clk>; | |
| 102 | + clock-frequency = <100000000>; | |
| 103 | + status = "disabled"; | |
| 104 | + }; | |
| 105 | + | |
| 106 | + uart3: serial@18023000 { | |
| 107 | + compatible = "snps,dw-apb-uart"; | |
| 108 | + reg = <0x18023000 0x100>; | |
| 109 | + reg-shift = <2>; | |
| 110 | + reg-io-width = <4>; | |
| 111 | + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
| 112 | + clocks = <&axi81_clk>; | |
| 113 | + clock-frequency = <100000000>; | |
| 114 | + status = "disabled"; | |
| 115 | + }; | |
| 116 | + | |
| 117 | + gic: interrupt-controller@19021000 { | |
| 118 | + compatible = "arm,cortex-a9-gic"; | |
| 119 | + #interrupt-cells = <3>; | |
| 120 | + #address-cells = <0>; | |
| 121 | + interrupt-controller; | |
| 122 | + reg = <0x19021000 0x1000>, | |
| 123 | + <0x19020100 0x100>; | |
| 124 | + }; | |
| 125 | + | |
| 126 | + L2: l2-cache { | |
| 127 | + compatible = "arm,pl310-cache"; | |
| 128 | + reg = <0x19022000 0x1000>; | |
| 129 | + cache-unified; | |
| 130 | + cache-level = <2>; | |
| 131 | + }; | |
| 132 | + | |
| 133 | + timer@19020200 { | |
| 134 | + compatible = "arm,cortex-a9-global-timer"; | |
| 135 | + reg = <0x19020200 0x100>; | |
| 136 | + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 137 | + clocks = <&periph_clk>; | |
| 138 | + }; | |
| 139 | + | |
| 140 | +}; | |
| @@ -0,0 +1,30 @@ | ||
| 1 | +/dts-v1/; | |
| 2 | +/include/ "bcm2835-rpi.dtsi" | |
| 3 | + | |
| 4 | +/ { | |
| 5 | + compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; | |
| 6 | + model = "Raspberry Pi Model B+"; | |
| 7 | + | |
| 8 | + leds { | |
| 9 | + act { | |
| 10 | + gpios = <&gpio 47 0>; | |
| 11 | + }; | |
| 12 | + | |
| 13 | + pwr { | |
| 14 | + label = "PWR"; | |
| 15 | + gpios = <&gpio 35 0>; | |
| 16 | + default-state = "keep"; | |
| 17 | + linux,default-trigger = "default-on"; | |
| 18 | + }; | |
| 19 | + }; | |
| 20 | +}; | |
| 21 | + | |
| 22 | +&gpio { | |
| 23 | + pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; | |
| 24 | + | |
| 25 | + /* I2S interface */ | |
| 26 | + i2s_alt0: i2s_alt0 { | |
| 27 | + brcm,pins = <18 19 20 21>; | |
| 28 | + brcm,function = <4>; /* alt0 */ | |
| 29 | + }; | |
| 30 | +}; | |
| @@ -1,63 +1,23 @@ | ||
| 1 | 1 | /dts-v1/; |
| 2 | −/include/ "bcm2835.dtsi" | |
| 2 | +/include/ "bcm2835-rpi.dtsi" | |
| 3 | 3 | |
| 4 | 4 | / { |
| 5 | 5 | compatible = "raspberrypi,model-b", "brcm,bcm2835"; |
| 6 | 6 | model = "Raspberry Pi Model B"; |
| 7 | 7 | |
| 8 | − memory { | |
| 9 | − reg = <0 0x10000000>; | |
| 10 | − }; | |
| 11 | − | |
| 12 | 8 | leds { |
| 13 | − compatible = "gpio-leds"; | |
| 14 | − | |
| 15 | 9 | act { |
| 16 | − label = "ACT"; | |
| 17 | 10 | gpios = <&gpio 16 1>; |
| 18 | − default-state = "keep"; | |
| 19 | − linux,default-trigger = "heartbeat"; | |
| 20 | 11 | }; |
| 21 | 12 | }; |
| 22 | 13 | }; |
| 23 | 14 | |
| 24 | 15 | &gpio { |
| 25 | − pinctrl-names = "default"; | |
| 26 | − pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>; | |
| 27 | − | |
| 28 | − gpioout: gpioout { | |
| 29 | − brcm,pins = <6>; | |
| 30 | − brcm,function = <1>; /* GPIO out */ | |
| 31 | − }; | |
| 32 | − | |
| 33 | − alt0: alt0 { | |
| 34 | − brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; | |
| 35 | − brcm,function = <4>; /* alt0 */ | |
| 36 | − }; | |
| 37 | − | |
| 38 | − alt3: alt3 { | |
| 39 | − brcm,pins = <48 49 50 51 52 53>; | |
| 40 | − brcm,function = <7>; /* alt3 */ | |
| 41 | − }; | |
| 16 | + pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; | |
| 42 | 17 | |
| 43 | 18 | /* I2S interface */ |
| 44 | − alt2: alt2 { | |
| 19 | + i2s_alt2: i2s_alt2 { | |
| 45 | 20 | brcm,pins = <28 29 30 31>; |
| 46 | 21 | brcm,function = <6>; /* alt2 */ |
| 47 | 22 | }; |
| 48 | 23 | }; |
| 49 | − | |
| 50 | −&i2c0 { | |
| 51 | − status = "okay"; | |
| 52 | − clock-frequency = <100000>; | |
| 53 | −}; | |
| 54 | − | |
| 55 | −&i2c1 { | |
| 56 | − status = "okay"; | |
| 57 | − clock-frequency = <100000>; | |
| 58 | −}; | |
| 59 | − | |
| 60 | −&sdhci { | |
| 61 | − status = "okay"; | |
| 62 | − bus-width = <4>; | |
| 63 | −}; | |
| @@ -0,0 +1,51 @@ | ||
| 1 | +/include/ "bcm2835.dtsi" | |
| 2 | + | |
| 3 | +/ { | |
| 4 | + memory { | |
| 5 | + reg = <0 0x10000000>; | |
| 6 | + }; | |
| 7 | + | |
| 8 | + leds { | |
| 9 | + compatible = "gpio-leds"; | |
| 10 | + | |
| 11 | + act { | |
| 12 | + label = "ACT"; | |
| 13 | + default-state = "keep"; | |
| 14 | + linux,default-trigger = "heartbeat"; | |
| 15 | + }; | |
| 16 | + }; | |
| 17 | +}; | |
| 18 | + | |
| 19 | +&gpio { | |
| 20 | + pinctrl-names = "default"; | |
| 21 | + | |
| 22 | + gpioout: gpioout { | |
| 23 | + brcm,pins = <6>; | |
| 24 | + brcm,function = <1>; /* GPIO out */ | |
| 25 | + }; | |
| 26 | + | |
| 27 | + alt0: alt0 { | |
| 28 | + brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; | |
| 29 | + brcm,function = <4>; /* alt0 */ | |
| 30 | + }; | |
| 31 | + | |
| 32 | + alt3: alt3 { | |
| 33 | + brcm,pins = <48 49 50 51 52 53>; | |
| 34 | + brcm,function = <7>; /* alt3 */ | |
| 35 | + }; | |
| 36 | +}; | |
| 37 | + | |
| 38 | +&i2c0 { | |
| 39 | + status = "okay"; | |
| 40 | + clock-frequency = <100000>; | |
| 41 | +}; | |
| 42 | + | |
| 43 | +&i2c1 { | |
| 44 | + status = "okay"; | |
| 45 | + clock-frequency = <100000>; | |
| 46 | +}; | |
| 47 | + | |
| 48 | +&sdhci { | |
| 49 | + status = "okay"; | |
| 50 | + bus-width = <4>; | |
| 51 | +}; | |
| @@ -0,0 +1,64 @@ | ||
| 1 | +/* | |
| 2 | + * Broadcom BCM470X / BCM5301X ARM platform code. | |
| 3 | + * DTS for Buffalo WZR-1750DHP | |
| 4 | + * | |
| 5 | + * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com> | |
| 6 | + * | |
| 7 | + * Licensed under the GNU/GPL. See COPYING for details. | |
| 8 | + */ | |
| 9 | + | |
| 10 | +/dts-v1/; | |
| 11 | + | |
| 12 | +#include "bcm4708.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; | |
| 16 | + model = "Buffalo WZR-1750DHP (BCM4708)"; | |
| 17 | + | |
| 18 | + chosen { | |
| 19 | + bootargs = "console=ttyS0,115200"; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + reg = <0x00000000 0x08000000>; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + gpio-keys { | |
| 27 | + compatible = "gpio-keys"; | |
| 28 | + #address-cells = <1>; | |
| 29 | + #size-cells = <0>; | |
| 30 | + poll-interval = <200>; | |
| 31 | + | |
| 32 | + restart { | |
| 33 | + label = "Reset"; | |
| 34 | + linux,code = <KEY_RESTART>; | |
| 35 | + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; | |
| 36 | + }; | |
| 37 | + | |
| 38 | + aoss { | |
| 39 | + label = "AOSS"; | |
| 40 | + linux,code = <KEY_WPS_BUTTON>; | |
| 41 | + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + /* Commit mode set by switch? */ | |
| 45 | + mode { | |
| 46 | + label = "Mode"; | |
| 47 | + linux,code = <KEY_SETUP>; | |
| 48 | + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; | |
| 49 | + }; | |
| 50 | + | |
| 51 | + /* Switch: AP mode */ | |
| 52 | + sw_ap { | |
| 53 | + label = "AP"; | |
| 54 | + linux,code = <BTN_0>; | |
| 55 | + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; | |
| 56 | + }; | |
| 57 | + | |
| 58 | + eject { | |
| 59 | + label = "USB eject"; | |
| 60 | + linux,code = <KEY_EJECTCD>; | |
| 61 | + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; | |
| 62 | + }; | |
| 63 | + }; | |
| 64 | +}; | |
| @@ -32,4 +32,63 @@ · 31 unmodified lines | ||
| 32 | 32 | status = "okay"; |
| 33 | 33 | }; |
| 34 | 34 | }; |
| 35 | + | |
| 36 | + leds { | |
| 37 | + compatible = "gpio-leds"; | |
| 38 | + | |
| 39 | + logo { | |
| 40 | + label = "bcm53xx:white:logo"; | |
| 41 | + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; | |
| 42 | + linux,default-trigger = "default-on"; | |
| 43 | + }; | |
| 44 | + | |
| 45 | + power0 { | |
| 46 | + label = "bcm53xx:green:power"; | |
| 47 | + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; | |
| 48 | + linux,default-trigger = "default-off"; | |
| 49 | + }; | |
| 50 | + | |
| 51 | + power1 { | |
| 52 | + label = "bcm53xx:amber:power"; | |
| 53 | + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; | |
| 54 | + linux,default-trigger = "default-on"; | |
| 55 | + }; | |
| 56 | + | |
| 57 | + usb { | |
| 58 | + label = "bcm53xx:blue:usb"; | |
| 59 | + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; | |
| 60 | + linux,default-trigger = "default-off"; | |
| 61 | + }; | |
| 62 | + | |
| 63 | + wireless { | |
| 64 | + label = "bcm53xx:blue:wireless"; | |
| 65 | + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; | |
| 66 | + linux,default-trigger = "default-off"; | |
| 67 | + }; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + gpio-keys { | |
| 71 | + compatible = "gpio-keys"; | |
| 72 | + #address-cells = <1>; | |
| 73 | + #size-cells = <0>; | |
| 74 | + poll-interval = <200>; | |
| 75 | + | |
| 76 | + wps { | |
| 77 | + label = "WPS"; | |
| 78 | + linux,code = <KEY_WPS_BUTTON>; | |
| 79 | + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + rfkill { | |
| 83 | + label = "WiFi"; | |
| 84 | + linux,code = <KEY_RFKILL>; | |
| 85 | + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; | |
| 86 | + }; | |
| 87 | + | |
| 88 | + restart { | |
| 89 | + label = "Reset"; | |
| 90 | + linux,code = <KEY_RESTART>; | |
| 91 | + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; | |
| 92 | + }; | |
| 93 | + }; | |
| 35 | 94 | }; |
| @@ -0,0 +1,84 @@ | ||
| 1 | +/* | |
| 2 | + * Broadcom BCM470X / BCM5301X ARM platform code. | |
| 3 | + * DTS for Netgear R6300 V2 | |
| 4 | + * | |
| 5 | + * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com> | |
| 6 | + * | |
| 7 | + * Licensed under the GNU/GPL. See COPYING for details. | |
| 8 | + */ | |
| 9 | + | |
| 10 | +/dts-v1/; | |
| 11 | + | |
| 12 | +#include "bcm4708.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + compatible = "netgear,r6300v2", "brcm,bcm4708"; | |
| 16 | + model = "Netgear R6300 V2 (BCM4708)"; | |
| 17 | + | |
| 18 | + chosen { | |
| 19 | + bootargs = "console=ttyS0,115200"; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + reg = <0x00000000 0x08000000>; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + leds { | |
| 27 | + compatible = "gpio-leds"; | |
| 28 | + | |
| 29 | + logo { | |
| 30 | + label = "bcm53xx:white:logo"; | |
| 31 | + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; | |
| 32 | + linux,default-trigger = "default-on"; | |
| 33 | + }; | |
| 34 | + | |
| 35 | + power0 { | |
| 36 | + label = "bcm53xx:green:power"; | |
| 37 | + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; | |
| 38 | + linux,default-trigger = "default-off"; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + power1 { | |
| 42 | + label = "bcm53xx:amber:power"; | |
| 43 | + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; | |
| 44 | + linux,default-trigger = "default-on"; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + usb { | |
| 48 | + label = "bcm53xx:blue:usb"; | |
| 49 | + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; | |
| 50 | + linux,default-trigger = "default-off"; | |
| 51 | + }; | |
| 52 | + | |
| 53 | + wireless { | |
| 54 | + label = "bcm53xx:blue:wireless"; | |
| 55 | + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; | |
| 56 | + linux,default-trigger = "default-off"; | |
| 57 | + }; | |
| 58 | + }; | |
| 59 | + | |
| 60 | + gpio-keys { | |
| 61 | + compatible = "gpio-keys"; | |
| 62 | + #address-cells = <1>; | |
| 63 | + #size-cells = <0>; | |
| 64 | + poll-interval = <200>; | |
| 65 | + | |
| 66 | + wps { | |
| 67 | + label = "WPS"; | |
| 68 | + linux,code = <KEY_WPS_BUTTON>; | |
| 69 | + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + rfkill { | |
| 73 | + label = "WiFi"; | |
| 74 | + linux,code = <KEY_RFKILL>; | |
| 75 | + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; | |
| 76 | + }; | |
| 77 | + | |
| 78 | + restart { | |
| 79 | + label = "Reset"; | |
| 80 | + linux,code = <KEY_RESTART>; | |
| 81 | + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; | |
| 82 | + }; | |
| 83 | + }; | |
| 84 | +}; | |
| @@ -0,0 +1,78 @@ | ||
| 1 | +/* | |
| 2 | + * Broadcom BCM470X / BCM5301X ARM platform code. | |
| 3 | + * DTS for Asus RT-N18U | |
| 4 | + * | |
| 5 | + * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com> | |
| 6 | + * | |
| 7 | + * Licensed under the GNU/GPL. See COPYING for details. | |
| 8 | + */ | |
| 9 | + | |
| 10 | +/dts-v1/; | |
| 11 | + | |
| 12 | +#include "bcm47081.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; | |
| 16 | + model = "Asus RT-N18U (BCM47081)"; | |
| 17 | + | |
| 18 | + chosen { | |
| 19 | + bootargs = "console=ttyS0,115200"; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + reg = <0x00000000 0x08000000>; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + leds { | |
| 27 | + compatible = "gpio-leds"; | |
| 28 | + | |
| 29 | + power { | |
| 30 | + label = "bcm53xx:blue:power"; | |
| 31 | + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; | |
| 32 | + linux,default-trigger = "default-on"; | |
| 33 | + }; | |
| 34 | + | |
| 35 | + usb2 { | |
| 36 | + label = "bcm53xx:blue:usb2"; | |
| 37 | + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; | |
| 38 | + linux,default-trigger = "default-off"; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + wan { | |
| 42 | + label = "bcm53xx:blue:wan"; | |
| 43 | + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; | |
| 44 | + linux,default-trigger = "default-on"; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + lan { | |
| 48 | + label = "bcm53xx:blue:lan"; | |
| 49 | + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; | |
| 50 | + linux,default-trigger = "default-on"; | |
| 51 | + }; | |
| 52 | + | |
| 53 | + usb3 { | |
| 54 | + label = "bcm53xx:blue:usb3"; | |
| 55 | + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; | |
| 56 | + linux,default-trigger = "default-off"; | |
| 57 | + }; | |
| 58 | + }; | |
| 59 | + | |
| 60 | + gpio-keys { | |
| 61 | + compatible = "gpio-keys"; | |
| 62 | + #address-cells = <1>; | |
| 63 | + #size-cells = <0>; | |
| 64 | + poll-interval = <200>; | |
| 65 | + | |
| 66 | + restart { | |
| 67 | + label = "Reset"; | |
| 68 | + linux,code = <KEY_RESTART>; | |
| 69 | + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + wps { | |
| 73 | + label = "WPS"; | |
| 74 | + linux,code = <KEY_WPS_BUTTON>; | |
| 75 | + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; | |
| 76 | + }; | |
| 77 | + }; | |
| 78 | +}; | |
| @@ -0,0 +1,57 @@ | ||
| 1 | +/* | |
| 2 | + * Broadcom BCM470X / BCM5301X ARM platform code. | |
| 3 | + * DTS for Buffalo WZR-600DHP2 | |
| 4 | + * | |
| 5 | + * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com> | |
| 6 | + * | |
| 7 | + * Licensed under the GNU/GPL. See COPYING for details. | |
| 8 | + */ | |
| 9 | + | |
| 10 | +/dts-v1/; | |
| 11 | + | |
| 12 | +#include "bcm47081.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; | |
| 16 | + model = "Buffalo WZR-600DHP2 (BCM47081)"; | |
| 17 | + | |
| 18 | + chosen { | |
| 19 | + bootargs = "console=ttyS0,115200"; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + reg = <0x00000000 0x08000000>; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + gpio-keys { | |
| 27 | + compatible = "gpio-keys"; | |
| 28 | + #address-cells = <1>; | |
| 29 | + #size-cells = <0>; | |
| 30 | + poll-interval = <200>; | |
| 31 | + | |
| 32 | + aoss { | |
| 33 | + label = "AOSS"; | |
| 34 | + linux,code = <KEY_WPS_BUTTON>; | |
| 35 | + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; | |
| 36 | + }; | |
| 37 | + | |
| 38 | + restart { | |
| 39 | + label = "Reset"; | |
| 40 | + linux,code = <KEY_RESTART>; | |
| 41 | + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + /* Switch device mode? */ | |
| 45 | + mode { | |
| 46 | + label = "Mode"; | |
| 47 | + linux,code = <KEY_SETUP>; | |
| 48 | + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; | |
| 49 | + }; | |
| 50 | + | |
| 51 | + eject { | |
| 52 | + label = "USB eject"; | |
| 53 | + linux,code = <KEY_EJECTCD>; | |
| 54 | + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; | |
| 55 | + }; | |
| 56 | + }; | |
| 57 | +}; | |
| @@ -0,0 +1,26 @@ | ||
| 1 | +/* | |
| 2 | + * Broadcom BCM470X / BCM5301X ARM platform code. | |
| 3 | + * DTS for BCM47081 SoC. | |
| 4 | + * | |
| 5 | + * Copyright © 2014 Rafał Miłecki <zajec5@gmail.com> | |
| 6 | + * | |
| 7 | + * Licensed under the GNU/GPL. See COPYING for details. | |
| 8 | + */ | |
| 9 | + | |
| 10 | +#include "bcm5301x.dtsi" | |
| 11 | + | |
| 12 | +/ { | |
| 13 | + compatible = "brcm,bcm47081"; | |
| 14 | + | |
| 15 | + cpus { | |
| 16 | + #address-cells = <1>; | |
| 17 | + #size-cells = <0>; | |
| 18 | + | |
| 19 | + cpu@0 { | |
| 20 | + device_type = "cpu"; | |
| 21 | + compatible = "arm,cortex-a9"; | |
| 22 | + next-level-cache = <&L2>; | |
| 23 | + reg = <0x0>; | |
| 24 | + }; | |
| 25 | + }; | |
| 26 | +}; | |
| @@ -8,6 +8,8 @@ · 7 unmodified lines | ||
| 8 | 8 | * Licensed under the GNU/GPL. See COPYING for details. |
| 9 | 9 | */ |
| 10 | 10 | |
| 11 | +#include <dt-bindings/gpio/gpio.h> | |
| 12 | +#include <dt-bindings/input/input.h> | |
| 11 | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 13 | 15 | #include "skeleton.dtsi" |
| @@ -92,4 +94,53 @@ · 78 unmodified lines | ||
| 92 | 94 | clock-frequency = <400000000>; |
| 93 | 95 | }; |
| 94 | 96 | }; |
| 97 | + | |
| 98 | + axi@18000000 { | |
| 99 | + compatible = "brcm,bus-axi"; | |
| 100 | + reg = <0x18000000 0x1000>; | |
| 101 | + ranges = <0x00000000 0x18000000 0x00100000>; | |
| 102 | + #address-cells = <1>; | |
| 103 | + #size-cells = <1>; | |
| 104 | + | |
| 105 | + #interrupt-cells = <1>; | |
| 106 | + interrupt-map-mask = <0x000fffff 0xffff>; | |
| 107 | + interrupt-map = | |
| 108 | + /* ChipCommon */ | |
| 109 | + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
| 110 | + | |
| 111 | + /* USB 2.0 Controller */ | |
| 112 | + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, | |
| 113 | + | |
| 114 | + /* USB 3.0 Controller */ | |
| 115 | + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, | |
| 116 | + | |
| 117 | + /* Ethernet Controller 0 */ | |
| 118 | + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, | |
| 119 | + | |
| 120 | + /* Ethernet Controller 1 */ | |
| 121 | + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, | |
| 122 | + | |
| 123 | + /* Ethernet Controller 2 */ | |
| 124 | + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
| 125 | + | |
| 126 | + /* Ethernet Controller 3 */ | |
| 127 | + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, | |
| 128 | + | |
| 129 | + /* NAND Controller */ | |
| 130 | + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, | |
| 131 | + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, | |
| 132 | + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
| 133 | + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
| 134 | + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
| 135 | + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, | |
| 136 | + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
| 137 | + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| 138 | + | |
| 139 | + chipcommon: chipcommon@0 { | |
| 140 | + reg = <0x00000000 0x1000>; | |
| 141 | + | |
| 142 | + gpio-controller; | |
| 143 | + #gpio-cells = <2>; | |
| 144 | + }; | |
| 145 | + }; | |
| 95 | 146 | }; |
| @@ -0,0 +1,53 @@ | ||
| 1 | +/* | |
| 2 | + * BSD LICENSE | |
| 3 | + * | |
| 4 | + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. | |
| 5 | + * | |
| 6 | + * Redistribution and use in source and binary forms, with or without | |
| 7 | + * modification, are permitted provided that the following conditions | |
| 8 | + * are met: | |
| 9 | + * | |
| 10 | + * * Redistributions of source code must retain the above copyright | |
| 11 | + * notice, this list of conditions and the following disclaimer. | |
| 12 | + * * Redistributions in binary form must reproduce the above copyright | |
| 13 | + * notice, this list of conditions and the following disclaimer in | |
| 14 | + * the documentation and/or other materials provided with the | |
| 15 | + * distribution. | |
| 16 | + * * Neither the name of Broadcom Corporation nor the names of its | |
| 17 | + * contributors may be used to endorse or promote products derived | |
| 18 | + * from this software without specific prior written permission. | |
| 19 | + * | |
| 20 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 23 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 24 | + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 25 | + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 27 | + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 28 | + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 30 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | + */ | |
| 32 | + | |
| 33 | +/dts-v1/; | |
| 34 | + | |
| 35 | +#include "bcm-cygnus.dtsi" | |
| 36 | + | |
| 37 | +/ { | |
| 38 | + model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; | |
| 39 | + compatible = "brcm,bcm11360", "brcm,cygnus"; | |
| 40 | + | |
| 41 | + aliases { | |
| 42 | + serial0 = &uart3; | |
| 43 | + }; | |
| 44 | + | |
| 45 | + chosen { | |
| 46 | + stdout-path = &uart3; | |
| 47 | + bootargs = "console=ttyS0,115200"; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + uart3: serial@18023000 { | |
| 51 | + status = "okay"; | |
| 52 | + }; | |
| 53 | +}; | |
| @@ -0,0 +1,53 @@ | ||
| 1 | +/* | |
| 2 | + * BSD LICENSE | |
| 3 | + * | |
| 4 | + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. | |
| 5 | + * | |
| 6 | + * Redistribution and use in source and binary forms, with or without | |
| 7 | + * modification, are permitted provided that the following conditions | |
| 8 | + * are met: | |
| 9 | + * | |
| 10 | + * * Redistributions of source code must retain the above copyright | |
| 11 | + * notice, this list of conditions and the following disclaimer. | |
| 12 | + * * Redistributions in binary form must reproduce the above copyright | |
| 13 | + * notice, this list of conditions and the following disclaimer in | |
| 14 | + * the documentation and/or other materials provided with the | |
| 15 | + * distribution. | |
| 16 | + * * Neither the name of Broadcom Corporation nor the names of its | |
| 17 | + * contributors may be used to endorse or promote products derived | |
| 18 | + * from this software without specific prior written permission. | |
| 19 | + * | |
| 20 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 23 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 24 | + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 25 | + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 27 | + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 28 | + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 30 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | + */ | |
| 32 | + | |
| 33 | +/dts-v1/; | |
| 34 | + | |
| 35 | +#include "bcm-cygnus.dtsi" | |
| 36 | + | |
| 37 | +/ { | |
| 38 | + model = "Cygnus SVK (BCM911360K)"; | |
| 39 | + compatible = "brcm,bcm11360", "brcm,cygnus"; | |
| 40 | + | |
| 41 | + aliases { | |
| 42 | + serial0 = &uart3; | |
| 43 | + }; | |
| 44 | + | |
| 45 | + chosen { | |
| 46 | + stdout-path = &uart3; | |
| 47 | + bootargs = "console=ttyS0,115200"; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + uart3: serial@18023000 { | |
| 51 | + status = "okay"; | |
| 52 | + }; | |
| 53 | +}; | |
| @@ -0,0 +1,53 @@ | ||
| 1 | +/* | |
| 2 | + * BSD LICENSE | |
| 3 | + * | |
| 4 | + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. | |
| 5 | + * | |
| 6 | + * Redistribution and use in source and binary forms, with or without | |
| 7 | + * modification, are permitted provided that the following conditions | |
| 8 | + * are met: | |
| 9 | + * | |
| 10 | + * * Redistributions of source code must retain the above copyright | |
| 11 | + * notice, this list of conditions and the following disclaimer. | |
| 12 | + * * Redistributions in binary form must reproduce the above copyright | |
| 13 | + * notice, this list of conditions and the following disclaimer in | |
| 14 | + * the documentation and/or other materials provided with the | |
| 15 | + * distribution. | |
| 16 | + * * Neither the name of Broadcom Corporation nor the names of its | |
| 17 | + * contributors may be used to endorse or promote products derived | |
| 18 | + * from this software without specific prior written permission. | |
| 19 | + * | |
| 20 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 23 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 24 | + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 25 | + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 27 | + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 28 | + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 30 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | + */ | |
| 32 | + | |
| 33 | +/dts-v1/; | |
| 34 | + | |
| 35 | +#include "bcm-cygnus.dtsi" | |
| 36 | + | |
| 37 | +/ { | |
| 38 | + model = "Cygnus SVK (BCM958300K)"; | |
| 39 | + compatible = "brcm,bcm58300", "brcm,cygnus"; | |
| 40 | + | |
| 41 | + aliases { | |
| 42 | + serial0 = &uart3; | |
| 43 | + }; | |
| 44 | + | |
| 45 | + chosen { | |
| 46 | + stdout-path = &uart3; | |
| 47 | + bootargs = "console=ttyS0,115200"; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + uart3: serial@18023000 { | |
| 51 | + status = "okay"; | |
| 52 | + }; | |
| 53 | +}; | |
| @@ -26,4 +26,20 @@ · 25 unmodified lines | ||
| 26 | 26 | }; |
| 27 | 27 | }; |
| 28 | 28 | |
| 29 | +&ahci { status = "okay"; }; | |
| 30 | + | |
| 31 | +ð1 { status = "okay"; }; | |
| 32 | + | |
| 33 | +/* Unpopulated SATA plug on solder side */ | |
| 34 | +&sata0 { status = "okay"; }; | |
| 35 | + | |
| 36 | +&sata_phy { status = "okay"; }; | |
| 37 | + | |
| 38 | +/* Samsung M8G2FA 8GB eMMC */ | |
| 39 | +&sdhci2 { | |
| 40 | + non-removable; | |
| 41 | + bus-width = <8>; | |
| 42 | + status = "okay"; | |
| 43 | +}; | |
| 44 | + | |
| 29 | 45 | &uart0 { status = "okay"; }; |
| @@ -53,6 +53,35 @@ · 52 unmodified lines | ||
| 53 | 53 | |
| 54 | 54 | ranges = <0 0xf7000000 0x1000000>; |
| 55 | 55 | |
| 56 | + sdhci0: sdhci@ab0000 { | |
| 57 | + compatible = "mrvl,pxav3-mmc"; | |
| 58 | + reg = <0xab0000 0x200>; | |
| 59 | + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; | |
| 60 | + clock-names = "io", "core"; | |
| 61 | + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 62 | + status = "disabled"; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + sdhci1: sdhci@ab0800 { | |
| 66 | + compatible = "mrvl,pxav3-mmc"; | |
| 67 | + reg = <0xab0800 0x200>; | |
| 68 | + clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; | |
| 69 | + clock-names = "io", "core"; | |
| 70 | + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 71 | + status = "disabled"; | |
| 72 | + }; | |
| 73 | + | |
| 74 | + sdhci2: sdhci@ab1000 { | |
| 75 | + compatible = "mrvl,pxav3-mmc"; | |
| 76 | + reg = <0xab1000 0x200>; | |
| 77 | + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
| 78 | + clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; | |
| 79 | + clock-names = "io", "core"; | |
| 80 | + pinctrl-0 = <&emmc_pmux>; | |
| 81 | + pinctrl-names = "default"; | |
| 82 | + status = "disabled"; | |
| 83 | + }; | |
| 84 | + | |
| 56 | 85 | l2: l2-cache-controller@ac0000 { |
| 57 | 86 | compatible = "marvell,tauros3-cache", "arm,pl310-cache"; |
| 58 | 87 | reg = <0xac0000 0x1000>; |
| @@ -79,11 +108,47 @@ · 20 unmodified lines | ||
| 79 | 108 | clocks = <&chip CLKID_TWD>; |
| 80 | 109 | }; |
| 81 | 110 | |
| 111 | + eth1: ethernet@b90000 { | |
| 112 | + compatible = "marvell,pxa168-eth"; | |
| 113 | + reg = <0xb90000 0x10000>; | |
| 114 | + clocks = <&chip CLKID_GETH1>; | |
| 115 | + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 116 | + /* set by bootloader */ | |
| 117 | + local-mac-address = [00 00 00 00 00 00]; | |
| 118 | + #address-cells = <1>; | |
| 119 | + #size-cells = <0>; | |
| 120 | + phy-connection-type = "mii"; | |
| 121 | + phy-handle = <ðphy1>; | |
| 122 | + status = "disabled"; | |
| 123 | + | |
| 124 | + ethphy1: ethernet-phy@0 { | |
| 125 | + reg = <0>; | |
| 126 | + }; | |
| 127 | + }; | |
| 128 | + | |
| 82 | 129 | cpu-ctrl@dd0000 { |
| 83 | 130 | compatible = "marvell,berlin-cpu-ctrl"; |
| 84 | 131 | reg = <0xdd0000 0x10000>; |
| 85 | 132 | }; |
| 86 | 133 | |
| 134 | + eth0: ethernet@e50000 { | |
| 135 | + compatible = "marvell,pxa168-eth"; | |
| 136 | + reg = <0xe50000 0x10000>; | |
| 137 | + clocks = <&chip CLKID_GETH0>; | |
| 138 | + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 139 | + /* set by bootloader */ | |
| 140 | + local-mac-address = [00 00 00 00 00 00]; | |
| 141 | + #address-cells = <1>; | |
| 142 | + #size-cells = <0>; | |
| 143 | + phy-connection-type = "mii"; | |
| 144 | + phy-handle = <ðphy0>; | |
| 145 | + status = "disabled"; | |
| 146 | + | |
| 147 | + ethphy0: ethernet-phy@0 { | |
| 148 | + reg = <0>; | |
| 149 | + }; | |
| 150 | + }; | |
| 151 | + | |
| 87 | 152 | apb@e80000 { |
| 88 | 153 | compatible = "simple-bus"; |
| 89 | 154 | #address-cells = <1>; |
| @@ -246,12 +311,57 @@ · 156 unmodified lines | ||
| 246 | 311 | }; |
| 247 | 312 | }; |
| 248 | 313 | |
| 314 | + ahci: sata@e90000 { | |
| 315 | + compatible = "marvell,berlin2-ahci", "generic-ahci"; | |
| 316 | + reg = <0xe90000 0x1000>; | |
| 317 | + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 318 | + clocks = <&chip CLKID_SATA>; | |
| 319 | + #address-cells = <1>; | |
| 320 | + #size-cells = <0>; | |
| 321 | + | |
| 322 | + sata0: sata-port@0 { | |
| 323 | + reg = <0>; | |
| 324 | + phys = <&sata_phy 0>; | |
| 325 | + status = "disabled"; | |
| 326 | + }; | |
| 327 | + | |
| 328 | + sata1: sata-port@1 { | |
| 329 | + reg = <1>; | |
| 330 | + phys = <&sata_phy 1>; | |
| 331 | + status = "disabled"; | |
| 332 | + }; | |
| 333 | + }; | |
| 334 | + | |
| 335 | + sata_phy: phy@e900a0 { | |
| 336 | + compatible = "marvell,berlin2-sata-phy"; | |
| 337 | + reg = <0xe900a0 0x200>; | |
| 338 | + clocks = <&chip CLKID_SATA>; | |
| 339 | + #address-cells = <1>; | |
| 340 | + #size-cells = <0>; | |
| 341 | + #phy-cells = <1>; | |
| 342 | + status = "disabled"; | |
| 343 | + | |
| 344 | + sata-phy@0 { | |
| 345 | + reg = <0>; | |
| 346 | + }; | |
| 347 | + | |
| 348 | + sata-phy@1 { | |
| 349 | + reg = <1>; | |
| 350 | + }; | |
| 351 | + }; | |
| 352 | + | |
| 249 | 353 | chip: chip-control@ea0000 { |
| 250 | 354 | compatible = "marvell,berlin2-chip-ctrl"; |
| 251 | 355 | #clock-cells = <1>; |
| 356 | + #reset-cells = <2>; | |
| 252 | 357 | reg = <0xea0000 0x400>; |
| 253 | 358 | clocks = <&refclk>; |
| 254 | 359 | clock-names = "refclk"; |
| 360 | + | |
| 361 | + emmc_pmux: emmc-pmux { | |
| 362 | + groups = "G26"; | |
| 363 | + function = "emmc"; | |
| 364 | + }; | |
| 255 | 365 | }; |
| 256 | 366 | |
| 257 | 367 | apb@fc0000 { |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | ||
| 11 | 11 | /dts-v1/; |
| 12 | 12 | |
| 13 | 13 | #include "berlin2cd.dtsi" |
| 14 | +#include <dt-bindings/gpio/gpio.h> | |
| 14 | 15 | |
| 15 | 16 | / { |
| 16 | 17 | model = "Google Chromecast"; |
| @@ -24,6 +25,35 @@ · 7 unmodified lines | ||
| 24 | 25 | device_type = "memory"; |
| 25 | 26 | reg = <0x00000000 0x20000000>; /* 512 MB */ |
| 26 | 27 | }; |
| 28 | + | |
| 29 | + leds { | |
| 30 | + compatible = "gpio-leds"; | |
| 31 | + | |
| 32 | + white { | |
| 33 | + label = "white"; | |
| 34 | + gpios = <&portc 1 GPIO_ACTIVE_HIGH>; | |
| 35 | + default-state = "keep"; | |
| 36 | + }; | |
| 37 | + | |
| 38 | + red { | |
| 39 | + label = "red"; | |
| 40 | + gpios = <&portc 2 GPIO_ACTIVE_HIGH>; | |
| 41 | + default-state = "keep"; | |
| 42 | + }; | |
| 43 | + }; | |
| 44 | +}; | |
| 45 | + | |
| 46 | +/* | |
| 47 | + * AzureWave AW-NH387 (Marvell 88W8787) | |
| 48 | + * 802.11b/g/n + Bluetooth 2.1 | |
| 49 | + */ | |
| 50 | +&sdhci0 { | |
| 51 | + non-removable; | |
| 52 | + status = "okay"; | |
| 27 | 53 | }; |
| 28 | 54 | |
| 29 | 55 | &uart0 { status = "okay"; }; |
| 56 | + | |
| 57 | +&usb_phy1 { status = "okay"; }; | |
| 58 | + | |
| 59 | +&usb1 { status = "okay"; }; | |
| @@ -45,6 +45,15 @@ · 44 unmodified lines | ||
| 45 | 45 | |
| 46 | 46 | ranges = <0 0xf7000000 0x1000000>; |
| 47 | 47 | |
| 48 | + sdhci0: sdhci@ab0000 { | |
| 49 | + compatible = "mrvl,pxav3-mmc"; | |
| 50 | + reg = <0xab0000 0x200>; | |
| 51 | + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; | |
| 52 | + clock-names = "io", "core"; | |
| 53 | + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 54 | + status = "disabled"; | |
| 55 | + }; | |
| 56 | + | |
| 48 | 57 | l2: l2-cache-controller@ac0000 { |
| 49 | 58 | compatible = "arm,pl310-cache"; |
| 50 | 59 | reg = <0xac0000 0x1000>; |
| @@ -66,6 +75,58 @@ · 15 unmodified lines | ||
| 66 | 75 | clocks = <&chip CLKID_TWD>; |
| 67 | 76 | }; |
| 68 | 77 | |
| 78 | + usb_phy0: usb-phy@b74000 { | |
| 79 | + compatible = "marvell,berlin2cd-usb-phy"; | |
| 80 | + reg = <0xb74000 0x128>; | |
| 81 | + #phy-cells = <0>; | |
| 82 | + resets = <&chip 0x178 23>; | |
| 83 | + status = "disabled"; | |
| 84 | + }; | |
| 85 | + | |
| 86 | + usb_phy1: usb-phy@b78000 { | |
| 87 | + compatible = "marvell,berlin2cd-usb-phy"; | |
| 88 | + reg = <0xb78000 0x128>; | |
| 89 | + #phy-cells = <0>; | |
| 90 | + resets = <&chip 0x178 24>; | |
| 91 | + status = "disabled"; | |
| 92 | + }; | |
| 93 | + | |
| 94 | + eth1: ethernet@b90000 { | |
| 95 | + compatible = "marvell,pxa168-eth"; | |
| 96 | + reg = <0xb90000 0x10000>; | |
| 97 | + clocks = <&chip CLKID_GETH1>; | |
| 98 | + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 99 | + /* set by bootloader */ | |
| 100 | + local-mac-address = [00 00 00 00 00 00]; | |
| 101 | + #address-cells = <1>; | |
| 102 | + #size-cells = <0>; | |
| 103 | + phy-connection-type = "mii"; | |
| 104 | + phy-handle = <ðphy1>; | |
| 105 | + status = "disabled"; | |
| 106 | + | |
| 107 | + ethphy1: ethernet-phy@0 { | |
| 108 | + reg = <0>; | |
| 109 | + }; | |
| 110 | + }; | |
| 111 | + | |
| 112 | + eth0: ethernet@e50000 { | |
| 113 | + compatible = "marvell,pxa168-eth"; | |
| 114 | + reg = <0xe50000 0x10000>; | |
| 115 | + clocks = <&chip CLKID_GETH0>; | |
| 116 | + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 117 | + /* set by bootloader */ | |
| 118 | + local-mac-address = [00 00 00 00 00 00]; | |
| 119 | + #address-cells = <1>; | |
| 120 | + #size-cells = <0>; | |
| 121 | + phy-connection-type = "mii"; | |
| 122 | + phy-handle = <ðphy0>; | |
| 123 | + status = "disabled"; | |
| 124 | + | |
| 125 | + ethphy0: ethernet-phy@0 { | |
| 126 | + reg = <0>; | |
| 127 | + }; | |
| 128 | + }; | |
| 129 | + | |
| 69 | 130 | apb@e80000 { |
| 70 | 131 | compatible = "simple-bus"; |
| 71 | 132 | #address-cells = <1>; |
| @@ -231,6 +292,7 @@ · 159 unmodified lines | ||
| 231 | 292 | chip: chip-control@ea0000 { |
| 232 | 293 | compatible = "marvell,berlin2cd-chip-ctrl"; |
| 233 | 294 | #clock-cells = <1>; |
| 295 | + #reset-cells = <2>; | |
| 234 | 296 | reg = <0xea0000 0x400>; |
| 235 | 297 | clocks = <&refclk>; |
| 236 | 298 | clock-names = "refclk"; |
| @@ -241,6 +303,26 @@ · 4 unmodified lines | ||
| 241 | 303 | }; |
| 242 | 304 | }; |
| 243 | 305 | |
| 306 | + usb0: usb@ed0000 { | |
| 307 | + compatible = "chipidea,usb2"; | |
| 308 | + reg = <0xed0000 0x200>; | |
| 309 | + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 310 | + clocks = <&chip CLKID_USB0>; | |
| 311 | + phys = <&usb_phy0>; | |
| 312 | + phy-names = "usb-phy"; | |
| 313 | + status = "disabled"; | |
| 314 | + }; | |
| 315 | + | |
| 316 | + usb1: usb@ee0000 { | |
| 317 | + compatible = "chipidea,usb2"; | |
| 318 | + reg = <0xee0000 0x200>; | |
| 319 | + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 320 | + clocks = <&chip CLKID_USB1>; | |
| 321 | + phys = <&usb_phy1>; | |
| 322 | + phy-names = "usb-phy"; | |
| 323 | + status = "disabled"; | |
| 324 | + }; | |
| 325 | + | |
| 244 | 326 | apb@fc0000 { |
| 245 | 327 | compatible = "simple-bus"; |
| 246 | 328 | #address-cells = <1>; |
| @@ -7,6 +7,8 @@ · 6 unmodified lines | ||
| 7 | 7 | */ |
| 8 | 8 | |
| 9 | 9 | /dts-v1/; |
| 10 | + | |
| 11 | +#include <dt-bindings/gpio/gpio.h> | |
| 10 | 12 | #include "berlin2q.dtsi" |
| 11 | 13 | |
| 12 | 14 | / { |
| @@ -21,6 +23,39 @@ · 8 unmodified lines | ||
| 21 | 23 | choosen { |
| 22 | 24 | bootargs = "console=ttyS0,115200 earlyprintk"; |
| 23 | 25 | }; |
| 26 | + | |
| 27 | + regulators { | |
| 28 | + compatible = "simple-bus"; | |
| 29 | + #address-cells = <1>; | |
| 30 | + #size-cells = <0>; | |
| 31 | + | |
| 32 | + reg_usb0_vbus: regulator@0 { | |
| 33 | + compatible = "regulator-fixed"; | |
| 34 | + regulator-name = "usb0_vbus"; | |
| 35 | + regulator-min-microvolt = <5000000>; | |
| 36 | + regulator-max-microvolt = <5000000>; | |
| 37 | + gpio = <&portb 8 GPIO_ACTIVE_HIGH>; | |
| 38 | + enable-active-high; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + reg_usb1_vbus: regulator@1 { | |
| 42 | + compatible = "regulator-fixed"; | |
| 43 | + regulator-name = "usb1_vbus"; | |
| 44 | + regulator-min-microvolt = <5000000>; | |
| 45 | + regulator-max-microvolt = <5000000>; | |
| 46 | + gpio = <&portb 10 GPIO_ACTIVE_HIGH>; | |
| 47 | + enable-active-high; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + reg_usb2_vbus: regulator@2 { | |
| 51 | + compatible = "regulator-fixed"; | |
| 52 | + regulator-name = "usb2_vbus"; | |
| 53 | + regulator-min-microvolt = <5000000>; | |
| 54 | + regulator-max-microvolt = <5000000>; | |
| 55 | + gpio = <&portb 12 GPIO_ACTIVE_HIGH>; | |
| 56 | + enable-active-high; | |
| 57 | + }; | |
| 58 | + }; | |
| 24 | 59 | }; |
| 25 | 60 | |
| 26 | 61 | &sdhci1 { |
| @@ -46,6 +81,32 @@ · 19 unmodified lines | ||
| 46 | 81 | status = "okay"; |
| 47 | 82 | }; |
| 48 | 83 | |
| 84 | +&usb_phy0 { | |
| 85 | + status = "okay"; | |
| 86 | +}; | |
| 87 | + | |
| 88 | +&usb_phy2 { | |
| 89 | + status = "okay"; | |
| 90 | +}; | |
| 91 | + | |
| 92 | +&usb0 { | |
| 93 | + vbus-supply = <®_usb0_vbus>; | |
| 94 | + status = "okay"; | |
| 95 | +}; | |
| 96 | + | |
| 97 | +&usb2 { | |
| 98 | + vbus-supply = <®_usb2_vbus>; | |
| 99 | + status = "okay"; | |
| 100 | +}; | |
| 101 | + | |
| 49 | 102 | ð0 { |
| 50 | 103 | status = "okay"; |
| 51 | 104 | }; |
| 105 | + | |
| 106 | +&sata0 { | |
| 107 | + status = "okay"; | |
| 108 | +}; | |
| 109 | + | |
| 110 | +&sata_phy { | |
| 111 | + status = "okay"; | |
| 112 | +}; | |
| @@ -114,6 +114,40 @@ · 113 unmodified lines | ||
| 114 | 114 | #interrupt-cells = <3>; |
| 115 | 115 | }; |
| 116 | 116 | |
| 117 | + usb_phy2: phy@a2f400 { | |
| 118 | + compatible = "marvell,berlin2-usb-phy"; | |
| 119 | + reg = <0xa2f400 0x128>; | |
| 120 | + #phy-cells = <0>; | |
| 121 | + resets = <&chip 0x104 14>; | |
| 122 | + status = "disabled"; | |
| 123 | + }; | |
| 124 | + | |
| 125 | + usb2: usb@a30000 { | |
| 126 | + compatible = "chipidea,usb2"; | |
| 127 | + reg = <0xa30000 0x10000>; | |
| 128 | + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
| 129 | + clocks = <&chip CLKID_USB2>; | |
| 130 | + phys = <&usb_phy2>; | |
| 131 | + phy-names = "usb-phy"; | |
| 132 | + status = "disabled"; | |
| 133 | + }; | |
| 134 | + | |
| 135 | + usb_phy0: phy@b74000 { | |
| 136 | + compatible = "marvell,berlin2-usb-phy"; | |
| 137 | + reg = <0xb74000 0x128>; | |
| 138 | + #phy-cells = <0>; | |
| 139 | + resets = <&chip 0x104 12>; | |
| 140 | + status = "disabled"; | |
| 141 | + }; | |
| 142 | + | |
| 143 | + usb_phy1: phy@b78000 { | |
| 144 | + compatible = "marvell,berlin2-usb-phy"; | |
| 145 | + reg = <0xb78000 0x128>; | |
| 146 | + #phy-cells = <0>; | |
| 147 | + resets = <&chip 0x104 13>; | |
| 148 | + status = "disabled"; | |
| 149 | + }; | |
| 150 | + | |
| 117 | 151 | eth0: ethernet@b90000 { |
| 118 | 152 | compatible = "marvell,pxa168-eth"; |
| 119 | 153 | reg = <0xb90000 0x10000>; |
| @@ -123,6 +157,7 @@ · 3 unmodified lines | ||
| 123 | 157 | local-mac-address = [00 00 00 00 00 00]; |
| 124 | 158 | #address-cells = <1>; |
| 125 | 159 | #size-cells = <0>; |
| 160 | + phy-connection-type = "mii"; | |
| 126 | 161 | phy-handle = <ðphy0>; |
| 127 | 162 | status = "disabled"; |
| 128 | 163 | |
| @@ -255,7 +290,6 @@ · 126 unmodified lines | ||
| 255 | 290 | reg = <0x2c14 0x14>; |
| 256 | 291 | clocks = <&chip CLKID_CFG>; |
| 257 | 292 | clock-names = "timer"; |
| 258 | − status = "disabled"; | |
| 259 | 293 | }; |
| 260 | 294 | |
| 261 | 295 | timer2: timer@2c28 { |
| @@ -349,6 +383,7 @@ · 87 unmodified lines | ||
| 349 | 383 | chip: chip-control@ea0000 { |
| 350 | 384 | compatible = "marvell,berlin2q-chip-ctrl"; |
| 351 | 385 | #clock-cells = <1>; |
| 386 | + #reset-cells = <2>; | |
| 352 | 387 | reg = <0xea0000 0x400>, <0xdd0170 0x10>; |
| 353 | 388 | clocks = <&refclk>; |
| 354 | 389 | clock-names = "refclk"; |
| @@ -364,6 +399,65 @@ · 9 unmodified lines | ||
| 364 | 399 | }; |
| 365 | 400 | }; |
| 366 | 401 | |
| 402 | + ahci: sata@e90000 { | |
| 403 | + compatible = "marvell,berlin2q-ahci", "generic-ahci"; | |
| 404 | + reg = <0xe90000 0x1000>; | |
| 405 | + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 406 | + clocks = <&chip CLKID_SATA>; | |
| 407 | + #address-cells = <1>; | |
| 408 | + #size-cells = <0>; | |
| 409 | + | |
| 410 | + sata0: sata-port@0 { | |
| 411 | + reg = <0>; | |
| 412 | + phys = <&sata_phy 0>; | |
| 413 | + status = "disabled"; | |
| 414 | + }; | |
| 415 | + | |
| 416 | + sata1: sata-port@1 { | |
| 417 | + reg = <1>; | |
| 418 | + phys = <&sata_phy 1>; | |
| 419 | + status = "disabled"; | |
| 420 | + }; | |
| 421 | + }; | |
| 422 | + | |
| 423 | + sata_phy: phy@e900a0 { | |
| 424 | + compatible = "marvell,berlin2q-sata-phy"; | |
| 425 | + reg = <0xe900a0 0x200>; | |
| 426 | + clocks = <&chip CLKID_SATA>; | |
| 427 | + #address-cells = <1>; | |
| 428 | + #size-cells = <0>; | |
| 429 | + #phy-cells = <1>; | |
| 430 | + status = "disabled"; | |
| 431 | + | |
| 432 | + sata-phy@0 { | |
| 433 | + reg = <0>; | |
| 434 | + }; | |
| 435 | + | |
| 436 | + sata-phy@1 { | |
| 437 | + reg = <1>; | |
| 438 | + }; | |
| 439 | + }; | |
| 440 | + | |
| 441 | + usb0: usb@ed0000 { | |
| 442 | + compatible = "chipidea,usb2"; | |
| 443 | + reg = <0xed0000 0x10000>; | |
| 444 | + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 445 | + clocks = <&chip CLKID_USB0>; | |
| 446 | + phys = <&usb_phy0>; | |
| 447 | + phy-names = "usb-phy"; | |
| 448 | + status = "disabled"; | |
| 449 | + }; | |
| 450 | + | |
| 451 | + usb1: usb@ee0000 { | |
| 452 | + compatible = "chipidea,usb2"; | |
| 453 | + reg = <0xee0000 0x10000>; | |
| 454 | + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 455 | + clocks = <&chip CLKID_USB1>; | |
| 456 | + phys = <&usb_phy1>; | |
| 457 | + phy-names = "usb-phy"; | |
| 458 | + status = "disabled"; | |
| 459 | + }; | |
| 460 | + | |
| 367 | 461 | apb@fc0000 { |
| 368 | 462 | compatible = "simple-bus"; |
| 369 | 463 | #address-cells = <1>; |
| @@ -171,6 +171,101 @@ · 170 unmodified lines | ||
| 171 | 171 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ |
| 172 | 172 | >; |
| 173 | 173 | }; |
| 174 | + | |
| 175 | + cpsw_default: cpsw_default { | |
| 176 | + pinctrl-single,pins = < | |
| 177 | + /* Slave 1 */ | |
| 178 | + 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ | |
| 179 | + 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ | |
| 180 | + 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ | |
| 181 | + 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ | |
| 182 | + 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ | |
| 183 | + 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ | |
| 184 | + 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ | |
| 185 | + 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ | |
| 186 | + 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ | |
| 187 | + 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ | |
| 188 | + 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ | |
| 189 | + 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ | |
| 190 | + | |
| 191 | + /* Slave 2 */ | |
| 192 | + 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ | |
| 193 | + 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ | |
| 194 | + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ | |
| 195 | + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ | |
| 196 | + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ | |
| 197 | + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ | |
| 198 | + 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ | |
| 199 | + 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ | |
| 200 | + 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ | |
| 201 | + 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ | |
| 202 | + 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ | |
| 203 | + 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ | |
| 204 | + >; | |
| 205 | + | |
| 206 | + }; | |
| 207 | + | |
| 208 | + cpsw_sleep: cpsw_sleep { | |
| 209 | + pinctrl-single,pins = < | |
| 210 | + /* Slave 1 */ | |
| 211 | + 0x250 (MUX_MODE15) | |
| 212 | + 0x254 (MUX_MODE15) | |
| 213 | + 0x258 (MUX_MODE15) | |
| 214 | + 0x25c (MUX_MODE15) | |
| 215 | + 0x260 (MUX_MODE15) | |
| 216 | + 0x264 (MUX_MODE15) | |
| 217 | + 0x268 (MUX_MODE15) | |
| 218 | + 0x26c (MUX_MODE15) | |
| 219 | + 0x270 (MUX_MODE15) | |
| 220 | + 0x274 (MUX_MODE15) | |
| 221 | + 0x278 (MUX_MODE15) | |
| 222 | + 0x27c (MUX_MODE15) | |
| 223 | + | |
| 224 | + /* Slave 2 */ | |
| 225 | + 0x198 (MUX_MODE15) | |
| 226 | + 0x19c (MUX_MODE15) | |
| 227 | + 0x1a0 (MUX_MODE15) | |
| 228 | + 0x1a4 (MUX_MODE15) | |
| 229 | + 0x1a8 (MUX_MODE15) | |
| 230 | + 0x1ac (MUX_MODE15) | |
| 231 | + 0x1b0 (MUX_MODE15) | |
| 232 | + 0x1b4 (MUX_MODE15) | |
| 233 | + 0x1b8 (MUX_MODE15) | |
| 234 | + 0x1bc (MUX_MODE15) | |
| 235 | + 0x1c0 (MUX_MODE15) | |
| 236 | + 0x1c4 (MUX_MODE15) | |
| 237 | + >; | |
| 238 | + }; | |
| 239 | + | |
| 240 | + davinci_mdio_default: davinci_mdio_default { | |
| 241 | + pinctrl-single,pins = < | |
| 242 | + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ | |
| 243 | + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
| 244 | + >; | |
| 245 | + }; | |
| 246 | + | |
| 247 | + davinci_mdio_sleep: davinci_mdio_sleep { | |
| 248 | + pinctrl-single,pins = < | |
| 249 | + 0x23c (MUX_MODE15) | |
| 250 | + 0x240 (MUX_MODE15) | |
| 251 | + >; | |
| 252 | + }; | |
| 253 | + | |
| 254 | + dcan1_pins_default: dcan1_pins_default { | |
| 255 | + pinctrl-single,pins = < | |
| 256 | + 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ | |
| 257 | + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ | |
| 258 | + 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */ | |
| 259 | + >; | |
| 260 | + }; | |
| 261 | + | |
| 262 | + dcan1_pins_sleep: dcan1_pins_sleep { | |
| 263 | + pinctrl-single,pins = < | |
| 264 | + 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ | |
| 265 | + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ | |
| 266 | + 0x418 (MUX_MODE15) /* wakeup0.off */ | |
| 267 | + >; | |
| 268 | + }; | |
| 174 | 269 | }; |
| 175 | 270 | |
| 176 | 271 | &i2c1 { |
| @@ -201,6 +296,7 @@ · 24 unmodified lines | ||
| 201 | 296 | regulator-name = "smps45"; |
| 202 | 297 | regulator-min-microvolt = < 850000>; |
| 203 | 298 | regulator-max-microvolt = <1150000>; |
| 299 | + regulator-always-on; | |
| 204 | 300 | regulator-boot-on; |
| 205 | 301 | }; |
| 206 | 302 | |
| @@ -209,6 +305,7 @@ · 2 unmodified lines | ||
| 209 | 305 | regulator-name = "smps6"; |
| 210 | 306 | regulator-min-microvolt = <850000>; |
| 211 | 307 | regulator-max-microvolt = <12500000>; |
| 308 | + regulator-always-on; | |
| 212 | 309 | regulator-boot-on; |
| 213 | 310 | }; |
| 214 | 311 | |
| @@ -226,6 +323,7 @@ · 11 unmodified lines | ||
| 226 | 323 | regulator-name = "smps8"; |
| 227 | 324 | regulator-min-microvolt = < 850000>; |
| 228 | 325 | regulator-max-microvolt = <1250000>; |
| 326 | + regulator-always-on; | |
| 229 | 327 | regulator-boot-on; |
| 230 | 328 | }; |
| 231 | 329 | |
| @@ -252,6 +350,7 @@ · 20 unmodified lines | ||
| 252 | 350 | regulator-name = "ldo2"; |
| 253 | 351 | regulator-min-microvolt = <3300000>; |
| 254 | 352 | regulator-max-microvolt = <3300000>; |
| 353 | + regulator-always-on; | |
| 255 | 354 | regulator-boot-on; |
| 256 | 355 | }; |
| 257 | 356 | |
| @@ -269,6 +368,7 @@ · 11 unmodified lines | ||
| 269 | 368 | regulator-name = "ldo9"; |
| 270 | 369 | regulator-min-microvolt = <1050000>; |
| 271 | 370 | regulator-max-microvolt = <1050000>; |
| 371 | + regulator-always-on; | |
| 272 | 372 | regulator-boot-on; |
| 273 | 373 | }; |
| 274 | 374 | |
| @@ -528,3 +628,36 @@ · 253 unmodified lines | ||
| 528 | 628 | ti,no-reset-on-init; |
| 529 | 629 | ti,no-idle-on-init; |
| 530 | 630 | }; |
| 631 | + | |
| 632 | +&mac { | |
| 633 | + status = "okay"; | |
| 634 | + pinctrl-names = "default", "sleep"; | |
| 635 | + pinctrl-0 = <&cpsw_default>; | |
| 636 | + pinctrl-1 = <&cpsw_sleep>; | |
| 637 | + dual_emac; | |
| 638 | +}; | |
| 639 | + | |
| 640 | +&cpsw_emac0 { | |
| 641 | + phy_id = <&davinci_mdio>, <2>; | |
| 642 | + phy-mode = "rgmii"; | |
| 643 | + dual_emac_res_vlan = <1>; | |
| 644 | +}; | |
| 645 | + | |
| 646 | +&cpsw_emac1 { | |
| 647 | + phy_id = <&davinci_mdio>, <3>; | |
| 648 | + phy-mode = "rgmii"; | |
| 649 | + dual_emac_res_vlan = <2>; | |
| 650 | +}; | |
| 651 | + | |
| 652 | +&davinci_mdio { | |
| 653 | + pinctrl-names = "default", "sleep"; | |
| 654 | + pinctrl-0 = <&davinci_mdio_default>; | |
| 655 | + pinctrl-1 = <&davinci_mdio_sleep>; | |
| 656 | +}; | |
| 657 | + | |
| 658 | +&dcan1 { | |
| 659 | + status = "ok"; | |
| 660 | + pinctrl-names = "default", "sleep"; | |
| 661 | + pinctrl-0 = <&dcan1_pins_default>; | |
| 662 | + pinctrl-1 = <&dcan1_pins_sleep>; | |
| 663 | +}; | |
| @@ -34,6 +34,14 @@ · 33 unmodified lines | ||
| 34 | 34 | serial3 = &uart4; |
| 35 | 35 | serial4 = &uart5; |
| 36 | 36 | serial5 = &uart6; |
| 37 | + serial6 = &uart7; | |
| 38 | + serial7 = &uart8; | |
| 39 | + serial8 = &uart9; | |
| 40 | + serial9 = &uart10; | |
| 41 | + ethernet0 = &cpsw_emac0; | |
| 42 | + ethernet1 = &cpsw_emac1; | |
| 43 | + d_can0 = &dcan1; | |
| 44 | + d_can1 = &dcan2; | |
| 37 | 45 | }; |
| 38 | 46 | |
| 39 | 47 | timer { |
| @@ -201,6 +209,11 @@ · 161 unmodified lines | ||
| 201 | 209 | ti,hwmods = "counter_32k"; |
| 202 | 210 | }; |
| 203 | 211 | |
| 212 | + dra7_ctrl_core: ctrl_core@4a002000 { | |
| 213 | + compatible = "syscon"; | |
| 214 | + reg = <0x4a002000 0x6d0>; | |
| 215 | + }; | |
| 216 | + | |
| 204 | 217 | dra7_ctrl_general: tisyscon@4a002e00 { |
| 205 | 218 | compatible = "syscon"; |
| 206 | 219 | reg = <0x4a002e00 0x7c>; |
| @@ -335,6 +348,8 @@ · 128 unmodified lines | ||
| 335 | 348 | ti,hwmods = "uart1"; |
| 336 | 349 | clock-frequency = <48000000>; |
| 337 | 350 | status = "disabled"; |
| 351 | + dmas = <&sdma 49>, <&sdma 50>; | |
| 352 | + dma-names = "tx", "rx"; | |
| 338 | 353 | }; |
| 339 | 354 | |
| 340 | 355 | uart2: serial@4806c000 { |
| @@ -344,6 +359,8 @@ · 3 unmodified lines | ||
| 344 | 359 | ti,hwmods = "uart2"; |
| 345 | 360 | clock-frequency = <48000000>; |
| 346 | 361 | status = "disabled"; |
| 362 | + dmas = <&sdma 51>, <&sdma 52>; | |
| 363 | + dma-names = "tx", "rx"; | |
| 347 | 364 | }; |
| 348 | 365 | |
| 349 | 366 | uart3: serial@48020000 { |
| @@ -353,6 +370,8 @@ · 3 unmodified lines | ||
| 353 | 370 | ti,hwmods = "uart3"; |
| 354 | 371 | clock-frequency = <48000000>; |
| 355 | 372 | status = "disabled"; |
| 373 | + dmas = <&sdma 53>, <&sdma 54>; | |
| 374 | + dma-names = "tx", "rx"; | |
| 356 | 375 | }; |
| 357 | 376 | |
| 358 | 377 | uart4: serial@4806e000 { |
| @@ -362,6 +381,8 @@ · 3 unmodified lines | ||
| 362 | 381 | ti,hwmods = "uart4"; |
| 363 | 382 | clock-frequency = <48000000>; |
| 364 | 383 | status = "disabled"; |
| 384 | + dmas = <&sdma 55>, <&sdma 56>; | |
| 385 | + dma-names = "tx", "rx"; | |
| 365 | 386 | }; |
| 366 | 387 | |
| 367 | 388 | uart5: serial@48066000 { |
| @@ -371,6 +392,8 @@ · 3 unmodified lines | ||
| 371 | 392 | ti,hwmods = "uart5"; |
| 372 | 393 | clock-frequency = <48000000>; |
| 373 | 394 | status = "disabled"; |
| 395 | + dmas = <&sdma 63>, <&sdma 64>; | |
| 396 | + dma-names = "tx", "rx"; | |
| 374 | 397 | }; |
| 375 | 398 | |
| 376 | 399 | uart6: serial@48068000 { |
| @@ -380,6 +403,8 @@ · 3 unmodified lines | ||
| 380 | 403 | ti,hwmods = "uart6"; |
| 381 | 404 | clock-frequency = <48000000>; |
| 382 | 405 | status = "disabled"; |
| 406 | + dmas = <&sdma 79>, <&sdma 80>; | |
| 407 | + dma-names = "tx", "rx"; | |
| 383 | 408 | }; |
| 384 | 409 | |
| 385 | 410 | uart7: serial@48420000 { |
| @@ -421,7 +446,11 @@ · 35 unmodified lines | ||
| 421 | 446 | mailbox1: mailbox@4a0f4000 { |
| 422 | 447 | compatible = "ti,omap4-mailbox"; |
| 423 | 448 | reg = <0x4a0f4000 0x200>; |
| 449 | + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, | |
| 450 | + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 451 | + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
| 424 | 452 | ti,hwmods = "mailbox1"; |
| 453 | + #mbox-cells = <1>; | |
| 425 | 454 | ti,mbox-num-users = <3>; |
| 426 | 455 | ti,mbox-num-fifos = <8>; |
| 427 | 456 | status = "disabled"; |
| @@ -430,7 +459,12 @@ · 2 unmodified lines | ||
| 430 | 459 | mailbox2: mailbox@4883a000 { |
| 431 | 460 | compatible = "ti,omap4-mailbox"; |
| 432 | 461 | reg = <0x4883a000 0x200>; |
| 462 | + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, | |
| 463 | + <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, | |
| 464 | + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
| 465 | + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
| 433 | 466 | ti,hwmods = "mailbox2"; |
| 467 | + #mbox-cells = <1>; | |
| 434 | 468 | ti,mbox-num-users = <4>; |
| 435 | 469 | ti,mbox-num-fifos = <12>; |
| 436 | 470 | status = "disabled"; |
| @@ -439,7 +473,12 @@ · 2 unmodified lines | ||
| 439 | 473 | mailbox3: mailbox@4883c000 { |
| 440 | 474 | compatible = "ti,omap4-mailbox"; |
| 441 | 475 | reg = <0x4883c000 0x200>; |
| 476 | + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, | |
| 477 | + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
| 478 | + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, | |
| 479 | + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; | |
| 442 | 480 | ti,hwmods = "mailbox3"; |
| 481 | + #mbox-cells = <1>; | |
| 443 | 482 | ti,mbox-num-users = <4>; |
| 444 | 483 | ti,mbox-num-fifos = <12>; |
| 445 | 484 | status = "disabled"; |
| @@ -448,7 +487,12 @@ · 2 unmodified lines | ||
| 448 | 487 | mailbox4: mailbox@4883e000 { |
| 449 | 488 | compatible = "ti,omap4-mailbox"; |
| 450 | 489 | reg = <0x4883e000 0x200>; |
| 490 | + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
| 491 | + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
| 492 | + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
| 493 | + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; | |
| 451 | 494 | ti,hwmods = "mailbox4"; |
| 495 | + #mbox-cells = <1>; | |
| 452 | 496 | ti,mbox-num-users = <4>; |
| 453 | 497 | ti,mbox-num-fifos = <12>; |
| 454 | 498 | status = "disabled"; |
| @@ -457,7 +501,12 @@ · 2 unmodified lines | ||
| 457 | 501 | mailbox5: mailbox@48840000 { |
| 458 | 502 | compatible = "ti,omap4-mailbox"; |
| 459 | 503 | reg = <0x48840000 0x200>; |
| 504 | + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, | |
| 505 | + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
| 506 | + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
| 507 | + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; | |
| 460 | 508 | ti,hwmods = "mailbox5"; |
| 509 | + #mbox-cells = <1>; | |
| 461 | 510 | ti,mbox-num-users = <4>; |
| 462 | 511 | ti,mbox-num-fifos = <12>; |
| 463 | 512 | status = "disabled"; |
| @@ -466,7 +515,12 @@ · 2 unmodified lines | ||
| 466 | 515 | mailbox6: mailbox@48842000 { |
| 467 | 516 | compatible = "ti,omap4-mailbox"; |
| 468 | 517 | reg = <0x48842000 0x200>; |
| 518 | + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, | |
| 519 | + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
| 520 | + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
| 521 | + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | |
| 469 | 522 | ti,hwmods = "mailbox6"; |
| 523 | + #mbox-cells = <1>; | |
| 470 | 524 | ti,mbox-num-users = <4>; |
| 471 | 525 | ti,mbox-num-fifos = <12>; |
| 472 | 526 | status = "disabled"; |
| @@ -475,7 +529,12 @@ · 2 unmodified lines | ||
| 475 | 529 | mailbox7: mailbox@48844000 { |
| 476 | 530 | compatible = "ti,omap4-mailbox"; |
| 477 | 531 | reg = <0x48844000 0x200>; |
| 532 | + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, | |
| 533 | + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
| 534 | + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
| 535 | + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; | |
| 478 | 536 | ti,hwmods = "mailbox7"; |
| 537 | + #mbox-cells = <1>; | |
| 479 | 538 | ti,mbox-num-users = <4>; |
| 480 | 539 | ti,mbox-num-fifos = <12>; |
| 481 | 540 | status = "disabled"; |
| @@ -484,7 +543,12 @@ · 2 unmodified lines | ||
| 484 | 543 | mailbox8: mailbox@48846000 { |
| 485 | 544 | compatible = "ti,omap4-mailbox"; |
| 486 | 545 | reg = <0x48846000 0x200>; |
| 546 | + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, | |
| 547 | + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, | |
| 548 | + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, | |
| 549 | + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; | |
| 487 | 550 | ti,hwmods = "mailbox8"; |
| 551 | + #mbox-cells = <1>; | |
| 488 | 552 | ti,mbox-num-users = <4>; |
| 489 | 553 | ti,mbox-num-fifos = <12>; |
| 490 | 554 | status = "disabled"; |
| @@ -493,7 +557,12 @@ · 2 unmodified lines | ||
| 493 | 557 | mailbox9: mailbox@4885e000 { |
| 494 | 558 | compatible = "ti,omap4-mailbox"; |
| 495 | 559 | reg = <0x4885e000 0x200>; |
| 560 | + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, | |
| 561 | + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, | |
| 562 | + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, | |
| 563 | + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
| 496 | 564 | ti,hwmods = "mailbox9"; |
| 565 | + #mbox-cells = <1>; | |
| 497 | 566 | ti,mbox-num-users = <4>; |
| 498 | 567 | ti,mbox-num-fifos = <12>; |
| 499 | 568 | status = "disabled"; |
| @@ -502,7 +571,12 @@ · 2 unmodified lines | ||
| 502 | 571 | mailbox10: mailbox@48860000 { |
| 503 | 572 | compatible = "ti,omap4-mailbox"; |
| 504 | 573 | reg = <0x48860000 0x200>; |
| 574 | + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, | |
| 575 | + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, | |
| 576 | + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, | |
| 577 | + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; | |
| 505 | 578 | ti,hwmods = "mailbox10"; |
| 579 | + #mbox-cells = <1>; | |
| 506 | 580 | ti,mbox-num-users = <4>; |
| 507 | 581 | ti,mbox-num-fifos = <12>; |
| 508 | 582 | status = "disabled"; |
| @@ -511,7 +585,12 @@ · 2 unmodified lines | ||
| 511 | 585 | mailbox11: mailbox@48862000 { |
| 512 | 586 | compatible = "ti,omap4-mailbox"; |
| 513 | 587 | reg = <0x48862000 0x200>; |
| 588 | + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, | |
| 589 | + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, | |
| 590 | + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, | |
| 591 | + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; | |
| 514 | 592 | ti,hwmods = "mailbox11"; |
| 593 | + #mbox-cells = <1>; | |
| 515 | 594 | ti,mbox-num-users = <4>; |
| 516 | 595 | ti,mbox-num-fifos = <12>; |
| 517 | 596 | status = "disabled"; |
| @@ -520,7 +599,12 @@ · 2 unmodified lines | ||
| 520 | 599 | mailbox12: mailbox@48864000 { |
| 521 | 600 | compatible = "ti,omap4-mailbox"; |
| 522 | 601 | reg = <0x48864000 0x200>; |
| 602 | + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, | |
| 603 | + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, | |
| 604 | + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
| 605 | + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; | |
| 523 | 606 | ti,hwmods = "mailbox12"; |
| 607 | + #mbox-cells = <1>; | |
| 524 | 608 | ti,mbox-num-users = <4>; |
| 525 | 609 | ti,mbox-num-fifos = <12>; |
| 526 | 610 | status = "disabled"; |
| @@ -529,7 +613,12 @@ · 2 unmodified lines | ||
| 529 | 613 | mailbox13: mailbox@48802000 { |
| 530 | 614 | compatible = "ti,omap4-mailbox"; |
| 531 | 615 | reg = <0x48802000 0x200>; |
| 616 | + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, | |
| 617 | + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, | |
| 618 | + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, | |
| 619 | + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; | |
| 532 | 620 | ti,hwmods = "mailbox13"; |
| 621 | + #mbox-cells = <1>; | |
| 533 | 622 | ti,mbox-num-users = <4>; |
| 534 | 623 | ti,mbox-num-fifos = <12>; |
| 535 | 624 | status = "disabled"; |
| @@ -1075,6 +1164,15 @@ · 539 unmodified lines | ||
| 1075 | 1164 | status = "disabled"; |
| 1076 | 1165 | }; |
| 1077 | 1166 | |
| 1167 | + rtc@48838000 { | |
| 1168 | + compatible = "ti,am3352-rtc"; | |
| 1169 | + reg = <0x48838000 0x100>; | |
| 1170 | + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, | |
| 1171 | + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; | |
| 1172 | + ti,hwmods = "rtcss"; | |
| 1173 | + clocks = <&sys_32k_ck>; | |
| 1174 | + }; | |
| 1175 | + | |
| 1078 | 1176 | omap_control_usb2phy1: control-phy@4a002300 { |
| 1079 | 1177 | compatible = "ti,control-phy-usb2"; |
| 1080 | 1178 | reg = <0x4a002300 0x4>; |
| @@ -1141,7 +1239,7 @@ · 60 unmodified lines | ||
| 1141 | 1239 | }; |
| 1142 | 1240 | }; |
| 1143 | 1241 | |
| 1144 | − omap_dwc3_1@48880000 { | |
| 1242 | + omap_dwc3_1: omap_dwc3_1@48880000 { | |
| 1145 | 1243 | compatible = "ti,dwc3"; |
| 1146 | 1244 | ti,hwmods = "usb_otg_ss1"; |
| 1147 | 1245 | reg = <0x48880000 0x10000>; |
| @@ -1162,7 +1260,7 @@ · 14 unmodified lines | ||
| 1162 | 1260 | }; |
| 1163 | 1261 | }; |
| 1164 | 1262 | |
| 1165 | − omap_dwc3_2@488c0000 { | |
| 1263 | + omap_dwc3_2: omap_dwc3_2@488c0000 { | |
| 1166 | 1264 | compatible = "ti,dwc3"; |
| 1167 | 1265 | ti,hwmods = "usb_otg_ss2"; |
| 1168 | 1266 | reg = <0x488c0000 0x10000>; |
| @@ -1184,7 +1282,7 @@ · 15 unmodified lines | ||
| 1184 | 1282 | }; |
| 1185 | 1283 | |
| 1186 | 1284 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
| 1187 | − omap_dwc3_3@48900000 { | |
| 1285 | + omap_dwc3_3: omap_dwc3_3@48900000 { | |
| 1188 | 1286 | compatible = "ti,dwc3"; |
| 1189 | 1287 | ti,hwmods = "usb_otg_ss3"; |
| 1190 | 1288 | reg = <0x48900000 0x10000>; |
| @@ -1204,26 +1302,6 @@ · 13 unmodified lines | ||
| 1204 | 1302 | }; |
| 1205 | 1303 | }; |
| 1206 | 1304 | |
| 1207 | − omap_dwc3_4@48940000 { | |
| 1208 | − compatible = "ti,dwc3"; | |
| 1209 | − ti,hwmods = "usb_otg_ss4"; | |
| 1210 | − reg = <0x48940000 0x10000>; | |
| 1211 | − interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; | |
| 1212 | − #address-cells = <1>; | |
| 1213 | − #size-cells = <1>; | |
| 1214 | − utmi-mode = <2>; | |
| 1215 | − ranges; | |
| 1216 | − status = "disabled"; | |
| 1217 | − usb4: usb@48950000 { | |
| 1218 | − compatible = "snps,dwc3"; | |
| 1219 | − reg = <0x48950000 0x17000>; | |
| 1220 | − interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; | |
| 1221 | − tx-fifo-resize; | |
| 1222 | − maximum-speed = "high-speed"; | |
| 1223 | − dr_mode = "otg"; | |
| 1224 | − }; | |
| 1225 | − }; | |
| 1226 | − | |
| 1227 | 1305 | elm: elm@48078000 { |
| 1228 | 1306 | compatible = "ti,am3352-elm"; |
| 1229 | 1307 | reg = <0x48078000 0xfc0>; /* device IO registers */ |
| @@ -1265,6 +1343,84 @@ · 35 unmodified lines | ||
| 1265 | 1343 | ti,irqs-skip = <10 133 139 140>; |
| 1266 | 1344 | ti,irqs-safe-map = <0>; |
| 1267 | 1345 | }; |
| 1346 | + | |
| 1347 | + mac: ethernet@4a100000 { | |
| 1348 | + compatible = "ti,cpsw"; | |
| 1349 | + ti,hwmods = "gmac"; | |
| 1350 | + clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; | |
| 1351 | + clock-names = "fck", "cpts"; | |
| 1352 | + cpdma_channels = <8>; | |
| 1353 | + ale_entries = <1024>; | |
| 1354 | + bd_ram_size = <0x2000>; | |
| 1355 | + no_bd_ram = <0>; | |
| 1356 | + rx_descs = <64>; | |
| 1357 | + mac_control = <0x20>; | |
| 1358 | + slaves = <2>; | |
| 1359 | + active_slave = <0>; | |
| 1360 | + cpts_clock_mult = <0x80000000>; | |
| 1361 | + cpts_clock_shift = <29>; | |
| 1362 | + reg = <0x48484000 0x1000 | |
| 1363 | + 0x48485200 0x2E00>; | |
| 1364 | + #address-cells = <1>; | |
| 1365 | + #size-cells = <1>; | |
| 1366 | + /* | |
| 1367 | + * rx_thresh_pend | |
| 1368 | + * rx_pend | |
| 1369 | + * tx_pend | |
| 1370 | + * misc_pend | |
| 1371 | + */ | |
| 1372 | + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
| 1373 | + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
| 1374 | + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
| 1375 | + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; | |
| 1376 | + ranges; | |
| 1377 | + status = "disabled"; | |
| 1378 | + | |
| 1379 | + davinci_mdio: mdio@48485000 { | |
| 1380 | + compatible = "ti,davinci_mdio"; | |
| 1381 | + #address-cells = <1>; | |
| 1382 | + #size-cells = <0>; | |
| 1383 | + ti,hwmods = "davinci_mdio"; | |
| 1384 | + bus_freq = <1000000>; | |
| 1385 | + reg = <0x48485000 0x100>; | |
| 1386 | + }; | |
| 1387 | + | |
| 1388 | + cpsw_emac0: slave@48480200 { | |
| 1389 | + /* Filled in by U-Boot */ | |
| 1390 | + mac-address = [ 00 00 00 00 00 00 ]; | |
| 1391 | + }; | |
| 1392 | + | |
| 1393 | + cpsw_emac1: slave@48480300 { | |
| 1394 | + /* Filled in by U-Boot */ | |
| 1395 | + mac-address = [ 00 00 00 00 00 00 ]; | |
| 1396 | + }; | |
| 1397 | + | |
| 1398 | + phy_sel: cpsw-phy-sel@4a002554 { | |
| 1399 | + compatible = "ti,dra7xx-cpsw-phy-sel"; | |
| 1400 | + reg= <0x4a002554 0x4>; | |
| 1401 | + reg-names = "gmii-sel"; | |
| 1402 | + }; | |
| 1403 | + }; | |
| 1404 | + | |
| 1405 | + dcan1: can@481cc000 { | |
| 1406 | + compatible = "ti,dra7-d_can"; | |
| 1407 | + ti,hwmods = "dcan1"; | |
| 1408 | + reg = <0x4ae3c000 0x2000>; | |
| 1409 | + syscon-raminit = <&dra7_ctrl_core 0x558 0>; | |
| 1410 | + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; | |
| 1411 | + clocks = <&dcan1_sys_clk_mux>; | |
| 1412 | + status = "disabled"; | |
| 1413 | + }; | |
| 1414 | + | |
| 1415 | + dcan2: can@481d0000 { | |
| 1416 | + compatible = "ti,dra7-d_can"; | |
| 1417 | + ti,hwmods = "dcan2"; | |
| 1418 | + reg = <0x48480000 0x2000>; | |
| 1419 | + syscon-raminit = <&dra7_ctrl_core 0x558 1>; | |
| 1420 | + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; | |
| 1421 | + clocks = <&sys_clkin1>; | |
| 1422 | + status = "disabled"; | |
| 1423 | + }; | |
| 1268 | 1424 | }; |
| 1269 | 1425 | }; |
| 1270 | 1426 | |
| @@ -17,6 +17,13 @@ · 16 unmodified lines | ||
| 17 | 17 | device_type = "memory"; |
| 18 | 18 | reg = <0x80000000 0x40000000>; /* 1024 MB */ |
| 19 | 19 | }; |
| 20 | + | |
| 21 | + evm_3v3: fixedregulator-evm_3v3 { | |
| 22 | + compatible = "regulator-fixed"; | |
| 23 | + regulator-name = "evm_3v3"; | |
| 24 | + regulator-min-microvolt = <3300000>; | |
| 25 | + regulator-max-microvolt = <3300000>; | |
| 26 | + }; | |
| 20 | 27 | }; |
| 21 | 28 | |
| 22 | 29 | &dra7_pmx_core { |
| @@ -26,6 +33,94 @@ · 3 unmodified lines | ||
| 26 | 33 | 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ |
| 27 | 34 | >; |
| 28 | 35 | }; |
| 36 | + | |
| 37 | + nand_default: nand_default { | |
| 38 | + pinctrl-single,pins = < | |
| 39 | + 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ | |
| 40 | + 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ | |
| 41 | + 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ | |
| 42 | + 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ | |
| 43 | + 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ | |
| 44 | + 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ | |
| 45 | + 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ | |
| 46 | + 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ | |
| 47 | + 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ | |
| 48 | + 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ | |
| 49 | + 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ | |
| 50 | + 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ | |
| 51 | + 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ | |
| 52 | + 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ | |
| 53 | + 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ | |
| 54 | + 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ | |
| 55 | + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ | |
| 56 | + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ | |
| 57 | + 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ | |
| 58 | + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ | |
| 59 | + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ | |
| 60 | + 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ | |
| 61 | + >; | |
| 62 | + }; | |
| 63 | + | |
| 64 | + usb1_pins: pinmux_usb1_pins { | |
| 65 | + pinctrl-single,pins = < | |
| 66 | + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ | |
| 67 | + >; | |
| 68 | + }; | |
| 69 | + | |
| 70 | + usb2_pins: pinmux_usb2_pins { | |
| 71 | + pinctrl-single,pins = < | |
| 72 | + 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ | |
| 73 | + >; | |
| 74 | + }; | |
| 75 | + | |
| 76 | + tps65917_pins_default: tps65917_pins_default { | |
| 77 | + pinctrl-single,pins = < | |
| 78 | + 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ | |
| 79 | + >; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + mmc1_pins_default: mmc1_pins_default { | |
| 83 | + pinctrl-single,pins = < | |
| 84 | + 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ | |
| 85 | + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | |
| 86 | + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | |
| 87 | + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | |
| 88 | + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | |
| 89 | + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | |
| 90 | + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | |
| 91 | + >; | |
| 92 | + }; | |
| 93 | + | |
| 94 | + mmc2_pins_default: mmc2_pins_default { | |
| 95 | + pinctrl-single,pins = < | |
| 96 | + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | |
| 97 | + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | |
| 98 | + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | |
| 99 | + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | |
| 100 | + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | |
| 101 | + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | |
| 102 | + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | |
| 103 | + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | |
| 104 | + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | |
| 105 | + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | |
| 106 | + >; | |
| 107 | + }; | |
| 108 | + | |
| 109 | + dcan1_pins_default: dcan1_pins_default { | |
| 110 | + pinctrl-single,pins = < | |
| 111 | + 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ | |
| 112 | + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ | |
| 113 | + 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */ | |
| 114 | + >; | |
| 115 | + }; | |
| 116 | + | |
| 117 | + dcan1_pins_sleep: dcan1_pins_sleep { | |
| 118 | + pinctrl-single,pins = < | |
| 119 | + 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ | |
| 120 | + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ | |
| 121 | + 0x418 (MUX_MODE15) /* wakeup0.off */ | |
| 122 | + >; | |
| 123 | + }; | |
| 29 | 124 | }; |
| 30 | 125 | |
| 31 | 126 | &i2c1 { |
| @@ -38,6 +133,9 @@ · 6 unmodified lines | ||
| 38 | 133 | compatible = "ti,tps65917"; |
| 39 | 134 | reg = <0x58>; |
| 40 | 135 | |
| 136 | + pinctrl-names = "default"; | |
| 137 | + pinctrl-0 = <&tps65917_pins_default>; | |
| 138 | + | |
| 41 | 139 | interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
| 42 | 140 | interrupt-parent = <&gic>; |
| 43 | 141 | interrupt-controller; |
| @@ -136,9 +234,230 @@ · 92 unmodified lines | ||
| 136 | 234 | }; |
| 137 | 235 | }; |
| 138 | 236 | }; |
| 237 | + | |
| 238 | + tps65917_power_button { | |
| 239 | + compatible = "ti,palmas-pwrbutton"; | |
| 240 | + interrupt-parent = <&tps65917>; | |
| 241 | + interrupts = <1 IRQ_TYPE_NONE>; | |
| 242 | + wakeup-source; | |
| 243 | + ti,palmas-long-press-seconds = <6>; | |
| 244 | + }; | |
| 139 | 245 | }; |
| 140 | 246 | }; |
| 141 | 247 | |
| 142 | 248 | &uart1 { |
| 143 | 249 | status = "okay"; |
| 144 | 250 | }; |
| 251 | + | |
| 252 | +&elm { | |
| 253 | + status = "okay"; | |
| 254 | +}; | |
| 255 | + | |
| 256 | +&gpmc { | |
| 257 | + status = "okay"; | |
| 258 | + pinctrl-names = "default"; | |
| 259 | + pinctrl-0 = <&nand_default>; | |
| 260 | + ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ | |
| 261 | + nand@0,0 { | |
| 262 | + /* To use NAND, DIP switch SW5 must be set like so: | |
| 263 | + * SW5.1 (NAND_SELn) = ON (LOW) | |
| 264 | + * SW5.9 (GPMC_WPN) = OFF (HIGH) | |
| 265 | + */ | |
| 266 | + reg = <0 0 4>; /* device IO registers */ | |
| 267 | + ti,nand-ecc-opt = "bch8"; | |
| 268 | + ti,elm-id = <&elm>; | |
| 269 | + nand-bus-width = <16>; | |
| 270 | + gpmc,device-width = <2>; | |
| 271 | + gpmc,sync-clk-ps = <0>; | |
| 272 | + gpmc,cs-on-ns = <0>; | |
| 273 | + gpmc,cs-rd-off-ns = <80>; | |
| 274 | + gpmc,cs-wr-off-ns = <80>; | |
| 275 | + gpmc,adv-on-ns = <0>; | |
| 276 | + gpmc,adv-rd-off-ns = <60>; | |
| 277 | + gpmc,adv-wr-off-ns = <60>; | |
| 278 | + gpmc,we-on-ns = <10>; | |
| 279 | + gpmc,we-off-ns = <50>; | |
| 280 | + gpmc,oe-on-ns = <4>; | |
| 281 | + gpmc,oe-off-ns = <40>; | |
| 282 | + gpmc,access-ns = <40>; | |
| 283 | + gpmc,wr-access-ns = <80>; | |
| 284 | + gpmc,rd-cycle-ns = <80>; | |
| 285 | + gpmc,wr-cycle-ns = <80>; | |
| 286 | + gpmc,bus-turnaround-ns = <0>; | |
| 287 | + gpmc,cycle2cycle-delay-ns = <0>; | |
| 288 | + gpmc,clk-activation-ns = <0>; | |
| 289 | + gpmc,wait-monitoring-ns = <0>; | |
| 290 | + gpmc,wr-data-mux-bus-ns = <0>; | |
| 291 | + /* MTD partition table */ | |
| 292 | + /* All SPL-* partitions are sized to minimal length | |
| 293 | + * which can be independently programmable. For | |
| 294 | + * NAND flash this is equal to size of erase-block */ | |
| 295 | + #address-cells = <1>; | |
| 296 | + #size-cells = <1>; | |
| 297 | + partition@0 { | |
| 298 | + label = "NAND.SPL"; | |
| 299 | + reg = <0x00000000 0x000020000>; | |
| 300 | + }; | |
| 301 | + partition@1 { | |
| 302 | + label = "NAND.SPL.backup1"; | |
| 303 | + reg = <0x00020000 0x00020000>; | |
| 304 | + }; | |
| 305 | + partition@2 { | |
| 306 | + label = "NAND.SPL.backup2"; | |
| 307 | + reg = <0x00040000 0x00020000>; | |
| 308 | + }; | |
| 309 | + partition@3 { | |
| 310 | + label = "NAND.SPL.backup3"; | |
| 311 | + reg = <0x00060000 0x00020000>; | |
| 312 | + }; | |
| 313 | + partition@4 { | |
| 314 | + label = "NAND.u-boot-spl-os"; | |
| 315 | + reg = <0x00080000 0x00040000>; | |
| 316 | + }; | |
| 317 | + partition@5 { | |
| 318 | + label = "NAND.u-boot"; | |
| 319 | + reg = <0x000c0000 0x00100000>; | |
| 320 | + }; | |
| 321 | + partition@6 { | |
| 322 | + label = "NAND.u-boot-env"; | |
| 323 | + reg = <0x001c0000 0x00020000>; | |
| 324 | + }; | |
| 325 | + partition@7 { | |
| 326 | + label = "NAND.u-boot-env.backup1"; | |
| 327 | + reg = <0x001e0000 0x00020000>; | |
| 328 | + }; | |
| 329 | + partition@8 { | |
| 330 | + label = "NAND.kernel"; | |
| 331 | + reg = <0x00200000 0x00800000>; | |
| 332 | + }; | |
| 333 | + partition@9 { | |
| 334 | + label = "NAND.file-system"; | |
| 335 | + reg = <0x00a00000 0x0f600000>; | |
| 336 | + }; | |
| 337 | + }; | |
| 338 | +}; | |
| 339 | + | |
| 340 | +&usb2_phy1 { | |
| 341 | + phy-supply = <&ldo4_reg>; | |
| 342 | +}; | |
| 343 | + | |
| 344 | +&usb2_phy2 { | |
| 345 | + phy-supply = <&ldo4_reg>; | |
| 346 | +}; | |
| 347 | + | |
| 348 | +&usb1 { | |
| 349 | + dr_mode = "peripheral"; | |
| 350 | + pinctrl-names = "default"; | |
| 351 | + pinctrl-0 = <&usb1_pins>; | |
| 352 | +}; | |
| 353 | + | |
| 354 | +&usb2 { | |
| 355 | + dr_mode = "host"; | |
| 356 | + pinctrl-names = "default"; | |
| 357 | + pinctrl-0 = <&usb2_pins>; | |
| 358 | +}; | |
| 359 | + | |
| 360 | +&mmc1 { | |
| 361 | + status = "okay"; | |
| 362 | + pinctrl-names = "default"; | |
| 363 | + pinctrl-0 = <&mmc1_pins_default>; | |
| 364 | + | |
| 365 | + vmmc-supply = <&ldo1_reg>; | |
| 366 | + bus-width = <4>; | |
| 367 | + /* | |
| 368 | + * SDCD signal is not being used here - using the fact that GPIO mode | |
| 369 | + * is a viable alternative | |
| 370 | + */ | |
| 371 | + cd-gpios = <&gpio6 27 0>; | |
| 372 | +}; | |
| 373 | + | |
| 374 | +&mmc2 { | |
| 375 | + /* SW5-3 in ON position */ | |
| 376 | + status = "okay"; | |
| 377 | + pinctrl-names = "default"; | |
| 378 | + pinctrl-0 = <&mmc2_pins_default>; | |
| 379 | + | |
| 380 | + vmmc-supply = <&evm_3v3>; | |
| 381 | + bus-width = <8>; | |
| 382 | + ti,non-removable; | |
| 383 | +}; | |
| 384 | + | |
| 385 | +&dra7_pmx_core { | |
| 386 | + cpsw_default: cpsw_default { | |
| 387 | + pinctrl-single,pins = < | |
| 388 | + /* Slave 2 */ | |
| 389 | + 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ | |
| 390 | + 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ | |
| 391 | + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ | |
| 392 | + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ | |
| 393 | + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ | |
| 394 | + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ | |
| 395 | + 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ | |
| 396 | + 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ | |
| 397 | + 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ | |
| 398 | + 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ | |
| 399 | + 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ | |
| 400 | + 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ | |
| 401 | + >; | |
| 402 | + | |
| 403 | + }; | |
| 404 | + | |
| 405 | + cpsw_sleep: cpsw_sleep { | |
| 406 | + pinctrl-single,pins = < | |
| 407 | + /* Slave 2 */ | |
| 408 | + 0x198 (MUX_MODE15) | |
| 409 | + 0x19c (MUX_MODE15) | |
| 410 | + 0x1a0 (MUX_MODE15) | |
| 411 | + 0x1a4 (MUX_MODE15) | |
| 412 | + 0x1a8 (MUX_MODE15) | |
| 413 | + 0x1ac (MUX_MODE15) | |
| 414 | + 0x1b0 (MUX_MODE15) | |
| 415 | + 0x1b4 (MUX_MODE15) | |
| 416 | + 0x1b8 (MUX_MODE15) | |
| 417 | + 0x1bc (MUX_MODE15) | |
| 418 | + 0x1c0 (MUX_MODE15) | |
| 419 | + 0x1c4 (MUX_MODE15) | |
| 420 | + >; | |
| 421 | + }; | |
| 422 | + | |
| 423 | + davinci_mdio_default: davinci_mdio_default { | |
| 424 | + pinctrl-single,pins = < | |
| 425 | + /* MDIO */ | |
| 426 | + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ | |
| 427 | + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
| 428 | + >; | |
| 429 | + }; | |
| 430 | + | |
| 431 | + davinci_mdio_sleep: davinci_mdio_sleep { | |
| 432 | + pinctrl-single,pins = < | |
| 433 | + 0x23c (MUX_MODE15) | |
| 434 | + 0x240 (MUX_MODE15) | |
| 435 | + >; | |
| 436 | + }; | |
| 437 | +}; | |
| 438 | + | |
| 439 | +&mac { | |
| 440 | + status = "okay"; | |
| 441 | + pinctrl-names = "default", "sleep"; | |
| 442 | + pinctrl-0 = <&cpsw_default>; | |
| 443 | + pinctrl-1 = <&cpsw_sleep>; | |
| 444 | +}; | |
| 445 | + | |
| 446 | +&cpsw_emac1 { | |
| 447 | + phy_id = <&davinci_mdio>, <3>; | |
| 448 | + phy-mode = "rgmii"; | |
| 449 | +}; | |
| 450 | + | |
| 451 | +&davinci_mdio { | |
| 452 | + pinctrl-names = "default", "sleep"; | |
| 453 | + pinctrl-0 = <&davinci_mdio_default>; | |
| 454 | + pinctrl-1 = <&davinci_mdio_sleep>; | |
| 455 | + active_slave = <1>; | |
| 456 | +}; | |
| 457 | + | |
| 458 | +&dcan1 { | |
| 459 | + status = "ok"; | |
| 460 | + pinctrl-names = "default", "sleep"; | |
| 461 | + pinctrl-0 = <&dcan1_pins_default>; | |
| 462 | + pinctrl-1 = <&dcan1_pins_sleep>; | |
| 463 | +}; | |
| @@ -44,4 +44,26 @@ · 43 unmodified lines | ||
| 44 | 44 | interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>, |
| 45 | 45 | <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>; |
| 46 | 46 | }; |
| 47 | + | |
| 48 | + ocp { | |
| 49 | + omap_dwc3_4: omap_dwc3_4@48940000 { | |
| 50 | + compatible = "ti,dwc3"; | |
| 51 | + ti,hwmods = "usb_otg_ss4"; | |
| 52 | + reg = <0x48940000 0x10000>; | |
| 53 | + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; | |
| 54 | + #address-cells = <1>; | |
| 55 | + #size-cells = <1>; | |
| 56 | + utmi-mode = <2>; | |
| 57 | + ranges; | |
| 58 | + status = "disabled"; | |
| 59 | + usb4: usb@48950000 { | |
| 60 | + compatible = "snps,dwc3"; | |
| 61 | + reg = <0x48950000 0x17000>; | |
| 62 | + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; | |
| 63 | + tx-fifo-resize; | |
| 64 | + maximum-speed = "high-speed"; | |
| 65 | + dr_mode = "otg"; | |
| 66 | + }; | |
| 67 | + }; | |
| 68 | + }; | |
| 47 | 69 | }; |
| @@ -25,37 +25,7 @@ · 24 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | chosen { |
| 27 | 27 | bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; |
| 28 | − }; | |
| 29 | − | |
| 30 | − reg_1p8v: regulator@0 { | |
| 31 | − compatible = "regulator-fixed"; | |
| 32 | − regulator-name = "fixed-1.8V"; | |
| 33 | − regulator-min-microvolt = <1800000>; | |
| 34 | − regulator-max-microvolt = <1800000>; | |
| 35 | − regulator-always-on; | |
| 36 | − regulator-boot-on; | |
| 37 | − }; | |
| 38 | − | |
| 39 | − reg_3p3v: regulator@1 { | |
| 40 | − compatible = "regulator-fixed"; | |
| 41 | − regulator-name = "fixed-3.3V"; | |
| 42 | − regulator-min-microvolt = <3300000>; | |
| 43 | − regulator-max-microvolt = <3300000>; | |
| 44 | − regulator-always-on; | |
| 45 | − regulator-boot-on; | |
| 46 | − }; | |
| 47 | − | |
| 48 | − lan9220@20000000 { | |
| 49 | − compatible = "smsc,lan9220", "smsc,lan9115"; | |
| 50 | − reg = <0x20000000 0x10000>; | |
| 51 | − phy-mode = "mii"; | |
| 52 | − interrupt-parent = <&gpio0>; | |
| 53 | − interrupts = <1 IRQ_TYPE_EDGE_RISING>; | |
| 54 | − reg-io-width = <4>; | |
| 55 | − smsc,irq-active-high; | |
| 56 | − smsc,irq-push-pull; | |
| 57 | − vddvario-supply = <®_1p8v>; | |
| 58 | − vdd33a-supply = <®_3p3v>; | |
| 28 | + stdout-path = &uart1; | |
| 59 | 29 | }; |
| 60 | 30 | |
| 61 | 31 | gpio_keys { |
| @@ -92,4 +62,35 @@ · 30 unmodified lines | ||
| 92 | 62 | gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; |
| 93 | 63 | }; |
| 94 | 64 | }; |
| 65 | + | |
| 66 | + reg_1p8v: regulator@0 { | |
| 67 | + compatible = "regulator-fixed"; | |
| 68 | + regulator-name = "fixed-1.8V"; | |
| 69 | + regulator-min-microvolt = <1800000>; | |
| 70 | + regulator-max-microvolt = <1800000>; | |
| 71 | + regulator-always-on; | |
| 72 | + regulator-boot-on; | |
| 73 | + }; | |
| 74 | + | |
| 75 | + reg_3p3v: regulator@1 { | |
| 76 | + compatible = "regulator-fixed"; | |
| 77 | + regulator-name = "fixed-3.3V"; | |
| 78 | + regulator-min-microvolt = <3300000>; | |
| 79 | + regulator-max-microvolt = <3300000>; | |
| 80 | + regulator-always-on; | |
| 81 | + regulator-boot-on; | |
| 82 | + }; | |
| 83 | + | |
| 84 | + lan9220@20000000 { | |
| 85 | + compatible = "smsc,lan9220", "smsc,lan9115"; | |
| 86 | + reg = <0x20000000 0x10000>; | |
| 87 | + phy-mode = "mii"; | |
| 88 | + interrupt-parent = <&gpio0>; | |
| 89 | + interrupts = <1 IRQ_TYPE_EDGE_RISING>; | |
| 90 | + reg-io-width = <4>; | |
| 91 | + smsc,irq-active-high; | |
| 92 | + smsc,irq-push-pull; | |
| 93 | + vddvario-supply = <®_1p8v>; | |
| 94 | + vdd33a-supply = <®_3p3v>; | |
| 95 | + }; | |
| 95 | 96 | }; |
| @@ -55,7 +55,7 @@ · 54 unmodified lines | ||
| 55 | 55 | <0 121 IRQ_TYPE_LEVEL_HIGH>; |
| 56 | 56 | }; |
| 57 | 57 | |
| 58 | − smu@e0110000 { | |
| 58 | + clocks@e0110000 { | |
| 59 | 59 | compatible = "renesas,emev2-smu"; |
| 60 | 60 | reg = <0xe0110000 0x10000>; |
| 61 | 61 | #address-cells = <2>; |
| @@ -129,7 +129,7 @@ · 67 unmodified lines | ||
| 129 | 129 | }; |
| 130 | 130 | }; |
| 131 | 131 | |
| 132 | − sti@e0180000 { | |
| 132 | + timer@e0180000 { | |
| 133 | 133 | compatible = "renesas,em-sti"; |
| 134 | 134 | reg = <0xe0180000 0x54>; |
| 135 | 135 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -137,7 +137,7 @@ · 1 unmodified line | ||
| 137 | 137 | clock-names = "sclk"; |
| 138 | 138 | }; |
| 139 | 139 | |
| 140 | − uart@e1020000 { | |
| 140 | + uart0: serial@e1020000 { | |
| 141 | 141 | compatible = "renesas,em-uart"; |
| 142 | 142 | reg = <0xe1020000 0x38>; |
| 143 | 143 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -145,7 +145,7 @@ · 1 unmodified line | ||
| 145 | 145 | clock-names = "sclk"; |
| 146 | 146 | }; |
| 147 | 147 | |
| 148 | − uart@e1030000 { | |
| 148 | + uart1: serial@e1030000 { | |
| 149 | 149 | compatible = "renesas,em-uart"; |
| 150 | 150 | reg = <0xe1030000 0x38>; |
| 151 | 151 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -153,7 +153,7 @@ · 1 unmodified line | ||
| 153 | 153 | clock-names = "sclk"; |
| 154 | 154 | }; |
| 155 | 155 | |
| 156 | − uart@e1040000 { | |
| 156 | + uart2: serial@e1040000 { | |
| 157 | 157 | compatible = "renesas,em-uart"; |
| 158 | 158 | reg = <0xe1040000 0x38>; |
| 159 | 159 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -161,7 +161,7 @@ · 1 unmodified line | ||
| 161 | 161 | clock-names = "sclk"; |
| 162 | 162 | }; |
| 163 | 163 | |
| 164 | − uart@e1050000 { | |
| 164 | + uart3: serial@e1050000 { | |
| 165 | 165 | compatible = "renesas,em-uart"; |
| 166 | 166 | reg = <0xe1050000 0x38>; |
| 167 | 167 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -0,0 +1,579 @@ | ||
| 1 | +/* | |
| 2 | + * Samsung's Exynos3250 based Monk board device tree source | |
| 3 | + * | |
| 4 | + * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
| 5 | + * http://www.samsung.com | |
| 6 | + * | |
| 7 | + * Device tree source file for Samsung's Monk board which is based on | |
| 8 | + * Samsung Exynos3250 SoC. | |
| 9 | + * | |
| 10 | + * This program is free software; you can redistribute it and/or modify | |
| 11 | + * it under the terms of the GNU General Public License version 2 as | |
| 12 | + * published by the Free Software Foundation. | |
| 13 | + */ | |
| 14 | + | |
| 15 | +/dts-v1/; | |
| 16 | +#include "exynos3250.dtsi" | |
| 17 | +#include <dt-bindings/input/input.h> | |
| 18 | + | |
| 19 | +/ { | |
| 20 | + model = "Samsung Monk board"; | |
| 21 | + compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3"; | |
| 22 | + | |
| 23 | + aliases { | |
| 24 | + i2c7 = &i2c_max77836; | |
| 25 | + }; | |
| 26 | + | |
| 27 | + memory { | |
| 28 | + reg = <0x40000000 0x1ff00000>; | |
| 29 | + }; | |
| 30 | + | |
| 31 | + firmware@0205F000 { | |
| 32 | + compatible = "samsung,secure-firmware"; | |
| 33 | + reg = <0x0205F000 0x1000>; | |
| 34 | + }; | |
| 35 | + | |
| 36 | + gpio_keys { | |
| 37 | + compatible = "gpio-keys"; | |
| 38 | + | |
| 39 | + power_key { | |
| 40 | + interrupt-parent = <&gpx2>; | |
| 41 | + interrupts = <7 0>; | |
| 42 | + gpios = <&gpx2 7 1>; | |
| 43 | + linux,code = <KEY_POWER>; | |
| 44 | + label = "power key"; | |
| 45 | + debounce-interval = <10>; | |
| 46 | + gpio-key,wakeup; | |
| 47 | + }; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + vemmc_reg: voltage-regulator-0 { | |
| 51 | + compatible = "regulator-fixed"; | |
| 52 | + regulator-name = "V_EMMC_2.8V-fixed"; | |
| 53 | + regulator-min-microvolt = <2800000>; | |
| 54 | + regulator-max-microvolt = <2800000>; | |
| 55 | + gpio = <&gpk0 2 0>; | |
| 56 | + enable-active-high; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + i2c_max77836: i2c-gpio-0 { | |
| 60 | + compatible = "i2c-gpio"; | |
| 61 | + gpios = <&gpd0 2 0>, <&gpd0 3 0>; | |
| 62 | + #address-cells = <1>; | |
| 63 | + #size-cells = <0>; | |
| 64 | + | |
| 65 | + max77836: subpmic@25 { | |
| 66 | + compatible = "maxim,max77836"; | |
| 67 | + interrupt-parent = <&gpx1>; | |
| 68 | + interrupts = <5 0>; | |
| 69 | + reg = <0x25>; | |
| 70 | + wakeup; | |
| 71 | + | |
| 72 | + muic: max77836-muic { | |
| 73 | + compatible = "maxim,max77836-muic"; | |
| 74 | + }; | |
| 75 | + | |
| 76 | + regulators { | |
| 77 | + compatible = "maxim,max77836-regulator"; | |
| 78 | + safeout_reg: SAFEOUT { | |
| 79 | + regulator-name = "SAFEOUT"; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + charger_reg: CHARGER { | |
| 83 | + regulator-name = "CHARGER"; | |
| 84 | + regulator-min-microamp = <45000>; | |
| 85 | + regulator-max-microamp = <475000>; | |
| 86 | + regulator-boot-on; | |
| 87 | + }; | |
| 88 | + | |
| 89 | + motor_reg: LDO1 { | |
| 90 | + regulator-name = "MOT_2.7V"; | |
| 91 | + regulator-min-microvolt = <1100000>; | |
| 92 | + regulator-max-microvolt = <2700000>; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + LDO2 { | |
| 96 | + regulator-name = "UNUSED_LDO2"; | |
| 97 | + regulator-min-microvolt = <800000>; | |
| 98 | + regulator-max-microvolt = <3950000>; | |
| 99 | + }; | |
| 100 | + }; | |
| 101 | + | |
| 102 | + charger { | |
| 103 | + compatible = "maxim,max77836-charger"; | |
| 104 | + | |
| 105 | + maxim,constant-uvolt = <4350000>; | |
| 106 | + maxim,fast-charge-uamp = <225000>; | |
| 107 | + maxim,eoc-uamp = <7500>; | |
| 108 | + maxim,ovp-uvolt = <6500000>; | |
| 109 | + }; | |
| 110 | + }; | |
| 111 | + }; | |
| 112 | +}; | |
| 113 | + | |
| 114 | +&adc { | |
| 115 | + vdd-supply = <&ldo3_reg>; | |
| 116 | + status = "okay"; | |
| 117 | + assigned-clocks = <&cmu CLK_SCLK_TSADC>; | |
| 118 | + assigned-clock-rates = <6000000>; | |
| 119 | + | |
| 120 | + thermistor-ap { | |
| 121 | + compatible = "ntc,ncp15wb473"; | |
| 122 | + pullup-uv = <1800000>; | |
| 123 | + pullup-ohm = <100000>; | |
| 124 | + pulldown-ohm = <100000>; | |
| 125 | + io-channels = <&adc 0>; | |
| 126 | + }; | |
| 127 | + | |
| 128 | + thermistor-battery { | |
| 129 | + compatible = "ntc,ncp15wb473"; | |
| 130 | + pullup-uv = <1800000>; | |
| 131 | + pullup-ohm = <100000>; | |
| 132 | + pulldown-ohm = <100000>; | |
| 133 | + io-channels = <&adc 1>; | |
| 134 | + }; | |
| 135 | +}; | |
| 136 | + | |
| 137 | +&i2c_0 { | |
| 138 | + #address-cells = <1>; | |
| 139 | + #size-cells = <0>; | |
| 140 | + samsung,i2c-sda-delay = <100>; | |
| 141 | + samsung,i2c-slave-addr = <0x10>; | |
| 142 | + samsung,i2c-max-bus-freq = <100000>; | |
| 143 | + status = "okay"; | |
| 144 | + | |
| 145 | + s2mps14_pmic@66 { | |
| 146 | + compatible = "samsung,s2mps14-pmic"; | |
| 147 | + interrupt-parent = <&gpx0>; | |
| 148 | + interrupts = <7 0>; | |
| 149 | + reg = <0x66>; | |
| 150 | + wakeup; | |
| 151 | + | |
| 152 | + s2mps14_osc: clocks { | |
| 153 | + compatible = "samsung,s2mps14-clk"; | |
| 154 | + #clock-cells = <1>; | |
| 155 | + clock-output-names = "s2mps14_ap", "unused", | |
| 156 | + "s2mps14_bt"; | |
| 157 | + }; | |
| 158 | + | |
| 159 | + regulators { | |
| 160 | + ldo1_reg: LDO1 { | |
| 161 | + regulator-name = "VAP_ALIVE_1.0V"; | |
| 162 | + regulator-min-microvolt = <1000000>; | |
| 163 | + regulator-max-microvolt = <1000000>; | |
| 164 | + regulator-always-on; | |
| 165 | + }; | |
| 166 | + | |
| 167 | + ldo2_reg: LDO2 { | |
| 168 | + regulator-name = "VAP_M1_1.2V"; | |
| 169 | + regulator-min-microvolt = <1200000>; | |
| 170 | + regulator-max-microvolt = <1200000>; | |
| 171 | + regulator-always-on; | |
| 172 | + }; | |
| 173 | + | |
| 174 | + ldo3_reg: LDO3 { | |
| 175 | + regulator-name = "VCC_AP_1.8V"; | |
| 176 | + regulator-min-microvolt = <1800000>; | |
| 177 | + regulator-max-microvolt = <1800000>; | |
| 178 | + regulator-always-on; | |
| 179 | + }; | |
| 180 | + | |
| 181 | + ldo4_reg: LDO4 { | |
| 182 | + regulator-name = "VAP_AVDD_PLL1"; | |
| 183 | + regulator-min-microvolt = <1800000>; | |
| 184 | + regulator-max-microvolt = <1800000>; | |
| 185 | + regulator-always-on; | |
| 186 | + }; | |
| 187 | + | |
| 188 | + ldo5_reg: LDO5 { | |
| 189 | + regulator-name = "VAP_PLL_ISO_1.0V"; | |
| 190 | + regulator-min-microvolt = <1000000>; | |
| 191 | + regulator-max-microvolt = <1000000>; | |
| 192 | + regulator-always-on; | |
| 193 | + }; | |
| 194 | + | |
| 195 | + ldo6_reg: LDO6 { | |
| 196 | + regulator-name = "VAP_MIPI_1.0V"; | |
| 197 | + regulator-min-microvolt = <1000000>; | |
| 198 | + regulator-max-microvolt = <1000000>; | |
| 199 | + }; | |
| 200 | + | |
| 201 | + ldo7_reg: LDO7 { | |
| 202 | + regulator-name = "VAP_AVDD_1.8V"; | |
| 203 | + regulator-min-microvolt = <1800000>; | |
| 204 | + regulator-max-microvolt = <1800000>; | |
| 205 | + regulator-always-on; | |
| 206 | + }; | |
| 207 | + | |
| 208 | + ldo8_reg: LDO8 { | |
| 209 | + regulator-name = "VAP_USB_3.0V"; | |
| 210 | + regulator-min-microvolt = <3000000>; | |
| 211 | + regulator-max-microvolt = <3000000>; | |
| 212 | + regulator-always-on; | |
| 213 | + }; | |
| 214 | + | |
| 215 | + ldo9_reg: LDO9 { | |
| 216 | + regulator-name = "V_LPDDR_1.2V"; | |
| 217 | + regulator-min-microvolt = <1200000>; | |
| 218 | + regulator-max-microvolt = <1200000>; | |
| 219 | + regulator-always-on; | |
| 220 | + }; | |
| 221 | + | |
| 222 | + ldo10_reg: LDO10 { | |
| 223 | + regulator-name = "UNUSED_LDO10"; | |
| 224 | + regulator-min-microvolt = <1000000>; | |
| 225 | + regulator-max-microvolt = <1000000>; | |
| 226 | + }; | |
| 227 | + | |
| 228 | + ldo11_reg: LDO11 { | |
| 229 | + regulator-name = "V_EMMC_1.8V"; | |
| 230 | + regulator-min-microvolt = <1800000>; | |
| 231 | + regulator-max-microvolt = <1800000>; | |
| 232 | + samsung,ext-control-gpios = <&gpk0 2 0>; | |
| 233 | + }; | |
| 234 | + | |
| 235 | + ldo12_reg: LDO12 { | |
| 236 | + regulator-name = "V_EMMC_2.8V"; | |
| 237 | + regulator-min-microvolt = <2800000>; | |
| 238 | + regulator-max-microvolt = <2800000>; | |
| 239 | + samsung,ext-control-gpios = <&gpk0 2 0>; | |
| 240 | + }; | |
| 241 | + | |
| 242 | + ldo13_reg: LDO13 { | |
| 243 | + regulator-name = "VSENSOR_2.85V"; | |
| 244 | + regulator-min-microvolt = <2850000>; | |
| 245 | + regulator-max-microvolt = <2850000>; | |
| 246 | + regulator-always-on; | |
| 247 | + }; | |
| 248 | + | |
| 249 | + ldo14_reg: LDO14 { | |
| 250 | + regulator-name = "UNUSED_LDO14"; | |
| 251 | + regulator-min-microvolt = <1800000>; | |
| 252 | + regulator-max-microvolt = <1800000>; | |
| 253 | + }; | |
| 254 | + | |
| 255 | + ldo15_reg: LDO15 { | |
| 256 | + regulator-name = "TSP_AVDD_3.3V"; | |
| 257 | + regulator-min-microvolt = <3300000>; | |
| 258 | + regulator-max-microvolt = <3300000>; | |
| 259 | + }; | |
| 260 | + | |
| 261 | + ldo16_reg: LDO16 { | |
| 262 | + regulator-name = "LCD_VDD_3.3V"; | |
| 263 | + regulator-min-microvolt = <3300000>; | |
| 264 | + regulator-max-microvolt = <3300000>; | |
| 265 | + }; | |
| 266 | + | |
| 267 | + ldo17_reg: LDO17 { | |
| 268 | + regulator-name = "UNUSED_LDO17"; | |
| 269 | + regulator-min-microvolt = <1800000>; | |
| 270 | + regulator-max-microvolt = <1800000>; | |
| 271 | + }; | |
| 272 | + | |
| 273 | + ldo18_reg: LDO18 { | |
| 274 | + regulator-name = "UNUSED_LDO18"; | |
| 275 | + regulator-min-microvolt = <1800000>; | |
| 276 | + regulator-max-microvolt = <1800000>; | |
| 277 | + }; | |
| 278 | + | |
| 279 | + ldo19_reg: LDO19 { | |
| 280 | + regulator-name = "TSP_VDD_1.8V"; | |
| 281 | + regulator-min-microvolt = <1800000>; | |
| 282 | + regulator-max-microvolt = <1800000>; | |
| 283 | + }; | |
| 284 | + | |
| 285 | + ldo20_reg: LDO20 { | |
| 286 | + regulator-name = "LCD_VDD_1.8V"; | |
| 287 | + regulator-min-microvolt = <1800000>; | |
| 288 | + regulator-max-microvolt = <1800000>; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + ldo21_reg: LDO21 { | |
| 292 | + regulator-name = "UNUSED_LDO21"; | |
| 293 | + regulator-min-microvolt = <1000000>; | |
| 294 | + regulator-max-microvolt = <1000000>; | |
| 295 | + }; | |
| 296 | + | |
| 297 | + ldo22_reg: LDO22 { | |
| 298 | + regulator-name = "UNUSED_LDO22"; | |
| 299 | + regulator-min-microvolt = <1000000>; | |
| 300 | + regulator-max-microvolt = <1000000>; | |
| 301 | + }; | |
| 302 | + | |
| 303 | + ldo23_reg: LDO23 { | |
| 304 | + regulator-name = "UNUSED_LDO23"; | |
| 305 | + regulator-min-microvolt = <1000000>; | |
| 306 | + regulator-max-microvolt = <1000000>; | |
| 307 | + regulator-always-on; | |
| 308 | + }; | |
| 309 | + | |
| 310 | + ldo24_reg: LDO24 { | |
| 311 | + regulator-name = "UNUSED_LDO24"; | |
| 312 | + regulator-min-microvolt = <1800000>; | |
| 313 | + regulator-max-microvolt = <1800000>; | |
| 314 | + }; | |
| 315 | + | |
| 316 | + ldo25_reg: LDO25 { | |
| 317 | + regulator-name = "UNUSED_LDO25"; | |
| 318 | + regulator-min-microvolt = <1800000>; | |
| 319 | + regulator-max-microvolt = <1800000>; | |
| 320 | + }; | |
| 321 | + | |
| 322 | + buck1_reg: BUCK1 { | |
| 323 | + regulator-name = "VAP_MIF_1.0V"; | |
| 324 | + regulator-min-microvolt = <800000>; | |
| 325 | + regulator-max-microvolt = <900000>; | |
| 326 | + regulator-always-on; | |
| 327 | + }; | |
| 328 | + | |
| 329 | + buck2_reg: BUCK2 { | |
| 330 | + regulator-name = "VAP_ARM_1.0V"; | |
| 331 | + regulator-min-microvolt = <850000>; | |
| 332 | + regulator-max-microvolt = <1150000>; | |
| 333 | + regulator-always-on; | |
| 334 | + }; | |
| 335 | + | |
| 336 | + buck3_reg: BUCK3 { | |
| 337 | + regulator-name = "VAP_INT3D_1.0V"; | |
| 338 | + regulator-min-microvolt = <850000>; | |
| 339 | + regulator-max-microvolt = <1000000>; | |
| 340 | + regulator-always-on; | |
| 341 | + }; | |
| 342 | + | |
| 343 | + buck4_reg: BUCK4 { | |
| 344 | + regulator-name = "VCC_SUB_1.95V"; | |
| 345 | + regulator-min-microvolt = <1950000>; | |
| 346 | + regulator-max-microvolt = <1950000>; | |
| 347 | + regulator-always-on; | |
| 348 | + }; | |
| 349 | + | |
| 350 | + buck5_reg: BUCK5 { | |
| 351 | + regulator-name = "VCC_SUB_1.35V"; | |
| 352 | + regulator-min-microvolt = <1350000>; | |
| 353 | + regulator-max-microvolt = <1350000>; | |
| 354 | + regulator-always-on; | |
| 355 | + }; | |
| 356 | + }; | |
| 357 | + }; | |
| 358 | +}; | |
| 359 | + | |
| 360 | +&i2c_1 { | |
| 361 | + #address-cells = <1>; | |
| 362 | + #size-cells = <0>; | |
| 363 | + samsung,i2c-sda-delay = <100>; | |
| 364 | + samsung,i2c-slave-addr = <0x10>; | |
| 365 | + samsung,i2c-max-bus-freq = <400000>; | |
| 366 | + status = "okay"; | |
| 367 | + | |
| 368 | + fuelgauge@36 { | |
| 369 | + compatible = "maxim,max77836-battery"; | |
| 370 | + interrupt-parent = <&gpx1>; | |
| 371 | + interrupts = <2 8>; | |
| 372 | + reg = <0x36>; | |
| 373 | + }; | |
| 374 | +}; | |
| 375 | + | |
| 376 | +&i2s2 { | |
| 377 | + status = "okay"; | |
| 378 | +}; | |
| 379 | + | |
| 380 | +&mshc_0 { | |
| 381 | + #address-cells = <1>; | |
| 382 | + #size-cells = <0>; | |
| 383 | + num-slots = <1>; | |
| 384 | + broken-cd; | |
| 385 | + non-removable; | |
| 386 | + cap-mmc-highspeed; | |
| 387 | + desc-num = <4>; | |
| 388 | + mmc-hs200-1_8v; | |
| 389 | + card-detect-delay = <200>; | |
| 390 | + vmmc-supply = <&vemmc_reg>; | |
| 391 | + clock-frequency = <100000000>; | |
| 392 | + clock-freq-min-max = <400000 100000000>; | |
| 393 | + samsung,dw-mshc-ciu-div = <1>; | |
| 394 | + samsung,dw-mshc-sdr-timing = <0 1>; | |
| 395 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 396 | + pinctrl-names = "default"; | |
| 397 | + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; | |
| 398 | + bus-width = <8>; | |
| 399 | + status = "okay"; | |
| 400 | +}; | |
| 401 | + | |
| 402 | +&serial_0 { | |
| 403 | + assigned-clocks = <&cmu CLK_SCLK_UART0>; | |
| 404 | + assigned-clock-rates = <100000000>; | |
| 405 | + status = "okay"; | |
| 406 | +}; | |
| 407 | + | |
| 408 | +&serial_1 { | |
| 409 | + status = "okay"; | |
| 410 | +}; | |
| 411 | + | |
| 412 | +&tmu { | |
| 413 | + vtmu-supply = <&ldo7_reg>; | |
| 414 | + status = "okay"; | |
| 415 | +}; | |
| 416 | + | |
| 417 | +&rtc { | |
| 418 | + clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>; | |
| 419 | + clock-names = "rtc", "rtc_src"; | |
| 420 | + status = "okay"; | |
| 421 | +}; | |
| 422 | + | |
| 423 | +&xusbxti { | |
| 424 | + clock-frequency = <24000000>; | |
| 425 | +}; | |
| 426 | + | |
| 427 | +&pinctrl_0 { | |
| 428 | + pinctrl-names = "default"; | |
| 429 | + pinctrl-0 = <&sleep0>; | |
| 430 | + | |
| 431 | + sleep0: sleep-state { | |
| 432 | + PIN_SLP(gpa0-0, INPUT, DOWN); | |
| 433 | + PIN_SLP(gpa0-1, INPUT, DOWN); | |
| 434 | + PIN_SLP(gpa0-2, INPUT, DOWN); | |
| 435 | + PIN_SLP(gpa0-3, INPUT, DOWN); | |
| 436 | + PIN_SLP(gpa0-4, INPUT, DOWN); | |
| 437 | + PIN_SLP(gpa0-5, INPUT, DOWN); | |
| 438 | + PIN_SLP(gpa0-6, INPUT, DOWN); | |
| 439 | + PIN_SLP(gpa0-7, INPUT, DOWN); | |
| 440 | + | |
| 441 | + PIN_SLP(gpa1-0, INPUT, DOWN); | |
| 442 | + PIN_SLP(gpa1-1, INPUT, DOWN); | |
| 443 | + PIN_SLP(gpa1-2, INPUT, DOWN); | |
| 444 | + PIN_SLP(gpa1-3, INPUT, DOWN); | |
| 445 | + PIN_SLP(gpa1-4, INPUT, DOWN); | |
| 446 | + PIN_SLP(gpa1-5, INPUT, DOWN); | |
| 447 | + | |
| 448 | + PIN_SLP(gpb-0, PREV, NONE); | |
| 449 | + PIN_SLP(gpb-1, PREV, NONE); | |
| 450 | + PIN_SLP(gpb-2, PREV, NONE); | |
| 451 | + PIN_SLP(gpb-3, PREV, NONE); | |
| 452 | + PIN_SLP(gpb-4, INPUT, DOWN); | |
| 453 | + PIN_SLP(gpb-5, INPUT, DOWN); | |
| 454 | + PIN_SLP(gpb-6, INPUT, DOWN); | |
| 455 | + PIN_SLP(gpb-7, INPUT, DOWN); | |
| 456 | + | |
| 457 | + PIN_SLP(gpc0-0, INPUT, DOWN); | |
| 458 | + PIN_SLP(gpc0-1, INPUT, DOWN); | |
| 459 | + PIN_SLP(gpc0-2, INPUT, DOWN); | |
| 460 | + PIN_SLP(gpc0-3, INPUT, DOWN); | |
| 461 | + PIN_SLP(gpc0-4, INPUT, DOWN); | |
| 462 | + | |
| 463 | + PIN_SLP(gpc1-0, INPUT, DOWN); | |
| 464 | + PIN_SLP(gpc1-1, INPUT, DOWN); | |
| 465 | + PIN_SLP(gpc1-2, INPUT, DOWN); | |
| 466 | + PIN_SLP(gpc1-3, INPUT, DOWN); | |
| 467 | + PIN_SLP(gpc1-4, INPUT, DOWN); | |
| 468 | + | |
| 469 | + PIN_SLP(gpd0-0, INPUT, DOWN); | |
| 470 | + PIN_SLP(gpd0-1, INPUT, DOWN); | |
| 471 | + PIN_SLP(gpd0-2, INPUT, NONE); | |
| 472 | + PIN_SLP(gpd0-3, INPUT, NONE); | |
| 473 | + | |
| 474 | + PIN_SLP(gpd1-0, INPUT, NONE); | |
| 475 | + PIN_SLP(gpd1-1, INPUT, NONE); | |
| 476 | + PIN_SLP(gpd1-2, INPUT, NONE); | |
| 477 | + PIN_SLP(gpd1-3, INPUT, NONE); | |
| 478 | + }; | |
| 479 | +}; | |
| 480 | + | |
| 481 | +&pinctrl_1 { | |
| 482 | + pinctrl-names = "default"; | |
| 483 | + pinctrl-0 = <&sleep1>; | |
| 484 | + | |
| 485 | + sleep1: sleep-state { | |
| 486 | + PIN_SLP(gpe0-0, PREV, NONE); | |
| 487 | + PIN_SLP(gpe0-1, PREV, NONE); | |
| 488 | + PIN_SLP(gpe0-2, INPUT, DOWN); | |
| 489 | + PIN_SLP(gpe0-3, INPUT, DOWN); | |
| 490 | + PIN_SLP(gpe0-4, PREV, NONE); | |
| 491 | + PIN_SLP(gpe0-5, INPUT, DOWN); | |
| 492 | + PIN_SLP(gpe0-6, INPUT, DOWN); | |
| 493 | + PIN_SLP(gpe0-7, INPUT, DOWN); | |
| 494 | + | |
| 495 | + PIN_SLP(gpe1-0, INPUT, DOWN); | |
| 496 | + PIN_SLP(gpe1-1, PREV, NONE); | |
| 497 | + PIN_SLP(gpe1-2, INPUT, DOWN); | |
| 498 | + PIN_SLP(gpe1-3, INPUT, DOWN); | |
| 499 | + PIN_SLP(gpe1-4, INPUT, DOWN); | |
| 500 | + PIN_SLP(gpe1-5, INPUT, DOWN); | |
| 501 | + PIN_SLP(gpe1-6, INPUT, DOWN); | |
| 502 | + PIN_SLP(gpe1-7, INPUT, NONE); | |
| 503 | + | |
| 504 | + PIN_SLP(gpe2-0, INPUT, NONE); | |
| 505 | + PIN_SLP(gpe2-1, INPUT, NONE); | |
| 506 | + PIN_SLP(gpe2-2, INPUT, NONE); | |
| 507 | + | |
| 508 | + PIN_SLP(gpk0-0, INPUT, DOWN); | |
| 509 | + PIN_SLP(gpk0-1, INPUT, DOWN); | |
| 510 | + PIN_SLP(gpk0-2, OUT0, NONE); | |
| 511 | + PIN_SLP(gpk0-3, INPUT, DOWN); | |
| 512 | + PIN_SLP(gpk0-4, INPUT, DOWN); | |
| 513 | + PIN_SLP(gpk0-5, INPUT, DOWN); | |
| 514 | + PIN_SLP(gpk0-6, INPUT, DOWN); | |
| 515 | + PIN_SLP(gpk0-7, INPUT, DOWN); | |
| 516 | + | |
| 517 | + PIN_SLP(gpk1-0, PREV, NONE); | |
| 518 | + PIN_SLP(gpk1-1, PREV, NONE); | |
| 519 | + PIN_SLP(gpk1-2, INPUT, DOWN); | |
| 520 | + PIN_SLP(gpk1-3, PREV, NONE); | |
| 521 | + PIN_SLP(gpk1-4, PREV, NONE); | |
| 522 | + PIN_SLP(gpk1-5, PREV, NONE); | |
| 523 | + PIN_SLP(gpk1-6, PREV, NONE); | |
| 524 | + | |
| 525 | + PIN_SLP(gpk2-0, INPUT, DOWN); | |
| 526 | + PIN_SLP(gpk2-1, INPUT, DOWN); | |
| 527 | + PIN_SLP(gpk2-2, INPUT, DOWN); | |
| 528 | + PIN_SLP(gpk2-3, INPUT, DOWN); | |
| 529 | + PIN_SLP(gpk2-4, INPUT, DOWN); | |
| 530 | + PIN_SLP(gpk2-5, INPUT, DOWN); | |
| 531 | + PIN_SLP(gpk2-6, INPUT, DOWN); | |
| 532 | + | |
| 533 | + PIN_SLP(gpl0-0, INPUT, DOWN); | |
| 534 | + PIN_SLP(gpl0-1, INPUT, DOWN); | |
| 535 | + PIN_SLP(gpl0-2, INPUT, DOWN); | |
| 536 | + PIN_SLP(gpl0-3, INPUT, DOWN); | |
| 537 | + | |
| 538 | + PIN_SLP(gpm0-0, INPUT, DOWN); | |
| 539 | + PIN_SLP(gpm0-1, INPUT, DOWN); | |
| 540 | + PIN_SLP(gpm0-2, INPUT, DOWN); | |
| 541 | + PIN_SLP(gpm0-3, INPUT, DOWN); | |
| 542 | + PIN_SLP(gpm0-4, INPUT, DOWN); | |
| 543 | + PIN_SLP(gpm0-5, INPUT, DOWN); | |
| 544 | + PIN_SLP(gpm0-6, INPUT, DOWN); | |
| 545 | + PIN_SLP(gpm0-7, INPUT, DOWN); | |
| 546 | + | |
| 547 | + PIN_SLP(gpm1-0, INPUT, DOWN); | |
| 548 | + PIN_SLP(gpm1-1, INPUT, DOWN); | |
| 549 | + PIN_SLP(gpm1-2, INPUT, DOWN); | |
| 550 | + PIN_SLP(gpm1-3, INPUT, DOWN); | |
| 551 | + PIN_SLP(gpm1-4, INPUT, DOWN); | |
| 552 | + PIN_SLP(gpm1-5, INPUT, DOWN); | |
| 553 | + PIN_SLP(gpm1-6, INPUT, DOWN); | |
| 554 | + | |
| 555 | + PIN_SLP(gpm2-0, INPUT, DOWN); | |
| 556 | + PIN_SLP(gpm2-1, INPUT, DOWN); | |
| 557 | + PIN_SLP(gpm2-2, INPUT, DOWN); | |
| 558 | + PIN_SLP(gpm2-3, INPUT, DOWN); | |
| 559 | + PIN_SLP(gpm2-4, INPUT, DOWN); | |
| 560 | + | |
| 561 | + PIN_SLP(gpm3-0, INPUT, DOWN); | |
| 562 | + PIN_SLP(gpm3-1, INPUT, DOWN); | |
| 563 | + PIN_SLP(gpm3-2, INPUT, DOWN); | |
| 564 | + PIN_SLP(gpm3-3, INPUT, DOWN); | |
| 565 | + PIN_SLP(gpm3-4, INPUT, DOWN); | |
| 566 | + PIN_SLP(gpm3-5, INPUT, DOWN); | |
| 567 | + PIN_SLP(gpm3-6, INPUT, DOWN); | |
| 568 | + PIN_SLP(gpm3-7, INPUT, DOWN); | |
| 569 | + | |
| 570 | + PIN_SLP(gpm4-0, INPUT, DOWN); | |
| 571 | + PIN_SLP(gpm4-1, INPUT, DOWN); | |
| 572 | + PIN_SLP(gpm4-2, INPUT, DOWN); | |
| 573 | + PIN_SLP(gpm4-3, INPUT, DOWN); | |
| 574 | + PIN_SLP(gpm4-4, INPUT, DOWN); | |
| 575 | + PIN_SLP(gpm4-5, INPUT, DOWN); | |
| 576 | + PIN_SLP(gpm4-6, INPUT, DOWN); | |
| 577 | + PIN_SLP(gpm4-7, INPUT, DOWN); | |
| 578 | + }; | |
| 579 | +}; | |
| @@ -12,6 +12,22 @@ · 11 unmodified lines | ||
| 12 | 12 | * published by the Free Software Foundation. |
| 13 | 13 | */ |
| 14 | 14 | |
| 15 | +#define PIN_PULL_NONE 0 | |
| 16 | +#define PIN_PULL_DOWN 1 | |
| 17 | +#define PIN_PULL_UP 3 | |
| 18 | + | |
| 19 | +#define PIN_PDN_OUT0 0 | |
| 20 | +#define PIN_PDN_OUT1 1 | |
| 21 | +#define PIN_PDN_INPUT 2 | |
| 22 | +#define PIN_PDN_PREV 3 | |
| 23 | + | |
| 24 | +#define PIN_SLP(_pin, _mode, _pull) \ | |
| 25 | + _pin { \ | |
| 26 | + samsung,pins = #_pin; \ | |
| 27 | + samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \ | |
| 28 | + samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \ | |
| 29 | + } | |
| 30 | + | |
| 15 | 31 | &pinctrl_0 { |
| 16 | 32 | gpa0: gpa0 { |
| 17 | 33 | gpio-controller; |
| @@ -0,0 +1,682 @@ | ||
| 1 | +/* | |
| 2 | + * Samsung's Exynos3250 based Rinato board device tree source | |
| 3 | + * | |
| 4 | + * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
| 5 | + * http://www.samsung.com | |
| 6 | + * | |
| 7 | + * Device tree source file for Samsung's Rinato board which is based on | |
| 8 | + * Samsung Exynos3250 SoC. | |
| 9 | + * | |
| 10 | + * This program is free software; you can redistribute it and/or modify | |
| 11 | + * it under the terms of the GNU General Public License version 2 as | |
| 12 | + * published by the Free Software Foundation. | |
| 13 | + */ | |
| 14 | + | |
| 15 | +/dts-v1/; | |
| 16 | +#include "exynos3250.dtsi" | |
| 17 | +#include <dt-bindings/input/input.h> | |
| 18 | + | |
| 19 | +/ { | |
| 20 | + model = "Samsung Rinato board"; | |
| 21 | + compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3"; | |
| 22 | + | |
| 23 | + aliases { | |
| 24 | + i2c7 = &i2c_max77836; | |
| 25 | + }; | |
| 26 | + | |
| 27 | + memory { | |
| 28 | + reg = <0x40000000 0x1ff00000>; | |
| 29 | + }; | |
| 30 | + | |
| 31 | + firmware@0205F000 { | |
| 32 | + compatible = "samsung,secure-firmware"; | |
| 33 | + reg = <0x0205F000 0x1000>; | |
| 34 | + }; | |
| 35 | + | |
| 36 | + gpio_keys { | |
| 37 | + compatible = "gpio-keys"; | |
| 38 | + | |
| 39 | + power_key { | |
| 40 | + interrupt-parent = <&gpx2>; | |
| 41 | + interrupts = <7 0>; | |
| 42 | + gpios = <&gpx2 7 1>; | |
| 43 | + linux,code = <KEY_POWER>; | |
| 44 | + label = "power key"; | |
| 45 | + debounce-interval = <10>; | |
| 46 | + gpio-key,wakeup; | |
| 47 | + }; | |
| 48 | + }; | |
| 49 | + | |
| 50 | + i2c_max77836: i2c-gpio-0 { | |
| 51 | + compatible = "i2c-gpio"; | |
| 52 | + gpios = <&gpd0 2 0>, <&gpd0 3 0>; | |
| 53 | + #address-cells = <1>; | |
| 54 | + #size-cells = <0>; | |
| 55 | + | |
| 56 | + max77836: subpmic@25 { | |
| 57 | + compatible = "maxim,max77836"; | |
| 58 | + interrupt-parent = <&gpx1>; | |
| 59 | + interrupts = <5 0>; | |
| 60 | + reg = <0x25>; | |
| 61 | + wakeup; | |
| 62 | + | |
| 63 | + muic: max77836-muic { | |
| 64 | + compatible = "maxim,max77836-muic"; | |
| 65 | + }; | |
| 66 | + | |
| 67 | + regulators { | |
| 68 | + compatible = "maxim,max77836-regulator"; | |
| 69 | + safeout_reg: SAFEOUT { | |
| 70 | + regulator-name = "SAFEOUT"; | |
| 71 | + }; | |
| 72 | + | |
| 73 | + charger_reg: CHARGER { | |
| 74 | + regulator-name = "CHARGER"; | |
| 75 | + regulator-min-microamp = <45000>; | |
| 76 | + regulator-max-microamp = <475000>; | |
| 77 | + regulator-boot-on; | |
| 78 | + }; | |
| 79 | + | |
| 80 | + motor_reg: LDO1 { | |
| 81 | + regulator-name = "MOT_2.7V"; | |
| 82 | + regulator-min-microvolt = <1100000>; | |
| 83 | + regulator-max-microvolt = <2700000>; | |
| 84 | + }; | |
| 85 | + | |
| 86 | + LDO2 { | |
| 87 | + regulator-name = "UNUSED_LDO2"; | |
| 88 | + regulator-min-microvolt = <800000>; | |
| 89 | + regulator-max-microvolt = <3950000>; | |
| 90 | + }; | |
| 91 | + }; | |
| 92 | + | |
| 93 | + charger { | |
| 94 | + compatible = "maxim,max77836-charger"; | |
| 95 | + | |
| 96 | + maxim,constant-uvolt = <4350000>; | |
| 97 | + maxim,fast-charge-uamp = <225000>; | |
| 98 | + maxim,eoc-uamp = <7500>; | |
| 99 | + maxim,ovp-uvolt = <6500000>; | |
| 100 | + }; | |
| 101 | + }; | |
| 102 | + }; | |
| 103 | +}; | |
| 104 | + | |
| 105 | +&adc { | |
| 106 | + vdd-supply = <&ldo3_reg>; | |
| 107 | + status = "okay"; | |
| 108 | + assigned-clocks = <&cmu CLK_SCLK_TSADC>; | |
| 109 | + assigned-clock-rates = <6000000>; | |
| 110 | + | |
| 111 | + thermistor-ap { | |
| 112 | + compatible = "ntc,ncp15wb473"; | |
| 113 | + pullup-uv = <1800000>; | |
| 114 | + pullup-ohm = <100000>; | |
| 115 | + pulldown-ohm = <100000>; | |
| 116 | + io-channels = <&adc 0>; | |
| 117 | + }; | |
| 118 | + | |
| 119 | + thermistor-battery { | |
| 120 | + compatible = "ntc,ncp15wb473"; | |
| 121 | + pullup-uv = <1800000>; | |
| 122 | + pullup-ohm = <100000>; | |
| 123 | + pulldown-ohm = <100000>; | |
| 124 | + io-channels = <&adc 1>; | |
| 125 | + }; | |
| 126 | +}; | |
| 127 | + | |
| 128 | +&i2c_0 { | |
| 129 | + #address-cells = <1>; | |
| 130 | + #size-cells = <0>; | |
| 131 | + samsung,i2c-sda-delay = <100>; | |
| 132 | + samsung,i2c-slave-addr = <0x10>; | |
| 133 | + samsung,i2c-max-bus-freq = <100000>; | |
| 134 | + status = "okay"; | |
| 135 | + | |
| 136 | + s2mps14_pmic@66 { | |
| 137 | + compatible = "samsung,s2mps14-pmic"; | |
| 138 | + interrupt-parent = <&gpx0>; | |
| 139 | + interrupts = <7 0>; | |
| 140 | + reg = <0x66>; | |
| 141 | + wakeup; | |
| 142 | + | |
| 143 | + s2mps14_osc: clocks { | |
| 144 | + compatible = "samsung,s2mps14-clk"; | |
| 145 | + #clock-cells = <1>; | |
| 146 | + clock-output-names = "s2mps14_ap", "unused", | |
| 147 | + "s2mps14_bt"; | |
| 148 | + }; | |
| 149 | + | |
| 150 | + regulators { | |
| 151 | + ldo1_reg: LDO1 { | |
| 152 | + regulator-name = "VAP_ALIVE_1.0V"; | |
| 153 | + regulator-min-microvolt = <1000000>; | |
| 154 | + regulator-max-microvolt = <1000000>; | |
| 155 | + regulator-always-on; | |
| 156 | + | |
| 157 | + regulator-state-mem { | |
| 158 | + regulator-on-in-suspend; | |
| 159 | + }; | |
| 160 | + }; | |
| 161 | + | |
| 162 | + ldo2_reg: LDO2 { | |
| 163 | + regulator-name = "VAP_M1_1.2V"; | |
| 164 | + regulator-min-microvolt = <1200000>; | |
| 165 | + regulator-max-microvolt = <1200000>; | |
| 166 | + regulator-always-on; | |
| 167 | + | |
| 168 | + regulator-state-mem { | |
| 169 | + regulator-off-in-suspend; | |
| 170 | + }; | |
| 171 | + }; | |
| 172 | + | |
| 173 | + ldo3_reg: LDO3 { | |
| 174 | + regulator-name = "VCC_AP_1.8V"; | |
| 175 | + regulator-min-microvolt = <1800000>; | |
| 176 | + regulator-max-microvolt = <1800000>; | |
| 177 | + regulator-always-on; | |
| 178 | + | |
| 179 | + regulator-state-mem { | |
| 180 | + regulator-off-in-suspend; | |
| 181 | + }; | |
| 182 | + }; | |
| 183 | + | |
| 184 | + ldo4_reg: LDO4 { | |
| 185 | + regulator-name = "VAP_AVDD_PLL1"; | |
| 186 | + regulator-min-microvolt = <1800000>; | |
| 187 | + regulator-max-microvolt = <1800000>; | |
| 188 | + regulator-always-on; | |
| 189 | + | |
| 190 | + regulator-state-mem { | |
| 191 | + regulator-off-in-suspend; | |
| 192 | + }; | |
| 193 | + }; | |
| 194 | + | |
| 195 | + ldo5_reg: LDO5 { | |
| 196 | + regulator-name = "VAP_PLL_ISO_1.0V"; | |
| 197 | + regulator-min-microvolt = <1000000>; | |
| 198 | + regulator-max-microvolt = <1000000>; | |
| 199 | + regulator-always-on; | |
| 200 | + | |
| 201 | + regulator-state-mem { | |
| 202 | + regulator-off-in-suspend; | |
| 203 | + }; | |
| 204 | + }; | |
| 205 | + | |
| 206 | + ldo6_reg: LDO6 { | |
| 207 | + regulator-name = "VAP_VMIPI_1.0V"; | |
| 208 | + regulator-min-microvolt = <1000000>; | |
| 209 | + regulator-max-microvolt = <1000000>; | |
| 210 | + regulator-always-on; | |
| 211 | + | |
| 212 | + regulator-state-mem { | |
| 213 | + regulator-off-in-suspend; | |
| 214 | + }; | |
| 215 | + }; | |
| 216 | + | |
| 217 | + ldo7_reg: LDO7 { | |
| 218 | + regulator-name = "VAP_AVDD_1.8V"; | |
| 219 | + regulator-min-microvolt = <1800000>; | |
| 220 | + regulator-max-microvolt = <1800000>; | |
| 221 | + regulator-always-on; | |
| 222 | + | |
| 223 | + regulator-state-mem { | |
| 224 | + regulator-off-in-suspend; | |
| 225 | + }; | |
| 226 | + }; | |
| 227 | + | |
| 228 | + ldo8_reg: LDO8 { | |
| 229 | + regulator-name = "VAP_USB_3.0V"; | |
| 230 | + regulator-min-microvolt = <3000000>; | |
| 231 | + regulator-max-microvolt = <3000000>; | |
| 232 | + regulator-always-on; | |
| 233 | + | |
| 234 | + regulator-state-mem { | |
| 235 | + regulator-off-in-suspend; | |
| 236 | + }; | |
| 237 | + }; | |
| 238 | + | |
| 239 | + ldo9_reg: LDO9 { | |
| 240 | + regulator-name = "V_LPDDR_1.2V"; | |
| 241 | + regulator-min-microvolt = <1200000>; | |
| 242 | + regulator-max-microvolt = <1200000>; | |
| 243 | + regulator-always-on; | |
| 244 | + | |
| 245 | + regulator-state-mem { | |
| 246 | + regulator-on-in-suspend; | |
| 247 | + }; | |
| 248 | + }; | |
| 249 | + | |
| 250 | + ldo10_reg: LDO10 { | |
| 251 | + regulator-name = "UNUSED_LDO10"; | |
| 252 | + regulator-min-microvolt = <1000000>; | |
| 253 | + regulator-max-microvolt = <1000000>; | |
| 254 | + | |
| 255 | + regulator-state-mem { | |
| 256 | + regulator-off-in-suspend; | |
| 257 | + }; | |
| 258 | + }; | |
| 259 | + | |
| 260 | + ldo11_reg: LDO11 { | |
| 261 | + regulator-name = "V_EMMC_1.8V"; | |
| 262 | + regulator-min-microvolt = <1800000>; | |
| 263 | + regulator-max-microvolt = <1800000>; | |
| 264 | + samsung,ext-control-gpios = <&gpk0 2 0>; | |
| 265 | + }; | |
| 266 | + | |
| 267 | + ldo12_reg: LDO12 { | |
| 268 | + regulator-name = "V_EMMC_2.8V"; | |
| 269 | + regulator-min-microvolt = <2800000>; | |
| 270 | + regulator-max-microvolt = <2800000>; | |
| 271 | + samsung,ext-control-gpios = <&gpk0 2 0>; | |
| 272 | + }; | |
| 273 | + | |
| 274 | + ldo13_reg: LDO13 { | |
| 275 | + regulator-name = "CAM_AVDD_2.8V"; | |
| 276 | + regulator-min-microvolt = <2800000>; | |
| 277 | + regulator-max-microvolt = <2800000>; | |
| 278 | + | |
| 279 | + regulator-state-mem { | |
| 280 | + regulator-off-in-suspend; | |
| 281 | + }; | |
| 282 | + }; | |
| 283 | + | |
| 284 | + ldo14_reg: LDO14 { | |
| 285 | + regulator-name = "UNUSED_LDO14"; | |
| 286 | + regulator-min-microvolt = <2700000>; | |
| 287 | + regulator-max-microvolt = <2700000>; | |
| 288 | + | |
| 289 | + regulator-state-mem { | |
| 290 | + regulator-off-in-suspend; | |
| 291 | + }; | |
| 292 | + }; | |
| 293 | + | |
| 294 | + ldo15_reg: LDO15 { | |
| 295 | + regulator-name = "TSP_AVDD_3.3V"; | |
| 296 | + regulator-min-microvolt = <3300000>; | |
| 297 | + regulator-max-microvolt = <3300000>; | |
| 298 | + | |
| 299 | + regulator-state-mem { | |
| 300 | + regulator-off-in-suspend; | |
| 301 | + }; | |
| 302 | + }; | |
| 303 | + | |
| 304 | + ldo16_reg: LDO16 { | |
| 305 | + regulator-name = "LCD_VDD_3.3V"; | |
| 306 | + regulator-min-microvolt = <3300000>; | |
| 307 | + regulator-max-microvolt = <3300000>; | |
| 308 | + | |
| 309 | + regulator-state-mem { | |
| 310 | + regulator-off-in-suspend; | |
| 311 | + }; | |
| 312 | + }; | |
| 313 | + | |
| 314 | + ldo17_reg: LDO17 { | |
| 315 | + regulator-name = "V_IRLED_3.3V"; | |
| 316 | + regulator-min-microvolt = <3300000>; | |
| 317 | + regulator-max-microvolt = <3300000>; | |
| 318 | + | |
| 319 | + regulator-state-mem { | |
| 320 | + regulator-off-in-suspend; | |
| 321 | + }; | |
| 322 | + }; | |
| 323 | + | |
| 324 | + ldo18_reg: LDO18 { | |
| 325 | + regulator-name = "CAM_AF_2.8V"; | |
| 326 | + regulator-min-microvolt = <2800000>; | |
| 327 | + regulator-max-microvolt = <2800000>; | |
| 328 | + | |
| 329 | + regulator-state-mem { | |
| 330 | + regulator-off-in-suspend; | |
| 331 | + }; | |
| 332 | + }; | |
| 333 | + | |
| 334 | + ldo19_reg: LDO19 { | |
| 335 | + regulator-name = "TSP_VDD_1.8V"; | |
| 336 | + regulator-min-microvolt = <1800000>; | |
| 337 | + regulator-max-microvolt = <1800000>; | |
| 338 | + | |
| 339 | + regulator-state-mem { | |
| 340 | + regulator-off-in-suspend; | |
| 341 | + }; | |
| 342 | + }; | |
| 343 | + | |
| 344 | + ldo20_reg: LDO20 { | |
| 345 | + regulator-name = "LCD_VDD_1.8V"; | |
| 346 | + regulator-min-microvolt = <1800000>; | |
| 347 | + regulator-max-microvolt = <1800000>; | |
| 348 | + | |
| 349 | + regulator-state-mem { | |
| 350 | + regulator-off-in-suspend; | |
| 351 | + }; | |
| 352 | + }; | |
| 353 | + | |
| 354 | + ldo21_reg: LDO21 { | |
| 355 | + regulator-name = "CAM_IO_1.8V"; | |
| 356 | + regulator-min-microvolt = <1800000>; | |
| 357 | + regulator-max-microvolt = <1800000>; | |
| 358 | + | |
| 359 | + regulator-state-mem { | |
| 360 | + regulator-off-in-suspend; | |
| 361 | + }; | |
| 362 | + }; | |
| 363 | + | |
| 364 | + ldo22_reg: LDO22 { | |
| 365 | + regulator-name = "CAM_DVDD_1.2V"; | |
| 366 | + regulator-min-microvolt = <1200000>; | |
| 367 | + regulator-max-microvolt = <1200000>; | |
| 368 | + | |
| 369 | + regulator-state-mem { | |
| 370 | + regulator-off-in-suspend; | |
| 371 | + }; | |
| 372 | + }; | |
| 373 | + | |
| 374 | + ldo23_reg: LDO23 { | |
| 375 | + regulator-name = "HRM_VCC_1.8V"; | |
| 376 | + regulator-min-microvolt = <1800000>; | |
| 377 | + regulator-max-microvolt = <1800000>; | |
| 378 | + regulator-always-on; | |
| 379 | + }; | |
| 380 | + | |
| 381 | + ldo24_reg: LDO24 { | |
| 382 | + regulator-name = "HRM_VCC_3.3V"; | |
| 383 | + regulator-min-microvolt = <3000000>; | |
| 384 | + regulator-max-microvolt = <3000000>; | |
| 385 | + | |
| 386 | + regulator-state-mem { | |
| 387 | + regulator-off-in-suspend; | |
| 388 | + }; | |
| 389 | + }; | |
| 390 | + | |
| 391 | + ldo25_reg: LDO25 { | |
| 392 | + regulator-name = "UNUSED_LDO25"; | |
| 393 | + regulator-min-microvolt = <3000000>; | |
| 394 | + regulator-max-microvolt = <3000000>; | |
| 395 | + | |
| 396 | + regulator-state-mem { | |
| 397 | + regulator-off-in-suspend; | |
| 398 | + }; | |
| 399 | + }; | |
| 400 | + | |
| 401 | + buck1_reg: BUCK1 { | |
| 402 | + regulator-name = "VAP_MIF_1.0V"; | |
| 403 | + regulator-min-microvolt = <800000>; | |
| 404 | + regulator-max-microvolt = <900000>; | |
| 405 | + regulator-always-on; | |
| 406 | + | |
| 407 | + regulator-state-mem { | |
| 408 | + regulator-off-in-suspend; | |
| 409 | + }; | |
| 410 | + }; | |
| 411 | + | |
| 412 | + buck2_reg: BUCK2 { | |
| 413 | + regulator-name = "VAP_ARM_1.0V"; | |
| 414 | + regulator-min-microvolt = <850000>; | |
| 415 | + regulator-max-microvolt = <1150000>; | |
| 416 | + regulator-always-on; | |
| 417 | + | |
| 418 | + regulator-state-mem { | |
| 419 | + regulator-off-in-suspend; | |
| 420 | + }; | |
| 421 | + }; | |
| 422 | + | |
| 423 | + buck3_reg: BUCK3 { | |
| 424 | + regulator-name = "VAP_INT3D_1.0V"; | |
| 425 | + regulator-min-microvolt = <850000>; | |
| 426 | + regulator-max-microvolt = <1000000>; | |
| 427 | + regulator-always-on; | |
| 428 | + | |
| 429 | + regulator-state-mem { | |
| 430 | + regulator-off-in-suspend; | |
| 431 | + }; | |
| 432 | + }; | |
| 433 | + | |
| 434 | + buck4_reg: BUCK4 { | |
| 435 | + regulator-name = "VCC_SUB_1.95V"; | |
| 436 | + regulator-min-microvolt = <1950000>; | |
| 437 | + regulator-max-microvolt = <1950000>; | |
| 438 | + regulator-always-on; | |
| 439 | + | |
| 440 | + regulator-state-mem { | |
| 441 | + regulator-on-in-suspend; | |
| 442 | + }; | |
| 443 | + }; | |
| 444 | + | |
| 445 | + buck5_reg: BUCK5 { | |
| 446 | + regulator-name = "VCC_SUB_1.35V"; | |
| 447 | + regulator-min-microvolt = <1350000>; | |
| 448 | + regulator-max-microvolt = <1350000>; | |
| 449 | + regulator-always-on; | |
| 450 | + | |
| 451 | + regulator-state-mem { | |
| 452 | + regulator-on-in-suspend; | |
| 453 | + }; | |
| 454 | + }; | |
| 455 | + }; | |
| 456 | + }; | |
| 457 | +}; | |
| 458 | + | |
| 459 | +&i2c_1 { | |
| 460 | + #address-cells = <1>; | |
| 461 | + #size-cells = <0>; | |
| 462 | + samsung,i2c-sda-delay = <100>; | |
| 463 | + samsung,i2c-slave-addr = <0x10>; | |
| 464 | + samsung,i2c-max-bus-freq = <400000>; | |
| 465 | + status = "okay"; | |
| 466 | + | |
| 467 | + fuelgauge@36 { | |
| 468 | + compatible = "maxim,max77836-battery"; | |
| 469 | + interrupt-parent = <&gpx1>; | |
| 470 | + interrupts = <2 8>; | |
| 471 | + reg = <0x36>; | |
| 472 | + }; | |
| 473 | +}; | |
| 474 | + | |
| 475 | +&i2s2 { | |
| 476 | + status = "okay"; | |
| 477 | +}; | |
| 478 | + | |
| 479 | +&mfc { | |
| 480 | + status = "okay"; | |
| 481 | +}; | |
| 482 | + | |
| 483 | +&mshc_0 { | |
| 484 | + #address-cells = <1>; | |
| 485 | + #size-cells = <0>; | |
| 486 | + num-slots = <1>; | |
| 487 | + broken-cd; | |
| 488 | + non-removable; | |
| 489 | + cap-mmc-highspeed; | |
| 490 | + desc-num = <4>; | |
| 491 | + mmc-hs200-1_8v; | |
| 492 | + card-detect-delay = <200>; | |
| 493 | + vmmc-supply = <&ldo12_reg>; | |
| 494 | + clock-frequency = <100000000>; | |
| 495 | + clock-freq-min-max = <400000 100000000>; | |
| 496 | + samsung,dw-mshc-ciu-div = <1>; | |
| 497 | + samsung,dw-mshc-sdr-timing = <0 1>; | |
| 498 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 499 | + pinctrl-names = "default"; | |
| 500 | + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; | |
| 501 | + bus-width = <8>; | |
| 502 | + status = "okay"; | |
| 503 | +}; | |
| 504 | + | |
| 505 | +&serial_0 { | |
| 506 | + assigned-clocks = <&cmu CLK_SCLK_UART0>; | |
| 507 | + assigned-clock-rates = <100000000>; | |
| 508 | + status = "okay"; | |
| 509 | +}; | |
| 510 | + | |
| 511 | +&serial_1 { | |
| 512 | + status = "okay"; | |
| 513 | +}; | |
| 514 | + | |
| 515 | +&tmu { | |
| 516 | + vtmu-supply = <&ldo7_reg>; | |
| 517 | + status = "okay"; | |
| 518 | +}; | |
| 519 | + | |
| 520 | +&rtc { | |
| 521 | + clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>; | |
| 522 | + clock-names = "rtc", "rtc_src"; | |
| 523 | + status = "okay"; | |
| 524 | +}; | |
| 525 | + | |
| 526 | +&xusbxti { | |
| 527 | + clock-frequency = <24000000>; | |
| 528 | +}; | |
| 529 | + | |
| 530 | +&pinctrl_0 { | |
| 531 | + pinctrl-names = "default"; | |
| 532 | + pinctrl-0 = <&sleep0>; | |
| 533 | + | |
| 534 | + sleep0: sleep-state { | |
| 535 | + PIN_SLP(gpa0-0, INPUT, DOWN); | |
| 536 | + PIN_SLP(gpa0-1, INPUT, DOWN); | |
| 537 | + PIN_SLP(gpa0-2, INPUT, DOWN); | |
| 538 | + PIN_SLP(gpa0-3, INPUT, DOWN); | |
| 539 | + PIN_SLP(gpa0-4, INPUT, DOWN); | |
| 540 | + PIN_SLP(gpa0-5, INPUT, DOWN); | |
| 541 | + PIN_SLP(gpa0-6, INPUT, DOWN); | |
| 542 | + PIN_SLP(gpa0-7, INPUT, DOWN); | |
| 543 | + | |
| 544 | + PIN_SLP(gpa1-0, INPUT, DOWN); | |
| 545 | + PIN_SLP(gpa1-1, INPUT, DOWN); | |
| 546 | + PIN_SLP(gpa1-2, INPUT, DOWN); | |
| 547 | + PIN_SLP(gpa1-3, INPUT, DOWN); | |
| 548 | + PIN_SLP(gpa1-4, INPUT, DOWN); | |
| 549 | + PIN_SLP(gpa1-5, INPUT, DOWN); | |
| 550 | + | |
| 551 | + PIN_SLP(gpb-0, PREV, NONE); | |
| 552 | + PIN_SLP(gpb-1, PREV, NONE); | |
| 553 | + PIN_SLP(gpb-2, PREV, NONE); | |
| 554 | + PIN_SLP(gpb-3, PREV, NONE); | |
| 555 | + PIN_SLP(gpb-4, INPUT, DOWN); | |
| 556 | + PIN_SLP(gpb-5, INPUT, DOWN); | |
| 557 | + PIN_SLP(gpb-6, INPUT, DOWN); | |
| 558 | + PIN_SLP(gpb-7, INPUT, DOWN); | |
| 559 | + | |
| 560 | + PIN_SLP(gpc0-0, INPUT, DOWN); | |
| 561 | + PIN_SLP(gpc0-1, INPUT, DOWN); | |
| 562 | + PIN_SLP(gpc0-2, INPUT, DOWN); | |
| 563 | + PIN_SLP(gpc0-3, INPUT, DOWN); | |
| 564 | + PIN_SLP(gpc0-4, INPUT, DOWN); | |
| 565 | + | |
| 566 | + PIN_SLP(gpc1-0, INPUT, DOWN); | |
| 567 | + PIN_SLP(gpc1-1, INPUT, DOWN); | |
| 568 | + PIN_SLP(gpc1-2, INPUT, DOWN); | |
| 569 | + PIN_SLP(gpc1-3, INPUT, DOWN); | |
| 570 | + PIN_SLP(gpc1-4, INPUT, DOWN); | |
| 571 | + | |
| 572 | + PIN_SLP(gpd0-0, INPUT, DOWN); | |
| 573 | + PIN_SLP(gpd0-1, INPUT, DOWN); | |
| 574 | + PIN_SLP(gpd0-2, INPUT, NONE); | |
| 575 | + PIN_SLP(gpd0-3, INPUT, NONE); | |
| 576 | + | |
| 577 | + PIN_SLP(gpd1-0, INPUT, NONE); | |
| 578 | + PIN_SLP(gpd1-1, INPUT, NONE); | |
| 579 | + PIN_SLP(gpd1-2, INPUT, NONE); | |
| 580 | + PIN_SLP(gpd1-3, INPUT, NONE); | |
| 581 | + }; | |
| 582 | +}; | |
| 583 | + | |
| 584 | +&pinctrl_1 { | |
| 585 | + pinctrl-names = "default"; | |
| 586 | + pinctrl-0 = <&sleep1>; | |
| 587 | + | |
| 588 | + sleep1: sleep-state { | |
| 589 | + PIN_SLP(gpe0-0, PREV, NONE); | |
| 590 | + PIN_SLP(gpe0-1, PREV, NONE); | |
| 591 | + PIN_SLP(gpe0-2, INPUT, DOWN); | |
| 592 | + PIN_SLP(gpe0-3, INPUT, UP); | |
| 593 | + PIN_SLP(gpe0-4, INPUT, DOWN); | |
| 594 | + PIN_SLP(gpe0-5, INPUT, DOWN); | |
| 595 | + PIN_SLP(gpe0-6, INPUT, DOWN); | |
| 596 | + PIN_SLP(gpe0-7, INPUT, DOWN); | |
| 597 | + | |
| 598 | + PIN_SLP(gpe1-0, INPUT, DOWN); | |
| 599 | + PIN_SLP(gpe1-1, PREV, NONE); | |
| 600 | + PIN_SLP(gpe1-2, INPUT, DOWN); | |
| 601 | + PIN_SLP(gpe1-3, INPUT, DOWN); | |
| 602 | + PIN_SLP(gpe1-4, INPUT, DOWN); | |
| 603 | + PIN_SLP(gpe1-5, INPUT, DOWN); | |
| 604 | + PIN_SLP(gpe1-6, INPUT, DOWN); | |
| 605 | + PIN_SLP(gpe1-7, INPUT, NONE); | |
| 606 | + | |
| 607 | + PIN_SLP(gpe2-0, INPUT, NONE); | |
| 608 | + PIN_SLP(gpe2-1, INPUT, NONE); | |
| 609 | + PIN_SLP(gpe2-2, INPUT, NONE); | |
| 610 | + | |
| 611 | + PIN_SLP(gpk0-0, INPUT, DOWN); | |
| 612 | + PIN_SLP(gpk0-1, INPUT, DOWN); | |
| 613 | + PIN_SLP(gpk0-2, OUT0, NONE); | |
| 614 | + PIN_SLP(gpk0-3, INPUT, DOWN); | |
| 615 | + PIN_SLP(gpk0-4, INPUT, DOWN); | |
| 616 | + PIN_SLP(gpk0-5, INPUT, DOWN); | |
| 617 | + PIN_SLP(gpk0-6, INPUT, DOWN); | |
| 618 | + PIN_SLP(gpk0-7, INPUT, DOWN); | |
| 619 | + | |
| 620 | + PIN_SLP(gpk1-0, INPUT, DOWN); | |
| 621 | + PIN_SLP(gpk1-1, INPUT, DOWN); | |
| 622 | + PIN_SLP(gpk1-2, INPUT, DOWN); | |
| 623 | + PIN_SLP(gpk1-3, INPUT, DOWN); | |
| 624 | + PIN_SLP(gpk1-4, INPUT, DOWN); | |
| 625 | + PIN_SLP(gpk1-5, INPUT, DOWN); | |
| 626 | + PIN_SLP(gpk1-6, INPUT, DOWN); | |
| 627 | + | |
| 628 | + PIN_SLP(gpk2-0, INPUT, DOWN); | |
| 629 | + PIN_SLP(gpk2-1, INPUT, DOWN); | |
| 630 | + PIN_SLP(gpk2-2, INPUT, DOWN); | |
| 631 | + PIN_SLP(gpk2-3, INPUT, DOWN); | |
| 632 | + PIN_SLP(gpk2-4, INPUT, DOWN); | |
| 633 | + PIN_SLP(gpk2-5, INPUT, DOWN); | |
| 634 | + PIN_SLP(gpk2-6, INPUT, DOWN); | |
| 635 | + | |
| 636 | + PIN_SLP(gpl0-0, INPUT, DOWN); | |
| 637 | + PIN_SLP(gpl0-1, INPUT, DOWN); | |
| 638 | + PIN_SLP(gpl0-2, INPUT, DOWN); | |
| 639 | + PIN_SLP(gpl0-3, INPUT, DOWN); | |
| 640 | + | |
| 641 | + PIN_SLP(gpm0-0, INPUT, DOWN); | |
| 642 | + PIN_SLP(gpm0-1, INPUT, DOWN); | |
| 643 | + PIN_SLP(gpm0-2, INPUT, DOWN); | |
| 644 | + PIN_SLP(gpm0-3, INPUT, DOWN); | |
| 645 | + PIN_SLP(gpm0-4, INPUT, DOWN); | |
| 646 | + PIN_SLP(gpm0-5, INPUT, DOWN); | |
| 647 | + PIN_SLP(gpm0-6, INPUT, DOWN); | |
| 648 | + PIN_SLP(gpm0-7, INPUT, DOWN); | |
| 649 | + | |
| 650 | + PIN_SLP(gpm1-0, INPUT, DOWN); | |
| 651 | + PIN_SLP(gpm1-1, INPUT, DOWN); | |
| 652 | + PIN_SLP(gpm1-2, INPUT, DOWN); | |
| 653 | + PIN_SLP(gpm1-3, INPUT, DOWN); | |
| 654 | + PIN_SLP(gpm1-4, INPUT, DOWN); | |
| 655 | + PIN_SLP(gpm1-5, INPUT, DOWN); | |
| 656 | + PIN_SLP(gpm1-6, INPUT, DOWN); | |
| 657 | + | |
| 658 | + PIN_SLP(gpm2-0, INPUT, DOWN); | |
| 659 | + PIN_SLP(gpm2-1, INPUT, DOWN); | |
| 660 | + PIN_SLP(gpm2-2, INPUT, DOWN); | |
| 661 | + PIN_SLP(gpm2-3, INPUT, DOWN); | |
| 662 | + PIN_SLP(gpm2-4, INPUT, DOWN); | |
| 663 | + | |
| 664 | + PIN_SLP(gpm3-0, INPUT, DOWN); | |
| 665 | + PIN_SLP(gpm3-1, INPUT, DOWN); | |
| 666 | + PIN_SLP(gpm3-2, INPUT, DOWN); | |
| 667 | + PIN_SLP(gpm3-3, INPUT, DOWN); | |
| 668 | + PIN_SLP(gpm3-4, INPUT, DOWN); | |
| 669 | + PIN_SLP(gpm3-5, INPUT, DOWN); | |
| 670 | + PIN_SLP(gpm3-6, INPUT, DOWN); | |
| 671 | + PIN_SLP(gpm3-7, INPUT, DOWN); | |
| 672 | + | |
| 673 | + PIN_SLP(gpm4-0, INPUT, DOWN); | |
| 674 | + PIN_SLP(gpm4-1, INPUT, DOWN); | |
| 675 | + PIN_SLP(gpm4-2, INPUT, DOWN); | |
| 676 | + PIN_SLP(gpm4-3, INPUT, DOWN); | |
| 677 | + PIN_SLP(gpm4-4, INPUT, DOWN); | |
| 678 | + PIN_SLP(gpm4-5, INPUT, DOWN); | |
| 679 | + PIN_SLP(gpm4-6, INPUT, DOWN); | |
| 680 | + PIN_SLP(gpm4-7, INPUT, DOWN); | |
| 681 | + }; | |
| 682 | +}; | |
| @@ -320,6 +320,16 @@ · 319 unmodified lines | ||
| 320 | 320 | status = "disabled"; |
| 321 | 321 | }; |
| 322 | 322 | |
| 323 | + mfc: codec@13400000 { | |
| 324 | + compatible = "samsung,mfc-v7"; | |
| 325 | + reg = <0x13400000 0x10000>; | |
| 326 | + interrupts = <0 102 0>; | |
| 327 | + clock-names = "mfc", "sclk_mfc"; | |
| 328 | + clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; | |
| 329 | + samsung,power-domain = <&pd_mfc>; | |
| 330 | + status = "disabled"; | |
| 331 | + }; | |
| 332 | + | |
| 323 | 333 | serial_0: serial@13800000 { |
| 324 | 334 | compatible = "samsung,exynos4210-uart"; |
| 325 | 335 | reg = <0x13800000 0x100>; |
| @@ -392,8 +392,8 @@ · 391 unmodified lines | ||
| 392 | 392 | reg = <0x13400000 0x10000>; |
| 393 | 393 | interrupts = <0 94 0>; |
| 394 | 394 | samsung,power-domain = <&pd_mfc>; |
| 395 | − clocks = <&clock CLK_MFC>; | |
| 396 | − clock-names = "mfc"; | |
| 395 | + clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; | |
| 396 | + clock-names = "mfc", "sclk_mfc"; | |
| 397 | 397 | status = "disabled"; |
| 398 | 398 | }; |
| 399 | 399 | |
| @@ -431,18 +431,34 @@ · 430 unmodified lines | ||
| 431 | 431 | |
| 432 | 432 | fimc_0: fimc@11800000 { |
| 433 | 433 | status = "okay"; |
| 434 | + assigned-clocks = <&clock CLK_MOUT_FIMC0>, | |
| 435 | + <&clock CLK_SCLK_FIMC0>; | |
| 436 | + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; | |
| 437 | + assigned-clock-rates = <0>, <160000000>; | |
| 434 | 438 | }; |
| 435 | 439 | |
| 436 | 440 | fimc_1: fimc@11810000 { |
| 437 | 441 | status = "okay"; |
| 442 | + assigned-clocks = <&clock CLK_MOUT_FIMC1>, | |
| 443 | + <&clock CLK_SCLK_FIMC1>; | |
| 444 | + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; | |
| 445 | + assigned-clock-rates = <0>, <160000000>; | |
| 438 | 446 | }; |
| 439 | 447 | |
| 440 | 448 | fimc_2: fimc@11820000 { |
| 441 | 449 | status = "okay"; |
| 450 | + assigned-clocks = <&clock CLK_MOUT_FIMC2>, | |
| 451 | + <&clock CLK_SCLK_FIMC2>; | |
| 452 | + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; | |
| 453 | + assigned-clock-rates = <0>, <160000000>; | |
| 442 | 454 | }; |
| 443 | 455 | |
| 444 | 456 | fimc_3: fimc@11830000 { |
| 445 | 457 | status = "okay"; |
| 458 | + assigned-clocks = <&clock CLK_MOUT_FIMC3>, | |
| 459 | + <&clock CLK_SCLK_FIMC3>; | |
| 460 | + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; | |
| 461 | + assigned-clock-rates = <0>, <160000000>; | |
| 446 | 462 | }; |
| 447 | 463 | }; |
| 448 | 464 | }; |
| @@ -473,18 +473,34 @@ · 472 unmodified lines | ||
| 473 | 473 | |
| 474 | 474 | fimc_0: fimc@11800000 { |
| 475 | 475 | status = "okay"; |
| 476 | + assigned-clocks = <&clock CLK_MOUT_FIMC0>, | |
| 477 | + <&clock CLK_SCLK_FIMC0>; | |
| 478 | + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; | |
| 479 | + assigned-clock-rates = <0>, <160000000>; | |
| 476 | 480 | }; |
| 477 | 481 | |
| 478 | 482 | fimc_1: fimc@11810000 { |
| 479 | 483 | status = "okay"; |
| 484 | + assigned-clocks = <&clock CLK_MOUT_FIMC1>, | |
| 485 | + <&clock CLK_SCLK_FIMC1>; | |
| 486 | + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; | |
| 487 | + assigned-clock-rates = <0>, <160000000>; | |
| 480 | 488 | }; |
| 481 | 489 | |
| 482 | 490 | fimc_2: fimc@11820000 { |
| 483 | 491 | status = "okay"; |
| 492 | + assigned-clocks = <&clock CLK_MOUT_FIMC2>, | |
| 493 | + <&clock CLK_SCLK_FIMC2>; | |
| 494 | + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; | |
| 495 | + assigned-clock-rates = <0>, <160000000>; | |
| 484 | 496 | }; |
| 485 | 497 | |
| 486 | 498 | fimc_3: fimc@11830000 { |
| 487 | 499 | status = "okay"; |
| 500 | + assigned-clocks = <&clock CLK_MOUT_FIMC3>, | |
| 501 | + <&clock CLK_SCLK_FIMC3>; | |
| 502 | + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; | |
| 503 | + assigned-clock-rates = <0>, <160000000>; | |
| 488 | 504 | }; |
| 489 | 505 | }; |
| 490 | 506 | }; |
| @@ -31,6 +31,23 @@ · 30 unmodified lines | ||
| 31 | 31 | pinctrl2 = &pinctrl_2; |
| 32 | 32 | }; |
| 33 | 33 | |
| 34 | + cpus { | |
| 35 | + #address-cells = <1>; | |
| 36 | + #size-cells = <0>; | |
| 37 | + | |
| 38 | + cpu@900 { | |
| 39 | + device_type = "cpu"; | |
| 40 | + compatible = "arm,cortex-a9"; | |
| 41 | + reg = <0x900>; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + cpu@901 { | |
| 45 | + device_type = "cpu"; | |
| 46 | + compatible = "arm,cortex-a9"; | |
| 47 | + reg = <0x901>; | |
| 48 | + }; | |
| 49 | + }; | |
| 50 | + | |
| 34 | 51 | pmu_system_controller: system-controller@10020000 { |
| 35 | 52 | clock-names = "clkout0", "clkout1", "clkout2", "clkout3", |
| 36 | 53 | "clkout4", "clkout8", "clkout9"; |
| @@ -22,6 +22,23 @@ · 21 unmodified lines | ||
| 22 | 22 | / { |
| 23 | 23 | compatible = "samsung,exynos4212", "samsung,exynos4"; |
| 24 | 24 | |
| 25 | + cpus { | |
| 26 | + #address-cells = <1>; | |
| 27 | + #size-cells = <0>; | |
| 28 | + | |
| 29 | + cpu@A00 { | |
| 30 | + device_type = "cpu"; | |
| 31 | + compatible = "arm,cortex-a9"; | |
| 32 | + reg = <0xA00>; | |
| 33 | + }; | |
| 34 | + | |
| 35 | + cpu@A01 { | |
| 36 | + device_type = "cpu"; | |
| 37 | + compatible = "arm,cortex-a9"; | |
| 38 | + reg = <0xA01>; | |
| 39 | + }; | |
| 40 | + }; | |
| 41 | + | |
| 25 | 42 | combiner: interrupt-controller@10440000 { |
| 26 | 43 | samsung,combiner-nr = <18>; |
| 27 | 44 | }; |
| @@ -45,6 +45,16 @@ · 44 unmodified lines | ||
| 45 | 45 | compatible = "samsung,odroidx2-audio"; |
| 46 | 46 | samsung,i2s-controller = <&i2s0>; |
| 47 | 47 | samsung,audio-codec = <&max98090>; |
| 48 | + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, | |
| 49 | + <&clock_audss EXYNOS_MOUT_I2S>, | |
| 50 | + <&clock_audss EXYNOS_DOUT_SRP>, | |
| 51 | + <&clock_audss EXYNOS_DOUT_AUD_BUS>; | |
| 52 | + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, | |
| 53 | + <&clock_audss EXYNOS_MOUT_AUDSS>; | |
| 54 | + assigned-clock-rates = <0>, | |
| 55 | + <0>, | |
| 56 | + <192000000>, | |
| 57 | + <19200000>; | |
| 48 | 58 | }; |
| 49 | 59 | |
| 50 | 60 | mmc@12550000 { |
| @@ -82,18 +92,34 @@ · 31 unmodified lines | ||
| 82 | 92 | |
| 83 | 93 | fimc_0: fimc@11800000 { |
| 84 | 94 | status = "okay"; |
| 95 | + assigned-clocks = <&clock CLK_MOUT_FIMC0>, | |
| 96 | + <&clock CLK_SCLK_FIMC0>; | |
| 97 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 98 | + assigned-clock-rates = <0>, <176000000>; | |
| 85 | 99 | }; |
| 86 | 100 | |
| 87 | 101 | fimc_1: fimc@11810000 { |
| 88 | 102 | status = "okay"; |
| 103 | + assigned-clocks = <&clock CLK_MOUT_FIMC1>, | |
| 104 | + <&clock CLK_SCLK_FIMC1>; | |
| 105 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 106 | + assigned-clock-rates = <0>, <176000000>; | |
| 89 | 107 | }; |
| 90 | 108 | |
| 91 | 109 | fimc_2: fimc@11820000 { |
| 92 | 110 | status = "okay"; |
| 111 | + assigned-clocks = <&clock CLK_MOUT_FIMC2>, | |
| 112 | + <&clock CLK_SCLK_FIMC2>; | |
| 113 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 114 | + assigned-clock-rates = <0>, <176000000>; | |
| 93 | 115 | }; |
| 94 | 116 | |
| 95 | 117 | fimc_3: fimc@11830000 { |
| 96 | 118 | status = "okay"; |
| 119 | + assigned-clocks = <&clock CLK_MOUT_FIMC3>, | |
| 120 | + <&clock CLK_SCLK_FIMC3>; | |
| 121 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 122 | + assigned-clock-rates = <0>, <176000000>; | |
| 97 | 123 | }; |
| 98 | 124 | }; |
| 99 | 125 | |
| @@ -14,6 +14,7 @@ · 13 unmodified lines | ||
| 14 | 14 | |
| 15 | 15 | /dts-v1/; |
| 16 | 16 | #include "exynos4412.dtsi" |
| 17 | +#include <dt-bindings/gpio/gpio.h> | |
| 17 | 18 | |
| 18 | 19 | / { |
| 19 | 20 | model = "Samsung Trats 2 based on Exynos4412"; |
| @@ -22,6 +23,7 @@ · 2 unmodified lines | ||
| 22 | 23 | aliases { |
| 23 | 24 | i2c9 = &i2c_ak8975; |
| 24 | 25 | i2c10 = &i2c_cm36651; |
| 26 | + i2c11 = &i2c_max77693; | |
| 25 | 27 | }; |
| 26 | 28 | |
| 27 | 29 | memory { |
| @@ -399,8 +401,6 @@ · 371 unmodified lines | ||
| 399 | 401 | regulator-name = "VMEM_VDD_2.8V"; |
| 400 | 402 | regulator-min-microvolt = <2800000>; |
| 401 | 403 | regulator-max-microvolt = <2800000>; |
| 402 | − regulator-always-on; | |
| 403 | − regulator-mem-off; | |
| 404 | 404 | }; |
| 405 | 405 | |
| 406 | 406 | ldo23_reg: ldo23 { |
| @@ -503,8 +503,6 @@ · 96 unmodified lines | ||
| 503 | 503 | regulator-name = "VMEM_VDDF_3.0V"; |
| 504 | 504 | regulator-min-microvolt = <2850000>; |
| 505 | 505 | regulator-max-microvolt = <2850000>; |
| 506 | − regulator-always-on; | |
| 507 | − regulator-mem-off; | |
| 508 | 506 | }; |
| 509 | 507 | |
| 510 | 508 | buck9_reg: buck9 { |
| @@ -518,6 +516,42 @@ · 7 unmodified lines | ||
| 518 | 516 | }; |
| 519 | 517 | }; |
| 520 | 518 | |
| 519 | + i2c_max77693: i2c-gpio-1 { | |
| 520 | + compatible = "i2c-gpio"; | |
| 521 | + gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; | |
| 522 | + i2c-gpio,delay-us = <2>; | |
| 523 | + #address-cells = <1>; | |
| 524 | + #size-cells = <0>; | |
| 525 | + status = "okay"; | |
| 526 | + | |
| 527 | + max77693@66 { | |
| 528 | + compatible = "maxim,max77693"; | |
| 529 | + interrupt-parent = <&gpx1>; | |
| 530 | + interrupts = <5 2>; | |
| 531 | + reg = <0x66>; | |
| 532 | + | |
| 533 | + regulators { | |
| 534 | + esafeout1_reg: ESAFEOUT1@1 { | |
| 535 | + regulator-name = "ESAFEOUT1"; | |
| 536 | + }; | |
| 537 | + esafeout2_reg: ESAFEOUT2@2 { | |
| 538 | + regulator-name = "ESAFEOUT2"; | |
| 539 | + }; | |
| 540 | + charger_reg: CHARGER@0 { | |
| 541 | + regulator-name = "CHARGER"; | |
| 542 | + regulator-min-microamp = <60000>; | |
| 543 | + regulator-max-microamp = <2580000>; | |
| 544 | + }; | |
| 545 | + }; | |
| 546 | + | |
| 547 | + max77693_haptic { | |
| 548 | + compatible = "maxim,max77693-haptic"; | |
| 549 | + haptic-supply = <&ldo26_reg>; | |
| 550 | + pwms = <&pwm 0 38022 0>; | |
| 551 | + }; | |
| 552 | + }; | |
| 553 | + }; | |
| 554 | + | |
| 521 | 555 | mmc@12550000 { |
| 522 | 556 | num-slots = <1>; |
| 523 | 557 | broken-cd; |
| @@ -535,6 +569,16 @@ · 11 unmodified lines | ||
| 535 | 569 | cap-mmc-highspeed; |
| 536 | 570 | }; |
| 537 | 571 | |
| 572 | + sdhci@12530000 { | |
| 573 | + bus-width = <4>; | |
| 574 | + cd-gpios = <&gpx3 4 0>; | |
| 575 | + cd-inverted; | |
| 576 | + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; | |
| 577 | + pinctrl-names = "default"; | |
| 578 | + vmmc-supply = <&ldo21_reg>; | |
| 579 | + status = "okay"; | |
| 580 | + }; | |
| 581 | + | |
| 538 | 582 | serial@13800000 { |
| 539 | 583 | status = "okay"; |
| 540 | 584 | }; |
| @@ -551,6 +595,11 @@ · 10 unmodified lines | ||
| 551 | 595 | status = "okay"; |
| 552 | 596 | }; |
| 553 | 597 | |
| 598 | + tmu@100C0000 { | |
| 599 | + vtmu-supply = <&ldo10_reg>; | |
| 600 | + status = "okay"; | |
| 601 | + }; | |
| 602 | + | |
| 554 | 603 | i2c_ak8975: i2c-gpio-0 { |
| 555 | 604 | compatible = "i2c-gpio"; |
| 556 | 605 | gpios = <&gpy2 4 0>, <&gpy2 5 0>; |
| @@ -598,6 +647,13 @@ · 41 unmodified lines | ||
| 598 | 647 | }; |
| 599 | 648 | }; |
| 600 | 649 | |
| 650 | + pwm: pwm@139D0000 { | |
| 651 | + pinctrl-0 = <&pwm0_out>; | |
| 652 | + pinctrl-names = "default"; | |
| 653 | + samsung,pwm-outputs = <0>; | |
| 654 | + status = "okay"; | |
| 655 | + }; | |
| 656 | + | |
| 601 | 657 | dsi_0: dsi@11C80000 { |
| 602 | 658 | vddcore-supply = <&ldo8_reg>; |
| 603 | 659 | vddio-supply = <&ldo10_reg>; |
| @@ -663,28 +719,51 @@ · 59 unmodified lines | ||
| 663 | 719 | pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; |
| 664 | 720 | pinctrl-names = "default"; |
| 665 | 721 | status = "okay"; |
| 722 | + assigned-clocks = <&clock CLK_MOUT_CAM0>, | |
| 723 | + <&clock CLK_MOUT_CAM1>; | |
| 724 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>, | |
| 725 | + <&clock CLK_MOUT_MPLL_USER_T>; | |
| 666 | 726 | |
| 667 | 727 | fimc_0: fimc@11800000 { |
| 668 | 728 | status = "okay"; |
| 729 | + assigned-clocks = <&clock CLK_MOUT_FIMC0>, | |
| 730 | + <&clock CLK_SCLK_FIMC0>; | |
| 731 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 732 | + assigned-clock-rates = <0>, <176000000>; | |
| 669 | 733 | }; |
| 670 | 734 | |
| 671 | 735 | fimc_1: fimc@11810000 { |
| 672 | 736 | status = "okay"; |
| 737 | + assigned-clocks = <&clock CLK_MOUT_FIMC1>, | |
| 738 | + <&clock CLK_SCLK_FIMC1>; | |
| 739 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 740 | + assigned-clock-rates = <0>, <176000000>; | |
| 673 | 741 | }; |
| 674 | 742 | |
| 675 | 743 | fimc_2: fimc@11820000 { |
| 676 | 744 | status = "okay"; |
| 745 | + assigned-clocks = <&clock CLK_MOUT_FIMC2>, | |
| 746 | + <&clock CLK_SCLK_FIMC2>; | |
| 747 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 748 | + assigned-clock-rates = <0>, <176000000>; | |
| 677 | 749 | }; |
| 678 | 750 | |
| 679 | 751 | fimc_3: fimc@11830000 { |
| 680 | 752 | status = "okay"; |
| 753 | + assigned-clocks = <&clock CLK_MOUT_FIMC3>, | |
| 754 | + <&clock CLK_SCLK_FIMC3>; | |
| 755 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 756 | + assigned-clock-rates = <0>, <176000000>; | |
| 681 | 757 | }; |
| 682 | 758 | |
| 683 | 759 | csis_0: csis@11880000 { |
| 684 | 760 | status = "okay"; |
| 685 | 761 | vddcore-supply = <&ldo8_reg>; |
| 686 | 762 | vddio-supply = <&ldo10_reg>; |
| 687 | − clock-frequency = <176000000>; | |
| 763 | + assigned-clocks = <&clock CLK_MOUT_CSIS0>, | |
| 764 | + <&clock CLK_SCLK_CSIS0>; | |
| 765 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 766 | + assigned-clock-rates = <0>, <176000000>; | |
| 688 | 767 | |
| 689 | 768 | /* Camera C (3) MIPI CSI-2 (CSIS0) */ |
| 690 | 769 | port@3 { |
| @@ -698,10 +777,13 @@ · 7 unmodified lines | ||
| 698 | 777 | }; |
| 699 | 778 | |
| 700 | 779 | csis_1: csis@11890000 { |
| 780 | + status = "okay"; | |
| 701 | 781 | vddcore-supply = <&ldo8_reg>; |
| 702 | 782 | vddio-supply = <&ldo10_reg>; |
| 703 | − clock-frequency = <160000000>; | |
| 704 | − status = "okay"; | |
| 783 | + assigned-clocks = <&clock CLK_MOUT_CSIS1>, | |
| 784 | + <&clock CLK_SCLK_CSIS1>; | |
| 785 | + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; | |
| 786 | + assigned-clock-rates = <0>, <176000000>; | |
| 705 | 787 | |
| 706 | 788 | /* Camera D (4) MIPI CSI-2 (CSIS1) */ |
| 707 | 789 | port@4 { |
| @@ -782,3 +864,319 @@ · 74 unmodified lines | ||
| 782 | 864 | io-channels = <&adc 2>; /* Battery temperature */ |
| 783 | 865 | }; |
| 784 | 866 | }; |
| 867 | + | |
| 868 | +&pinctrl_0 { | |
| 869 | + pinctrl-names = "default"; | |
| 870 | + pinctrl-0 = <&sleep0>; | |
| 871 | + | |
| 872 | + sleep0: sleep-states { | |
| 873 | + PIN_SLP(gpa0-0, INPUT, NONE); | |
| 874 | + PIN_SLP(gpa0-1, OUT0, NONE); | |
| 875 | + PIN_SLP(gpa0-2, INPUT, NONE); | |
| 876 | + PIN_SLP(gpa0-3, INPUT, UP); | |
| 877 | + PIN_SLP(gpa0-4, INPUT, NONE); | |
| 878 | + PIN_SLP(gpa0-5, INPUT, DOWN); | |
| 879 | + PIN_SLP(gpa0-6, INPUT, DOWN); | |
| 880 | + PIN_SLP(gpa0-7, INPUT, UP); | |
| 881 | + | |
| 882 | + PIN_SLP(gpa1-0, INPUT, DOWN); | |
| 883 | + PIN_SLP(gpa1-1, INPUT, DOWN); | |
| 884 | + PIN_SLP(gpa1-2, INPUT, DOWN); | |
| 885 | + PIN_SLP(gpa1-3, INPUT, DOWN); | |
| 886 | + PIN_SLP(gpa1-4, INPUT, DOWN); | |
| 887 | + PIN_SLP(gpa1-5, INPUT, DOWN); | |
| 888 | + | |
| 889 | + PIN_SLP(gpb-0, INPUT, NONE); | |
| 890 | + PIN_SLP(gpb-1, INPUT, NONE); | |
| 891 | + PIN_SLP(gpb-2, INPUT, NONE); | |
| 892 | + PIN_SLP(gpb-3, INPUT, NONE); | |
| 893 | + PIN_SLP(gpb-4, INPUT, DOWN); | |
| 894 | + PIN_SLP(gpb-5, INPUT, UP); | |
| 895 | + PIN_SLP(gpb-6, INPUT, DOWN); | |
| 896 | + PIN_SLP(gpb-7, INPUT, DOWN); | |
| 897 | + | |
| 898 | + PIN_SLP(gpc0-0, INPUT, DOWN); | |
| 899 | + PIN_SLP(gpc0-1, INPUT, DOWN); | |
| 900 | + PIN_SLP(gpc0-2, INPUT, DOWN); | |
| 901 | + PIN_SLP(gpc0-3, INPUT, DOWN); | |
| 902 | + PIN_SLP(gpc0-4, INPUT, DOWN); | |
| 903 | + | |
| 904 | + PIN_SLP(gpc1-0, INPUT, NONE); | |
| 905 | + PIN_SLP(gpc1-1, PREV, NONE); | |
| 906 | + PIN_SLP(gpc1-2, INPUT, NONE); | |
| 907 | + PIN_SLP(gpc1-3, INPUT, NONE); | |
| 908 | + PIN_SLP(gpc1-4, INPUT, NONE); | |
| 909 | + | |
| 910 | + PIN_SLP(gpd0-0, INPUT, DOWN); | |
| 911 | + PIN_SLP(gpd0-1, INPUT, DOWN); | |
| 912 | + PIN_SLP(gpd0-2, INPUT, NONE); | |
| 913 | + PIN_SLP(gpd0-3, INPUT, NONE); | |
| 914 | + | |
| 915 | + PIN_SLP(gpd1-0, INPUT, DOWN); | |
| 916 | + PIN_SLP(gpd1-1, INPUT, DOWN); | |
| 917 | + PIN_SLP(gpd1-2, INPUT, NONE); | |
| 918 | + PIN_SLP(gpd1-3, INPUT, NONE); | |
| 919 | + | |
| 920 | + PIN_SLP(gpf0-0, INPUT, NONE); | |
| 921 | + PIN_SLP(gpf0-1, INPUT, NONE); | |
| 922 | + PIN_SLP(gpf0-2, INPUT, DOWN); | |
| 923 | + PIN_SLP(gpf0-3, INPUT, DOWN); | |
| 924 | + PIN_SLP(gpf0-4, INPUT, NONE); | |
| 925 | + PIN_SLP(gpf0-5, INPUT, DOWN); | |
| 926 | + PIN_SLP(gpf0-6, INPUT, NONE); | |
| 927 | + PIN_SLP(gpf0-7, INPUT, DOWN); | |
| 928 | + | |
| 929 | + PIN_SLP(gpf1-0, INPUT, DOWN); | |
| 930 | + PIN_SLP(gpf1-1, INPUT, DOWN); | |
| 931 | + PIN_SLP(gpf1-2, INPUT, DOWN); | |
| 932 | + PIN_SLP(gpf1-3, INPUT, DOWN); | |
| 933 | + PIN_SLP(gpf1-4, INPUT, NONE); | |
| 934 | + PIN_SLP(gpf1-5, INPUT, NONE); | |
| 935 | + PIN_SLP(gpf1-6, INPUT, DOWN); | |
| 936 | + PIN_SLP(gpf1-7, PREV, NONE); | |
| 937 | + | |
| 938 | + PIN_SLP(gpf2-0, PREV, NONE); | |
| 939 | + PIN_SLP(gpf2-1, INPUT, DOWN); | |
| 940 | + PIN_SLP(gpf2-2, INPUT, DOWN); | |
| 941 | + PIN_SLP(gpf2-3, INPUT, DOWN); | |
| 942 | + PIN_SLP(gpf2-4, INPUT, DOWN); | |
| 943 | + PIN_SLP(gpf2-5, INPUT, DOWN); | |
| 944 | + PIN_SLP(gpf2-6, INPUT, NONE); | |
| 945 | + PIN_SLP(gpf2-7, INPUT, NONE); | |
| 946 | + | |
| 947 | + PIN_SLP(gpf3-0, INPUT, NONE); | |
| 948 | + PIN_SLP(gpf3-1, PREV, NONE); | |
| 949 | + PIN_SLP(gpf3-2, PREV, NONE); | |
| 950 | + PIN_SLP(gpf3-3, PREV, NONE); | |
| 951 | + PIN_SLP(gpf3-4, OUT1, NONE); | |
| 952 | + PIN_SLP(gpf3-5, INPUT, DOWN); | |
| 953 | + | |
| 954 | + PIN_SLP(gpj0-0, PREV, NONE); | |
| 955 | + PIN_SLP(gpj0-1, PREV, NONE); | |
| 956 | + PIN_SLP(gpj0-2, PREV, NONE); | |
| 957 | + PIN_SLP(gpj0-3, INPUT, DOWN); | |
| 958 | + PIN_SLP(gpj0-4, PREV, NONE); | |
| 959 | + PIN_SLP(gpj0-5, PREV, NONE); | |
| 960 | + PIN_SLP(gpj0-6, INPUT, DOWN); | |
| 961 | + PIN_SLP(gpj0-7, INPUT, DOWN); | |
| 962 | + | |
| 963 | + PIN_SLP(gpj1-0, INPUT, DOWN); | |
| 964 | + PIN_SLP(gpj1-1, PREV, NONE); | |
| 965 | + PIN_SLP(gpj1-2, PREV, NONE); | |
| 966 | + PIN_SLP(gpj1-3, INPUT, DOWN); | |
| 967 | + PIN_SLP(gpj1-4, INPUT, DOWN); | |
| 968 | + }; | |
| 969 | +}; | |
| 970 | + | |
| 971 | +&pinctrl_1 { | |
| 972 | + pinctrl-names = "default"; | |
| 973 | + pinctrl-0 = <&sleep1>; | |
| 974 | + | |
| 975 | + sleep1: sleep-states { | |
| 976 | + PIN_SLP(gpk0-0, PREV, NONE); | |
| 977 | + PIN_SLP(gpk0-1, PREV, NONE); | |
| 978 | + PIN_SLP(gpk0-2, OUT0, NONE); | |
| 979 | + PIN_SLP(gpk0-3, PREV, NONE); | |
| 980 | + PIN_SLP(gpk0-4, PREV, NONE); | |
| 981 | + PIN_SLP(gpk0-5, PREV, NONE); | |
| 982 | + PIN_SLP(gpk0-6, PREV, NONE); | |
| 983 | + | |
| 984 | + PIN_SLP(gpk1-0, INPUT, DOWN); | |
| 985 | + PIN_SLP(gpk1-1, INPUT, DOWN); | |
| 986 | + PIN_SLP(gpk1-2, INPUT, DOWN); | |
| 987 | + PIN_SLP(gpk1-3, PREV, NONE); | |
| 988 | + PIN_SLP(gpk1-4, PREV, NONE); | |
| 989 | + PIN_SLP(gpk1-5, PREV, NONE); | |
| 990 | + PIN_SLP(gpk1-6, PREV, NONE); | |
| 991 | + | |
| 992 | + PIN_SLP(gpk2-0, INPUT, DOWN); | |
| 993 | + PIN_SLP(gpk2-1, INPUT, DOWN); | |
| 994 | + PIN_SLP(gpk2-2, INPUT, DOWN); | |
| 995 | + PIN_SLP(gpk2-3, INPUT, DOWN); | |
| 996 | + PIN_SLP(gpk2-4, INPUT, DOWN); | |
| 997 | + PIN_SLP(gpk2-5, INPUT, DOWN); | |
| 998 | + PIN_SLP(gpk2-6, INPUT, DOWN); | |
| 999 | + | |
| 1000 | + PIN_SLP(gpk3-0, OUT0, NONE); | |
| 1001 | + PIN_SLP(gpk3-1, INPUT, NONE); | |
| 1002 | + PIN_SLP(gpk3-2, INPUT, DOWN); | |
| 1003 | + PIN_SLP(gpk3-3, INPUT, NONE); | |
| 1004 | + PIN_SLP(gpk3-4, INPUT, NONE); | |
| 1005 | + PIN_SLP(gpk3-5, INPUT, NONE); | |
| 1006 | + PIN_SLP(gpk3-6, INPUT, NONE); | |
| 1007 | + | |
| 1008 | + PIN_SLP(gpl0-0, INPUT, DOWN); | |
| 1009 | + PIN_SLP(gpl0-1, INPUT, DOWN); | |
| 1010 | + PIN_SLP(gpl0-2, INPUT, DOWN); | |
| 1011 | + PIN_SLP(gpl0-3, INPUT, DOWN); | |
| 1012 | + PIN_SLP(gpl0-4, PREV, NONE); | |
| 1013 | + PIN_SLP(gpl0-6, PREV, NONE); | |
| 1014 | + | |
| 1015 | + PIN_SLP(gpl1-0, INPUT, DOWN); | |
| 1016 | + PIN_SLP(gpl1-1, INPUT, DOWN); | |
| 1017 | + PIN_SLP(gpl2-0, INPUT, DOWN); | |
| 1018 | + PIN_SLP(gpl2-1, INPUT, DOWN); | |
| 1019 | + PIN_SLP(gpl2-2, INPUT, DOWN); | |
| 1020 | + PIN_SLP(gpl2-3, INPUT, DOWN); | |
| 1021 | + PIN_SLP(gpl2-4, INPUT, DOWN); | |
| 1022 | + PIN_SLP(gpl2-5, INPUT, DOWN); | |
| 1023 | + PIN_SLP(gpl2-6, PREV, NONE); | |
| 1024 | + PIN_SLP(gpl2-7, INPUT, DOWN); | |
| 1025 | + | |
| 1026 | + PIN_SLP(gpm0-0, INPUT, DOWN); | |
| 1027 | + PIN_SLP(gpm0-1, INPUT, DOWN); | |
| 1028 | + PIN_SLP(gpm0-2, INPUT, DOWN); | |
| 1029 | + PIN_SLP(gpm0-3, INPUT, DOWN); | |
| 1030 | + PIN_SLP(gpm0-4, INPUT, DOWN); | |
| 1031 | + PIN_SLP(gpm0-5, INPUT, DOWN); | |
| 1032 | + PIN_SLP(gpm0-6, INPUT, DOWN); | |
| 1033 | + PIN_SLP(gpm0-7, INPUT, DOWN); | |
| 1034 | + | |
| 1035 | + PIN_SLP(gpm1-0, INPUT, DOWN); | |
| 1036 | + PIN_SLP(gpm1-1, INPUT, DOWN); | |
| 1037 | + PIN_SLP(gpm1-2, INPUT, NONE); | |
| 1038 | + PIN_SLP(gpm1-3, INPUT, NONE); | |
| 1039 | + PIN_SLP(gpm1-4, INPUT, NONE); | |
| 1040 | + PIN_SLP(gpm1-5, INPUT, NONE); | |
| 1041 | + PIN_SLP(gpm1-6, INPUT, DOWN); | |
| 1042 | + | |
| 1043 | + PIN_SLP(gpm2-0, INPUT, NONE); | |
| 1044 | + PIN_SLP(gpm2-1, INPUT, NONE); | |
| 1045 | + PIN_SLP(gpm2-2, INPUT, DOWN); | |
| 1046 | + PIN_SLP(gpm2-3, INPUT, DOWN); | |
| 1047 | + PIN_SLP(gpm2-4, INPUT, DOWN); | |
| 1048 | + | |
| 1049 | + PIN_SLP(gpm3-0, PREV, NONE); | |
| 1050 | + PIN_SLP(gpm3-1, PREV, NONE); | |
| 1051 | + PIN_SLP(gpm3-2, PREV, NONE); | |
| 1052 | + PIN_SLP(gpm3-3, OUT1, NONE); | |
| 1053 | + PIN_SLP(gpm3-4, INPUT, DOWN); | |
| 1054 | + PIN_SLP(gpm3-5, INPUT, DOWN); | |
| 1055 | + PIN_SLP(gpm3-6, INPUT, DOWN); | |
| 1056 | + PIN_SLP(gpm3-7, INPUT, DOWN); | |
| 1057 | + | |
| 1058 | + PIN_SLP(gpm4-0, INPUT, DOWN); | |
| 1059 | + PIN_SLP(gpm4-1, INPUT, DOWN); | |
| 1060 | + PIN_SLP(gpm4-2, INPUT, DOWN); | |
| 1061 | + PIN_SLP(gpm4-3, INPUT, DOWN); | |
| 1062 | + PIN_SLP(gpm4-4, INPUT, DOWN); | |
| 1063 | + PIN_SLP(gpm4-5, INPUT, DOWN); | |
| 1064 | + PIN_SLP(gpm4-6, INPUT, DOWN); | |
| 1065 | + PIN_SLP(gpm4-7, INPUT, DOWN); | |
| 1066 | + | |
| 1067 | + PIN_SLP(gpy0-0, INPUT, DOWN); | |
| 1068 | + PIN_SLP(gpy0-1, INPUT, DOWN); | |
| 1069 | + PIN_SLP(gpy0-2, INPUT, DOWN); | |
| 1070 | + PIN_SLP(gpy0-3, INPUT, DOWN); | |
| 1071 | + PIN_SLP(gpy0-4, INPUT, DOWN); | |
| 1072 | + PIN_SLP(gpy0-5, INPUT, DOWN); | |
| 1073 | + | |
| 1074 | + PIN_SLP(gpy1-0, INPUT, DOWN); | |
| 1075 | + PIN_SLP(gpy1-1, INPUT, DOWN); | |
| 1076 | + PIN_SLP(gpy1-2, INPUT, DOWN); | |
| 1077 | + PIN_SLP(gpy1-3, INPUT, DOWN); | |
| 1078 | + | |
| 1079 | + PIN_SLP(gpy2-0, PREV, NONE); | |
| 1080 | + PIN_SLP(gpy2-1, INPUT, DOWN); | |
| 1081 | + PIN_SLP(gpy2-2, INPUT, NONE); | |
| 1082 | + PIN_SLP(gpy2-3, INPUT, NONE); | |
| 1083 | + PIN_SLP(gpy2-4, INPUT, NONE); | |
| 1084 | + PIN_SLP(gpy2-5, INPUT, NONE); | |
| 1085 | + | |
| 1086 | + PIN_SLP(gpy3-0, INPUT, DOWN); | |
| 1087 | + PIN_SLP(gpy3-1, INPUT, DOWN); | |
| 1088 | + PIN_SLP(gpy3-2, INPUT, DOWN); | |
| 1089 | + PIN_SLP(gpy3-3, INPUT, DOWN); | |
| 1090 | + PIN_SLP(gpy3-4, INPUT, DOWN); | |
| 1091 | + PIN_SLP(gpy3-5, INPUT, DOWN); | |
| 1092 | + PIN_SLP(gpy3-6, INPUT, DOWN); | |
| 1093 | + PIN_SLP(gpy3-7, INPUT, DOWN); | |
| 1094 | + | |
| 1095 | + PIN_SLP(gpy4-0, INPUT, DOWN); | |
| 1096 | + PIN_SLP(gpy4-1, INPUT, DOWN); | |
| 1097 | + PIN_SLP(gpy4-2, INPUT, DOWN); | |
| 1098 | + PIN_SLP(gpy4-3, INPUT, DOWN); | |
| 1099 | + PIN_SLP(gpy4-4, INPUT, DOWN); | |
| 1100 | + PIN_SLP(gpy4-5, INPUT, DOWN); | |
| 1101 | + PIN_SLP(gpy4-6, INPUT, DOWN); | |
| 1102 | + PIN_SLP(gpy4-7, INPUT, DOWN); | |
| 1103 | + | |
| 1104 | + PIN_SLP(gpy5-0, INPUT, DOWN); | |
| 1105 | + PIN_SLP(gpy5-1, INPUT, DOWN); | |
| 1106 | + PIN_SLP(gpy5-2, INPUT, DOWN); | |
| 1107 | + PIN_SLP(gpy5-3, INPUT, DOWN); | |
| 1108 | + PIN_SLP(gpy5-4, INPUT, DOWN); | |
| 1109 | + PIN_SLP(gpy5-5, INPUT, DOWN); | |
| 1110 | + PIN_SLP(gpy5-6, INPUT, DOWN); | |
| 1111 | + PIN_SLP(gpy5-7, INPUT, DOWN); | |
| 1112 | + | |
| 1113 | + PIN_SLP(gpy6-0, INPUT, DOWN); | |
| 1114 | + PIN_SLP(gpy6-1, INPUT, DOWN); | |
| 1115 | + PIN_SLP(gpy6-2, INPUT, DOWN); | |
| 1116 | + PIN_SLP(gpy6-3, INPUT, DOWN); | |
| 1117 | + PIN_SLP(gpy6-4, INPUT, DOWN); | |
| 1118 | + PIN_SLP(gpy6-5, INPUT, DOWN); | |
| 1119 | + PIN_SLP(gpy6-6, INPUT, DOWN); | |
| 1120 | + PIN_SLP(gpy6-7, INPUT, DOWN); | |
| 1121 | + }; | |
| 1122 | +}; | |
| 1123 | + | |
| 1124 | +&pinctrl_2 { | |
| 1125 | + pinctrl-names = "default"; | |
| 1126 | + pinctrl-0 = <&sleep2>; | |
| 1127 | + | |
| 1128 | + sleep2: sleep-states { | |
| 1129 | + PIN_SLP(gpz-0, INPUT, DOWN); | |
| 1130 | + PIN_SLP(gpz-1, INPUT, DOWN); | |
| 1131 | + PIN_SLP(gpz-2, INPUT, DOWN); | |
| 1132 | + PIN_SLP(gpz-3, INPUT, DOWN); | |
| 1133 | + PIN_SLP(gpz-4, INPUT, DOWN); | |
| 1134 | + PIN_SLP(gpz-5, INPUT, DOWN); | |
| 1135 | + PIN_SLP(gpz-6, INPUT, DOWN); | |
| 1136 | + }; | |
| 1137 | +}; | |
| 1138 | + | |
| 1139 | +&pinctrl_3 { | |
| 1140 | + pinctrl-names = "default"; | |
| 1141 | + pinctrl-0 = <&sleep3>; | |
| 1142 | + | |
| 1143 | + sleep3: sleep-states { | |
| 1144 | + PIN_SLP(gpv0-0, INPUT, DOWN); | |
| 1145 | + PIN_SLP(gpv0-1, INPUT, DOWN); | |
| 1146 | + PIN_SLP(gpv0-2, INPUT, DOWN); | |
| 1147 | + PIN_SLP(gpv0-3, INPUT, DOWN); | |
| 1148 | + PIN_SLP(gpv0-4, INPUT, DOWN); | |
| 1149 | + PIN_SLP(gpv0-5, INPUT, DOWN); | |
| 1150 | + PIN_SLP(gpv0-6, INPUT, DOWN); | |
| 1151 | + PIN_SLP(gpv0-7, INPUT, DOWN); | |
| 1152 | + | |
| 1153 | + PIN_SLP(gpv1-0, INPUT, DOWN); | |
| 1154 | + PIN_SLP(gpv1-1, INPUT, DOWN); | |
| 1155 | + PIN_SLP(gpv1-2, INPUT, DOWN); | |
| 1156 | + PIN_SLP(gpv1-3, INPUT, DOWN); | |
| 1157 | + PIN_SLP(gpv1-4, INPUT, DOWN); | |
| 1158 | + PIN_SLP(gpv1-5, INPUT, DOWN); | |
| 1159 | + PIN_SLP(gpv1-6, INPUT, DOWN); | |
| 1160 | + PIN_SLP(gpv1-7, INPUT, DOWN); | |
| 1161 | + | |
| 1162 | + PIN_SLP(gpv2-0, INPUT, DOWN); | |
| 1163 | + PIN_SLP(gpv2-1, INPUT, DOWN); | |
| 1164 | + PIN_SLP(gpv2-2, INPUT, DOWN); | |
| 1165 | + PIN_SLP(gpv2-3, INPUT, DOWN); | |
| 1166 | + PIN_SLP(gpv2-4, INPUT, DOWN); | |
| 1167 | + PIN_SLP(gpv2-5, INPUT, DOWN); | |
| 1168 | + PIN_SLP(gpv2-6, INPUT, DOWN); | |
| 1169 | + PIN_SLP(gpv2-7, INPUT, DOWN); | |
| 1170 | + | |
| 1171 | + PIN_SLP(gpv3-0, INPUT, DOWN); | |
| 1172 | + PIN_SLP(gpv3-1, INPUT, DOWN); | |
| 1173 | + PIN_SLP(gpv3-2, INPUT, DOWN); | |
| 1174 | + PIN_SLP(gpv3-3, INPUT, DOWN); | |
| 1175 | + PIN_SLP(gpv3-4, INPUT, DOWN); | |
| 1176 | + PIN_SLP(gpv3-5, INPUT, DOWN); | |
| 1177 | + PIN_SLP(gpv3-6, INPUT, DOWN); | |
| 1178 | + PIN_SLP(gpv3-7, INPUT, DOWN); | |
| 1179 | + | |
| 1180 | + PIN_SLP(gpv4-0, INPUT, DOWN); | |
| 1181 | + }; | |
| 1182 | +}; | |
| @@ -22,6 +22,35 @@ · 21 unmodified lines | ||
| 22 | 22 | / { |
| 23 | 23 | compatible = "samsung,exynos4412", "samsung,exynos4"; |
| 24 | 24 | |
| 25 | + cpus { | |
| 26 | + #address-cells = <1>; | |
| 27 | + #size-cells = <0>; | |
| 28 | + | |
| 29 | + cpu@A00 { | |
| 30 | + device_type = "cpu"; | |
| 31 | + compatible = "arm,cortex-a9"; | |
| 32 | + reg = <0xA00>; | |
| 33 | + }; | |
| 34 | + | |
| 35 | + cpu@A01 { | |
| 36 | + device_type = "cpu"; | |
| 37 | + compatible = "arm,cortex-a9"; | |
| 38 | + reg = <0xA01>; | |
| 39 | + }; | |
| 40 | + | |
| 41 | + cpu@A02 { | |
| 42 | + device_type = "cpu"; | |
| 43 | + compatible = "arm,cortex-a9"; | |
| 44 | + reg = <0xA02>; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + cpu@A03 { | |
| 48 | + device_type = "cpu"; | |
| 49 | + compatible = "arm,cortex-a9"; | |
| 50 | + reg = <0xA03>; | |
| 51 | + }; | |
| 52 | + }; | |
| 53 | + | |
| 25 | 54 | combiner: interrupt-controller@10440000 { |
| 26 | 55 | samsung,combiner-nr = <20>; |
| 27 | 56 | }; |
| @@ -0,0 +1,573 @@ | ||
| 1 | +/* | |
| 2 | + * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source | |
| 3 | + * | |
| 4 | + * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
| 5 | + * | |
| 6 | + * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device | |
| 7 | + * tree nodes are listed in this file. | |
| 8 | + * | |
| 9 | + * This program is free software; you can redistribute it and/or modify | |
| 10 | + * it under the terms of the GNU General Public License version 2 as | |
| 11 | + * published by the Free Software Foundation. | |
| 12 | +*/ | |
| 13 | + | |
| 14 | +&pinctrl_0 { | |
| 15 | + gpa0: gpa0 { | |
| 16 | + gpio-controller; | |
| 17 | + #gpio-cells = <2>; | |
| 18 | + | |
| 19 | + interrupt-controller; | |
| 20 | + #interrupt-cells = <2>; | |
| 21 | + }; | |
| 22 | + | |
| 23 | + gpa1: gpa1 { | |
| 24 | + gpio-controller; | |
| 25 | + #gpio-cells = <2>; | |
| 26 | + | |
| 27 | + interrupt-controller; | |
| 28 | + #interrupt-cells = <2>; | |
| 29 | + }; | |
| 30 | + | |
| 31 | + gpb: gpb { | |
| 32 | + gpio-controller; | |
| 33 | + #gpio-cells = <2>; | |
| 34 | + | |
| 35 | + interrupt-controller; | |
| 36 | + #interrupt-cells = <2>; | |
| 37 | + }; | |
| 38 | + | |
| 39 | + gpc0: gpc0 { | |
| 40 | + gpio-controller; | |
| 41 | + #gpio-cells = <2>; | |
| 42 | + | |
| 43 | + interrupt-controller; | |
| 44 | + #interrupt-cells = <2>; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + gpc1: gpc1 { | |
| 48 | + gpio-controller; | |
| 49 | + #gpio-cells = <2>; | |
| 50 | + | |
| 51 | + interrupt-controller; | |
| 52 | + #interrupt-cells = <2>; | |
| 53 | + }; | |
| 54 | + | |
| 55 | + gpd0: gpd0 { | |
| 56 | + gpio-controller; | |
| 57 | + #gpio-cells = <2>; | |
| 58 | + | |
| 59 | + interrupt-controller; | |
| 60 | + #interrupt-cells = <2>; | |
| 61 | + }; | |
| 62 | + | |
| 63 | + gpd1: gpd1 { | |
| 64 | + gpio-controller; | |
| 65 | + #gpio-cells = <2>; | |
| 66 | + | |
| 67 | + interrupt-controller; | |
| 68 | + #interrupt-cells = <2>; | |
| 69 | + }; | |
| 70 | + | |
| 71 | + gpf0: gpf0 { | |
| 72 | + gpio-controller; | |
| 73 | + #gpio-cells = <2>; | |
| 74 | + | |
| 75 | + interrupt-controller; | |
| 76 | + #interrupt-cells = <2>; | |
| 77 | + }; | |
| 78 | + | |
| 79 | + gpf1: gpf1 { | |
| 80 | + gpio-controller; | |
| 81 | + #gpio-cells = <2>; | |
| 82 | + | |
| 83 | + interrupt-controller; | |
| 84 | + #interrupt-cells = <2>; | |
| 85 | + }; | |
| 86 | + | |
| 87 | + gpf2: gpf2 { | |
| 88 | + gpio-controller; | |
| 89 | + #gpio-cells = <2>; | |
| 90 | + | |
| 91 | + interrupt-controller; | |
| 92 | + #interrupt-cells = <2>; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + uart0_data: uart0-data { | |
| 96 | + samsung,pins = "gpa0-0", "gpa0-1"; | |
| 97 | + samsung,pin-function = <0x2>; | |
| 98 | + samsung,pin-pud = <0>; | |
| 99 | + samsung,pin-drv = <0>; | |
| 100 | + }; | |
| 101 | + | |
| 102 | + uart0_fctl: uart0-fctl { | |
| 103 | + samsung,pins = "gpa0-2", "gpa0-3"; | |
| 104 | + samsung,pin-function = <2>; | |
| 105 | + samsung,pin-pud = <0>; | |
| 106 | + samsung,pin-drv = <0>; | |
| 107 | + }; | |
| 108 | + | |
| 109 | + uart1_data: uart1-data { | |
| 110 | + samsung,pins = "gpa0-4", "gpa0-5"; | |
| 111 | + samsung,pin-function = <2>; | |
| 112 | + samsung,pin-pud = <0>; | |
| 113 | + samsung,pin-drv = <0>; | |
| 114 | + }; | |
| 115 | + | |
| 116 | + uart1_fctl: uart1-fctl { | |
| 117 | + samsung,pins = "gpa0-6", "gpa0-7"; | |
| 118 | + samsung,pin-function = <2>; | |
| 119 | + samsung,pin-pud = <0>; | |
| 120 | + samsung,pin-drv = <0>; | |
| 121 | + }; | |
| 122 | + | |
| 123 | + uart2_data: uart2-data { | |
| 124 | + samsung,pins = "gpa1-0", "gpa1-1"; | |
| 125 | + samsung,pin-function = <2>; | |
| 126 | + samsung,pin-pud = <0>; | |
| 127 | + samsung,pin-drv = <0>; | |
| 128 | + }; | |
| 129 | + | |
| 130 | + uart2_fctl: uart2-fctl { | |
| 131 | + samsung,pins = "gpa1-2", "gpa1-3"; | |
| 132 | + samsung,pin-function = <2>; | |
| 133 | + samsung,pin-pud = <0>; | |
| 134 | + samsung,pin-drv = <0>; | |
| 135 | + }; | |
| 136 | + | |
| 137 | + uart3_data: uart3-data { | |
| 138 | + samsung,pins = "gpa1-4", "gpa1-5"; | |
| 139 | + samsung,pin-function = <2>; | |
| 140 | + samsung,pin-pud = <0>; | |
| 141 | + samsung,pin-drv = <0>; | |
| 142 | + }; | |
| 143 | + | |
| 144 | + i2c2_bus: i2c2-bus { | |
| 145 | + samsung,pins = "gpa0-6", "gpa0-7"; | |
| 146 | + samsung,pin-function = <3>; | |
| 147 | + samsung,pin-pud = <3>; | |
| 148 | + samsung,pin-drv = <0>; | |
| 149 | + }; | |
| 150 | + | |
| 151 | + i2c3_bus: i2c3-bus { | |
| 152 | + samsung,pins = "gpa1-2", "gpa1-3"; | |
| 153 | + samsung,pin-function = <3>; | |
| 154 | + samsung,pin-pud = <3>; | |
| 155 | + samsung,pin-drv = <0>; | |
| 156 | + }; | |
| 157 | + | |
| 158 | + spi0_bus: spi0-bus { | |
| 159 | + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; | |
| 160 | + samsung,pin-function = <2>; | |
| 161 | + samsung,pin-pud = <3>; | |
| 162 | + samsung,pin-drv = <0>; | |
| 163 | + }; | |
| 164 | + | |
| 165 | + i2c4_bus: i2c4-bus { | |
| 166 | + samsung,pins = "gpb-0", "gpb-1"; | |
| 167 | + samsung,pin-function = <3>; | |
| 168 | + samsung,pin-pud = <3>; | |
| 169 | + samsung,pin-drv = <0>; | |
| 170 | + }; | |
| 171 | + | |
| 172 | + spi1_bus: spi1-bus { | |
| 173 | + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; | |
| 174 | + samsung,pin-function = <2>; | |
| 175 | + samsung,pin-pud = <3>; | |
| 176 | + samsung,pin-drv = <0>; | |
| 177 | + }; | |
| 178 | + | |
| 179 | + i2c5_bus: i2c5-bus { | |
| 180 | + samsung,pins = "gpb-2", "gpb-3"; | |
| 181 | + samsung,pin-function = <3>; | |
| 182 | + samsung,pin-pud = <3>; | |
| 183 | + samsung,pin-drv = <0>; | |
| 184 | + }; | |
| 185 | + | |
| 186 | + i2s1_bus: i2s1-bus { | |
| 187 | + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", | |
| 188 | + "gpc0-4"; | |
| 189 | + samsung,pin-function = <2>; | |
| 190 | + samsung,pin-pud = <0>; | |
| 191 | + samsung,pin-drv = <0>; | |
| 192 | + }; | |
| 193 | + | |
| 194 | + i2s2_bus: i2s2-bus { | |
| 195 | + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", | |
| 196 | + "gpc1-4"; | |
| 197 | + samsung,pin-function = <2>; | |
| 198 | + samsung,pin-pud = <0>; | |
| 199 | + samsung,pin-drv = <0>; | |
| 200 | + }; | |
| 201 | + | |
| 202 | + pcm2_bus: pcm2-bus { | |
| 203 | + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", | |
| 204 | + "gpc1-4"; | |
| 205 | + samsung,pin-function = <3>; | |
| 206 | + samsung,pin-pud = <0>; | |
| 207 | + samsung,pin-drv = <0>; | |
| 208 | + }; | |
| 209 | + | |
| 210 | + i2c6_bus: i2c6-bus { | |
| 211 | + samsung,pins = "gpc1-3", "gpc1-4"; | |
| 212 | + samsung,pin-function = <4>; | |
| 213 | + samsung,pin-pud = <3>; | |
| 214 | + samsung,pin-drv = <0>; | |
| 215 | + }; | |
| 216 | + | |
| 217 | + spi2_bus: spi2-bus { | |
| 218 | + samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; | |
| 219 | + samsung,pin-function = <5>; | |
| 220 | + samsung,pin-pud = <3>; | |
| 221 | + samsung,pin-drv = <0>; | |
| 222 | + }; | |
| 223 | + | |
| 224 | + pwm0_out: pwm0-out { | |
| 225 | + samsung,pins = "gpd0-0"; | |
| 226 | + samsung,pin-function = <2>; | |
| 227 | + samsung,pin-pud = <0>; | |
| 228 | + samsung,pin-drv = <0>; | |
| 229 | + }; | |
| 230 | + | |
| 231 | + pwm1_out: pwm1-out { | |
| 232 | + samsung,pins = "gpd0-1"; | |
| 233 | + samsung,pin-function = <2>; | |
| 234 | + samsung,pin-pud = <0>; | |
| 235 | + samsung,pin-drv = <0>; | |
| 236 | + }; | |
| 237 | + | |
| 238 | + pwm2_out: pwm2-out { | |
| 239 | + samsung,pins = "gpd0-2"; | |
| 240 | + samsung,pin-function = <2>; | |
| 241 | + samsung,pin-pud = <0>; | |
| 242 | + samsung,pin-drv = <0>; | |
| 243 | + }; | |
| 244 | + | |
| 245 | + pwm3_out: pwm3-out { | |
| 246 | + samsung,pins = "gpd0-3"; | |
| 247 | + samsung,pin-function = <2>; | |
| 248 | + samsung,pin-pud = <0>; | |
| 249 | + samsung,pin-drv = <0>; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + i2c7_bus: i2c7-bus { | |
| 253 | + samsung,pins = "gpd0-2", "gpd0-3"; | |
| 254 | + samsung,pin-function = <3>; | |
| 255 | + samsung,pin-pud = <3>; | |
| 256 | + samsung,pin-drv = <0>; | |
| 257 | + }; | |
| 258 | + | |
| 259 | + i2c0_bus: i2c0-bus { | |
| 260 | + samsung,pins = "gpd1-0", "gpd1-1"; | |
| 261 | + samsung,pin-function = <2>; | |
| 262 | + samsung,pin-pud = <3>; | |
| 263 | + samsung,pin-drv = <0>; | |
| 264 | + }; | |
| 265 | + | |
| 266 | + i2c1_bus: i2c1-bus { | |
| 267 | + samsung,pins = "gpd1-2", "gpd1-3"; | |
| 268 | + samsung,pin-function = <2>; | |
| 269 | + samsung,pin-pud = <3>; | |
| 270 | + samsung,pin-drv = <0>; | |
| 271 | + }; | |
| 272 | +}; | |
| 273 | + | |
| 274 | +&pinctrl_1 { | |
| 275 | + gpk0: gpk0 { | |
| 276 | + gpio-controller; | |
| 277 | + #gpio-cells = <2>; | |
| 278 | + | |
| 279 | + interrupt-controller; | |
| 280 | + #interrupt-cells = <2>; | |
| 281 | + }; | |
| 282 | + | |
| 283 | + gpk1: gpk1 { | |
| 284 | + gpio-controller; | |
| 285 | + #gpio-cells = <2>; | |
| 286 | + | |
| 287 | + interrupt-controller; | |
| 288 | + #interrupt-cells = <2>; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + gpk2: gpk2 { | |
| 292 | + gpio-controller; | |
| 293 | + #gpio-cells = <2>; | |
| 294 | + | |
| 295 | + interrupt-controller; | |
| 296 | + #interrupt-cells = <2>; | |
| 297 | + }; | |
| 298 | + | |
| 299 | + gpk3: gpk3 { | |
| 300 | + gpio-controller; | |
| 301 | + #gpio-cells = <2>; | |
| 302 | + | |
| 303 | + interrupt-controller; | |
| 304 | + #interrupt-cells = <2>; | |
| 305 | + }; | |
| 306 | + | |
| 307 | + gpl0: gpl0 { | |
| 308 | + gpio-controller; | |
| 309 | + #gpio-cells = <2>; | |
| 310 | + | |
| 311 | + interrupt-controller; | |
| 312 | + #interrupt-cells = <2>; | |
| 313 | + }; | |
| 314 | + | |
| 315 | + gpm0: gpm0 { | |
| 316 | + gpio-controller; | |
| 317 | + #gpio-cells = <2>; | |
| 318 | + | |
| 319 | + interrupt-controller; | |
| 320 | + #interrupt-cells = <2>; | |
| 321 | + }; | |
| 322 | + | |
| 323 | + gpm1: gpm1 { | |
| 324 | + gpio-controller; | |
| 325 | + #gpio-cells = <2>; | |
| 326 | + | |
| 327 | + interrupt-controller; | |
| 328 | + #interrupt-cells = <2>; | |
| 329 | + }; | |
| 330 | + | |
| 331 | + gpm2: gpm2 { | |
| 332 | + gpio-controller; | |
| 333 | + #gpio-cells = <2>; | |
| 334 | + | |
| 335 | + interrupt-controller; | |
| 336 | + #interrupt-cells = <2>; | |
| 337 | + }; | |
| 338 | + | |
| 339 | + gpm3: gpm3 { | |
| 340 | + gpio-controller; | |
| 341 | + #gpio-cells = <2>; | |
| 342 | + | |
| 343 | + interrupt-controller; | |
| 344 | + #interrupt-cells = <2>; | |
| 345 | + }; | |
| 346 | + | |
| 347 | + gpm4: gpm4 { | |
| 348 | + gpio-controller; | |
| 349 | + #gpio-cells = <2>; | |
| 350 | + | |
| 351 | + interrupt-controller; | |
| 352 | + #interrupt-cells = <2>; | |
| 353 | + }; | |
| 354 | + | |
| 355 | + gpx0: gpx0 { | |
| 356 | + gpio-controller; | |
| 357 | + #gpio-cells = <2>; | |
| 358 | + | |
| 359 | + interrupt-controller; | |
| 360 | + interrupt-parent = <&gic>; | |
| 361 | + interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, | |
| 362 | + <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; | |
| 363 | + #interrupt-cells = <2>; | |
| 364 | + }; | |
| 365 | + | |
| 366 | + gpx1: gpx1 { | |
| 367 | + gpio-controller; | |
| 368 | + #gpio-cells = <2>; | |
| 369 | + | |
| 370 | + interrupt-controller; | |
| 371 | + interrupt-parent = <&gic>; | |
| 372 | + interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, | |
| 373 | + <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; | |
| 374 | + #interrupt-cells = <2>; | |
| 375 | + }; | |
| 376 | + | |
| 377 | + gpx2: gpx2 { | |
| 378 | + gpio-controller; | |
| 379 | + #gpio-cells = <2>; | |
| 380 | + | |
| 381 | + interrupt-controller; | |
| 382 | + #interrupt-cells = <2>; | |
| 383 | + }; | |
| 384 | + | |
| 385 | + gpx3: gpx3 { | |
| 386 | + gpio-controller; | |
| 387 | + #gpio-cells = <2>; | |
| 388 | + | |
| 389 | + interrupt-controller; | |
| 390 | + #interrupt-cells = <2>; | |
| 391 | + }; | |
| 392 | + | |
| 393 | + sd0_clk: sd0-clk { | |
| 394 | + samsung,pins = "gpk0-0"; | |
| 395 | + samsung,pin-function = <2>; | |
| 396 | + samsung,pin-pud = <0>; | |
| 397 | + samsung,pin-drv = <3>; | |
| 398 | + }; | |
| 399 | + | |
| 400 | + sd0_cmd: sd0-cmd { | |
| 401 | + samsung,pins = "gpk0-1"; | |
| 402 | + samsung,pin-function = <2>; | |
| 403 | + samsung,pin-pud = <0>; | |
| 404 | + samsung,pin-drv = <3>; | |
| 405 | + }; | |
| 406 | + | |
| 407 | + sd0_cd: sd0-cd { | |
| 408 | + samsung,pins = "gpk0-2"; | |
| 409 | + samsung,pin-function = <2>; | |
| 410 | + samsung,pin-pud = <3>; | |
| 411 | + samsung,pin-drv = <3>; | |
| 412 | + }; | |
| 413 | + | |
| 414 | + sd0_rdqs: sd0-rdqs { | |
| 415 | + samsung,pins = "gpk0-7"; | |
| 416 | + samsung,pin-function = <2>; | |
| 417 | + samsung,pin-pud = <0>; | |
| 418 | + samsung,pin-drv = <3>; | |
| 419 | + }; | |
| 420 | + | |
| 421 | + sd0_bus1: sd0-bus-width1 { | |
| 422 | + samsung,pins = "gpk0-3"; | |
| 423 | + samsung,pin-function = <2>; | |
| 424 | + samsung,pin-pud = <3>; | |
| 425 | + samsung,pin-drv = <3>; | |
| 426 | + }; | |
| 427 | + | |
| 428 | + sd0_bus4: sd0-bus-width4 { | |
| 429 | + samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; | |
| 430 | + samsung,pin-function = <2>; | |
| 431 | + samsung,pin-pud = <3>; | |
| 432 | + samsung,pin-drv = <3>; | |
| 433 | + }; | |
| 434 | + | |
| 435 | + sd0_bus8: sd0-bus-width8 { | |
| 436 | + samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; | |
| 437 | + samsung,pin-function = <2>; | |
| 438 | + samsung,pin-pud = <3>; | |
| 439 | + samsung,pin-drv = <3>; | |
| 440 | + }; | |
| 441 | + | |
| 442 | + sd1_clk: sd1-clk { | |
| 443 | + samsung,pins = "gpk1-0"; | |
| 444 | + samsung,pin-function = <2>; | |
| 445 | + samsung,pin-pud = <0>; | |
| 446 | + samsung,pin-drv = <3>; | |
| 447 | + }; | |
| 448 | + | |
| 449 | + sd1_cmd: sd1-cmd { | |
| 450 | + samsung,pins = "gpk1-1"; | |
| 451 | + samsung,pin-function = <2>; | |
| 452 | + samsung,pin-pud = <0>; | |
| 453 | + samsung,pin-drv = <3>; | |
| 454 | + }; | |
| 455 | + | |
| 456 | + sd1_cd: sd1-cd { | |
| 457 | + samsung,pins = "gpk1-2"; | |
| 458 | + samsung,pin-function = <2>; | |
| 459 | + samsung,pin-pud = <3>; | |
| 460 | + samsung,pin-drv = <3>; | |
| 461 | + }; | |
| 462 | + | |
| 463 | + sd1_bus1: sd1-bus-width1 { | |
| 464 | + samsung,pins = "gpk1-3"; | |
| 465 | + samsung,pin-function = <2>; | |
| 466 | + samsung,pin-pud = <3>; | |
| 467 | + samsung,pin-drv = <3>; | |
| 468 | + }; | |
| 469 | + | |
| 470 | + sd1_bus4: sd1-bus-width4 { | |
| 471 | + samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; | |
| 472 | + samsung,pin-function = <2>; | |
| 473 | + samsung,pin-pud = <3>; | |
| 474 | + samsung,pin-drv = <3>; | |
| 475 | + }; | |
| 476 | + | |
| 477 | + sd2_clk: sd2-clk { | |
| 478 | + samsung,pins = "gpk2-0"; | |
| 479 | + samsung,pin-function = <2>; | |
| 480 | + samsung,pin-pud = <0>; | |
| 481 | + samsung,pin-drv = <4>; | |
| 482 | + }; | |
| 483 | + | |
| 484 | + sd2_cmd: sd2-cmd { | |
| 485 | + samsung,pins = "gpk2-1"; | |
| 486 | + samsung,pin-function = <2>; | |
| 487 | + samsung,pin-pud = <0>; | |
| 488 | + samsung,pin-drv = <4>; | |
| 489 | + }; | |
| 490 | + | |
| 491 | + sd2_cd: sd2-cd { | |
| 492 | + samsung,pins = "gpk2-2"; | |
| 493 | + samsung,pin-function = <2>; | |
| 494 | + samsung,pin-pud = <3>; | |
| 495 | + samsung,pin-drv = <3>; | |
| 496 | + }; | |
| 497 | + | |
| 498 | + sd2_bus1: sd2-bus-width1 { | |
| 499 | + samsung,pins = "gpk2-3"; | |
| 500 | + samsung,pin-function = <2>; | |
| 501 | + samsung,pin-pud = <3>; | |
| 502 | + samsung,pin-drv = <4>; | |
| 503 | + }; | |
| 504 | + | |
| 505 | + sd2_bus4: sd2-bus-width4 { | |
| 506 | + samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; | |
| 507 | + samsung,pin-function = <2>; | |
| 508 | + samsung,pin-pud = <3>; | |
| 509 | + samsung,pin-drv = <4>; | |
| 510 | + }; | |
| 511 | + | |
| 512 | + cam_port_b_io: cam-port-b-io { | |
| 513 | + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", | |
| 514 | + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", | |
| 515 | + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; | |
| 516 | + samsung,pin-function = <3>; | |
| 517 | + samsung,pin-pud = <3>; | |
| 518 | + samsung,pin-drv = <0>; | |
| 519 | + }; | |
| 520 | + | |
| 521 | + cam_port_b_clk_active: cam-port-b-clk-active { | |
| 522 | + samsung,pins = "gpm2-2"; | |
| 523 | + samsung,pin-function = <3>; | |
| 524 | + samsung,pin-pud = <0>; | |
| 525 | + samsung,pin-drv = <3>; | |
| 526 | + }; | |
| 527 | + | |
| 528 | + cam_port_b_clk_idle: cam-port-b-clk-idle { | |
| 529 | + samsung,pins = "gpm2-2"; | |
| 530 | + samsung,pin-function = <0>; | |
| 531 | + samsung,pin-pud = <0>; | |
| 532 | + samsung,pin-drv = <0>; | |
| 533 | + }; | |
| 534 | + | |
| 535 | + fimc_is_i2c0: fimc-is-i2c0 { | |
| 536 | + samsung,pins = "gpm4-0", "gpm4-1"; | |
| 537 | + samsung,pin-function = <2>; | |
| 538 | + samsung,pin-pud = <0>; | |
| 539 | + samsung,pin-drv = <0>; | |
| 540 | + }; | |
| 541 | + | |
| 542 | + fimc_is_i2c1: fimc-is-i2c1 { | |
| 543 | + samsung,pins = "gpm4-2", "gpm4-3"; | |
| 544 | + samsung,pin-function = <2>; | |
| 545 | + samsung,pin-pud = <0>; | |
| 546 | + samsung,pin-drv = <0>; | |
| 547 | + }; | |
| 548 | + | |
| 549 | + fimc_is_uart: fimc-is-uart { | |
| 550 | + samsung,pins = "gpm3-5", "gpm3-7"; | |
| 551 | + samsung,pin-function = <3>; | |
| 552 | + samsung,pin-pud = <0>; | |
| 553 | + samsung,pin-drv = <0>; | |
| 554 | + }; | |
| 555 | +}; | |
| 556 | + | |
| 557 | +&pinctrl_2 { | |
| 558 | + gpz: gpz { | |
| 559 | + gpio-controller; | |
| 560 | + #gpio-cells = <2>; | |
| 561 | + | |
| 562 | + interrupt-controller; | |
| 563 | + #interrupt-cells = <2>; | |
| 564 | + }; | |
| 565 | + | |
| 566 | + i2s0_bus: i2s0-bus { | |
| 567 | + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", | |
| 568 | + "gpz-4", "gpz-5", "gpz-6"; | |
| 569 | + samsung,pin-function = <2>; | |
| 570 | + samsung,pin-pud = <0>; | |
| 571 | + samsung,pin-drv = <0>; | |
| 572 | + }; | |
| 573 | +}; | |
| @@ -0,0 +1,604 @@ | ||
| 1 | +/* | |
| 2 | + * Samsung's Exynos4415 SoC device tree source | |
| 3 | + * | |
| 4 | + * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
| 5 | + * | |
| 6 | + * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 | |
| 7 | + * based board files can include this file and provide values for board | |
| 8 | + * specific bindings. | |
| 9 | + * | |
| 10 | + * Note: This file does not include device nodes for all the controllers in | |
| 11 | + * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional | |
| 12 | + * nodes can be added to this file. | |
| 13 | + * | |
| 14 | + * This program is free software; you can redistribute it and/or modify | |
| 15 | + * it under the terms of the GNU General Public License version 2 as | |
| 16 | + * published by the Free Software Foundation. | |
| 17 | + */ | |
| 18 | + | |
| 19 | +#include "skeleton.dtsi" | |
| 20 | +#include <dt-bindings/clock/exynos4415.h> | |
| 21 | +#include <dt-bindings/clock/exynos-audss-clk.h> | |
| 22 | + | |
| 23 | +/ { | |
| 24 | + compatible = "samsung,exynos4415"; | |
| 25 | + interrupt-parent = <&gic>; | |
| 26 | + | |
| 27 | + aliases { | |
| 28 | + pinctrl0 = &pinctrl_0; | |
| 29 | + pinctrl1 = &pinctrl_1; | |
| 30 | + pinctrl2 = &pinctrl_2; | |
| 31 | + mshc0 = &mshc_0; | |
| 32 | + mshc1 = &mshc_1; | |
| 33 | + mshc2 = &mshc_2; | |
| 34 | + spi0 = &spi_0; | |
| 35 | + spi1 = &spi_1; | |
| 36 | + spi2 = &spi_2; | |
| 37 | + i2c0 = &i2c_0; | |
| 38 | + i2c1 = &i2c_1; | |
| 39 | + i2c2 = &i2c_2; | |
| 40 | + i2c3 = &i2c_3; | |
| 41 | + i2c4 = &i2c_4; | |
| 42 | + i2c5 = &i2c_5; | |
| 43 | + i2c6 = &i2c_6; | |
| 44 | + i2c7 = &i2c_7; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + cpus { | |
| 48 | + #address-cells = <1>; | |
| 49 | + #size-cells = <0>; | |
| 50 | + | |
| 51 | + cpu0: cpu@a00 { | |
| 52 | + device_type = "cpu"; | |
| 53 | + compatible = "arm,cortex-a9"; | |
| 54 | + reg = <0xa00>; | |
| 55 | + clock-frequency = <1600000000>; | |
| 56 | + }; | |
| 57 | + | |
| 58 | + cpu1: cpu@a01 { | |
| 59 | + device_type = "cpu"; | |
| 60 | + compatible = "arm,cortex-a9"; | |
| 61 | + reg = <0xa01>; | |
| 62 | + clock-frequency = <1600000000>; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + cpu2: cpu@a02 { | |
| 66 | + device_type = "cpu"; | |
| 67 | + compatible = "arm,cortex-a9"; | |
| 68 | + reg = <0xa02>; | |
| 69 | + clock-frequency = <1600000000>; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + cpu3: cpu@a03 { | |
| 73 | + device_type = "cpu"; | |
| 74 | + compatible = "arm,cortex-a9"; | |
| 75 | + reg = <0xa03>; | |
| 76 | + clock-frequency = <1600000000>; | |
| 77 | + }; | |
| 78 | + }; | |
| 79 | + | |
| 80 | + soc: soc { | |
| 81 | + compatible = "simple-bus"; | |
| 82 | + #address-cells = <1>; | |
| 83 | + #size-cells = <1>; | |
| 84 | + ranges; | |
| 85 | + | |
| 86 | + sysram@02020000 { | |
| 87 | + compatible = "mmio-sram"; | |
| 88 | + reg = <0x02020000 0x50000>; | |
| 89 | + #address-cells = <1>; | |
| 90 | + #size-cells = <1>; | |
| 91 | + ranges = <0 0x02020000 0x50000>; | |
| 92 | + | |
| 93 | + smp-sysram@0 { | |
| 94 | + compatible = "samsung,exynos4210-sysram"; | |
| 95 | + reg = <0x0 0x1000>; | |
| 96 | + }; | |
| 97 | + | |
| 98 | + smp-sysram@4f000 { | |
| 99 | + compatible = "samsung,exynos4210-sysram-ns"; | |
| 100 | + reg = <0x4f000 0x1000>; | |
| 101 | + }; | |
| 102 | + }; | |
| 103 | + | |
| 104 | + pinctrl_2: pinctrl@03860000 { | |
| 105 | + compatible = "samsung,exynos4415-pinctrl"; | |
| 106 | + reg = <0x03860000 0x1000>; | |
| 107 | + interrupts = <0 242 0>; | |
| 108 | + }; | |
| 109 | + | |
| 110 | + chipid@10000000 { | |
| 111 | + compatible = "samsung,exynos4210-chipid"; | |
| 112 | + reg = <0x10000000 0x100>; | |
| 113 | + }; | |
| 114 | + | |
| 115 | + sysreg_system_controller: syscon@10010000 { | |
| 116 | + compatible = "samsung,exynos4-sysreg", "syscon"; | |
| 117 | + reg = <0x10010000 0x400>; | |
| 118 | + }; | |
| 119 | + | |
| 120 | + pmu_system_controller: system-controller@10020000 { | |
| 121 | + compatible = "samsung,exynos4415-pmu", "syscon"; | |
| 122 | + reg = <0x10020000 0x4000>; | |
| 123 | + }; | |
| 124 | + | |
| 125 | + mipi_phy: video-phy@10020710 { | |
| 126 | + compatible = "samsung,s5pv210-mipi-video-phy"; | |
| 127 | + reg = <0x10020710 8>; | |
| 128 | + #phy-cells = <1>; | |
| 129 | + }; | |
| 130 | + | |
| 131 | + pd_cam: cam-power-domain@10024000 { | |
| 132 | + compatible = "samsung,exynos4210-pd"; | |
| 133 | + reg = <0x10024000 0x20>; | |
| 134 | + }; | |
| 135 | + | |
| 136 | + pd_tv: tv-power-domain@10024020 { | |
| 137 | + compatible = "samsung,exynos4210-pd"; | |
| 138 | + reg = <0x10024020 0x20>; | |
| 139 | + }; | |
| 140 | + | |
| 141 | + pd_mfc: mfc-power-domain@10024040 { | |
| 142 | + compatible = "samsung,exynos4210-pd"; | |
| 143 | + reg = <0x10024040 0x20>; | |
| 144 | + }; | |
| 145 | + | |
| 146 | + pd_g3d: g3d-power-domain@10024060 { | |
| 147 | + compatible = "samsung,exynos4210-pd"; | |
| 148 | + reg = <0x10024060 0x20>; | |
| 149 | + }; | |
| 150 | + | |
| 151 | + pd_lcd0: lcd0-power-domain@10024080 { | |
| 152 | + compatible = "samsung,exynos4210-pd"; | |
| 153 | + reg = <0x10024080 0x20>; | |
| 154 | + }; | |
| 155 | + | |
| 156 | + pd_isp0: isp0-power-domain@100240A0 { | |
| 157 | + compatible = "samsung,exynos4210-pd"; | |
| 158 | + reg = <0x100240A0 0x20>; | |
| 159 | + }; | |
| 160 | + | |
| 161 | + pd_isp1: isp1-power-domain@100240E0 { | |
| 162 | + compatible = "samsung,exynos4210-pd"; | |
| 163 | + reg = <0x100240E0 0x20>; | |
| 164 | + }; | |
| 165 | + | |
| 166 | + cmu: clock-controller@10030000 { | |
| 167 | + compatible = "samsung,exynos4415-cmu"; | |
| 168 | + reg = <0x10030000 0x18000>; | |
| 169 | + #clock-cells = <1>; | |
| 170 | + }; | |
| 171 | + | |
| 172 | + rtc: rtc@10070000 { | |
| 173 | + compatible = "samsung,exynos3250-rtc"; | |
| 174 | + reg = <0x10070000 0x100>; | |
| 175 | + interrupts = <0 73 0>, <0 74 0>; | |
| 176 | + status = "disabled"; | |
| 177 | + }; | |
| 178 | + | |
| 179 | + mct@10050000 { | |
| 180 | + compatible = "samsung,exynos4210-mct"; | |
| 181 | + reg = <0x10050000 0x800>; | |
| 182 | + interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, | |
| 183 | + <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; | |
| 184 | + clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; | |
| 185 | + clock-names = "fin_pll", "mct"; | |
| 186 | + }; | |
| 187 | + | |
| 188 | + gic: interrupt-controller@10481000 { | |
| 189 | + compatible = "arm,cortex-a9-gic"; | |
| 190 | + #interrupt-cells = <3>; | |
| 191 | + interrupt-controller; | |
| 192 | + reg = <0x10481000 0x1000>, | |
| 193 | + <0x10482000 0x1000>, | |
| 194 | + <0x10484000 0x2000>, | |
| 195 | + <0x10486000 0x2000>; | |
| 196 | + interrupts = <1 9 0xf04>; | |
| 197 | + }; | |
| 198 | + | |
| 199 | + l2c: l2-cache-controller@10502000 { | |
| 200 | + compatible = "arm,pl310-cache"; | |
| 201 | + reg = <0x10502000 0x1000>; | |
| 202 | + cache-unified; | |
| 203 | + cache-level = <2>; | |
| 204 | + arm,tag-latency = <2 2 1>; | |
| 205 | + arm,data-latency = <3 2 1>; | |
| 206 | + arm,double-linefill = <1>; | |
| 207 | + arm,double-linefill-incr = <0>; | |
| 208 | + arm,double-linefill-wrap = <1>; | |
| 209 | + arm,prefetch-drop = <1>; | |
| 210 | + arm,prefetch-offset = <7>; | |
| 211 | + }; | |
| 212 | + | |
| 213 | + cmu_dmc: clock-controller@105C0000 { | |
| 214 | + compatible = "samsung,exynos4415-cmu-dmc"; | |
| 215 | + reg = <0x105C0000 0x3000>; | |
| 216 | + #clock-cells = <1>; | |
| 217 | + }; | |
| 218 | + | |
| 219 | + pinctrl_1: pinctrl@11000000 { | |
| 220 | + compatible = "samsung,exynos4415-pinctrl"; | |
| 221 | + reg = <0x11000000 0x1000>; | |
| 222 | + interrupts = <0 225 0>; | |
| 223 | + | |
| 224 | + wakeup-interrupt-controller { | |
| 225 | + compatible = "samsung,exynos4210-wakeup-eint"; | |
| 226 | + interrupt-parent = <&gic>; | |
| 227 | + interrupts = <0 48 0>; | |
| 228 | + }; | |
| 229 | + }; | |
| 230 | + | |
| 231 | + pinctrl_0: pinctrl@11400000 { | |
| 232 | + compatible = "samsung,exynos4415-pinctrl"; | |
| 233 | + reg = <0x11400000 0x1000>; | |
| 234 | + interrupts = <0 240 0>; | |
| 235 | + }; | |
| 236 | + | |
| 237 | + hsotg: hsotg@12480000 { | |
| 238 | + compatible = "samsung,s3c6400-hsotg"; | |
| 239 | + reg = <0x12480000 0x20000>; | |
| 240 | + interrupts = <0 141 0>; | |
| 241 | + clocks = <&cmu CLK_USBDEVICE>; | |
| 242 | + clock-names = "otg"; | |
| 243 | + phys = <&exynos_usbphy 0>; | |
| 244 | + phy-names = "usb2-phy"; | |
| 245 | + status = "disabled"; | |
| 246 | + }; | |
| 247 | + | |
| 248 | + mshc_0: mshc@12510000 { | |
| 249 | + compatible = "samsung,exynos5250-dw-mshc"; | |
| 250 | + reg = <0x12510000 0x1000>; | |
| 251 | + interrupts = <0 142 0>; | |
| 252 | + clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; | |
| 253 | + clock-names = "biu", "ciu"; | |
| 254 | + fifo-depth = <0x80>; | |
| 255 | + #address-cells = <1>; | |
| 256 | + #size-cells = <0>; | |
| 257 | + status = "disabled"; | |
| 258 | + }; | |
| 259 | + | |
| 260 | + mshc_1: mshc@12520000 { | |
| 261 | + compatible = "samsung,exynos5250-dw-mshc"; | |
| 262 | + reg = <0x12520000 0x1000>; | |
| 263 | + interrupts = <0 143 0>; | |
| 264 | + clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; | |
| 265 | + clock-names = "biu", "ciu"; | |
| 266 | + fifo-depth = <0x80>; | |
| 267 | + #address-cells = <1>; | |
| 268 | + #size-cells = <0>; | |
| 269 | + status = "disabled"; | |
| 270 | + }; | |
| 271 | + | |
| 272 | + mshc_2: mshc@12530000 { | |
| 273 | + compatible = "samsung,exynos5250-dw-mshc"; | |
| 274 | + reg = <0x12530000 0x1000>; | |
| 275 | + interrupts = <0 144 0>; | |
| 276 | + clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; | |
| 277 | + clock-names = "biu", "ciu"; | |
| 278 | + fifo-depth = <0x80>; | |
| 279 | + #address-cells = <1>; | |
| 280 | + #size-cells = <0>; | |
| 281 | + status = "disabled"; | |
| 282 | + }; | |
| 283 | + | |
| 284 | + ehci: ehci@12580000 { | |
| 285 | + compatible = "samsung,exynos4210-ehci"; | |
| 286 | + reg = <0x12580000 0x100>; | |
| 287 | + interrupts = <0 140 0>; | |
| 288 | + clocks = <&cmu CLK_USBHOST>; | |
| 289 | + clock-names = "usbhost"; | |
| 290 | + status = "disabled"; | |
| 291 | + #address-cells = <1>; | |
| 292 | + #size-cells = <0>; | |
| 293 | + port@0 { | |
| 294 | + reg = <0>; | |
| 295 | + phys = <&exynos_usbphy 1>; | |
| 296 | + status = "disabled"; | |
| 297 | + }; | |
| 298 | + port@1 { | |
| 299 | + reg = <1>; | |
| 300 | + phys = <&exynos_usbphy 2>; | |
| 301 | + status = "disabled"; | |
| 302 | + }; | |
| 303 | + port@2 { | |
| 304 | + reg = <2>; | |
| 305 | + phys = <&exynos_usbphy 3>; | |
| 306 | + status = "disabled"; | |
| 307 | + }; | |
| 308 | + }; | |
| 309 | + | |
| 310 | + ohci: ohci@12590000 { | |
| 311 | + compatible = "samsung,exynos4210-ohci"; | |
| 312 | + reg = <0x12590000 0x100>; | |
| 313 | + interrupts = <0 140 0>; | |
| 314 | + clocks = <&cmu CLK_USBHOST>; | |
| 315 | + clock-names = "usbhost"; | |
| 316 | + status = "disabled"; | |
| 317 | + #address-cells = <1>; | |
| 318 | + #size-cells = <0>; | |
| 319 | + port@0 { | |
| 320 | + reg = <0>; | |
| 321 | + phys = <&exynos_usbphy 1>; | |
| 322 | + status = "disabled"; | |
| 323 | + }; | |
| 324 | + }; | |
| 325 | + | |
| 326 | + exynos_usbphy: exynos-usbphy@125B0000 { | |
| 327 | + compatible = "samsung,exynos4x12-usb2-phy"; | |
| 328 | + reg = <0x125B0000 0x100>; | |
| 329 | + samsung,pmureg-phandle = <&pmu_system_controller>; | |
| 330 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 331 | + clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; | |
| 332 | + clock-names = "phy", "ref"; | |
| 333 | + #phy-cells = <1>; | |
| 334 | + status = "disabled"; | |
| 335 | + }; | |
| 336 | + | |
| 337 | + amba { | |
| 338 | + compatible = "arm,amba-bus"; | |
| 339 | + #address-cells = <1>; | |
| 340 | + #size-cells = <1>; | |
| 341 | + interrupt-parent = <&gic>; | |
| 342 | + ranges; | |
| 343 | + | |
| 344 | + pdma0: pdma@12680000 { | |
| 345 | + compatible = "arm,pl330", "arm,primecell"; | |
| 346 | + reg = <0x12680000 0x1000>; | |
| 347 | + interrupts = <0 138 0>; | |
| 348 | + clocks = <&cmu CLK_PDMA0>; | |
| 349 | + clock-names = "apb_pclk"; | |
| 350 | + #dma-cells = <1>; | |
| 351 | + #dma-channels = <8>; | |
| 352 | + #dma-requests = <32>; | |
| 353 | + }; | |
| 354 | + | |
| 355 | + pdma1: pdma@12690000 { | |
| 356 | + compatible = "arm,pl330", "arm,primecell"; | |
| 357 | + reg = <0x12690000 0x1000>; | |
| 358 | + interrupts = <0 139 0>; | |
| 359 | + clocks = <&cmu CLK_PDMA1>; | |
| 360 | + clock-names = "apb_pclk"; | |
| 361 | + #dma-cells = <1>; | |
| 362 | + #dma-channels = <8>; | |
| 363 | + #dma-requests = <32>; | |
| 364 | + }; | |
| 365 | + }; | |
| 366 | + | |
| 367 | + adc: adc@126C0000 { | |
| 368 | + compatible = "samsung,exynos3250-adc", | |
| 369 | + "samsung,exynos-adc-v2"; | |
| 370 | + reg = <0x126C0000 0x100>, <0x10020718 0x4>; | |
| 371 | + interrupts = <0 137 0>; | |
| 372 | + clock-names = "adc", "sclk"; | |
| 373 | + clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; | |
| 374 | + #io-channel-cells = <1>; | |
| 375 | + io-channel-ranges; | |
| 376 | + status = "disabled"; | |
| 377 | + }; | |
| 378 | + | |
| 379 | + serial_0: serial@13800000 { | |
| 380 | + compatible = "samsung,exynos4210-uart"; | |
| 381 | + reg = <0x13800000 0x100>; | |
| 382 | + interrupts = <0 109 0>; | |
| 383 | + clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; | |
| 384 | + clock-names = "uart", "clk_uart_baud0"; | |
| 385 | + status = "disabled"; | |
| 386 | + }; | |
| 387 | + | |
| 388 | + serial_1: serial@13810000 { | |
| 389 | + compatible = "samsung,exynos4210-uart"; | |
| 390 | + reg = <0x13810000 0x100>; | |
| 391 | + interrupts = <0 110 0>; | |
| 392 | + clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; | |
| 393 | + clock-names = "uart", "clk_uart_baud0"; | |
| 394 | + status = "disabled"; | |
| 395 | + }; | |
| 396 | + | |
| 397 | + serial_2: serial@13820000 { | |
| 398 | + compatible = "samsung,exynos4210-uart"; | |
| 399 | + reg = <0x13820000 0x100>; | |
| 400 | + interrupts = <0 111 0>; | |
| 401 | + clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; | |
| 402 | + clock-names = "uart", "clk_uart_baud0"; | |
| 403 | + status = "disabled"; | |
| 404 | + }; | |
| 405 | + | |
| 406 | + serial_3: serial@13830000 { | |
| 407 | + compatible = "samsung,exynos4210-uart"; | |
| 408 | + reg = <0x13830000 0x100>; | |
| 409 | + interrupts = <0 112 0>; | |
| 410 | + clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; | |
| 411 | + clock-names = "uart", "clk_uart_baud0"; | |
| 412 | + status = "disabled"; | |
| 413 | + }; | |
| 414 | + | |
| 415 | + i2c_0: i2c@13860000 { | |
| 416 | + #address-cells = <1>; | |
| 417 | + #size-cells = <0>; | |
| 418 | + compatible = "samsung,s3c2440-i2c"; | |
| 419 | + reg = <0x13860000 0x100>; | |
| 420 | + interrupts = <0 113 0>; | |
| 421 | + clocks = <&cmu CLK_I2C0>; | |
| 422 | + clock-names = "i2c"; | |
| 423 | + pinctrl-names = "default"; | |
| 424 | + pinctrl-0 = <&i2c0_bus>; | |
| 425 | + status = "disabled"; | |
| 426 | + }; | |
| 427 | + | |
| 428 | + i2c_1: i2c@13870000 { | |
| 429 | + #address-cells = <1>; | |
| 430 | + #size-cells = <0>; | |
| 431 | + compatible = "samsung,s3c2440-i2c"; | |
| 432 | + reg = <0x13870000 0x100>; | |
| 433 | + interrupts = <0 114 0>; | |
| 434 | + clocks = <&cmu CLK_I2C1>; | |
| 435 | + clock-names = "i2c"; | |
| 436 | + pinctrl-names = "default"; | |
| 437 | + pinctrl-0 = <&i2c1_bus>; | |
| 438 | + status = "disabled"; | |
| 439 | + }; | |
| 440 | + | |
| 441 | + i2c_2: i2c@13880000 { | |
| 442 | + #address-cells = <1>; | |
| 443 | + #size-cells = <0>; | |
| 444 | + compatible = "samsung,s3c2440-i2c"; | |
| 445 | + reg = <0x13880000 0x100>; | |
| 446 | + interrupts = <0 115 0>; | |
| 447 | + clocks = <&cmu CLK_I2C2>; | |
| 448 | + clock-names = "i2c"; | |
| 449 | + pinctrl-names = "default"; | |
| 450 | + pinctrl-0 = <&i2c2_bus>; | |
| 451 | + status = "disabled"; | |
| 452 | + }; | |
| 453 | + | |
| 454 | + i2c_3: i2c@13890000 { | |
| 455 | + #address-cells = <1>; | |
| 456 | + #size-cells = <0>; | |
| 457 | + compatible = "samsung,s3c2440-i2c"; | |
| 458 | + reg = <0x13890000 0x100>; | |
| 459 | + interrupts = <0 116 0>; | |
| 460 | + clocks = <&cmu CLK_I2C3>; | |
| 461 | + clock-names = "i2c"; | |
| 462 | + pinctrl-names = "default"; | |
| 463 | + pinctrl-0 = <&i2c3_bus>; | |
| 464 | + status = "disabled"; | |
| 465 | + }; | |
| 466 | + | |
| 467 | + i2c_4: i2c@138A0000 { | |
| 468 | + #address-cells = <1>; | |
| 469 | + #size-cells = <0>; | |
| 470 | + compatible = "samsung,s3c2440-i2c"; | |
| 471 | + reg = <0x138A0000 0x100>; | |
| 472 | + interrupts = <0 117 0>; | |
| 473 | + clocks = <&cmu CLK_I2C4>; | |
| 474 | + clock-names = "i2c"; | |
| 475 | + pinctrl-names = "default"; | |
| 476 | + pinctrl-0 = <&i2c4_bus>; | |
| 477 | + status = "disabled"; | |
| 478 | + }; | |
| 479 | + | |
| 480 | + i2c_5: i2c@138B0000 { | |
| 481 | + #address-cells = <1>; | |
| 482 | + #size-cells = <0>; | |
| 483 | + compatible = "samsung,s3c2440-i2c"; | |
| 484 | + reg = <0x138B0000 0x100>; | |
| 485 | + interrupts = <0 118 0>; | |
| 486 | + clocks = <&cmu CLK_I2C5>; | |
| 487 | + clock-names = "i2c"; | |
| 488 | + pinctrl-names = "default"; | |
| 489 | + pinctrl-0 = <&i2c5_bus>; | |
| 490 | + status = "disabled"; | |
| 491 | + }; | |
| 492 | + | |
| 493 | + i2c_6: i2c@138C0000 { | |
| 494 | + #address-cells = <1>; | |
| 495 | + #size-cells = <0>; | |
| 496 | + compatible = "samsung,s3c2440-i2c"; | |
| 497 | + reg = <0x138C0000 0x100>; | |
| 498 | + interrupts = <0 119 0>; | |
| 499 | + clocks = <&cmu CLK_I2C6>; | |
| 500 | + clock-names = "i2c"; | |
| 501 | + pinctrl-names = "default"; | |
| 502 | + pinctrl-0 = <&i2c6_bus>; | |
| 503 | + status = "disabled"; | |
| 504 | + }; | |
| 505 | + | |
| 506 | + i2c_7: i2c@138D0000 { | |
| 507 | + #address-cells = <1>; | |
| 508 | + #size-cells = <0>; | |
| 509 | + compatible = "samsung,s3c2440-i2c"; | |
| 510 | + reg = <0x138D0000 0x100>; | |
| 511 | + interrupts = <0 120 0>; | |
| 512 | + clocks = <&cmu CLK_I2C7>; | |
| 513 | + clock-names = "i2c"; | |
| 514 | + pinctrl-names = "default"; | |
| 515 | + pinctrl-0 = <&i2c7_bus>; | |
| 516 | + status = "disabled"; | |
| 517 | + }; | |
| 518 | + | |
| 519 | + spi_0: spi@13920000 { | |
| 520 | + compatible = "samsung,exynos4210-spi"; | |
| 521 | + reg = <0x13920000 0x100>; | |
| 522 | + interrupts = <0 121 0>; | |
| 523 | + dmas = <&pdma0 7>, <&pdma0 6>; | |
| 524 | + dma-names = "tx", "rx"; | |
| 525 | + #address-cells = <1>; | |
| 526 | + #size-cells = <0>; | |
| 527 | + clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; | |
| 528 | + clock-names = "spi", "spi_busclk0"; | |
| 529 | + samsung,spi-src-clk = <0>; | |
| 530 | + pinctrl-names = "default"; | |
| 531 | + pinctrl-0 = <&spi0_bus>; | |
| 532 | + status = "disabled"; | |
| 533 | + }; | |
| 534 | + | |
| 535 | + spi_1: spi@13930000 { | |
| 536 | + compatible = "samsung,exynos4210-spi"; | |
| 537 | + reg = <0x13930000 0x100>; | |
| 538 | + interrupts = <0 122 0>; | |
| 539 | + dmas = <&pdma1 7>, <&pdma1 6>; | |
| 540 | + dma-names = "tx", "rx"; | |
| 541 | + #address-cells = <1>; | |
| 542 | + #size-cells = <0>; | |
| 543 | + clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; | |
| 544 | + clock-names = "spi", "spi_busclk0"; | |
| 545 | + samsung,spi-src-clk = <0>; | |
| 546 | + pinctrl-names = "default"; | |
| 547 | + pinctrl-0 = <&spi1_bus>; | |
| 548 | + status = "disabled"; | |
| 549 | + }; | |
| 550 | + | |
| 551 | + spi_2: spi@13940000 { | |
| 552 | + compatible = "samsung,exynos4210-spi"; | |
| 553 | + reg = <0x13940000 0x100>; | |
| 554 | + interrupts = <0 123 0>; | |
| 555 | + dmas = <&pdma0 9>, <&pdma0 8>; | |
| 556 | + dma-names = "tx", "rx"; | |
| 557 | + #address-cells = <1>; | |
| 558 | + #size-cells = <0>; | |
| 559 | + clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; | |
| 560 | + clock-names = "spi", "spi_busclk0"; | |
| 561 | + samsung,spi-src-clk = <0>; | |
| 562 | + pinctrl-names = "default"; | |
| 563 | + pinctrl-0 = <&spi2_bus>; | |
| 564 | + status = "disabled"; | |
| 565 | + }; | |
| 566 | + | |
| 567 | + clock_audss: clock-controller@03810000 { | |
| 568 | + compatible = "samsung,exynos4210-audss-clock"; | |
| 569 | + reg = <0x03810000 0x0C>; | |
| 570 | + #clock-cells = <1>; | |
| 571 | + }; | |
| 572 | + | |
| 573 | + i2s0: i2s@3830000 { | |
| 574 | + compatible = "samsung,s5pv210-i2s"; | |
| 575 | + reg = <0x03830000 0x100>; | |
| 576 | + interrupts = <0 124 0>; | |
| 577 | + clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
| 578 | + <&clock_audss EXYNOS_SCLK_I2S>; | |
| 579 | + clock-names = "iis", "i2s_opclk0"; | |
| 580 | + dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; | |
| 581 | + dma-names = "tx", "rx", "tx-sec"; | |
| 582 | + pinctrl-names = "default"; | |
| 583 | + pinctrl-0 = <&i2s0_bus>; | |
| 584 | + samsung,idma-addr = <0x03000000>; | |
| 585 | + status = "disabled"; | |
| 586 | + }; | |
| 587 | + | |
| 588 | + pwm: pwm@139D0000 { | |
| 589 | + compatible = "samsung,exynos4210-pwm"; | |
| 590 | + reg = <0x139D0000 0x1000>; | |
| 591 | + interrupts = <0 104 0>, <0 105 0>, <0 106 0>, | |
| 592 | + <0 107 0>, <0 108 0>; | |
| 593 | + #pwm-cells = <3>; | |
| 594 | + status = "disabled"; | |
| 595 | + }; | |
| 596 | + | |
| 597 | + pmu { | |
| 598 | + compatible = "arm,cortex-a9-pmu"; | |
| 599 | + interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; | |
| 600 | + }; | |
| 601 | + }; | |
| 602 | +}; | |
| 603 | + | |
| 604 | +#include "exynos4415-pinctrl.dtsi" | |
| @@ -12,6 +12,22 @@ · 11 unmodified lines | ||
| 12 | 12 | * published by the Free Software Foundation. |
| 13 | 13 | */ |
| 14 | 14 | |
| 15 | +#define PIN_PULL_NONE 0 | |
| 16 | +#define PIN_PULL_DOWN 1 | |
| 17 | +#define PIN_PULL_UP 3 | |
| 18 | + | |
| 19 | +#define PIN_PDN_OUT0 0 | |
| 20 | +#define PIN_PDN_OUT1 1 | |
| 21 | +#define PIN_PDN_INPUT 2 | |
| 22 | +#define PIN_PDN_PREV 3 | |
| 23 | + | |
| 24 | +#define PIN_SLP(_pin, _mode, _pull) \ | |
| 25 | + _pin { \ | |
| 26 | + samsung,pins = #_pin; \ | |
| 27 | + samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \ | |
| 28 | + samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \ | |
| 29 | + } | |
| 30 | + | |
| 15 | 31 | / { |
| 16 | 32 | pinctrl@11400000 { |
| 17 | 33 | gpa0: gpa0 { |
| @@ -271,4 +271,14 @@ · 270 unmodified lines | ||
| 271 | 271 | compatible = "samsung,exynos4x12-usb2-phy"; |
| 272 | 272 | samsung,sysreg-phandle = <&sys_reg>; |
| 273 | 273 | }; |
| 274 | + | |
| 275 | + tmu@100C0000 { | |
| 276 | + compatible = "samsung,exynos4412-tmu"; | |
| 277 | + interrupt-parent = <&combiner>; | |
| 278 | + interrupts = <2 4>; | |
| 279 | + reg = <0x100C0000 0x100>; | |
| 280 | + clocks = <&clock 383>; | |
| 281 | + clock-names = "tmu_apbif"; | |
| 282 | + status = "disabled"; | |
| 283 | + }; | |
| 274 | 284 | }; |
| @@ -7,12 +7,13 @@ · 6 unmodified lines | ||
| 7 | 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | 9 | * published by the Free Software Foundation. |
| 10 | −*/ | |
| 10 | + */ | |
| 11 | 11 | |
| 12 | 12 | /dts-v1/; |
| 13 | −#include "exynos5250.dtsi" | |
| 13 | +#include <dt-bindings/gpio/gpio.h> | |
| 14 | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | 15 | #include <dt-bindings/input/input.h> |
| 16 | +#include "exynos5250.dtsi" | |
| 16 | 17 | |
| 17 | 18 | / { |
| 18 | 19 | model = "Insignal Arndale evaluation board based on EXYNOS5250"; |
| @@ -26,465 +27,52 @@ · 7 unmodified lines | ||
| 26 | 27 | bootargs = "console=ttySAC2,115200"; |
| 27 | 28 | }; |
| 28 | 29 | |
| 29 | − rtc@101E0000 { | |
| 30 | − status = "okay"; | |
| 31 | − }; | |
| 32 | − | |
| 33 | − codec@11000000 { | |
| 34 | − samsung,mfc-r = <0x43000000 0x800000>; | |
| 35 | − samsung,mfc-l = <0x51000000 0x800000>; | |
| 36 | − }; | |
| 37 | − | |
| 38 | − i2c@12C60000 { | |
| 39 | − samsung,i2c-sda-delay = <100>; | |
| 40 | − samsung,i2c-max-bus-freq = <20000>; | |
| 41 | − samsung,i2c-slave-addr = <0x66>; | |
| 42 | − status = "okay"; | |
| 43 | − | |
| 44 | − s5m8767_pmic@66 { | |
| 45 | − compatible = "samsung,s5m8767-pmic"; | |
| 46 | − reg = <0x66>; | |
| 47 | − interrupt-parent = <&gpx3>; | |
| 48 | − interrupts = <2 IRQ_TYPE_LEVEL_LOW>; | |
| 49 | − | |
| 50 | − vinb1-supply = <&main_dc_reg>; | |
| 51 | − vinb2-supply = <&main_dc_reg>; | |
| 52 | − vinb3-supply = <&main_dc_reg>; | |
| 53 | − vinb4-supply = <&main_dc_reg>; | |
| 54 | − vinb5-supply = <&main_dc_reg>; | |
| 55 | − vinb6-supply = <&main_dc_reg>; | |
| 56 | − vinb7-supply = <&main_dc_reg>; | |
| 57 | − vinb8-supply = <&main_dc_reg>; | |
| 58 | − vinb9-supply = <&main_dc_reg>; | |
| 59 | − | |
| 60 | − vinl1-supply = <&buck7_reg>; | |
| 61 | − vinl2-supply = <&buck7_reg>; | |
| 62 | − vinl3-supply = <&buck7_reg>; | |
| 63 | − vinl4-supply = <&main_dc_reg>; | |
| 64 | − vinl5-supply = <&main_dc_reg>; | |
| 65 | − vinl6-supply = <&main_dc_reg>; | |
| 66 | − vinl7-supply = <&main_dc_reg>; | |
| 67 | − vinl8-supply = <&buck8_reg>; | |
| 68 | − vinl9-supply = <&buck8_reg>; | |
| 69 | − | |
| 70 | − s5m8767,pmic-buck2-dvs-voltage = <1300000>; | |
| 71 | − s5m8767,pmic-buck3-dvs-voltage = <1100000>; | |
| 72 | − s5m8767,pmic-buck4-dvs-voltage = <1200000>; | |
| 73 | − s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>, | |
| 74 | − <&gpd1 1 0>, | |
| 75 | − <&gpd1 2 0>; | |
| 76 | − s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>, | |
| 77 | − <&gpx2 4 0>, | |
| 78 | − <&gpx2 5 0>; | |
| 79 | − regulators { | |
| 80 | − ldo1_reg: LDO1 { | |
| 81 | − regulator-name = "VDD_ALIVE_1.0V"; | |
| 82 | − regulator-min-microvolt = <1100000>; | |
| 83 | − regulator-max-microvolt = <1100000>; | |
| 84 | − regulator-always-on; | |
| 85 | − regulator-boot-on; | |
| 86 | − op_mode = <1>; | |
| 87 | − }; | |
| 88 | − | |
| 89 | − ldo2_reg: LDO2 { | |
| 90 | − regulator-name = "VDD_28IO_DP_1.35V"; | |
| 91 | − regulator-min-microvolt = <1200000>; | |
| 92 | − regulator-max-microvolt = <1200000>; | |
| 93 | − regulator-always-on; | |
| 94 | − regulator-boot-on; | |
| 95 | − op_mode = <1>; | |
| 96 | − }; | |
| 97 | − | |
| 98 | − ldo3_reg: LDO3 { | |
| 99 | − regulator-name = "VDD_COMMON1_1.8V"; | |
| 100 | − regulator-min-microvolt = <1800000>; | |
| 101 | − regulator-max-microvolt = <1800000>; | |
| 102 | − regulator-always-on; | |
| 103 | − regulator-boot-on; | |
| 104 | − op_mode = <1>; | |
| 105 | − }; | |
| 106 | − | |
| 107 | − ldo4_reg: LDO4 { | |
| 108 | − regulator-name = "VDD_IOPERI_1.8V"; | |
| 109 | − regulator-min-microvolt = <1800000>; | |
| 110 | − regulator-max-microvolt = <1800000>; | |
| 111 | − regulator-always-on; | |
| 112 | − op_mode = <1>; | |
| 113 | − }; | |
| 114 | − | |
| 115 | − ldo5_reg: LDO5 { | |
| 116 | − regulator-name = "VDD_EXT_1.8V"; | |
| 117 | − regulator-min-microvolt = <1800000>; | |
| 118 | − regulator-max-microvolt = <1800000>; | |
| 119 | − regulator-always-on; | |
| 120 | − regulator-boot-on; | |
| 121 | − op_mode = <1>; | |
| 122 | − }; | |
| 123 | − | |
| 124 | − ldo6_reg: LDO6 { | |
| 125 | − regulator-name = "VDD_MPLL_1.1V"; | |
| 126 | − regulator-min-microvolt = <1100000>; | |
| 127 | − regulator-max-microvolt = <1100000>; | |
| 128 | − regulator-always-on; | |
| 129 | − regulator-boot-on; | |
| 130 | − op_mode = <1>; | |
| 131 | − }; | |
| 132 | − | |
| 133 | − ldo7_reg: LDO7 { | |
| 134 | − regulator-name = "VDD_XPLL_1.1V"; | |
| 135 | − regulator-min-microvolt = <1100000>; | |
| 136 | − regulator-max-microvolt = <1100000>; | |
| 137 | − regulator-always-on; | |
| 138 | − regulator-boot-on; | |
| 139 | − op_mode = <1>; | |
| 140 | − }; | |
| 141 | − | |
| 142 | − ldo8_reg: LDO8 { | |
| 143 | − regulator-name = "VDD_COMMON2_1.0V"; | |
| 144 | − regulator-min-microvolt = <1000000>; | |
| 145 | − regulator-max-microvolt = <1000000>; | |
| 146 | − regulator-always-on; | |
| 147 | − regulator-boot-on; | |
| 148 | − op_mode = <1>; | |
| 149 | − }; | |
| 150 | − | |
| 151 | − ldo9_reg: LDO9 { | |
| 152 | − regulator-name = "VDD_33ON_3.0V"; | |
| 153 | − regulator-min-microvolt = <3000000>; | |
| 154 | − regulator-max-microvolt = <3000000>; | |
| 155 | − op_mode = <1>; | |
| 156 | − }; | |
| 157 | − | |
| 158 | − ldo10_reg: LDO10 { | |
| 159 | − regulator-name = "VDD_COMMON3_1.8V"; | |
| 160 | − regulator-min-microvolt = <1800000>; | |
| 161 | − regulator-max-microvolt = <1800000>; | |
| 162 | − regulator-always-on; | |
| 163 | − regulator-boot-on; | |
| 164 | − op_mode = <1>; | |
| 165 | − }; | |
| 166 | − | |
| 167 | − ldo11_reg: LDO11 { | |
| 168 | − regulator-name = "VDD_ABB2_1.8V"; | |
| 169 | − regulator-min-microvolt = <1800000>; | |
| 170 | − regulator-max-microvolt = <1800000>; | |
| 171 | − regulator-always-on; | |
| 172 | − regulator-boot-on; | |
| 173 | − op_mode = <1>; | |
| 174 | − }; | |
| 175 | − | |
| 176 | − ldo12_reg: LDO12 { | |
| 177 | − regulator-name = "VDD_USB_3.0V"; | |
| 178 | − regulator-min-microvolt = <3000000>; | |
| 179 | − regulator-max-microvolt = <3000000>; | |
| 180 | − regulator-always-on; | |
| 181 | − regulator-boot-on; | |
| 182 | − op_mode = <1>; | |
| 183 | − }; | |
| 184 | − | |
| 185 | − ldo13_reg: LDO13 { | |
| 186 | − regulator-name = "VDDQ_C2C_W_1.8V"; | |
| 187 | − regulator-min-microvolt = <1800000>; | |
| 188 | − regulator-max-microvolt = <1800000>; | |
| 189 | − regulator-always-on; | |
| 190 | − regulator-boot-on; | |
| 191 | − op_mode = <1>; | |
| 192 | − }; | |
| 193 | − | |
| 194 | − ldo14_reg: LDO14 { | |
| 195 | − regulator-name = "VDD18_ABB0_3_1.8V"; | |
| 196 | − regulator-min-microvolt = <1800000>; | |
| 197 | − regulator-max-microvolt = <1800000>; | |
| 198 | − regulator-always-on; | |
| 199 | − regulator-boot-on; | |
| 200 | − op_mode = <1>; | |
| 201 | − }; | |
| 202 | − | |
| 203 | − ldo15_reg: LDO15 { | |
| 204 | − regulator-name = "VDD10_COMMON4_1.0V"; | |
| 205 | − regulator-min-microvolt = <1000000>; | |
| 206 | − regulator-max-microvolt = <1000000>; | |
| 207 | − regulator-always-on; | |
| 208 | − regulator-boot-on; | |
| 209 | − op_mode = <1>; | |
| 210 | − }; | |
| 211 | − | |
| 212 | − ldo16_reg: LDO16 { | |
| 213 | − regulator-name = "VDD18_HSIC_1.8V"; | |
| 214 | − regulator-min-microvolt = <1800000>; | |
| 215 | − regulator-max-microvolt = <1800000>; | |
| 216 | − regulator-always-on; | |
| 217 | − regulator-boot-on; | |
| 218 | − op_mode = <1>; | |
| 219 | − }; | |
| 220 | − | |
| 221 | − ldo17_reg: LDO17 { | |
| 222 | − regulator-name = "VDDQ_MMC2_3_2.8V"; | |
| 223 | − regulator-min-microvolt = <2800000>; | |
| 224 | − regulator-max-microvolt = <2800000>; | |
| 225 | − regulator-always-on; | |
| 226 | − regulator-boot-on; | |
| 227 | − op_mode = <1>; | |
| 228 | − }; | |
| 229 | − | |
| 230 | − ldo18_reg: LDO18 { | |
| 231 | − regulator-name = "VDD_33ON_2.8V"; | |
| 232 | − regulator-min-microvolt = <2800000>; | |
| 233 | − regulator-max-microvolt = <2800000>; | |
| 234 | − op_mode = <1>; | |
| 235 | − }; | |
| 236 | − | |
| 237 | − ldo22_reg: LDO22 { | |
| 238 | − regulator-name = "EXT_33_OFF"; | |
| 239 | − regulator-min-microvolt = <3300000>; | |
| 240 | − regulator-max-microvolt = <3300000>; | |
| 241 | − op_mode = <1>; | |
| 242 | − }; | |
| 243 | − | |
| 244 | − ldo23_reg: LDO23 { | |
| 245 | − regulator-name = "EXT_28_OFF"; | |
| 246 | − regulator-min-microvolt = <2800000>; | |
| 247 | − regulator-max-microvolt = <2800000>; | |
| 248 | − op_mode = <1>; | |
| 249 | − }; | |
| 250 | − | |
| 251 | − ldo25_reg: LDO25 { | |
| 252 | − regulator-name = "PVDD_LDO25"; | |
| 253 | − regulator-min-microvolt = <1200000>; | |
| 254 | − regulator-max-microvolt = <1200000>; | |
| 255 | − op_mode = <1>; | |
| 256 | − }; | |
| 257 | − | |
| 258 | − ldo26_reg: LDO26 { | |
| 259 | − regulator-name = "EXT_18_OFF"; | |
| 260 | − regulator-min-microvolt = <1800000>; | |
| 261 | − regulator-max-microvolt = <1800000>; | |
| 262 | − op_mode = <1>; | |
| 263 | − }; | |
| 264 | − | |
| 265 | − buck1_reg: BUCK1 { | |
| 266 | − regulator-name = "vdd_mif"; | |
| 267 | − regulator-min-microvolt = <950000>; | |
| 268 | − regulator-max-microvolt = <1200000>; | |
| 269 | − regulator-always-on; | |
| 270 | − regulator-boot-on; | |
| 271 | − op_mode = <1>; | |
| 272 | − }; | |
| 273 | − | |
| 274 | − buck2_reg: BUCK2 { | |
| 275 | − regulator-name = "vdd_arm"; | |
| 276 | − regulator-min-microvolt = <912500>; | |
| 277 | − regulator-max-microvolt = <1300000>; | |
| 278 | − regulator-always-on; | |
| 279 | − regulator-boot-on; | |
| 280 | − op_mode = <1>; | |
| 281 | − }; | |
| 282 | − | |
| 283 | − buck3_reg: BUCK3 { | |
| 284 | − regulator-name = "vdd_int"; | |
| 285 | − regulator-min-microvolt = <900000>; | |
| 286 | − regulator-max-microvolt = <1200000>; | |
| 287 | − regulator-always-on; | |
| 288 | − regulator-boot-on; | |
| 289 | − op_mode = <1>; | |
| 290 | − }; | |
| 291 | − | |
| 292 | − buck4_reg: BUCK4 { | |
| 293 | − regulator-name = "vdd_g3d"; | |
| 294 | − regulator-min-microvolt = <1000000>; | |
| 295 | − regulator-max-microvolt = <1000000>; | |
| 296 | − regulator-always-on; | |
| 297 | − regulator-boot-on; | |
| 298 | − op_mode = <1>; | |
| 299 | − }; | |
| 300 | − | |
| 301 | − buck5_reg: BUCK5 { | |
| 302 | − regulator-name = "VDD_MEM_1.35V"; | |
| 303 | − regulator-min-microvolt = <750000>; | |
| 304 | − regulator-max-microvolt = <1355000>; | |
| 305 | − regulator-always-on; | |
| 306 | − regulator-boot-on; | |
| 307 | − op_mode = <1>; | |
| 308 | − }; | |
| 309 | − | |
| 310 | − buck7_reg: BUCK7 { | |
| 311 | − regulator-name = "PVDD_BUCK7"; | |
| 312 | − regulator-always-on; | |
| 313 | − op_mode = <1>; | |
| 314 | − }; | |
| 315 | − | |
| 316 | − buck8_reg: BUCK8 { | |
| 317 | − regulator-name = "PVDD_BUCK8"; | |
| 318 | − regulator-always-on; | |
| 319 | − op_mode = <1>; | |
| 320 | − }; | |
| 321 | − | |
| 322 | − buck9_reg: BUCK9 { | |
| 323 | − regulator-name = "VDD_33_OFF_EXT1"; | |
| 324 | − regulator-min-microvolt = <750000>; | |
| 325 | − regulator-max-microvolt = <3000000>; | |
| 326 | − op_mode = <1>; | |
| 327 | − }; | |
| 328 | − }; | |
| 329 | − }; | |
| 330 | − }; | |
| 331 | − | |
| 332 | − i2c@12C80000 { | |
| 333 | − status = "okay"; | |
| 334 | − | |
| 335 | − samsung,i2c-sda-delay = <100>; | |
| 336 | − samsung,i2c-max-bus-freq = <66000>; | |
| 337 | − samsung,i2c-slave-addr = <0x50>; | |
| 338 | − | |
| 339 | − hdmiddc@50 { | |
| 340 | − compatible = "samsung,exynos4210-hdmiddc"; | |
| 341 | − reg = <0x50>; | |
| 342 | − }; | |
| 343 | − }; | |
| 344 | − | |
| 345 | − i2c@12C90000 { | |
| 346 | − status = "okay"; | |
| 347 | − | |
| 348 | − wm1811a@1a { | |
| 349 | − | |
| 350 | − compatible = "wlf,wm1811"; | |
| 351 | − reg = <0x1a>; | |
| 352 | − | |
| 353 | − AVDD2-supply = <&main_dc_reg>; | |
| 354 | − CPVDD-supply = <&main_dc_reg>; | |
| 355 | − DBVDD1-supply = <&main_dc_reg>; | |
| 356 | − DBVDD2-supply = <&main_dc_reg>; | |
| 357 | − DBVDD3-supply = <&main_dc_reg>; | |
| 358 | − LDO1VDD-supply = <&main_dc_reg>; | |
| 359 | − SPKVDD1-supply = <&main_dc_reg>; | |
| 360 | − SPKVDD2-supply = <&main_dc_reg>; | |
| 361 | − | |
| 362 | − wlf,ldo1ena = <&gpb0 0 0>; | |
| 363 | − wlf,ldo2ena = <&gpb0 1 0>; | |
| 364 | − }; | |
| 365 | − }; | |
| 366 | − | |
| 367 | − i2c@12CE0000 { | |
| 368 | − status = "okay"; | |
| 369 | − | |
| 370 | − samsung,i2c-sda-delay = <100>; | |
| 371 | − samsung,i2c-max-bus-freq = <66000>; | |
| 372 | − samsung,i2c-slave-addr = <0x38>; | |
| 373 | − | |
| 374 | − hdmiphy@38 { | |
| 375 | − compatible = "samsung,exynos4212-hdmiphy"; | |
| 376 | − reg = <0x38>; | |
| 377 | − }; | |
| 378 | − }; | |
| 379 | − | |
| 380 | − i2c@121D0000 { | |
| 381 | − status = "okay"; | |
| 382 | − samsung,i2c-sda-delay = <100>; | |
| 383 | − samsung,i2c-max-bus-freq = <40000>; | |
| 384 | − samsung,i2c-slave-addr = <0x38>; | |
| 385 | − | |
| 386 | − sata_phy_i2c:sata-phy@38 { | |
| 387 | − compatible = "samsung,exynos-sataphy-i2c"; | |
| 388 | − reg = <0x38>; | |
| 389 | − }; | |
| 390 | − }; | |
| 391 | − | |
| 392 | − sata@122F0000 { | |
| 393 | − status = "okay"; | |
| 394 | − }; | |
| 395 | − | |
| 396 | − sata-phy@12170000 { | |
| 397 | − status = "okay"; | |
| 398 | − samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; | |
| 399 | − }; | |
| 400 | − | |
| 401 | − mmc_0: mmc@12200000 { | |
| 402 | − status = "okay"; | |
| 403 | − num-slots = <1>; | |
| 404 | − broken-cd; | |
| 405 | − card-detect-delay = <200>; | |
| 406 | − samsung,dw-mshc-ciu-div = <3>; | |
| 407 | − samsung,dw-mshc-sdr-timing = <2 3>; | |
| 408 | − samsung,dw-mshc-ddr-timing = <1 2>; | |
| 409 | − vmmc-supply = <&mmc_reg>; | |
| 410 | − pinctrl-names = "default"; | |
| 411 | − pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; | |
| 412 | − bus-width = <8>; | |
| 413 | − cap-mmc-highspeed; | |
| 414 | − }; | |
| 415 | − | |
| 416 | − mmc_2: mmc@12220000 { | |
| 417 | − status = "okay"; | |
| 418 | − num-slots = <1>; | |
| 419 | − card-detect-delay = <200>; | |
| 420 | − samsung,dw-mshc-ciu-div = <3>; | |
| 421 | − samsung,dw-mshc-sdr-timing = <2 3>; | |
| 422 | − samsung,dw-mshc-ddr-timing = <1 2>; | |
| 423 | − vmmc-supply = <&mmc_reg>; | |
| 424 | − pinctrl-names = "default"; | |
| 425 | − pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | |
| 426 | − bus-width = <4>; | |
| 427 | − disable-wp; | |
| 428 | − cap-sd-highspeed; | |
| 429 | − }; | |
| 430 | − | |
| 431 | − i2s0: i2s@03830000 { | |
| 432 | − status = "okay"; | |
| 433 | − }; | |
| 434 | − | |
| 435 | 30 | gpio_keys { |
| 436 | 31 | compatible = "gpio-keys"; |
| 437 | 32 | |
| 438 | 33 | menu { |
| 439 | 34 | label = "SW-TACT2"; |
| 440 | − gpios = <&gpx1 4 1>; | |
| 35 | + gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; | |
| 441 | 36 | linux,code = <KEY_MENU>; |
| 442 | 37 | gpio-key,wakeup; |
| 443 | 38 | }; |
| 444 | 39 | |
| 445 | 40 | home { |
| 446 | 41 | label = "SW-TACT3"; |
| 447 | − gpios = <&gpx1 5 1>; | |
| 42 | + gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; | |
| 448 | 43 | linux,code = <KEY_HOME>; |
| 449 | 44 | gpio-key,wakeup; |
| 450 | 45 | }; |
| 451 | 46 | |
| 452 | 47 | up { |
| 453 | 48 | label = "SW-TACT4"; |
| 454 | − gpios = <&gpx1 6 1>; | |
| 49 | + gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; | |
| 455 | 50 | linux,code = <KEY_UP>; |
| 456 | 51 | gpio-key,wakeup; |
| 457 | 52 | }; |
| 458 | 53 | |
| 459 | 54 | down { |
| 460 | 55 | label = "SW-TACT5"; |
| 461 | − gpios = <&gpx1 7 1>; | |
| 56 | + gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; | |
| 462 | 57 | linux,code = <KEY_DOWN>; |
| 463 | 58 | gpio-key,wakeup; |
| 464 | 59 | }; |
| 465 | 60 | |
| 466 | 61 | back { |
| 467 | 62 | label = "SW-TACT6"; |
| 468 | − gpios = <&gpx2 0 1>; | |
| 63 | + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; | |
| 469 | 64 | linux,code = <KEY_BACK>; |
| 470 | 65 | gpio-key,wakeup; |
| 471 | 66 | }; |
| 472 | 67 | |
| 473 | 68 | wakeup { |
| 474 | 69 | label = "SW-TACT7"; |
| 475 | − gpios = <&gpx2 1 1>; | |
| 70 | + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; | |
| 476 | 71 | linux,code = <KEY_WAKEUP>; |
| 477 | 72 | gpio-key,wakeup; |
| 478 | 73 | }; |
| 479 | 74 | }; |
| 480 | 75 | |
| 481 | − hdmi { | |
| 482 | − hpd-gpio = <&gpx3 7 2>; | |
| 483 | − vdd_osc-supply = <&ldo10_reg>; | |
| 484 | − vdd_pll-supply = <&ldo8_reg>; | |
| 485 | − vdd-supply = <&ldo8_reg>; | |
| 486 | − }; | |
| 487 | − | |
| 488 | 76 | regulators { |
| 489 | 77 | compatible = "simple-bus"; |
| 490 | 78 | #address-cells = <1>; |
| @@ -502,7 +90,7 @@ · 11 unmodified lines | ||
| 502 | 90 | regulator-name = "VDD_33ON_2.8V"; |
| 503 | 91 | regulator-min-microvolt = <2800000>; |
| 504 | 92 | regulator-max-microvolt = <2800000>; |
| 505 | − gpio = <&gpx1 1 1>; | |
| 93 | + gpio = <&gpx1 1 GPIO_ACTIVE_LOW>; | |
| 506 | 94 | enable-active-high; |
| 507 | 95 | }; |
| 508 | 96 | |
| @@ -520,46 +108,455 @@ · 11 unmodified lines | ||
| 520 | 108 | }; |
| 521 | 109 | }; |
| 522 | 110 | |
| 523 | − dp-controller@145B0000 { | |
| 524 | − samsung,color-space = <0>; | |
| 525 | − samsung,dynamic-range = <0>; | |
| 526 | − samsung,ycbcr-coeff = <0>; | |
| 527 | − samsung,color-depth = <1>; | |
| 528 | − samsung,link-rate = <0x0a>; | |
| 529 | − samsung,lane-count = <4>; | |
| 530 | − status = "okay"; | |
| 111 | + // SMSC USB3503 connected in hardware only mode as a PHY | |
| 112 | + usb_hub: usb-hub { | |
| 113 | + compatible = "smsc,usb3503a"; | |
| 114 | + | |
| 115 | + reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; | |
| 116 | + connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>; | |
| 531 | 117 | }; |
| 118 | +}; | |
| 532 | 119 | |
| 533 | − fimd: fimd@14400000 { | |
| 534 | − status = "okay"; | |
| 535 | − display-timings { | |
| 536 | − native-mode = <&timing0>; | |
| 537 | − timing0: timing@0 { | |
| 538 | − /* 2560x1600 DP panel */ | |
| 539 | − clock-frequency = <50000>; | |
| 540 | − hactive = <2560>; | |
| 541 | − vactive = <1600>; | |
| 542 | − hfront-porch = <48>; | |
| 543 | − hback-porch = <80>; | |
| 544 | − hsync-len = <32>; | |
| 545 | − vback-porch = <16>; | |
| 546 | − vfront-porch = <8>; | |
| 547 | − vsync-len = <6>; | |
| 548 | − }; | |
| 120 | +&dp { | |
| 121 | + status = "okay"; | |
| 122 | + samsung,color-space = <0>; | |
| 123 | + samsung,dynamic-range = <0>; | |
| 124 | + samsung,ycbcr-coeff = <0>; | |
| 125 | + samsung,color-depth = <1>; | |
| 126 | + samsung,link-rate = <0x0a>; | |
| 127 | + samsung,lane-count = <4>; | |
| 128 | +}; | |
| 129 | + | |
| 130 | +&fimd { | |
| 131 | + status = "okay"; | |
| 132 | + | |
| 133 | + display-timings { | |
| 134 | + native-mode = <&timing0>; | |
| 135 | + | |
| 136 | + timing0: timing@0 { | |
| 137 | + /* 2560x1600 DP panel */ | |
| 138 | + clock-frequency = <50000>; | |
| 139 | + hactive = <2560>; | |
| 140 | + vactive = <1600>; | |
| 141 | + hfront-porch = <48>; | |
| 142 | + hback-porch = <80>; | |
| 143 | + hsync-len = <32>; | |
| 144 | + vback-porch = <16>; | |
| 145 | + vfront-porch = <8>; | |
| 146 | + vsync-len = <6>; | |
| 549 | 147 | }; |
| 550 | 148 | }; |
| 149 | +}; | |
| 551 | 150 | |
| 552 | − usb_hub_bus { | |
| 553 | − compatible = "simple-bus"; | |
| 554 | − #address-cells = <1>; | |
| 555 | − #size-cells = <0>; | |
| 151 | +&hdmi { | |
| 152 | + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_LOW>; | |
| 153 | + vdd_osc-supply = <&ldo10_reg>; | |
| 154 | + vdd_pll-supply = <&ldo8_reg>; | |
| 155 | + vdd-supply = <&ldo8_reg>; | |
| 156 | +}; | |
| 157 | + | |
| 158 | +&i2c_0 { | |
| 159 | + status = "okay"; | |
| 160 | + samsung,i2c-sda-delay = <100>; | |
| 161 | + samsung,i2c-max-bus-freq = <20000>; | |
| 162 | + samsung,i2c-slave-addr = <0x66>; | |
| 163 | + | |
| 164 | + s5m8767_pmic@66 { | |
| 165 | + compatible = "samsung,s5m8767-pmic"; | |
| 166 | + reg = <0x66>; | |
| 167 | + interrupt-parent = <&gpx3>; | |
| 168 | + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; | |
| 169 | + | |
| 170 | + vinb1-supply = <&main_dc_reg>; | |
| 171 | + vinb2-supply = <&main_dc_reg>; | |
| 172 | + vinb3-supply = <&main_dc_reg>; | |
| 173 | + vinb4-supply = <&main_dc_reg>; | |
| 174 | + vinb5-supply = <&main_dc_reg>; | |
| 175 | + vinb6-supply = <&main_dc_reg>; | |
| 176 | + vinb7-supply = <&main_dc_reg>; | |
| 177 | + vinb8-supply = <&main_dc_reg>; | |
| 178 | + vinb9-supply = <&main_dc_reg>; | |
| 179 | + | |
| 180 | + vinl1-supply = <&buck7_reg>; | |
| 181 | + vinl2-supply = <&buck7_reg>; | |
| 182 | + vinl3-supply = <&buck7_reg>; | |
| 183 | + vinl4-supply = <&main_dc_reg>; | |
| 184 | + vinl5-supply = <&main_dc_reg>; | |
| 185 | + vinl6-supply = <&main_dc_reg>; | |
| 186 | + vinl7-supply = <&main_dc_reg>; | |
| 187 | + vinl8-supply = <&buck8_reg>; | |
| 188 | + vinl9-supply = <&buck8_reg>; | |
| 189 | + | |
| 190 | + s5m8767,pmic-buck2-dvs-voltage = <1300000>; | |
| 191 | + s5m8767,pmic-buck3-dvs-voltage = <1100000>; | |
| 192 | + s5m8767,pmic-buck4-dvs-voltage = <1200000>; | |
| 193 | + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, | |
| 194 | + <&gpd1 1 GPIO_ACTIVE_HIGH>, | |
| 195 | + <&gpd1 2 GPIO_ACTIVE_HIGH>; | |
| 196 | + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, | |
| 197 | + <&gpx2 4 GPIO_ACTIVE_HIGH>, | |
| 198 | + <&gpx2 5 GPIO_ACTIVE_HIGH>; | |
| 199 | + | |
| 200 | + regulators { | |
| 201 | + ldo1_reg: LDO1 { | |
| 202 | + regulator-name = "VDD_ALIVE_1.0V"; | |
| 203 | + regulator-min-microvolt = <1100000>; | |
| 204 | + regulator-max-microvolt = <1100000>; | |
| 205 | + regulator-always-on; | |
| 206 | + regulator-boot-on; | |
| 207 | + op_mode = <1>; | |
| 208 | + }; | |
| 556 | 209 | |
| 557 | − // SMSC USB3503 connected in hardware only mode as a PHY | |
| 558 | − usb_hub: usb_hub { | |
| 559 | − compatible = "smsc,usb3503a"; | |
| 210 | + ldo2_reg: LDO2 { | |
| 211 | + regulator-name = "VDD_28IO_DP_1.35V"; | |
| 212 | + regulator-min-microvolt = <1200000>; | |
| 213 | + regulator-max-microvolt = <1200000>; | |
| 214 | + regulator-always-on; | |
| 215 | + regulator-boot-on; | |
| 216 | + op_mode = <1>; | |
| 217 | + }; | |
| 218 | + | |
| 219 | + ldo3_reg: LDO3 { | |
| 220 | + regulator-name = "VDD_COMMON1_1.8V"; | |
| 221 | + regulator-min-microvolt = <1800000>; | |
| 222 | + regulator-max-microvolt = <1800000>; | |
| 223 | + regulator-always-on; | |
| 224 | + regulator-boot-on; | |
| 225 | + op_mode = <1>; | |
| 226 | + }; | |
| 227 | + | |
| 228 | + ldo4_reg: LDO4 { | |
| 229 | + regulator-name = "VDD_IOPERI_1.8V"; | |
| 230 | + regulator-min-microvolt = <1800000>; | |
| 231 | + regulator-max-microvolt = <1800000>; | |
| 232 | + regulator-always-on; | |
| 233 | + op_mode = <1>; | |
| 234 | + }; | |
| 235 | + | |
| 236 | + ldo5_reg: LDO5 { | |
| 237 | + regulator-name = "VDD_EXT_1.8V"; | |
| 238 | + regulator-min-microvolt = <1800000>; | |
| 239 | + regulator-max-microvolt = <1800000>; | |
| 240 | + regulator-always-on; | |
| 241 | + regulator-boot-on; | |
| 242 | + op_mode = <1>; | |
| 243 | + }; | |
| 244 | + | |
| 245 | + ldo6_reg: LDO6 { | |
| 246 | + regulator-name = "VDD_MPLL_1.1V"; | |
| 247 | + regulator-min-microvolt = <1100000>; | |
| 248 | + regulator-max-microvolt = <1100000>; | |
| 249 | + regulator-always-on; | |
| 250 | + regulator-boot-on; | |
| 251 | + op_mode = <1>; | |
| 252 | + }; | |
| 560 | 253 | |
| 561 | − reset-gpios = <&gpx3 5 1>; | |
| 562 | − connect-gpios = <&gpd1 7 1>; | |
| 254 | + ldo7_reg: LDO7 { | |
| 255 | + regulator-name = "VDD_XPLL_1.1V"; | |
| 256 | + regulator-min-microvolt = <1100000>; | |
| 257 | + regulator-max-microvolt = <1100000>; | |
| 258 | + regulator-always-on; | |
| 259 | + regulator-boot-on; | |
| 260 | + op_mode = <1>; | |
| 261 | + }; | |
| 262 | + | |
| 263 | + ldo8_reg: LDO8 { | |
| 264 | + regulator-name = "VDD_COMMON2_1.0V"; | |
| 265 | + regulator-min-microvolt = <1000000>; | |
| 266 | + regulator-max-microvolt = <1000000>; | |
| 267 | + regulator-always-on; | |
| 268 | + regulator-boot-on; | |
| 269 | + op_mode = <1>; | |
| 270 | + }; | |
| 271 | + | |
| 272 | + ldo9_reg: LDO9 { | |
| 273 | + regulator-name = "VDD_33ON_3.0V"; | |
| 274 | + regulator-min-microvolt = <3000000>; | |
| 275 | + regulator-max-microvolt = <3000000>; | |
| 276 | + op_mode = <1>; | |
| 277 | + }; | |
| 278 | + | |
| 279 | + ldo10_reg: LDO10 { | |
| 280 | + regulator-name = "VDD_COMMON3_1.8V"; | |
| 281 | + regulator-min-microvolt = <1800000>; | |
| 282 | + regulator-max-microvolt = <1800000>; | |
| 283 | + regulator-always-on; | |
| 284 | + regulator-boot-on; | |
| 285 | + op_mode = <1>; | |
| 286 | + }; | |
| 287 | + | |
| 288 | + ldo11_reg: LDO11 { | |
| 289 | + regulator-name = "VDD_ABB2_1.8V"; | |
| 290 | + regulator-min-microvolt = <1800000>; | |
| 291 | + regulator-max-microvolt = <1800000>; | |
| 292 | + regulator-always-on; | |
| 293 | + regulator-boot-on; | |
| 294 | + op_mode = <1>; | |
| 295 | + }; | |
| 296 | + | |
| 297 | + ldo12_reg: LDO12 { | |
| 298 | + regulator-name = "VDD_USB_3.0V"; | |
| 299 | + regulator-min-microvolt = <3000000>; | |
| 300 | + regulator-max-microvolt = <3000000>; | |
| 301 | + regulator-always-on; | |
| 302 | + regulator-boot-on; | |
| 303 | + op_mode = <1>; | |
| 304 | + }; | |
| 305 | + | |
| 306 | + ldo13_reg: LDO13 { | |
| 307 | + regulator-name = "VDDQ_C2C_W_1.8V"; | |
| 308 | + regulator-min-microvolt = <1800000>; | |
| 309 | + regulator-max-microvolt = <1800000>; | |
| 310 | + regulator-always-on; | |
| 311 | + regulator-boot-on; | |
| 312 | + op_mode = <1>; | |
| 313 | + }; | |
| 314 | + | |
| 315 | + ldo14_reg: LDO14 { | |
| 316 | + regulator-name = "VDD18_ABB0_3_1.8V"; | |
| 317 | + regulator-min-microvolt = <1800000>; | |
| 318 | + regulator-max-microvolt = <1800000>; | |
| 319 | + regulator-always-on; | |
| 320 | + regulator-boot-on; | |
| 321 | + op_mode = <1>; | |
| 322 | + }; | |
| 323 | + | |
| 324 | + ldo15_reg: LDO15 { | |
| 325 | + regulator-name = "VDD10_COMMON4_1.0V"; | |
| 326 | + regulator-min-microvolt = <1000000>; | |
| 327 | + regulator-max-microvolt = <1000000>; | |
| 328 | + regulator-always-on; | |
| 329 | + regulator-boot-on; | |
| 330 | + op_mode = <1>; | |
| 331 | + }; | |
| 332 | + | |
| 333 | + ldo16_reg: LDO16 { | |
| 334 | + regulator-name = "VDD18_HSIC_1.8V"; | |
| 335 | + regulator-min-microvolt = <1800000>; | |
| 336 | + regulator-max-microvolt = <1800000>; | |
| 337 | + regulator-always-on; | |
| 338 | + regulator-boot-on; | |
| 339 | + op_mode = <1>; | |
| 340 | + }; | |
| 341 | + | |
| 342 | + ldo17_reg: LDO17 { | |
| 343 | + regulator-name = "VDDQ_MMC2_3_2.8V"; | |
| 344 | + regulator-min-microvolt = <2800000>; | |
| 345 | + regulator-max-microvolt = <2800000>; | |
| 346 | + regulator-always-on; | |
| 347 | + regulator-boot-on; | |
| 348 | + op_mode = <1>; | |
| 349 | + }; | |
| 350 | + | |
| 351 | + ldo18_reg: LDO18 { | |
| 352 | + regulator-name = "VDD_33ON_2.8V"; | |
| 353 | + regulator-min-microvolt = <2800000>; | |
| 354 | + regulator-max-microvolt = <2800000>; | |
| 355 | + op_mode = <1>; | |
| 356 | + }; | |
| 357 | + | |
| 358 | + ldo22_reg: LDO22 { | |
| 359 | + regulator-name = "EXT_33_OFF"; | |
| 360 | + regulator-min-microvolt = <3300000>; | |
| 361 | + regulator-max-microvolt = <3300000>; | |
| 362 | + op_mode = <1>; | |
| 363 | + }; | |
| 364 | + | |
| 365 | + ldo23_reg: LDO23 { | |
| 366 | + regulator-name = "EXT_28_OFF"; | |
| 367 | + regulator-min-microvolt = <2800000>; | |
| 368 | + regulator-max-microvolt = <2800000>; | |
| 369 | + op_mode = <1>; | |
| 370 | + }; | |
| 371 | + | |
| 372 | + ldo25_reg: LDO25 { | |
| 373 | + regulator-name = "PVDD_LDO25"; | |
| 374 | + regulator-min-microvolt = <1200000>; | |
| 375 | + regulator-max-microvolt = <1200000>; | |
| 376 | + op_mode = <1>; | |
| 377 | + }; | |
| 378 | + | |
| 379 | + ldo26_reg: LDO26 { | |
| 380 | + regulator-name = "EXT_18_OFF"; | |
| 381 | + regulator-min-microvolt = <1800000>; | |
| 382 | + regulator-max-microvolt = <1800000>; | |
| 383 | + op_mode = <1>; | |
| 384 | + }; | |
| 385 | + | |
| 386 | + buck1_reg: BUCK1 { | |
| 387 | + regulator-name = "vdd_mif"; | |
| 388 | + regulator-min-microvolt = <950000>; | |
| 389 | + regulator-max-microvolt = <1200000>; | |
| 390 | + regulator-always-on; | |
| 391 | + regulator-boot-on; | |
| 392 | + op_mode = <1>; | |
| 393 | + }; | |
| 394 | + | |
| 395 | + buck2_reg: BUCK2 { | |
| 396 | + regulator-name = "vdd_arm"; | |
| 397 | + regulator-min-microvolt = <912500>; | |
| 398 | + regulator-max-microvolt = <1300000>; | |
| 399 | + regulator-always-on; | |
| 400 | + regulator-boot-on; | |
| 401 | + op_mode = <1>; | |
| 402 | + }; | |
| 403 | + | |
| 404 | + buck3_reg: BUCK3 { | |
| 405 | + regulator-name = "vdd_int"; | |
| 406 | + regulator-min-microvolt = <900000>; | |
| 407 | + regulator-max-microvolt = <1200000>; | |
| 408 | + regulator-always-on; | |
| 409 | + regulator-boot-on; | |
| 410 | + op_mode = <1>; | |
| 411 | + }; | |
| 412 | + | |
| 413 | + buck4_reg: BUCK4 { | |
| 414 | + regulator-name = "vdd_g3d"; | |
| 415 | + regulator-min-microvolt = <1000000>; | |
| 416 | + regulator-max-microvolt = <1000000>; | |
| 417 | + regulator-always-on; | |
| 418 | + regulator-boot-on; | |
| 419 | + op_mode = <1>; | |
| 420 | + }; | |
| 421 | + | |
| 422 | + buck5_reg: BUCK5 { | |
| 423 | + regulator-name = "VDD_MEM_1.35V"; | |
| 424 | + regulator-min-microvolt = <750000>; | |
| 425 | + regulator-max-microvolt = <1355000>; | |
| 426 | + regulator-always-on; | |
| 427 | + regulator-boot-on; | |
| 428 | + op_mode = <1>; | |
| 429 | + }; | |
| 430 | + | |
| 431 | + buck7_reg: BUCK7 { | |
| 432 | + regulator-name = "PVDD_BUCK7"; | |
| 433 | + regulator-always-on; | |
| 434 | + op_mode = <1>; | |
| 435 | + }; | |
| 436 | + | |
| 437 | + buck8_reg: BUCK8 { | |
| 438 | + regulator-name = "PVDD_BUCK8"; | |
| 439 | + regulator-always-on; | |
| 440 | + op_mode = <1>; | |
| 441 | + }; | |
| 442 | + | |
| 443 | + buck9_reg: BUCK9 { | |
| 444 | + regulator-name = "VDD_33_OFF_EXT1"; | |
| 445 | + regulator-min-microvolt = <750000>; | |
| 446 | + regulator-max-microvolt = <3000000>; | |
| 447 | + op_mode = <1>; | |
| 448 | + }; | |
| 563 | 449 | }; |
| 564 | 450 | }; |
| 565 | 451 | }; |
| 452 | + | |
| 453 | +&i2c_2 { | |
| 454 | + status = "okay"; | |
| 455 | + | |
| 456 | + samsung,i2c-sda-delay = <100>; | |
| 457 | + samsung,i2c-max-bus-freq = <66000>; | |
| 458 | + samsung,i2c-slave-addr = <0x50>; | |
| 459 | + | |
| 460 | + hdmiddc@50 { | |
| 461 | + compatible = "samsung,exynos4210-hdmiddc"; | |
| 462 | + reg = <0x50>; | |
| 463 | + }; | |
| 464 | +}; | |
| 465 | + | |
| 466 | +&i2c_3 { | |
| 467 | + status = "okay"; | |
| 468 | + | |
| 469 | + wm1811a@1a { | |
| 470 | + compatible = "wlf,wm1811"; | |
| 471 | + reg = <0x1a>; | |
| 472 | + | |
| 473 | + AVDD2-supply = <&main_dc_reg>; | |
| 474 | + CPVDD-supply = <&main_dc_reg>; | |
| 475 | + DBVDD1-supply = <&main_dc_reg>; | |
| 476 | + DBVDD2-supply = <&main_dc_reg>; | |
| 477 | + DBVDD3-supply = <&main_dc_reg>; | |
| 478 | + LDO1VDD-supply = <&main_dc_reg>; | |
| 479 | + SPKVDD1-supply = <&main_dc_reg>; | |
| 480 | + SPKVDD2-supply = <&main_dc_reg>; | |
| 481 | + | |
| 482 | + wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>; | |
| 483 | + wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>; | |
| 484 | + }; | |
| 485 | +}; | |
| 486 | + | |
| 487 | +&i2c_8 { | |
| 488 | + status = "okay"; | |
| 489 | + | |
| 490 | + samsung,i2c-sda-delay = <100>; | |
| 491 | + samsung,i2c-max-bus-freq = <66000>; | |
| 492 | + samsung,i2c-slave-addr = <0x38>; | |
| 493 | + | |
| 494 | + hdmiphy@38 { | |
| 495 | + compatible = "samsung,exynos4212-hdmiphy"; | |
| 496 | + reg = <0x38>; | |
| 497 | + }; | |
| 498 | +}; | |
| 499 | + | |
| 500 | +&i2c_9 { | |
| 501 | + status = "okay"; | |
| 502 | + samsung,i2c-sda-delay = <100>; | |
| 503 | + samsung,i2c-max-bus-freq = <40000>; | |
| 504 | + samsung,i2c-slave-addr = <0x38>; | |
| 505 | + | |
| 506 | + sata_phy_i2c:sata-phy@38 { | |
| 507 | + compatible = "samsung,exynos-sataphy-i2c"; | |
| 508 | + reg = <0x38>; | |
| 509 | + }; | |
| 510 | +}; | |
| 511 | + | |
| 512 | +&i2s0 { | |
| 513 | + status = "okay"; | |
| 514 | +}; | |
| 515 | + | |
| 516 | +&mfc { | |
| 517 | + samsung,mfc-r = <0x43000000 0x800000>; | |
| 518 | + samsung,mfc-l = <0x51000000 0x800000>; | |
| 519 | +}; | |
| 520 | + | |
| 521 | +&mmc_0 { | |
| 522 | + status = "okay"; | |
| 523 | + num-slots = <1>; | |
| 524 | + broken-cd; | |
| 525 | + card-detect-delay = <200>; | |
| 526 | + samsung,dw-mshc-ciu-div = <3>; | |
| 527 | + samsung,dw-mshc-sdr-timing = <2 3>; | |
| 528 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 529 | + vmmc-supply = <&mmc_reg>; | |
| 530 | + pinctrl-names = "default"; | |
| 531 | + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; | |
| 532 | + bus-width = <8>; | |
| 533 | + cap-mmc-highspeed; | |
| 534 | +}; | |
| 535 | + | |
| 536 | +&mmc_2 { | |
| 537 | + status = "okay"; | |
| 538 | + num-slots = <1>; | |
| 539 | + card-detect-delay = <200>; | |
| 540 | + samsung,dw-mshc-ciu-div = <3>; | |
| 541 | + samsung,dw-mshc-sdr-timing = <2 3>; | |
| 542 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 543 | + vmmc-supply = <&mmc_reg>; | |
| 544 | + pinctrl-names = "default"; | |
| 545 | + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | |
| 546 | + bus-width = <4>; | |
| 547 | + disable-wp; | |
| 548 | + cap-sd-highspeed; | |
| 549 | +}; | |
| 550 | + | |
| 551 | +&rtc { | |
| 552 | + status = "okay"; | |
| 553 | +}; | |
| 554 | + | |
| 555 | +&sata { | |
| 556 | + status = "okay"; | |
| 557 | +}; | |
| 558 | + | |
| 559 | +&sata_phy { | |
| 560 | + status = "okay"; | |
| 561 | + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; | |
| 562 | +}; | |
| @@ -7,9 +7,11 @@ · 6 unmodified lines | ||
| 7 | 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | 9 | * published by the Free Software Foundation. |
| 10 | −*/ | |
| 10 | + */ | |
| 11 | 11 | |
| 12 | 12 | /dts-v1/; |
| 13 | +#include <dt-bindings/gpio/gpio.h> | |
| 14 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 13 | 15 | #include "exynos5250.dtsi" |
| 14 | 16 | |
| 15 | 17 | / { |
| @@ -27,165 +29,6 @@ · 11 unmodified lines | ||
| 27 | 29 | bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; |
| 28 | 30 | }; |
| 29 | 31 | |
| 30 | − rtc@101E0000 { | |
| 31 | − status = "okay"; | |
| 32 | − }; | |
| 33 | − | |
| 34 | − i2c@12C60000 { | |
| 35 | − samsung,i2c-sda-delay = <100>; | |
| 36 | − samsung,i2c-max-bus-freq = <20000>; | |
| 37 | − status = "okay"; | |
| 38 | − | |
| 39 | − eeprom@50 { | |
| 40 | − compatible = "samsung,s524ad0xd1"; | |
| 41 | − reg = <0x50>; | |
| 42 | − }; | |
| 43 | − | |
| 44 | − max77686@09 { | |
| 45 | − compatible = "maxim,max77686"; | |
| 46 | − reg = <0x09>; | |
| 47 | − interrupt-parent = <&gpx3>; | |
| 48 | − interrupts = <2 0>; | |
| 49 | − | |
| 50 | − voltage-regulators { | |
| 51 | − ldo1_reg: LDO1 { | |
| 52 | − regulator-name = "P1.0V_LDO_OUT1"; | |
| 53 | − regulator-min-microvolt = <1000000>; | |
| 54 | − regulator-max-microvolt = <1000000>; | |
| 55 | − regulator-always-on; | |
| 56 | − }; | |
| 57 | − | |
| 58 | − ldo2_reg: LDO2 { | |
| 59 | − regulator-name = "P1.2V_LDO_OUT2"; | |
| 60 | − regulator-min-microvolt = <1200000>; | |
| 61 | − regulator-max-microvolt = <1200000>; | |
| 62 | − regulator-always-on; | |
| 63 | − }; | |
| 64 | − | |
| 65 | − ldo3_reg: LDO3 { | |
| 66 | − regulator-name = "P1.8V_LDO_OUT3"; | |
| 67 | − regulator-min-microvolt = <1800000>; | |
| 68 | − regulator-max-microvolt = <1800000>; | |
| 69 | − regulator-always-on; | |
| 70 | − }; | |
| 71 | − | |
| 72 | − ldo4_reg: LDO4 { | |
| 73 | − regulator-name = "P2.8V_LDO_OUT4"; | |
| 74 | − regulator-min-microvolt = <2800000>; | |
| 75 | − regulator-max-microvolt = <2800000>; | |
| 76 | − }; | |
| 77 | − | |
| 78 | − ldo5_reg: LDO5 { | |
| 79 | − regulator-name = "P1.8V_LDO_OUT5"; | |
| 80 | − regulator-min-microvolt = <1800000>; | |
| 81 | − regulator-max-microvolt = <1800000>; | |
| 82 | − }; | |
| 83 | − | |
| 84 | − ldo6_reg: LDO6 { | |
| 85 | − regulator-name = "P1.1V_LDO_OUT6"; | |
| 86 | − regulator-min-microvolt = <1100000>; | |
| 87 | − regulator-max-microvolt = <1100000>; | |
| 88 | − regulator-always-on; | |
| 89 | − }; | |
| 90 | − | |
| 91 | − ldo7_reg: LDO7 { | |
| 92 | − regulator-name = "P1.1V_LDO_OUT7"; | |
| 93 | − regulator-min-microvolt = <1100000>; | |
| 94 | − regulator-max-microvolt = <1100000>; | |
| 95 | − regulator-always-on; | |
| 96 | − }; | |
| 97 | − | |
| 98 | − ldo8_reg: LDO8 { | |
| 99 | − regulator-name = "P1.0V_LDO_OUT8"; | |
| 100 | − regulator-min-microvolt = <1000000>; | |
| 101 | − regulator-max-microvolt = <1000000>; | |
| 102 | − }; | |
| 103 | − | |
| 104 | − ldo10_reg: LDO10 { | |
| 105 | − regulator-name = "P1.8V_LDO_OUT10"; | |
| 106 | − regulator-min-microvolt = <1800000>; | |
| 107 | − regulator-max-microvolt = <1800000>; | |
| 108 | − }; | |
| 109 | − | |
| 110 | − ldo11_reg: LDO11 { | |
| 111 | − regulator-name = "P1.8V_LDO_OUT11"; | |
| 112 | − regulator-min-microvolt = <1800000>; | |
| 113 | − regulator-max-microvolt = <1800000>; | |
| 114 | − }; | |
| 115 | − | |
| 116 | − ldo12_reg: LDO12 { | |
| 117 | − regulator-name = "P3.0V_LDO_OUT12"; | |
| 118 | − regulator-min-microvolt = <3000000>; | |
| 119 | − regulator-max-microvolt = <3000000>; | |
| 120 | − }; | |
| 121 | − | |
| 122 | − ldo13_reg: LDO13 { | |
| 123 | − regulator-name = "P1.8V_LDO_OUT13"; | |
| 124 | − regulator-min-microvolt = <1800000>; | |
| 125 | − regulator-max-microvolt = <1800000>; | |
| 126 | − }; | |
| 127 | − | |
| 128 | − ldo14_reg: LDO14 { | |
| 129 | − regulator-name = "P1.8V_LDO_OUT14"; | |
| 130 | − regulator-min-microvolt = <1800000>; | |
| 131 | − regulator-max-microvolt = <1800000>; | |
| 132 | − }; | |
| 133 | − | |
| 134 | − ldo15_reg: LDO15 { | |
| 135 | − regulator-name = "P1.0V_LDO_OUT15"; | |
| 136 | − regulator-min-microvolt = <1000000>; | |
| 137 | − regulator-max-microvolt = <1000000>; | |
| 138 | − }; | |
| 139 | − | |
| 140 | − ldo16_reg: LDO16 { | |
| 141 | − regulator-name = "P1.8V_LDO_OUT16"; | |
| 142 | − regulator-min-microvolt = <1800000>; | |
| 143 | − regulator-max-microvolt = <1800000>; | |
| 144 | − }; | |
| 145 | − | |
| 146 | − buck1_reg: BUCK1 { | |
| 147 | − regulator-name = "vdd_mif"; | |
| 148 | − regulator-min-microvolt = <950000>; | |
| 149 | − regulator-max-microvolt = <1300000>; | |
| 150 | − regulator-always-on; | |
| 151 | − regulator-boot-on; | |
| 152 | − }; | |
| 153 | − | |
| 154 | − buck2_reg: BUCK2 { | |
| 155 | − regulator-name = "vdd_arm"; | |
| 156 | − regulator-min-microvolt = <850000>; | |
| 157 | − regulator-max-microvolt = <1350000>; | |
| 158 | − regulator-always-on; | |
| 159 | − regulator-boot-on; | |
| 160 | − }; | |
| 161 | − | |
| 162 | − buck3_reg: BUCK3 { | |
| 163 | − regulator-name = "vdd_int"; | |
| 164 | − regulator-min-microvolt = <900000>; | |
| 165 | − regulator-max-microvolt = <1200000>; | |
| 166 | − regulator-always-on; | |
| 167 | − regulator-boot-on; | |
| 168 | − }; | |
| 169 | − | |
| 170 | − buck4_reg: BUCK4 { | |
| 171 | − regulator-name = "vdd_g3d"; | |
| 172 | − regulator-min-microvolt = <850000>; | |
| 173 | − regulator-max-microvolt = <1300000>; | |
| 174 | − regulator-always-on; | |
| 175 | − regulator-boot-on; | |
| 176 | − }; | |
| 177 | − | |
| 178 | − buck5_reg: BUCK5 { | |
| 179 | − regulator-name = "P1.8V_BUCK_OUT5"; | |
| 180 | − regulator-min-microvolt = <1800000>; | |
| 181 | − regulator-max-microvolt = <1800000>; | |
| 182 | − regulator-always-on; | |
| 183 | − regulator-boot-on; | |
| 184 | − }; | |
| 185 | − }; | |
| 186 | − }; | |
| 187 | − }; | |
| 188 | − | |
| 189 | 32 | vdd: fixed-regulator@0 { |
| 190 | 33 | compatible = "regulator-fixed"; |
| 191 | 34 | regulator-name = "vdd-supply"; |
| @@ -210,199 +53,360 @@ · 18 unmodified lines | ||
| 210 | 53 | regulator-always-on; |
| 211 | 54 | }; |
| 212 | 55 | |
| 213 | − i2c@12C70000 { | |
| 214 | − samsung,i2c-sda-delay = <100>; | |
| 215 | − samsung,i2c-max-bus-freq = <20000>; | |
| 216 | − status = "okay"; | |
| 56 | + sound { | |
| 57 | + compatible = "samsung,smdk-wm8994"; | |
| 217 | 58 | |
| 218 | − eeprom@51 { | |
| 219 | − compatible = "samsung,s524ad0xd1"; | |
| 220 | − reg = <0x51>; | |
| 59 | + samsung,i2s-controller = <&i2s0>; | |
| 60 | + samsung,audio-codec = <&wm8994>; | |
| 61 | + }; | |
| 62 | + | |
| 63 | + fixed-rate-clocks { | |
| 64 | + xxti { | |
| 65 | + compatible = "samsung,clock-xxti"; | |
| 66 | + clock-frequency = <24000000>; | |
| 221 | 67 | }; |
| 222 | 68 | |
| 223 | − wm8994: wm8994@1a { | |
| 224 | − compatible = "wlf,wm8994"; | |
| 225 | − reg = <0x1a>; | |
| 69 | + codec_mclk: codec-mclk { | |
| 70 | + compatible = "fixed-clock"; | |
| 71 | + #clock-cells = <0>; | |
| 72 | + clock-frequency = <16934000>; | |
| 73 | + }; | |
| 74 | + }; | |
| 75 | +}; | |
| 226 | 76 | |
| 227 | − gpio-controller; | |
| 228 | − #gpio-cells = <2>; | |
| 77 | +&dp { | |
| 78 | + samsung,color-space = <0>; | |
| 79 | + samsung,dynamic-range = <0>; | |
| 80 | + samsung,ycbcr-coeff = <0>; | |
| 81 | + samsung,color-depth = <1>; | |
| 82 | + samsung,link-rate = <0x0a>; | |
| 83 | + samsung,lane-count = <4>; | |
| 84 | + | |
| 85 | + pinctrl-names = "default"; | |
| 86 | + pinctrl-0 = <&dp_hpd>; | |
| 87 | + status = "okay"; | |
| 88 | +}; | |
| 229 | 89 | |
| 230 | − clocks = <&codec_mclk>; | |
| 231 | − clock-names = "MCLK1"; | |
| 90 | +&ehci { | |
| 91 | + samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; | |
| 92 | +}; | |
| 232 | 93 | |
| 233 | − AVDD2-supply = <&vdd>; | |
| 234 | − CPVDD-supply = <&vdd>; | |
| 235 | − DBVDD-supply = <&dbvdd>; | |
| 236 | − SPKVDD1-supply = <&spkvdd>; | |
| 237 | − SPKVDD2-supply = <&spkvdd>; | |
| 94 | +&fimd { | |
| 95 | + status = "okay"; | |
| 96 | + | |
| 97 | + display-timings { | |
| 98 | + native-mode = <&timing0>; | |
| 99 | + | |
| 100 | + timing0: timing@0 { | |
| 101 | + /* 1280x800 */ | |
| 102 | + clock-frequency = <50000>; | |
| 103 | + hactive = <1280>; | |
| 104 | + vactive = <800>; | |
| 105 | + hfront-porch = <4>; | |
| 106 | + hback-porch = <4>; | |
| 107 | + hsync-len = <4>; | |
| 108 | + vback-porch = <4>; | |
| 109 | + vfront-porch = <4>; | |
| 110 | + vsync-len = <4>; | |
| 238 | 111 | }; |
| 239 | 112 | }; |
| 113 | +}; | |
| 240 | 114 | |
| 241 | − i2c@121D0000 { | |
| 242 | − samsung,i2c-sda-delay = <100>; | |
| 243 | − samsung,i2c-max-bus-freq = <40000>; | |
| 244 | − samsung,i2c-slave-addr = <0x38>; | |
| 245 | − status = "okay"; | |
| 115 | +&hdmi { | |
| 116 | + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | |
| 117 | +}; | |
| 246 | 118 | |
| 247 | − sata_phy_i2c:sata-phy@38 { | |
| 248 | − compatible = "samsung,exynos-sataphy-i2c"; | |
| 249 | − reg = <0x38>; | |
| 250 | − }; | |
| 119 | +&i2c_0 { | |
| 120 | + status = "okay"; | |
| 121 | + samsung,i2c-sda-delay = <100>; | |
| 122 | + samsung,i2c-max-bus-freq = <20000>; | |
| 123 | + | |
| 124 | + eeprom@50 { | |
| 125 | + compatible = "samsung,s524ad0xd1"; | |
| 126 | + reg = <0x50>; | |
| 251 | 127 | }; |
| 252 | 128 | |
| 253 | − i2c@12C80000 { | |
| 254 | − samsung,i2c-sda-delay = <100>; | |
| 255 | − samsung,i2c-max-bus-freq = <66000>; | |
| 256 | − status = "okay"; | |
| 129 | + max77686@09 { | |
| 130 | + compatible = "maxim,max77686"; | |
| 131 | + reg = <0x09>; | |
| 132 | + interrupt-parent = <&gpx3>; | |
| 133 | + interrupts = <2 IRQ_TYPE_NONE>; | |
| 134 | + | |
| 135 | + voltage-regulators { | |
| 136 | + ldo1_reg: LDO1 { | |
| 137 | + regulator-name = "P1.0V_LDO_OUT1"; | |
| 138 | + regulator-min-microvolt = <1000000>; | |
| 139 | + regulator-max-microvolt = <1000000>; | |
| 140 | + regulator-always-on; | |
| 141 | + }; | |
| 257 | 142 | |
| 258 | − hdmiddc@50 { | |
| 259 | − compatible = "samsung,exynos4210-hdmiddc"; | |
| 260 | − reg = <0x50>; | |
| 261 | − }; | |
| 262 | − }; | |
| 143 | + ldo2_reg: LDO2 { | |
| 144 | + regulator-name = "P1.2V_LDO_OUT2"; | |
| 145 | + regulator-min-microvolt = <1200000>; | |
| 146 | + regulator-max-microvolt = <1200000>; | |
| 147 | + regulator-always-on; | |
| 148 | + }; | |
| 263 | 149 | |
| 264 | − i2c@12CE0000 { | |
| 265 | − samsung,i2c-sda-delay = <100>; | |
| 266 | − samsung,i2c-max-bus-freq = <66000>; | |
| 267 | − status = "okay"; | |
| 150 | + ldo3_reg: LDO3 { | |
| 151 | + regulator-name = "P1.8V_LDO_OUT3"; | |
| 152 | + regulator-min-microvolt = <1800000>; | |
| 153 | + regulator-max-microvolt = <1800000>; | |
| 154 | + regulator-always-on; | |
| 155 | + }; | |
| 268 | 156 | |
| 269 | − hdmiphy@38 { | |
| 270 | − compatible = "samsung,exynos4212-hdmiphy"; | |
| 271 | − reg = <0x38>; | |
| 272 | − }; | |
| 273 | − }; | |
| 157 | + ldo4_reg: LDO4 { | |
| 158 | + regulator-name = "P2.8V_LDO_OUT4"; | |
| 159 | + regulator-min-microvolt = <2800000>; | |
| 160 | + regulator-max-microvolt = <2800000>; | |
| 161 | + }; | |
| 274 | 162 | |
| 275 | − sata@122F0000 { | |
| 276 | − status = "okay"; | |
| 277 | − }; | |
| 163 | + ldo5_reg: LDO5 { | |
| 164 | + regulator-name = "P1.8V_LDO_OUT5"; | |
| 165 | + regulator-min-microvolt = <1800000>; | |
| 166 | + regulator-max-microvolt = <1800000>; | |
| 167 | + }; | |
| 278 | 168 | |
| 279 | − sata-phy@12170000 { | |
| 280 | − status = "okay"; | |
| 281 | − samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; | |
| 282 | − }; | |
| 169 | + ldo6_reg: LDO6 { | |
| 170 | + regulator-name = "P1.1V_LDO_OUT6"; | |
| 171 | + regulator-min-microvolt = <1100000>; | |
| 172 | + regulator-max-microvolt = <1100000>; | |
| 173 | + regulator-always-on; | |
| 174 | + }; | |
| 283 | 175 | |
| 284 | − mmc@12200000 { | |
| 285 | − status = "okay"; | |
| 286 | − num-slots = <1>; | |
| 287 | − broken-cd; | |
| 288 | − card-detect-delay = <200>; | |
| 289 | − samsung,dw-mshc-ciu-div = <3>; | |
| 290 | − samsung,dw-mshc-sdr-timing = <2 3>; | |
| 291 | − samsung,dw-mshc-ddr-timing = <1 2>; | |
| 292 | − pinctrl-names = "default"; | |
| 293 | − pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; | |
| 294 | − bus-width = <8>; | |
| 295 | − cap-mmc-highspeed; | |
| 296 | − }; | |
| 176 | + ldo7_reg: LDO7 { | |
| 177 | + regulator-name = "P1.1V_LDO_OUT7"; | |
| 178 | + regulator-min-microvolt = <1100000>; | |
| 179 | + regulator-max-microvolt = <1100000>; | |
| 180 | + regulator-always-on; | |
| 181 | + }; | |
| 297 | 182 | |
| 298 | − mmc@12220000 { | |
| 299 | − status = "okay"; | |
| 300 | − num-slots = <1>; | |
| 301 | − card-detect-delay = <200>; | |
| 302 | − samsung,dw-mshc-ciu-div = <3>; | |
| 303 | − samsung,dw-mshc-sdr-timing = <2 3>; | |
| 304 | − samsung,dw-mshc-ddr-timing = <1 2>; | |
| 305 | − pinctrl-names = "default"; | |
| 306 | − pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | |
| 307 | − bus-width = <4>; | |
| 308 | − disable-wp; | |
| 309 | − cap-sd-highspeed; | |
| 310 | − }; | |
| 183 | + ldo8_reg: LDO8 { | |
| 184 | + regulator-name = "P1.0V_LDO_OUT8"; | |
| 185 | + regulator-min-microvolt = <1000000>; | |
| 186 | + regulator-max-microvolt = <1000000>; | |
| 187 | + }; | |
| 188 | + | |
| 189 | + ldo10_reg: LDO10 { | |
| 190 | + regulator-name = "P1.8V_LDO_OUT10"; | |
| 191 | + regulator-min-microvolt = <1800000>; | |
| 192 | + regulator-max-microvolt = <1800000>; | |
| 193 | + }; | |
| 311 | 194 | |
| 312 | − spi_1: spi@12d30000 { | |
| 313 | − cs-gpios = <&gpa2 5 0>; | |
| 314 | − status = "okay"; | |
| 195 | + ldo11_reg: LDO11 { | |
| 196 | + regulator-name = "P1.8V_LDO_OUT11"; | |
| 197 | + regulator-min-microvolt = <1800000>; | |
| 198 | + regulator-max-microvolt = <1800000>; | |
| 199 | + }; | |
| 315 | 200 | |
| 316 | − w25q80bw@0 { | |
| 317 | − #address-cells = <1>; | |
| 318 | − #size-cells = <1>; | |
| 319 | − compatible = "w25x80"; | |
| 320 | − reg = <0>; | |
| 321 | − spi-max-frequency = <1000000>; | |
| 201 | + ldo12_reg: LDO12 { | |
| 202 | + regulator-name = "P3.0V_LDO_OUT12"; | |
| 203 | + regulator-min-microvolt = <3000000>; | |
| 204 | + regulator-max-microvolt = <3000000>; | |
| 205 | + }; | |
| 322 | 206 | |
| 323 | − controller-data { | |
| 324 | − samsung,spi-feedback-delay = <0>; | |
| 207 | + ldo13_reg: LDO13 { | |
| 208 | + regulator-name = "P1.8V_LDO_OUT13"; | |
| 209 | + regulator-min-microvolt = <1800000>; | |
| 210 | + regulator-max-microvolt = <1800000>; | |
| 325 | 211 | }; |
| 326 | 212 | |
| 327 | − partition@0 { | |
| 328 | − label = "U-Boot"; | |
| 329 | − reg = <0x0 0x40000>; | |
| 330 | − read-only; | |
| 213 | + ldo14_reg: LDO14 { | |
| 214 | + regulator-name = "P1.8V_LDO_OUT14"; | |
| 215 | + regulator-min-microvolt = <1800000>; | |
| 216 | + regulator-max-microvolt = <1800000>; | |
| 331 | 217 | }; |
| 332 | 218 | |
| 333 | − partition@40000 { | |
| 334 | − label = "Kernel"; | |
| 335 | − reg = <0x40000 0xc0000>; | |
| 219 | + ldo15_reg: LDO15 { | |
| 220 | + regulator-name = "P1.0V_LDO_OUT15"; | |
| 221 | + regulator-min-microvolt = <1000000>; | |
| 222 | + regulator-max-microvolt = <1000000>; | |
| 223 | + }; | |
| 224 | + | |
| 225 | + ldo16_reg: LDO16 { | |
| 226 | + regulator-name = "P1.8V_LDO_OUT16"; | |
| 227 | + regulator-min-microvolt = <1800000>; | |
| 228 | + regulator-max-microvolt = <1800000>; | |
| 229 | + }; | |
| 230 | + | |
| 231 | + buck1_reg: BUCK1 { | |
| 232 | + regulator-name = "vdd_mif"; | |
| 233 | + regulator-min-microvolt = <950000>; | |
| 234 | + regulator-max-microvolt = <1300000>; | |
| 235 | + regulator-always-on; | |
| 236 | + regulator-boot-on; | |
| 237 | + }; | |
| 238 | + | |
| 239 | + buck2_reg: BUCK2 { | |
| 240 | + regulator-name = "vdd_arm"; | |
| 241 | + regulator-min-microvolt = <850000>; | |
| 242 | + regulator-max-microvolt = <1350000>; | |
| 243 | + regulator-always-on; | |
| 244 | + regulator-boot-on; | |
| 245 | + }; | |
| 246 | + | |
| 247 | + buck3_reg: BUCK3 { | |
| 248 | + regulator-name = "vdd_int"; | |
| 249 | + regulator-min-microvolt = <900000>; | |
| 250 | + regulator-max-microvolt = <1200000>; | |
| 251 | + regulator-always-on; | |
| 252 | + regulator-boot-on; | |
| 253 | + }; | |
| 254 | + | |
| 255 | + buck4_reg: BUCK4 { | |
| 256 | + regulator-name = "vdd_g3d"; | |
| 257 | + regulator-min-microvolt = <850000>; | |
| 258 | + regulator-max-microvolt = <1300000>; | |
| 259 | + regulator-always-on; | |
| 260 | + regulator-boot-on; | |
| 261 | + }; | |
| 262 | + | |
| 263 | + buck5_reg: BUCK5 { | |
| 264 | + regulator-name = "P1.8V_BUCK_OUT5"; | |
| 265 | + regulator-min-microvolt = <1800000>; | |
| 266 | + regulator-max-microvolt = <1800000>; | |
| 267 | + regulator-always-on; | |
| 268 | + regulator-boot-on; | |
| 336 | 269 | }; |
| 337 | 270 | }; |
| 338 | 271 | }; |
| 272 | +}; | |
| 339 | 273 | |
| 340 | − hdmi { | |
| 341 | − hpd-gpio = <&gpx3 7 0>; | |
| 342 | − }; | |
| 274 | +&i2c_1 { | |
| 275 | + status = "okay"; | |
| 276 | + samsung,i2c-sda-delay = <100>; | |
| 277 | + samsung,i2c-max-bus-freq = <20000>; | |
| 343 | 278 | |
| 344 | − codec@11000000 { | |
| 345 | − samsung,mfc-r = <0x43000000 0x800000>; | |
| 346 | − samsung,mfc-l = <0x51000000 0x800000>; | |
| 279 | + eeprom@51 { | |
| 280 | + compatible = "samsung,s524ad0xd1"; | |
| 281 | + reg = <0x51>; | |
| 347 | 282 | }; |
| 348 | 283 | |
| 349 | − i2s0: i2s@03830000 { | |
| 350 | − status = "okay"; | |
| 284 | + wm8994: wm8994@1a { | |
| 285 | + compatible = "wlf,wm8994"; | |
| 286 | + reg = <0x1a>; | |
| 287 | + | |
| 288 | + gpio-controller; | |
| 289 | + #gpio-cells = <2>; | |
| 290 | + | |
| 291 | + clocks = <&codec_mclk>; | |
| 292 | + clock-names = "MCLK1"; | |
| 293 | + | |
| 294 | + AVDD2-supply = <&vdd>; | |
| 295 | + CPVDD-supply = <&vdd>; | |
| 296 | + DBVDD-supply = <&dbvdd>; | |
| 297 | + SPKVDD1-supply = <&spkvdd>; | |
| 298 | + SPKVDD2-supply = <&spkvdd>; | |
| 351 | 299 | }; |
| 300 | +}; | |
| 352 | 301 | |
| 353 | − sound { | |
| 354 | − compatible = "samsung,smdk-wm8994"; | |
| 302 | +&i2c_2 { | |
| 303 | + status = "okay"; | |
| 304 | + samsung,i2c-sda-delay = <100>; | |
| 305 | + samsung,i2c-max-bus-freq = <66000>; | |
| 355 | 306 | |
| 356 | − samsung,i2s-controller = <&i2s0>; | |
| 357 | − samsung,audio-codec = <&wm8994>; | |
| 307 | + hdmiddc@50 { | |
| 308 | + compatible = "samsung,exynos4210-hdmiddc"; | |
| 309 | + reg = <0x50>; | |
| 358 | 310 | }; |
| 311 | +}; | |
| 312 | + | |
| 313 | +&i2c_8 { | |
| 314 | + status = "okay"; | |
| 315 | + samsung,i2c-sda-delay = <100>; | |
| 316 | + samsung,i2c-max-bus-freq = <66000>; | |
| 359 | 317 | |
| 360 | − usb@12110000 { | |
| 361 | − samsung,vbus-gpio = <&gpx2 6 0>; | |
| 318 | + hdmiphy@38 { | |
| 319 | + compatible = "samsung,exynos4212-hdmiphy"; | |
| 320 | + reg = <0x38>; | |
| 362 | 321 | }; |
| 322 | +}; | |
| 323 | + | |
| 324 | +&i2c_9 { | |
| 325 | + status = "okay"; | |
| 326 | + samsung,i2c-sda-delay = <100>; | |
| 327 | + samsung,i2c-max-bus-freq = <40000>; | |
| 328 | + samsung,i2c-slave-addr = <0x38>; | |
| 363 | 329 | |
| 364 | − dp-controller@145B0000 { | |
| 365 | − samsung,color-space = <0>; | |
| 366 | − samsung,dynamic-range = <0>; | |
| 367 | − samsung,ycbcr-coeff = <0>; | |
| 368 | − samsung,color-depth = <1>; | |
| 369 | − samsung,link-rate = <0x0a>; | |
| 370 | − samsung,lane-count = <4>; | |
| 371 | − | |
| 372 | − pinctrl-names = "default"; | |
| 373 | − pinctrl-0 = <&dp_hpd>; | |
| 374 | − status = "okay"; | |
| 330 | + sata_phy_i2c: sata-phy@38 { | |
| 331 | + compatible = "samsung,exynos-sataphy-i2c"; | |
| 332 | + reg = <0x38>; | |
| 375 | 333 | }; |
| 334 | +}; | |
| 376 | 335 | |
| 377 | − fimd@14400000 { | |
| 378 | − status = "okay"; | |
| 379 | − display-timings { | |
| 380 | − native-mode = <&timing0>; | |
| 381 | − timing0: timing@0 { | |
| 382 | − /* 1280x800 */ | |
| 383 | − clock-frequency = <50000>; | |
| 384 | − hactive = <1280>; | |
| 385 | − vactive = <800>; | |
| 386 | − hfront-porch = <4>; | |
| 387 | − hback-porch = <4>; | |
| 388 | − hsync-len = <4>; | |
| 389 | − vback-porch = <4>; | |
| 390 | − vfront-porch = <4>; | |
| 391 | − vsync-len = <4>; | |
| 392 | − }; | |
| 336 | +&i2s0 { | |
| 337 | + status = "okay"; | |
| 338 | +}; | |
| 339 | + | |
| 340 | +&mfc { | |
| 341 | + samsung,mfc-r = <0x43000000 0x800000>; | |
| 342 | + samsung,mfc-l = <0x51000000 0x800000>; | |
| 343 | +}; | |
| 344 | + | |
| 345 | +&mmc_0 { | |
| 346 | + status = "okay"; | |
| 347 | + num-slots = <1>; | |
| 348 | + broken-cd; | |
| 349 | + card-detect-delay = <200>; | |
| 350 | + samsung,dw-mshc-ciu-div = <3>; | |
| 351 | + samsung,dw-mshc-sdr-timing = <2 3>; | |
| 352 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 353 | + pinctrl-names = "default"; | |
| 354 | + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; | |
| 355 | + bus-width = <8>; | |
| 356 | + cap-mmc-highspeed; | |
| 357 | +}; | |
| 358 | + | |
| 359 | +&mmc_2 { | |
| 360 | + status = "okay"; | |
| 361 | + num-slots = <1>; | |
| 362 | + card-detect-delay = <200>; | |
| 363 | + samsung,dw-mshc-ciu-div = <3>; | |
| 364 | + samsung,dw-mshc-sdr-timing = <2 3>; | |
| 365 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 366 | + pinctrl-names = "default"; | |
| 367 | + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | |
| 368 | + bus-width = <4>; | |
| 369 | + disable-wp; | |
| 370 | + cap-sd-highspeed; | |
| 371 | +}; | |
| 372 | + | |
| 373 | +&rtc { | |
| 374 | + status = "okay"; | |
| 375 | +}; | |
| 376 | + | |
| 377 | +&sata { | |
| 378 | + status = "okay"; | |
| 379 | +}; | |
| 380 | + | |
| 381 | +&sata_phy { | |
| 382 | + status = "okay"; | |
| 383 | + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; | |
| 384 | +}; | |
| 385 | + | |
| 386 | +&spi_1 { | |
| 387 | + status = "okay"; | |
| 388 | + cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; | |
| 389 | + | |
| 390 | + w25q80bw@0 { | |
| 391 | + #address-cells = <1>; | |
| 392 | + #size-cells = <1>; | |
| 393 | + compatible = "w25x80"; | |
| 394 | + reg = <0>; | |
| 395 | + spi-max-frequency = <1000000>; | |
| 396 | + | |
| 397 | + controller-data { | |
| 398 | + samsung,spi-feedback-delay = <0>; | |
| 393 | 399 | }; |
| 394 | − }; | |
| 395 | 400 | |
| 396 | − fixed-rate-clocks { | |
| 397 | − xxti { | |
| 398 | − compatible = "samsung,clock-xxti"; | |
| 399 | − clock-frequency = <24000000>; | |
| 401 | + partition@0 { | |
| 402 | + label = "U-Boot"; | |
| 403 | + reg = <0x0 0x40000>; | |
| 404 | + read-only; | |
| 400 | 405 | }; |
| 401 | 406 | |
| 402 | − codec_mclk: codec-mclk { | |
| 403 | − compatible = "fixed-clock"; | |
| 404 | − #clock-cells = <0>; | |
| 405 | − clock-frequency = <16934000>; | |
| 407 | + partition@40000 { | |
| 408 | + label = "Kernel"; | |
| 409 | + reg = <0x40000 0xc0000>; | |
| 406 | 410 | }; |
| 407 | 411 | }; |
| 408 | 412 | }; |
| @@ -6,10 +6,13 @@ · 5 unmodified lines | ||
| 6 | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | 8 | * published by the Free Software Foundation. |
| 9 | −*/ | |
| 9 | + */ | |
| 10 | 10 | |
| 11 | 11 | /dts-v1/; |
| 12 | 12 | #include <dt-bindings/gpio/gpio.h> |
| 13 | +#include <dt-bindings/clock/maxim,max77686.h> | |
| 14 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 15 | +#include <dt-bindings/input/input.h> | |
| 13 | 16 | #include "exynos5250.dtsi" |
| 14 | 17 | |
| 15 | 18 | / { |
| @@ -25,76 +28,7 @@ · 9 unmodified lines | ||
| 25 | 28 | }; |
| 26 | 29 | |
| 27 | 30 | chosen { |
| 28 | − }; | |
| 29 | − | |
| 30 | − rtc@101E0000 { | |
| 31 | − status = "okay"; | |
| 32 | − }; | |
| 33 | − | |
| 34 | − pinctrl@11400000 { | |
| 35 | − ec_irq: ec-irq { | |
| 36 | − samsung,pins = "gpx1-6"; | |
| 37 | − samsung,pin-function = <0>; | |
| 38 | − samsung,pin-pud = <0>; | |
| 39 | − samsung,pin-drv = <0>; | |
| 40 | − }; | |
| 41 | − | |
| 42 | − sd3_clk: sd3-clk { | |
| 43 | − samsung,pin-drv = <0>; | |
| 44 | − }; | |
| 45 | − | |
| 46 | − sd3_cmd: sd3-cmd { | |
| 47 | − samsung,pin-pud = <3>; | |
| 48 | − samsung,pin-drv = <0>; | |
| 49 | − }; | |
| 50 | − | |
| 51 | − sd3_bus4: sd3-bus-width4 { | |
| 52 | − samsung,pin-drv = <0>; | |
| 53 | − }; | |
| 54 | − | |
| 55 | − max98095_en: max98095-en { | |
| 56 | − samsung,pins = "gpx1-7"; | |
| 57 | − samsung,pin-function = <0>; | |
| 58 | − samsung,pin-pud = <3>; | |
| 59 | − samsung,pin-drv = <0>; | |
| 60 | − }; | |
| 61 | − | |
| 62 | − tps65090_irq: tps65090-irq { | |
| 63 | − samsung,pins = "gpx2-6"; | |
| 64 | − samsung,pin-function = <0>; | |
| 65 | − samsung,pin-pud = <0>; | |
| 66 | − samsung,pin-drv = <0>; | |
| 67 | − }; | |
| 68 | − | |
| 69 | − usb3_vbus_en: usb3-vbus-en { | |
| 70 | − samsung,pins = "gpx2-7"; | |
| 71 | − samsung,pin-function = <1>; | |
| 72 | − samsung,pin-pud = <0>; | |
| 73 | − samsung,pin-drv = <0>; | |
| 74 | − }; | |
| 75 | − | |
| 76 | − hdmi_hpd_irq: hdmi-hpd-irq { | |
| 77 | − samsung,pins = "gpx3-7"; | |
| 78 | − samsung,pin-function = <0>; | |
| 79 | − samsung,pin-pud = <1>; | |
| 80 | − samsung,pin-drv = <0>; | |
| 81 | − }; | |
| 82 | − }; | |
| 83 | − | |
| 84 | − pinctrl@13400000 { | |
| 85 | − arb_their_claim: arb-their-claim { | |
| 86 | − samsung,pins = "gpe0-4"; | |
| 87 | − samsung,pin-function = <0>; | |
| 88 | − samsung,pin-pud = <3>; | |
| 89 | − samsung,pin-drv = <0>; | |
| 90 | − }; | |
| 91 | − | |
| 92 | − arb_our_claim: arb-our-claim { | |
| 93 | − samsung,pins = "gpf0-3"; | |
| 94 | − samsung,pin-function = <1>; | |
| 95 | − samsung,pin-pud = <0>; | |
| 96 | − samsung,pin-drv = <0>; | |
| 97 | − }; | |
| 31 | + bootargs = "console=tty1"; | |
| 98 | 32 | }; |
| 99 | 33 | |
| 100 | 34 | gpio-keys { |
| @@ -102,14 +36,14 @@ · 1 unmodified line | ||
| 102 | 36 | |
| 103 | 37 | power { |
| 104 | 38 | label = "Power"; |
| 105 | − gpios = <&gpx1 3 1>; | |
| 106 | − linux,code = <116>; /* KEY_POWER */ | |
| 39 | + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; | |
| 40 | + linux,code = <KEY_POWER>; | |
| 107 | 41 | gpio-key,wakeup; |
| 108 | 42 | }; |
| 109 | 43 | |
| 110 | 44 | lid-switch { |
| 111 | 45 | label = "Lid"; |
| 112 | − gpios = <&gpx3 5 1>; | |
| 46 | + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; | |
| 113 | 47 | linux,input-type = <5>; /* EV_SW */ |
| 114 | 48 | linux,code = <0>; /* SW_LID */ |
| 115 | 49 | debounce-interval = <1>; |
| @@ -130,8 +64,8 @@ · 14 unmodified lines | ||
| 130 | 64 | |
| 131 | 65 | i2c-parent = <&{/i2c@12CA0000}>; |
| 132 | 66 | |
| 133 | − our-claim-gpio = <&gpf0 3 1>; | |
| 134 | − their-claim-gpios = <&gpe0 4 1>; | |
| 67 | + our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; | |
| 68 | + their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; | |
| 135 | 69 | slew-delay-us = <10>; |
| 136 | 70 | wait-retry-us = <3000>; |
| 137 | 71 | wait-free-us = <50000>; |
| @@ -154,7 +88,7 @@ · 16 unmodified lines | ||
| 154 | 88 | cros_ec: embedded-controller { |
| 155 | 89 | compatible = "google,cros-ec-i2c"; |
| 156 | 90 | reg = <0x1e>; |
| 157 | − interrupts = <6 0>; | |
| 91 | + interrupts = <6 IRQ_TYPE_NONE>; | |
| 158 | 92 | interrupt-parent = <&gpx1>; |
| 159 | 93 | pinctrl-names = "default"; |
| 160 | 94 | pinctrl-0 = <&ec_irq>; |
| @@ -241,13 +175,6 @@ · 80 unmodified lines | ||
| 241 | 175 | }; |
| 242 | 176 | |
| 243 | 177 | i2c@12CD0000 { |
| 244 | − max98095: codec@11 { | |
| 245 | − compatible = "maxim,max98095"; | |
| 246 | − reg = <0x11>; | |
| 247 | − pinctrl-0 = <&max98095_en>; | |
| 248 | − pinctrl-names = "default"; | |
| 249 | − }; | |
| 250 | − | |
| 251 | 178 | ptn3460: lvds-bridge@20 { |
| 252 | 179 | compatible = "nxp,ptn3460"; |
| 253 | 180 | reg = <0x20>; |
| @@ -258,10 +185,6 @@ · 4 unmodified lines | ||
| 258 | 185 | }; |
| 259 | 186 | }; |
| 260 | 187 | |
| 261 | − i2s0: i2s@03830000 { | |
| 262 | − status = "okay"; | |
| 263 | − }; | |
| 264 | − | |
| 265 | 188 | sound { |
| 266 | 189 | compatible = "google,snow-audio-max98095"; |
| 267 | 190 | |
| @@ -275,20 +198,12 @@ · 7 unmodified lines | ||
| 275 | 198 | regulator-name = "P5.0V_USB3CON"; |
| 276 | 199 | regulator-min-microvolt = <5000000>; |
| 277 | 200 | regulator-max-microvolt = <5000000>; |
| 278 | − gpio = <&gpx2 7 0>; | |
| 201 | + gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; | |
| 279 | 202 | pinctrl-names = "default"; |
| 280 | 203 | pinctrl-0 = <&usb3_vbus_en>; |
| 281 | 204 | enable-active-high; |
| 282 | 205 | }; |
| 283 | 206 | |
| 284 | − phy@12100000 { | |
| 285 | − vbus-supply = <&usb3_vbus_reg>; | |
| 286 | − }; | |
| 287 | − | |
| 288 | − usb@12110000 { | |
| 289 | − samsung,vbus-gpio = <&gpx1 1 0>; | |
| 290 | − }; | |
| 291 | − | |
| 292 | 207 | fixed-rate-clocks { |
| 293 | 208 | xxti { |
| 294 | 209 | compatible = "samsung,clock-xxti"; |
| @@ -296,18 +211,6 @@ · 1 unmodified line | ||
| 296 | 211 | }; |
| 297 | 212 | }; |
| 298 | 213 | |
| 299 | − hdmi { | |
| 300 | − hpd-gpio = <&gpx3 7 0>; | |
| 301 | − pinctrl-names = "default"; | |
| 302 | − pinctrl-0 = <&hdmi_hpd_irq>; | |
| 303 | − phy = <&hdmiphy>; | |
| 304 | − ddc = <&i2c_2>; | |
| 305 | − hdmi-en-supply = <&tps65090_fet7>; | |
| 306 | − vdd-supply = <&ldo8_reg>; | |
| 307 | − vdd_osc-supply = <&ldo10_reg>; | |
| 308 | − vdd_pll-supply = <&ldo8_reg>; | |
| 309 | − }; | |
| 310 | − | |
| 311 | 214 | backlight: backlight { |
| 312 | 215 | compatible = "pwm-backlight"; |
| 313 | 216 | pwms = <&pwm 0 1000000 0>; |
| @@ -319,30 +222,46 @@ · 5 unmodified lines | ||
| 319 | 222 | pinctrl-names = "default"; |
| 320 | 223 | }; |
| 321 | 224 | |
| 322 | − fimd@14400000 { | |
| 323 | − status = "okay"; | |
| 324 | − samsung,invert-vclk; | |
| 325 | − }; | |
| 326 | − | |
| 327 | 225 | panel: panel { |
| 328 | 226 | compatible = "auo,b116xw03"; |
| 329 | 227 | power-supply = <&fet6>; |
| 330 | 228 | backlight = <&backlight>; |
| 331 | 229 | }; |
| 230 | +}; | |
| 332 | 231 | |
| 333 | − dp-controller@145B0000 { | |
| 334 | − status = "okay"; | |
| 335 | − pinctrl-names = "default"; | |
| 336 | − pinctrl-0 = <&dp_hpd>; | |
| 337 | − samsung,color-space = <0>; | |
| 338 | − samsung,dynamic-range = <0>; | |
| 339 | − samsung,ycbcr-coeff = <0>; | |
| 340 | − samsung,color-depth = <1>; | |
| 341 | − samsung,link-rate = <0x0a>; | |
| 342 | − samsung,lane-count = <2>; | |
| 343 | − samsung,hpd-gpio = <&gpx0 7 0>; | |
| 344 | − bridge = <&ptn3460>; | |
| 345 | − }; | |
| 232 | +&dp { | |
| 233 | + status = "okay"; | |
| 234 | + pinctrl-names = "default"; | |
| 235 | + pinctrl-0 = <&dp_hpd>; | |
| 236 | + samsung,color-space = <0>; | |
| 237 | + samsung,dynamic-range = <0>; | |
| 238 | + samsung,ycbcr-coeff = <0>; | |
| 239 | + samsung,color-depth = <1>; | |
| 240 | + samsung,link-rate = <0x0a>; | |
| 241 | + samsung,lane-count = <2>; | |
| 242 | + samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; | |
| 243 | + bridge = <&ptn3460>; | |
| 244 | +}; | |
| 245 | + | |
| 246 | +&ehci { | |
| 247 | + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; | |
| 248 | +}; | |
| 249 | + | |
| 250 | +&fimd { | |
| 251 | + status = "okay"; | |
| 252 | + samsung,invert-vclk; | |
| 253 | +}; | |
| 254 | + | |
| 255 | +&hdmi { | |
| 256 | + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | |
| 257 | + pinctrl-names = "default"; | |
| 258 | + pinctrl-0 = <&hdmi_hpd_irq>; | |
| 259 | + phy = <&hdmiphy>; | |
| 260 | + ddc = <&i2c_2>; | |
| 261 | + hdmi-en-supply = <&tps65090_fet7>; | |
| 262 | + vdd-supply = <&ldo8_reg>; | |
| 263 | + vdd_osc-supply = <&ldo10_reg>; | |
| 264 | + vdd_pll-supply = <&ldo8_reg>; | |
| 346 | 265 | }; |
| 347 | 266 | |
| 348 | 267 | &i2c_0 { |
| @@ -350,10 +269,10 @@ · 1 unmodified line | ||
| 350 | 269 | samsung,i2c-sda-delay = <100>; |
| 351 | 270 | samsung,i2c-max-bus-freq = <378000>; |
| 352 | 271 | |
| 353 | − max77686@09 { | |
| 272 | + max77686: max77686@09 { | |
| 354 | 273 | compatible = "maxim,max77686"; |
| 355 | 274 | interrupt-parent = <&gpx3>; |
| 356 | − interrupts = <2 0>; | |
| 275 | + interrupts = <2 IRQ_TYPE_NONE>; | |
| 357 | 276 | pinctrl-names = "default"; |
| 358 | 277 | pinctrl-0 = <&max77686_irq>; |
| 359 | 278 | wakeup-source; |
| @@ -503,7 +422,7 @@ · 143 unmodified lines | ||
| 503 | 422 | trackpad { |
| 504 | 423 | reg = <0x67>; |
| 505 | 424 | compatible = "cypress,cyapa"; |
| 506 | − interrupts = <2 0>; | |
| 425 | + interrupts = <2 IRQ_TYPE_NONE>; | |
| 507 | 426 | interrupt-parent = <&gpx1>; |
| 508 | 427 | wakeup-source; |
| 509 | 428 | }; |
| @@ -550,6 +469,13 @@ · 40 unmodified lines | ||
| 550 | 469 | status = "okay"; |
| 551 | 470 | samsung,i2c-sda-delay = <100>; |
| 552 | 471 | samsung,i2c-max-bus-freq = <66000>; |
| 472 | + | |
| 473 | + max98095: codec@11 { | |
| 474 | + compatible = "maxim,max98095"; | |
| 475 | + reg = <0x11>; | |
| 476 | + pinctrl-0 = <&max98095_en>; | |
| 477 | + pinctrl-names = "default"; | |
| 478 | + }; | |
| 553 | 479 | }; |
| 554 | 480 | |
| 555 | 481 | &i2c_8 { |
| @@ -563,6 +489,10 @@ · 7 unmodified lines | ||
| 563 | 489 | }; |
| 564 | 490 | }; |
| 565 | 491 | |
| 492 | +&i2s0 { | |
| 493 | + status = "okay"; | |
| 494 | +}; | |
| 495 | + | |
| 566 | 496 | &mmc_0 { |
| 567 | 497 | status = "okay"; |
| 568 | 498 | num-slots = <1>; |
| @@ -587,7 +517,7 @@ · 18 unmodified lines | ||
| 587 | 517 | pinctrl-names = "default"; |
| 588 | 518 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; |
| 589 | 519 | bus-width = <4>; |
| 590 | − wp-gpios = <&gpc2 1 0>; | |
| 520 | + wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; | |
| 591 | 521 | cap-sd-highspeed; |
| 592 | 522 | }; |
| 593 | 523 | |
| @@ -610,12 +540,82 @@ · 16 unmodified lines | ||
| 610 | 540 | }; |
| 611 | 541 | |
| 612 | 542 | &pinctrl_0 { |
| 543 | + ec_irq: ec-irq { | |
| 544 | + samsung,pins = "gpx1-6"; | |
| 545 | + samsung,pin-function = <0>; | |
| 546 | + samsung,pin-pud = <0>; | |
| 547 | + samsung,pin-drv = <0>; | |
| 548 | + }; | |
| 549 | + | |
| 550 | + max98095_en: max98095-en { | |
| 551 | + samsung,pins = "gpx1-7"; | |
| 552 | + samsung,pin-function = <0>; | |
| 553 | + samsung,pin-pud = <3>; | |
| 554 | + samsung,pin-drv = <0>; | |
| 555 | + }; | |
| 556 | + | |
| 557 | + tps65090_irq: tps65090-irq { | |
| 558 | + samsung,pins = "gpx2-6"; | |
| 559 | + samsung,pin-function = <0>; | |
| 560 | + samsung,pin-pud = <0>; | |
| 561 | + samsung,pin-drv = <0>; | |
| 562 | + }; | |
| 563 | + | |
| 564 | + usb3_vbus_en: usb3-vbus-en { | |
| 565 | + samsung,pins = "gpx2-7"; | |
| 566 | + samsung,pin-function = <1>; | |
| 567 | + samsung,pin-pud = <0>; | |
| 568 | + samsung,pin-drv = <0>; | |
| 569 | + }; | |
| 570 | + | |
| 613 | 571 | max77686_irq: max77686-irq { |
| 614 | 572 | samsung,pins = "gpx3-2"; |
| 615 | 573 | samsung,pin-function = <0>; |
| 616 | 574 | samsung,pin-pud = <0>; |
| 617 | 575 | samsung,pin-drv = <0>; |
| 618 | 576 | }; |
| 577 | + | |
| 578 | + hdmi_hpd_irq: hdmi-hpd-irq { | |
| 579 | + samsung,pins = "gpx3-7"; | |
| 580 | + samsung,pin-function = <0>; | |
| 581 | + samsung,pin-pud = <1>; | |
| 582 | + samsung,pin-drv = <0>; | |
| 583 | + }; | |
| 584 | +}; | |
| 585 | + | |
| 586 | +&pinctrl_1 { | |
| 587 | + arb_their_claim: arb-their-claim { | |
| 588 | + samsung,pins = "gpe0-4"; | |
| 589 | + samsung,pin-function = <0>; | |
| 590 | + samsung,pin-pud = <3>; | |
| 591 | + samsung,pin-drv = <0>; | |
| 592 | + }; | |
| 593 | + | |
| 594 | + arb_our_claim: arb-our-claim { | |
| 595 | + samsung,pins = "gpf0-3"; | |
| 596 | + samsung,pin-function = <1>; | |
| 597 | + samsung,pin-pud = <0>; | |
| 598 | + samsung,pin-drv = <0>; | |
| 599 | + }; | |
| 600 | +}; | |
| 601 | + | |
| 602 | +&rtc { | |
| 603 | + status = "okay"; | |
| 604 | + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; | |
| 605 | + clock-names = "rtc", "rtc_src"; | |
| 606 | +}; | |
| 607 | + | |
| 608 | +&sd3_bus4 { | |
| 609 | + samsung,pin-drv = <0>; | |
| 610 | +}; | |
| 611 | + | |
| 612 | +&sd3_clk { | |
| 613 | + samsung,pin-drv = <0>; | |
| 614 | +}; | |
| 615 | + | |
| 616 | +&sd3_cmd { | |
| 617 | + samsung,pin-pud = <3>; | |
| 618 | + samsung,pin-drv = <0>; | |
| 619 | 619 | }; |
| 620 | 620 | |
| 621 | 621 | &spi_1 { |
| @@ -624,4 +624,12 @@ · 2 unmodified lines | ||
| 624 | 624 | num-cs = <1>; |
| 625 | 625 | }; |
| 626 | 626 | |
| 627 | +&usbdrd_dwc3 { | |
| 628 | + dr_mode = "host"; | |
| 629 | +}; | |
| 630 | + | |
| 631 | +&usbdrd_phy { | |
| 632 | + vbus-supply = <&usb3_vbus_reg>; | |
| 633 | +}; | |
| 634 | + | |
| 627 | 635 | #include "cros-ec-keyboard.dtsi" |
| @@ -0,0 +1,566 @@ | ||
| 1 | +/* | |
| 2 | + * Google Spring board device tree source | |
| 3 | + * | |
| 4 | + * Copyright (c) 2013 Google, Inc | |
| 5 | + * Copyright (c) 2014 SUSE LINUX Products GmbH | |
| 6 | + * | |
| 7 | + * This program is free software; you can redistribute it and/or modify | |
| 8 | + * it under the terms of the GNU General Public License version 2 as | |
| 9 | + * published by the Free Software Foundation. | |
| 10 | + */ | |
| 11 | + | |
| 12 | +/dts-v1/; | |
| 13 | +#include <dt-bindings/gpio/gpio.h> | |
| 14 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 15 | +#include <dt-bindings/input/input.h> | |
| 16 | +#include "exynos5250.dtsi" | |
| 17 | + | |
| 18 | +/ { | |
| 19 | + model = "Google Spring"; | |
| 20 | + compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + reg = <0x40000000 0x80000000>; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + chosen { | |
| 27 | + bootargs = "console=tty1"; | |
| 28 | + }; | |
| 29 | + | |
| 30 | + gpio-keys { | |
| 31 | + compatible = "gpio-keys"; | |
| 32 | + pinctrl-names = "default"; | |
| 33 | + pinctrl-0 = <&power_key_irq>, <&lid_irq>; | |
| 34 | + | |
| 35 | + power { | |
| 36 | + label = "Power"; | |
| 37 | + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; | |
| 38 | + linux,code = <KEY_POWER>; | |
| 39 | + gpio-key,wakeup; | |
| 40 | + }; | |
| 41 | + | |
| 42 | + lid-switch { | |
| 43 | + label = "Lid"; | |
| 44 | + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; | |
| 45 | + linux,input-type = <5>; /* EV_SW */ | |
| 46 | + linux,code = <0>; /* SW_LID */ | |
| 47 | + debounce-interval = <1>; | |
| 48 | + gpio-key,wakeup; | |
| 49 | + }; | |
| 50 | + }; | |
| 51 | + | |
| 52 | + usb-hub { | |
| 53 | + compatible = "smsc,usb3503a"; | |
| 54 | + reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>; | |
| 55 | + pinctrl-names = "default"; | |
| 56 | + pinctrl-0 = <&hsic_reset>; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + fixed-rate-clocks { | |
| 60 | + xxti { | |
| 61 | + compatible = "samsung,clock-xxti"; | |
| 62 | + clock-frequency = <24000000>; | |
| 63 | + }; | |
| 64 | + }; | |
| 65 | +}; | |
| 66 | + | |
| 67 | +&dp { | |
| 68 | + status = "okay"; | |
| 69 | + pinctrl-names = "default"; | |
| 70 | + pinctrl-0 = <&dp_hpd_gpio>; | |
| 71 | + samsung,color-space = <0>; | |
| 72 | + samsung,dynamic-range = <0>; | |
| 73 | + samsung,ycbcr-coeff = <0>; | |
| 74 | + samsung,color-depth = <1>; | |
| 75 | + samsung,link-rate = <0x0a>; | |
| 76 | + samsung,lane-count = <1>; | |
| 77 | + samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>; | |
| 78 | +}; | |
| 79 | + | |
| 80 | +&ehci { | |
| 81 | + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; | |
| 82 | +}; | |
| 83 | + | |
| 84 | +&fimd { | |
| 85 | + status = "okay"; | |
| 86 | + samsung,invert-vclk; | |
| 87 | +}; | |
| 88 | + | |
| 89 | +&hdmi { | |
| 90 | + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; | |
| 91 | + pinctrl-names = "default"; | |
| 92 | + pinctrl-0 = <&hdmi_hpd_irq>; | |
| 93 | + phy = <&hdmiphy>; | |
| 94 | + ddc = <&i2c_2>; | |
| 95 | + hdmi-en-supply = <&ldo8_reg>; | |
| 96 | + vdd-supply = <&ldo8_reg>; | |
| 97 | + vdd_osc-supply = <&ldo10_reg>; | |
| 98 | + vdd_pll-supply = <&ldo8_reg>; | |
| 99 | +}; | |
| 100 | + | |
| 101 | +&i2c_0 { | |
| 102 | + status = "okay"; | |
| 103 | + samsung,i2c-sda-delay = <100>; | |
| 104 | + samsung,i2c-max-bus-freq = <378000>; | |
| 105 | + | |
| 106 | + s5m8767-pmic@66 { | |
| 107 | + compatible = "samsung,s5m8767-pmic"; | |
| 108 | + reg = <0x66>; | |
| 109 | + interrupt-parent = <&gpx3>; | |
| 110 | + interrupts = <2 IRQ_TYPE_NONE>; | |
| 111 | + pinctrl-names = "default"; | |
| 112 | + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; | |
| 113 | + wakeup-source; | |
| 114 | + | |
| 115 | + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ | |
| 116 | + <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ | |
| 117 | + <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ | |
| 118 | + | |
| 119 | + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ | |
| 120 | + <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ | |
| 121 | + <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ | |
| 122 | + | |
| 123 | + /* | |
| 124 | + * The following arrays of DVS voltages are not used, since we are | |
| 125 | + * not using GPIOs to control PMIC bucks, but they must be defined | |
| 126 | + * to please the driver. | |
| 127 | + */ | |
| 128 | + s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, | |
| 129 | + <1250000>, <1200000>, | |
| 130 | + <1150000>, <1100000>, | |
| 131 | + <1000000>, <950000>; | |
| 132 | + | |
| 133 | + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, | |
| 134 | + <1100000>, <1100000>, | |
| 135 | + <1000000>, <1000000>, | |
| 136 | + <1000000>, <1000000>; | |
| 137 | + | |
| 138 | + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, | |
| 139 | + <1200000>, <1200000>, | |
| 140 | + <1200000>, <1200000>, | |
| 141 | + <1200000>, <1200000>; | |
| 142 | + | |
| 143 | + clocks { | |
| 144 | + compatible = "samsung,s5m8767-clk"; | |
| 145 | + #clock-cells = <1>; | |
| 146 | + clock-output-names = "en32khz_ap", | |
| 147 | + "en32khz_cp", | |
| 148 | + "en32khz_bt"; | |
| 149 | + }; | |
| 150 | + | |
| 151 | + regulators { | |
| 152 | + ldo4_reg: LDO4 { | |
| 153 | + regulator-name = "P1.0V_LDO_OUT4"; | |
| 154 | + regulator-min-microvolt = <1000000>; | |
| 155 | + regulator-max-microvolt = <1000000>; | |
| 156 | + regulator-always-on; | |
| 157 | + op_mode = <0>; | |
| 158 | + }; | |
| 159 | + | |
| 160 | + ldo5_reg: LDO5 { | |
| 161 | + regulator-name = "P1.0V_LDO_OUT5"; | |
| 162 | + regulator-min-microvolt = <1000000>; | |
| 163 | + regulator-max-microvolt = <1000000>; | |
| 164 | + regulator-always-on; | |
| 165 | + op_mode = <0>; | |
| 166 | + }; | |
| 167 | + | |
| 168 | + ldo6_reg: LDO6 { | |
| 169 | + regulator-name = "vdd_mydp"; | |
| 170 | + regulator-min-microvolt = <1000000>; | |
| 171 | + regulator-max-microvolt = <1000000>; | |
| 172 | + regulator-always-on; | |
| 173 | + op_mode = <3>; | |
| 174 | + }; | |
| 175 | + | |
| 176 | + ldo7_reg: LDO7 { | |
| 177 | + regulator-name = "P1.1V_LDO_OUT7"; | |
| 178 | + regulator-min-microvolt = <1100000>; | |
| 179 | + regulator-max-microvolt = <1100000>; | |
| 180 | + regulator-always-on; | |
| 181 | + op_mode = <3>; | |
| 182 | + }; | |
| 183 | + | |
| 184 | + ldo8_reg: LDO8 { | |
| 185 | + regulator-name = "P1.0V_LDO_OUT8"; | |
| 186 | + regulator-min-microvolt = <1000000>; | |
| 187 | + regulator-max-microvolt = <1000000>; | |
| 188 | + regulator-always-on; | |
| 189 | + op_mode = <3>; | |
| 190 | + }; | |
| 191 | + | |
| 192 | + ldo10_reg: LDO10 { | |
| 193 | + regulator-name = "P1.8V_LDO_OUT10"; | |
| 194 | + regulator-min-microvolt = <1800000>; | |
| 195 | + regulator-max-microvolt = <1800000>; | |
| 196 | + regulator-always-on; | |
| 197 | + op_mode = <3>; | |
| 198 | + }; | |
| 199 | + | |
| 200 | + ldo11_reg: LDO11 { | |
| 201 | + regulator-name = "P1.8V_LDO_OUT11"; | |
| 202 | + regulator-min-microvolt = <1800000>; | |
| 203 | + regulator-max-microvolt = <1800000>; | |
| 204 | + regulator-always-on; | |
| 205 | + op_mode = <0>; | |
| 206 | + }; | |
| 207 | + | |
| 208 | + ldo12_reg: LDO12 { | |
| 209 | + regulator-name = "P3.0V_LDO_OUT12"; | |
| 210 | + regulator-min-microvolt = <3000000>; | |
| 211 | + regulator-max-microvolt = <3000000>; | |
| 212 | + regulator-always-on; | |
| 213 | + op_mode = <3>; | |
| 214 | + }; | |
| 215 | + | |
| 216 | + ldo13_reg: LDO13 { | |
| 217 | + regulator-name = "P1.8V_LDO_OUT13"; | |
| 218 | + regulator-min-microvolt = <1800000>; | |
| 219 | + regulator-max-microvolt = <1800000>; | |
| 220 | + regulator-always-on; | |
| 221 | + op_mode = <0>; | |
| 222 | + }; | |
| 223 | + | |
| 224 | + ldo14_reg: LDO14 { | |
| 225 | + regulator-name = "P1.8V_LDO_OUT14"; | |
| 226 | + regulator-min-microvolt = <1800000>; | |
| 227 | + regulator-max-microvolt = <1800000>; | |
| 228 | + regulator-always-on; | |
| 229 | + op_mode = <3>; | |
| 230 | + }; | |
| 231 | + | |
| 232 | + ldo15_reg: LDO15 { | |
| 233 | + regulator-name = "P1.0V_LDO_OUT15"; | |
| 234 | + regulator-min-microvolt = <1000000>; | |
| 235 | + regulator-max-microvolt = <1000000>; | |
| 236 | + regulator-always-on; | |
| 237 | + op_mode = <3>; | |
| 238 | + }; | |
| 239 | + | |
| 240 | + ldo16_reg: LDO16 { | |
| 241 | + regulator-name = "P1.8V_LDO_OUT16"; | |
| 242 | + regulator-min-microvolt = <1800000>; | |
| 243 | + regulator-max-microvolt = <1800000>; | |
| 244 | + regulator-always-on; | |
| 245 | + op_mode = <3>; | |
| 246 | + }; | |
| 247 | + | |
| 248 | + ldo17_reg: LDO17 { | |
| 249 | + regulator-name = "P2.8V_LDO_OUT17"; | |
| 250 | + regulator-min-microvolt = <2800000>; | |
| 251 | + regulator-max-microvolt = <2800000>; | |
| 252 | + regulator-always-on; | |
| 253 | + op_mode = <0>; | |
| 254 | + }; | |
| 255 | + | |
| 256 | + ldo25_reg: LDO25 { | |
| 257 | + regulator-name = "vdd_bridge"; | |
| 258 | + regulator-min-microvolt = <1200000>; | |
| 259 | + regulator-max-microvolt = <1200000>; | |
| 260 | + regulator-always-on; | |
| 261 | + op_mode = <1>; | |
| 262 | + }; | |
| 263 | + | |
| 264 | + buck1_reg: BUCK1 { | |
| 265 | + regulator-name = "vdd_mif"; | |
| 266 | + regulator-min-microvolt = <950000>; | |
| 267 | + regulator-max-microvolt = <1300000>; | |
| 268 | + regulator-always-on; | |
| 269 | + regulator-boot-on; | |
| 270 | + op_mode = <3>; | |
| 271 | + }; | |
| 272 | + | |
| 273 | + buck2_reg: BUCK2 { | |
| 274 | + regulator-name = "vdd_arm"; | |
| 275 | + regulator-min-microvolt = <850000>; | |
| 276 | + regulator-max-microvolt = <1350000>; | |
| 277 | + regulator-always-on; | |
| 278 | + regulator-boot-on; | |
| 279 | + op_mode = <3>; | |
| 280 | + }; | |
| 281 | + | |
| 282 | + buck3_reg: BUCK3 { | |
| 283 | + regulator-name = "vdd_int"; | |
| 284 | + regulator-min-microvolt = <900000>; | |
| 285 | + regulator-max-microvolt = <1200000>; | |
| 286 | + regulator-always-on; | |
| 287 | + regulator-boot-on; | |
| 288 | + op_mode = <3>; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + buck4_reg: BUCK4 { | |
| 292 | + regulator-name = "vdd_g3d"; | |
| 293 | + regulator-min-microvolt = <850000>; | |
| 294 | + regulator-max-microvolt = <1300000>; | |
| 295 | + regulator-boot-on; | |
| 296 | + op_mode = <3>; | |
| 297 | + }; | |
| 298 | + | |
| 299 | + buck5_reg: BUCK5 { | |
| 300 | + regulator-name = "P1.8V_BUCK_OUT5"; | |
| 301 | + regulator-min-microvolt = <1800000>; | |
| 302 | + regulator-max-microvolt = <1800000>; | |
| 303 | + regulator-always-on; | |
| 304 | + regulator-boot-on; | |
| 305 | + op_mode = <1>; | |
| 306 | + }; | |
| 307 | + | |
| 308 | + buck6_reg: BUCK6 { | |
| 309 | + regulator-name = "P1.2V_BUCK_OUT6"; | |
| 310 | + regulator-min-microvolt = <1200000>; | |
| 311 | + regulator-max-microvolt = <1200000>; | |
| 312 | + regulator-always-on; | |
| 313 | + regulator-boot-on; | |
| 314 | + op_mode = <0>; | |
| 315 | + }; | |
| 316 | + | |
| 317 | + buck9_reg: BUCK9 { | |
| 318 | + regulator-name = "vdd_ummc"; | |
| 319 | + regulator-min-microvolt = <950000>; | |
| 320 | + regulator-max-microvolt = <3000000>; | |
| 321 | + regulator-always-on; | |
| 322 | + regulator-boot-on; | |
| 323 | + op_mode = <3>; | |
| 324 | + }; | |
| 325 | + }; | |
| 326 | + }; | |
| 327 | +}; | |
| 328 | + | |
| 329 | +&i2c_1 { | |
| 330 | + status = "okay"; | |
| 331 | + samsung,i2c-sda-delay = <100>; | |
| 332 | + samsung,i2c-max-bus-freq = <378000>; | |
| 333 | + | |
| 334 | + trackpad@4b { | |
| 335 | + compatible = "atmel,maxtouch"; | |
| 336 | + reg = <0x4b>; | |
| 337 | + interrupt-parent = <&gpx1>; | |
| 338 | + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; | |
| 339 | + pinctrl-names = "default"; | |
| 340 | + pinctrl-0 = <&trackpad_irq>; | |
| 341 | + linux,gpio-keymap = <KEY_RESERVED | |
| 342 | + KEY_RESERVED | |
| 343 | + KEY_RESERVED | |
| 344 | + KEY_RESERVED | |
| 345 | + KEY_RESERVED | |
| 346 | + BTN_LEFT>; | |
| 347 | + wakeup-source; | |
| 348 | + }; | |
| 349 | +}; | |
| 350 | + | |
| 351 | +/* | |
| 352 | + * Disabled pullups since external part has its own pullups and | |
| 353 | + * double-pulling gets us out of spec in some cases. | |
| 354 | + */ | |
| 355 | +&i2c2_bus { | |
| 356 | + samsung,pin-pud = <0>; | |
| 357 | +}; | |
| 358 | + | |
| 359 | +&i2c_2 { | |
| 360 | + status = "okay"; | |
| 361 | + samsung,i2c-sda-delay = <100>; | |
| 362 | + samsung,i2c-max-bus-freq = <66000>; | |
| 363 | + | |
| 364 | + hdmiddc@50 { | |
| 365 | + compatible = "samsung,exynos4210-hdmiddc"; | |
| 366 | + reg = <0x50>; | |
| 367 | + }; | |
| 368 | +}; | |
| 369 | + | |
| 370 | +&i2c_3 { | |
| 371 | + status = "okay"; | |
| 372 | + samsung,i2c-sda-delay = <100>; | |
| 373 | + samsung,i2c-max-bus-freq = <66000>; | |
| 374 | +}; | |
| 375 | + | |
| 376 | +&i2c_4 { | |
| 377 | + status = "okay"; | |
| 378 | + samsung,i2c-sda-delay = <100>; | |
| 379 | + samsung,i2c-max-bus-freq = <66000>; | |
| 380 | + | |
| 381 | + cros_ec: embedded-controller { | |
| 382 | + compatible = "google,cros-ec-i2c"; | |
| 383 | + reg = <0x1e>; | |
| 384 | + interrupts = <6 IRQ_TYPE_NONE>; | |
| 385 | + interrupt-parent = <&gpx1>; | |
| 386 | + wakeup-source; | |
| 387 | + pinctrl-names = "default"; | |
| 388 | + pinctrl-0 = <&ec_irq>; | |
| 389 | + }; | |
| 390 | +}; | |
| 391 | + | |
| 392 | +&i2c_5 { | |
| 393 | + status = "okay"; | |
| 394 | + samsung,i2c-sda-delay = <100>; | |
| 395 | + samsung,i2c-max-bus-freq = <66000>; | |
| 396 | +}; | |
| 397 | + | |
| 398 | +&i2c_7 { | |
| 399 | + status = "okay"; | |
| 400 | + samsung,i2c-sda-delay = <100>; | |
| 401 | + samsung,i2c-max-bus-freq = <66000>; | |
| 402 | + | |
| 403 | + temperature-sensor@4c { | |
| 404 | + compatible = "gmt,g781"; | |
| 405 | + reg = <0x4c>; | |
| 406 | + }; | |
| 407 | +}; | |
| 408 | + | |
| 409 | +&i2c_8 { | |
| 410 | + status = "okay"; | |
| 411 | + samsung,i2c-sda-delay = <100>; | |
| 412 | + samsung,i2c-max-bus-freq = <378000>; | |
| 413 | + | |
| 414 | + hdmiphy: hdmiphy@38 { | |
| 415 | + compatible = "samsung,exynos4212-hdmiphy"; | |
| 416 | + reg = <0x38>; | |
| 417 | + }; | |
| 418 | +}; | |
| 419 | + | |
| 420 | +&i2s0 { | |
| 421 | + status = "okay"; | |
| 422 | +}; | |
| 423 | + | |
| 424 | +&mfc { | |
| 425 | + samsung,mfc-r = <0x43000000 0x800000>; | |
| 426 | + samsung,mfc-l = <0x51000000 0x800000>; | |
| 427 | +}; | |
| 428 | + | |
| 429 | +&mmc_0 { | |
| 430 | + status = "okay"; | |
| 431 | + num-slots = <1>; | |
| 432 | + supports-highspeed; | |
| 433 | + broken-cd; | |
| 434 | + card-detect-delay = <200>; | |
| 435 | + samsung,dw-mshc-ciu-div = <3>; | |
| 436 | + samsung,dw-mshc-sdr-timing = <2 3>; | |
| 437 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 438 | + pinctrl-names = "default"; | |
| 439 | + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; | |
| 440 | + | |
| 441 | + slot@0 { | |
| 442 | + reg = <0>; | |
| 443 | + bus-width = <8>; | |
| 444 | + }; | |
| 445 | +}; | |
| 446 | + | |
| 447 | +/* | |
| 448 | + * On Spring we've got SIP WiFi and so can keep drive strengths low to | |
| 449 | + * reduce EMI. | |
| 450 | + */ | |
| 451 | +&mmc_1 { | |
| 452 | + status = "okay"; | |
| 453 | + num-slots = <1>; | |
| 454 | + supports-highspeed; | |
| 455 | + broken-cd; | |
| 456 | + card-detect-delay = <200>; | |
| 457 | + samsung,dw-mshc-ciu-div = <3>; | |
| 458 | + samsung,dw-mshc-sdr-timing = <2 3>; | |
| 459 | + samsung,dw-mshc-ddr-timing = <1 2>; | |
| 460 | + pinctrl-names = "default"; | |
| 461 | + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; | |
| 462 | + | |
| 463 | + slot@0 { | |
| 464 | + reg = <0>; | |
| 465 | + bus-width = <4>; | |
| 466 | + }; | |
| 467 | +}; | |
| 468 | + | |
| 469 | +&pinctrl_0 { | |
| 470 | + s5m8767_dvs: s5m8767-dvs { | |
| 471 | + samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; | |
| 472 | + samsung,pin-function = <0>; | |
| 473 | + samsung,pin-pud = <1>; | |
| 474 | + samsung,pin-drv = <0>; | |
| 475 | + }; | |
| 476 | + | |
| 477 | + dp_hpd_gpio: dp-hpd-gpio { | |
| 478 | + samsung,pins = "gpc3-0"; | |
| 479 | + samsung,pin-function = <0>; | |
| 480 | + samsung,pin-pud = <3>; | |
| 481 | + samsung,pin-drv = <0>; | |
| 482 | + }; | |
| 483 | + | |
| 484 | + trackpad_irq: trackpad-irq { | |
| 485 | + samsung,pins = "gpx1-2"; | |
| 486 | + samsung,pin-function = <0xf>; | |
| 487 | + samsung,pin-pud = <0>; | |
| 488 | + samsung,pin-drv = <0>; | |
| 489 | + }; | |
| 490 | + | |
| 491 | + power_key_irq: power-key-irq { | |
| 492 | + samsung,pins = "gpx1-3"; | |
| 493 | + samsung,pin-function = <0>; | |
| 494 | + samsung,pin-pud = <0>; | |
| 495 | + samsung,pin-drv = <0>; | |
| 496 | + }; | |
| 497 | + | |
| 498 | + ec_irq: ec-irq { | |
| 499 | + samsung,pins = "gpx1-6"; | |
| 500 | + samsung,pin-function = <0>; | |
| 501 | + samsung,pin-pud = <0>; | |
| 502 | + samsung,pin-drv = <0>; | |
| 503 | + }; | |
| 504 | + | |
| 505 | + s5m8767_ds: s5m8767-ds { | |
| 506 | + samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; | |
| 507 | + samsung,pin-function = <0>; | |
| 508 | + samsung,pin-pud = <1>; | |
| 509 | + samsung,pin-drv = <0>; | |
| 510 | + }; | |
| 511 | + | |
| 512 | + s5m8767_irq: s5m8767-irq { | |
| 513 | + samsung,pins = "gpx3-2"; | |
| 514 | + samsung,pin-function = <0>; | |
| 515 | + samsung,pin-pud = <0>; | |
| 516 | + samsung,pin-drv = <0>; | |
| 517 | + }; | |
| 518 | + | |
| 519 | + lid_irq: lid-irq { | |
| 520 | + samsung,pins = "gpx3-5"; | |
| 521 | + samsung,pin-function = <0>; | |
| 522 | + samsung,pin-pud = <0>; | |
| 523 | + samsung,pin-drv = <0>; | |
| 524 | + }; | |
| 525 | + | |
| 526 | + hdmi_hpd_irq: hdmi-hpd-irq { | |
| 527 | + samsung,pins = "gpx3-7"; | |
| 528 | + samsung,pin-function = <0>; | |
| 529 | + samsung,pin-pud = <1>; | |
| 530 | + samsung,pin-drv = <0>; | |
| 531 | + }; | |
| 532 | +}; | |
| 533 | + | |
| 534 | +&pinctrl_1 { | |
| 535 | + hsic_reset: hsic-reset { | |
| 536 | + samsung,pins = "gpe1-0"; | |
| 537 | + samsung,pin-function = <1>; | |
| 538 | + samsung,pin-pud = <0>; | |
| 539 | + samsung,pin-drv = <0>; | |
| 540 | + }; | |
| 541 | +}; | |
| 542 | + | |
| 543 | +&sd1_bus4 { | |
| 544 | + samsung,pin-drv = <0>; | |
| 545 | +}; | |
| 546 | + | |
| 547 | +&sd1_cd { | |
| 548 | + samsung,pin-drv = <0>; | |
| 549 | +}; | |
| 550 | + | |
| 551 | +&sd1_clk { | |
| 552 | + samsung,pin-drv = <0>; | |
| 553 | +}; | |
| 554 | + | |
| 555 | +&sd1_cmd { | |
| 556 | + samsung,pin-pud = <3>; | |
| 557 | + samsung,pin-drv = <0>; | |
| 558 | +}; | |
| 559 | + | |
| 560 | +&spi_1 { | |
| 561 | + status = "okay"; | |
| 562 | + samsung,spi-src-clk = <0>; | |
| 563 | + num-cs = <1>; | |
| 564 | +}; | |
| 565 | + | |
| 566 | +#include "cros-ec-keyboard.dtsi" | |
| @@ -218,7 +218,7 @@ · 217 unmodified lines | ||
| 218 | 218 | clock-names = "fimg2d"; |
| 219 | 219 | }; |
| 220 | 220 | |
| 221 | − codec@11000000 { | |
| 221 | + mfc: codec@11000000 { | |
| 222 | 222 | compatible = "samsung,mfc-v6"; |
| 223 | 223 | reg = <0x11000000 0x10000>; |
| 224 | 224 | interrupts = <0 96 0>; |
| @@ -227,7 +227,7 @@ · 2 unmodified lines | ||
| 227 | 227 | clock-names = "mfc"; |
| 228 | 228 | }; |
| 229 | 229 | |
| 230 | − rtc@101E0000 { | |
| 230 | + rtc: rtc@101E0000 { | |
| 231 | 231 | clocks = <&clock CLK_RTC>; |
| 232 | 232 | clock-names = "rtc"; |
| 233 | 233 | status = "disabled"; |
| @@ -261,7 +261,7 @@ · 27 unmodified lines | ||
| 261 | 261 | clock-names = "uart", "clk_uart_baud0"; |
| 262 | 262 | }; |
| 263 | 263 | |
| 264 | − sata@122F0000 { | |
| 264 | + sata: sata@122F0000 { | |
| 265 | 265 | compatible = "snps,dwc-ahci"; |
| 266 | 266 | samsung,sata-freq = <66>; |
| 267 | 267 | reg = <0x122F0000 0x1ff>; |
| @@ -293,6 +293,7 @@ · 25 unmodified lines | ||
| 293 | 293 | clock-names = "i2c"; |
| 294 | 294 | pinctrl-names = "default"; |
| 295 | 295 | pinctrl-0 = <&i2c0_bus>; |
| 296 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 296 | 297 | status = "disabled"; |
| 297 | 298 | }; |
| 298 | 299 | |
| @@ -306,6 +307,7 @@ · 7 unmodified lines | ||
| 306 | 307 | clock-names = "i2c"; |
| 307 | 308 | pinctrl-names = "default"; |
| 308 | 309 | pinctrl-0 = <&i2c1_bus>; |
| 310 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 309 | 311 | status = "disabled"; |
| 310 | 312 | }; |
| 311 | 313 | |
| @@ -319,6 +321,7 @@ · 7 unmodified lines | ||
| 319 | 321 | clock-names = "i2c"; |
| 320 | 322 | pinctrl-names = "default"; |
| 321 | 323 | pinctrl-0 = <&i2c2_bus>; |
| 324 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 322 | 325 | status = "disabled"; |
| 323 | 326 | }; |
| 324 | 327 | |
| @@ -332,6 +335,7 @@ · 7 unmodified lines | ||
| 332 | 335 | clock-names = "i2c"; |
| 333 | 336 | pinctrl-names = "default"; |
| 334 | 337 | pinctrl-0 = <&i2c3_bus>; |
| 338 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 335 | 339 | status = "disabled"; |
| 336 | 340 | }; |
| 337 | 341 | |
| @@ -555,7 +559,7 @@ · 217 unmodified lines | ||
| 555 | 559 | #size-cells = <1>; |
| 556 | 560 | ranges; |
| 557 | 561 | |
| 558 | − dwc3 { | |
| 562 | + usbdrd_dwc3: dwc3 { | |
| 559 | 563 | compatible = "synopsys,dwc3"; |
| 560 | 564 | reg = <0x12000000 0x10000>; |
| 561 | 565 | interrupts = <0 72 0>; |
| @@ -573,7 +577,7 @@ · 11 unmodified lines | ||
| 573 | 577 | #phy-cells = <1>; |
| 574 | 578 | }; |
| 575 | 579 | |
| 576 | − usb@12110000 { | |
| 580 | + ehci: usb@12110000 { | |
| 577 | 581 | compatible = "samsung,exynos4210-ehci"; |
| 578 | 582 | reg = <0x12110000 0x100>; |
| 579 | 583 | interrupts = <0 71 0>; |
| @@ -588,7 +592,7 @@ · 8 unmodified lines | ||
| 588 | 592 | }; |
| 589 | 593 | }; |
| 590 | 594 | |
| 591 | − usb@12120000 { | |
| 595 | + ohci: usb@12120000 { | |
| 592 | 596 | compatible = "samsung,exynos4210-ohci"; |
| 593 | 597 | reg = <0x12120000 0x100>; |
| 594 | 598 | interrupts = <0 71 0>; |
| @@ -710,7 +714,7 @@ · 115 unmodified lines | ||
| 710 | 714 | clock-names = "gscl"; |
| 711 | 715 | }; |
| 712 | 716 | |
| 713 | − hdmi { | |
| 717 | + hdmi: hdmi { | |
| 714 | 718 | compatible = "samsung,exynos4212-hdmi"; |
| 715 | 719 | reg = <0x14530000 0x70000>; |
| 716 | 720 | interrupts = <0 95 0>; |
| @@ -736,14 +740,14 @@ · 19 unmodified lines | ||
| 736 | 740 | #phy-cells = <0>; |
| 737 | 741 | }; |
| 738 | 742 | |
| 739 | − dp-controller@145B0000 { | |
| 743 | + dp: dp-controller@145B0000 { | |
| 740 | 744 | clocks = <&clock CLK_DP>; |
| 741 | 745 | clock-names = "dp"; |
| 742 | 746 | phys = <&dp_phy>; |
| 743 | 747 | phy-names = "dp"; |
| 744 | 748 | }; |
| 745 | 749 | |
| 746 | − fimd@14400000 { | |
| 750 | + fimd: fimd@14400000 { | |
| 747 | 751 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
| 748 | 752 | clock-names = "sclk_fimd", "fimd"; |
| 749 | 753 | }; |
| @@ -12,6 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | #include <dt-bindings/input/input.h> |
| 13 | 13 | #include <dt-bindings/gpio/gpio.h> |
| 14 | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | +#include <dt-bindings/clock/maxim,max77802.h> | |
| 15 | 16 | #include "exynos5420.dtsi" |
| 16 | 17 | |
| 17 | 18 | / { |
| @@ -151,7 +152,7 @@ · 133 unmodified lines | ||
| 151 | 152 | status = "okay"; |
| 152 | 153 | clock-frequency = <400000>; |
| 153 | 154 | |
| 154 | − max77802-pmic@9 { | |
| 155 | + max77802: max77802-pmic@9 { | |
| 155 | 156 | compatible = "maxim,max77802"; |
| 156 | 157 | interrupt-parent = <&gpx3>; |
| 157 | 158 | interrupts = <1 IRQ_TYPE_NONE>; |
| @@ -560,7 +561,7 @@ · 402 unmodified lines | ||
| 560 | 561 | status = "okay"; |
| 561 | 562 | num-slots = <1>; |
| 562 | 563 | broken-cd; |
| 563 | − caps2-mmc-hs200-1_8v; | |
| 564 | + mmc-hs200-1_8v; | |
| 564 | 565 | cap-mmc-highspeed; |
| 565 | 566 | non-removable; |
| 566 | 567 | card-detect-delay = <200>; |
| @@ -727,6 +728,8 @@ · 160 unmodified lines | ||
| 727 | 728 | |
| 728 | 729 | &rtc { |
| 729 | 730 | status = "okay"; |
| 731 | + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; | |
| 732 | + clock-names = "rtc", "rtc_src"; | |
| 730 | 733 | }; |
| 731 | 734 | |
| 732 | 735 | &spi_2 { |
| @@ -560,6 +560,7 @@ · 559 unmodified lines | ||
| 560 | 560 | clock-names = "i2c"; |
| 561 | 561 | pinctrl-names = "default"; |
| 562 | 562 | pinctrl-0 = <&i2c0_bus>; |
| 563 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 563 | 564 | status = "disabled"; |
| 564 | 565 | }; |
| 565 | 566 | |
| @@ -573,6 +574,7 @@ · 7 unmodified lines | ||
| 573 | 574 | clock-names = "i2c"; |
| 574 | 575 | pinctrl-names = "default"; |
| 575 | 576 | pinctrl-0 = <&i2c1_bus>; |
| 577 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 576 | 578 | status = "disabled"; |
| 577 | 579 | }; |
| 578 | 580 | |
| @@ -586,6 +588,7 @@ · 7 unmodified lines | ||
| 586 | 588 | clock-names = "i2c"; |
| 587 | 589 | pinctrl-names = "default"; |
| 588 | 590 | pinctrl-0 = <&i2c2_bus>; |
| 591 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 589 | 592 | status = "disabled"; |
| 590 | 593 | }; |
| 591 | 594 | |
| @@ -599,6 +602,7 @@ · 7 unmodified lines | ||
| 599 | 602 | clock-names = "i2c"; |
| 600 | 603 | pinctrl-names = "default"; |
| 601 | 604 | pinctrl-0 = <&i2c3_bus>; |
| 605 | + samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 602 | 606 | status = "disabled"; |
| 603 | 607 | }; |
| 604 | 608 | |
| @@ -12,6 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | #include <dt-bindings/input/input.h> |
| 13 | 13 | #include <dt-bindings/gpio/gpio.h> |
| 14 | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | +#include <dt-bindings/clock/maxim,max77802.h> | |
| 15 | 16 | #include "exynos5800.dtsi" |
| 16 | 17 | |
| 17 | 18 | / { |
| @@ -150,7 +151,7 @@ · 132 unmodified lines | ||
| 150 | 151 | status = "okay"; |
| 151 | 152 | clock-frequency = <400000>; |
| 152 | 153 | |
| 153 | − max77802-pmic@9 { | |
| 154 | + max77802: max77802-pmic@9 { | |
| 154 | 155 | compatible = "maxim,max77802"; |
| 155 | 156 | interrupt-parent = <&gpx3>; |
| 156 | 157 | interrupts = <1 IRQ_TYPE_NONE>; |
| @@ -548,7 +549,7 @@ · 391 unmodified lines | ||
| 548 | 549 | status = "okay"; |
| 549 | 550 | num-slots = <1>; |
| 550 | 551 | broken-cd; |
| 551 | − caps2-mmc-hs200-1_8v; | |
| 552 | + mmc-hs200-1_8v; | |
| 552 | 553 | cap-mmc-highspeed; |
| 553 | 554 | non-removable; |
| 554 | 555 | card-detect-delay = <200>; |
| @@ -715,6 +716,8 @@ · 160 unmodified lines | ||
| 715 | 716 | |
| 716 | 717 | &rtc { |
| 717 | 718 | status = "okay"; |
| 719 | + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; | |
| 720 | + clock-names = "rtc", "rtc_src"; | |
| 718 | 721 | }; |
| 719 | 722 | |
| 720 | 723 | &spi_2 { |
| @@ -51,3 +51,36 @@ · 50 unmodified lines | ||
| 51 | 51 | &uart0 { |
| 52 | 52 | status = "okay"; |
| 53 | 53 | }; |
| 54 | + | |
| 55 | +&gmac0 { | |
| 56 | + #address-cells = <1>; | |
| 57 | + #size-cells = <0>; | |
| 58 | + phy-handle = <&phy2>; | |
| 59 | + phy-mode = "mii"; | |
| 60 | + /* Placeholder, overwritten by bootloader */ | |
| 61 | + mac-address = [00 00 00 00 00 00]; | |
| 62 | + status = "okay"; | |
| 63 | + | |
| 64 | + phy2: ethernet-phy@2 { | |
| 65 | + reg = <2>; | |
| 66 | + }; | |
| 67 | +}; | |
| 68 | + | |
| 69 | +&gmac1 { | |
| 70 | + #address-cells = <1>; | |
| 71 | + #size-cells = <0>; | |
| 72 | + phy-handle = <&phy1>; | |
| 73 | + phy-mode = "rgmii"; | |
| 74 | + /* Placeholder, overwritten by bootloader */ | |
| 75 | + mac-address = [00 00 00 00 00 00]; | |
| 76 | + status = "okay"; | |
| 77 | + | |
| 78 | + phy1: ethernet-phy@1 { | |
| 79 | + reg = <1>; | |
| 80 | + }; | |
| 81 | +}; | |
| 82 | + | |
| 83 | +&ahci { | |
| 84 | + phys = <&sata_phy>; | |
| 85 | + phy-names = "sata-phy"; | |
| 86 | +}; | |
| @@ -131,6 +131,249 @@ · 130 unmodified lines | ||
| 131 | 131 | clock-names = "apb_pclk"; |
| 132 | 132 | status = "disabled"; |
| 133 | 133 | }; |
| 134 | + | |
| 135 | + gpio0: gpio@b20000 { | |
| 136 | + compatible = "arm,pl061", "arm,primecell"; | |
| 137 | + reg = <0xb20000 0x1000>; | |
| 138 | + interrupts = <0 108 0x4>; | |
| 139 | + gpio-controller; | |
| 140 | + #gpio-cells = <2>; | |
| 141 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 142 | + clock-names = "apb_pclk"; | |
| 143 | + interrupt-controller; | |
| 144 | + #interrupt-cells = <2>; | |
| 145 | + status = "disabled"; | |
| 146 | + }; | |
| 147 | + | |
| 148 | + gpio1: gpio@b21000 { | |
| 149 | + compatible = "arm,pl061", "arm,primecell"; | |
| 150 | + reg = <0xb21000 0x1000>; | |
| 151 | + interrupts = <0 109 0x4>; | |
| 152 | + gpio-controller; | |
| 153 | + #gpio-cells = <2>; | |
| 154 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 155 | + clock-names = "apb_pclk"; | |
| 156 | + interrupt-controller; | |
| 157 | + #interrupt-cells = <2>; | |
| 158 | + status = "disabled"; | |
| 159 | + }; | |
| 160 | + | |
| 161 | + gpio2: gpio@b22000 { | |
| 162 | + compatible = "arm,pl061", "arm,primecell"; | |
| 163 | + reg = <0xb22000 0x1000>; | |
| 164 | + interrupts = <0 110 0x4>; | |
| 165 | + gpio-controller; | |
| 166 | + #gpio-cells = <2>; | |
| 167 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 168 | + clock-names = "apb_pclk"; | |
| 169 | + interrupt-controller; | |
| 170 | + #interrupt-cells = <2>; | |
| 171 | + status = "disabled"; | |
| 172 | + }; | |
| 173 | + | |
| 174 | + gpio3: gpio@b23000 { | |
| 175 | + compatible = "arm,pl061", "arm,primecell"; | |
| 176 | + reg = <0xb23000 0x1000>; | |
| 177 | + interrupts = <0 111 0x4>; | |
| 178 | + gpio-controller; | |
| 179 | + #gpio-cells = <2>; | |
| 180 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 181 | + clock-names = "apb_pclk"; | |
| 182 | + interrupt-controller; | |
| 183 | + #interrupt-cells = <2>; | |
| 184 | + status = "disabled"; | |
| 185 | + }; | |
| 186 | + | |
| 187 | + gpio4: gpio@b24000 { | |
| 188 | + compatible = "arm,pl061", "arm,primecell"; | |
| 189 | + reg = <0xb24000 0x1000>; | |
| 190 | + interrupts = <0 112 0x4>; | |
| 191 | + gpio-controller; | |
| 192 | + #gpio-cells = <2>; | |
| 193 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 194 | + clock-names = "apb_pclk"; | |
| 195 | + interrupt-controller; | |
| 196 | + #interrupt-cells = <2>; | |
| 197 | + status = "disabled"; | |
| 198 | + }; | |
| 199 | + | |
| 200 | + gpio5: gpio@004000 { | |
| 201 | + compatible = "arm,pl061", "arm,primecell"; | |
| 202 | + reg = <0x004000 0x1000>; | |
| 203 | + interrupts = <0 113 0x4>; | |
| 204 | + gpio-controller; | |
| 205 | + #gpio-cells = <2>; | |
| 206 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 207 | + clock-names = "apb_pclk"; | |
| 208 | + interrupt-controller; | |
| 209 | + #interrupt-cells = <2>; | |
| 210 | + status = "disabled"; | |
| 211 | + }; | |
| 212 | + | |
| 213 | + gpio6: gpio@b26000 { | |
| 214 | + compatible = "arm,pl061", "arm,primecell"; | |
| 215 | + reg = <0xb26000 0x1000>; | |
| 216 | + interrupts = <0 114 0x4>; | |
| 217 | + gpio-controller; | |
| 218 | + #gpio-cells = <2>; | |
| 219 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 220 | + clock-names = "apb_pclk"; | |
| 221 | + interrupt-controller; | |
| 222 | + #interrupt-cells = <2>; | |
| 223 | + status = "disabled"; | |
| 224 | + }; | |
| 225 | + | |
| 226 | + gpio7: gpio@b27000 { | |
| 227 | + compatible = "arm,pl061", "arm,primecell"; | |
| 228 | + reg = <0xb27000 0x1000>; | |
| 229 | + interrupts = <0 115 0x4>; | |
| 230 | + gpio-controller; | |
| 231 | + #gpio-cells = <2>; | |
| 232 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 233 | + clock-names = "apb_pclk"; | |
| 234 | + interrupt-controller; | |
| 235 | + #interrupt-cells = <2>; | |
| 236 | + status = "disabled"; | |
| 237 | + }; | |
| 238 | + | |
| 239 | + gpio8: gpio@b28000 { | |
| 240 | + compatible = "arm,pl061", "arm,primecell"; | |
| 241 | + reg = <0xb28000 0x1000>; | |
| 242 | + interrupts = <0 116 0x4>; | |
| 243 | + gpio-controller; | |
| 244 | + #gpio-cells = <2>; | |
| 245 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 246 | + clock-names = "apb_pclk"; | |
| 247 | + interrupt-controller; | |
| 248 | + #interrupt-cells = <2>; | |
| 249 | + status = "disabled"; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + gpio9: gpio@b29000 { | |
| 253 | + compatible = "arm,pl061", "arm,primecell"; | |
| 254 | + reg = <0xb29000 0x1000>; | |
| 255 | + interrupts = <0 117 0x4>; | |
| 256 | + gpio-controller; | |
| 257 | + #gpio-cells = <2>; | |
| 258 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 259 | + clock-names = "apb_pclk"; | |
| 260 | + interrupt-controller; | |
| 261 | + #interrupt-cells = <2>; | |
| 262 | + status = "disabled"; | |
| 263 | + }; | |
| 264 | + | |
| 265 | + gpio10: gpio@b2a000 { | |
| 266 | + compatible = "arm,pl061", "arm,primecell"; | |
| 267 | + reg = <0xb2a000 0x1000>; | |
| 268 | + interrupts = <0 118 0x4>; | |
| 269 | + gpio-controller; | |
| 270 | + #gpio-cells = <2>; | |
| 271 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 272 | + clock-names = "apb_pclk"; | |
| 273 | + interrupt-controller; | |
| 274 | + #interrupt-cells = <2>; | |
| 275 | + status = "disabled"; | |
| 276 | + }; | |
| 277 | + | |
| 278 | + gpio11: gpio@b2b000 { | |
| 279 | + compatible = "arm,pl061", "arm,primecell"; | |
| 280 | + reg = <0xb2b000 0x1000>; | |
| 281 | + interrupts = <0 119 0x4>; | |
| 282 | + gpio-controller; | |
| 283 | + #gpio-cells = <2>; | |
| 284 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 285 | + clock-names = "apb_pclk"; | |
| 286 | + interrupt-controller; | |
| 287 | + #interrupt-cells = <2>; | |
| 288 | + status = "disabled"; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + gpio12: gpio@b2c000 { | |
| 292 | + compatible = "arm,pl061", "arm,primecell"; | |
| 293 | + reg = <0xb2c000 0x1000>; | |
| 294 | + interrupts = <0 120 0x4>; | |
| 295 | + gpio-controller; | |
| 296 | + #gpio-cells = <2>; | |
| 297 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 298 | + clock-names = "apb_pclk"; | |
| 299 | + interrupt-controller; | |
| 300 | + #interrupt-cells = <2>; | |
| 301 | + status = "disabled"; | |
| 302 | + }; | |
| 303 | + | |
| 304 | + gpio13: gpio@b2d000 { | |
| 305 | + compatible = "arm,pl061", "arm,primecell"; | |
| 306 | + reg = <0xb2d000 0x1000>; | |
| 307 | + interrupts = <0 121 0x4>; | |
| 308 | + gpio-controller; | |
| 309 | + #gpio-cells = <2>; | |
| 310 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 311 | + clock-names = "apb_pclk"; | |
| 312 | + interrupt-controller; | |
| 313 | + #interrupt-cells = <2>; | |
| 314 | + status = "disabled"; | |
| 315 | + }; | |
| 316 | + | |
| 317 | + gpio14: gpio@b2e000 { | |
| 318 | + compatible = "arm,pl061", "arm,primecell"; | |
| 319 | + reg = <0xb2e000 0x1000>; | |
| 320 | + interrupts = <0 122 0x4>; | |
| 321 | + gpio-controller; | |
| 322 | + #gpio-cells = <2>; | |
| 323 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 324 | + clock-names = "apb_pclk"; | |
| 325 | + interrupt-controller; | |
| 326 | + #interrupt-cells = <2>; | |
| 327 | + status = "disabled"; | |
| 328 | + }; | |
| 329 | + | |
| 330 | + gpio15: gpio@b2f000 { | |
| 331 | + compatible = "arm,pl061", "arm,primecell"; | |
| 332 | + reg = <0xb2f000 0x1000>; | |
| 333 | + interrupts = <0 123 0x4>; | |
| 334 | + gpio-controller; | |
| 335 | + #gpio-cells = <2>; | |
| 336 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 337 | + clock-names = "apb_pclk"; | |
| 338 | + interrupt-controller; | |
| 339 | + #interrupt-cells = <2>; | |
| 340 | + status = "disabled"; | |
| 341 | + }; | |
| 342 | + | |
| 343 | + gpio16: gpio@b30000 { | |
| 344 | + compatible = "arm,pl061", "arm,primecell"; | |
| 345 | + reg = <0xb30000 0x1000>; | |
| 346 | + interrupts = <0 124 0x4>; | |
| 347 | + gpio-controller; | |
| 348 | + #gpio-cells = <2>; | |
| 349 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 350 | + clock-names = "apb_pclk"; | |
| 351 | + interrupt-controller; | |
| 352 | + #interrupt-cells = <2>; | |
| 353 | + status = "disabled"; | |
| 354 | + }; | |
| 355 | + | |
| 356 | + gpio17: gpio@b31000 { | |
| 357 | + compatible = "arm,pl061", "arm,primecell"; | |
| 358 | + reg = <0xb31000 0x1000>; | |
| 359 | + interrupts = <0 125 0x4>; | |
| 360 | + gpio-controller; | |
| 361 | + #gpio-cells = <2>; | |
| 362 | + clocks = <&clock HIX5HD2_FIXED_100M>; | |
| 363 | + clock-names = "apb_pclk"; | |
| 364 | + interrupt-controller; | |
| 365 | + #interrupt-cells = <2>; | |
| 366 | + status = "disabled"; | |
| 367 | + }; | |
| 368 | + | |
| 369 | + wdt0: watchdog@a2c000 { | |
| 370 | + compatible = "arm,sp805", "arm,primecell"; | |
| 371 | + arm,primecell-periphid = <0x00141805>; | |
| 372 | + reg = <0xa2c000 0x1000>; | |
| 373 | + interrupts = <0 29 4>; | |
| 374 | + clocks = <&clock HIX5HD2_WDG0_RST>; | |
| 375 | + clock-names = "apb_pclk"; | |
| 376 | + }; | |
| 134 | 377 | }; |
| 135 | 378 | |
| 136 | 379 | local_timer@00a00600 { |
| @@ -148,9 +391,15 @@ · 11 unmodified lines | ||
| 148 | 391 | }; |
| 149 | 392 | |
| 150 | 393 | sysctrl: system-controller@00000000 { |
| 151 | − compatible = "hisilicon,sysctrl"; | |
| 394 | + compatible = "hisilicon,sysctrl", "syscon"; | |
| 152 | 395 | reg = <0x00000000 0x1000>; |
| 153 | − reboot-offset = <0x4>; | |
| 396 | + }; | |
| 397 | + | |
| 398 | + reboot { | |
| 399 | + compatible = "syscon-reboot"; | |
| 400 | + regmap = <&sysctrl>; | |
| 401 | + offset = <0x4>; | |
| 402 | + mask = <0xdeadbeef>; | |
| 154 | 403 | }; |
| 155 | 404 | |
| 156 | 405 | cpuctrl@00a22000 { |
| @@ -166,5 +415,142 @@ · 9 unmodified lines | ||
| 166 | 415 | #clock-cells = <1>; |
| 167 | 416 | }; |
| 168 | 417 | }; |
| 418 | + | |
| 419 | + /* unremovable emmc as mmcblk0 */ | |
| 420 | + mmc: mmc@1830000 { | |
| 421 | + compatible = "snps,dw-mshc"; | |
| 422 | + reg = <0x1830000 0x1000>; | |
| 423 | + interrupts = <0 35 4>; | |
| 424 | + clocks = <&clock HIX5HD2_MMC_CIU_RST>, | |
| 425 | + <&clock HIX5HD2_MMC_BIU_CLK>; | |
| 426 | + clock-names = "ciu", "biu"; | |
| 427 | + }; | |
| 428 | + | |
| 429 | + sd: mmc@1820000 { | |
| 430 | + compatible = "snps,dw-mshc"; | |
| 431 | + reg = <0x1820000 0x1000>; | |
| 432 | + interrupts = <0 34 4>; | |
| 433 | + clocks = <&clock HIX5HD2_SD_CIU_RST>, | |
| 434 | + <&clock HIX5HD2_SD_BIU_CLK>; | |
| 435 | + clock-names = "ciu","biu"; | |
| 436 | + }; | |
| 437 | + | |
| 438 | + gmac0: ethernet@1840000 { | |
| 439 | + compatible = "hisilicon,hix5hd2-gmac"; | |
| 440 | + reg = <0x1840000 0x1000>,<0x184300c 0x4>; | |
| 441 | + interrupts = <0 71 4>; | |
| 442 | + clocks = <&clock HIX5HD2_MAC0_CLK>; | |
| 443 | + status = "disabled"; | |
| 444 | + }; | |
| 445 | + | |
| 446 | + gmac1: ethernet@1841000 { | |
| 447 | + compatible = "hisilicon,hix5hd2-gmac"; | |
| 448 | + reg = <0x1841000 0x1000>,<0x1843010 0x4>; | |
| 449 | + interrupts = <0 72 4>; | |
| 450 | + clocks = <&clock HIX5HD2_MAC1_CLK>; | |
| 451 | + status = "disabled"; | |
| 452 | + }; | |
| 453 | + | |
| 454 | + usb0: ehci@1890000 { | |
| 455 | + compatible = "generic-ehci"; | |
| 456 | + reg = <0x1890000 0x1000>; | |
| 457 | + interrupts = <0 66 4>; | |
| 458 | + clocks = <&clock HIX5HD2_USB_CLK>; | |
| 459 | + }; | |
| 460 | + | |
| 461 | + usb1: ohci@1880000 { | |
| 462 | + compatible = "generic-ohci"; | |
| 463 | + reg = <0x1880000 0x1000>; | |
| 464 | + interrupts = <0 67 4>; | |
| 465 | + clocks = <&clock HIX5HD2_USB_CLK>; | |
| 466 | + }; | |
| 467 | + | |
| 468 | + peripheral_ctrl: syscon@a20000 { | |
| 469 | + compatible = "syscon"; | |
| 470 | + reg = <0xa20000 0x1000>; | |
| 471 | + }; | |
| 472 | + | |
| 473 | + sata_phy: phy@1900000 { | |
| 474 | + compatible = "hisilicon,hix5hd2-sata-phy"; | |
| 475 | + reg = <0x1900000 0x10000>; | |
| 476 | + #phy-cells = <0>; | |
| 477 | + hisilicon,peripheral-syscon = <&peripheral_ctrl>; | |
| 478 | + hisilicon,power-reg = <0x8 10>; | |
| 479 | + }; | |
| 480 | + | |
| 481 | + ahci: sata@1900000 { | |
| 482 | + compatible = "hisilicon,hisi-ahci"; | |
| 483 | + reg = <0x1900000 0x10000>; | |
| 484 | + interrupts = <0 70 4>; | |
| 485 | + clocks = <&clock HIX5HD2_SATA_CLK>; | |
| 486 | + }; | |
| 487 | + | |
| 488 | + ir: ir@001000 { | |
| 489 | + compatible = "hisilicon,hix5hd2-ir"; | |
| 490 | + reg = <0x001000 0x1000>; | |
| 491 | + interrupts = <0 47 4>; | |
| 492 | + clocks = <&clock HIX5HD2_FIXED_24M>; | |
| 493 | + hisilicon,power-syscon = <&sysctrl>; | |
| 494 | + }; | |
| 495 | + | |
| 496 | + i2c0: i2c@b10000 { | |
| 497 | + compatible = "hisilicon,hix5hd2-i2c"; | |
| 498 | + reg = <0xb10000 0x1000>; | |
| 499 | + interrupts = <0 38 4>; | |
| 500 | + clocks = <&clock HIX5HD2_I2C0_RST>; | |
| 501 | + #address-cells = <1>; | |
| 502 | + #size-cells = <0>; | |
| 503 | + status = "disabled"; | |
| 504 | + }; | |
| 505 | + | |
| 506 | + i2c1: i2c@b11000 { | |
| 507 | + compatible = "hisilicon,hix5hd2-i2c"; | |
| 508 | + reg = <0xb11000 0x1000>; | |
| 509 | + interrupts = <0 39 4>; | |
| 510 | + clocks = <&clock HIX5HD2_I2C1_RST>; | |
| 511 | + #address-cells = <1>; | |
| 512 | + #size-cells = <0>; | |
| 513 | + status = "disabled"; | |
| 514 | + }; | |
| 515 | + | |
| 516 | + i2c2: i2c@b12000 { | |
| 517 | + compatible = "hisilicon,hix5hd2-i2c"; | |
| 518 | + reg = <0xb12000 0x1000>; | |
| 519 | + interrupts = <0 40 4>; | |
| 520 | + clocks = <&clock HIX5HD2_I2C2_RST>; | |
| 521 | + #address-cells = <1>; | |
| 522 | + #size-cells = <0>; | |
| 523 | + status = "disabled"; | |
| 524 | + }; | |
| 525 | + | |
| 526 | + i2c3: i2c@b13000 { | |
| 527 | + compatible = "hisilicon,hix5hd2-i2c"; | |
| 528 | + reg = <0xb13000 0x1000>; | |
| 529 | + interrupts = <0 41 4>; | |
| 530 | + clocks = <&clock HIX5HD2_I2C3_RST>; | |
| 531 | + #address-cells = <1>; | |
| 532 | + #size-cells = <0>; | |
| 533 | + status = "disabled"; | |
| 534 | + }; | |
| 535 | + | |
| 536 | + i2c4: i2c@b16000 { | |
| 537 | + compatible = "hisilicon,hix5hd2-i2c"; | |
| 538 | + reg = <0xb16000 0x1000>; | |
| 539 | + interrupts = <0 43 4>; | |
| 540 | + clocks = <&clock HIX5HD2_I2C4_RST>; | |
| 541 | + #address-cells = <1>; | |
| 542 | + #size-cells = <0>; | |
| 543 | + status = "disabled"; | |
| 544 | + }; | |
| 545 | + | |
| 546 | + i2c5: i2c@b17000 { | |
| 547 | + compatible = "hisilicon,hix5hd2-i2c"; | |
| 548 | + reg = <0xb17000 0x1000>; | |
| 549 | + interrupts = <0 44 4>; | |
| 550 | + clocks = <&clock HIX5HD2_I2C5_RST>; | |
| 551 | + #address-cells = <1>; | |
| 552 | + #size-cells = <0>; | |
| 553 | + status = "disabled"; | |
| 554 | + }; | |
| 169 | 555 | }; |
| 170 | 556 | }; |
| @@ -214,7 +214,9 @@ · 213 unmodified lines | ||
| 214 | 214 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 215 | 215 | reg = <0x70014000 0x4000>; |
| 216 | 216 | interrupts = <30>; |
| 217 | − clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; | |
| 217 | + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, | |
| 218 | + <&clks IMX5_CLK_SSI2_ROOT_GATE>; | |
| 219 | + clock-names = "ipg", "baud"; | |
| 218 | 220 | dmas = <&sdma 24 1 0>, |
| 219 | 221 | <&sdma 25 1 0>; |
| 220 | 222 | dma-names = "rx", "tx"; |
| @@ -504,7 +506,9 @@ · 283 unmodified lines | ||
| 504 | 506 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 505 | 507 | reg = <0x83fcc000 0x4000>; |
| 506 | 508 | interrupts = <29>; |
| 507 | − clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; | |
| 509 | + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, | |
| 510 | + <&clks IMX5_CLK_SSI1_ROOT_GATE>; | |
| 511 | + clock-names = "ipg", "baud"; | |
| 508 | 512 | dmas = <&sdma 28 0 0>, |
| 509 | 513 | <&sdma 29 0 0>; |
| 510 | 514 | dma-names = "rx", "tx"; |
| @@ -560,7 +564,9 @@ · 49 unmodified lines | ||
| 560 | 564 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 561 | 565 | reg = <0x83fe8000 0x4000>; |
| 562 | 566 | interrupts = <96>; |
| 563 | − clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; | |
| 567 | + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, | |
| 568 | + <&clks IMX5_CLK_SSI3_ROOT_GATE>; | |
| 569 | + clock-names = "ipg", "baud"; | |
| 564 | 570 | dmas = <&sdma 46 0 0>, |
| 565 | 571 | <&sdma 47 0 0>; |
| 566 | 572 | dma-names = "rx", "tx"; |
| @@ -46,10 +46,21 @@ · 45 unmodified lines | ||
| 46 | 46 | cpus { |
| 47 | 47 | #address-cells = <1>; |
| 48 | 48 | #size-cells = <0>; |
| 49 | − cpu@0 { | |
| 49 | + cpu0: cpu@0 { | |
| 50 | 50 | device_type = "cpu"; |
| 51 | 51 | compatible = "arm,cortex-a8"; |
| 52 | 52 | reg = <0x0>; |
| 53 | + clocks = <&clks IMX5_CLK_ARM>; | |
| 54 | + clock-latency = <61036>; | |
| 55 | + voltage-tolerance = <5>; | |
| 56 | + operating-points = < | |
| 57 | + /* kHz */ | |
| 58 | + 166666 850000 | |
| 59 | + 400000 900000 | |
| 60 | + 800000 1050000 | |
| 61 | + 1000000 1200000 | |
| 62 | + 1200000 1300000 | |
| 63 | + >; | |
| 53 | 64 | }; |
| 54 | 65 | }; |
| 55 | 66 | |
| @@ -227,7 +238,9 @@ · 171 unmodified lines | ||
| 227 | 238 | "fsl,imx21-ssi"; |
| 228 | 239 | reg = <0x50014000 0x4000>; |
| 229 | 240 | interrupts = <30>; |
| 230 | − clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; | |
| 241 | + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, | |
| 242 | + <&clks IMX5_CLK_SSI2_ROOT_GATE>; | |
| 243 | + clock-names = "ipg", "baud"; | |
| 231 | 244 | dmas = <&sdma 24 1 0>, |
| 232 | 245 | <&sdma 25 1 0>; |
| 233 | 246 | dma-names = "rx", "tx"; |
| @@ -675,7 +688,9 @@ · 441 unmodified lines | ||
| 675 | 688 | "fsl,imx21-ssi"; |
| 676 | 689 | reg = <0x63fcc000 0x4000>; |
| 677 | 690 | interrupts = <29>; |
| 678 | − clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; | |
| 691 | + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, | |
| 692 | + <&clks IMX5_CLK_SSI1_ROOT_GATE>; | |
| 693 | + clock-names = "ipg", "baud"; | |
| 679 | 694 | dmas = <&sdma 28 0 0>, |
| 680 | 695 | <&sdma 29 0 0>; |
| 681 | 696 | dma-names = "rx", "tx"; |
| @@ -703,7 +718,9 @@ · 21 unmodified lines | ||
| 703 | 718 | "fsl,imx21-ssi"; |
| 704 | 719 | reg = <0x63fe8000 0x4000>; |
| 705 | 720 | interrupts = <96>; |
| 706 | − clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; | |
| 721 | + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, | |
| 722 | + <&clks IMX5_CLK_SSI3_ROOT_GATE>; | |
| 723 | + clock-names = "ipg", "baud"; | |
| 707 | 724 | dmas = <&sdma 46 0 0>, |
| 708 | 725 | <&sdma 47 0 0>; |
| 709 | 726 | dma-names = "rx", "tx"; |
| @@ -13,6 +13,10 @@ · 12 unmodified lines | ||
| 13 | 13 | #include "imx6qdl.dtsi" |
| 14 | 14 | |
| 15 | 15 | / { |
| 16 | + aliases { | |
| 17 | + i2c3 = &i2c4; | |
| 18 | + }; | |
| 19 | + | |
| 16 | 20 | cpus { |
| 17 | 21 | #address-cells = <1>; |
| 18 | 22 | #size-cells = <0>; |
| @@ -114,3 +118,7 @@ · 95 unmodified lines | ||
| 114 | 118 | "di0_sel", "di1_sel", |
| 115 | 119 | "di0", "di1"; |
| 116 | 120 | }; |
| 121 | + | |
| 122 | +&vpu { | |
| 123 | + compatible = "fsl,imx6dl-vpu", "cnm,coda960"; | |
| 124 | +}; | |
| @@ -0,0 +1,432 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2014 Soeren Moch <smoch@web.de> | |
| 3 | + * | |
| 4 | + * This file is dual-licensed: you can use it either under the terms | |
| 5 | + * of the GPL or the X11 license, at your option. Note that this dual | |
| 6 | + * licensing only applies to this file, and not this project as a | |
| 7 | + * whole. | |
| 8 | + * | |
| 9 | + * a) This file is free software; you can redistribute it and/or | |
| 10 | + * modify it under the terms of the GNU General Public License as | |
| 11 | + * published by the Free Software Foundation; either version 2 of | |
| 12 | + * the License, or (at your option) any later version. | |
| 13 | + * | |
| 14 | + * This file is distributed in the hope that it will be useful, | |
| 15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | + * GNU General Public License for more details. | |
| 18 | + * | |
| 19 | + * You should have received a copy of the GNU General Public | |
| 20 | + * License along with this file; if not, write to the Free | |
| 21 | + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
| 22 | + * MA 02110-1301 USA | |
| 23 | + * | |
| 24 | + * Or, alternatively, | |
| 25 | + * | |
| 26 | + * b) Permission is hereby granted, free of charge, to any person | |
| 27 | + * obtaining a copy of this software and associated documentation | |
| 28 | + * files (the "Software"), to deal in the Software without | |
| 29 | + * restriction, including without limitation the rights to use, | |
| 30 | + * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 31 | + * sell copies of the Software, and to permit persons to whom the | |
| 32 | + * Software is furnished to do so, subject to the following | |
| 33 | + * conditions: | |
| 34 | + * | |
| 35 | + * The above copyright notice and this permission notice shall be | |
| 36 | + * included in all copies or substantial portions of the Software. | |
| 37 | + * | |
| 38 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 39 | + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 40 | + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 41 | + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 42 | + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 43 | + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 44 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 45 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 46 | + */ | |
| 47 | + | |
| 48 | +/dts-v1/; | |
| 49 | + | |
| 50 | +#include "imx6q.dtsi" | |
| 51 | +#include <dt-bindings/gpio/gpio.h> | |
| 52 | +#include <dt-bindings/input/input.h> | |
| 53 | + | |
| 54 | +/ { | |
| 55 | + model = "TBS2910 Matrix ARM mini PC"; | |
| 56 | + compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; | |
| 57 | + | |
| 58 | + chosen { | |
| 59 | + stdout-path = &uart1; | |
| 60 | + }; | |
| 61 | + | |
| 62 | + memory { | |
| 63 | + reg = <0x10000000 0x80000000>; | |
| 64 | + }; | |
| 65 | + | |
| 66 | + fan { | |
| 67 | + compatible = "gpio-fan"; | |
| 68 | + pinctrl-names = "default"; | |
| 69 | + pinctrl-0 = <&pinctrl_gpio_fan>; | |
| 70 | + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; | |
| 71 | + gpio-fan,speed-map = <0 0 | |
| 72 | + 3000 1>; | |
| 73 | + }; | |
| 74 | + | |
| 75 | + ir_recv { | |
| 76 | + compatible = "gpio-ir-receiver"; | |
| 77 | + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; | |
| 78 | + pinctrl-names = "default"; | |
| 79 | + pinctrl-0 = <&pinctrl_ir>; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + leds { | |
| 83 | + compatible = "gpio-leds"; | |
| 84 | + pinctrl-names = "default"; | |
| 85 | + pinctrl-0 = <&pinctrl_gpio_leds>; | |
| 86 | + | |
| 87 | + blue { | |
| 88 | + label = "blue_status_led"; | |
| 89 | + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; | |
| 90 | + default-state = "keep"; | |
| 91 | + }; | |
| 92 | + }; | |
| 93 | + | |
| 94 | + regulators { | |
| 95 | + compatible = "simple-bus"; | |
| 96 | + #address-cells = <1>; | |
| 97 | + #size-cells = <0>; | |
| 98 | + | |
| 99 | + reg_2p5v: regulator@0 { | |
| 100 | + compatible = "regulator-fixed"; | |
| 101 | + reg = <0>; | |
| 102 | + regulator-name = "2P5V"; | |
| 103 | + regulator-min-microvolt = <2500000>; | |
| 104 | + regulator-max-microvolt = <2500000>; | |
| 105 | + }; | |
| 106 | + | |
| 107 | + reg_3p3v: regulator@1 { | |
| 108 | + compatible = "regulator-fixed"; | |
| 109 | + reg = <1>; | |
| 110 | + regulator-name = "3P3V"; | |
| 111 | + regulator-min-microvolt = <3300000>; | |
| 112 | + regulator-max-microvolt = <3300000>; | |
| 113 | + }; | |
| 114 | + | |
| 115 | + reg_5p0v: regulator@2 { | |
| 116 | + compatible = "regulator-fixed"; | |
| 117 | + reg = <2>; | |
| 118 | + regulator-name = "5P0V"; | |
| 119 | + regulator-min-microvolt = <5000000>; | |
| 120 | + regulator-max-microvolt = <5000000>; | |
| 121 | + }; | |
| 122 | + }; | |
| 123 | + | |
| 124 | + sound-sgtl5000 { | |
| 125 | + audio-codec = <&sgtl5000>; | |
| 126 | + audio-routing = | |
| 127 | + "MIC_IN", "Mic Jack", | |
| 128 | + "Mic Jack", "Mic Bias", | |
| 129 | + "Headphone Jack", "HP_OUT"; | |
| 130 | + compatible = "fsl,imx-audio-sgtl5000"; | |
| 131 | + model = "On-board Codec"; | |
| 132 | + mux-ext-port = <3>; | |
| 133 | + mux-int-port = <1>; | |
| 134 | + ssi-controller = <&ssi1>; | |
| 135 | + }; | |
| 136 | + | |
| 137 | + sound-spdif { | |
| 138 | + compatible = "fsl,imx-audio-spdif"; | |
| 139 | + model = "On-board SPDIF"; | |
| 140 | + spdif-controller = <&spdif>; | |
| 141 | + spdif-out; | |
| 142 | + }; | |
| 143 | +}; | |
| 144 | + | |
| 145 | +&audmux { | |
| 146 | + status = "okay"; | |
| 147 | +}; | |
| 148 | + | |
| 149 | +&fec { | |
| 150 | + pinctrl-names = "default"; | |
| 151 | + pinctrl-0 = <&pinctrl_enet>; | |
| 152 | + phy-mode = "rgmii"; | |
| 153 | + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; | |
| 154 | + status = "okay"; | |
| 155 | +}; | |
| 156 | + | |
| 157 | +&hdmi { | |
| 158 | + pinctrl-names = "default"; | |
| 159 | + pinctrl-0 = <&pinctrl_hdmi>; | |
| 160 | + ddc-i2c-bus = <&i2c2>; | |
| 161 | + status = "okay"; | |
| 162 | +}; | |
| 163 | + | |
| 164 | +&i2c1 { | |
| 165 | + clock-frequency = <100000>; | |
| 166 | + pinctrl-names = "default"; | |
| 167 | + pinctrl-0 = <&pinctrl_i2c1>; | |
| 168 | + status = "okay"; | |
| 169 | + | |
| 170 | + sgtl5000: sgtl5000@0a { | |
| 171 | + clocks = <&clks 201>; | |
| 172 | + compatible = "fsl,sgtl5000"; | |
| 173 | + pinctrl-names = "default"; | |
| 174 | + pinctrl-0 = <&pinctrl_sgtl5000>; | |
| 175 | + reg = <0x0a>; | |
| 176 | + VDDA-supply = <®_2p5v>; | |
| 177 | + VDDIO-supply = <®_3p3v>; | |
| 178 | + }; | |
| 179 | +}; | |
| 180 | + | |
| 181 | +&i2c2 { | |
| 182 | + clock-frequency = <100000>; | |
| 183 | + pinctrl-names = "default"; | |
| 184 | + pinctrl-0 = <&pinctrl_i2c2>; | |
| 185 | + status = "okay"; | |
| 186 | +}; | |
| 187 | + | |
| 188 | +&i2c3 { | |
| 189 | + clock-frequency = <100000>; | |
| 190 | + pinctrl-names = "default"; | |
| 191 | + pinctrl-0 = <&pinctrl_i2c3>; | |
| 192 | + status = "okay"; | |
| 193 | + | |
| 194 | + rtc: ds1307@68 { | |
| 195 | + compatible = "dallas,ds1307"; | |
| 196 | + reg = <0x68>; | |
| 197 | + }; | |
| 198 | +}; | |
| 199 | + | |
| 200 | +&pcie { | |
| 201 | + pinctrl-names = "default"; | |
| 202 | + pinctrl-0 = <&pinctrl_pcie>; | |
| 203 | + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; | |
| 204 | + status = "okay"; | |
| 205 | +}; | |
| 206 | + | |
| 207 | +&sata { | |
| 208 | + status = "okay"; | |
| 209 | +}; | |
| 210 | + | |
| 211 | +&snvs_poweroff { | |
| 212 | + status = "okay"; | |
| 213 | +}; | |
| 214 | + | |
| 215 | +&spdif { | |
| 216 | + pinctrl-names = "default"; | |
| 217 | + pinctrl-0 = <&pinctrl_spdif>; | |
| 218 | + status = "okay"; | |
| 219 | +}; | |
| 220 | + | |
| 221 | +&ssi1 { | |
| 222 | + status = "okay"; | |
| 223 | +}; | |
| 224 | + | |
| 225 | +&uart1 { | |
| 226 | + pinctrl-names = "default"; | |
| 227 | + pinctrl-0 = <&pinctrl_uart1>; | |
| 228 | + status = "okay"; | |
| 229 | +}; | |
| 230 | + | |
| 231 | +&uart2 { | |
| 232 | + pinctrl-names = "default"; | |
| 233 | + pinctrl-0 = <&pinctrl_uart2>; | |
| 234 | + status = "okay"; | |
| 235 | +}; | |
| 236 | + | |
| 237 | +&usbh1 { | |
| 238 | + vbus-supply = <®_5p0v>; | |
| 239 | + status = "okay"; | |
| 240 | +}; | |
| 241 | + | |
| 242 | +&usbotg { | |
| 243 | + vbus-supply = <®_5p0v>; | |
| 244 | + pinctrl-names = "default"; | |
| 245 | + pinctrl-0 = <&pinctrl_usbotg>; | |
| 246 | + disable-over-current; | |
| 247 | + status = "okay"; | |
| 248 | +}; | |
| 249 | + | |
| 250 | +&usdhc2 { | |
| 251 | + pinctrl-names = "default"; | |
| 252 | + pinctrl-0 = <&pinctrl_usdhc2>; | |
| 253 | + bus-width = <4>; | |
| 254 | + cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; | |
| 255 | + vmmc-supply = <®_3p3v>; | |
| 256 | + status = "okay"; | |
| 257 | +}; | |
| 258 | + | |
| 259 | +&usdhc3 { | |
| 260 | + pinctrl-names = "default"; | |
| 261 | + pinctrl-0 = <&pinctrl_usdhc3>; | |
| 262 | + bus-width = <4>; | |
| 263 | + cd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; | |
| 264 | + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; | |
| 265 | + vmmc-supply = <®_3p3v>; | |
| 266 | + status = "okay"; | |
| 267 | +}; | |
| 268 | + | |
| 269 | +&usdhc4 { | |
| 270 | + pinctrl-names = "default"; | |
| 271 | + pinctrl-0 = <&pinctrl_usdhc4>; | |
| 272 | + bus-width = <8>; | |
| 273 | + non-removable; | |
| 274 | + no-1-8-v; | |
| 275 | + status = "okay"; | |
| 276 | +}; | |
| 277 | + | |
| 278 | +&iomuxc { | |
| 279 | + imx6q-tbs2910 { | |
| 280 | + pinctrl_enet: enetgrp { | |
| 281 | + fsl,pins = < | |
| 282 | + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | |
| 283 | + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | |
| 284 | + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
| 285 | + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
| 286 | + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
| 287 | + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
| 288 | + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
| 289 | + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
| 290 | + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
| 291 | + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
| 292 | + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
| 293 | + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
| 294 | + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
| 295 | + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
| 296 | + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
| 297 | + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | |
| 298 | + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 | |
| 299 | + >; | |
| 300 | + }; | |
| 301 | + | |
| 302 | + pinctrl_hdmi: hdmigrp { | |
| 303 | + fsl,pins = < | |
| 304 | + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | |
| 305 | + >; | |
| 306 | + }; | |
| 307 | + | |
| 308 | + pinctrl_i2c1: i2c1grp { | |
| 309 | + fsl,pins = < | |
| 310 | + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | |
| 311 | + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | |
| 312 | + >; | |
| 313 | + }; | |
| 314 | + | |
| 315 | + pinctrl_i2c2: i2c2grp { | |
| 316 | + fsl,pins = < | |
| 317 | + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | |
| 318 | + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | |
| 319 | + >; | |
| 320 | + }; | |
| 321 | + | |
| 322 | + pinctrl_i2c3: i2c3grp { | |
| 323 | + fsl,pins = < | |
| 324 | + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | |
| 325 | + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | |
| 326 | + >; | |
| 327 | + }; | |
| 328 | + | |
| 329 | + pinctrl_ir: irgrp { | |
| 330 | + fsl,pins = < | |
| 331 | + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 | |
| 332 | + >; | |
| 333 | + }; | |
| 334 | + | |
| 335 | + pinctrl_pcie: pciegrp { | |
| 336 | + fsl,pins = < | |
| 337 | + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 | |
| 338 | + >; | |
| 339 | + }; | |
| 340 | + | |
| 341 | + pinctrl_sgtl5000: sgtl5000grp { | |
| 342 | + fsl,pins = < | |
| 343 | + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 | |
| 344 | + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 | |
| 345 | + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 | |
| 346 | + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 | |
| 347 | + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 | |
| 348 | + >; | |
| 349 | + }; | |
| 350 | + | |
| 351 | + pinctrl_spdif: spdifgrp { | |
| 352 | + fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 | |
| 353 | + >; | |
| 354 | + }; | |
| 355 | + | |
| 356 | + pinctrl_uart1: uart1grp { | |
| 357 | + fsl,pins = < | |
| 358 | + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | |
| 359 | + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | |
| 360 | + >; | |
| 361 | + }; | |
| 362 | + | |
| 363 | + pinctrl_uart2: uart2grp { | |
| 364 | + fsl,pins = < | |
| 365 | + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | |
| 366 | + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | |
| 367 | + >; | |
| 368 | + }; | |
| 369 | + | |
| 370 | + pinctrl_usbotg: usbotggrp { | |
| 371 | + fsl,pins = < | |
| 372 | + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | |
| 373 | + >; | |
| 374 | + }; | |
| 375 | + | |
| 376 | + pinctrl_usdhc2: usdhc2grp { | |
| 377 | + fsl,pins = < | |
| 378 | + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | |
| 379 | + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | |
| 380 | + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | |
| 381 | + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | |
| 382 | + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | |
| 383 | + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | |
| 384 | + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 | |
| 385 | + >; | |
| 386 | + }; | |
| 387 | + | |
| 388 | + pinctrl_usdhc3: usdhc3grp { | |
| 389 | + fsl,pins = < | |
| 390 | + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
| 391 | + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
| 392 | + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
| 393 | + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
| 394 | + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
| 395 | + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
| 396 | + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 | |
| 397 | + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 | |
| 398 | + >; | |
| 399 | + }; | |
| 400 | + | |
| 401 | + pinctrl_usdhc4: usdhc4grp { | |
| 402 | + fsl,pins = < | |
| 403 | + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | |
| 404 | + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | |
| 405 | + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | |
| 406 | + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | |
| 407 | + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | |
| 408 | + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | |
| 409 | + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | |
| 410 | + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | |
| 411 | + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | |
| 412 | + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | |
| 413 | + >; | |
| 414 | + }; | |
| 415 | + }; | |
| 416 | + | |
| 417 | + gpio_fan { | |
| 418 | + pinctrl_gpio_fan: gpiofangrp { | |
| 419 | + fsl,pins = < | |
| 420 | + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 | |
| 421 | + >; | |
| 422 | + }; | |
| 423 | + }; | |
| 424 | + | |
| 425 | + gpio_leds { | |
| 426 | + pinctrl_gpio_leds: gpioledsgrp { | |
| 427 | + fsl,pins = < | |
| 428 | + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 | |
| 429 | + >; | |
| 430 | + }; | |
| 431 | + }; | |
| 432 | +}; | |
| @@ -308,3 +308,7 @@ · 307 unmodified lines | ||
| 308 | 308 | }; |
| 309 | 309 | }; |
| 310 | 310 | }; |
| 311 | + | |
| 312 | +&vpu { | |
| 313 | + compatible = "fsl,imx6q-vpu", "cnm,coda960"; | |
| 314 | +}; | |
| @@ -282,7 +282,6 @@ · 281 unmodified lines | ||
| 282 | 282 | }; |
| 283 | 283 | |
| 284 | 284 | &ssi1 { |
| 285 | − fsl,mode = "i2s-slave"; | |
| 286 | 285 | status = "okay"; |
| 287 | 286 | }; |
| 288 | 287 | |
| @@ -287,7 +287,6 @@ · 286 unmodified lines | ||
| 287 | 287 | }; |
| 288 | 288 | |
| 289 | 289 | &ssi1 { |
| 290 | − fsl,mode = "i2s-slave"; | |
| 291 | 290 | status = "okay"; |
| 292 | 291 | }; |
| 293 | 292 | |
| @@ -376,12 +376,10 @@ · 375 unmodified lines | ||
| 376 | 376 | }; |
| 377 | 377 | |
| 378 | 378 | &ssi1 { |
| 379 | − fsl,mode = "i2s-slave"; | |
| 380 | 379 | status = "okay"; |
| 381 | 380 | }; |
| 382 | 381 | |
| 383 | 382 | &ssi2 { |
| 384 | − fsl,mode = "i2s-slave"; | |
| 385 | 383 | status = "okay"; |
| 386 | 384 | }; |
| 387 | 385 | |
| @@ -9,17 +9,103 @@ · 8 unmodified lines | ||
| 9 | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | 10 | */ |
| 11 | 11 | |
| 12 | +#include <dt-bindings/sound/fsl-imx-audmux.h> | |
| 13 | + | |
| 12 | 14 | / { |
| 13 | 15 | chosen { |
| 14 | 16 | linux,stdout-path = &uart4; |
| 15 | 17 | }; |
| 18 | + | |
| 19 | + regulators { | |
| 20 | + sound_1v8: regulator@2 { | |
| 21 | + compatible = "regulator-fixed"; | |
| 22 | + reg = <2>; | |
| 23 | + regulator-name = "i2s-audio-1v8"; | |
| 24 | + regulator-min-microvolt = <1800000>; | |
| 25 | + regulator-max-microvolt = <1800000>; | |
| 26 | + }; | |
| 27 | + | |
| 28 | + sound_3v3: regulator@3 { | |
| 29 | + compatible = "regulator-fixed"; | |
| 30 | + reg = <3>; | |
| 31 | + regulator-name = "i2s-audio-3v3"; | |
| 32 | + regulator-min-microvolt = <3300000>; | |
| 33 | + regulator-max-microvolt = <3300000>; | |
| 34 | + }; | |
| 35 | + }; | |
| 36 | + | |
| 37 | + tlv320_mclk: oscillator { | |
| 38 | + compatible = "fixed-clock"; | |
| 39 | + #clock-cells = <0>; | |
| 40 | + clock-frequency = <19200000>; | |
| 41 | + clock-output-names = "tlv320-mclk"; | |
| 42 | + }; | |
| 43 | + | |
| 44 | + sound { | |
| 45 | + compatible = "simple-audio-card"; | |
| 46 | + simple-audio-card,name = "OnboardTLV320AIC3007"; | |
| 47 | + simple-audio-card,format = "i2s"; | |
| 48 | + simple-audio-card,bitclock-master = <&dailink_master>; | |
| 49 | + simple-audio-card,frame-master = <&dailink_master>; | |
| 50 | + simple-audio-card,widgets = | |
| 51 | + "Microphone", "Mic Jack", | |
| 52 | + "Line", "Line In", | |
| 53 | + "Line", "Line Out", | |
| 54 | + "Speaker", "Speaker", | |
| 55 | + "Headphone", "Headphone Jack"; | |
| 56 | + simple-audio-card,routing = | |
| 57 | + "Line Out", "LLOUT", | |
| 58 | + "Line Out", "RLOUT", | |
| 59 | + "Speaker", "SPOP", | |
| 60 | + "Speaker", "SPOM", | |
| 61 | + "Headphone Jack", "HPLOUT", | |
| 62 | + "Headphone Jack", "HPROUT", | |
| 63 | + "MIC3L", "Mic Jack", | |
| 64 | + "MIC3R", "Mic Jack", | |
| 65 | + "Mic Jack", "Mic Bias", | |
| 66 | + "LINE1L", "Line In", | |
| 67 | + "LINE1R", "Line In"; | |
| 68 | + | |
| 69 | + simple-audio-card,cpu { | |
| 70 | + sound-dai = <&ssi2>; | |
| 71 | + }; | |
| 72 | + | |
| 73 | + dailink_master: simple-audio-card,codec { | |
| 74 | + sound-dai = <&codec>; | |
| 75 | + clocks = <&tlv320_mclk>; | |
| 76 | + }; | |
| 77 | + }; | |
| 78 | + | |
| 16 | 79 | }; |
| 17 | 80 | |
| 18 | −&fec { | |
| 81 | +&audmux { | |
| 19 | 82 | status = "okay"; |
| 83 | + | |
| 84 | + ssi2 { | |
| 85 | + fsl,audmux-port = <1>; | |
| 86 | + fsl,port-config = < | |
| 87 | + (IMX_AUDMUX_V2_PTCR_TFSDIR | | |
| 88 | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | | |
| 89 | + IMX_AUDMUX_V2_PTCR_TCLKDIR | | |
| 90 | + IMX_AUDMUX_V2_PTCR_TCSEL(4)) | |
| 91 | + IMX_AUDMUX_V2_PDCR_RXDSEL(4) | |
| 92 | + >; | |
| 93 | + }; | |
| 94 | + | |
| 95 | + pins5 { | |
| 96 | + fsl,audmux-port = <4>; | |
| 97 | + fsl,port-config = < | |
| 98 | + 0x00000000 | |
| 99 | + IMX_AUDMUX_V2_PDCR_RXDSEL(1) | |
| 100 | + >; | |
| 101 | + }; | |
| 20 | 102 | }; |
| 21 | 103 | |
| 22 | −&gpmi { | |
| 104 | +&can1 { | |
| 105 | + status = "okay"; | |
| 106 | +}; | |
| 107 | + | |
| 108 | +&fec { | |
| 23 | 109 | status = "okay"; |
| 24 | 110 | }; |
| 25 | 111 | |
| @@ -28,14 +114,18 @@ · 2 unmodified lines | ||
| 28 | 114 | }; |
| 29 | 115 | |
| 30 | 116 | &i2c2 { |
| 31 | − pinctrl-names = "default"; | |
| 32 | − pinctrl-0 = <&pinctrl_i2c2>; | |
| 33 | − clock-frequency = <100000>; | |
| 34 | 117 | status = "okay"; |
| 35 | 118 | |
| 36 | − tlv320@18 { | |
| 37 | − compatible = "ti,tlv320aic3x"; | |
| 119 | + codec: tlv320@18 { | |
| 120 | + compatible = "ti,tlv320aic3007"; | |
| 121 | + #sound-dai-cells = <0>; | |
| 38 | 122 | reg = <0x18>; |
| 123 | + ai3x-micbias-vg = <2>; | |
| 124 | + | |
| 125 | + AVDD-supply = <&sound_3v3>; | |
| 126 | + IOVDD-supply = <&sound_3v3>; | |
| 127 | + DRVDD-supply = <&sound_3v3>; | |
| 128 | + DVDD-supply = <&sound_1v8>; | |
| 39 | 129 | }; |
| 40 | 130 | |
| 41 | 131 | stmpe@41 { |
| @@ -55,9 +145,14 @@ · 13 unmodified lines | ||
| 55 | 145 | }; |
| 56 | 146 | |
| 57 | 147 | &i2c3 { |
| 58 | − pinctrl-names = "default"; | |
| 59 | − pinctrl-0 = <&pinctrl_i2c3>; | |
| 60 | − clock-frequency = <100000>; | |
| 148 | + status = "okay"; | |
| 149 | +}; | |
| 150 | + | |
| 151 | +&pcie { | |
| 152 | + status = "okay"; | |
| 153 | +}; | |
| 154 | + | |
| 155 | +&ssi2 { | |
| 61 | 156 | status = "okay"; |
| 62 | 157 | }; |
| 63 | 158 | |
| @@ -84,19 +179,3 @@ · 20 unmodified lines | ||
| 84 | 179 | &usdhc3 { |
| 85 | 180 | status = "okay"; |
| 86 | 181 | }; |
| 87 | − | |
| 88 | −&iomuxc { | |
| 89 | − pinctrl_i2c2: i2c2grp { | |
| 90 | − fsl,pins = < | |
| 91 | − MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | |
| 92 | − MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | |
| 93 | − >; | |
| 94 | − }; | |
| 95 | − | |
| 96 | − pinctrl_i2c3: i2c3grp { | |
| 97 | − fsl,pins = < | |
| 98 | − MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | |
| 99 | − MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | |
| 100 | − >; | |
| 101 | − }; | |
| 102 | −}; | |
| @@ -58,6 +58,18 @@ · 57 unmodified lines | ||
| 58 | 58 | }; |
| 59 | 59 | }; |
| 60 | 60 | |
| 61 | +&audmux { | |
| 62 | + pinctrl-names = "default"; | |
| 63 | + pinctrl-0 = <&pinctrl_audmux>; | |
| 64 | + status = "disabled"; | |
| 65 | +}; | |
| 66 | + | |
| 67 | +&can1 { | |
| 68 | + pinctrl-names = "default"; | |
| 69 | + pinctrl-0 = <&pinctrl_flexcan1>; | |
| 70 | + status = "disabled"; | |
| 71 | +}; | |
| 72 | + | |
| 61 | 73 | &ecspi3 { |
| 62 | 74 | pinctrl-names = "default"; |
| 63 | 75 | pinctrl-0 = <&pinctrl_ecspi3>; |
| @@ -72,6 +84,22 @@ · 8 unmodified lines | ||
| 72 | 84 | }; |
| 73 | 85 | }; |
| 74 | 86 | |
| 87 | +&fec { | |
| 88 | + pinctrl-names = "default"; | |
| 89 | + pinctrl-0 = <&pinctrl_enet>; | |
| 90 | + phy-mode = "rgmii"; | |
| 91 | + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; | |
| 92 | + phy-supply = <&vdd_eth_io_reg>; | |
| 93 | + status = "disabled"; | |
| 94 | +}; | |
| 95 | + | |
| 96 | +&gpmi { | |
| 97 | + pinctrl-names = "default"; | |
| 98 | + pinctrl-0 = <&pinctrl_gpmi_nand>; | |
| 99 | + nand-on-flash-bbt; | |
| 100 | + status = "okay"; | |
| 101 | +}; | |
| 102 | + | |
| 75 | 103 | &i2c1 { |
| 76 | 104 | pinctrl-names = "default"; |
| 77 | 105 | pinctrl-0 = <&pinctrl_i2c1>; |
| @@ -85,8 +113,8 @@ · 7 unmodified lines | ||
| 85 | 113 | pmic@58 { |
| 86 | 114 | compatible = "dlg,da9063"; |
| 87 | 115 | reg = <0x58>; |
| 88 | − interrupt-parent = <&gpio4>; | |
| 89 | − interrupts = <17 0x8>; /* active-low GPIO4_17 */ | |
| 116 | + interrupt-parent = <&gpio2>; | |
| 117 | + interrupts = <9 0x8>; /* active-low GPIO2_9 */ | |
| 90 | 118 | |
| 91 | 119 | regulators { |
| 92 | 120 | vddcore_reg: bcore1 { |
| @@ -162,6 +190,18 @@ · 69 unmodified lines | ||
| 162 | 190 | }; |
| 163 | 191 | }; |
| 164 | 192 | |
| 193 | +&i2c2 { | |
| 194 | + pinctrl-names = "default"; | |
| 195 | + pinctrl-0 = <&pinctrl_i2c2>; | |
| 196 | + clock-frequency = <100000>; | |
| 197 | +}; | |
| 198 | + | |
| 199 | +&i2c3 { | |
| 200 | + pinctrl-names = "default"; | |
| 201 | + pinctrl-0 = <&pinctrl_i2c3>; | |
| 202 | + clock-frequency = <100000>; | |
| 203 | +}; | |
| 204 | + | |
| 165 | 205 | &iomuxc { |
| 166 | 206 | pinctrl-names = "default"; |
| 167 | 207 | pinctrl-0 = <&pinctrl_hog>; |
| @@ -171,7 +211,7 @@ · 3 unmodified lines | ||
| 171 | 211 | fsl,pins = < |
| 172 | 212 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 |
| 173 | 213 | MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ |
| 174 | − MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ | |
| 214 | + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */ | |
| 175 | 215 | MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ |
| 176 | 216 | MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ |
| 177 | 217 | >; |
| @@ -206,6 +246,13 @@ · 28 unmodified lines | ||
| 206 | 246 | >; |
| 207 | 247 | }; |
| 208 | 248 | |
| 249 | + pinctrl_flexcan1: flexcan1grp { | |
| 250 | + fsl,pins = < | |
| 251 | + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 | |
| 252 | + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 | |
| 253 | + >; | |
| 254 | + }; | |
| 255 | + | |
| 209 | 256 | pinctrl_gpmi_nand: gpminandgrp { |
| 210 | 257 | fsl,pins = < |
| 211 | 258 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 |
| @@ -235,6 +282,24 @@ · 23 unmodified lines | ||
| 235 | 282 | >; |
| 236 | 283 | }; |
| 237 | 284 | |
| 285 | + pinctrl_i2c2: i2c2grp { | |
| 286 | + fsl,pins = < | |
| 287 | + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | |
| 288 | + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | |
| 289 | + >; | |
| 290 | + }; | |
| 291 | + | |
| 292 | + pinctrl_i2c3: i2c3grp { | |
| 293 | + fsl,pins = < | |
| 294 | + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | |
| 295 | + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | |
| 296 | + >; | |
| 297 | + }; | |
| 298 | + | |
| 299 | + pinctrl_pcie: pciegrp { | |
| 300 | + fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; | |
| 301 | + }; | |
| 302 | + | |
| 238 | 303 | pinctrl_uart3: uart3grp { |
| 239 | 304 | fsl,pins = < |
| 240 | 305 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 |
| @@ -293,22 +358,22 @@ · 52 unmodified lines | ||
| 293 | 358 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 |
| 294 | 359 | >; |
| 295 | 360 | }; |
| 296 | − }; | |
| 297 | −}; | |
| 298 | 361 | |
| 299 | −&fec { | |
| 300 | − pinctrl-names = "default"; | |
| 301 | − pinctrl-0 = <&pinctrl_enet>; | |
| 302 | − phy-mode = "rgmii"; | |
| 303 | − phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; | |
| 304 | − phy-supply = <&vdd_eth_io_reg>; | |
| 305 | − status = "disabled"; | |
| 362 | + pinctrl_audmux: audmuxgrp { | |
| 363 | + fsl,pins = < | |
| 364 | + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 | |
| 365 | + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 | |
| 366 | + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 | |
| 367 | + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 | |
| 368 | + >; | |
| 369 | + }; | |
| 370 | + }; | |
| 306 | 371 | }; |
| 307 | 372 | |
| 308 | −&gpmi { | |
| 309 | − pinctrl-names = "default"; | |
| 310 | − pinctrl-0 = <&pinctrl_gpmi_nand>; | |
| 311 | − nand-on-flash-bbt; | |
| 373 | +&pcie { | |
| 374 | + pinctrl-name = "default"; | |
| 375 | + pinctrl-0 = <&pinctrl_pcie>; | |
| 376 | + reset-gpio = <&gpio4 17 0>; | |
| 312 | 377 | status = "disabled"; |
| 313 | 378 | }; |
| 314 | 379 | |
| @@ -308,7 +308,6 @@ · 307 unmodified lines | ||
| 308 | 308 | }; |
| 309 | 309 | |
| 310 | 310 | &ssi1 { |
| 311 | − fsl,mode = "i2s-slave"; | |
| 312 | 311 | status = "okay"; |
| 313 | 312 | }; |
| 314 | 313 | |
| @@ -107,10 +107,8 @@ · 106 unmodified lines | ||
| 107 | 107 | "Headphone Jack", "HPOUTR", |
| 108 | 108 | "Ext Spk", "SPKOUTL", |
| 109 | 109 | "Ext Spk", "SPKOUTR", |
| 110 | − "MICBIAS", "AMIC", | |
| 111 | − "IN3R", "MICBIAS", | |
| 112 | − "DMIC", "MICBIAS", | |
| 113 | − "DMICDAT", "DMIC"; | |
| 110 | + "AMIC", "MICBIAS", | |
| 111 | + "IN3R", "AMIC"; | |
| 114 | 112 | mux-int-port = <2>; |
| 115 | 113 | mux-ext-port = <3>; |
| 116 | 114 | }; |
| @@ -179,7 +177,7 @@ · 62 unmodified lines | ||
| 179 | 177 | codec: wm8962@1a { |
| 180 | 178 | compatible = "wlf,wm8962"; |
| 181 | 179 | reg = <0x1a>; |
| 182 | − clocks = <&clks 201>; | |
| 180 | + clocks = <&clks IMX6QDL_CLK_CKO>; | |
| 183 | 181 | DCVDD-supply = <®_audio>; |
| 184 | 182 | DBVDD-supply = <®_audio>; |
| 185 | 183 | AVDD-supply = <®_audio>; |
| @@ -531,6 +529,10 @@ · 345 unmodified lines | ||
| 531 | 529 | status = "okay"; |
| 532 | 530 | }; |
| 533 | 531 | |
| 532 | +&snvs_poweroff { | |
| 533 | + status = "okay"; | |
| 534 | +}; | |
| 535 | + | |
| 534 | 536 | &ssi2 { |
| 535 | 537 | status = "okay"; |
| 536 | 538 | }; |
| @@ -333,9 +333,17 @@ · 332 unmodified lines | ||
| 333 | 333 | }; |
| 334 | 334 | |
| 335 | 335 | vpu: vpu@02040000 { |
| 336 | + compatible = "cnm,coda960"; | |
| 336 | 337 | reg = <0x02040000 0x3c000>; |
| 337 | 338 | interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, |
| 338 | 339 | <0 12 IRQ_TYPE_LEVEL_HIGH>; |
| 340 | + interrupt-names = "bit", "jpeg"; | |
| 341 | + clocks = <&clks IMX6QDL_CLK_VPU_AXI>, | |
| 342 | + <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, | |
| 343 | + <&clks IMX6QDL_CLK_OCRAM>; | |
| 344 | + clock-names = "per", "ahb", "ocram"; | |
| 345 | + resets = <&src 1>; | |
| 346 | + iram = <&ocram>; | |
| 339 | 347 | }; |
| 340 | 348 | |
| 341 | 349 | aipstz@0207c000 { /* AIPSTZ1 */ |
| @@ -657,6 +665,12 @@ · 315 unmodified lines | ||
| 657 | 665 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| 658 | 666 | <0 20 IRQ_TYPE_LEVEL_HIGH>; |
| 659 | 667 | }; |
| 668 | + | |
| 669 | + snvs_poweroff: snvs-poweroff@38 { | |
| 670 | + compatible = "fsl,sec-v4.0-poweroff"; | |
| 671 | + reg = <0x38 0x4>; | |
| 672 | + status = "disabled"; | |
| 673 | + }; | |
| 660 | 674 | }; |
| 661 | 675 | |
| 662 | 676 | epit1: epit@020d0000 { /* EPIT1 */ |
| @@ -580,6 +580,10 @@ · 579 unmodified lines | ||
| 580 | 580 | status = "okay"; |
| 581 | 581 | }; |
| 582 | 582 | |
| 583 | +&snvs_poweroff { | |
| 584 | + status = "okay"; | |
| 585 | +}; | |
| 586 | + | |
| 583 | 587 | &ssi2 { |
| 584 | 588 | status = "okay"; |
| 585 | 589 | }; |
| @@ -574,6 +574,12 @@ · 573 unmodified lines | ||
| 574 | 574 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| 575 | 575 | <0 20 IRQ_TYPE_LEVEL_HIGH>; |
| 576 | 576 | }; |
| 577 | + | |
| 578 | + snvs_poweroff: snvs-poweroff@38 { | |
| 579 | + compatible = "fsl,sec-v4.0-poweroff"; | |
| 580 | + reg = <0x38 0x4>; | |
| 581 | + status = "disabled"; | |
| 582 | + }; | |
| 577 | 583 | }; |
| 578 | 584 | |
| 579 | 585 | epit1: epit@020d0000 { |
| @@ -105,6 +105,30 @@ · 104 unmodified lines | ||
| 105 | 105 | gpio = <&gpio3 27 0>; |
| 106 | 106 | enable-active-high; |
| 107 | 107 | }; |
| 108 | + | |
| 109 | + reg_peri_3v3: regulator@5 { | |
| 110 | + compatible = "regulator-fixed"; | |
| 111 | + reg = <5>; | |
| 112 | + pinctrl-names = "default"; | |
| 113 | + pinctrl-0 = <&pinctrl_peri_3v3>; | |
| 114 | + regulator-name = "peri_3v3"; | |
| 115 | + regulator-min-microvolt = <3300000>; | |
| 116 | + regulator-max-microvolt = <3300000>; | |
| 117 | + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; | |
| 118 | + enable-active-high; | |
| 119 | + regulator-always-on; | |
| 120 | + }; | |
| 121 | + | |
| 122 | + reg_enet_3v3: regulator@6 { | |
| 123 | + compatible = "regulator-fixed"; | |
| 124 | + reg = <6>; | |
| 125 | + pinctrl-names = "default"; | |
| 126 | + pinctrl-0 = <&pinctrl_enet_3v3>; | |
| 127 | + regulator-name = "enet_3v3"; | |
| 128 | + regulator-min-microvolt = <3300000>; | |
| 129 | + regulator-max-microvolt = <3300000>; | |
| 130 | + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; | |
| 131 | + }; | |
| 108 | 132 | }; |
| 109 | 133 | |
| 110 | 134 | sound { |
| @@ -133,6 +157,14 @@ · 22 unmodified lines | ||
| 133 | 157 | &fec1 { |
| 134 | 158 | pinctrl-names = "default"; |
| 135 | 159 | pinctrl-0 = <&pinctrl_enet1>; |
| 160 | + phy-supply = <®_enet_3v3>; | |
| 161 | + phy-mode = "rgmii"; | |
| 162 | + status = "okay"; | |
| 163 | +}; | |
| 164 | + | |
| 165 | +&fec2 { | |
| 166 | + pinctrl-names = "default"; | |
| 167 | + pinctrl-0 = <&pinctrl_enet2>; | |
| 136 | 168 | phy-mode = "rgmii"; |
| 137 | 169 | status = "okay"; |
| 138 | 170 | }; |
| @@ -304,6 +336,10 @@ · 165 unmodified lines | ||
| 304 | 336 | status = "okay"; |
| 305 | 337 | }; |
| 306 | 338 | |
| 339 | +&snvs_poweroff { | |
| 340 | + status = "okay"; | |
| 341 | +}; | |
| 342 | + | |
| 307 | 343 | &ssi2 { |
| 308 | 344 | status = "okay"; |
| 309 | 345 | }; |
| @@ -394,6 +430,30 @@ · 84 unmodified lines | ||
| 394 | 430 | MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 |
| 395 | 431 | MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 |
| 396 | 432 | MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 |
| 433 | + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 | |
| 434 | + >; | |
| 435 | + }; | |
| 436 | + | |
| 437 | + pinctrl_enet_3v3: enet3v3grp { | |
| 438 | + fsl,pins = < | |
| 439 | + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 | |
| 440 | + >; | |
| 441 | + }; | |
| 442 | + | |
| 443 | + pinctrl_enet2: enet2grp { | |
| 444 | + fsl,pins = < | |
| 445 | + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 | |
| 446 | + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 | |
| 447 | + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 | |
| 448 | + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 | |
| 449 | + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 | |
| 450 | + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 | |
| 451 | + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 | |
| 452 | + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 | |
| 453 | + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 | |
| 454 | + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 | |
| 455 | + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 | |
| 456 | + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 | |
| 397 | 457 | >; |
| 398 | 458 | }; |
| 399 | 459 | |
| @@ -452,6 +512,12 @@ · 52 unmodified lines | ||
| 452 | 512 | >; |
| 453 | 513 | }; |
| 454 | 514 | |
| 515 | + pinctrl_peri_3v3: peri3v3grp { | |
| 516 | + fsl,pins = < | |
| 517 | + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 | |
| 518 | + >; | |
| 519 | + }; | |
| 520 | + | |
| 455 | 521 | pinctrl_pwm3: pwm3grp-1 { |
| 456 | 522 | fsl,pins = < |
| 457 | 523 | MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 |
| @@ -671,6 +671,12 @@ · 670 unmodified lines | ||
| 671 | 671 | reg = <0x34 0x58>; |
| 672 | 672 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 673 | 673 | }; |
| 674 | + | |
| 675 | + snvs_poweroff: snvs-poweroff@38 { | |
| 676 | + compatible = "fsl,sec-v4.0-poweroff"; | |
| 677 | + reg = <0x38 0x4>; | |
| 678 | + status = "disabled"; | |
| 679 | + }; | |
| 674 | 680 | }; |
| 675 | 681 | |
| 676 | 682 | epit1: epit@020d0000 { |
| @@ -877,7 +883,7 @@ · 200 unmodified lines | ||
| 877 | 883 | }; |
| 878 | 884 | |
| 879 | 885 | fec2: ethernet@021b4000 { |
| 880 | − compatible = "fsl,imx6sx-fec"; | |
| 886 | + compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; | |
| 881 | 887 | reg = <0x021b4000 0x4000>; |
| 882 | 888 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| 883 | 889 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -6,8 +6,18 @@ · 5 unmodified lines | ||
| 6 | 6 | |
| 7 | 7 | / { |
| 8 | 8 | core-module@10000000 { |
| 9 | − compatible = "arm,core-module-integrator"; | |
| 9 | + compatible = "arm,core-module-integrator", "syscon"; | |
| 10 | 10 | reg = <0x10000000 0x200>; |
| 11 | + | |
| 12 | + /* Use core module LED to indicate CPU load */ | |
| 13 | + led@0c.0 { | |
| 14 | + compatible = "register-bit-led"; | |
| 15 | + offset = <0x0c>; | |
| 16 | + mask = <0x01>; | |
| 17 | + label = "integrator:core_module"; | |
| 18 | + linux,default-trigger = "cpu0"; | |
| 19 | + default-state = "on"; | |
| 20 | + }; | |
| 11 | 21 | }; |
| 12 | 22 | |
| 13 | 23 | ebi@12000000 { |
| @@ -82,5 +92,41 @@ · 68 unmodified lines | ||
| 82 | 92 | reg = <0x19000000 0x1000>; |
| 83 | 93 | interrupts = <4>; |
| 84 | 94 | }; |
| 95 | + | |
| 96 | + syscon { | |
| 97 | + /* Debug registers mapped as syscon */ | |
| 98 | + compatible = "syscon"; | |
| 99 | + reg = <0x1a000000 0x10>; | |
| 100 | + | |
| 101 | + led@04.0 { | |
| 102 | + compatible = "register-bit-led"; | |
| 103 | + offset = <0x04>; | |
| 104 | + mask = <0x01>; | |
| 105 | + label = "integrator:green0"; | |
| 106 | + linux,default-trigger = "heartbeat"; | |
| 107 | + default-state = "on"; | |
| 108 | + }; | |
| 109 | + led@04.1 { | |
| 110 | + compatible = "register-bit-led"; | |
| 111 | + offset = <0x04>; | |
| 112 | + mask = <0x02>; | |
| 113 | + label = "integrator:yellow"; | |
| 114 | + default-state = "off"; | |
| 115 | + }; | |
| 116 | + led@04.2 { | |
| 117 | + compatible = "register-bit-led"; | |
| 118 | + offset = <0x04>; | |
| 119 | + mask = <0x04>; | |
| 120 | + label = "integrator:red"; | |
| 121 | + default-state = "off"; | |
| 122 | + }; | |
| 123 | + led@04.3 { | |
| 124 | + compatible = "register-bit-led"; | |
| 125 | + offset = <0x04>; | |
| 126 | + mask = <0x08>; | |
| 127 | + label = "integrator:green1"; | |
| 128 | + default-state = "off"; | |
| 129 | + }; | |
| 130 | + }; | |
| 85 | 131 | }; |
| 86 | 132 | }; |
| @@ -139,3 +139,15 @@ · 138 unmodified lines | ||
| 139 | 139 | }; |
| 140 | 140 | }; |
| 141 | 141 | }; |
| 142 | + | |
| 143 | +&mdio { | |
| 144 | + ethphy0: ethernet-phy@0 { | |
| 145 | + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; | |
| 146 | + reg = <0>; | |
| 147 | + }; | |
| 148 | + | |
| 149 | + ethphy1: ethernet-phy@1 { | |
| 150 | + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; | |
| 151 | + reg = <1>; | |
| 152 | + }; | |
| 153 | +}; | |
| @@ -85,6 +85,51 @@ · 84 unmodified lines | ||
| 85 | 85 | #gpio-cells = <2>; |
| 86 | 86 | gpio,syscon-dev = <&devctrl 0x240>; |
| 87 | 87 | }; |
| 88 | + | |
| 89 | + pcie@21020000 { | |
| 90 | + compatible = "ti,keystone-pcie","snps,dw-pcie"; | |
| 91 | + clocks = <&clkpcie1>; | |
| 92 | + clock-names = "pcie"; | |
| 93 | + #address-cells = <3>; | |
| 94 | + #size-cells = <2>; | |
| 95 | + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; | |
| 96 | + ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 | |
| 97 | + 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; | |
| 98 | + | |
| 99 | + device_type = "pci"; | |
| 100 | + num-lanes = <2>; | |
| 101 | + | |
| 102 | + #interrupt-cells = <1>; | |
| 103 | + interrupt-map-mask = <0 0 0 7>; | |
| 104 | + interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ | |
| 105 | + <0 0 0 2 &pcie_intc1 1>, /* INT B */ | |
| 106 | + <0 0 0 3 &pcie_intc1 2>, /* INT C */ | |
| 107 | + <0 0 0 4 &pcie_intc1 3>; /* INT D */ | |
| 108 | + | |
| 109 | + pcie_msi_intc1: msi-interrupt-controller { | |
| 110 | + interrupt-controller; | |
| 111 | + #interrupt-cells = <1>; | |
| 112 | + interrupt-parent = <&gic>; | |
| 113 | + interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, | |
| 114 | + <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, | |
| 115 | + <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>, | |
| 116 | + <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>, | |
| 117 | + <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>, | |
| 118 | + <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>, | |
| 119 | + <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>, | |
| 120 | + <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>; | |
| 121 | + }; | |
| 122 | + | |
| 123 | + pcie_intc1: legacy-interrupt-controller { | |
| 124 | + interrupt-controller; | |
| 125 | + #interrupt-cells = <1>; | |
| 126 | + interrupt-parent = <&gic>; | |
| 127 | + interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, | |
| 128 | + <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, | |
| 129 | + <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, | |
| 130 | + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>; | |
| 131 | + }; | |
| 132 | + }; | |
| 88 | 133 | }; |
| 89 | 134 | }; |
| 90 | 135 | |
| @@ -116,3 +116,15 @@ · 115 unmodified lines | ||
| 116 | 116 | }; |
| 117 | 117 | }; |
| 118 | 118 | }; |
| 119 | + | |
| 120 | +&mdio { | |
| 121 | + ethphy0: ethernet-phy@0 { | |
| 122 | + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; | |
| 123 | + reg = <0>; | |
| 124 | + }; | |
| 125 | + | |
| 126 | + ethphy1: ethernet-phy@1 { | |
| 127 | + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; | |
| 128 | + reg = <1>; | |
| 129 | + }; | |
| 130 | +}; | |
| @@ -285,5 +285,50 @@ · 284 unmodified lines | ||
| 285 | 285 | #interrupt-cells = <1>; |
| 286 | 286 | ti,syscon-dev = <&devctrl 0x2a0>; |
| 287 | 287 | }; |
| 288 | + | |
| 289 | + pcie@21800000 { | |
| 290 | + compatible = "ti,keystone-pcie", "snps,dw-pcie"; | |
| 291 | + clocks = <&clkpcie>; | |
| 292 | + clock-names = "pcie"; | |
| 293 | + #address-cells = <3>; | |
| 294 | + #size-cells = <2>; | |
| 295 | + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; | |
| 296 | + ranges = <0x81000000 0 0 0x23250000 0 0x4000 | |
| 297 | + 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; | |
| 298 | + | |
| 299 | + device_type = "pci"; | |
| 300 | + num-lanes = <2>; | |
| 301 | + | |
| 302 | + #interrupt-cells = <1>; | |
| 303 | + interrupt-map-mask = <0 0 0 7>; | |
| 304 | + interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ | |
| 305 | + <0 0 0 2 &pcie_intc0 1>, /* INT B */ | |
| 306 | + <0 0 0 3 &pcie_intc0 2>, /* INT C */ | |
| 307 | + <0 0 0 4 &pcie_intc0 3>; /* INT D */ | |
| 308 | + | |
| 309 | + pcie_msi_intc0: msi-interrupt-controller { | |
| 310 | + interrupt-controller; | |
| 311 | + #interrupt-cells = <1>; | |
| 312 | + interrupt-parent = <&gic>; | |
| 313 | + interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, | |
| 314 | + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, | |
| 315 | + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, | |
| 316 | + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, | |
| 317 | + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, | |
| 318 | + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, | |
| 319 | + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, | |
| 320 | + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; | |
| 321 | + }; | |
| 322 | + | |
| 323 | + pcie_intc0: legacy-interrupt-controller { | |
| 324 | + interrupt-controller; | |
| 325 | + #interrupt-cells = <1>; | |
| 326 | + interrupt-parent = <&gic>; | |
| 327 | + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, | |
| 328 | + <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, | |
| 329 | + <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, | |
| 330 | + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; | |
| 331 | + }; | |
| 332 | + }; | |
| 288 | 333 | }; |
| 289 | 334 | }; |
| @@ -0,0 +1,278 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Claudio Leite <leitec@staticky.com> | |
| 3 | + * | |
| 4 | + * This file is licensed under the terms of the GNU General Public | |
| 5 | + * License version 2. This program is licensed "as is" without any | |
| 6 | + * warranty of any kind, whether express or implied. | |
| 7 | + */ | |
| 8 | + | |
| 9 | +/dts-v1/; | |
| 10 | + | |
| 11 | +#include "kirkwood.dtsi" | |
| 12 | +#include "kirkwood-6281.dtsi" | |
| 13 | + | |
| 14 | +/ { | |
| 15 | + model = "D-Link DIR-665"; | |
| 16 | + compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | |
| 17 | + | |
| 18 | + memory { | |
| 19 | + device_type = "memory"; | |
| 20 | + reg = <0x00000000 0x8000000>; /* 128 MB */ | |
| 21 | + }; | |
| 22 | + | |
| 23 | + chosen { | |
| 24 | + bootargs = "console=ttyS0,115200n8 earlyprintk"; | |
| 25 | + stdout-path = &uart0; | |
| 26 | + }; | |
| 27 | + | |
| 28 | + mbus { | |
| 29 | + pcie-controller { | |
| 30 | + status = "okay"; | |
| 31 | + | |
| 32 | + pcie@1,0 { | |
| 33 | + status = "okay"; | |
| 34 | + }; | |
| 35 | + }; | |
| 36 | + }; | |
| 37 | + | |
| 38 | + ocp@f1000000 { | |
| 39 | + pinctrl: pin-controller@10000 { | |
| 40 | + pinctrl-0 =< &pmx_led_usb | |
| 41 | + &pmx_led_internet_blue | |
| 42 | + &pmx_led_internet_amber | |
| 43 | + &pmx_led_5g &pmx_led_status_blue | |
| 44 | + &pmx_led_wps &pmx_led_status_amber | |
| 45 | + &pmx_led_24g | |
| 46 | + &pmx_btn_restart &pmx_btn_wps>; | |
| 47 | + pinctrl-names = "default"; | |
| 48 | + | |
| 49 | + pmx_led_usb: pmx-led-usb { | |
| 50 | + marvell,pins = "mpp12"; | |
| 51 | + marvell,function = "gpio"; | |
| 52 | + }; | |
| 53 | + pmx_led_internet_blue: pmx-led-internet-blue { | |
| 54 | + marvell,pins = "mpp42"; | |
| 55 | + marvell,function = "gpio"; | |
| 56 | + }; | |
| 57 | + pmx_led_internet_amber: pmx-led-internet-amber { | |
| 58 | + marvell,pins = "mpp43"; | |
| 59 | + marvell,function = "gpio"; | |
| 60 | + }; | |
| 61 | + pmx_led_5g: pmx-led-5g { | |
| 62 | + marvell,pins = "mpp44"; | |
| 63 | + marvell,function = "gpio"; | |
| 64 | + }; | |
| 65 | + pmx_led_status_blue: pmx-led-status-blue { | |
| 66 | + marvell,pins = "mpp45"; | |
| 67 | + marvell,function = "gpio"; | |
| 68 | + }; | |
| 69 | + pmx_led_wps: pmx-led-wps { | |
| 70 | + marvell,pins = "mpp47"; | |
| 71 | + marvell,function = "gpio"; | |
| 72 | + }; | |
| 73 | + pmx_led_status_amber: pmx-led-status-amber { | |
| 74 | + marvell,pins = "mpp48"; | |
| 75 | + marvell,function = "gpio"; | |
| 76 | + }; | |
| 77 | + pmx_led_24g: pmx-led-24g { | |
| 78 | + marvell,pins = "mpp49"; | |
| 79 | + marvell,function = "gpio"; | |
| 80 | + }; | |
| 81 | + pmx_btn_restart: pmx-btn-restart { | |
| 82 | + marvell,pins = "mpp28"; | |
| 83 | + marvell,function = "gpio"; | |
| 84 | + }; | |
| 85 | + pmx_btn_wps: pmx-btn-wps { | |
| 86 | + marvell,pins = "mpp46"; | |
| 87 | + marvell,function = "gpio"; | |
| 88 | + }; | |
| 89 | + }; | |
| 90 | + | |
| 91 | + spi@10600 { | |
| 92 | + status = "okay"; | |
| 93 | + m25p80@0 { | |
| 94 | + #address-cells = <1>; | |
| 95 | + #size-cells = <1>; | |
| 96 | + compatible = "mxicy,mx25l12805d"; | |
| 97 | + spi-max-frequency = <50000000>; | |
| 98 | + reg = <0>; | |
| 99 | + | |
| 100 | + partition@0 { | |
| 101 | + label = "uboot"; | |
| 102 | + reg = <0x0 0x30000>; | |
| 103 | + read-only; | |
| 104 | + }; | |
| 105 | + | |
| 106 | + partition@30000 { | |
| 107 | + label = "nvram"; | |
| 108 | + reg = <0x30000 0x10000>; | |
| 109 | + read-only; | |
| 110 | + }; | |
| 111 | + | |
| 112 | + partition@40000 { | |
| 113 | + label = "kernel"; | |
| 114 | + reg = <0x40000 0x180000>; | |
| 115 | + }; | |
| 116 | + | |
| 117 | + partition@1c0000 { | |
| 118 | + label = "rootfs"; | |
| 119 | + reg = <0x1c0000 0xe00000>; | |
| 120 | + }; | |
| 121 | + | |
| 122 | + cal_data: partition@fc0000 { | |
| 123 | + label = "cal_data"; | |
| 124 | + reg = <0xfc0000 0x10000>; | |
| 125 | + read-only; | |
| 126 | + }; | |
| 127 | + | |
| 128 | + partition@fd0000 { | |
| 129 | + label = "lang_pack"; | |
| 130 | + reg = <0xfd0000 0x30000>; | |
| 131 | + read-only; | |
| 132 | + }; | |
| 133 | + }; | |
| 134 | + }; | |
| 135 | + | |
| 136 | + serial@12000 { | |
| 137 | + status = "okay"; | |
| 138 | + }; | |
| 139 | + | |
| 140 | + i2c@11000 { | |
| 141 | + status = "okay"; | |
| 142 | + }; | |
| 143 | + | |
| 144 | + ehci@50000 { | |
| 145 | + status = "okay"; | |
| 146 | + }; | |
| 147 | + }; | |
| 148 | + | |
| 149 | + gpio-leds { | |
| 150 | + compatible = "gpio-leds"; | |
| 151 | + | |
| 152 | + blue-usb { | |
| 153 | + label = "dir665:blue:usb"; | |
| 154 | + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; | |
| 155 | + }; | |
| 156 | + blue-internet { | |
| 157 | + /* Can only be turned on if the Internet | |
| 158 | + * Ethernet port has Link | |
| 159 | + */ | |
| 160 | + label = "dir665:blue:internet"; | |
| 161 | + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; | |
| 162 | + }; | |
| 163 | + amber-internet { | |
| 164 | + label = "dir665:amber:internet"; | |
| 165 | + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; | |
| 166 | + }; | |
| 167 | + blue-wifi5g { | |
| 168 | + label = "dir665:blue:5g"; | |
| 169 | + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; | |
| 170 | + }; | |
| 171 | + blue-status { | |
| 172 | + label = "dir665:blue:status"; | |
| 173 | + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; | |
| 174 | + }; | |
| 175 | + blue-wps { | |
| 176 | + label = "dir665:blue:wps"; | |
| 177 | + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; | |
| 178 | + }; | |
| 179 | + amber-status { | |
| 180 | + label = "dir665:amber:status"; | |
| 181 | + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; | |
| 182 | + }; | |
| 183 | + blue-24g { | |
| 184 | + label = "dir665:blue:24g"; | |
| 185 | + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; | |
| 186 | + }; | |
| 187 | + }; | |
| 188 | + | |
| 189 | + gpio-keys { | |
| 190 | + compatible = "gpio-keys"; | |
| 191 | + #address-cells = <1>; | |
| 192 | + #size-cells = <0>; | |
| 193 | + | |
| 194 | + reset { | |
| 195 | + label = "reset"; | |
| 196 | + linux,code = <KEY_RESTART>; | |
| 197 | + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; | |
| 198 | + }; | |
| 199 | + wps { | |
| 200 | + label = "wps"; | |
| 201 | + linux,code = <KEY_WPS_BUTTON>; | |
| 202 | + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; | |
| 203 | + }; | |
| 204 | + }; | |
| 205 | + | |
| 206 | + dsa@0 { | |
| 207 | + compatible = "marvell,dsa"; | |
| 208 | + #address-cells = <2>; | |
| 209 | + #size-cells = <0>; | |
| 210 | + | |
| 211 | + dsa,ethernet = <ð0port>; | |
| 212 | + dsa,mii-bus = <&mdio>; | |
| 213 | + | |
| 214 | + switch@0 { | |
| 215 | + #address-cells = <1>; | |
| 216 | + #size-cells = <0>; | |
| 217 | + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ | |
| 218 | + | |
| 219 | + port@0 { | |
| 220 | + reg = <0>; | |
| 221 | + label = "lan4"; | |
| 222 | + }; | |
| 223 | + | |
| 224 | + port@1 { | |
| 225 | + reg = <1>; | |
| 226 | + label = "lan3"; | |
| 227 | + }; | |
| 228 | + | |
| 229 | + port@2 { | |
| 230 | + reg = <2>; | |
| 231 | + label = "lan2"; | |
| 232 | + }; | |
| 233 | + | |
| 234 | + port@3 { | |
| 235 | + reg = <3>; | |
| 236 | + label = "lan1"; | |
| 237 | + }; | |
| 238 | + | |
| 239 | + port@4 { | |
| 240 | + reg = <4>; | |
| 241 | + label = "wan"; | |
| 242 | + }; | |
| 243 | + | |
| 244 | + port@6 { | |
| 245 | + reg = <6>; | |
| 246 | + label = "cpu"; | |
| 247 | + }; | |
| 248 | + }; | |
| 249 | + }; | |
| 250 | +}; | |
| 251 | + | |
| 252 | +&mdio { | |
| 253 | + status = "okay"; | |
| 254 | +}; | |
| 255 | + | |
| 256 | +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set | |
| 257 | + * fixed speed and duplex. */ | |
| 258 | +ð0 { | |
| 259 | + status = "okay"; | |
| 260 | + | |
| 261 | + ethernet0-port@0 { | |
| 262 | + speed = <1000>; | |
| 263 | + duplex = <1>; | |
| 264 | + }; | |
| 265 | +}; | |
| 266 | + | |
| 267 | +/* eth1 is connected to the switch as well. However DSA only supports a | |
| 268 | + * single CPU port. So leave this port disabled to avoid confusion. */ | |
| 269 | + | |
| 270 | +ð1 { | |
| 271 | + status = "disabled"; | |
| 272 | +}; | |
| 273 | + | |
| 274 | +/* There is no battery on the boards, so the RTC does not keep time | |
| 275 | + * when there is no power, making it useless. */ | |
| 276 | +&rtc { | |
| 277 | + status = "disabled"; | |
| 278 | +}; | |
| @@ -266,7 +266,7 @@ · 265 unmodified lines | ||
| 266 | 266 | |
| 267 | 267 | s35390a: s35390a@30 { |
| 268 | 268 | status = "disabled"; |
| 269 | − compatible = "ssi,s35390a"; | |
| 269 | + compatible = "sii,s35390a"; | |
| 270 | 270 | reg = <0x30>; |
| 271 | 271 | }; |
| 272 | 272 | }; |
| @@ -0,0 +1,240 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2013-2014 Freescale Semiconductor, Inc. | |
| 3 | + * | |
| 4 | + * This file is dual-licensed: you can use it either under the terms | |
| 5 | + * of the GPL or the X11 license, at your option. Note that this dual | |
| 6 | + * licensing only applies to this file, and not this project as a | |
| 7 | + * whole. | |
| 8 | + * | |
| 9 | + * a) This file is free software; you can redistribute it and/or | |
| 10 | + * modify it under the terms of the GNU General Public License as | |
| 11 | + * published by the Free Software Foundation; either version 2 of | |
| 12 | + * the License, or (at your option) any later version. | |
| 13 | + * | |
| 14 | + * This file is distributed in the hope that it will be useful, | |
| 15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | + * GNU General Public License for more details. | |
| 18 | + * | |
| 19 | + * You should have received a copy of the GNU General Public | |
| 20 | + * License along with this file; if not, write to the Free | |
| 21 | + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
| 22 | + * MA 02110-1301 USA | |
| 23 | + * | |
| 24 | + * Or, alternatively, | |
| 25 | + * | |
| 26 | + * b) Permission is hereby granted, free of charge, to any person | |
| 27 | + * obtaining a copy of this software and associated documentation | |
| 28 | + * files (the "Software"), to deal in the Software without | |
| 29 | + * restriction, including without limitation the rights to use, | |
| 30 | + * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 31 | + * sell copies of the Software, and to permit persons to whom the | |
| 32 | + * Software is furnished to do so, subject to the following | |
| 33 | + * conditions: | |
| 34 | + * | |
| 35 | + * The above copyright notice and this permission notice shall be | |
| 36 | + * included in all copies or substantial portions of the Software. | |
| 37 | + * | |
| 38 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 39 | + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 40 | + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 41 | + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 42 | + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 43 | + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 44 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 45 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 46 | + */ | |
| 47 | + | |
| 48 | +/dts-v1/; | |
| 49 | +#include "ls1021a.dtsi" | |
| 50 | + | |
| 51 | +/ { | |
| 52 | + model = "LS1021A QDS Board"; | |
| 53 | + | |
| 54 | + aliases { | |
| 55 | + enet0_rgmii_phy = &rgmii_phy1; | |
| 56 | + enet1_rgmii_phy = &rgmii_phy2; | |
| 57 | + enet2_rgmii_phy = &rgmii_phy3; | |
| 58 | + enet0_sgmii_phy = &sgmii_phy1c; | |
| 59 | + enet1_sgmii_phy = &sgmii_phy1d; | |
| 60 | + }; | |
| 61 | +}; | |
| 62 | + | |
| 63 | +&dspi0 { | |
| 64 | + bus-num = <0>; | |
| 65 | + status = "okay"; | |
| 66 | + | |
| 67 | + dspiflash: at45db021d@0 { | |
| 68 | + #address-cells = <1>; | |
| 69 | + #size-cells = <1>; | |
| 70 | + compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; | |
| 71 | + spi-max-frequency = <16000000>; | |
| 72 | + spi-cpol; | |
| 73 | + spi-cpha; | |
| 74 | + reg = <0>; | |
| 75 | + }; | |
| 76 | +}; | |
| 77 | + | |
| 78 | +&i2c0 { | |
| 79 | + status = "okay"; | |
| 80 | + | |
| 81 | + pca9547: mux@77 { | |
| 82 | + reg = <0x77>; | |
| 83 | + #address-cells = <1>; | |
| 84 | + #size-cells = <0>; | |
| 85 | + | |
| 86 | + i2c@0 { | |
| 87 | + #address-cells = <1>; | |
| 88 | + #size-cells = <0>; | |
| 89 | + reg = <0x0>; | |
| 90 | + | |
| 91 | + ds3232: rtc@68 { | |
| 92 | + compatible = "dallas,ds3232"; | |
| 93 | + reg = <0x68>; | |
| 94 | + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; | |
| 95 | + }; | |
| 96 | + }; | |
| 97 | + | |
| 98 | + i2c@2 { | |
| 99 | + #address-cells = <1>; | |
| 100 | + #size-cells = <0>; | |
| 101 | + reg = <0x2>; | |
| 102 | + | |
| 103 | + ina220@40 { | |
| 104 | + compatible = "ti,ina220"; | |
| 105 | + reg = <0x40>; | |
| 106 | + shunt-resistor = <1000>; | |
| 107 | + }; | |
| 108 | + | |
| 109 | + ina220@41 { | |
| 110 | + compatible = "ti,ina220"; | |
| 111 | + reg = <0x41>; | |
| 112 | + shunt-resistor = <1000>; | |
| 113 | + }; | |
| 114 | + }; | |
| 115 | + | |
| 116 | + i2c@3 { | |
| 117 | + #address-cells = <1>; | |
| 118 | + #size-cells = <0>; | |
| 119 | + reg = <0x3>; | |
| 120 | + | |
| 121 | + eeprom@56 { | |
| 122 | + compatible = "atmel,24c512"; | |
| 123 | + reg = <0x56>; | |
| 124 | + }; | |
| 125 | + | |
| 126 | + eeprom@57 { | |
| 127 | + compatible = "atmel,24c512"; | |
| 128 | + reg = <0x57>; | |
| 129 | + }; | |
| 130 | + | |
| 131 | + adt7461a@4c { | |
| 132 | + compatible = "adi,adt7461a"; | |
| 133 | + reg = <0x4c>; | |
| 134 | + }; | |
| 135 | + }; | |
| 136 | + }; | |
| 137 | +}; | |
| 138 | + | |
| 139 | +&ifc { | |
| 140 | + #address-cells = <2>; | |
| 141 | + #size-cells = <1>; | |
| 142 | + /* NOR, NAND Flashes and FPGA on board */ | |
| 143 | + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 | |
| 144 | + 0x2 0x0 0x0 0x7e800000 0x00010000 | |
| 145 | + 0x3 0x0 0x0 0x7fb00000 0x00000100>; | |
| 146 | + status = "okay"; | |
| 147 | + | |
| 148 | + nor@0,0 { | |
| 149 | + #address-cells = <1>; | |
| 150 | + #size-cells = <1>; | |
| 151 | + compatible = "cfi-flash"; | |
| 152 | + reg = <0x0 0x0 0x8000000>; | |
| 153 | + bank-width = <2>; | |
| 154 | + device-width = <1>; | |
| 155 | + }; | |
| 156 | + | |
| 157 | + fpga: board-control@3,0 { | |
| 158 | + #address-cells = <1>; | |
| 159 | + #size-cells = <1>; | |
| 160 | + compatible = "simple-bus"; | |
| 161 | + reg = <0x3 0x0 0x0000100>; | |
| 162 | + bank-width = <1>; | |
| 163 | + device-width = <1>; | |
| 164 | + ranges = <0 3 0 0x100>; | |
| 165 | + | |
| 166 | + mdio-mux-emi1 { | |
| 167 | + compatible = "mdio-mux-mmioreg"; | |
| 168 | + mdio-parent-bus = <&mdio0>; | |
| 169 | + #address-cells = <1>; | |
| 170 | + #size-cells = <0>; | |
| 171 | + reg = <0x54 1>; /* BRDCFG4 */ | |
| 172 | + mux-mask = <0xe0>; /* EMI1[2:0] */ | |
| 173 | + | |
| 174 | + /* Onboard PHYs */ | |
| 175 | + ls1021amdio0: mdio@0 { | |
| 176 | + reg = <0>; | |
| 177 | + #address-cells = <1>; | |
| 178 | + #size-cells = <0>; | |
| 179 | + rgmii_phy1: ethernet-phy@1 { | |
| 180 | + reg = <0x1>; | |
| 181 | + }; | |
| 182 | + }; | |
| 183 | + | |
| 184 | + ls1021amdio1: mdio@20 { | |
| 185 | + reg = <0x20>; | |
| 186 | + #address-cells = <1>; | |
| 187 | + #size-cells = <0>; | |
| 188 | + rgmii_phy2: ethernet-phy@2 { | |
| 189 | + reg = <0x2>; | |
| 190 | + }; | |
| 191 | + }; | |
| 192 | + | |
| 193 | + ls1021amdio2: mdio@40 { | |
| 194 | + reg = <0x40>; | |
| 195 | + #address-cells = <1>; | |
| 196 | + #size-cells = <0>; | |
| 197 | + rgmii_phy3: ethernet-phy@3 { | |
| 198 | + reg = <0x3>; | |
| 199 | + }; | |
| 200 | + }; | |
| 201 | + | |
| 202 | + ls1021amdio3: mdio@60 { | |
| 203 | + reg = <0x60>; | |
| 204 | + #address-cells = <1>; | |
| 205 | + #size-cells = <0>; | |
| 206 | + sgmii_phy1c: ethernet-phy@1c { | |
| 207 | + reg = <0x1c>; | |
| 208 | + }; | |
| 209 | + }; | |
| 210 | + | |
| 211 | + ls1021amdio4: mdio@80 { | |
| 212 | + reg = <0x80>; | |
| 213 | + #address-cells = <1>; | |
| 214 | + #size-cells = <0>; | |
| 215 | + sgmii_phy1d: ethernet-phy@1d { | |
| 216 | + reg = <0x1d>; | |
| 217 | + }; | |
| 218 | + }; | |
| 219 | + }; | |
| 220 | + }; | |
| 221 | +}; | |
| 222 | + | |
| 223 | +&lpuart0 { | |
| 224 | + status = "okay"; | |
| 225 | +}; | |
| 226 | + | |
| 227 | +&mdio0 { | |
| 228 | + tbi0: tbi-phy@8 { | |
| 229 | + reg = <0x8>; | |
| 230 | + device_type = "tbi-phy"; | |
| 231 | + }; | |
| 232 | +}; | |
| 233 | + | |
| 234 | +&uart0 { | |
| 235 | + status = "okay"; | |
| 236 | +}; | |
| 237 | + | |
| 238 | +&uart1 { | |
| 239 | + status = "okay"; | |
| 240 | +}; | |
| @@ -0,0 +1,127 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2013-2014 Freescale Semiconductor, Inc. | |
| 3 | + * | |
| 4 | + * This file is dual-licensed: you can use it either under the terms | |
| 5 | + * of the GPL or the X11 license, at your option. Note that this dual | |
| 6 | + * licensing only applies to this file, and not this project as a | |
| 7 | + * whole. | |
| 8 | + * | |
| 9 | + * a) This file is free software; you can redistribute it and/or | |
| 10 | + * modify it under the terms of the GNU General Public License as | |
| 11 | + * published by the Free Software Foundation; either version 2 of | |
| 12 | + * the License, or (at your option) any later version. | |
| 13 | + * | |
| 14 | + * This file is distributed in the hope that it will be useful, | |
| 15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | + * GNU General Public License for more details. | |
| 18 | + * | |
| 19 | + * You should have received a copy of the GNU General Public | |
| 20 | + * License along with this file; if not, write to the Free | |
| 21 | + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
| 22 | + * MA 02110-1301 USA | |
| 23 | + * | |
| 24 | + * Or, alternatively, | |
| 25 | + * | |
| 26 | + * b) Permission is hereby granted, free of charge, to any person | |
| 27 | + * obtaining a copy of this software and associated documentation | |
| 28 | + * files (the "Software"), to deal in the Software without | |
| 29 | + * restriction, including without limitation the rights to use, | |
| 30 | + * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 31 | + * sell copies of the Software, and to permit persons to whom the | |
| 32 | + * Software is furnished to do so, subject to the following | |
| 33 | + * conditions: | |
| 34 | + * | |
| 35 | + * The above copyright notice and this permission notice shall be | |
| 36 | + * included in all copies or substantial portions of the Software. | |
| 37 | + * | |
| 38 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 39 | + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 40 | + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 41 | + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 42 | + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 43 | + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 44 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 45 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 46 | + */ | |
| 47 | + | |
| 48 | +/dts-v1/; | |
| 49 | +#include "ls1021a.dtsi" | |
| 50 | + | |
| 51 | +/ { | |
| 52 | + model = "LS1021A TWR Board"; | |
| 53 | + | |
| 54 | + aliases { | |
| 55 | + enet2_rgmii_phy = &rgmii_phy1; | |
| 56 | + enet0_sgmii_phy = &sgmii_phy2; | |
| 57 | + enet1_sgmii_phy = &sgmii_phy0; | |
| 58 | + }; | |
| 59 | +}; | |
| 60 | + | |
| 61 | +&dspi1 { | |
| 62 | + bus-num = <0>; | |
| 63 | + status = "okay"; | |
| 64 | + | |
| 65 | + dspiflash: s25fl064k@0 { | |
| 66 | + #address-cells = <1>; | |
| 67 | + #size-cells = <1>; | |
| 68 | + compatible = "spansion,s25fl064k"; | |
| 69 | + spi-max-frequency = <16000000>; | |
| 70 | + spi-cpol; | |
| 71 | + spi-cpha; | |
| 72 | + reg = <0>; | |
| 73 | + }; | |
| 74 | +}; | |
| 75 | + | |
| 76 | +&i2c0 { | |
| 77 | + status = "okay"; | |
| 78 | +}; | |
| 79 | + | |
| 80 | +&i2c1 { | |
| 81 | + status = "okay"; | |
| 82 | +}; | |
| 83 | + | |
| 84 | +&ifc { | |
| 85 | + #address-cells = <2>; | |
| 86 | + #size-cells = <1>; | |
| 87 | + /* NOR Flash on board */ | |
| 88 | + ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; | |
| 89 | + status = "okay"; | |
| 90 | + | |
| 91 | + nor@0,0 { | |
| 92 | + #address-cells = <1>; | |
| 93 | + #size-cells = <1>; | |
| 94 | + compatible = "cfi-flash"; | |
| 95 | + reg = <0x0 0x0 0x8000000>; | |
| 96 | + bank-width = <2>; | |
| 97 | + device-width = <1>; | |
| 98 | + }; | |
| 99 | +}; | |
| 100 | + | |
| 101 | +&lpuart0 { | |
| 102 | + status = "okay"; | |
| 103 | +}; | |
| 104 | + | |
| 105 | +&mdio0 { | |
| 106 | + sgmii_phy0: ethernet-phy@0 { | |
| 107 | + reg = <0x0>; | |
| 108 | + }; | |
| 109 | + rgmii_phy1: ethernet-phy@1 { | |
| 110 | + reg = <0x1>; | |
| 111 | + }; | |
| 112 | + sgmii_phy2: ethernet-phy@2 { | |
| 113 | + reg = <0x2>; | |
| 114 | + }; | |
| 115 | + tbi1: tbi-phy@1f { | |
| 116 | + reg = <0x1f>; | |
| 117 | + device_type = "tbi-phy"; | |
| 118 | + }; | |
| 119 | +}; | |
| 120 | + | |
| 121 | +&uart0 { | |
| 122 | + status = "okay"; | |
| 123 | +}; | |
| 124 | + | |
| 125 | +&uart1 { | |
| 126 | + status = "okay"; | |
| 127 | +}; | |
| @@ -0,0 +1,408 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2013-2014 Freescale Semiconductor, Inc. | |
| 3 | + * | |
| 4 | + * This file is dual-licensed: you can use it either under the terms | |
| 5 | + * of the GPL or the X11 license, at your option. Note that this dual | |
| 6 | + * licensing only applies to this file, and not this project as a | |
| 7 | + * whole. | |
| 8 | + * | |
| 9 | + * a) This file is free software; you can redistribute it and/or | |
| 10 | + * modify it under the terms of the GNU General Public License as | |
| 11 | + * published by the Free Software Foundation; either version 2 of | |
| 12 | + * the License, or (at your option) any later version. | |
| 13 | + * | |
| 14 | + * This file is distributed in the hope that it will be useful, | |
| 15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | + * GNU General Public License for more details. | |
| 18 | + * | |
| 19 | + * You should have received a copy of the GNU General Public | |
| 20 | + * License along with this file; if not, write to the Free | |
| 21 | + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
| 22 | + * MA 02110-1301 USA | |
| 23 | + * | |
| 24 | + * Or, alternatively, | |
| 25 | + * | |
| 26 | + * b) Permission is hereby granted, free of charge, to any person | |
| 27 | + * obtaining a copy of this software and associated documentation | |
| 28 | + * files (the "Software"), to deal in the Software without | |
| 29 | + * restriction, including without limitation the rights to use, | |
| 30 | + * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 31 | + * sell copies of the Software, and to permit persons to whom the | |
| 32 | + * Software is furnished to do so, subject to the following | |
| 33 | + * conditions: | |
| 34 | + * | |
| 35 | + * The above copyright notice and this permission notice shall be | |
| 36 | + * included in all copies or substantial portions of the Software. | |
| 37 | + * | |
| 38 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 39 | + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 40 | + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 41 | + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 42 | + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 43 | + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 44 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 45 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 46 | + */ | |
| 47 | + | |
| 48 | +#include "skeleton64.dtsi" | |
| 49 | +#include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 50 | + | |
| 51 | +/ { | |
| 52 | + compatible = "fsl,ls1021a"; | |
| 53 | + interrupt-parent = <&gic>; | |
| 54 | + | |
| 55 | + aliases { | |
| 56 | + serial0 = &lpuart0; | |
| 57 | + serial1 = &lpuart1; | |
| 58 | + serial2 = &lpuart2; | |
| 59 | + serial3 = &lpuart3; | |
| 60 | + serial4 = &lpuart4; | |
| 61 | + serial5 = &lpuart5; | |
| 62 | + sysclk = &sysclk; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + cpus { | |
| 66 | + #address-cells = <1>; | |
| 67 | + #size-cells = <0>; | |
| 68 | + | |
| 69 | + cpu@f00 { | |
| 70 | + compatible = "arm,cortex-a7"; | |
| 71 | + device_type = "cpu"; | |
| 72 | + reg = <0xf00>; | |
| 73 | + clocks = <&cluster1_clk>; | |
| 74 | + }; | |
| 75 | + | |
| 76 | + cpu@f01 { | |
| 77 | + compatible = "arm,cortex-a7"; | |
| 78 | + device_type = "cpu"; | |
| 79 | + reg = <0xf01>; | |
| 80 | + clocks = <&cluster1_clk>; | |
| 81 | + }; | |
| 82 | + }; | |
| 83 | + | |
| 84 | + timer { | |
| 85 | + compatible = "arm,armv7-timer"; | |
| 86 | + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
| 87 | + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
| 88 | + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
| 89 | + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
| 90 | + }; | |
| 91 | + | |
| 92 | + pmu { | |
| 93 | + compatible = "arm,cortex-a7-pmu"; | |
| 94 | + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
| 95 | + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; | |
| 96 | + }; | |
| 97 | + | |
| 98 | + soc { | |
| 99 | + compatible = "simple-bus"; | |
| 100 | + #address-cells = <2>; | |
| 101 | + #size-cells = <2>; | |
| 102 | + device_type = "soc"; | |
| 103 | + interrupt-parent = <&gic>; | |
| 104 | + ranges; | |
| 105 | + | |
| 106 | + gic: interrupt-controller@1400000 { | |
| 107 | + compatible = "arm,cortex-a7-gic"; | |
| 108 | + #interrupt-cells = <3>; | |
| 109 | + interrupt-controller; | |
| 110 | + reg = <0x0 0x1401000 0x0 0x1000>, | |
| 111 | + <0x0 0x1402000 0x0 0x1000>, | |
| 112 | + <0x0 0x1404000 0x0 0x2000>, | |
| 113 | + <0x0 0x1406000 0x0 0x2000>; | |
| 114 | + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 115 | + | |
| 116 | + }; | |
| 117 | + | |
| 118 | + ifc: ifc@1530000 { | |
| 119 | + compatible = "fsl,ifc", "simple-bus"; | |
| 120 | + reg = <0x0 0x1530000 0x0 0x10000>; | |
| 121 | + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 122 | + }; | |
| 123 | + | |
| 124 | + dcfg: dcfg@1ee0000 { | |
| 125 | + compatible = "fsl,ls1021a-dcfg", "syscon"; | |
| 126 | + reg = <0x0 0x1ee0000 0x0 0x10000>; | |
| 127 | + big-endian; | |
| 128 | + }; | |
| 129 | + | |
| 130 | + esdhc: esdhc@1560000 { | |
| 131 | + compatible = "fsl,esdhc"; | |
| 132 | + reg = <0x0 0x1560000 0x0 0x10000>; | |
| 133 | + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
| 134 | + clock-frequency = <0>; | |
| 135 | + voltage-ranges = <1800 1800 3300 3300>; | |
| 136 | + sdhci,auto-cmd12; | |
| 137 | + big-endian; | |
| 138 | + bus-width = <4>; | |
| 139 | + status = "disabled"; | |
| 140 | + }; | |
| 141 | + | |
| 142 | + scfg: scfg@1570000 { | |
| 143 | + compatible = "fsl,ls1021a-scfg", "syscon"; | |
| 144 | + reg = <0x0 0x1570000 0x0 0x10000>; | |
| 145 | + }; | |
| 146 | + | |
| 147 | + clockgen: clocking@1ee1000 { | |
| 148 | + #address-cells = <1>; | |
| 149 | + #size-cells = <1>; | |
| 150 | + ranges = <0x0 0x0 0x1ee1000 0x10000>; | |
| 151 | + | |
| 152 | + sysclk: sysclk { | |
| 153 | + compatible = "fixed-clock"; | |
| 154 | + #clock-cells = <0>; | |
| 155 | + clock-output-names = "sysclk"; | |
| 156 | + }; | |
| 157 | + | |
| 158 | + cga_pll1: pll@800 { | |
| 159 | + compatible = "fsl,qoriq-core-pll-2.0"; | |
| 160 | + #clock-cells = <1>; | |
| 161 | + reg = <0x800 0x10>; | |
| 162 | + clocks = <&sysclk>; | |
| 163 | + clock-output-names = "cga-pll1", "cga-pll1-div2", | |
| 164 | + "cga-pll1-div4"; | |
| 165 | + }; | |
| 166 | + | |
| 167 | + platform_clk: pll@c00 { | |
| 168 | + compatible = "fsl,qoriq-core-pll-2.0"; | |
| 169 | + #clock-cells = <1>; | |
| 170 | + reg = <0xc00 0x10>; | |
| 171 | + clocks = <&sysclk>; | |
| 172 | + clock-output-names = "platform-clk", "platform-clk-div2"; | |
| 173 | + }; | |
| 174 | + | |
| 175 | + cluster1_clk: clk0c0@0 { | |
| 176 | + compatible = "fsl,qoriq-core-mux-2.0"; | |
| 177 | + #clock-cells = <0>; | |
| 178 | + reg = <0x0 0x10>; | |
| 179 | + clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; | |
| 180 | + clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; | |
| 181 | + clock-output-names = "cluster1-clk"; | |
| 182 | + }; | |
| 183 | + }; | |
| 184 | + | |
| 185 | + dspi0: dspi@2100000 { | |
| 186 | + compatible = "fsl,vf610-dspi"; | |
| 187 | + #address-cells = <1>; | |
| 188 | + #size-cells = <0>; | |
| 189 | + reg = <0x0 0x2100000 0x0 0x10000>; | |
| 190 | + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 191 | + clock-names = "dspi"; | |
| 192 | + clocks = <&platform_clk 1>; | |
| 193 | + spi-num-chipselects = <5>; | |
| 194 | + big-endian; | |
| 195 | + status = "disabled"; | |
| 196 | + }; | |
| 197 | + | |
| 198 | + dspi1: dspi@2110000 { | |
| 199 | + compatible = "fsl,vf610-dspi"; | |
| 200 | + #address-cells = <1>; | |
| 201 | + #size-cells = <0>; | |
| 202 | + reg = <0x0 0x2110000 0x0 0x10000>; | |
| 203 | + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
| 204 | + clock-names = "dspi"; | |
| 205 | + clocks = <&platform_clk 1>; | |
| 206 | + spi-num-chipselects = <5>; | |
| 207 | + big-endian; | |
| 208 | + status = "disabled"; | |
| 209 | + }; | |
| 210 | + | |
| 211 | + i2c0: i2c@2180000 { | |
| 212 | + compatible = "fsl,vf610-i2c"; | |
| 213 | + #address-cells = <1>; | |
| 214 | + #size-cells = <0>; | |
| 215 | + reg = <0x0 0x2180000 0x0 0x10000>; | |
| 216 | + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
| 217 | + clock-names = "i2c"; | |
| 218 | + clocks = <&platform_clk 1>; | |
| 219 | + status = "disabled"; | |
| 220 | + }; | |
| 221 | + | |
| 222 | + i2c1: i2c@2190000 { | |
| 223 | + compatible = "fsl,vf610-i2c"; | |
| 224 | + #address-cells = <1>; | |
| 225 | + #size-cells = <0>; | |
| 226 | + reg = <0x0 0x2190000 0x0 0x10000>; | |
| 227 | + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
| 228 | + clock-names = "i2c"; | |
| 229 | + clocks = <&platform_clk 1>; | |
| 230 | + status = "disabled"; | |
| 231 | + }; | |
| 232 | + | |
| 233 | + i2c2: i2c@21a0000 { | |
| 234 | + compatible = "fsl,vf610-i2c"; | |
| 235 | + #address-cells = <1>; | |
| 236 | + #size-cells = <0>; | |
| 237 | + reg = <0x0 0x21a0000 0x0 0x10000>; | |
| 238 | + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 239 | + clock-names = "i2c"; | |
| 240 | + clocks = <&platform_clk 1>; | |
| 241 | + status = "disabled"; | |
| 242 | + }; | |
| 243 | + | |
| 244 | + uart0: serial@21c0500 { | |
| 245 | + compatible = "fsl,16550-FIFO64", "ns16550a"; | |
| 246 | + reg = <0x0 0x21c0500 0x0 0x100>; | |
| 247 | + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 248 | + clock-frequency = <0>; | |
| 249 | + fifo-size = <15>; | |
| 250 | + status = "disabled"; | |
| 251 | + }; | |
| 252 | + | |
| 253 | + uart1: serial@21c0600 { | |
| 254 | + compatible = "fsl,16550-FIFO64", "ns16550a"; | |
| 255 | + reg = <0x0 0x21c0600 0x0 0x100>; | |
| 256 | + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 257 | + clock-frequency = <0>; | |
| 258 | + fifo-size = <15>; | |
| 259 | + status = "disabled"; | |
| 260 | + }; | |
| 261 | + | |
| 262 | + uart2: serial@21d0500 { | |
| 263 | + compatible = "fsl,16550-FIFO64", "ns16550a"; | |
| 264 | + reg = <0x0 0x21d0500 0x0 0x100>; | |
| 265 | + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 266 | + clock-frequency = <0>; | |
| 267 | + fifo-size = <15>; | |
| 268 | + status = "disabled"; | |
| 269 | + }; | |
| 270 | + | |
| 271 | + uart3: serial@21d0600 { | |
| 272 | + compatible = "fsl,16550-FIFO64", "ns16550a"; | |
| 273 | + reg = <0x0 0x21d0600 0x0 0x100>; | |
| 274 | + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 275 | + clock-frequency = <0>; | |
| 276 | + fifo-size = <15>; | |
| 277 | + status = "disabled"; | |
| 278 | + }; | |
| 279 | + | |
| 280 | + lpuart0: serial@2950000 { | |
| 281 | + compatible = "fsl,ls1021a-lpuart"; | |
| 282 | + reg = <0x0 0x2950000 0x0 0x1000>; | |
| 283 | + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
| 284 | + clocks = <&sysclk>; | |
| 285 | + clock-names = "ipg"; | |
| 286 | + status = "disabled"; | |
| 287 | + }; | |
| 288 | + | |
| 289 | + lpuart1: serial@2960000 { | |
| 290 | + compatible = "fsl,ls1021a-lpuart"; | |
| 291 | + reg = <0x0 0x2960000 0x0 0x1000>; | |
| 292 | + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| 293 | + clocks = <&platform_clk 1>; | |
| 294 | + clock-names = "ipg"; | |
| 295 | + status = "disabled"; | |
| 296 | + }; | |
| 297 | + | |
| 298 | + lpuart2: serial@2970000 { | |
| 299 | + compatible = "fsl,ls1021a-lpuart"; | |
| 300 | + reg = <0x0 0x2970000 0x0 0x1000>; | |
| 301 | + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
| 302 | + clocks = <&platform_clk 1>; | |
| 303 | + clock-names = "ipg"; | |
| 304 | + status = "disabled"; | |
| 305 | + }; | |
| 306 | + | |
| 307 | + lpuart3: serial@2980000 { | |
| 308 | + compatible = "fsl,ls1021a-lpuart"; | |
| 309 | + reg = <0x0 0x2980000 0x0 0x1000>; | |
| 310 | + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
| 311 | + clocks = <&platform_clk 1>; | |
| 312 | + clock-names = "ipg"; | |
| 313 | + status = "disabled"; | |
| 314 | + }; | |
| 315 | + | |
| 316 | + lpuart4: serial@2990000 { | |
| 317 | + compatible = "fsl,ls1021a-lpuart"; | |
| 318 | + reg = <0x0 0x2990000 0x0 0x1000>; | |
| 319 | + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| 320 | + clocks = <&platform_clk 1>; | |
| 321 | + clock-names = "ipg"; | |
| 322 | + status = "disabled"; | |
| 323 | + }; | |
| 324 | + | |
| 325 | + lpuart5: serial@29a0000 { | |
| 326 | + compatible = "fsl,ls1021a-lpuart"; | |
| 327 | + reg = <0x0 0x29a0000 0x0 0x1000>; | |
| 328 | + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
| 329 | + clocks = <&platform_clk 1>; | |
| 330 | + clock-names = "ipg"; | |
| 331 | + status = "disabled"; | |
| 332 | + }; | |
| 333 | + | |
| 334 | + wdog0: watchdog@2ad0000 { | |
| 335 | + compatible = "fsl,imx21-wdt"; | |
| 336 | + reg = <0x0 0x2ad0000 0x0 0x10000>; | |
| 337 | + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
| 338 | + clocks = <&platform_clk 1>; | |
| 339 | + clock-names = "wdog-en"; | |
| 340 | + big-endian; | |
| 341 | + }; | |
| 342 | + | |
| 343 | + sai1: sai@2b50000 { | |
| 344 | + compatible = "fsl,vf610-sai"; | |
| 345 | + reg = <0x0 0x2b50000 0x0 0x10000>; | |
| 346 | + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
| 347 | + clocks = <&platform_clk 1>; | |
| 348 | + clock-names = "sai"; | |
| 349 | + dma-names = "tx", "rx"; | |
| 350 | + dmas = <&edma0 1 47>, | |
| 351 | + <&edma0 1 46>; | |
| 352 | + big-endian; | |
| 353 | + status = "disabled"; | |
| 354 | + }; | |
| 355 | + | |
| 356 | + sai2: sai@2b60000 { | |
| 357 | + compatible = "fsl,vf610-sai"; | |
| 358 | + reg = <0x0 0x2b60000 0x0 0x10000>; | |
| 359 | + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
| 360 | + clocks = <&platform_clk 1>; | |
| 361 | + clock-names = "sai"; | |
| 362 | + dma-names = "tx", "rx"; | |
| 363 | + dmas = <&edma0 1 45>, | |
| 364 | + <&edma0 1 44>; | |
| 365 | + big-endian; | |
| 366 | + status = "disabled"; | |
| 367 | + }; | |
| 368 | + | |
| 369 | + edma0: edma@2c00000 { | |
| 370 | + #dma-cells = <2>; | |
| 371 | + compatible = "fsl,vf610-edma"; | |
| 372 | + reg = <0x0 0x2c00000 0x0 0x10000>, | |
| 373 | + <0x0 0x2c10000 0x0 0x10000>, | |
| 374 | + <0x0 0x2c20000 0x0 0x10000>; | |
| 375 | + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 376 | + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
| 377 | + interrupt-names = "edma-tx", "edma-err"; | |
| 378 | + dma-channels = <32>; | |
| 379 | + big-endian; | |
| 380 | + clock-names = "dmamux0", "dmamux1"; | |
| 381 | + clocks = <&platform_clk 1>, | |
| 382 | + <&platform_clk 1>; | |
| 383 | + }; | |
| 384 | + | |
| 385 | + mdio0: mdio@2d24000 { | |
| 386 | + compatible = "gianfar"; | |
| 387 | + device_type = "mdio"; | |
| 388 | + #address-cells = <1>; | |
| 389 | + #size-cells = <0>; | |
| 390 | + reg = <0x0 0x2d24000 0x0 0x4000>; | |
| 391 | + }; | |
| 392 | + | |
| 393 | + usb@8600000 { | |
| 394 | + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; | |
| 395 | + reg = <0x0 0x8600000 0x0 0x1000>; | |
| 396 | + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; | |
| 397 | + dr_mode = "host"; | |
| 398 | + phy_type = "ulpi"; | |
| 399 | + }; | |
| 400 | + | |
| 401 | + usb3@3100000 { | |
| 402 | + compatible = "snps,dwc3"; | |
| 403 | + reg = <0x0 0x3100000 0x0 0x10000>; | |
| 404 | + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
| 405 | + dr_mode = "host"; | |
| 406 | + }; | |
| 407 | + }; | |
| 408 | +}; | |
| @@ -50,6 +50,13 @@ · 49 unmodified lines | ||
| 50 | 50 | / { |
| 51 | 51 | interrupt-parent = <&gic>; |
| 52 | 52 | |
| 53 | + L2: l2-cache-controller@c4200000 { | |
| 54 | + compatible = "arm,pl310-cache"; | |
| 55 | + reg = <0xc4200000 0x1000>; | |
| 56 | + cache-unified; | |
| 57 | + cache-level = <2>; | |
| 58 | + }; | |
| 59 | + | |
| 53 | 60 | gic: interrupt-controller@c4301000 { |
| 54 | 61 | compatible = "arm,cortex-a9-gic"; |
| 55 | 62 | reg = <0xc4301000 0x1000>, |
| @@ -106,5 +113,35 @@ · 50 unmodified lines | ||
| 106 | 113 | clocks = <&clk81>; |
| 107 | 114 | status = "disabled"; |
| 108 | 115 | }; |
| 116 | + | |
| 117 | + i2c_AO: i2c@c8100500 { | |
| 118 | + compatible = "amlogic,meson6-i2c"; | |
| 119 | + reg = <0xc8100500 0x20>; | |
| 120 | + interrupts = <0 92 1>; | |
| 121 | + clocks = <&clk81>; | |
| 122 | + #address-cells = <1>; | |
| 123 | + #size-cells = <0>; | |
| 124 | + status = "disabled"; | |
| 125 | + }; | |
| 126 | + | |
| 127 | + i2c_A: i2c@c1108500 { | |
| 128 | + compatible = "amlogic,meson6-i2c"; | |
| 129 | + reg = <0xc1108500 0x20>; | |
| 130 | + interrupts = <0 21 1>; | |
| 131 | + clocks = <&clk81>; | |
| 132 | + #address-cells = <1>; | |
| 133 | + #size-cells = <0>; | |
| 134 | + status = "disabled"; | |
| 135 | + }; | |
| 136 | + | |
| 137 | + i2c_B: i2c@c11087c0 { | |
| 138 | + compatible = "amlogic,meson6-i2c"; | |
| 139 | + reg = <0xc11087c0 0x20>; | |
| 140 | + interrupts = <0 128 1>; | |
| 141 | + clocks = <&clk81>; | |
| 142 | + #address-cells = <1>; | |
| 143 | + #size-cells = <0>; | |
| 144 | + status = "disabled"; | |
| 145 | + }; | |
| 109 | 146 | }; |
| 110 | 147 | }; /* end of / */ |
| @@ -50,7 +50,7 @@ · 49 unmodified lines | ||
| 50 | 50 | |
| 51 | 51 | / { |
| 52 | 52 | model = "Geniatech ATV1200"; |
| 53 | − compatible = "geniatech,atv1200"; | |
| 53 | + compatible = "geniatech,atv1200", "amlogic,meson6"; | |
| 54 | 54 | |
| 55 | 55 | aliases { |
| 56 | 56 | serial0 = &uart_AO; |
| @@ -60,12 +60,14 @@ · 59 unmodified lines | ||
| 60 | 60 | cpu@200 { |
| 61 | 61 | device_type = "cpu"; |
| 62 | 62 | compatible = "arm,cortex-a9"; |
| 63 | + next-level-cache = <&L2>; | |
| 63 | 64 | reg = <0x200>; |
| 64 | 65 | }; |
| 65 | 66 | |
| 66 | 67 | cpu@201 { |
| 67 | 68 | device_type = "cpu"; |
| 68 | 69 | compatible = "arm,cortex-a9"; |
| 70 | + next-level-cache = <&L2>; | |
| 69 | 71 | reg = <0x201>; |
| 70 | 72 | }; |
| 71 | 73 | }; |
| @@ -0,0 +1,92 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright 2014 Carlo Caione <carlo@caione.org> | |
| 3 | + * | |
| 4 | + * This file is dual-licensed: you can use it either under the terms | |
| 5 | + * of the GPL or the X11 license, at your option. Note that this dual | |
| 6 | + * licensing only applies to this file, and not this project as a | |
| 7 | + * whole. | |
| 8 | + * | |
| 9 | + * a) This library is free software; you can redistribute it and/or | |
| 10 | + * modify it under the terms of the GNU General Public License as | |
| 11 | + * published by the Free Software Foundation; either version 2 of the | |
| 12 | + * License, or (at your option) any later version. | |
| 13 | + * | |
| 14 | + * This library is distributed in the hope that it will be useful, | |
| 15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | + * GNU General Public License for more details. | |
| 18 | + * | |
| 19 | + * You should have received a copy of the GNU General Public License | |
| 20 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 21 | + * | |
| 22 | + * Or, alternatively, | |
| 23 | + * | |
| 24 | + * b) Permission is hereby granted, free of charge, to any person | |
| 25 | + * obtaining a copy of this software and associated documentation | |
| 26 | + * files (the "Software"), to deal in the Software without | |
| 27 | + * restriction, including without limitation the rights to use, | |
| 28 | + * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 29 | + * sell copies of the Software, and to permit persons to whom the | |
| 30 | + * Software is furnished to do so, subject to the following | |
| 31 | + * conditions: | |
| 32 | + * | |
| 33 | + * The above copyright notice and this permission notice shall be | |
| 34 | + * included in all copies or substantial portions of the Software. | |
| 35 | + * | |
| 36 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 37 | + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 38 | + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 39 | + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 40 | + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 41 | + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 42 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 43 | + * OTHER DEALINGS IN THE SOFTWARE. | |
| 44 | + */ | |
| 45 | + | |
| 46 | +/include/ "meson.dtsi" | |
| 47 | + | |
| 48 | +/ { | |
| 49 | + model = "Amlogic Meson8 SoC"; | |
| 50 | + compatible = "amlogic,meson8"; | |
| 51 | + | |
| 52 | + interrupt-parent = <&gic>; | |
| 53 | + | |
| 54 | + cpus { | |
| 55 | + #address-cells = <1>; | |
| 56 | + #size-cells = <0>; | |
| 57 | + | |
| 58 | + cpu@200 { | |
| 59 | + device_type = "cpu"; | |
| 60 | + compatible = "arm,cortex-a9"; | |
| 61 | + next-level-cache = <&L2>; | |
| 62 | + reg = <0x200>; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + cpu@201 { | |
| 66 | + device_type = "cpu"; | |
| 67 | + compatible = "arm,cortex-a9"; | |
| 68 | + next-level-cache = <&L2>; | |
| 69 | + reg = <0x201>; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + cpu@202 { | |
| 73 | + device_type = "cpu"; | |
| 74 | + compatible = "arm,cortex-a9"; | |
| 75 | + next-level-cache = <&L2>; | |
| 76 | + reg = <0x202>; | |
| 77 | + }; | |
| 78 | + | |
| 79 | + cpu@203 { | |
| 80 | + device_type = "cpu"; | |
| 81 | + compatible = "arm,cortex-a9"; | |
| 82 | + next-level-cache = <&L2>; | |
| 83 | + reg = <0x203>; | |
| 84 | + }; | |
| 85 | + }; | |
| 86 | + | |
| 87 | + clk81: clk@0 { | |
| 88 | + #clock-cells = <0>; | |
| 89 | + compatible = "fixed-clock"; | |
| 90 | + clock-frequency = <141666666>; | |
| 91 | + }; | |
| 92 | +}; /* end of / */ | |
| @@ -0,0 +1,26 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (c) 2014 MediaTek Inc. | |
| 3 | + * Author: Howard Chen <ibanezchen@gmail.com> | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * published by the Free Software Foundation. | |
| 8 | + * | |
| 9 | + * This program is distributed in the hope that it will be useful, | |
| 10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | + * GNU General Public License for more details. | |
| 13 | + */ | |
| 14 | + | |
| 15 | +/dts-v1/; | |
| 16 | +#include "mt6592.dtsi" | |
| 17 | + | |
| 18 | +/ { | |
| 19 | + model = "mt6592 evb"; | |
| 20 | + compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + reg = <0x80000000 0x40000000>; | |
| 24 | + }; | |
| 25 | +}; | |
| 26 | + | |
| @@ -0,0 +1,98 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (c) 2014 MediaTek Inc. | |
| 3 | + * Author: Howard Chen <ibanezchen@gmail.com> | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * published by the Free Software Foundation. | |
| 8 | + * | |
| 9 | + * This program is distributed in the hope that it will be useful, | |
| 10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | + * GNU General Public License for more details. | |
| 13 | + */ | |
| 14 | + | |
| 15 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 16 | +#include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 17 | +#include "skeleton.dtsi" | |
| 18 | + | |
| 19 | +/ { | |
| 20 | + compatible = "mediatek,mt6592"; | |
| 21 | + interrupt-parent = <&gic>; | |
| 22 | + | |
| 23 | + cpus { | |
| 24 | + #address-cells = <1>; | |
| 25 | + #size-cells = <0>; | |
| 26 | + | |
| 27 | + cpu@0 { | |
| 28 | + device_type = "cpu"; | |
| 29 | + compatible = "arm,cortex-a7"; | |
| 30 | + reg = <0x0>; | |
| 31 | + }; | |
| 32 | + cpu@1 { | |
| 33 | + device_type = "cpu"; | |
| 34 | + compatible = "arm,cortex-a7"; | |
| 35 | + reg = <0x1>; | |
| 36 | + }; | |
| 37 | + cpu@2 { | |
| 38 | + device_type = "cpu"; | |
| 39 | + compatible = "arm,cortex-a7"; | |
| 40 | + reg = <0x2>; | |
| 41 | + }; | |
| 42 | + cpu@3 { | |
| 43 | + device_type = "cpu"; | |
| 44 | + compatible = "arm,cortex-a7"; | |
| 45 | + reg = <0x3>; | |
| 46 | + }; | |
| 47 | + cpu@4 { | |
| 48 | + device_type = "cpu"; | |
| 49 | + compatible = "arm,cortex-a7"; | |
| 50 | + reg = <0x4>; | |
| 51 | + }; | |
| 52 | + cpu@5 { | |
| 53 | + device_type = "cpu"; | |
| 54 | + compatible = "arm,cortex-a7"; | |
| 55 | + reg = <0x5>; | |
| 56 | + }; | |
| 57 | + cpu@6 { | |
| 58 | + device_type = "cpu"; | |
| 59 | + compatible = "arm,cortex-a7"; | |
| 60 | + reg = <0x6>; | |
| 61 | + }; | |
| 62 | + cpu@7 { | |
| 63 | + device_type = "cpu"; | |
| 64 | + compatible = "arm,cortex-a7"; | |
| 65 | + reg = <0x7>; | |
| 66 | + }; | |
| 67 | + }; | |
| 68 | + | |
| 69 | + system_clk: dummy13m { | |
| 70 | + compatible = "fixed-clock"; | |
| 71 | + clock-frequency = <13000000>; | |
| 72 | + #clock-cells = <0>; | |
| 73 | + }; | |
| 74 | + | |
| 75 | + rtc_clk: dummy32k { | |
| 76 | + compatible = "fixed-clock"; | |
| 77 | + clock-frequency = <32000>; | |
| 78 | + #clock-cells = <0>; | |
| 79 | + }; | |
| 80 | + | |
| 81 | + timer: timer@10008000 { | |
| 82 | + compatible = "mediatek,mt6577-timer"; | |
| 83 | + reg = <0x10008000 0x80>; | |
| 84 | + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
| 85 | + clocks = <&system_clk>, <&rtc_clk>; | |
| 86 | + clock-names = "system-clk", "rtc-clk"; | |
| 87 | + }; | |
| 88 | + | |
| 89 | + gic: interrupt-controller@10211000 { | |
| 90 | + compatible = "arm,cortex-a7-gic"; | |
| 91 | + interrupt-controller; | |
| 92 | + #interrupt-cells = <3>; | |
| 93 | + reg = <0x10211000 0x1000>, | |
| 94 | + <0x10212000 0x1000>; | |
| 95 | + }; | |
| 96 | + | |
| 97 | +}; | |
| 98 | + | |
| @@ -0,0 +1,25 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (c) 2014 MediaTek Inc. | |
| 3 | + * Author: Joe.C <yingjoe.chen@mediatek.com> | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * published by the Free Software Foundation. | |
| 8 | + * | |
| 9 | + * This program is distributed in the hope that it will be useful, | |
| 10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | + * GNU General Public License for more details. | |
| 13 | + */ | |
| 14 | + | |
| 15 | +/dts-v1/; | |
| 16 | +#include "mt8127.dtsi" | |
| 17 | + | |
| 18 | +/ { | |
| 19 | + model = "MediaTek MT8127 Moose Board"; | |
| 20 | + compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + reg = <0 0x80000000 0 0x40000000>; | |
| 24 | + }; | |
| 25 | +}; | |
| @@ -0,0 +1,94 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (c) 2014 MediaTek Inc. | |
| 3 | + * Author: Joe.C <yingjoe.chen@mediatek.com> | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * published by the Free Software Foundation. | |
| 8 | + * | |
| 9 | + * This program is distributed in the hope that it will be useful, | |
| 10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | + * GNU General Public License for more details. | |
| 13 | + */ | |
| 14 | + | |
| 15 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 16 | +#include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 17 | +#include "skeleton64.dtsi" | |
| 18 | + | |
| 19 | +/ { | |
| 20 | + compatible = "mediatek,mt8127"; | |
| 21 | + interrupt-parent = <&gic>; | |
| 22 | + | |
| 23 | + cpus { | |
| 24 | + #address-cells = <1>; | |
| 25 | + #size-cells = <0>; | |
| 26 | + | |
| 27 | + cpu@0 { | |
| 28 | + device_type = "cpu"; | |
| 29 | + compatible = "arm,cortex-a7"; | |
| 30 | + reg = <0x0>; | |
| 31 | + }; | |
| 32 | + cpu@1 { | |
| 33 | + device_type = "cpu"; | |
| 34 | + compatible = "arm,cortex-a7"; | |
| 35 | + reg = <0x1>; | |
| 36 | + }; | |
| 37 | + cpu@2 { | |
| 38 | + device_type = "cpu"; | |
| 39 | + compatible = "arm,cortex-a7"; | |
| 40 | + reg = <0x2>; | |
| 41 | + }; | |
| 42 | + cpu@3 { | |
| 43 | + device_type = "cpu"; | |
| 44 | + compatible = "arm,cortex-a7"; | |
| 45 | + reg = <0x3>; | |
| 46 | + }; | |
| 47 | + | |
| 48 | + }; | |
| 49 | + | |
| 50 | + clocks { | |
| 51 | + #address-cells = <2>; | |
| 52 | + #size-cells = <2>; | |
| 53 | + compatible = "simple-bus"; | |
| 54 | + ranges; | |
| 55 | + | |
| 56 | + system_clk: dummy13m { | |
| 57 | + compatible = "fixed-clock"; | |
| 58 | + clock-frequency = <13000000>; | |
| 59 | + #clock-cells = <0>; | |
| 60 | + }; | |
| 61 | + | |
| 62 | + rtc_clk: dummy32k { | |
| 63 | + compatible = "fixed-clock"; | |
| 64 | + clock-frequency = <32000>; | |
| 65 | + #clock-cells = <0>; | |
| 66 | + }; | |
| 67 | + }; | |
| 68 | + | |
| 69 | + soc { | |
| 70 | + #address-cells = <2>; | |
| 71 | + #size-cells = <2>; | |
| 72 | + compatible = "simple-bus"; | |
| 73 | + ranges; | |
| 74 | + | |
| 75 | + timer: timer@10008000 { | |
| 76 | + compatible = "mediatek,mt8127-timer", | |
| 77 | + "mediatek,mt6577-timer"; | |
| 78 | + reg = <0 0x10008000 0 0x80>; | |
| 79 | + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
| 80 | + clocks = <&system_clk>, <&rtc_clk>; | |
| 81 | + clock-names = "system-clk", "rtc-clk"; | |
| 82 | + }; | |
| 83 | + | |
| 84 | + gic: interrupt-controller@10211000 { | |
| 85 | + compatible = "arm,cortex-a7-gic"; | |
| 86 | + interrupt-controller; | |
| 87 | + #interrupt-cells = <3>; | |
| 88 | + reg = <0 0x10211000 0 0x1000>, | |
| 89 | + <0 0x10212000 0 0x1000>, | |
| 90 | + <0 0x10214000 0 0x2000>, | |
| 91 | + <0 0x10216000 0 0x2000>; | |
| 92 | + }; | |
| 93 | + }; | |
| 94 | +}; | |
| @@ -0,0 +1,25 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (c) 2014 MediaTek Inc. | |
| 3 | + * Author: Joe.C <yingjoe.chen@mediatek.com> | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * published by the Free Software Foundation. | |
| 8 | + * | |
| 9 | + * This program is distributed in the hope that it will be useful, | |
| 10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | + * GNU General Public License for more details. | |
| 13 | + */ | |
| 14 | + | |
| 15 | +/dts-v1/; | |
| 16 | +#include "mt8135.dtsi" | |
| 17 | + | |
| 18 | +/ { | |
| 19 | + model = "MediaTek MT8135 evaluation board"; | |
| 20 | + compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; | |
| 21 | + | |
| 22 | + memory { | |
| 23 | + reg = <0 0x80000000 0 0x40000000>; | |
| 24 | + }; | |
| 25 | +}; | |
| @@ -0,0 +1,116 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (c) 2014 MediaTek Inc. | |
| 3 | + * Author: Joe.C <yingjoe.chen@mediatek.com> | |
| 4 | + * | |
| 5 | + * This program is free software; you can redistribute it and/or modify | |
| 6 | + * it under the terms of the GNU General Public License version 2 as | |
| 7 | + * published by the Free Software Foundation. | |
| 8 | + * | |
| 9 | + * This program is distributed in the hope that it will be useful, | |
| 10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | + * GNU General Public License for more details. | |
| 13 | + */ | |
| 14 | + | |
| 15 | +#include <dt-bindings/interrupt-controller/irq.h> | |
| 16 | +#include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 17 | +#include "skeleton64.dtsi" | |
| 18 | + | |
| 19 | +/ { | |
| 20 | + compatible = "mediatek,mt8135"; | |
| 21 | + interrupt-parent = <&gic>; | |
| 22 | + | |
| 23 | + cpu-map { | |
| 24 | + cluster0 { | |
| 25 | + core0 { | |
| 26 | + cpu = <&cpu0>; | |
| 27 | + }; | |
| 28 | + core1 { | |
| 29 | + cpu = <&cpu1>; | |
| 30 | + }; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + cluster1 { | |
| 34 | + core0 { | |
| 35 | + cpu = <&cpu2>; | |
| 36 | + }; | |
| 37 | + core1 { | |
| 38 | + cpu = <&cpu3>; | |
| 39 | + }; | |
| 40 | + }; | |
| 41 | + }; | |
| 42 | + | |
| 43 | + cpus { | |
| 44 | + #address-cells = <1>; | |
| 45 | + #size-cells = <0>; | |
| 46 | + | |
| 47 | + cpu0: cpu@0 { | |
| 48 | + device_type = "cpu"; | |
| 49 | + compatible = "arm,cortex-a7"; | |
| 50 | + reg = <0x000>; | |
| 51 | + }; | |
| 52 | + | |
| 53 | + cpu1: cpu@1 { | |
| 54 | + device_type = "cpu"; | |
| 55 | + compatible = "arm,cortex-a7"; | |
| 56 | + reg = <0x001>; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + cpu2: cpu@100 { | |
| 60 | + device_type = "cpu"; | |
| 61 | + compatible = "arm,cortex-a15"; | |
| 62 | + reg = <0x100>; | |
| 63 | + }; | |
| 64 | + | |
| 65 | + cpu3: cpu@101 { | |
| 66 | + device_type = "cpu"; | |
| 67 | + compatible = "arm,cortex-a15"; | |
| 68 | + reg = <0x101>; | |
| 69 | + }; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + clocks { | |
| 73 | + #address-cells = <2>; | |
| 74 | + #size-cells = <2>; | |
| 75 | + compatible = "simple-bus"; | |
| 76 | + ranges; | |
| 77 | + | |
| 78 | + system_clk: dummy13m { | |
| 79 | + compatible = "fixed-clock"; | |
| 80 | + clock-frequency = <13000000>; | |
| 81 | + #clock-cells = <0>; | |
| 82 | + }; | |
| 83 | + | |
| 84 | + rtc_clk: dummy32k { | |
| 85 | + compatible = "fixed-clock"; | |
| 86 | + clock-frequency = <32000>; | |
| 87 | + #clock-cells = <0>; | |
| 88 | + }; | |
| 89 | + }; | |
| 90 | + | |
| 91 | + soc { | |
| 92 | + #address-cells = <2>; | |
| 93 | + #size-cells = <2>; | |
| 94 | + compatible = "simple-bus"; | |
| 95 | + ranges; | |
| 96 | + | |
| 97 | + timer: timer@10008000 { | |
| 98 | + compatible = "mediatek,mt8135-timer", | |
| 99 | + "mediatek,mt6577-timer"; | |
| 100 | + reg = <0 0x10008000 0 0x80>; | |
| 101 | + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 102 | + clocks = <&system_clk>, <&rtc_clk>; | |
| 103 | + clock-names = "system-clk", "rtc-clk"; | |
| 104 | + }; | |
| 105 | + | |
| 106 | + gic: interrupt-controller@10211000 { | |
| 107 | + compatible = "arm,cortex-a15-gic"; | |
| 108 | + interrupt-controller; | |
| 109 | + #interrupt-cells = <3>; | |
| 110 | + reg = <0 0x10211000 0 0x1000>, | |
| 111 | + <0 0x10212000 0 0x1000>, | |
| 112 | + <0 0x10214000 0 0x2000>, | |
| 113 | + <0 0x10216000 0 0x2000>; | |
| 114 | + }; | |
| 115 | + }; | |
| 116 | +}; | |
| @@ -23,24 +23,29 @@ · 22 unmodified lines | ||
| 23 | 23 | ethernet@gpmc { |
| 24 | 24 | compatible = "smsc,lan9221", "smsc,lan9115"; |
| 25 | 25 | bank-width = <2>; |
| 26 | − gpmc,mux-add-data; | |
| 27 | − gpmc,cs-on-ns = <1>; | |
| 28 | − gpmc,cs-rd-off-ns = <180>; | |
| 29 | − gpmc,cs-wr-off-ns = <180>; | |
| 30 | − gpmc,adv-rd-off-ns = <18>; | |
| 31 | − gpmc,adv-wr-off-ns = <48>; | |
| 32 | − gpmc,oe-on-ns = <54>; | |
| 33 | − gpmc,oe-off-ns = <168>; | |
| 34 | − gpmc,we-on-ns = <54>; | |
| 35 | − gpmc,we-off-ns = <168>; | |
| 36 | − gpmc,rd-cycle-ns = <186>; | |
| 37 | − gpmc,wr-cycle-ns = <186>; | |
| 38 | − gpmc,access-ns = <144>; | |
| 39 | − gpmc,page-burst-access-ns = <24>; | |
| 40 | − gpmc,bus-turnaround-ns = <90>; | |
| 41 | − gpmc,cycle2cycle-delay-ns = <90>; | |
| 42 | − gpmc,cycle2cycle-samecsen; | |
| 43 | − gpmc,cycle2cycle-diffcsen; | |
| 26 | + gpmc,device-width = <1>; | |
| 27 | + gpmc,cycle2cycle-samecsen = <1>; | |
| 28 | + gpmc,cycle2cycle-diffcsen = <1>; | |
| 29 | + gpmc,cs-on-ns = <5>; | |
| 30 | + gpmc,cs-rd-off-ns = <150>; | |
| 31 | + gpmc,cs-wr-off-ns = <150>; | |
| 32 | + gpmc,adv-on-ns = <0>; | |
| 33 | + gpmc,adv-rd-off-ns = <15>; | |
| 34 | + gpmc,adv-wr-off-ns = <40>; | |
| 35 | + gpmc,oe-on-ns = <45>; | |
| 36 | + gpmc,oe-off-ns = <140>; | |
| 37 | + gpmc,we-on-ns = <45>; | |
| 38 | + gpmc,we-off-ns = <140>; | |
| 39 | + gpmc,rd-cycle-ns = <155>; | |
| 40 | + gpmc,wr-cycle-ns = <155>; | |
| 41 | + gpmc,access-ns = <120>; | |
| 42 | + gpmc,page-burst-access-ns = <20>; | |
| 43 | + gpmc,bus-turnaround-ns = <75>; | |
| 44 | + gpmc,cycle2cycle-delay-ns = <75>; | |
| 45 | + gpmc,wait-monitoring-ns = <0>; | |
| 46 | + gpmc,clk-activation-ns = <0>; | |
| 47 | + gpmc,wr-data-mux-bus-ns = <0>; | |
| 48 | + gpmc,wr-access-ns = <0>; | |
| 44 | 49 | vddvario-supply = <&vddvario>; |
| 45 | 50 | vdd33a-supply = <&vdd33a>; |
| 46 | 51 | reg-io-width = <4>; |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | #include "omap-gpmc-smsc911x.dtsi" |
| 6 | 6 | |
| 7 | 7 | &gpmc { |
| 8 | − ranges = <3 0 0x10000000 0x00000400>, | |
| 8 | + ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */ | |
| 9 | 9 | <7 0 0x2c000000 0x01000000>; |
| 10 | 10 | |
| 11 | 11 | /* |
| @@ -15,7 +15,65 @@ · 3 unmodified lines | ||
| 15 | 15 | */ |
| 16 | 16 | uart@3,0 { |
| 17 | 17 | compatible = "ns16550a"; |
| 18 | − reg = <3 0 0x100>; | |
| 18 | + reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ | |
| 19 | + bank-width = <2>; | |
| 20 | + reg-shift = <1>; | |
| 21 | + reg-io-width = <1>; | |
| 22 | + interrupt-parent = <&gpio4>; | |
| 23 | + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ | |
| 24 | + clock-frequency = <1843200>; | |
| 25 | + current-speed = <115200>; | |
| 26 | + gpmc,mux-add-data = <0>; | |
| 27 | + gpmc,device-width = <1>; | |
| 28 | + gpmc,wait-pin = <1>; | |
| 29 | + gpmc,cycle2cycle-samecsen = <1>; | |
| 30 | + gpmc,cycle2cycle-diffcsen = <1>; | |
| 31 | + gpmc,cs-on-ns = <5>; | |
| 32 | + gpmc,cs-rd-off-ns = <155>; | |
| 33 | + gpmc,cs-wr-off-ns = <155>; | |
| 34 | + gpmc,adv-on-ns = <15>; | |
| 35 | + gpmc,adv-rd-off-ns = <40>; | |
| 36 | + gpmc,adv-wr-off-ns = <40>; | |
| 37 | + gpmc,oe-on-ns = <45>; | |
| 38 | + gpmc,oe-off-ns = <145>; | |
| 39 | + gpmc,we-on-ns = <45>; | |
| 40 | + gpmc,we-off-ns = <145>; | |
| 41 | + gpmc,rd-cycle-ns = <155>; | |
| 42 | + gpmc,wr-cycle-ns = <155>; | |
| 43 | + gpmc,access-ns = <145>; | |
| 44 | + gpmc,page-burst-access-ns = <20>; | |
| 45 | + gpmc,bus-turnaround-ns = <20>; | |
| 46 | + gpmc,cycle2cycle-delay-ns = <20>; | |
| 47 | + gpmc,wait-monitoring-ns = <0>; | |
| 48 | + gpmc,clk-activation-ns = <0>; | |
| 49 | + gpmc,wr-data-mux-bus-ns = <45>; | |
| 50 | + gpmc,wr-access-ns = <145>; | |
| 51 | + }; | |
| 52 | + uart@3,1 { | |
| 53 | + compatible = "ns16550a"; | |
| 54 | + reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ | |
| 55 | + bank-width = <2>; | |
| 56 | + reg-shift = <1>; | |
| 57 | + reg-io-width = <1>; | |
| 58 | + interrupt-parent = <&gpio4>; | |
| 59 | + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ | |
| 60 | + clock-frequency = <1843200>; | |
| 61 | + current-speed = <115200>; | |
| 62 | + }; | |
| 63 | + uart@3,2 { | |
| 64 | + compatible = "ns16550a"; | |
| 65 | + reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ | |
| 66 | + bank-width = <2>; | |
| 67 | + reg-shift = <1>; | |
| 68 | + reg-io-width = <1>; | |
| 69 | + interrupt-parent = <&gpio4>; | |
| 70 | + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ | |
| 71 | + clock-frequency = <1843200>; | |
| 72 | + current-speed = <115200>; | |
| 73 | + }; | |
| 74 | + uart@3,3 { | |
| 75 | + compatible = "ns16550a"; | |
| 76 | + reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ | |
| 19 | 77 | bank-width = <2>; |
| 20 | 78 | reg-shift = <1>; |
| 21 | 79 | reg-io-width = <1>; |
| @@ -40,14 +40,14 @@ · 39 unmodified lines | ||
| 40 | 40 | }; |
| 41 | 41 | |
| 42 | 42 | &gpmc { |
| 43 | − ranges = <0 0 0x04000000 0x10000000>; | |
| 43 | + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ | |
| 44 | 44 | |
| 45 | 45 | /* gpio-irq for dma: 26 */ |
| 46 | 46 | |
| 47 | 47 | onenand@0,0 { |
| 48 | 48 | #address-cells = <1>; |
| 49 | 49 | #size-cells = <1>; |
| 50 | − reg = <0 0 0x10000000>; | |
| 50 | + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ | |
| 51 | 51 | |
| 52 | 52 | gpmc,sync-read; |
| 53 | 53 | gpmc,burst-length = <16>; |
| @@ -157,6 +157,7 @@ · 156 unmodified lines | ||
| 157 | 157 | interrupts = <26>, <34>; |
| 158 | 158 | interrupt-names = "dsp", "iva"; |
| 159 | 159 | ti,hwmods = "mailbox"; |
| 160 | + #mbox-cells = <1>; | |
| 160 | 161 | ti,mbox-num-users = <4>; |
| 161 | 162 | ti,mbox-num-fifos = <6>; |
| 162 | 163 | mbox_dsp: dsp { |
| @@ -43,7 +43,31 @@ · 42 unmodified lines | ||
| 43 | 43 | interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ |
| 44 | 44 | reg = <5 0x300 0xf>; |
| 45 | 45 | bank-width = <2>; |
| 46 | − gpmc,mux-add-data; | |
| 47 | − }; | |
| 46 | + gpmc,sync-clk-ps = <0>; | |
| 47 | + gpmc,mux-add-data = <2>; | |
| 48 | + gpmc,device-width = <1>; | |
| 49 | + gpmc,cycle2cycle-samecsen = <1>; | |
| 50 | + gpmc,cycle2cycle-diffcsen = <1>; | |
| 51 | + gpmc,cs-on-ns = <7>; | |
| 52 | + gpmc,cs-rd-off-ns = <233>; | |
| 53 | + gpmc,cs-wr-off-ns = <233>; | |
| 54 | + gpmc,adv-on-ns = <22>; | |
| 55 | + gpmc,adv-rd-off-ns = <60>; | |
| 56 | + gpmc,adv-wr-off-ns = <60>; | |
| 57 | + gpmc,oe-on-ns = <67>; | |
| 58 | + gpmc,oe-off-ns = <210>; | |
| 59 | + gpmc,we-on-ns = <67>; | |
| 60 | + gpmc,we-off-ns = <210>; | |
| 61 | + gpmc,rd-cycle-ns = <233>; | |
| 62 | + gpmc,wr-cycle-ns = <233>; | |
| 63 | + gpmc,access-ns = <233>; | |
| 64 | + gpmc,page-burst-access-ns = <30>; | |
| 65 | + gpmc,bus-turnaround-ns = <30>; | |
| 66 | + gpmc,cycle2cycle-delay-ns = <30>; | |
| 67 | + gpmc,wait-monitoring-ns = <0>; | |
| 68 | + gpmc,clk-activation-ns = <0>; | |
| 69 | + gpmc,wr-data-mux-bus-ns = <0>; | |
| 70 | + gpmc,wr-access-ns = <0>; | |
| 71 | + }; | |
| 48 | 72 | }; |
| 49 | 73 | |
| @@ -247,6 +247,7 @@ · 246 unmodified lines | ||
| 247 | 247 | reg = <0x48094000 0x200>; |
| 248 | 248 | interrupts = <26>; |
| 249 | 249 | ti,hwmods = "mailbox"; |
| 250 | + #mbox-cells = <1>; | |
| 250 | 251 | ti,mbox-num-users = <4>; |
| 251 | 252 | ti,mbox-num-fifos = <6>; |
| 252 | 253 | mbox_dsp: dsp { |
| @@ -134,3 +134,14 @@ · 133 unmodified lines | ||
| 134 | 134 | bus-width = <4>; |
| 135 | 135 | cap-power-off-card; |
| 136 | 136 | }; |
| 137 | + | |
| 138 | +&dss { | |
| 139 | + status = "ok"; | |
| 140 | + | |
| 141 | + pinctrl-names = "default"; | |
| 142 | + pinctrl-0 = < | |
| 143 | + &dss_dpi_pins_common | |
| 144 | + &dss_dpi_pins_cm_t35x | |
| 145 | + >; | |
| 146 | +}; | |
| 147 | + | |
| @@ -46,3 +46,14 @@ · 45 unmodified lines | ||
| 46 | 46 | bus-width = <4>; |
| 47 | 47 | cap-power-off-card; |
| 48 | 48 | }; |
| 49 | + | |
| 50 | +&dss { | |
| 51 | + status = "ok"; | |
| 52 | + | |
| 53 | + pinctrl-names = "default"; | |
| 54 | + pinctrl-0 = < | |
| 55 | + &dss_dpi_pins_common | |
| 56 | + &dss_dpi_pins_cm_t35x | |
| 57 | + >; | |
| 58 | +}; | |
| 59 | + | |
| @@ -31,6 +31,19 @@ · 30 unmodified lines | ||
| 31 | 31 | }; |
| 32 | 32 | }; |
| 33 | 33 | |
| 34 | +&omap3_pmx_wkup { | |
| 35 | + dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { | |
| 36 | + pinctrl-single,pins = < | |
| 37 | + OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ | |
| 38 | + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ | |
| 39 | + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ | |
| 40 | + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ | |
| 41 | + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ | |
| 42 | + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ | |
| 43 | + >; | |
| 44 | + }; | |
| 45 | +}; | |
| 46 | + | |
| 34 | 47 | &omap3_pmx_core { |
| 35 | 48 | |
| 36 | 49 | mmc2_pins: pinmux_mmc2_pins { |
| @@ -61,3 +74,14 @@ · 24 unmodified lines | ||
| 61 | 74 | bus-width = <4>; |
| 62 | 75 | cap-power-off-card; |
| 63 | 76 | }; |
| 77 | + | |
| 78 | +&dss { | |
| 79 | + status = "ok"; | |
| 80 | + | |
| 81 | + pinctrl-names = "default"; | |
| 82 | + pinctrl-0 = < | |
| 83 | + &dss_dpi_pins_common | |
| 84 | + &dss_dpi_pins_cm_t3730 | |
| 85 | + >; | |
| 86 | +}; | |
| 87 | + | |
| @@ -49,6 +49,24 @@ · 48 unmodified lines | ||
| 49 | 49 | compatible = "usb-nop-xceiv"; |
| 50 | 50 | vcc-supply = <&hsusb2_power>; |
| 51 | 51 | }; |
| 52 | + | |
| 53 | + ads7846reg: ads7846-reg { | |
| 54 | + compatible = "regulator-fixed"; | |
| 55 | + regulator-name = "ads7846-reg"; | |
| 56 | + regulator-min-microvolt = <3300000>; | |
| 57 | + regulator-max-microvolt = <3300000>; | |
| 58 | + }; | |
| 59 | + | |
| 60 | + tv0: connector@1 { | |
| 61 | + compatible = "svideo-connector"; | |
| 62 | + label = "tv"; | |
| 63 | + | |
| 64 | + port { | |
| 65 | + tv_connector_in: endpoint { | |
| 66 | + remote-endpoint = <&venc_out>; | |
| 67 | + }; | |
| 68 | + }; | |
| 69 | + }; | |
| 52 | 70 | }; |
| 53 | 71 | |
| 54 | 72 | &omap3_pmx_core { |
| @@ -76,6 +94,76 @@ · 21 unmodified lines | ||
| 76 | 94 | OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ |
| 77 | 95 | >; |
| 78 | 96 | }; |
| 97 | + | |
| 98 | + dss_dpi_pins_common: pinmux_dss_dpi_pins_common { | |
| 99 | + pinctrl-single,pins = < | |
| 100 | + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ | |
| 101 | + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ | |
| 102 | + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ | |
| 103 | + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ | |
| 104 | + | |
| 105 | + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ | |
| 106 | + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ | |
| 107 | + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ | |
| 108 | + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ | |
| 109 | + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ | |
| 110 | + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ | |
| 111 | + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ | |
| 112 | + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ | |
| 113 | + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ | |
| 114 | + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ | |
| 115 | + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ | |
| 116 | + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ | |
| 117 | + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ | |
| 118 | + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ | |
| 119 | + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ | |
| 120 | + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ | |
| 121 | + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ | |
| 122 | + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ | |
| 123 | + >; | |
| 124 | + }; | |
| 125 | + | |
| 126 | + dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x { | |
| 127 | + pinctrl-single,pins = < | |
| 128 | + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ | |
| 129 | + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ | |
| 130 | + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ | |
| 131 | + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ | |
| 132 | + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ | |
| 133 | + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ | |
| 134 | + >; | |
| 135 | + }; | |
| 136 | + | |
| 137 | + ads7846_pins: pinmux_ads7846_pins { | |
| 138 | + pinctrl-single,pins = < | |
| 139 | + OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ | |
| 140 | + >; | |
| 141 | + }; | |
| 142 | + | |
| 143 | + mcspi1_pins: pinmux_mcspi1_pins { | |
| 144 | + pinctrl-single,pins = < | |
| 145 | + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ | |
| 146 | + OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ | |
| 147 | + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */ | |
| 148 | + OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */ | |
| 149 | + >; | |
| 150 | + }; | |
| 151 | + | |
| 152 | + i2c1_pins: pinmux_i2c1_pins { | |
| 153 | + pinctrl-single,pins = < | |
| 154 | + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ | |
| 155 | + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ | |
| 156 | + >; | |
| 157 | + }; | |
| 158 | + | |
| 159 | + mcbsp2_pins: pinmux_mcbsp2_pins { | |
| 160 | + pinctrl-single,pins = < | |
| 161 | + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ | |
| 162 | + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ | |
| 163 | + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ | |
| 164 | + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ | |
| 165 | + >; | |
| 166 | + }; | |
| 79 | 167 | }; |
| 80 | 168 | |
| 81 | 169 | &uart3 { |
| @@ -94,12 +182,22 @@ · 12 unmodified lines | ||
| 94 | 182 | }; |
| 95 | 183 | |
| 96 | 184 | &i2c1 { |
| 185 | + pinctrl-names = "default"; | |
| 186 | + pinctrl-0 = <&i2c1_pins>; | |
| 187 | + | |
| 97 | 188 | clock-frequency = <400000>; |
| 189 | + | |
| 190 | + at24@50 { | |
| 191 | + compatible = "at24,24c02"; | |
| 192 | + pagesize = <16>; | |
| 193 | + reg = <0x50>; | |
| 194 | + }; | |
| 98 | 195 | }; |
| 99 | 196 | |
| 100 | 197 | &i2c3 { |
| 101 | 198 | clock-frequency = <400000>; |
| 102 | 199 | }; |
| 200 | + | |
| 103 | 201 | &usbhshost { |
| 104 | 202 | port1-mode = "ehci-phy"; |
| 105 | 203 | port2-mode = "ehci-phy"; |
| @@ -108,3 +206,56 @@ · 2 unmodified lines | ||
| 108 | 206 | &usbhsehci { |
| 109 | 207 | phys = <&hsusb1_phy &hsusb2_phy>; |
| 110 | 208 | }; |
| 209 | + | |
| 210 | +&mcspi1 { | |
| 211 | + pinctrl-names = "default"; | |
| 212 | + pinctrl-0 = <&mcspi1_pins>; | |
| 213 | + | |
| 214 | + /* touch controller */ | |
| 215 | + ads7846@0 { | |
| 216 | + pinctrl-names = "default"; | |
| 217 | + pinctrl-0 = <&ads7846_pins>; | |
| 218 | + | |
| 219 | + compatible = "ti,ads7846"; | |
| 220 | + vcc-supply = <&ads7846reg>; | |
| 221 | + | |
| 222 | + reg = <0>; /* CS0 */ | |
| 223 | + spi-max-frequency = <1500000>; | |
| 224 | + | |
| 225 | + interrupt-parent = <&gpio2>; | |
| 226 | + interrupts = <25 0>; /* gpio_57 */ | |
| 227 | + pendown-gpio = <&gpio2 25 0>; | |
| 228 | + | |
| 229 | + ti,x-min = /bits/ 16 <0x0>; | |
| 230 | + ti,x-max = /bits/ 16 <0x0fff>; | |
| 231 | + ti,y-min = /bits/ 16 <0x0>; | |
| 232 | + ti,y-max = /bits/ 16 <0x0fff>; | |
| 233 | + | |
| 234 | + ti,x-plate-ohms = /bits/ 16 <180>; | |
| 235 | + ti,pressure-max = /bits/ 16 <255>; | |
| 236 | + | |
| 237 | + ti,debounce-max = /bits/ 16 <30>; | |
| 238 | + ti,debounce-tol = /bits/ 16 <10>; | |
| 239 | + ti,debounce-rep = /bits/ 16 <1>; | |
| 240 | + | |
| 241 | + linux,wakeup; | |
| 242 | + }; | |
| 243 | +}; | |
| 244 | + | |
| 245 | +&venc { | |
| 246 | + status = "ok"; | |
| 247 | + | |
| 248 | + port { | |
| 249 | + venc_out: endpoint { | |
| 250 | + remote-endpoint = <&tv_connector_in>; | |
| 251 | + ti,channels = <2>; | |
| 252 | + }; | |
| 253 | + }; | |
| 254 | +}; | |
| 255 | + | |
| 256 | +&mcbsp2 { | |
| 257 | + status = "ok"; | |
| 258 | + | |
| 259 | + pinctrl-names = "default"; | |
| 260 | + pinctrl-0 = <&mcbsp2_pins>; | |
| 261 | +}; | |
| @@ -10,6 +10,14 @@ · 9 unmodified lines | ||
| 10 | 10 | cpu0-supply = <&vcc>; |
| 11 | 11 | }; |
| 12 | 12 | }; |
| 13 | + | |
| 14 | + sound { | |
| 15 | + compatible = "ti,omap-twl4030"; | |
| 16 | + ti,model = "cm-t35"; | |
| 17 | + | |
| 18 | + ti,mcbsp = <&mcbsp2>; | |
| 19 | + ti,codec = <&twl_audio>; | |
| 20 | + }; | |
| 13 | 21 | }; |
| 14 | 22 | |
| 15 | 23 | &omap3_pmx_core { |
| @@ -59,11 +67,22 @@ · 43 unmodified lines | ||
| 59 | 67 | reg = <0x48>; |
| 60 | 68 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ |
| 61 | 69 | interrupt-parent = <&intc>; |
| 70 | + | |
| 71 | + twl_audio: audio { | |
| 72 | + compatible = "ti,twl4030-audio"; | |
| 73 | + codec { | |
| 74 | + }; | |
| 75 | + }; | |
| 62 | 76 | }; |
| 63 | 77 | }; |
| 64 | 78 | |
| 65 | 79 | #include "twl4030.dtsi" |
| 66 | 80 | #include "twl4030_omap3.dtsi" |
| 81 | +#include <dt-bindings/input/input.h> | |
| 82 | + | |
| 83 | +&venc { | |
| 84 | + vdda-supply = <&vdac>; | |
| 85 | +}; | |
| 67 | 86 | |
| 68 | 87 | &mmc1 { |
| 69 | 88 | vmmc-supply = <&vmmc1>; |
| @@ -75,6 +94,22 @@ · 5 unmodified lines | ||
| 75 | 94 | ti,pullups = <0x000001>; |
| 76 | 95 | }; |
| 77 | 96 | |
| 97 | +&twl_keypad { | |
| 98 | + linux,keymap = < | |
| 99 | + MATRIX_KEY(0x00, 0x01, KEY_A) | |
| 100 | + MATRIX_KEY(0x00, 0x02, KEY_B) | |
| 101 | + MATRIX_KEY(0x00, 0x03, KEY_LEFT) | |
| 102 | + | |
| 103 | + MATRIX_KEY(0x01, 0x01, KEY_UP) | |
| 104 | + MATRIX_KEY(0x01, 0x02, KEY_ENTER) | |
| 105 | + MATRIX_KEY(0x01, 0x03, KEY_DOWN) | |
| 106 | + | |
| 107 | + MATRIX_KEY(0x02, 0x01, KEY_RIGHT) | |
| 108 | + MATRIX_KEY(0x02, 0x02, KEY_C) | |
| 109 | + MATRIX_KEY(0x02, 0x03, KEY_D) | |
| 110 | + >; | |
| 111 | +}; | |
| 112 | + | |
| 78 | 113 | &hsusb1_phy { |
| 79 | 114 | reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; |
| 80 | 115 | }; |
| @@ -106,10 +106,10 @@ · 105 unmodified lines | ||
| 106 | 106 | }; |
| 107 | 107 | |
| 108 | 108 | &gpmc { |
| 109 | − ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ | |
| 109 | + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ | |
| 110 | 110 | |
| 111 | 111 | nand@0,0 { |
| 112 | − reg = <0 0 0>; /* CS0, offset 0 */ | |
| 112 | + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
| 113 | 113 | nand-bus-width = <16>; |
| 114 | 114 | |
| 115 | 115 | gpmc,sync-clk-ps = <0>; |
| @@ -154,13 +154,14 @@ · 153 unmodified lines | ||
| 154 | 154 | }; |
| 155 | 155 | |
| 156 | 156 | &gpmc { |
| 157 | − ranges = <0 0 0x00000000 0x20000000>, | |
| 157 | + ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */ | |
| 158 | 158 | <5 0 0x2c000000 0x01000000>; |
| 159 | 159 | |
| 160 | 160 | nand@0,0 { |
| 161 | 161 | linux,mtd-name= "hynix,h8kds0un0mer-4em"; |
| 162 | − reg = <0 0 0>; | |
| 162 | + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
| 163 | 163 | nand-bus-width = <16>; |
| 164 | + gpmc,device-width = <2>; | |
| 164 | 165 | ti,nand-ecc-opt = "bch8"; |
| 165 | 166 | |
| 166 | 167 | gpmc,sync-clk-ps = <0>; |
| @@ -2,6 +2,7 @@ · 1 unmodified line | ||
| 2 | 2 | * Common support for omap3 EVM boards |
| 3 | 3 | */ |
| 4 | 4 | |
| 5 | +#include <dt-bindings/input/input.h> | |
| 5 | 6 | #include "omap-gpmc-smsc911x.dtsi" |
| 6 | 7 | |
| 7 | 8 | / { |
| @@ -111,6 +112,26 @@ · 103 unmodified lines | ||
| 111 | 112 | ti,use-leds; |
| 112 | 113 | }; |
| 113 | 114 | |
| 115 | +&twl_keypad { | |
| 116 | + linux,keymap = < | |
| 117 | + MATRIX_KEY(2, 2, KEY_1) | |
| 118 | + MATRIX_KEY(1, 1, KEY_2) | |
| 119 | + MATRIX_KEY(0, 0, KEY_3) | |
| 120 | + MATRIX_KEY(3, 2, KEY_4) | |
| 121 | + MATRIX_KEY(2, 1, KEY_5) | |
| 122 | + MATRIX_KEY(1, 0, KEY_6) | |
| 123 | + MATRIX_KEY(1, 3, KEY_7) | |
| 124 | + MATRIX_KEY(3, 1, KEY_8) | |
| 125 | + MATRIX_KEY(2, 0, KEY_9) | |
| 126 | + MATRIX_KEY(2, 3, KEY_KPASTERISK) | |
| 127 | + MATRIX_KEY(0, 2, KEY_0) | |
| 128 | + MATRIX_KEY(3, 0, KEY_KPDOT) | |
| 129 | + /* s4 not wired */ | |
| 130 | + MATRIX_KEY(1, 2, KEY_BACKSPACE) | |
| 131 | + MATRIX_KEY(0, 1, KEY_ENTER) | |
| 132 | + >; | |
| 133 | +}; | |
| 134 | + | |
| 114 | 135 | &usb_otg_hs { |
| 115 | 136 | interface-type = <0>; |
| 116 | 137 | usb-phy = <&usb2_phy>; |
| @@ -104,67 +104,67 @@ · 103 unmodified lines | ||
| 104 | 104 | |
| 105 | 105 | uart1_pins: pinmux_uart1_pins { |
| 106 | 106 | pinctrl-single,pins = < |
| 107 | − 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ | |
| 108 | − 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ | |
| 107 | + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ | |
| 108 | + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ | |
| 109 | 109 | >; |
| 110 | 110 | }; |
| 111 | 111 | |
| 112 | 112 | uart2_pins: pinmux_uart2_pins { |
| 113 | 113 | pinctrl-single,pins = < |
| 114 | − 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ | |
| 115 | − 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ | |
| 114 | + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ | |
| 115 | + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ | |
| 116 | 116 | >; |
| 117 | 117 | }; |
| 118 | 118 | |
| 119 | 119 | uart3_pins: pinmux_uart3_pins { |
| 120 | 120 | pinctrl-single,pins = < |
| 121 | − 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ | |
| 122 | − 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ | |
| 121 | + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ | |
| 122 | + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ | |
| 123 | 123 | >; |
| 124 | 124 | }; |
| 125 | 125 | |
| 126 | 126 | mmc1_pins: pinmux_mmc1_pins { |
| 127 | 127 | pinctrl-single,pins = < |
| 128 | − 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ | |
| 129 | − 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ | |
| 130 | − 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ | |
| 131 | − 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ | |
| 132 | − 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ | |
| 133 | − 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ | |
| 128 | + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ | |
| 129 | + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ | |
| 130 | + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ | |
| 131 | + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ | |
| 132 | + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ | |
| 133 | + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ | |
| 134 | 134 | >; |
| 135 | 135 | }; |
| 136 | 136 | |
| 137 | 137 | dss_dpi_pins: pinmux_dss_dpi_pins { |
| 138 | 138 | pinctrl-single,pins = < |
| 139 | − 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ | |
| 140 | − 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ | |
| 141 | − 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ | |
| 142 | − 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ | |
| 143 | − 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ | |
| 144 | − 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ | |
| 145 | − 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ | |
| 146 | − 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ | |
| 147 | − 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ | |
| 148 | − 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ | |
| 149 | − 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ | |
| 150 | − 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ | |
| 151 | − 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ | |
| 152 | − 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ | |
| 153 | − 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ | |
| 154 | − 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ | |
| 155 | − 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ | |
| 156 | − 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ | |
| 157 | − 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ | |
| 158 | − 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ | |
| 159 | − 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ | |
| 160 | − 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ | |
| 161 | − 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ | |
| 162 | − 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ | |
| 163 | − 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ | |
| 164 | − 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ | |
| 165 | − 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ | |
| 166 | − 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ | |
| 167 | − >; | |
| 139 | + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ | |
| 140 | + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ | |
| 141 | + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ | |
| 142 | + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ | |
| 143 | + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ | |
| 144 | + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ | |
| 145 | + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ | |
| 146 | + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ | |
| 147 | + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ | |
| 148 | + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ | |
| 149 | + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ | |
| 150 | + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ | |
| 151 | + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ | |
| 152 | + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ | |
| 153 | + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ | |
| 154 | + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ | |
| 155 | + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ | |
| 156 | + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ | |
| 157 | + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ | |
| 158 | + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ | |
| 159 | + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ | |
| 160 | + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ | |
| 161 | + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ | |
| 162 | + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ | |
| 163 | + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ | |
| 164 | + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ | |
| 165 | + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ | |
| 166 | + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ | |
| 167 | + >; | |
| 168 | 168 | }; |
| 169 | 169 | }; |
| 170 | 170 | |
| @@ -397,10 +397,10 @@ · 226 unmodified lines | ||
| 397 | 397 | }; |
| 398 | 398 | |
| 399 | 399 | &gpmc { |
| 400 | − ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ | |
| 400 | + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ | |
| 401 | 401 | |
| 402 | 402 | nand@0,0 { |
| 403 | − reg = <0 0 0>; /* CS0, offset 0 */ | |
| 403 | + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
| 404 | 404 | nand-bus-width = <16>; |
| 405 | 405 | ti,nand-ecc-opt = "bch8"; |
| 406 | 406 | |
| @@ -31,18 +31,6 @@ · 30 unmodified lines | ||
| 31 | 31 | regulator-always-on; |
| 32 | 32 | }; |
| 33 | 33 | |
| 34 | − lbee1usjyc_vmmc: lbee1usjyc_vmmc { | |
| 35 | − pinctrl-names = "default"; | |
| 36 | − pinctrl-0 = <&lbee1usjyc_pins>; | |
| 37 | − compatible = "regulator-fixed"; | |
| 38 | − regulator-name = "regulator-lbee1usjyc"; | |
| 39 | − regulator-min-microvolt = <3300000>; | |
| 40 | − regulator-max-microvolt = <3300000>; | |
| 41 | − gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */ | |
| 42 | − startup-delay-us = <10000>; | |
| 43 | − enable-active-high; | |
| 44 | − vin-supply = <&vdd33>; | |
| 45 | − }; | |
| 46 | 34 | }; |
| 47 | 35 | |
| 48 | 36 | &omap3_pmx_core { |
| @@ -53,13 +41,6 @@ · 4 unmodified lines | ||
| 53 | 41 | >; |
| 54 | 42 | }; |
| 55 | 43 | |
| 56 | − uart2_pins: pinmux_uart2_pins { | |
| 57 | − pinctrl-single,pins = < | |
| 58 | − 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ | |
| 59 | − 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ | |
| 60 | − >; | |
| 61 | − }; | |
| 62 | − | |
| 63 | 44 | uart3_pins: pinmux_uart3_pins { |
| 64 | 45 | pinctrl-single,pins = < |
| 65 | 46 | 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ |
| @@ -67,15 +48,6 @@ · 1 unmodified line | ||
| 67 | 48 | >; |
| 68 | 49 | }; |
| 69 | 50 | |
| 70 | − /* WiFi/BT combo */ | |
| 71 | − lbee1usjyc_pins: pinmux_lbee1usjyc_pins { | |
| 72 | − pinctrl-single,pins = < | |
| 73 | − 0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */ | |
| 74 | − 0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ | |
| 75 | − 0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ | |
| 76 | − >; | |
| 77 | − }; | |
| 78 | − | |
| 79 | 51 | mcbsp2_pins: pinmux_mcbsp2_pins { |
| 80 | 52 | pinctrl-single,pins = < |
| 81 | 53 | 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ |
| @@ -120,13 +92,6 @@ · 38 unmodified lines | ||
| 120 | 92 | >; |
| 121 | 93 | }; |
| 122 | 94 | |
| 123 | − i2c2_pins: pinmux_i2c2_pins { | |
| 124 | − pinctrl-single,pins = < | |
| 125 | − 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ | |
| 126 | − 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ | |
| 127 | − >; | |
| 128 | − }; | |
| 129 | − | |
| 130 | 95 | i2c3_pins: pinmux_i2c3_pins { |
| 131 | 96 | pinctrl-single,pins = < |
| 132 | 97 | 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ |
| @@ -135,6 +100,55 @@ · 2 unmodified lines | ||
| 135 | 100 | }; |
| 136 | 101 | }; |
| 137 | 102 | |
| 103 | +&gpmc { | |
| 104 | + nand@0,0 { | |
| 105 | + linux,mtd-name= "micron,mt29c4g96maz"; | |
| 106 | + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
| 107 | + nand-bus-width = <16>; | |
| 108 | + gpmc,device-width = <2>; | |
| 109 | + ti,nand-ecc-opt = "bch8"; | |
| 110 | + | |
| 111 | + gpmc,sync-clk-ps = <0>; | |
| 112 | + gpmc,cs-on-ns = <0>; | |
| 113 | + gpmc,cs-rd-off-ns = <44>; | |
| 114 | + gpmc,cs-wr-off-ns = <44>; | |
| 115 | + gpmc,adv-on-ns = <6>; | |
| 116 | + gpmc,adv-rd-off-ns = <34>; | |
| 117 | + gpmc,adv-wr-off-ns = <44>; | |
| 118 | + gpmc,we-off-ns = <40>; | |
| 119 | + gpmc,oe-off-ns = <54>; | |
| 120 | + gpmc,access-ns = <64>; | |
| 121 | + gpmc,rd-cycle-ns = <82>; | |
| 122 | + gpmc,wr-cycle-ns = <82>; | |
| 123 | + gpmc,wr-access-ns = <40>; | |
| 124 | + gpmc,wr-data-mux-bus-ns = <0>; | |
| 125 | + | |
| 126 | + #address-cells = <1>; | |
| 127 | + #size-cells = <1>; | |
| 128 | + | |
| 129 | + partition@0 { | |
| 130 | + label = "SPL"; | |
| 131 | + reg = <0 0x100000>; | |
| 132 | + }; | |
| 133 | + partition@80000 { | |
| 134 | + label = "U-Boot"; | |
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File renamed without changes.
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