Like Lunarlake, Pantherlake supports CC1/CC6/CC7 and PC2/PC6/PC10.
Unified · Split
| @@ -41,7 +41,7 @@ · 40 unmodified lines | |||
| 41 | * MSR_CORE_C1_RES: CORE C1 Residency Counter | 41 | * MSR_CORE_C1_RES: CORE C1 Residency Counter |
| 42 | * perf code: 0x00 | 42 | * perf code: 0x00 |
| 43 | * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL | 43 | * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL |
| 44 | * MTL,SRF,GRR,ARL,LNL | 44 | * MTL,SRF,GRR,ARL,LNL,PTL |
| 45 | * Scope: Core (each processor core has a MSR) | 45 | * Scope: Core (each processor core has a MSR) |
| 46 | * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter | 46 | * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter |
| 47 | * perf code: 0x01 | 47 | * perf code: 0x01 |
| @@ -53,18 +53,19 @@ · 5 unmodified lines | |||
| 53 | * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, | 53 | * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, |
| 54 | * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, | 54 | * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, |
| 55 | * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF, | 55 | * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF, |
| 56 | * GRR,ARL,LNL | 56 | * GRR,ARL,LNL,PTL |
| 57 | * Scope: Core | 57 | * Scope: Core |
| 58 | * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter | 58 | * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter |
| 59 | * perf code: 0x03 | 59 | * perf code: 0x03 |
| 60 | * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, | 60 | * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, |
| 61 | * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL | 61 | * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL, |
| 62 | * PTL | ||
| 62 | * Scope: Core | 63 | * Scope: Core |
| 63 | * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. | 64 | * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. |
| 64 | * perf code: 0x00 | 65 | * perf code: 0x00 |
| 65 | * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, | 66 | * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, |
| 66 | * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, | 67 | * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, |
| 67 | * RPL,SPR,MTL,ARL,LNL,SRF | 68 | * RPL,SPR,MTL,ARL,LNL,SRF,PTL |
| 68 | * Scope: Package (physical package) | 69 | * Scope: Package (physical package) |
| 69 | * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. | 70 | * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. |
| 70 | * perf code: 0x01 | 71 | * perf code: 0x01 |
| @@ -77,7 +78,7 @@ · 6 unmodified lines | |||
| 77 | * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, | 78 | * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, |
| 78 | * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, | 79 | * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, |
| 79 | * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF, | 80 | * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF, |
| 80 | * ARL,LNL | 81 | * ARL,LNL,PTL |
| 81 | * Scope: Package (physical package) | 82 | * Scope: Package (physical package) |
| 82 | * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. | 83 | * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. |
| 83 | * perf code: 0x03 | 84 | * perf code: 0x03 |
| @@ -96,7 +97,7 @@ · 12 unmodified lines | |||
| 96 | * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. | 97 | * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. |
| 97 | * perf code: 0x06 | 98 | * perf code: 0x06 |
| 98 | * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, | 99 | * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, |
| 99 | * TNT,RKL,ADL,RPL,MTL,ARL,LNL | 100 | * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL |
| 100 | * Scope: Package (physical package) | 101 | * Scope: Package (physical package) |
| 101 | * MSR_MODULE_C6_RES_MS: Module C6 Residency Counter. | 102 | * MSR_MODULE_C6_RES_MS: Module C6 Residency Counter. |
| 102 | * perf code: 0x00 | 103 | * perf code: 0x00 |
| @@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { · 549 unmodified lines | |||
| 652 | X86_MATCH_VFM(INTEL_ARROWLAKE_H, &adl_cstates), | 653 | X86_MATCH_VFM(INTEL_ARROWLAKE_H, &adl_cstates), |
| 653 | X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates), | 654 | X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates), |
| 654 | X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates), | 655 | X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates), |
| 656 | X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates), | ||
| 655 | { }, | 657 | { }, |
| 656 | }; | 658 | }; |
| 657 | MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); | 659 | MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); |