Pull iommu updates from Joerg Roedel: - IOMMU Core changes: - Removal of aux domain related code as it is basically dead and will be replaced by iommu-fd framework - Split of iommu_ops to carry domain-specific call-backs separatly - Cleanup to remove useless ops->capable implementations - Improve 32-bit free space estimate in iova allocator - Intel VT-d updates: - Various cleanups of the driver - Support for ATS of SoC-integrated devices listed in ACPI/SATC table - ARM SMMU updates: - Fix SMMUv3 soft lockup during continuous stream of events - Fix error path for Qualcomm SMMU probe() - Rework SMMU IRQ setup to prepare the ground for PMU support - Minor cleanups and refactoring - AMD IOMMU driver: - Some minor cleanups and error-handling fixes - Rockchip IOMMU driver: - Use standard driver registration - MSM IOMMU driver: - Minor cleanup and change to standard driver registration - Mediatek IOMMU driver: - Fixes for IOTLB flushing logic * tag 'iommu-updates-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (47 commits) iommu/amd: Improve amd_iommu_v2_exit() iommu/amd: Remove unused struct fault.devid iommu/amd: Clean up function declarations iommu/amd: Call memunmap in error path iommu/arm-smmu: Account for PMU interrupts iommu/vt-d: Enable ATS for the devices in SATC table iommu/vt-d: Remove unused function intel_svm_capable() iommu/vt-d: Add missing "__init" for rmrr_sanity_check() iommu/vt-d: Move intel_iommu_ops to header file iommu/vt-d: Fix indentation of goto labels iommu/vt-d: Remove unnecessary prototypes iommu/vt-d: Remove unnecessary includes iommu/vt-d: Remove DEFER_DEVICE_DOMAIN_INFO iommu/vt-d: Remove domain and devinfo mempool iommu/vt-d: Remove iova_cache_get/put() iommu/vt-d: Remove finding domain in dmar_insert_one_dev_info() iommu/vt-d: Remove intel_iommu::domains iommu/mediatek: Always tlb_flush_all when each PM resume iommu/mediatek: Add tlb_lock in tlb_flush_all iommu/mediatek: Remove the power status checking in tlb flush all ...
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| @@ -158,185 +158,4 @@ struct iommu_page_response { · 157 unmodified lines | |||
| 158 | __u32 code; | 158 | __u32 code; |
| 159 | }; | 159 | }; |
| 160 | 160 | ||
| 161 | /* defines the granularity of the invalidation */ | ||
| 162 | enum iommu_inv_granularity { | ||
| 163 | IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */ | ||
| 164 | IOMMU_INV_GRANU_PASID, /* PASID-selective invalidation */ | ||
| 165 | IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */ | ||
| 166 | IOMMU_INV_GRANU_NR, /* number of invalidation granularities */ | ||
| 167 | }; | ||
| 168 | |||
| 169 | /** | ||
| 170 | * struct iommu_inv_addr_info - Address Selective Invalidation Structure | ||
| 171 | * | ||
| 172 | * @flags: indicates the granularity of the address-selective invalidation | ||
| 173 | * - If the PASID bit is set, the @pasid field is populated and the invalidation | ||
| 174 | * relates to cache entries tagged with this PASID and matching the address | ||
| 175 | * range. | ||
| 176 | * - If ARCHID bit is set, @archid is populated and the invalidation relates | ||
| 177 | * to cache entries tagged with this architecture specific ID and matching | ||
| 178 | * the address range. | ||
| 179 | * - Both PASID and ARCHID can be set as they may tag different caches. | ||
| 180 | * - If neither PASID or ARCHID is set, global addr invalidation applies. | ||
| 181 | * - The LEAF flag indicates whether only the leaf PTE caching needs to be | ||
| 182 | * invalidated and other paging structure caches can be preserved. | ||
| 183 | * @pasid: process address space ID | ||
| 184 | * @archid: architecture-specific ID | ||
| 185 | * @addr: first stage/level input address | ||
| 186 | * @granule_size: page/block size of the mapping in bytes | ||
| 187 | * @nb_granules: number of contiguous granules to be invalidated | ||
| 188 | */ | ||
| 189 | struct iommu_inv_addr_info { | ||
| 190 | #define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0) | ||
| 191 | #define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1) | ||
| 192 | #define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2) | ||
| 193 | __u32 flags; | ||
| 194 | __u32 archid; | ||
| 195 | __u64 pasid; | ||
| 196 | __u64 addr; | ||
| 197 | __u64 granule_size; | ||
| 198 | __u64 nb_granules; | ||
| 199 | }; | ||
| 200 | |||
| 201 | /** | ||
| 202 | * struct iommu_inv_pasid_info - PASID Selective Invalidation Structure | ||
| 203 | * | ||
| 204 | * @flags: indicates the granularity of the PASID-selective invalidation | ||
| 205 | * - If the PASID bit is set, the @pasid field is populated and the invalidation | ||
| 206 | * relates to cache entries tagged with this PASID and matching the address | ||
| 207 | * range. | ||
| 208 | * - If the ARCHID bit is set, the @archid is populated and the invalidation | ||
| 209 | * relates to cache entries tagged with this architecture specific ID and | ||
| 210 | * matching the address range. | ||
| 211 | * - Both PASID and ARCHID can be set as they may tag different caches. | ||
| 212 | * - At least one of PASID or ARCHID must be set. | ||
| 213 | * @pasid: process address space ID | ||
| 214 | * @archid: architecture-specific ID | ||
| 215 | */ | ||
| 216 | struct iommu_inv_pasid_info { | ||
| 217 | #define IOMMU_INV_PASID_FLAGS_PASID (1 << 0) | ||
| 218 | #define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1) | ||
| 219 | __u32 flags; | ||
| 220 | __u32 archid; | ||
| 221 | __u64 pasid; | ||
| 222 | }; | ||
| 223 | |||
| 224 | /** | ||
| 225 | * struct iommu_cache_invalidate_info - First level/stage invalidation | ||
| 226 | * information | ||
| 227 | * @argsz: User filled size of this data | ||
| 228 | * @version: API version of this structure | ||
| 229 | * @cache: bitfield that allows to select which caches to invalidate | ||
| 230 | * @granularity: defines the lowest granularity used for the invalidation: | ||
| 231 | * domain > PASID > addr | ||
| 232 | * @padding: reserved for future use (should be zero) | ||
| 233 | * @pasid_info: invalidation data when @granularity is %IOMMU_INV_GRANU_PASID | ||
| 234 | * @addr_info: invalidation data when @granularity is %IOMMU_INV_GRANU_ADDR | ||
| 235 | * | ||
| 236 | * Not all the combinations of cache/granularity are valid: | ||
| 237 | * | ||
| 238 | * +--------------+---------------+---------------+---------------+ | ||
| 239 | * | type / | DEV_IOTLB | IOTLB | PASID | | ||
| 240 | * | granularity | | | cache | | ||
| 241 | * +==============+===============+===============+===============+ | ||
| 242 | * | DOMAIN | N/A | Y | Y | | ||
| 243 | * +--------------+---------------+---------------+---------------+ | ||
| 244 | * | PASID | Y | Y | Y | | ||
| 245 | * +--------------+---------------+---------------+---------------+ | ||
| 246 | * | ADDR | Y | Y | N/A | | ||
| 247 | * +--------------+---------------+---------------+---------------+ | ||
| 248 | * | ||
| 249 | * Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument other than | ||
| 250 | * @version and @cache. | ||
| 251 | * | ||
| 252 | * If multiple cache types are invalidated simultaneously, they all | ||
| 253 | * must support the used granularity. | ||
| 254 | */ | ||
| 255 | struct iommu_cache_invalidate_info { | ||
| 256 | __u32 argsz; | ||
| 257 | #define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1 | ||
| 258 | __u32 version; | ||
| 259 | /* IOMMU paging structure cache */ | ||
| 260 | #define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */ | ||
| 261 | #define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */ | ||
| 262 | #define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */ | ||
| 263 | #define IOMMU_CACHE_INV_TYPE_NR (3) | ||
| 264 | __u8 cache; | ||
| 265 | __u8 granularity; | ||
| 266 | __u8 padding[6]; | ||
| 267 | union { | ||
| 268 | struct iommu_inv_pasid_info pasid_info; | ||
| 269 | struct iommu_inv_addr_info addr_info; | ||
| 270 | } granu; | ||
| 271 | }; | ||
| 272 | |||
| 273 | /** | ||
| 274 | * struct iommu_gpasid_bind_data_vtd - Intel VT-d specific data on device and guest | ||
| 275 | * SVA binding. | ||
| 276 | * | ||
| 277 | * @flags: VT-d PASID table entry attributes | ||
| 278 | * @pat: Page attribute table data to compute effective memory type | ||
| 279 | * @emt: Extended memory type | ||
| 280 | * | ||
| 281 | * Only guest vIOMMU selectable and effective options are passed down to | ||
| 282 | * the host IOMMU. | ||
| 283 | */ | ||
| 284 | struct iommu_gpasid_bind_data_vtd { | ||
| 285 | #define IOMMU_SVA_VTD_GPASID_SRE (1 << 0) /* supervisor request */ | ||
| 286 | #define IOMMU_SVA_VTD_GPASID_EAFE (1 << 1) /* extended access enable */ | ||
| 287 | #define IOMMU_SVA_VTD_GPASID_PCD (1 << 2) /* page-level cache disable */ | ||
| 288 | #define IOMMU_SVA_VTD_GPASID_PWT (1 << 3) /* page-level write through */ | ||
| 289 | #define IOMMU_SVA_VTD_GPASID_EMTE (1 << 4) /* extended mem type enable */ | ||
| 290 | #define IOMMU_SVA_VTD_GPASID_CD (1 << 5) /* PASID-level cache disable */ | ||
| 291 | #define IOMMU_SVA_VTD_GPASID_WPE (1 << 6) /* Write protect enable */ | ||
| 292 | #define IOMMU_SVA_VTD_GPASID_LAST (1 << 7) | ||
| 293 | __u64 flags; | ||
| 294 | __u32 pat; | ||
| 295 | __u32 emt; | ||
| 296 | }; | ||
| 297 | |||
| 298 | #define IOMMU_SVA_VTD_GPASID_MTS_MASK (IOMMU_SVA_VTD_GPASID_CD | \ | ||
| 299 | IOMMU_SVA_VTD_GPASID_EMTE | \ | ||
| 300 | IOMMU_SVA_VTD_GPASID_PCD | \ | ||
| 301 | IOMMU_SVA_VTD_GPASID_PWT) | ||
| 302 | |||
| 303 | /** | ||
| 304 | * struct iommu_gpasid_bind_data - Information about device and guest PASID binding | ||
| 305 | * @argsz: User filled size of this data | ||
| 306 | * @version: Version of this data structure | ||
| 307 | * @format: PASID table entry format | ||
| 308 | * @flags: Additional information on guest bind request | ||
| 309 | * @gpgd: Guest page directory base of the guest mm to bind | ||
| 310 | * @hpasid: Process address space ID used for the guest mm in host IOMMU | ||
| 311 | * @gpasid: Process address space ID used for the guest mm in guest IOMMU | ||
| 312 | * @addr_width: Guest virtual address width | ||
| 313 | * @padding: Reserved for future use (should be zero) | ||
| 314 | * @vtd: Intel VT-d specific data | ||
| 315 | * | ||
| 316 | * Guest to host PASID mapping can be an identity or non-identity, where guest | ||
| 317 | * has its own PASID space. For non-identify mapping, guest to host PASID lookup | ||
| 318 | * is needed when VM programs guest PASID into an assigned device. VMM may | ||
| 319 | * trap such PASID programming then request host IOMMU driver to convert guest | ||
| 320 | * PASID to host PASID based on this bind data. | ||
| 321 | */ | ||
| 322 | struct iommu_gpasid_bind_data { | ||
| 323 | __u32 argsz; | ||
| 324 | #define IOMMU_GPASID_BIND_VERSION_1 1 | ||
| 325 | __u32 version; | ||
| 326 | #define IOMMU_PASID_FORMAT_INTEL_VTD 1 | ||
| 327 | #define IOMMU_PASID_FORMAT_LAST 2 | ||
| 328 | __u32 format; | ||
| 329 | __u32 addr_width; | ||
| 330 | #define IOMMU_SVA_GPASID_VAL (1 << 0) /* guest PASID valid */ | ||
| 331 | __u64 flags; | ||
| 332 | __u64 gpgd; | ||
| 333 | __u64 hpasid; | ||
| 334 | __u64 gpasid; | ||
| 335 | __u8 padding[8]; | ||
| 336 | /* Vendor specific data */ | ||
| 337 | union { | ||
| 338 | struct iommu_gpasid_bind_data_vtd vtd; | ||
| 339 | } vendor; | ||
| 340 | }; | ||
| 341 | |||
| 342 | #endif /* _UAPI_IOMMU_H */ | 161 | #endif /* _UAPI_IOMMU_H */ |