In a multiplatform configuration, enabling DEBUG_LL breaks booting on all platforms with incompatible settings. In case of the Marvell platforms of the Orion/MVEBU family, the physical addresses are all the same, we just map them at different virtual addresses, which makes it impossible to run a kernel with DEBUG_LL enabled on a combination of the merged mvebu and the legacy boardfile based platforms. This is easily solved by using the same virtual address everywhere. I picked the address that is already used by mach-mvebu for UART0: 0xfec12000. All these platforms have a 1MB region with their internal registers, almost always at physical address 0xf1000000, so I'm updating the iotable for that entry. In case of mach-dove, this is slightly trickier, as the existing mapping is 8MB and a second 8MB mapping is already at the 0xfec00000 address. I have verified from the datasheet that the last 7MB of the physical mapping are "reserved" and nothing in Linux tries to use it either. I'm putting this 1MB mapping at the same address as the others, and the second 8MB register area immediately before that.
Unified · Split
| @@ -1760,10 +1760,7 @@ config DEBUG_UART_VIRT · 1759 unmodified lines | ||
| 1760 | 1760 | default 0xfc705000 if DEBUG_ZTE_ZX |
| 1761 | 1761 | default 0xfcfe8600 if DEBUG_BCM63XX_UART |
| 1762 | 1762 | default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX |
| 1763 | − default 0xfd012000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_MV78XX0 | |
| 1764 | 1763 | default 0xfd883000 if DEBUG_ALPINE_UART0 |
| 1765 | − default 0xfde12000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_DOVE | |
| 1766 | − default 0xfe012000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_ORION5X | |
| 1767 | 1764 | default 0xfe017000 if DEBUG_MMP_UART2 |
| 1768 | 1765 | default 0xfe018000 if DEBUG_MMP_UART3 |
| 1769 | 1766 | default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART |
| @@ -1778,7 +1775,7 @@ config DEBUG_UART_VIRT · 8 unmodified lines | ||
| 1778 | 1775 | default 0xfec02000 if DEBUG_SOCFPGA_UART0 |
| 1779 | 1776 | default 0xfec02100 if DEBUG_SOCFPGA_ARRIA10_UART1 |
| 1780 | 1777 | default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 |
| 1781 | − default 0xfec12000 if (DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE) && ARCH_MVEBU | |
| 1778 | + default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE | |
| 1782 | 1779 | default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE |
| 1783 | 1780 | default 0xfec10000 if DEBUG_SIRFATLAS7_UART0 |
| 1784 | 1781 | default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 |
| @@ -18,8 +18,8 @@ · 17 unmodified lines | ||
| 18 | 18 | * c8000000 fdb00000 1M Cryptographic SRAM |
| 19 | 19 | * e0000000 @runtime 128M PCIe-0 Memory space |
| 20 | 20 | * e8000000 @runtime 128M PCIe-1 Memory space |
| 21 | − * f1000000 fde00000 8M on-chip south-bridge registers | |
| 22 | − * f1800000 fe600000 8M on-chip north-bridge registers | |
| 21 | + * f1000000 fec00000 1M on-chip south-bridge registers | |
| 22 | + * f1800000 fe400000 8M on-chip north-bridge registers | |
| 23 | 23 | * f2000000 fee00000 1M PCIe-0 I/O space |
| 24 | 24 | * f2100000 fef00000 1M PCIe-1 I/O space |
| 25 | 25 | */ |
| @@ -42,11 +42,11 @@ · 16 unmodified lines | ||
| 42 | 42 | #define DOVE_SCRATCHPAD_SIZE SZ_1M |
| 43 | 43 | |
| 44 | 44 | #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 |
| 45 | −#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) | |
| 46 | −#define DOVE_SB_REGS_SIZE SZ_8M | |
| 45 | +#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000) | |
| 46 | +#define DOVE_SB_REGS_SIZE SZ_1M | |
| 47 | 47 | |
| 48 | 48 | #define DOVE_NB_REGS_PHYS_BASE 0xf1800000 |
| 49 | −#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000) | |
| 49 | +#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000) | |
| 50 | 50 | #define DOVE_NB_REGS_SIZE SZ_8M |
| 51 | 51 | |
| 52 | 52 | #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 |
| @@ -37,7 +37,7 @@ · 36 unmodified lines | ||
| 37 | 37 | * fee50000 f0d00000 64K PCIe #5 I/O space |
| 38 | 38 | * fee60000 f0e00000 64K PCIe #6 I/O space |
| 39 | 39 | * fee70000 f0f00000 64K PCIe #7 I/O space |
| 40 | − * fd000000 f1000000 1M on-chip peripheral registers | |
| 40 | + * fec00000 f1000000 1M on-chip peripheral registers | |
| 41 | 41 | */ |
| 42 | 42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 |
| 43 | 43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 |
| @@ -49,7 +49,7 @@ · 5 unmodified lines | ||
| 49 | 49 | #define MV78XX0_PCIE_IO_SIZE SZ_1M |
| 50 | 50 | |
| 51 | 51 | #define MV78XX0_REGS_PHYS_BASE 0xf1000000 |
| 52 | −#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) | |
| 52 | +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) | |
| 53 | 53 | #define MV78XX0_REGS_SIZE SZ_1M |
| 54 | 54 | |
| 55 | 55 | #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 |
| @@ -31,13 +31,13 @@ · 30 unmodified lines | ||
| 31 | 31 | * fc000000 device bus mappings (cs0/cs1) |
| 32 | 32 | * |
| 33 | 33 | * virt phys size |
| 34 | − * fe000000 f1000000 1M on-chip peripheral registers | |
| 34 | + * fec00000 f1000000 1M on-chip peripheral registers | |
| 35 | 35 | * fee00000 f2000000 64K PCIe I/O space |
| 36 | 36 | * fee10000 f2100000 64K PCI I/O space |
| 37 | 37 | * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) |
| 38 | 38 | ****************************************************************************/ |
| 39 | 39 | #define ORION5X_REGS_PHYS_BASE 0xf1000000 |
| 40 | −#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000) | |
| 40 | +#define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000) | |
| 41 | 41 | #define ORION5X_REGS_SIZE SZ_1M |
| 42 | 42 | |
| 43 | 43 | #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 |