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drm/i915: Add second slice l3 remapping

Certain HSW SKUs have a second bank of L3. This L3 remapping has a separate register set, and interrupt from the first "slice". A slice is simply a term to define some subset of the GPU's l3 cache. This patch implements both the interrupt handler, and ability to communicate with userspace about this second slice. v2: Remove redundant check about non-existent slice. Change warning about interrupts of unknown slices to WARN_ON_ONCE Handle the case where we get 2 slice interrupts concurrently, and switch the tracking of interrupts to be non-destructive (all Ville) Don't enable/mask the second slice parity interrupt for ivb/vlv (even though all docs I can find claim it's rsvd) (Ville + Bryan) Keep BYT excluded from L3 parity v3: Fix the slice = ffs to be decremented by one (found by Ville). When I initially did my testing on the series, I was using 1-based slice counting, so this code was correct. Not sure why my simpler tests that I've been running since then didn't pick it up sooner.

Ben Widawsky committed 13 years ago

Commit 35a85ac1 parent 1c966dd7 files · +117 −61Browse files

Showing the changes to include/uapi (1 of 7 files). Show all

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include/uapi/drm/i915_drm.h+4−4
@@ -38,10 +38,10 @@ · 37 unmodified lines
3838 *
3939 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
4040 * event from the gpu l3 cache. Additional information supplied is ROW,
41− * BANK, SUBBANK of the affected cacheline. Userspace should keep track of
42− * these events and if a specific cache-line seems to have a persistent
43− * error remap it with the l3 remapping tool supplied in intel-gpu-tools.
44− * The value supplied with the event is always 1.
41+ * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
42+ * track of these events and if a specific cache-line seems to have a
43+ * persistent error remap it with the l3 remapping tool supplied in
44+ * intel-gpu-tools. The value supplied with the event is always 1.
4545 *
4646 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
4747 * hangcheck. The error detection event is a good indicator of when things

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