| @@ -928,9 +928,9 @@ static int nand_reset_interface(struct nand_chip *chip, int chipnr) · 927 unmodified lines |
| 928 | * timings to timing mode 0. | 928 | * timings to timing mode 0. |
| 929 | */ | 929 | */ |
| 930 | | 930 | |
| 931 | onfi_fill_interface_config(chip, &chip->interface_config, | 931 | chip->current_interface_config = nand_get_reset_interface_config(); |
| 932 | NAND_SDR_IFACE, 0); | 932 | ret = ops->setup_interface(chip, chipnr, |
| 933 | ret = ops->setup_interface(chip, chipnr, &chip->interface_config); | 933 | chip->current_interface_config); |
| 934 | if (ret) | 934 | if (ret) |
| 935 | pr_err("Failed to configure data interface to SDR timing mode 0\n"); | 935 | pr_err("Failed to configure data interface to SDR timing mode 0\n"); |
| 936 | | 936 | |
| @@ -949,13 +949,25 @@ static int nand_reset_interface(struct nand_chip *chip, int chipnr) · 12 unmodified lines |
| 949 | */ | 949 | */ |
| 950 | static int nand_setup_interface(struct nand_chip *chip, int chipnr) | 950 | static int nand_setup_interface(struct nand_chip *chip, int chipnr) |
| 951 | { | 951 | { |
| 952 | u8 mode = chip->interface_config.timings.mode; | 952 | const struct nand_controller_ops *ops = chip->controller->ops; |
| 953 | u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { mode, }; | 953 | u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { }; |
| 954 | int ret; | 954 | int ret; |
| 955 | | 955 | |
| 956 | if (!nand_controller_can_setup_interface(chip)) | 956 | if (!nand_controller_can_setup_interface(chip)) |
| 957 | return 0; | 957 | return 0; |
| 958 | | 958 | |
| | 959 | /* |
| | 960 | * A nand_reset_interface() put both the NAND chip and the NAND |
| | 961 | * controller in timings mode 0. If the default mode for this chip is |
| | 962 | * also 0, no need to proceed to the change again. Plus, at probe time, |
| | 963 | * nand_setup_interface() uses ->set/get_features() which would |
| | 964 | * fail anyway as the parameter page is not available yet. |
| | 965 | */ |
| | 966 | if (!chip->best_interface_config) |
| | 967 | return 0; |
| | 968 | |
| | 969 | tmode_param[0] = chip->best_interface_config->timings.mode; |
| | 970 | |
| 959 | /* Change the mode on the chip side (if supported by the NAND chip) */ | 971 | /* Change the mode on the chip side (if supported by the NAND chip) */ |
| 960 | if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) { | 972 | if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) { |
| 961 | nand_select_target(chip, chipnr); | 973 | nand_select_target(chip, chipnr); |
| @@ -967,14 +979,13 @@ static int nand_setup_interface(struct nand_chip *chip, int chipnr) · 5 unmodified lines |
| 967 | } | 979 | } |
| 968 | | 980 | |
| 969 | /* Change the mode on the controller side */ | 981 | /* Change the mode on the controller side */ |
| 970 | ret = chip->controller->ops->setup_interface(chip, chipnr, | 982 | ret = ops->setup_interface(chip, chipnr, chip->best_interface_config); |
| 971 | &chip->interface_config); | | |
| 972 | if (ret) | 983 | if (ret) |
| 973 | return ret; | 984 | return ret; |
| 974 | | 985 | |
| 975 | /* Check the mode has been accepted by the chip, if supported */ | 986 | /* Check the mode has been accepted by the chip, if supported */ |
| 976 | if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) | 987 | if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) |
| 977 | return 0; | 988 | goto update_interface_config; |
| 978 | | 989 | |
| 979 | memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | 990 | memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN); |
| 980 | nand_select_target(chip, chipnr); | 991 | nand_select_target(chip, chipnr); |
| @@ -984,12 +995,15 @@ static int nand_setup_interface(struct nand_chip *chip, int chipnr) · 3 unmodified lines |
| 984 | if (ret) | 995 | if (ret) |
| 985 | goto err_reset_chip; | 996 | goto err_reset_chip; |
| 986 | | 997 | |
| 987 | if (tmode_param[0] != mode) { | 998 | if (tmode_param[0] != chip->best_interface_config->timings.mode) { |
| 988 | pr_warn("timing mode %d not acknowledged by the NAND chip\n", | 999 | pr_warn("timing mode %d not acknowledged by the NAND chip\n", |
| 989 | mode); | 1000 | chip->best_interface_config->timings.mode); |
| 990 | goto err_reset_chip; | 1001 | goto err_reset_chip; |
| 991 | } | 1002 | } |
| 992 | | 1003 | |
| | 1004 | update_interface_config: |
| | 1005 | chip->current_interface_config = chip->best_interface_config; |
| | 1006 | |
| 993 | return 0; | 1007 | return 0; |
| 994 | | 1008 | |
| 995 | err_reset_chip: | 1009 | err_reset_chip: |
| @@ -1031,8 +1045,10 @@ int nand_choose_best_sdr_timings(struct nand_chip *chip, · 35 unmodified lines |
| 1031 | /* Verify the controller supports the requested interface */ | 1045 | /* Verify the controller supports the requested interface */ |
| 1032 | ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, | 1046 | ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, |
| 1033 | iface); | 1047 | iface); |
| 1034 | if (!ret) | 1048 | if (!ret) { |
| | 1049 | chip->best_interface_config = iface; |
| 1035 | return ret; | 1050 | return ret; |
| | 1051 | } |
| 1036 | | 1052 | |
| 1037 | /* Fallback to slower modes */ | 1053 | /* Fallback to slower modes */ |
| 1038 | best_mode = iface->timings.mode; | 1054 | best_mode = iface->timings.mode; |
| @@ -1046,9 +1062,11 @@ int nand_choose_best_sdr_timings(struct nand_chip *chip, · 7 unmodified lines |
| 1046 | ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, | 1062 | ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, |
| 1047 | iface); | 1063 | iface); |
| 1048 | if (!ret) | 1064 | if (!ret) |
| 1049 | return 0; | 1065 | break; |
| 1050 | } | 1066 | } |
| 1051 | | 1067 | |
| | 1068 | chip->best_interface_config = iface; |
| | 1069 | |
| 1052 | return 0; | 1070 | return 0; |
| 1053 | } | 1071 | } |
| 1054 | | 1072 | |
| @@ -1067,15 +1085,25 @@ int nand_choose_best_sdr_timings(struct nand_chip *chip, · 12 unmodified lines |
| 1067 | */ | 1085 | */ |
| 1068 | static int nand_choose_interface_config(struct nand_chip *chip) | 1086 | static int nand_choose_interface_config(struct nand_chip *chip) |
| 1069 | { | 1087 | { |
| | 1088 | struct nand_interface_config *iface; |
| | 1089 | int ret; |
| | 1090 | |
| 1070 | if (!nand_controller_can_setup_interface(chip)) | 1091 | if (!nand_controller_can_setup_interface(chip)) |
| 1071 | return 0; | 1092 | return 0; |
| 1072 | | 1093 | |
| | 1094 | iface = kzalloc(sizeof(*iface), GFP_KERNEL); |
| | 1095 | if (!iface) |
| | 1096 | return -ENOMEM; |
| | 1097 | |
| 1073 | if (chip->ops.choose_interface_config) | 1098 | if (chip->ops.choose_interface_config) |
| 1074 | return chip->ops.choose_interface_config(chip, | 1099 | ret = chip->ops.choose_interface_config(chip, iface); |
| 1075 | &chip->interface_config); | 1100 | else |
| | 1101 | ret = nand_choose_best_sdr_timings(chip, iface, NULL); |
| 1076 | | 1102 | |
| 1077 | return nand_choose_best_sdr_timings(chip, &chip->interface_config, | 1103 | if (ret) |
| 1078 | NULL); | 1104 | kfree(iface); |
| | 1105 | |
| | 1106 | return ret; |
| 1079 | } | 1107 | } |
| 1080 | | 1108 | |
| 1081 | /** | 1109 | /** |
| @@ -2501,7 +2529,6 @@ EXPORT_SYMBOL_GPL(nand_subop_get_data_len); · 1419 unmodified lines |
| 2501 | */ | 2529 | */ |
| 2502 | int nand_reset(struct nand_chip *chip, int chipnr) | 2530 | int nand_reset(struct nand_chip *chip, int chipnr) |
| 2503 | { | 2531 | { |
| 2504 | struct nand_interface_config saved_intf_config = chip->interface_config; | | |
| 2505 | int ret; | 2532 | int ret; |
| 2506 | | 2533 | |
| 2507 | ret = nand_reset_interface(chip, chipnr); | 2534 | ret = nand_reset_interface(chip, chipnr); |
| @@ -2519,18 +2546,6 @@ int nand_reset(struct nand_chip *chip, int chipnr) · 11 unmodified lines |
| 2519 | if (ret) | 2546 | if (ret) |
| 2520 | return ret; | 2547 | return ret; |
| 2521 | | 2548 | |
| 2522 | /* | | |
| 2523 | * A nand_reset_interface() put both the NAND chip and the NAND | | |
| 2524 | * controller in timings mode 0. If the default mode for this chip is | | |
| 2525 | * also 0, no need to proceed to the change again. Plus, at probe time, | | |
| 2526 | * nand_setup_interface() uses ->set/get_features() which would | | |
| 2527 | * fail anyway as the parameter page is not available yet. | | |
| 2528 | */ | | |
| 2529 | if (!memcmp(&chip->interface_config, &saved_intf_config, | | |
| 2530 | sizeof(saved_intf_config))) | | |
| 2531 | return 0; | | |
| 2532 | | | |
| 2533 | chip->interface_config = saved_intf_config; | | |
| 2534 | ret = nand_setup_interface(chip, chipnr); | 2549 | ret = nand_setup_interface(chip, chipnr); |
| 2535 | if (ret) | 2550 | if (ret) |
| 2536 | return ret; | 2551 | return ret; |
| @@ -5198,7 +5213,7 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips, · 2661 unmodified lines |
| 5198 | mutex_init(&chip->lock); | 5213 | mutex_init(&chip->lock); |
| 5199 | | 5214 | |
| 5200 | /* Enforce the right timings for reset/detection */ | 5215 | /* Enforce the right timings for reset/detection */ |
| 5201 | onfi_fill_interface_config(chip, &chip->interface_config, NAND_SDR_IFACE, 0); | 5216 | chip->current_interface_config = nand_get_reset_interface_config(); |
| 5202 | | 5217 | |
| 5203 | ret = nand_dt_init(chip); | 5218 | ret = nand_dt_init(chip); |
| 5204 | if (ret) | 5219 | if (ret) |
| @@ -5994,7 +6009,7 @@ static int nand_scan_tail(struct nand_chip *chip) · 789 unmodified lines |
| 5994 | for (i = 0; i < nanddev_ntargets(&chip->base); i++) { | 6009 | for (i = 0; i < nanddev_ntargets(&chip->base); i++) { |
| 5995 | ret = nand_setup_interface(chip, i); | 6010 | ret = nand_setup_interface(chip, i); |
| 5996 | if (ret) | 6011 | if (ret) |
| 5997 | goto err_nanddev_cleanup; | 6012 | goto err_free_interface_config; |
| 5998 | } | 6013 | } |
| 5999 | | 6014 | |
| 6000 | /* Check, if we should skip the bad block table scan */ | 6015 | /* Check, if we should skip the bad block table scan */ |
| @@ -6004,10 +6019,12 @@ static int nand_scan_tail(struct nand_chip *chip) · 3 unmodified lines |
| 6004 | /* Build bad block table */ | 6019 | /* Build bad block table */ |
| 6005 | ret = nand_create_bbt(chip); | 6020 | ret = nand_create_bbt(chip); |
| 6006 | if (ret) | 6021 | if (ret) |
| 6007 | goto err_nanddev_cleanup; | 6022 | goto err_free_interface_config; |
| 6008 | | 6023 | |
| 6009 | return 0; | 6024 | return 0; |
| 6010 | | 6025 | |
| | 6026 | err_free_interface_config: |
| | 6027 | kfree(chip->best_interface_config); |
| 6011 | | 6028 | |
| 6012 | err_nanddev_cleanup: | 6029 | err_nanddev_cleanup: |
| 6013 | nanddev_cleanup(&chip->base); | 6030 | nanddev_cleanup(&chip->base); |
| @@ -6101,6 +6118,9 @@ void nand_cleanup(struct nand_chip *chip) · 87 unmodified lines |
| 6101 | & NAND_BBT_DYNAMICSTRUCT) | 6118 | & NAND_BBT_DYNAMICSTRUCT) |
| 6102 | kfree(chip->badblock_pattern); | 6119 | kfree(chip->badblock_pattern); |
| 6103 | | 6120 | |
| | 6121 | /* Free the data interface */ |
| | 6122 | kfree(chip->best_interface_config); |
| | 6123 | |
| 6104 | /* Free manufacturer priv data. */ | 6124 | /* Free manufacturer priv data. */ |
| 6105 | nand_manufacturer_cleanup(chip); | 6125 | nand_manufacturer_cleanup(chip); |
| 6106 | | 6126 | |