Take a early return from the clock recovery training when the sink reports CR_DONE for all lanes. There is no point in trying to adjust the link parameters further.
Unified · Split
| @@ -410,11 +410,6 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) · 409 unmodified lines | ||
| 410 | 410 | if (retval < 0) |
| 411 | 411 | return retval; |
| 412 | 412 | |
| 413 | − retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, | |
| 414 | − adjust_request, 2); | |
| 415 | − if (retval < 0) | |
| 416 | − return retval; | |
| 417 | − | |
| 418 | 413 | if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { |
| 419 | 414 | /* set training pattern 2 for EQ */ |
| 420 | 415 | analogix_dp_set_training_pattern(dp, TRAINING_PTN2); |
| @@ -427,30 +422,32 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) · 6 unmodified lines | ||
| 427 | 422 | |
| 428 | 423 | dev_dbg(dp->dev, "Link Training Clock Recovery success\n"); |
| 429 | 424 | dp->link_train.lt_state = EQUALIZER_TRAINING; |
| 430 | − } else { | |
| 431 | − for (lane = 0; lane < lane_count; lane++) { | |
| 432 | − training_lane = analogix_dp_get_lane_link_training( | |
| 433 | − dp, lane); | |
| 434 | − voltage_swing = analogix_dp_get_adjust_request_voltage( | |
| 435 | − adjust_request, lane); | |
| 436 | − pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( | |
| 437 | − adjust_request, lane); | |
| 438 | − | |
| 439 | − if (DPCD_VOLTAGE_SWING_GET(training_lane) == | |
| 440 | − voltage_swing && | |
| 441 | − DPCD_PRE_EMPHASIS_GET(training_lane) == | |
| 442 | − pre_emphasis) | |
| 443 | − dp->link_train.cr_loop[lane]++; | |
| 444 | − | |
| 445 | − if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || | |
| 446 | − voltage_swing == VOLTAGE_LEVEL_3 || | |
| 447 | − pre_emphasis == PRE_EMPHASIS_LEVEL_3) { | |
| 448 | − dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", | |
| 449 | − dp->link_train.cr_loop[lane], | |
| 450 | − voltage_swing, pre_emphasis); | |
| 451 | − analogix_dp_reduce_link_rate(dp); | |
| 452 | − return -EIO; | |
| 453 | − } | |
| 425 | + | |
| 426 | + return 0; | |
| 427 | + } | |
| 428 | + | |
| 429 | + retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, | |
| 430 | + adjust_request, 2); | |
| 431 | + if (retval < 0) | |
| 432 | + return retval; | |
| 433 | + | |
| 434 | + for (lane = 0; lane < lane_count; lane++) { | |
| 435 | + training_lane = analogix_dp_get_lane_link_training(dp, lane); | |
| 436 | + voltage_swing = analogix_dp_get_adjust_request_voltage(adjust_request, lane); | |
| 437 | + pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(adjust_request, lane); | |
| 438 | + | |
| 439 | + if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing && | |
| 440 | + DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis) | |
| 441 | + dp->link_train.cr_loop[lane]++; | |
| 442 | + | |
| 443 | + if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || | |
| 444 | + voltage_swing == VOLTAGE_LEVEL_3 || | |
| 445 | + pre_emphasis == PRE_EMPHASIS_LEVEL_3) { | |
| 446 | + dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", | |
| 447 | + dp->link_train.cr_loop[lane], | |
| 448 | + voltage_swing, pre_emphasis); | |
| 449 | + analogix_dp_reduce_link_rate(dp); | |
| 450 | + return -EIO; | |
| 454 | 451 | } |
| 455 | 452 | } |
| 456 | 453 | |