Unified · Split
| @@ -50,7 +50,9 @@ · 49 unmodified lines | ||
| 50 | 50 | |
| 51 | 51 | <sect1><title>Delaying, scheduling, and timer routines</title> |
| 52 | 52 | !Iinclude/linux/sched.h |
| 53 | −!Ekernel/sched.c | |
| 53 | +!Ekernel/sched/core.c | |
| 54 | +!Ikernel/sched/cpupri.c | |
| 55 | +!Ikernel/sched/fair.c | |
| 54 | 56 | !Iinclude/linux/completion.h |
| 55 | 57 | !Ekernel/timer.c |
| 56 | 58 | </sect1> |
| @@ -100,9 +102,12 @@ X!Iinclude/linux/kobject.h · 43 unmodified lines | ||
| 100 | 102 | !Iinclude/linux/device.h |
| 101 | 103 | </sect1> |
| 102 | 104 | <sect1><title>Device Drivers Base</title> |
| 105 | +!Idrivers/base/init.c | |
| 103 | 106 | !Edrivers/base/driver.c |
| 104 | 107 | !Edrivers/base/core.c |
| 108 | +!Edrivers/base/syscore.c | |
| 105 | 109 | !Edrivers/base/class.c |
| 110 | +!Idrivers/base/node.c | |
| 106 | 111 | !Edrivers/base/firmware_class.c |
| 107 | 112 | !Edrivers/base/transport_class.c |
| 108 | 113 | <!-- Cannot be included, because |
| @@ -111,13 +116,18 @@ X!Iinclude/linux/kobject.h · 2 unmodified lines | ||
| 111 | 116 | exceed allowed 44 characters maximum |
| 112 | 117 | X!Edrivers/base/attribute_container.c |
| 113 | 118 | --> |
| 114 | −!Edrivers/base/sys.c | |
| 119 | +!Edrivers/base/dd.c | |
| 115 | 120 | <!-- |
| 116 | 121 | X!Edrivers/base/interface.c |
| 117 | 122 | --> |
| 118 | 123 | !Iinclude/linux/platform_device.h |
| 119 | 124 | !Edrivers/base/platform.c |
| 120 | 125 | !Edrivers/base/bus.c |
| 126 | + </sect1> | |
| 127 | + <sect1><title>Device Drivers DMA Management</title> | |
| 128 | +!Edrivers/base/dma-buf.c | |
| 129 | +!Edrivers/base/dma-coherent.c | |
| 130 | +!Edrivers/base/dma-mapping.c | |
| 121 | 131 | </sect1> |
| 122 | 132 | <sect1><title>Device Drivers Power Management</title> |
| 123 | 133 | !Edrivers/base/power/main.c |
| @@ -216,9 +226,8 @@ X!Isound/sound_firmware.c · 92 unmodified lines | ||
| 216 | 226 | |
| 217 | 227 | <chapter id="uart16x50"> |
| 218 | 228 | <title>16x50 UART Driver</title> |
| 219 | −!Iinclude/linux/serial_core.h | |
| 220 | 229 | !Edrivers/tty/serial/serial_core.c |
| 221 | −!Edrivers/tty/serial/8250.c | |
| 230 | +!Edrivers/tty/serial/8250/8250.c | |
| 222 | 231 | </chapter> |
| 223 | 232 | |
| 224 | 233 | <chapter id="fbdev"> |
| @@ -317,7 +317,7 @@ CPU B: spin_unlock_irqrestore(&dev_lock, flags) · 316 unmodified lines | ||
| 317 | 317 | <chapter id="pubfunctions"> |
| 318 | 318 | <title>Public Functions Provided</title> |
| 319 | 319 | !Iarch/x86/include/asm/io.h |
| 320 | −!Elib/iomap.c | |
| 320 | +!Elib/pci_iomap.c | |
| 321 | 321 | </chapter> |
| 322 | 322 | |
| 323 | 323 | </book> |
| @@ -163,14 +163,16 @@ get/set up to 64 properties. The actual meaning of each property is described on · 162 unmodified lines | ||
| 163 | 163 | <section id="DTV-FREQUENCY"> |
| 164 | 164 | <title><constant>DTV_FREQUENCY</constant></title> |
| 165 | 165 | |
| 166 | − <para>Central frequency of the channel, in HZ.</para> | |
| 166 | + <para>Central frequency of the channel.</para> | |
| 167 | 167 | |
| 168 | 168 | <para>Notes:</para> |
| 169 | − <para>1)For ISDB-T, the channels are usually transmitted with an offset of 143kHz. | |
| 169 | + <para>1)For satellital delivery systems, it is measured in kHz. | |
| 170 | + For the other ones, it is measured in Hz.</para> | |
| 171 | + <para>2)For ISDB-T, the channels are usually transmitted with an offset of 143kHz. | |
| 170 | 172 | E.g. a valid frequncy could be 474143 kHz. The stepping is bound to the bandwidth of |
| 171 | 173 | the channel which is 6MHz.</para> |
| 172 | 174 | |
| 173 | − <para>2)As in ISDB-Tsb the channel consists of only one or three segments the | |
| 175 | + <para>3)As in ISDB-Tsb the channel consists of only one or three segments the | |
| 174 | 176 | frequency step is 429kHz, 3*429 respectively. As for ISDB-T the |
| 175 | 177 | central frequency of the channel is expected.</para> |
| 176 | 178 | </section> |
| @@ -735,14 +737,10 @@ typedef enum fe_hierarchy { · 558 unmodified lines | ||
| 735 | 737 | <listitem><para><link linkend="DTV-TUNE"><constant>DTV_TUNE</constant></link></para></listitem> |
| 736 | 738 | <listitem><para><link linkend="DTV-CLEAR"><constant>DTV_CLEAR</constant></link></para></listitem> |
| 737 | 739 | <listitem><para><link linkend="DTV-FREQUENCY"><constant>DTV_FREQUENCY</constant></link></para></listitem> |
| 738 | − <listitem><para><link linkend="DTV-MODULATION"><constant>DTV_MODULATION</constant></link></para></listitem> | |
| 739 | 740 | <listitem><para><link linkend="DTV-BANDWIDTH-HZ"><constant>DTV_BANDWIDTH_HZ</constant></link></para></listitem> |
| 740 | 741 | <listitem><para><link linkend="DTV-INVERSION"><constant>DTV_INVERSION</constant></link></para></listitem> |
| 741 | − <listitem><para><link linkend="DTV-CODE-RATE-HP"><constant>DTV_CODE_RATE_HP</constant></link></para></listitem> | |
| 742 | − <listitem><para><link linkend="DTV-CODE-RATE-LP"><constant>DTV_CODE_RATE_LP</constant></link></para></listitem> | |
| 743 | 742 | <listitem><para><link linkend="DTV-GUARD-INTERVAL"><constant>DTV_GUARD_INTERVAL</constant></link></para></listitem> |
| 744 | 743 | <listitem><para><link linkend="DTV-TRANSMISSION-MODE"><constant>DTV_TRANSMISSION_MODE</constant></link></para></listitem> |
| 745 | − <listitem><para><link linkend="DTV-HIERARCHY"><constant>DTV_HIERARCHY</constant></link></para></listitem> | |
| 746 | 744 | <listitem><para><link linkend="DTV-ISDBT-LAYER-ENABLED"><constant>DTV_ISDBT_LAYER_ENABLED</constant></link></para></listitem> |
| 747 | 745 | <listitem><para><link linkend="DTV-ISDBT-PARTIAL-RECEPTION"><constant>DTV_ISDBT_PARTIAL_RECEPTION</constant></link></para></listitem> |
| 748 | 746 | <listitem><para><link linkend="DTV-ISDBT-SOUND-BROADCASTING"><constant>DTV_ISDBT_SOUND_BROADCASTING</constant></link></para></listitem> |
| @@ -183,7 +183,12 @@ applications must set the array to zero.</entry> · 182 unmodified lines | ||
| 183 | 183 | <entry>__u32</entry> |
| 184 | 184 | <entry><structfield>ctrl_class</structfield></entry> |
| 185 | 185 | <entry>The control class to which all controls belong, see |
| 186 | −<xref linkend="ctrl-class" />.</entry> | |
| 186 | +<xref linkend="ctrl-class" />. Drivers that use a kernel framework for handling | |
| 187 | +controls will also accept a value of 0 here, meaning that the controls can | |
| 188 | +belong to any control class. Whether drivers support this can be tested by setting | |
| 189 | +<structfield>ctrl_class</structfield> to 0 and calling <constant>VIDIOC_TRY_EXT_CTRLS</constant> | |
| 190 | +with a <structfield>count</structfield> of 0. If that succeeds, then the driver | |
| 191 | +supports this feature.</entry> | |
| 187 | 192 | </row> |
| 188 | 193 | <row> |
| 189 | 194 | <entry>__u32</entry> |
| @@ -194,10 +199,13 @@ also be zero.</entry> · 4 unmodified lines | ||
| 194 | 199 | <row> |
| 195 | 200 | <entry>__u32</entry> |
| 196 | 201 | <entry><structfield>error_idx</structfield></entry> |
| 197 | − <entry>Set by the driver in case of an error. It is the | |
| 198 | −index of the control causing the error or equal to 'count' when the | |
| 199 | −error is not associated with a particular control. Undefined when the | |
| 200 | −ioctl returns 0 (success).</entry> | |
| 202 | + <entry>Set by the driver in case of an error. If it is equal | |
| 203 | +to <structfield>count</structfield>, then no actual changes were made to | |
| 204 | +controls. In other words, the error was not associated with setting a particular | |
| 205 | +control. If it is another value, then only the controls up to <structfield>error_idx-1</structfield> | |
| 206 | +were modified and control <structfield>error_idx</structfield> is the one that | |
| 207 | +caused the error. The <structfield>error_idx</structfield> value is undefined | |
| 208 | +if the ioctl returned 0 (success).</entry> | |
| 201 | 209 | </row> |
| 202 | 210 | <row> |
| 203 | 211 | <entry>__u32</entry> |
| @@ -364,15 +364,20 @@ capability and it is cleared otherwise.</entry> · 363 unmodified lines | ||
| 364 | 364 | <row> |
| 365 | 365 | <entry><constant>V4L2_FBUF_FLAG_OVERLAY</constant></entry> |
| 366 | 366 | <entry>0x0002</entry> |
| 367 | − <entry>The frame buffer is an overlay surface the same | |
| 368 | −size as the capture. [?]</entry> | |
| 369 | − </row> | |
| 370 | − <row> | |
| 371 | − <entry spanname="hspan">The purpose of | |
| 372 | −<constant>V4L2_FBUF_FLAG_OVERLAY</constant> was never quite clear. | |
| 373 | −Most drivers seem to ignore this flag. For compatibility with the | |
| 374 | −<wordasword>bttv</wordasword> driver applications should set the | |
| 375 | −<constant>V4L2_FBUF_FLAG_OVERLAY</constant> flag.</entry> | |
| 367 | + <entry>If this flag is set for a video capture device, then the | |
| 368 | +driver will set the initial overlay size to cover the full framebuffer size, | |
| 369 | +otherwise the existing overlay size (as set by &VIDIOC-S-FMT;) will be used. | |
| 370 | + | |
| 371 | +Only one video capture driver (bttv) supports this flag. The use of this flag | |
| 372 | +for capture devices is deprecated. There is no way to detect which drivers | |
| 373 | +support this flag, so the only reliable method of setting the overlay size is | |
| 374 | +through &VIDIOC-S-FMT;. | |
| 375 | + | |
| 376 | +If this flag is set for a video output device, then the video output overlay | |
| 377 | +window is relative to the top-left corner of the framebuffer and restricted | |
| 378 | +to the size of the framebuffer. If it is cleared, then the video output | |
| 379 | +overlay window is relative to the video output display. | |
| 380 | + </entry> | |
| 376 | 381 | </row> |
| 377 | 382 | <row> |
| 378 | 383 | <entry><constant>V4L2_FBUF_FLAG_CHROMAKEY</constant></entry> |
| @@ -98,8 +98,11 @@ the &v4l2-output; <structfield>modulator</structfield> field and the · 97 unmodified lines | ||
| 98 | 98 | <entry>&v4l2-tuner-type;</entry> |
| 99 | 99 | <entry><structfield>type</structfield></entry> |
| 100 | 100 | <entry>The tuner type. This is the same value as in the |
| 101 | −&v4l2-tuner; <structfield>type</structfield> field. The field is not | |
| 102 | −applicable to modulators, &ie; ignored by drivers.</entry> | |
| 101 | +&v4l2-tuner; <structfield>type</structfield> field. The type must be set | |
| 102 | +to <constant>V4L2_TUNER_RADIO</constant> for <filename>/dev/radioX</filename> | |
| 103 | +device nodes, and to <constant>V4L2_TUNER_ANALOG_TV</constant> | |
| 104 | +for all others. The field is not applicable to modulators, &ie; ignored | |
| 105 | +by drivers.</entry> | |
| 103 | 106 | </row> |
| 104 | 107 | <row> |
| 105 | 108 | <entry>__u32</entry> |
| @@ -61,8 +61,8 @@ desired input in an integer and call the · 60 unmodified lines | ||
| 61 | 61 | <constant>VIDIOC_S_INPUT</constant> ioctl with a pointer to this |
| 62 | 62 | integer. Side effects are possible. For example inputs may support |
| 63 | 63 | different video standards, so the driver may implicitly switch the |
| 64 | −current standard. It is good practice to select an input before | |
| 65 | −querying or negotiating any other parameters.</para> | |
| 64 | +current standard. Because of these possible side effects applications | |
| 65 | +must select an input before querying or negotiating any other parameters.</para> | |
| 66 | 66 | |
| 67 | 67 | <para>Information about video inputs is available using the |
| 68 | 68 | &VIDIOC-ENUMINPUT; ioctl.</para> |
| @@ -61,8 +61,9 @@ desired output in an integer and call the · 60 unmodified lines | ||
| 61 | 61 | <constant>VIDIOC_S_OUTPUT</constant> ioctl with a pointer to this integer. |
| 62 | 62 | Side effects are possible. For example outputs may support different |
| 63 | 63 | video standards, so the driver may implicitly switch the current |
| 64 | −standard. It is good practice to select an output before querying or | |
| 65 | −negotiating any other parameters.</para> | |
| 64 | +standard. | |
| 65 | +standard. Because of these possible side effects applications | |
| 66 | +must select an output before querying or negotiating any other parameters.</para> | |
| 66 | 67 | |
| 67 | 68 | <para>Information about video outputs is available using the |
| 68 | 69 | &VIDIOC-ENUMOUTPUT; ioctl.</para> |
| @@ -47,20 +47,53 @@ directory apei/einj. The following files are provided. · 46 unmodified lines | ||
| 47 | 47 | |
| 48 | 48 | - param1 |
| 49 | 49 | This file is used to set the first error parameter value. Effect of |
| 50 | − parameter depends on error_type specified. For memory error, this is | |
| 51 | − physical memory address. Only available if param_extension module | |
| 52 | − parameter is specified. | |
| 50 | + parameter depends on error_type specified. | |
| 53 | 51 | |
| 54 | 52 | - param2 |
| 55 | 53 | This file is used to set the second error parameter value. Effect of |
| 56 | − parameter depends on error_type specified. For memory error, this is | |
| 57 | − physical memory address mask. Only available if param_extension | |
| 58 | − module parameter is specified. | |
| 54 | + parameter depends on error_type specified. | |
| 55 | + | |
| 56 | +BIOS versions based in the ACPI 4.0 specification have limited options | |
| 57 | +to control where the errors are injected. Your BIOS may support an | |
| 58 | +extension (enabled with the param_extension=1 module parameter, or | |
| 59 | +boot command line einj.param_extension=1). This allows the address | |
| 60 | +and mask for memory injections to be specified by the param1 and | |
| 61 | +param2 files in apei/einj. | |
| 62 | + | |
| 63 | +BIOS versions using the ACPI 5.0 specification have more control over | |
| 64 | +the target of the injection. For processor related errors (type 0x1, | |
| 65 | +0x2 and 0x4) the APICID of the target should be provided using the | |
| 66 | +param1 file in apei/einj. For memory errors (type 0x8, 0x10 and 0x20) | |
| 67 | +the address is set using param1 with a mask in param2 (0x0 is equivalent | |
| 68 | +to all ones). For PCI express errors (type 0x40, 0x80 and 0x100) the | |
| 69 | +segment, bus, device and function are specified using param1: | |
| 70 | + | |
| 71 | + 31 24 23 16 15 11 10 8 7 0 | |
| 72 | + +-------------------------------------------------+ | |
| 73 | + | segment | bus | device | function | reserved | | |
| 74 | + +-------------------------------------------------+ | |
| 75 | + | |
| 76 | +An ACPI 5.0 BIOS may also allow vendor specific errors to be injected. | |
| 77 | +In this case a file named vendor will contain identifying information | |
| 78 | +from the BIOS that hopefully will allow an application wishing to use | |
| 79 | +the vendor specific extension to tell that they are running on a BIOS | |
| 80 | +that supports it. All vendor extensions have the 0x80000000 bit set in | |
| 81 | +error_type. A file vendor_flags controls the interpretation of param1 | |
| 82 | +and param2 (1 = PROCESSOR, 2 = MEMORY, 4 = PCI). See your BIOS vendor | |
| 83 | +documentation for details (and expect changes to this API if vendors | |
| 84 | +creativity in using this feature expands beyond our expectations). | |
| 85 | + | |
| 86 | +Example: | |
| 87 | +# cd /sys/kernel/debug/apei/einj | |
| 88 | +# cat available_error_type # See which errors can be injected | |
| 89 | +0x00000002 Processor Uncorrectable non-fatal | |
| 90 | +0x00000008 Memory Correctable | |
| 91 | +0x00000010 Memory Uncorrectable non-fatal | |
| 92 | +# echo 0x12345000 > param1 # Set memory address for injection | |
| 93 | +# echo 0xfffffffffffff000 > param2 # Mask - anywhere in this page | |
| 94 | +# echo 0x8 > error_type # Choose correctable memory error | |
| 95 | +# echo 1 > error_inject # Inject now | |
| 59 | 96 | |
| 60 | −Injecting parameter support is a BIOS version specific extension, that | |
| 61 | −is, it only works on some BIOS version. If you want to use it, please | |
| 62 | −make sure your BIOS version has the proper support and specify | |
| 63 | −"param_extension=y" in module parameter. | |
| 64 | 97 | |
| 65 | 98 | For more information about EINJ, please refer to ACPI specification |
| 66 | −version 4.0, section 17.5. | |
| 99 | +version 4.0, section 17.5 and ACPI 5.0, section 18.6. | |
| @@ -447,6 +447,9 @@ Your cooperation is appreciated. · 446 unmodified lines | ||
| 447 | 447 | 234 = /dev/btrfs-control Btrfs control device |
| 448 | 448 | 235 = /dev/autofs Autofs control device |
| 449 | 449 | 236 = /dev/mapper/control Device-Mapper control device |
| 450 | + 237 = /dev/loop-control Loopback control device | |
| 451 | + 238 = /dev/vhost-net Host kernel accelerator for virtio net | |
| 452 | + | |
| 450 | 453 | 240-254 Reserved for local use |
| 451 | 454 | 255 Reserved for MISC_DYNAMIC_MINOR |
| 452 | 455 | |
| @@ -0,0 +1,14 @@ | ||
| 1 | +* Atmel Direct Memory Access Controller (DMA) | |
| 2 | + | |
| 3 | +Required properties: | |
| 4 | +- compatible: Should be "atmel,<chip>-dma" | |
| 5 | +- reg: Should contain DMA registers location and length | |
| 6 | +- interrupts: Should contain DMA interrupt | |
| 7 | + | |
| 8 | +Examples: | |
| 9 | + | |
| 10 | +dma@ffffec00 { | |
| 11 | + compatible = "atmel,at91sam9g45-dma"; | |
| 12 | + reg = <0xffffec00 0x200>; | |
| 13 | + interrupts = <21>; | |
| 14 | +}; | |
| @@ -0,0 +1,30 @@ | ||
| 1 | +I2C for OMAP platforms | |
| 2 | + | |
| 3 | +Required properties : | |
| 4 | +- compatible : Must be "ti,omap3-i2c" or "ti,omap4-i2c" | |
| 5 | +- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based) | |
| 6 | +- #address-cells = <1>; | |
| 7 | +- #size-cells = <0>; | |
| 8 | + | |
| 9 | +Recommended properties : | |
| 10 | +- clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise | |
| 11 | + the default 100 kHz frequency will be used. | |
| 12 | + | |
| 13 | +Optional properties: | |
| 14 | +- Child nodes conforming to i2c bus binding | |
| 15 | + | |
| 16 | +Note: Current implementation will fetch base address, irq and dma | |
| 17 | +from omap hwmod data base during device registration. | |
| 18 | +Future plan is to migrate hwmod data base contents into device tree | |
| 19 | +blob so that, all the required data will be used from device tree dts | |
| 20 | +file. | |
| 21 | + | |
| 22 | +Examples : | |
| 23 | + | |
| 24 | +i2c1: i2c@0 { | |
| 25 | + compatible = "ti,omap3-i2c"; | |
| 26 | + #address-cells = <1>; | |
| 27 | + #size-cells = <0>; | |
| 28 | + ti,hwmods = "i2c1"; | |
| 29 | + clock-frequency = <400000>; | |
| 30 | +}; | |
| @@ -75,6 +75,10 @@ The slave DMA usage consists of following steps: · 74 unmodified lines | ||
| 75 | 75 | slave_sg - DMA a list of scatter gather buffers from/to a peripheral |
| 76 | 76 | dma_cyclic - Perform a cyclic DMA operation from/to a peripheral till the |
| 77 | 77 | operation is explicitly stopped. |
| 78 | + interleaved_dma - This is common to Slave as well as M2M clients. For slave | |
| 79 | + address of devices' fifo could be already known to the driver. | |
| 80 | + Various types of operations could be expressed by setting | |
| 81 | + appropriate values to the 'dma_interleaved_template' members. | |
| 78 | 82 | |
| 79 | 83 | A non-NULL return of this transfer API represents a "descriptor" for |
| 80 | 84 | the given transaction. |
| @@ -89,6 +93,10 @@ The slave DMA usage consists of following steps: · 8 unmodified lines | ||
| 89 | 93 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
| 90 | 94 | size_t period_len, enum dma_data_direction direction); |
| 91 | 95 | |
| 96 | + struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( | |
| 97 | + struct dma_chan *chan, struct dma_interleaved_template *xt, | |
| 98 | + unsigned long flags); | |
| 99 | + | |
| 92 | 100 | The peripheral driver is expected to have mapped the scatterlist for |
| 93 | 101 | the DMA operation prior to calling device_prep_slave_sg, and must |
| 94 | 102 | keep the scatterlist mapped until the DMA operation has completed. |
| @@ -233,6 +233,10 @@ certainly invest a bit more effort into libata core layer). · 232 unmodified lines | ||
| 233 | 233 | 6. List of managed interfaces |
| 234 | 234 | ----------------------------- |
| 235 | 235 | |
| 236 | +MEM | |
| 237 | + devm_kzalloc() | |
| 238 | + devm_kfree() | |
| 239 | + | |
| 236 | 240 | IO region |
| 237 | 241 | devm_request_region() |
| 238 | 242 | devm_request_mem_region() |
| @@ -439,17 +439,6 @@ Who: Jean Delvare <khali@linux-fr.org> · 438 unmodified lines | ||
| 439 | 439 | |
| 440 | 440 | ---------------------------- |
| 441 | 441 | |
| 442 | −What: For VIDIOC_S_FREQUENCY the type field must match the device node's type. | |
| 443 | − If not, return -EINVAL. | |
| 444 | −When: 3.2 | |
| 445 | −Why: It makes no sense to switch the tuner to radio mode by calling | |
| 446 | − VIDIOC_S_FREQUENCY on a video node, or to switch the tuner to tv mode by | |
| 447 | − calling VIDIOC_S_FREQUENCY on a radio node. This is the first step of a | |
| 448 | − move to more consistent handling of tv and radio tuners. | |
| 449 | −Who: Hans Verkuil <hans.verkuil@cisco.com> | |
| 450 | − | |
| 451 | −---------------------------- | |
| 452 | − | |
| 453 | 442 | What: Opening a radio device node will no longer automatically switch the |
| 454 | 443 | tuner mode from tv to radio. |
| 455 | 444 | When: 3.3 |
| @@ -521,3 +510,17 @@ Why: The pci_scan_bus_parented() interface creates a new root bus. The · 65 unmodified lines | ||
| 521 | 510 | convert to using pci_scan_root_bus() so they can supply a list of |
| 522 | 511 | bus resources when the bus is created. |
| 523 | 512 | Who: Bjorn Helgaas <bhelgaas@google.com> |
| 513 | + | |
| 514 | +---------------------------- | |
| 515 | + | |
| 516 | +What: The CAP9 SoC family will be removed | |
| 517 | +When: 3.4 | |
| 518 | +Files: arch/arm/mach-at91/at91cap9.c | |
| 519 | + arch/arm/mach-at91/at91cap9_devices.c | |
| 520 | + arch/arm/mach-at91/include/mach/at91cap9.h | |
| 521 | + arch/arm/mach-at91/include/mach/at91cap9_matrix.h | |
| 522 | + arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | |
| 523 | + arch/arm/mach-at91/board-cap9adk.c | |
| 524 | +Why: The code is not actively maintained and platforms are now hard to find. | |
| 525 | +Who: Nicolas Ferre <nicolas.ferre@atmel.com> | |
| 526 | + Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
| @@ -17,11 +17,11 @@ reports supported by a device are also provided by sysfs in · 16 unmodified lines | ||
| 17 | 17 | class/input/event*/device/capabilities/, and the properties of a device are |
| 18 | 18 | provided in class/input/event*/device/properties. |
| 19 | 19 | |
| 20 | −Types: | |
| 21 | −========== | |
| 22 | −Types are groupings of codes under a logical input construct. Each type has a | |
| 23 | −set of applicable codes to be used in generating events. See the Codes section | |
| 24 | −for details on valid codes for each type. | |
| 20 | +Event types: | |
| 21 | +=========== | |
| 22 | +Event types are groupings of codes under a logical input construct. Each | |
| 23 | +type has a set of applicable codes to be used in generating events. See the | |
| 24 | +Codes section for details on valid codes for each type. | |
| 25 | 25 | |
| 26 | 26 | * EV_SYN: |
| 27 | 27 | - Used as markers to separate events. Events may be separated in time or in |
| @@ -63,9 +63,9 @@ for details on valid codes for each type. · 35 unmodified lines | ||
| 63 | 63 | * EV_FF_STATUS: |
| 64 | 64 | - Used to receive force feedback device status. |
| 65 | 65 | |
| 66 | −Codes: | |
| 67 | −========== | |
| 68 | −Codes define the precise type of event. | |
| 66 | +Event codes: | |
| 67 | +=========== | |
| 68 | +Event codes define the precise type of event. | |
| 69 | 69 | |
| 70 | 70 | EV_SYN: |
| 71 | 71 | ---------- |
| @@ -220,6 +220,56 @@ EV_PWR: · 148 unmodified lines | ||
| 220 | 220 | EV_PWR events are a special type of event used specifically for power |
| 221 | 221 | mangement. Its usage is not well defined. To be addressed later. |
| 222 | 222 | |
| 223 | +Device properties: | |
| 224 | +================= | |
| 225 | +Normally, userspace sets up an input device based on the data it emits, | |
| 226 | +i.e., the event types. In the case of two devices emitting the same event | |
| 227 | +types, additional information can be provided in the form of device | |
| 228 | +properties. | |
| 229 | + | |
| 230 | +INPUT_PROP_DIRECT + INPUT_PROP_POINTER: | |
| 231 | +-------------------------------------- | |
| 232 | +The INPUT_PROP_DIRECT property indicates that device coordinates should be | |
| 233 | +directly mapped to screen coordinates (not taking into account trivial | |
| 234 | +transformations, such as scaling, flipping and rotating). Non-direct input | |
| 235 | +devices require non-trivial transformation, such as absolute to relative | |
| 236 | +transformation for touchpads. Typical direct input devices: touchscreens, | |
| 237 | +drawing tablets; non-direct devices: touchpads, mice. | |
| 238 | + | |
| 239 | +The INPUT_PROP_POINTER property indicates that the device is not transposed | |
| 240 | +on the screen and thus requires use of an on-screen pointer to trace user's | |
| 241 | +movements. Typical pointer devices: touchpads, tablets, mice; non-pointer | |
| 242 | +device: touchscreen. | |
| 243 | + | |
| 244 | +If neither INPUT_PROP_DIRECT or INPUT_PROP_POINTER are set, the property is | |
| 245 | +considered undefined and the device type should be deduced in the | |
| 246 | +traditional way, using emitted event types. | |
| 247 | + | |
| 248 | +INPUT_PROP_BUTTONPAD: | |
| 249 | +-------------------- | |
| 250 | +For touchpads where the button is placed beneath the surface, such that | |
| 251 | +pressing down on the pad causes a button click, this property should be | |
| 252 | +set. Common in clickpad notebooks and macbooks from 2009 and onwards. | |
| 253 | + | |
| 254 | +Originally, the buttonpad property was coded into the bcm5974 driver | |
| 255 | +version field under the name integrated button. For backwards | |
| 256 | +compatibility, both methods need to be checked in userspace. | |
| 257 | + | |
| 258 | +INPUT_PROP_SEMI_MT: | |
| 259 | +------------------ | |
| 260 | +Some touchpads, most common between 2008 and 2011, can detect the presence | |
| 261 | +of multiple contacts without resolving the individual positions; only the | |
| 262 | +number of contacts and a rectangular shape is known. For such | |
| 263 | +touchpads, the semi-mt property should be set. | |
| 264 | + | |
| 265 | +Depending on the device, the rectangle may enclose all touches, like a | |
| 266 | +bounding box, or just some of them, for instance the two most recent | |
| 267 | +touches. The diversity makes the rectangle of limited use, but some | |
| 268 | +gestures can normally be extracted from it. | |
| 269 | + | |
| 270 | +If INPUT_PROP_SEMI_MT is not set, the device is assumed to be a true MT | |
| 271 | +device. | |
| 272 | + | |
| 223 | 273 | Guidelines: |
| 224 | 274 | ========== |
| 225 | 275 | The guidelines below ensure proper single-touch and multi-finger functionality. |
| @@ -240,6 +290,8 @@ used to report when a touch is active on the screen. · 14 unmodified lines | ||
| 240 | 290 | BTN_{MOUSE,LEFT,MIDDLE,RIGHT} must not be reported as the result of touch |
| 241 | 291 | contact. BTN_TOOL_<name> events should be reported where possible. |
| 242 | 292 | |
| 293 | +For new hardware, INPUT_PROP_DIRECT should be set. | |
| 294 | + | |
| 243 | 295 | Trackpads: |
| 244 | 296 | ---------- |
| 245 | 297 | Legacy trackpads that only provide relative position information must report |
| @@ -250,6 +302,8 @@ location of the touch. BTN_TOUCH should be used to report when a touch is active · 4 unmodified lines | ||
| 250 | 302 | on the trackpad. Where multi-finger support is available, BTN_TOOL_<name> should |
| 251 | 303 | be used to report the number of touches active on the trackpad. |
| 252 | 304 | |
| 305 | +For new hardware, INPUT_PROP_POINTER should be set. | |
| 306 | + | |
| 253 | 307 | Tablets: |
| 254 | 308 | ---------- |
| 255 | 309 | BTN_TOOL_<name> events must be reported when a stylus or other tool is active on |
| @@ -260,3 +314,5 @@ button may be used for buttons on the tablet except BTN_{MOUSE,LEFT}. · 4 unmodified lines | ||
| 260 | 314 | BTN_{0,1,2,etc} are good generic codes for unlabeled buttons. Do not use |
| 261 | 315 | meaningful buttons, like BTN_FORWARD, unless the button is labeled for that |
| 262 | 316 | purpose on the device. |
| 317 | + | |
| 318 | +For new hardware, both INPUT_PROP_DIRECT and INPUT_PROP_POINTER should be set. | |
| @@ -149,6 +149,7 @@ Code Seq#(hex) Include File Comments · 148 unmodified lines | ||
| 149 | 149 | 'M' 01-03 drivers/scsi/megaraid/megaraid_sas.h |
| 150 | 150 | 'M' 00-0F drivers/video/fsl-diu-fb.h conflict! |
| 151 | 151 | 'N' 00-1F drivers/usb/scanner.h |
| 152 | +'N' 40-7F drivers/block/nvme.c | |
| 152 | 153 | 'O' 00-06 mtd/ubi-user.h UBI |
| 153 | 154 | 'P' all linux/soundcard.h conflict! |
| 154 | 155 | 'P' 60-6F sound/sscape_ioctl.h conflict! |
| @@ -1059,6 +1059,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted. · 1058 unmodified lines | ||
| 1059 | 1059 | By default, super page will be supported if Intel IOMMU |
| 1060 | 1060 | has the capability. With this option, super page will |
| 1061 | 1061 | not be supported. |
| 1062 | + | |
| 1063 | + intel_idle.max_cstate= [KNL,HW,ACPI,X86] | |
| 1064 | + 0 disables intel_idle and fall back on acpi_idle. | |
| 1065 | + 1 to 6 specify maximum depth of C-state. | |
| 1066 | + | |
| 1062 | 1067 | intremap= [X86-64, Intel-IOMMU] |
| 1063 | 1068 | on enable Interrupt Remapping (default) |
| 1064 | 1069 | off disable Interrupt Remapping |
| @@ -857,42 +857,41 @@ case), we define a mapping like this: · 856 unmodified lines | ||
| 857 | 857 | |
| 858 | 858 | ... |
| 859 | 859 | { |
| 860 | − .name "2bit" | |
| 860 | + .name = "2bit" | |
| 861 | 861 | .ctrl_dev_name = "pinctrl-foo", |
| 862 | 862 | .function = "mmc0", |
| 863 | 863 | .group = "mmc0_1_grp", |
| 864 | 864 | .dev_name = "foo-mmc.0", |
| 865 | 865 | }, |
| 866 | 866 | { |
| 867 | − .name "4bit" | |
| 867 | + .name = "4bit" | |
| 868 | 868 | .ctrl_dev_name = "pinctrl-foo", |
| 869 | 869 | .function = "mmc0", |
| 870 | 870 | .group = "mmc0_1_grp", |
| 871 | 871 | .dev_name = "foo-mmc.0", |
| 872 | 872 | }, |
| 873 | 873 | { |
| 874 | − .name "4bit" | |
| 874 | + .name = "4bit" | |
| 875 | 875 | .ctrl_dev_name = "pinctrl-foo", |
| 876 | 876 | .function = "mmc0", |
| 877 | 877 | .group = "mmc0_2_grp", |
| 878 | 878 | .dev_name = "foo-mmc.0", |
| 879 | 879 | }, |
| 880 | 880 | { |
| 881 | − .name "8bit" | |
| 881 | + .name = "8bit" | |
| 882 | 882 | .ctrl_dev_name = "pinctrl-foo", |
| 883 | − .function = "mmc0", | |
| 884 | 883 | .group = "mmc0_1_grp", |
| 885 | 884 | .dev_name = "foo-mmc.0", |
| 886 | 885 | }, |
| 887 | 886 | { |
| 888 | − .name "8bit" | |
| 887 | + .name = "8bit" | |
| 889 | 888 | .ctrl_dev_name = "pinctrl-foo", |
| 890 | 889 | .function = "mmc0", |
| 891 | 890 | .group = "mmc0_2_grp", |
| 892 | 891 | .dev_name = "foo-mmc.0", |
| 893 | 892 | }, |
| 894 | 893 | { |
| 895 | − .name "8bit" | |
| 894 | + .name = "8bit" | |
| 896 | 895 | .ctrl_dev_name = "pinctrl-foo", |
| 897 | 896 | .function = "mmc0", |
| 898 | 897 | .group = "mmc0_3_grp", |
| @@ -995,7 +994,7 @@ This is enabled by simply setting the .hog_on_boot field in the map to true, · 96 unmodified lines | ||
| 995 | 994 | like this: |
| 996 | 995 | |
| 997 | 996 | { |
| 998 | − .name "POWERMAP" | |
| 997 | + .name = "POWERMAP" | |
| 999 | 998 | .ctrl_dev_name = "pinctrl-foo", |
| 1000 | 999 | .function = "power_func", |
| 1001 | 1000 | .hog_on_boot = true, |
| @@ -1025,7 +1024,7 @@ it, disables and releases it, and muxes it in on the pins defined by group B: · 23 unmodified lines | ||
| 1025 | 1024 | |
| 1026 | 1025 | foo_switch() |
| 1027 | 1026 | { |
| 1028 | − struct pinmux pmx; | |
| 1027 | + struct pinmux *pmx; | |
| 1029 | 1028 | |
| 1030 | 1029 | /* Enable on position A */ |
| 1031 | 1030 | pmx = pinmux_get(&device, "spi0-pos-A"); |
| @@ -15,7 +15,7 @@ test at least a couple of times in a row for confidence. [This is necessary, · 14 unmodified lines | ||
| 15 | 15 | because some problems only show up on a second attempt at suspending and |
| 16 | 16 | resuming the system.] Moreover, hibernating in the "reboot" and "shutdown" |
| 17 | 17 | modes causes the PM core to skip some platform-related callbacks which on ACPI |
| 18 | −systems might be necessary to make hibernation work. Thus, if you machine fails | |
| 18 | +systems might be necessary to make hibernation work. Thus, if your machine fails | |
| 19 | 19 | to hibernate or resume in the "reboot" mode, you should try the "platform" mode: |
| 20 | 20 | |
| 21 | 21 | # echo platform > /sys/power/disk |
| @@ -120,10 +120,10 @@ So in practice, the 'at all' may become a 'why freeze kernel threads?' and · 119 unmodified lines | ||
| 120 | 120 | freezing user threads I don't find really objectionable." |
| 121 | 121 | |
| 122 | 122 | Still, there are kernel threads that may want to be freezable. For example, if |
| 123 | −a kernel that belongs to a device driver accesses the device directly, it in | |
| 124 | −principle needs to know when the device is suspended, so that it doesn't try to | |
| 125 | −access it at that time. However, if the kernel thread is freezable, it will be | |
| 126 | −frozen before the driver's .suspend() callback is executed and it will be | |
| 123 | +a kernel thread that belongs to a device driver accesses the device directly, it | |
| 124 | +in principle needs to know when the device is suspended, so that it doesn't try | |
| 125 | +to access it at that time. However, if the kernel thread is freezable, it will | |
| 126 | +be frozen before the driver's .suspend() callback is executed and it will be | |
| 127 | 127 | thawed after the driver's .resume() callback has run, so it won't be accessing |
| 128 | 128 | the device while it's suspended. |
| 129 | 129 | |
| @@ -1,3 +1,13 @@ | ||
| 1 | +Release Date : Fri. Jan 6, 2012 17:00:00 PST 2010 - | |
| 2 | + (emaild-id:megaraidlinux@lsi.com) | |
| 3 | + Adam Radford | |
| 4 | +Current Version : 00.00.06.14-rc1 | |
| 5 | +Old Version : 00.00.06.12-rc1 | |
| 6 | + 1. Fix reglockFlags for degraded raid5/6 for MR 9360/9380. | |
| 7 | + 2. Mask off flags in ioctl path to prevent memory scribble with older | |
| 8 | + MegaCLI versions. | |
| 9 | + 3. Remove poll_mode_io module paramater, sysfs node, and associated code. | |
| 10 | +------------------------------------------------------------------------------- | |
| 1 | 11 | Release Date : Wed. Oct 5, 2011 17:00:00 PST 2010 - |
| 2 | 12 | (emaild-id:megaraidlinux@lsi.com) |
| 3 | 13 | Adam Radford |
| @@ -1,32 +1,11 @@ | ||
| 1 | 1 | Copyright (c) 2003-2011 QLogic Corporation |
| 2 | −QLogic Linux iSCSI HBA Driver | |
| 2 | +QLogic Linux iSCSI Driver | |
| 3 | 3 | |
| 4 | 4 | This program includes a device driver for Linux 3.x. |
| 5 | 5 | You may modify and redistribute the device driver code under the |
| 6 | 6 | GNU General Public License (a copy of which is attached hereto as |
| 7 | 7 | Exhibit A) published by the Free Software Foundation (version 2). |
| 8 | 8 | |
| 9 | −REGARDLESS OF WHAT LICENSING MECHANISM IS USED OR APPLICABLE, | |
| 10 | −THIS PROGRAM IS PROVIDED BY QLOGIC CORPORATION "AS IS'' AND ANY | |
| 11 | −EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 12 | −IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
| 13 | −PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR | |
| 14 | −BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
| 15 | −EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED | |
| 16 | −TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 17 | −DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
| 18 | −ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
| 19 | −OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
| 20 | −OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
| 21 | −POSSIBILITY OF SUCH DAMAGE. | |
| 22 | − | |
| 23 | −USER ACKNOWLEDGES AND AGREES THAT USE OF THIS PROGRAM WILL NOT | |
| 24 | −CREATE OR GIVE GROUNDS FOR A LICENSE BY IMPLICATION, ESTOPPEL, OR | |
| 25 | −OTHERWISE IN ANY INTELLECTUAL PROPERTY RIGHTS (PATENT, COPYRIGHT, | |
| 26 | −TRADE SECRET, MASK WORK, OR OTHER PROPRIETARY RIGHT) EMBODIED IN | |
| 27 | −ANY OTHER QLOGIC HARDWARE OR SOFTWARE EITHER SOLELY OR IN | |
| 28 | −COMBINATION WITH THIS PROGRAM. | |
| 29 | − | |
| 30 | 9 | |
| 31 | 10 | EXHIBIT A |
| 32 | 11 | |
| @@ -25,7 +25,8 @@ Procedure for submitting patches to the -stable tree: · 24 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | - Send the patch, after verifying that it follows the above rules, to |
| 27 | 27 | stable@vger.kernel.org. You must note the upstream commit ID in the |
| 28 | − changelog of your submission. | |
| 28 | + changelog of your submission, as well as the kernel version you wish | |
| 29 | + it to be applied to. | |
| 29 | 30 | - To have the patch automatically included in the stable tree, add the tag |
| 30 | 31 | Cc: stable@vger.kernel.org |
| 31 | 32 | in the sign-off area. Once the patch is merged it will be applied to |
| @@ -601,6 +601,8 @@ can be ORed together: · 600 unmodified lines | ||
| 601 | 601 | instead of using the one provided by the hardware. |
| 602 | 602 | 512 - A kernel warning has occurred. |
| 603 | 603 | 1024 - A module from drivers/staging was loaded. |
| 604 | +2048 - The system is working around a severe firmware bug. | |
| 605 | +4096 - An out-of-tree module has been loaded. | |
| 604 | 606 | |
| 605 | 607 | ============================================================== |
| 606 | 608 | |
| @@ -230,14 +230,9 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 229 unmodified lines | ||
| 230 | 230 | buf += "#include <linux/ctype.h>\n" |
| 231 | 231 | buf += "#include <asm/unaligned.h>\n\n" |
| 232 | 232 | buf += "#include <target/target_core_base.h>\n" |
| 233 | − buf += "#include <target/target_core_transport.h>\n" | |
| 234 | − buf += "#include <target/target_core_fabric_ops.h>\n" | |
| 233 | + buf += "#include <target/target_core_fabric.h>\n" | |
| 235 | 234 | buf += "#include <target/target_core_fabric_configfs.h>\n" |
| 236 | − buf += "#include <target/target_core_fabric_lib.h>\n" | |
| 237 | − buf += "#include <target/target_core_device.h>\n" | |
| 238 | − buf += "#include <target/target_core_tpg.h>\n" | |
| 239 | 235 | buf += "#include <target/target_core_configfs.h>\n" |
| 240 | − buf += "#include <target/target_core_base.h>\n" | |
| 241 | 236 | buf += "#include <target/configfs_macros.h>\n\n" |
| 242 | 237 | buf += "#include \"" + fabric_mod_name + "_base.h\"\n" |
| 243 | 238 | buf += "#include \"" + fabric_mod_name + "_fabric.h\"\n\n" |
| @@ -260,7 +255,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 16 unmodified lines | ||
| 260 | 255 | buf += " /* " + fabric_mod_name + "_parse_wwn(name, &wwpn, 1) < 0)\n" |
| 261 | 256 | buf += " return ERR_PTR(-EINVAL); */\n" |
| 262 | 257 | buf += " se_nacl_new = " + fabric_mod_name + "_alloc_fabric_acl(se_tpg);\n" |
| 263 | − buf += " if (!(se_nacl_new))\n" | |
| 258 | + buf += " if (!se_nacl_new)\n" | |
| 264 | 259 | buf += " return ERR_PTR(-ENOMEM);\n" |
| 265 | 260 | buf += "//#warning FIXME: Hardcoded nexus depth in " + fabric_mod_name + "_make_nodeacl()\n" |
| 266 | 261 | buf += " nexus_depth = 1;\n" |
| @@ -308,7 +303,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 41 unmodified lines | ||
| 308 | 303 | buf += " if (strict_strtoul(name + 5, 10, &tpgt) || tpgt > UINT_MAX)\n" |
| 309 | 304 | buf += " return ERR_PTR(-EINVAL);\n\n" |
| 310 | 305 | buf += " tpg = kzalloc(sizeof(struct " + fabric_mod_name + "_tpg), GFP_KERNEL);\n" |
| 311 | − buf += " if (!(tpg)) {\n" | |
| 306 | + buf += " if (!tpg) {\n" | |
| 312 | 307 | buf += " printk(KERN_ERR \"Unable to allocate struct " + fabric_mod_name + "_tpg\");\n" |
| 313 | 308 | buf += " return ERR_PTR(-ENOMEM);\n" |
| 314 | 309 | buf += " }\n" |
| @@ -344,7 +339,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 29 unmodified lines | ||
| 344 | 339 | buf += " /* if (" + fabric_mod_name + "_parse_wwn(name, &wwpn, 1) < 0)\n" |
| 345 | 340 | buf += " return ERR_PTR(-EINVAL); */\n\n" |
| 346 | 341 | buf += " " + fabric_mod_port + " = kzalloc(sizeof(struct " + fabric_mod_name + "_" + fabric_mod_port + "), GFP_KERNEL);\n" |
| 347 | − buf += " if (!(" + fabric_mod_port + ")) {\n" | |
| 342 | + buf += " if (!" + fabric_mod_port + ") {\n" | |
| 348 | 343 | buf += " printk(KERN_ERR \"Unable to allocate struct " + fabric_mod_name + "_" + fabric_mod_port + "\");\n" |
| 349 | 344 | buf += " return ERR_PTR(-ENOMEM);\n" |
| 350 | 345 | buf += " }\n" |
| @@ -352,7 +347,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 1 unmodified line | ||
| 352 | 347 | if proto_ident == "FC" or proto_ident == "SAS": |
| 353 | 348 | buf += " " + fabric_mod_port + "->" + fabric_mod_port + "_wwpn = wwpn;\n" |
| 354 | 349 | |
| 355 | − buf += " /* " + fabric_mod_name + "_format_wwn(&" + fabric_mod_port + "->" + fabric_mod_port + "_name[0], " + fabric_mod_name.upper() + "__NAMELEN, wwpn); */\n\n" | |
| 350 | + buf += " /* " + fabric_mod_name + "_format_wwn(&" + fabric_mod_port + "->" + fabric_mod_port + "_name[0], " + fabric_mod_name.upper() + "_NAMELEN, wwpn); */\n\n" | |
| 356 | 351 | buf += " return &" + fabric_mod_port + "->" + fabric_mod_port + "_wwn;\n" |
| 357 | 352 | buf += "}\n\n" |
| 358 | 353 | buf += "static void " + fabric_mod_name + "_drop_" + fabric_mod_port + "(struct se_wwn *wwn)\n" |
| @@ -391,8 +386,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 32 unmodified lines | ||
| 391 | 386 | buf += " .tpg_alloc_fabric_acl = " + fabric_mod_name + "_alloc_fabric_acl,\n" |
| 392 | 387 | buf += " .tpg_release_fabric_acl = " + fabric_mod_name + "_release_fabric_acl,\n" |
| 393 | 388 | buf += " .tpg_get_inst_index = " + fabric_mod_name + "_tpg_get_inst_index,\n" |
| 394 | − buf += " .release_cmd_to_pool = " + fabric_mod_name + "_release_cmd,\n" | |
| 395 | − buf += " .release_cmd_direct = " + fabric_mod_name + "_release_cmd,\n" | |
| 389 | + buf += " .release_cmd = " + fabric_mod_name + "_release_cmd,\n" | |
| 396 | 390 | buf += " .shutdown_session = " + fabric_mod_name + "_shutdown_session,\n" |
| 397 | 391 | buf += " .close_session = " + fabric_mod_name + "_close_session,\n" |
| 398 | 392 | buf += " .stop_session = " + fabric_mod_name + "_stop_session,\n" |
| @@ -405,14 +399,12 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 6 unmodified lines | ||
| 405 | 399 | buf += " .set_default_node_attributes = " + fabric_mod_name + "_set_default_node_attrs,\n" |
| 406 | 400 | buf += " .get_task_tag = " + fabric_mod_name + "_get_task_tag,\n" |
| 407 | 401 | buf += " .get_cmd_state = " + fabric_mod_name + "_get_cmd_state,\n" |
| 408 | − buf += " .new_cmd_failure = " + fabric_mod_name + "_new_cmd_failure,\n" | |
| 409 | 402 | buf += " .queue_data_in = " + fabric_mod_name + "_queue_data_in,\n" |
| 410 | 403 | buf += " .queue_status = " + fabric_mod_name + "_queue_status,\n" |
| 411 | 404 | buf += " .queue_tm_rsp = " + fabric_mod_name + "_queue_tm_rsp,\n" |
| 412 | 405 | buf += " .get_fabric_sense_len = " + fabric_mod_name + "_get_fabric_sense_len,\n" |
| 413 | 406 | buf += " .set_fabric_sense_len = " + fabric_mod_name + "_set_fabric_sense_len,\n" |
| 414 | 407 | buf += " .is_state_remove = " + fabric_mod_name + "_is_state_remove,\n" |
| 415 | − buf += " .pack_lun = " + fabric_mod_name + "_pack_lun,\n" | |
| 416 | 408 | buf += " /*\n" |
| 417 | 409 | buf += " * Setup function pointers for generic logic in target_core_fabric_configfs.c\n" |
| 418 | 410 | buf += " */\n" |
| @@ -439,9 +431,9 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 20 unmodified lines | ||
| 439 | 431 | buf += " * Register the top level struct config_item_type with TCM core\n" |
| 440 | 432 | buf += " */\n" |
| 441 | 433 | buf += " fabric = target_fabric_configfs_init(THIS_MODULE, \"" + fabric_mod_name[4:] + "\");\n" |
| 442 | − buf += " if (!(fabric)) {\n" | |
| 434 | + buf += " if (IS_ERR(fabric)) {\n" | |
| 443 | 435 | buf += " printk(KERN_ERR \"target_fabric_configfs_init() failed\\n\");\n" |
| 444 | − buf += " return -ENOMEM;\n" | |
| 436 | + buf += " return PTR_ERR(fabric);\n" | |
| 445 | 437 | buf += " }\n" |
| 446 | 438 | buf += " /*\n" |
| 447 | 439 | buf += " * Setup fabric->tf_ops from our local " + fabric_mod_name + "_ops\n" |
| @@ -475,9 +467,9 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 27 unmodified lines | ||
| 475 | 467 | buf += " printk(KERN_INFO \"" + fabric_mod_name.upper() + "[0] - Set fabric -> " + fabric_mod_name + "_fabric_configfs\\n\");\n" |
| 476 | 468 | buf += " return 0;\n" |
| 477 | 469 | buf += "};\n\n" |
| 478 | − buf += "static void " + fabric_mod_name + "_deregister_configfs(void)\n" | |
| 470 | + buf += "static void __exit " + fabric_mod_name + "_deregister_configfs(void)\n" | |
| 479 | 471 | buf += "{\n" |
| 480 | − buf += " if (!(" + fabric_mod_name + "_fabric_configfs))\n" | |
| 472 | + buf += " if (!" + fabric_mod_name + "_fabric_configfs)\n" | |
| 481 | 473 | buf += " return;\n\n" |
| 482 | 474 | buf += " target_fabric_configfs_deregister(" + fabric_mod_name + "_fabric_configfs);\n" |
| 483 | 475 | buf += " " + fabric_mod_name + "_fabric_configfs = NULL;\n" |
| @@ -492,17 +484,15 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 8 unmodified lines | ||
| 492 | 484 | buf += " return ret;\n\n" |
| 493 | 485 | buf += " return 0;\n" |
| 494 | 486 | buf += "};\n\n" |
| 495 | − buf += "static void " + fabric_mod_name + "_exit(void)\n" | |
| 487 | + buf += "static void __exit " + fabric_mod_name + "_exit(void)\n" | |
| 496 | 488 | buf += "{\n" |
| 497 | 489 | buf += " " + fabric_mod_name + "_deregister_configfs();\n" |
| 498 | 490 | buf += "};\n\n" |
| 499 | 491 | |
| 500 | − buf += "#ifdef MODULE\n" | |
| 501 | 492 | buf += "MODULE_DESCRIPTION(\"" + fabric_mod_name.upper() + " series fabric driver\");\n" |
| 502 | 493 | buf += "MODULE_LICENSE(\"GPL\");\n" |
| 503 | 494 | buf += "module_init(" + fabric_mod_name + "_init);\n" |
| 504 | 495 | buf += "module_exit(" + fabric_mod_name + "_exit);\n" |
| 505 | − buf += "#endif\n" | |
| 506 | 496 | |
| 507 | 497 | ret = p.write(buf) |
| 508 | 498 | if ret: |
| @@ -514,7 +504,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 5 unmodified lines | ||
| 514 | 504 | |
| 515 | 505 | def tcm_mod_scan_fabric_ops(tcm_dir): |
| 516 | 506 | |
| 517 | − fabric_ops_api = tcm_dir + "include/target/target_core_fabric_ops.h" | |
| 507 | + fabric_ops_api = tcm_dir + "include/target/target_core_fabric.h" | |
| 518 | 508 | |
| 519 | 509 | print "Using tcm_mod_scan_fabric_ops: " + fabric_ops_api |
| 520 | 510 | process_fo = 0; |
| @@ -579,11 +569,7 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 58 unmodified lines | ||
| 579 | 569 | buf += "#include <scsi/scsi_cmnd.h>\n" |
| 580 | 570 | buf += "#include <scsi/libfc.h>\n\n" |
| 581 | 571 | buf += "#include <target/target_core_base.h>\n" |
| 582 | − buf += "#include <target/target_core_transport.h>\n" | |
| 583 | − buf += "#include <target/target_core_fabric_ops.h>\n" | |
| 584 | − buf += "#include <target/target_core_fabric_lib.h>\n" | |
| 585 | − buf += "#include <target/target_core_device.h>\n" | |
| 586 | − buf += "#include <target/target_core_tpg.h>\n" | |
| 572 | + buf += "#include <target/target_core_fabric.h>\n" | |
| 587 | 573 | buf += "#include <target/target_core_configfs.h>\n\n" |
| 588 | 574 | buf += "#include \"" + fabric_mod_name + "_base.h\"\n" |
| 589 | 575 | buf += "#include \"" + fabric_mod_name + "_fabric.h\"\n\n" |
| @@ -788,7 +774,7 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 198 unmodified lines | ||
| 788 | 774 | buf += "{\n" |
| 789 | 775 | buf += " struct " + fabric_mod_name + "_nacl *nacl;\n\n" |
| 790 | 776 | buf += " nacl = kzalloc(sizeof(struct " + fabric_mod_name + "_nacl), GFP_KERNEL);\n" |
| 791 | − buf += " if (!(nacl)) {\n" | |
| 777 | + buf += " if (!nacl) {\n" | |
| 792 | 778 | buf += " printk(KERN_ERR \"Unable to alocate struct " + fabric_mod_name + "_nacl\\n\");\n" |
| 793 | 779 | buf += " return NULL;\n" |
| 794 | 780 | buf += " }\n\n" |
| @@ -815,7 +801,7 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 20 unmodified lines | ||
| 815 | 801 | buf += "}\n\n" |
| 816 | 802 | bufi += "u32 " + fabric_mod_name + "_tpg_get_inst_index(struct se_portal_group *);\n" |
| 817 | 803 | |
| 818 | − if re.search('release_cmd_to_pool', fo): | |
| 804 | + if re.search('\*release_cmd\)\(', fo): | |
| 819 | 805 | buf += "void " + fabric_mod_name + "_release_cmd(struct se_cmd *se_cmd)\n" |
| 820 | 806 | buf += "{\n" |
| 821 | 807 | buf += " return;\n" |
| @@ -899,13 +885,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 77 unmodified lines | ||
| 899 | 885 | buf += "}\n\n" |
| 900 | 886 | bufi += "int " + fabric_mod_name + "_get_cmd_state(struct se_cmd *);\n" |
| 901 | 887 | |
| 902 | − if re.search('new_cmd_failure\)\(', fo): | |
| 903 | − buf += "void " + fabric_mod_name + "_new_cmd_failure(struct se_cmd *se_cmd)\n" | |
| 904 | − buf += "{\n" | |
| 905 | − buf += " return;\n" | |
| 906 | − buf += "}\n\n" | |
| 907 | − bufi += "void " + fabric_mod_name + "_new_cmd_failure(struct se_cmd *);\n" | |
| 908 | − | |
| 909 | 888 | if re.search('queue_data_in\)\(', fo): |
| 910 | 889 | buf += "int " + fabric_mod_name + "_queue_data_in(struct se_cmd *se_cmd)\n" |
| 911 | 890 | buf += "{\n" |
| @@ -948,15 +927,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 36 unmodified lines | ||
| 948 | 927 | buf += "}\n\n" |
| 949 | 928 | bufi += "int " + fabric_mod_name + "_is_state_remove(struct se_cmd *);\n" |
| 950 | 929 | |
| 951 | − if re.search('pack_lun\)\(', fo): | |
| 952 | − buf += "u64 " + fabric_mod_name + "_pack_lun(unsigned int lun)\n" | |
| 953 | − buf += "{\n" | |
| 954 | − buf += " WARN_ON(lun >= 256);\n" | |
| 955 | − buf += " /* Caller wants this byte-swapped */\n" | |
| 956 | − buf += " return cpu_to_le64((lun & 0xff) << 8);\n" | |
| 957 | − buf += "}\n\n" | |
| 958 | − bufi += "u64 " + fabric_mod_name + "_pack_lun(unsigned int);\n" | |
| 959 | − | |
| 960 | 930 | |
| 961 | 931 | ret = p.write(buf) |
| 962 | 932 | if ret: |
| @@ -284,7 +284,7 @@ method, the sys I/F structure will be built like this: · 283 unmodified lines | ||
| 284 | 284 | The framework includes a simple notification mechanism, in the form of a |
| 285 | 285 | netlink event. Netlink socket initialization is done during the _init_ |
| 286 | 286 | of the framework. Drivers which intend to use the notification mechanism |
| 287 | −just need to call generate_netlink_event() with two arguments viz | |
| 287 | +just need to call thermal_generate_netlink_event() with two arguments viz | |
| 288 | 288 | (originator, event). Typically the originator will be an integer assigned |
| 289 | 289 | to a thermal_zone_device when it registers itself with the framework. The |
| 290 | 290 | event will be one of:{THERMAL_AUX0, THERMAL_AUX1, THERMAL_CRITICAL, |
| @@ -666,27 +666,6 @@ a control of this type whenever the first control belonging to a new control · 665 unmodified lines | ||
| 666 | 666 | class is added. |
| 667 | 667 | |
| 668 | 668 | |
| 669 | −Differences from the Spec | |
| 670 | −========================= | |
| 671 | − | |
| 672 | −There are a few places where the framework acts slightly differently from the | |
| 673 | −V4L2 Specification. Those differences are described in this section. We will | |
| 674 | −have to see whether we need to adjust the spec or not. | |
| 675 | − | |
| 676 | −1) It is no longer required to have all controls contained in a | |
| 677 | −v4l2_ext_control array be from the same control class. The framework will be | |
| 678 | −able to handle any type of control in the array. You need to set ctrl_class | |
| 679 | −to 0 in order to enable this. If ctrl_class is non-zero, then it will still | |
| 680 | −check that all controls belong to that control class. | |
| 681 | − | |
| 682 | −If you set ctrl_class to 0 and count to 0, then it will only return an error | |
| 683 | −if there are no controls at all. | |
| 684 | − | |
| 685 | −2) Clarified the way error_idx works. For get and set it will be equal to | |
| 686 | −count if nothing was done yet. If it is less than count then only the controls | |
| 687 | −up to error_idx-1 were successfully applied. | |
| 688 | − | |
| 689 | − | |
| 690 | 669 | Proposals for Extensions |
| 691 | 670 | ======================== |
| 692 | 671 | |
| @@ -4,8 +4,6 @@ Virtualization support in the Linux kernel. · 3 unmodified lines | ||
| 4 | 4 | - this file. |
| 5 | 5 | kvm/ |
| 6 | 6 | - Kernel Virtual Machine. See also http://linux-kvm.org |
| 7 | −lguest/ | |
| 8 | − - Extremely simple hypervisor for experimental/educational use. | |
| 9 | 7 | uml/ |
| 10 | 8 | - User Mode Linux, builds/runs Linux kernel as a userspace program. |
| 11 | 9 | virtio.txt |
| @@ -159,7 +159,7 @@ S: Maintained · 158 unmodified lines | ||
| 159 | 159 | F: drivers/net/ethernet/realtek/r8169.c |
| 160 | 160 | |
| 161 | 161 | 8250/16?50 (AND CLONE UARTS) SERIAL DRIVER |
| 162 | −M: Greg Kroah-Hartman <gregkh@suse.de> | |
| 162 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 163 | 163 | L: linux-serial@vger.kernel.org |
| 164 | 164 | W: http://serial.sourceforge.net |
| 165 | 165 | S: Maintained |
| @@ -745,6 +745,7 @@ M: Barry Song <baohua.song@csr.com> · 579 unmodified lines | ||
| 745 | 745 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 746 | 746 | S: Maintained |
| 747 | 747 | F: arch/arm/mach-prima2/ |
| 748 | +F: drivers/dma/sirf-dma* | |
| 748 | 749 | |
| 749 | 750 | ARM/EBSA110 MACHINE SUPPORT |
| 750 | 751 | M: Russell King <linux@arm.linux.org.uk> |
| @@ -788,12 +789,6 @@ F: arch/arm/mach-mx*/ · 37 unmodified lines | ||
| 788 | 789 | F: arch/arm/mach-imx/ |
| 789 | 790 | F: arch/arm/plat-mxc/ |
| 790 | 791 | |
| 791 | −ARM/FREESCALE IMX51 | |
| 792 | −M: Amit Kucheria <amit.kucheria@canonical.com> | |
| 793 | −L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |
| 794 | −S: Maintained | |
| 795 | −F: arch/arm/mach-mx5/ | |
| 796 | − | |
| 797 | 792 | ARM/FREESCALE IMX6 |
| 798 | 793 | M: Shawn Guo <shawn.guo@linaro.org> |
| 799 | 794 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| @@ -1411,6 +1406,7 @@ F: net/ax25/ · 611 unmodified lines | ||
| 1411 | 1406 | B43 WIRELESS DRIVER |
| 1412 | 1407 | M: Stefano Brivio <stefano.brivio@polimi.it> |
| 1413 | 1408 | L: linux-wireless@vger.kernel.org |
| 1409 | +L: b43-dev@lists.infradead.org (moderated for non-subscribers) | |
| 1414 | 1410 | W: http://linuxwireless.org/en/users/Drivers/b43 |
| 1415 | 1411 | S: Maintained |
| 1416 | 1412 | F: drivers/net/wireless/b43/ |
| @@ -1587,6 +1583,13 @@ L: linux-scsi@vger.kernel.org · 170 unmodified lines | ||
| 1587 | 1583 | S: Supported |
| 1588 | 1584 | F: drivers/scsi/bnx2fc/ |
| 1589 | 1585 | |
| 1586 | +BROADCOM SPECIFIC AMBA DRIVER (BCMA) | |
| 1587 | +M: Rafał Miłecki <zajec5@gmail.com> | |
| 1588 | +L: linux-wireless@vger.kernel.org | |
| 1589 | +S: Maintained | |
| 1590 | +F: drivers/bcma/ | |
| 1591 | +F: include/linux/bcma/ | |
| 1592 | + | |
| 1590 | 1593 | BROCADE BFA FC SCSI DRIVER |
| 1591 | 1594 | M: Jing Huang <huangj@brocade.com> |
| 1592 | 1595 | L: linux-scsi@vger.kernel.org |
| @@ -1774,9 +1777,9 @@ X: net/wireless/wext* · 181 unmodified lines | ||
| 1774 | 1777 | |
| 1775 | 1778 | CHAR and MISC DRIVERS |
| 1776 | 1779 | M: Arnd Bergmann <arnd@arndb.de> |
| 1777 | −M: Greg Kroah-Hartman <greg@kroah.com> | |
| 1780 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 1778 | 1781 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git |
| 1779 | −S: Maintained | |
| 1782 | +S: Supported | |
| 1780 | 1783 | F: drivers/char/* |
| 1781 | 1784 | F: drivers/misc/* |
| 1782 | 1785 | |
| @@ -2237,6 +2240,17 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/teigland/dlm.git · 454 unmodified lines | ||
| 2237 | 2240 | S: Supported |
| 2238 | 2241 | F: fs/dlm/ |
| 2239 | 2242 | |
| 2243 | +DMA BUFFER SHARING FRAMEWORK | |
| 2244 | +M: Sumit Semwal <sumit.semwal@linaro.org> | |
| 2245 | +S: Maintained | |
| 2246 | +L: linux-media@vger.kernel.org | |
| 2247 | +L: dri-devel@lists.freedesktop.org | |
| 2248 | +L: linaro-mm-sig@lists.linaro.org | |
| 2249 | +F: drivers/base/dma-buf* | |
| 2250 | +F: include/linux/dma-buf* | |
| 2251 | +F: Documentation/dma-buf-sharing.txt | |
| 2252 | +T: git git://git.linaro.org/people/sumitsemwal/linux-dma-buf.git | |
| 2253 | + | |
| 2240 | 2254 | DMA GENERIC OFFLOAD ENGINE SUBSYSTEM |
| 2241 | 2255 | M: Vinod Koul <vinod.koul@intel.com> |
| 2242 | 2256 | M: Dan Williams <dan.j.williams@intel.com> |
| @@ -2267,7 +2281,7 @@ F: drivers/acpi/dock.c · 24 unmodified lines | ||
| 2267 | 2281 | DOCUMENTATION |
| 2268 | 2282 | M: Randy Dunlap <rdunlap@xenotime.net> |
| 2269 | 2283 | L: linux-doc@vger.kernel.org |
| 2270 | −T: quilt http://userweb.kernel.org/~rdunlap/kernel-doc-patches/current/ | |
| 2284 | +T: quilt http://xenotime.net/kernel-doc-patches/current/ | |
| 2271 | 2285 | S: Maintained |
| 2272 | 2286 | F: Documentation/ |
| 2273 | 2287 | |
| @@ -2300,7 +2314,7 @@ F: lib/lru_cache.c · 26 unmodified lines | ||
| 2300 | 2314 | F: Documentation/blockdev/drbd/ |
| 2301 | 2315 | |
| 2302 | 2316 | DRIVER CORE, KOBJECTS, DEBUGFS AND SYSFS |
| 2303 | −M: Greg Kroah-Hartman <gregkh@suse.de> | |
| 2317 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 2304 | 2318 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core-2.6.git |
| 2305 | 2319 | S: Supported |
| 2306 | 2320 | F: Documentation/kobject.txt |
| @@ -2330,6 +2344,9 @@ F: include/drm/i915* · 23 unmodified lines | ||
| 2330 | 2344 | |
| 2331 | 2345 | DRM DRIVERS FOR EXYNOS |
| 2332 | 2346 | M: Inki Dae <inki.dae@samsung.com> |
| 2347 | +M: Joonyoung Shim <jy0922.shim@samsung.com> | |
| 2348 | +M: Seung-Woo Kim <sw0312.kim@samsung.com> | |
| 2349 | +M: Kyungmin Park <kyungmin.park@samsung.com> | |
| 2333 | 2350 | L: dri-devel@lists.freedesktop.org |
| 2334 | 2351 | S: Supported |
| 2335 | 2352 | F: drivers/gpu/drm/exynos |
| @@ -2382,7 +2399,7 @@ F: net/bridge/netfilter/ebt*.c · 46 unmodified lines | ||
| 2382 | 2399 | |
| 2383 | 2400 | ECRYPT FILE SYSTEM |
| 2384 | 2401 | M: Tyler Hicks <tyhicks@canonical.com> |
| 2385 | −M: Dustin Kirkland <kirkland@canonical.com> | |
| 2402 | +M: Dustin Kirkland <dustin.kirkland@gazzang.com> | |
| 2386 | 2403 | L: ecryptfs@vger.kernel.org |
| 2387 | 2404 | W: https://launchpad.net/ecryptfs |
| 2388 | 2405 | S: Supported |
| @@ -3301,6 +3318,12 @@ S: Maintained · 912 unmodified lines | ||
| 3301 | 3318 | F: net/ieee802154/ |
| 3302 | 3319 | F: drivers/ieee802154/ |
| 3303 | 3320 | |
| 3321 | +IIO SUBSYSTEM AND DRIVERS | |
| 3322 | +M: Jonathan Cameron <jic23@cam.ac.uk> | |
| 3323 | +L: linux-iio@vger.kernel.org | |
| 3324 | +S: Maintained | |
| 3325 | +F: drivers/staging/iio/ | |
| 3326 | + | |
| 3304 | 3327 | IKANOS/ADI EAGLE ADSL USB DRIVER |
| 3305 | 3328 | M: Matthieu Castet <castet.matthieu@free.fr> |
| 3306 | 3329 | M: Stanislaw Gruszka <stf_xl@wp.pl> |
| @@ -3969,11 +3992,11 @@ M: Rusty Russell <rusty@rustcorp.com.au> · 662 unmodified lines | ||
| 3969 | 3992 | L: lguest@lists.ozlabs.org |
| 3970 | 3993 | W: http://lguest.ozlabs.org/ |
| 3971 | 3994 | S: Odd Fixes |
| 3972 | −F: Documentation/virtual/lguest/ | |
| 3995 | +F: arch/x86/include/asm/lguest*.h | |
| 3973 | 3996 | F: arch/x86/lguest/ |
| 3974 | 3997 | F: drivers/lguest/ |
| 3975 | 3998 | F: include/linux/lguest*.h |
| 3976 | −F: arch/x86/include/asm/lguest*.h | |
| 3999 | +F: tools/lguest/ | |
| 3977 | 4000 | |
| 3978 | 4001 | LINUX FOR IBM pSERIES (RS/6000) |
| 3979 | 4002 | M: Paul Mackerras <paulus@au.ibm.com> |
| @@ -4113,10 +4136,11 @@ L: linux-ntfs-dev@lists.sourceforge.net · 133 unmodified lines | ||
| 4113 | 4136 | W: http://www.linux-ntfs.org/content/view/19/37/ |
| 4114 | 4137 | S: Maintained |
| 4115 | 4138 | F: Documentation/ldm.txt |
| 4116 | −F: fs/partitions/ldm.* | |
| 4139 | +F: block/partitions/ldm.* | |
| 4117 | 4140 | |
| 4118 | 4141 | LogFS |
| 4119 | 4142 | M: Joern Engel <joern@logfs.org> |
| 4143 | +M: Prasad Joshi <prasadjoshi.linux@gmail.com> | |
| 4120 | 4144 | L: logfs@logfs.org |
| 4121 | 4145 | W: logfs.org |
| 4122 | 4146 | S: Maintained |
| @@ -4258,13 +4282,6 @@ S: Orphan · 135 unmodified lines | ||
| 4258 | 4282 | F: drivers/video/matrox/matroxfb_* |
| 4259 | 4283 | F: include/linux/matroxfb.h |
| 4260 | 4284 | |
| 4261 | −MAX1668 TEMPERATURE SENSOR DRIVER | |
| 4262 | −M: "David George" <david.george@ska.ac.za> | |
| 4263 | −L: lm-sensors@lm-sensors.org | |
| 4264 | −S: Maintained | |
| 4265 | −F: Documentation/hwmon/max1668 | |
| 4266 | −F: drivers/hwmon/max1668.c | |
| 4267 | − | |
| 4268 | 4285 | MAX6650 HARDWARE MONITOR AND FAN CONTROLLER DRIVER |
| 4269 | 4286 | M: "Hans J. Koch" <hjk@hansjkoch.de> |
| 4270 | 4287 | L: lm-sensors@lm-sensors.org |
| @@ -5616,7 +5633,7 @@ W: http://www.ibm.com/developerworks/linux/linux390/ · 1345 unmodified lines | ||
| 5616 | 5633 | S: Supported |
| 5617 | 5634 | F: arch/s390/ |
| 5618 | 5635 | F: drivers/s390/ |
| 5619 | −F: fs/partitions/ibm.c | |
| 5636 | +F: block/partitions/ibm.c | |
| 5620 | 5637 | F: Documentation/s390/ |
| 5621 | 5638 | F: Documentation/DocBook/s390* |
| 5622 | 5639 | |
| @@ -5844,9 +5861,9 @@ S: Maintained · 221 unmodified lines | ||
| 5844 | 5861 | F: drivers/mmc/host/sdhci-spear.c |
| 5845 | 5862 | |
| 5846 | 5863 | SECURITY SUBSYSTEM |
| 5847 | −M: James Morris <jmorris@namei.org> | |
| 5864 | +M: James Morris <james.l.morris@oracle.com> | |
| 5848 | 5865 | L: linux-security-module@vger.kernel.org (suggested Cc:) |
| 5849 | −T: git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/security-testing-2.6.git | |
| 5866 | +T: git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git | |
| 5850 | 5867 | W: http://security.wiki.kernel.org/ |
| 5851 | 5868 | S: Supported |
| 5852 | 5869 | F: security/ |
| @@ -5857,7 +5874,7 @@ S: Supported · 4 unmodified lines | ||
| 5857 | 5874 | |
| 5858 | 5875 | SELINUX SECURITY MODULE |
| 5859 | 5876 | M: Stephen Smalley <sds@tycho.nsa.gov> |
| 5860 | −M: James Morris <jmorris@namei.org> | |
| 5877 | +M: James Morris <james.l.morris@oracle.com> | |
| 5861 | 5878 | M: Eric Paris <eparis@parisplace.org> |
| 5862 | 5879 | L: selinux@tycho.nsa.gov (subscribers-only, general discussion) |
| 5863 | 5880 | W: http://selinuxproject.org |
| @@ -6116,13 +6133,6 @@ S: Maintained · 252 unmodified lines | ||
| 6116 | 6133 | F: drivers/ssb/ |
| 6117 | 6134 | F: include/linux/ssb/ |
| 6118 | 6135 | |
| 6119 | −BROADCOM SPECIFIC AMBA DRIVER (BCMA) | |
| 6120 | −M: Rafał Miłecki <zajec5@gmail.com> | |
| 6121 | −L: linux-wireless@vger.kernel.org | |
| 6122 | −S: Maintained | |
| 6123 | −F: drivers/bcma/ | |
| 6124 | −F: include/linux/bcma/ | |
| 6125 | − | |
| 6126 | 6136 | SONY VAIO CONTROL DEVICE DRIVER |
| 6127 | 6137 | M: Mattia Dongili <malattia@linux.it> |
| 6128 | 6138 | L: platform-driver-x86@vger.kernel.org |
| @@ -6266,15 +6276,15 @@ S: Maintained · 137 unmodified lines | ||
| 6266 | 6276 | F: arch/alpha/kernel/srm_env.c |
| 6267 | 6277 | |
| 6268 | 6278 | STABLE BRANCH |
| 6269 | −M: Greg Kroah-Hartman <greg@kroah.com> | |
| 6279 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 6270 | 6280 | L: stable@vger.kernel.org |
| 6271 | −S: Maintained | |
| 6281 | +S: Supported | |
| 6272 | 6282 | |
| 6273 | 6283 | STAGING SUBSYSTEM |
| 6274 | −M: Greg Kroah-Hartman <gregkh@suse.de> | |
| 6284 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 6275 | 6285 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git |
| 6276 | 6286 | L: devel@driverdev.osuosl.org |
| 6277 | −S: Maintained | |
| 6287 | +S: Supported | |
| 6278 | 6288 | F: drivers/staging/ |
| 6279 | 6289 | |
| 6280 | 6290 | STAGING - AGERE HERMES II and II.5 WIRELESS DRIVERS |
| @@ -6386,11 +6396,6 @@ M: Omar Ramirez Luna <omar.ramirez@ti.com> · 105 unmodified lines | ||
| 6386 | 6396 | S: Odd Fixes |
| 6387 | 6397 | F: drivers/staging/tidspbridge/ |
| 6388 | 6398 | |
| 6389 | −STAGING - TRIDENT TVMASTER TMxxxx USB VIDEO CAPTURE DRIVERS | |
| 6390 | −L: linux-media@vger.kernel.org | |
| 6391 | −S: Odd Fixes | |
| 6392 | −F: drivers/staging/tm6000/ | |
| 6393 | − | |
| 6394 | 6399 | STAGING - USB ENE SM/MS CARD READER DRIVER |
| 6395 | 6400 | M: Al Cho <acho@novell.com> |
| 6396 | 6401 | S: Odd Fixes |
| @@ -6659,10 +6664,10 @@ S: Maintained · 262 unmodified lines | ||
| 6659 | 6664 | K: ^Subject:.*(?i)trivial |
| 6660 | 6665 | |
| 6661 | 6666 | TTY LAYER |
| 6662 | −M: Greg Kroah-Hartman <gregkh@suse.de> | |
| 6663 | −S: Maintained | |
| 6667 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 6668 | +S: Supported | |
| 6664 | 6669 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6.git |
| 6665 | −F: drivers/tty/* | |
| 6670 | +F: drivers/tty/ | |
| 6666 | 6671 | F: drivers/tty/serial/serial_core.c |
| 6667 | 6672 | F: include/linux/serial_core.h |
| 6668 | 6673 | F: include/linux/serial.h |
| @@ -6948,7 +6953,7 @@ S: Maintained · 279 unmodified lines | ||
| 6948 | 6953 | F: drivers/usb/serial/digi_acceleport.c |
| 6949 | 6954 | |
| 6950 | 6955 | USB SERIAL DRIVER |
| 6951 | −M: Greg Kroah-Hartman <gregkh@suse.de> | |
| 6956 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 6952 | 6957 | L: linux-usb@vger.kernel.org |
| 6953 | 6958 | S: Supported |
| 6954 | 6959 | F: Documentation/usb/usb-serial.txt |
| @@ -6963,9 +6968,8 @@ S: Maintained · 8 unmodified lines | ||
| 6963 | 6968 | F: drivers/usb/serial/empeg.c |
| 6964 | 6969 | |
| 6965 | 6970 | USB SERIAL KEYSPAN DRIVER |
| 6966 | −M: Greg Kroah-Hartman <greg@kroah.com> | |
| 6971 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 6967 | 6972 | L: linux-usb@vger.kernel.org |
| 6968 | −W: http://www.kroah.com/linux/ | |
| 6969 | 6973 | S: Maintained |
| 6970 | 6974 | F: drivers/usb/serial/*keyspan* |
| 6971 | 6975 | |
| @@ -6993,7 +6997,7 @@ F: Documentation/video4linux/sn9c102.txt · 21 unmodified lines | ||
| 6993 | 6997 | F: drivers/media/video/sn9c102/ |
| 6994 | 6998 | |
| 6995 | 6999 | USB SUBSYSTEM |
| 6996 | −M: Greg Kroah-Hartman <gregkh@suse.de> | |
| 7000 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 6997 | 7001 | L: linux-usb@vger.kernel.org |
| 6998 | 7002 | W: http://www.linux-usb.org |
| 6999 | 7003 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6.git |
| @@ -7080,7 +7084,7 @@ F: fs/hppfs/ · 80 unmodified lines | ||
| 7080 | 7084 | |
| 7081 | 7085 | USERSPACE I/O (UIO) |
| 7082 | 7086 | M: "Hans J. Koch" <hjk@hansjkoch.de> |
| 7083 | −M: Greg Kroah-Hartman <gregkh@suse.de> | |
| 7087 | +M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 7084 | 7088 | S: Maintained |
| 7085 | 7089 | F: Documentation/DocBook/uio-howto.tmpl |
| 7086 | 7090 | F: drivers/uio/ |
| @@ -7198,7 +7202,7 @@ S: Maintained · 111 unmodified lines | ||
| 7198 | 7202 | F: drivers/net/vmxnet3/ |
| 7199 | 7203 | |
| 7200 | 7204 | VMware PVSCSI driver |
| 7201 | −M: Alok Kataria <akataria@vmware.com> | |
| 7205 | +M: Arvind Kumar <arvindkumar@vmware.com> | |
| 7202 | 7206 | M: VMware PV-Drivers <pv-drivers@vmware.com> |
| 7203 | 7207 | L: linux-scsi@vger.kernel.org |
| 7204 | 7208 | S: Maintained |
| @@ -7355,6 +7359,7 @@ S: Supported · 150 unmodified lines | ||
| 7355 | 7359 | F: Documentation/hwmon/wm83?? |
| 7356 | 7360 | F: arch/arm/mach-s3c64xx/mach-crag6410* |
| 7357 | 7361 | F: drivers/leds/leds-wm83*.c |
| 7362 | +F: drivers/hwmon/wm83??-hwmon.c | |
| 7358 | 7363 | F: drivers/input/misc/wm831x-on.c |
| 7359 | 7364 | F: drivers/input/touchscreen/wm831x-ts.c |
| 7360 | 7365 | F: drivers/input/touchscreen/wm97*.c |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | VERSION = 3 |
| 2 | −PATCHLEVEL = 2 | |
| 2 | +PATCHLEVEL = 3 | |
| 3 | 3 | SUBLEVEL = 0 |
| 4 | −EXTRAVERSION = | |
| 4 | +EXTRAVERSION = -rc4 | |
| 5 | 5 | NAME = Saber-toothed Squirrel |
| 6 | 6 | |
| 7 | 7 | # *DOCUMENTATION* |
| @@ -754,7 +754,7 @@ config ARCH_SA1100 · 753 unmodified lines | ||
| 754 | 754 | select ARCH_HAS_CPUFREQ |
| 755 | 755 | select CPU_FREQ |
| 756 | 756 | select GENERIC_CLOCKEVENTS |
| 757 | − select CLKDEV_LOOKUP | |
| 757 | + select HAVE_CLK | |
| 758 | 758 | select HAVE_SCHED_CLOCK |
| 759 | 759 | select TICK_ONESHOT |
| 760 | 760 | select ARCH_REQUIRE_GPIOLIB |
| @@ -825,7 +825,6 @@ config ARCH_S5PC100 · 64 unmodified lines | ||
| 825 | 825 | select HAVE_CLK |
| 826 | 826 | select CLKDEV_LOOKUP |
| 827 | 827 | select CPU_V7 |
| 828 | − select ARM_L1_CACHE_SHIFT_6 | |
| 829 | 828 | select ARCH_USES_GETTIMEOFFSET |
| 830 | 829 | select HAVE_S3C2410_I2C if I2C |
| 831 | 830 | select HAVE_S3C_RTC if RTC_CLASS |
| @@ -842,7 +841,6 @@ config ARCH_S5PV210 · 10 unmodified lines | ||
| 842 | 841 | select HAVE_CLK |
| 843 | 842 | select CLKDEV_LOOKUP |
| 844 | 843 | select CLKSRC_MMIO |
| 845 | − select ARM_L1_CACHE_SHIFT_6 | |
| 846 | 844 | select ARCH_HAS_CPUFREQ |
| 847 | 845 | select GENERIC_CLOCKEVENTS |
| 848 | 846 | select HAVE_SCHED_CLOCK |
| @@ -160,7 +160,6 @@ machine-$(CONFIG_ARCH_MSM) := msm · 159 unmodified lines | ||
| 160 | 160 | machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 |
| 161 | 161 | machine-$(CONFIG_ARCH_IMX_V4_V5) := imx |
| 162 | 162 | machine-$(CONFIG_ARCH_IMX_V6_V7) := imx |
| 163 | −machine-$(CONFIG_ARCH_MX5) := mx5 | |
| 164 | 163 | machine-$(CONFIG_ARCH_MXS) := mxs |
| 165 | 164 | machine-$(CONFIG_ARCH_NETX) := netx |
| 166 | 165 | machine-$(CONFIG_ARCH_NOMADIK) := nomadik |
| @@ -29,6 +29,7 @@ · 28 unmodified lines | ||
| 29 | 29 | compatible = "arm,cortex-a9-gic"; |
| 30 | 30 | #interrupt-cells = <3>; |
| 31 | 31 | interrupt-controller; |
| 32 | + cpu-offset = <0x8000>; | |
| 32 | 33 | reg = <0x10490000 0x1000>, <0x10480000 0x100>; |
| 33 | 34 | }; |
| 34 | 35 | |
| @@ -46,11 +46,11 @@ · 45 unmodified lines | ||
| 46 | 46 | }; |
| 47 | 47 | |
| 48 | 48 | serial@70006200 { |
| 49 | − status = "disable"; | |
| 49 | + clock-frequency = <216000000>; | |
| 50 | 50 | }; |
| 51 | 51 | |
| 52 | 52 | serial@70006300 { |
| 53 | − clock-frequency = <216000000>; | |
| 53 | + status = "disable"; | |
| 54 | 54 | }; |
| 55 | 55 | |
| 56 | 56 | serial@70006400 { |
| @@ -60,7 +60,7 @@ · 3 unmodified lines | ||
| 60 | 60 | sdhci@c8000000 { |
| 61 | 61 | cd-gpios = <&gpio 173 0>; /* gpio PV5 */ |
| 62 | 62 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
| 63 | − power-gpios = <&gpio 155 0>; /* gpio PT3 */ | |
| 63 | + power-gpios = <&gpio 169 0>; /* gpio PV1 */ | |
| 64 | 64 | }; |
| 65 | 65 | |
| 66 | 66 | sdhci@c8000200 { |
| @@ -41,6 +41,7 @@ · 40 unmodified lines | ||
| 41 | 41 | |
| 42 | 42 | #include <asm/irq.h> |
| 43 | 43 | #include <asm/exception.h> |
| 44 | +#include <asm/smp_plat.h> | |
| 44 | 45 | #include <asm/mach/irq.h> |
| 45 | 46 | #include <asm/hardware/gic.h> |
| 46 | 47 | |
| @@ -352,11 +353,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic) · 305 unmodified lines | ||
| 352 | 353 | unsigned int gic_irqs = gic->gic_irqs; |
| 353 | 354 | struct irq_domain *domain = &gic->domain; |
| 354 | 355 | void __iomem *base = gic_data_dist_base(gic); |
| 355 | − u32 cpu = 0; | |
| 356 | − | |
| 357 | −#ifdef CONFIG_SMP | |
| 358 | − cpu = cpu_logical_map(smp_processor_id()); | |
| 359 | −#endif | |
| 356 | + u32 cpu = cpu_logical_map(smp_processor_id()); | |
| 360 | 357 | |
| 361 | 358 | cpumask = 1 << cpu; |
| 362 | 359 | cpumask |= cpumask << 8; |
| @@ -320,13 +320,6 @@ err0: · 319 unmodified lines | ||
| 320 | 320 | return -EBUSY; |
| 321 | 321 | } |
| 322 | 322 | |
| 323 | −/* | |
| 324 | − * If we set up a device for bus mastering, we need to check the latency | |
| 325 | − * timer as we don't have even crappy BIOSes to set it properly. | |
| 326 | − * The implementation is from arch/i386/pci/i386.c | |
| 327 | − */ | |
| 328 | −unsigned int pcibios_max_latency = 255; | |
| 329 | − | |
| 330 | 323 | /* ITE bridge requires setting latency timer to avoid early bus access |
| 331 | 324 | termination by PCI bus master devices |
| 332 | 325 | */ |
| @@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) · 1501 unmodified lines | ||
| 1502 | 1502 | struct pl330_thread *thrd = ch_id; |
| 1503 | 1503 | struct pl330_dmac *pl330; |
| 1504 | 1504 | unsigned long flags; |
| 1505 | − int ret = 0, active = thrd->req_running; | |
| 1505 | + int ret = 0, active; | |
| 1506 | 1506 | |
| 1507 | 1507 | if (!thrd || thrd->free || thrd->dmac->state == DYING) |
| 1508 | 1508 | return -EINVAL; |
| 1509 | 1509 | |
| 1510 | 1510 | pl330 = thrd->dmac; |
| 1511 | + active = thrd->req_running; | |
| 1511 | 1512 | |
| 1512 | 1513 | spin_lock_irqsave(&pl330->lock, flags); |
| 1513 | 1514 | |
| @@ -3,6 +3,7 @@ CONFIG_EXPERIMENTAL=y · 2 unmodified lines | ||
| 3 | 3 | CONFIG_KERNEL_LZO=y |
| 4 | 4 | CONFIG_SYSVIPC=y |
| 5 | 5 | CONFIG_LOG_BUF_SHIFT=18 |
| 6 | +CONFIG_CGROUPS=y | |
| 6 | 7 | CONFIG_RELAY=y |
| 7 | 8 | CONFIG_EXPERT=y |
| 8 | 9 | # CONFIG_SLUB_DEBUG is not set |
| @@ -14,20 +15,31 @@ CONFIG_MODULE_SRCVERSION_ALL=y · 5 unmodified lines | ||
| 14 | 15 | # CONFIG_LBDAF is not set |
| 15 | 16 | # CONFIG_BLK_DEV_BSG is not set |
| 16 | 17 | CONFIG_ARCH_MXC=y |
| 17 | −CONFIG_ARCH_MX5=y | |
| 18 | −CONFIG_MACH_MX51_BABBAGE=y | |
| 18 | +CONFIG_MACH_MX31LILLY=y | |
| 19 | +CONFIG_MACH_MX31LITE=y | |
| 20 | +CONFIG_MACH_PCM037=y | |
| 21 | +CONFIG_MACH_PCM037_EET=y | |
| 22 | +CONFIG_MACH_MX31_3DS=y | |
| 23 | +CONFIG_MACH_MX31MOBOARD=y | |
| 24 | +CONFIG_MACH_QONG=y | |
| 25 | +CONFIG_MACH_ARMADILLO5X0=y | |
| 26 | +CONFIG_MACH_KZM_ARM11_01=y | |
| 27 | +CONFIG_MACH_PCM043=y | |
| 28 | +CONFIG_MACH_MX35_3DS=y | |
| 29 | +CONFIG_MACH_EUKREA_CPUIMX35=y | |
| 30 | +CONFIG_MACH_VPR200=y | |
| 31 | +CONFIG_MACH_IMX51_DT=y | |
| 19 | 32 | CONFIG_MACH_MX51_3DS=y |
| 20 | 33 | CONFIG_MACH_EUKREA_CPUIMX51=y |
| 21 | 34 | CONFIG_MACH_EUKREA_CPUIMX51SD=y |
| 22 | 35 | CONFIG_MACH_MX51_EFIKAMX=y |
| 23 | 36 | CONFIG_MACH_MX51_EFIKASB=y |
| 24 | −CONFIG_MACH_MX53_EVK=y | |
| 25 | −CONFIG_MACH_MX53_SMD=y | |
| 26 | −CONFIG_MACH_MX53_LOCO=y | |
| 27 | −CONFIG_MACH_MX53_ARD=y | |
| 37 | +CONFIG_MACH_IMX53_DT=y | |
| 38 | +CONFIG_SOC_IMX6Q=y | |
| 28 | 39 | CONFIG_MXC_PWM=y |
| 29 | 40 | CONFIG_NO_HZ=y |
| 30 | 41 | CONFIG_HIGH_RES_TIMERS=y |
| 42 | +CONFIG_SMP=y | |
| 31 | 43 | CONFIG_VMSPLIT_2G=y |
| 32 | 44 | CONFIG_PREEMPT_VOLUNTARY=y |
| 33 | 45 | CONFIG_AEABI=y |
| @@ -49,7 +61,7 @@ CONFIG_IP_PNP_DHCP=y · 15 unmodified lines | ||
| 49 | 61 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 50 | 62 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 51 | 63 | # CONFIG_INET_LRO is not set |
| 52 | −# CONFIG_IPV6 is not set | |
| 64 | +CONFIG_IPV6=y | |
| 53 | 65 | # CONFIG_WIRELESS is not set |
| 54 | 66 | CONFIG_DEVTMPFS=y |
| 55 | 67 | CONFIG_DEVTMPFS_MOUNT=y |
| @@ -68,24 +80,20 @@ CONFIG_SCSI_SCAN_ASYNC=y · 12 unmodified lines | ||
| 68 | 80 | CONFIG_ATA=y |
| 69 | 81 | CONFIG_PATA_IMX=y |
| 70 | 82 | CONFIG_NETDEVICES=y |
| 71 | −CONFIG_MII=m | |
| 72 | −CONFIG_MARVELL_PHY=y | |
| 73 | −CONFIG_DAVICOM_PHY=y | |
| 74 | −CONFIG_QSEMI_PHY=y | |
| 75 | −CONFIG_LXT_PHY=y | |
| 76 | −CONFIG_CICADA_PHY=y | |
| 77 | −CONFIG_VITESSE_PHY=y | |
| 78 | −CONFIG_SMSC_PHY=y | |
| 79 | −CONFIG_BROADCOM_PHY=y | |
| 80 | −CONFIG_ICPLUS_PHY=y | |
| 81 | −CONFIG_REALTEK_PHY=y | |
| 82 | −CONFIG_NATIONAL_PHY=y | |
| 83 | −CONFIG_STE10XP=y | |
| 84 | −CONFIG_LSI_ET1011C_PHY=y | |
| 85 | −CONFIG_MICREL_PHY=y | |
| 86 | −CONFIG_NET_ETHERNET=y | |
| 87 | −# CONFIG_NETDEV_1000 is not set | |
| 88 | −# CONFIG_NETDEV_10000 is not set | |
| 83 | +# CONFIG_NET_VENDOR_BROADCOM is not set | |
| 84 | +# CONFIG_NET_VENDOR_CHELSIO is not set | |
| 85 | +# CONFIG_NET_VENDOR_FARADAY is not set | |
| 86 | +CONFIG_FEC=y | |
| 87 | +# CONFIG_NET_VENDOR_INTEL is not set | |
| 88 | +# CONFIG_NET_VENDOR_MARVELL is not set | |
| 89 | +# CONFIG_NET_VENDOR_MICREL is not set | |
| 90 | +# CONFIG_NET_VENDOR_MICROCHIP is not set | |
| 91 | +# CONFIG_NET_VENDOR_NATSEMI is not set | |
| 92 | +# CONFIG_NET_VENDOR_SEEQ is not set | |
| 93 | +CONFIG_SMC91X=y | |
| 94 | +CONFIG_SMC911X=y | |
| 95 | +CONFIG_SMSC911X=y | |
| 96 | +# CONFIG_NET_VENDOR_STMICRO is not set | |
| 89 | 97 | # CONFIG_WLAN is not set |
| 90 | 98 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 91 | 99 | CONFIG_INPUT_EVDEV=y |
| @@ -124,7 +132,6 @@ CONFIG_USB_EHCI_HCD=y · 32 unmodified lines | ||
| 124 | 132 | CONFIG_USB_EHCI_MXC=y |
| 125 | 133 | CONFIG_USB_STORAGE=y |
| 126 | 134 | CONFIG_MMC=y |
| 127 | −CONFIG_MMC_BLOCK=m | |
| 128 | 135 | CONFIG_MMC_SDHCI=y |
| 129 | 136 | CONFIG_MMC_SDHCI_PLTFM=y |
| 130 | 137 | CONFIG_MMC_SDHCI_ESDHC_IMX=y |
| @@ -133,6 +140,8 @@ CONFIG_LEDS_CLASS=y · 2 unmodified lines | ||
| 133 | 140 | CONFIG_RTC_CLASS=y |
| 134 | 141 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y |
| 135 | 142 | CONFIG_RTC_MXC=y |
| 143 | +CONFIG_DMADEVICES=y | |
| 144 | +CONFIG_IMX_SDMA=y | |
| 136 | 145 | CONFIG_EXT2_FS=y |
| 137 | 146 | CONFIG_EXT2_FS_XATTR=y |
| 138 | 147 | CONFIG_EXT2_FS_POSIX_ACL=y |
| @@ -1,144 +0,0 @@ | ||
| 1 | −CONFIG_EXPERIMENTAL=y | |
| 2 | −CONFIG_SYSVIPC=y | |
| 3 | −CONFIG_IKCONFIG=y | |
| 4 | −CONFIG_IKCONFIG_PROC=y | |
| 5 | −CONFIG_LOG_BUF_SHIFT=14 | |
| 6 | −CONFIG_EXPERT=y | |
| 7 | −CONFIG_SLAB=y | |
| 8 | −CONFIG_MODULES=y | |
| 9 | −CONFIG_MODULE_UNLOAD=y | |
| 10 | −CONFIG_MODULE_FORCE_UNLOAD=y | |
| 11 | −CONFIG_MODVERSIONS=y | |
| 12 | −# CONFIG_BLK_DEV_BSG is not set | |
| 13 | −CONFIG_ARCH_MXC=y | |
| 14 | −CONFIG_MACH_MX31ADS_WM1133_EV1=y | |
| 15 | −CONFIG_MACH_MX31LILLY=y | |
| 16 | −CONFIG_MACH_MX31LITE=y | |
| 17 | −CONFIG_MACH_PCM037=y | |
| 18 | −CONFIG_MACH_PCM037_EET=y | |
| 19 | −CONFIG_MACH_MX31_3DS=y | |
| 20 | −CONFIG_MACH_MX31MOBOARD=y | |
| 21 | −CONFIG_MACH_QONG=y | |
| 22 | −CONFIG_MACH_ARMADILLO5X0=y | |
| 23 | −CONFIG_MACH_KZM_ARM11_01=y | |
| 24 | −CONFIG_MACH_PCM043=y | |
| 25 | −CONFIG_MACH_MX35_3DS=y | |
| 26 | −CONFIG_MACH_EUKREA_CPUIMX35=y | |
| 27 | −CONFIG_MXC_IRQ_PRIOR=y | |
| 28 | −CONFIG_MXC_PWM=y | |
| 29 | −CONFIG_ARM_ERRATA_411920=y | |
| 30 | −CONFIG_NO_HZ=y | |
| 31 | −CONFIG_HIGH_RES_TIMERS=y | |
| 32 | −CONFIG_PREEMPT=y | |
| 33 | −CONFIG_AEABI=y | |
| 34 | −CONFIG_ZBOOT_ROM_TEXT=0x0 | |
| 35 | −CONFIG_ZBOOT_ROM_BSS=0x0 | |
| 36 | −CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off" | |
| 37 | −CONFIG_VFP=y | |
| 38 | −CONFIG_PM_DEBUG=y | |
| 39 | −CONFIG_NET=y | |
| 40 | −CONFIG_PACKET=y | |
| 41 | −CONFIG_UNIX=y | |
| 42 | −CONFIG_INET=y | |
| 43 | −CONFIG_IP_PNP=y | |
| 44 | −CONFIG_IP_PNP_DHCP=y | |
| 45 | −# CONFIG_INET_XFRM_MODE_TRANSPORT is not set | |
| 46 | −# CONFIG_INET_XFRM_MODE_TUNNEL is not set | |
| 47 | −# CONFIG_INET_XFRM_MODE_BEET is not set | |
| 48 | −# CONFIG_INET_LRO is not set | |
| 49 | −# CONFIG_INET_DIAG is not set | |
| 50 | −# CONFIG_IPV6 is not set | |
| 51 | −CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |
| 52 | −CONFIG_FW_LOADER=m | |
| 53 | −CONFIG_MTD=y | |
| 54 | −CONFIG_MTD_CMDLINE_PARTS=y | |
| 55 | −CONFIG_MTD_CHAR=y | |
| 56 | −CONFIG_MTD_BLOCK=y | |
| 57 | −CONFIG_MTD_CFI=y | |
| 58 | −CONFIG_MTD_PHYSMAP=y | |
| 59 | −CONFIG_MTD_NAND=y | |
| 60 | −CONFIG_MTD_NAND_MXC=y | |
| 61 | −CONFIG_MTD_UBI=y | |
| 62 | −# CONFIG_BLK_DEV is not set | |
| 63 | −CONFIG_MISC_DEVICES=y | |
| 64 | −CONFIG_EEPROM_AT24=y | |
| 65 | −CONFIG_NETDEVICES=y | |
| 66 | −CONFIG_SMSC_PHY=y | |
| 67 | −CONFIG_NET_ETHERNET=y | |
| 68 | −CONFIG_SMSC911X=y | |
| 69 | −CONFIG_DNET=y | |
| 70 | −# CONFIG_NETDEV_1000 is not set | |
| 71 | −# CONFIG_NETDEV_10000 is not set | |
| 72 | −# CONFIG_INPUT_MOUSEDEV is not set | |
| 73 | −# CONFIG_KEYBOARD_ATKBD is not set | |
| 74 | −CONFIG_KEYBOARD_IMX=y | |
| 75 | −# CONFIG_INPUT_MOUSE is not set | |
| 76 | −# CONFIG_SERIO is not set | |
| 77 | −# CONFIG_VT is not set | |
| 78 | −# CONFIG_LEGACY_PTYS is not set | |
| 79 | −CONFIG_SERIAL_8250=m | |
| 80 | −CONFIG_SERIAL_8250_EXTENDED=y | |
| 81 | −CONFIG_SERIAL_8250_SHARE_IRQ=y | |
| 82 | −CONFIG_SERIAL_IMX=y | |
| 83 | −CONFIG_SERIAL_IMX_CONSOLE=y | |
| 84 | −# CONFIG_HW_RANDOM is not set | |
| 85 | −CONFIG_I2C=y | |
| 86 | −CONFIG_I2C_CHARDEV=y | |
| 87 | −CONFIG_I2C_IMX=y | |
| 88 | −CONFIG_SPI=y | |
| 89 | −CONFIG_W1=y | |
| 90 | −CONFIG_W1_MASTER_MXC=y | |
| 91 | −CONFIG_W1_SLAVE_THERM=y | |
| 92 | −# CONFIG_HWMON is not set | |
| 93 | −CONFIG_WATCHDOG=y | |
| 94 | −CONFIG_IMX2_WDT=y | |
| 95 | −CONFIG_MFD_WM8350_I2C=y | |
| 96 | −CONFIG_REGULATOR=y | |
| 97 | −CONFIG_REGULATOR_WM8350=y | |
| 98 | −CONFIG_MEDIA_SUPPORT=y | |
| 99 | −CONFIG_VIDEO_DEV=y | |
| 100 | −# CONFIG_RC_CORE is not set | |
| 101 | −# CONFIG_MEDIA_TUNER_CUSTOMISE is not set | |
| 102 | −CONFIG_SOC_CAMERA=y | |
| 103 | −CONFIG_SOC_CAMERA_MT9M001=y | |
| 104 | −CONFIG_SOC_CAMERA_MT9M111=y | |
| 105 | −CONFIG_SOC_CAMERA_MT9T031=y | |
| 106 | −CONFIG_SOC_CAMERA_MT9V022=y | |
| 107 | −CONFIG_SOC_CAMERA_TW9910=y | |
| 108 | −CONFIG_SOC_CAMERA_OV772X=y | |
| 109 | −CONFIG_VIDEO_MX3=y | |
| 110 | −# CONFIG_RADIO_ADAPTERS is not set | |
| 111 | −CONFIG_FB=y | |
| 112 | −CONFIG_SOUND=y | |
| 113 | −CONFIG_SND=y | |
| 114 | −# CONFIG_SND_ARM is not set | |
| 115 | −# CONFIG_SND_SPI is not set | |
| 116 | −CONFIG_SND_SOC=y | |
| 117 | −CONFIG_SND_IMX_SOC=y | |
| 118 | −CONFIG_SND_MXC_SOC_WM1133_EV1=y | |
| 119 | −CONFIG_SND_SOC_PHYCORE_AC97=y | |
| 120 | −CONFIG_SND_SOC_EUKREA_TLV320=y | |
| 121 | −CONFIG_USB=y | |
| 122 | −CONFIG_USB_EHCI_HCD=y | |
| 123 | −CONFIG_USB_EHCI_MXC=y | |
| 124 | −CONFIG_USB_GADGET=m | |
| 125 | −CONFIG_USB_FSL_USB2=m | |
| 126 | −CONFIG_USB_G_SERIAL=m | |
| 127 | −CONFIG_USB_ULPI=y | |
| 128 | −CONFIG_MMC=y | |
| 129 | −CONFIG_MMC_MXC=y | |
| 130 | −CONFIG_RTC_CLASS=y | |
| 131 | −CONFIG_RTC_MXC=y | |
| 132 | −CONFIG_DMADEVICES=y | |
| 133 | −# CONFIG_DNOTIFY is not set | |
| 134 | −CONFIG_TMPFS=y | |
| 135 | −CONFIG_JFFS2_FS=y | |
| 136 | −CONFIG_UBIFS_FS=y | |
| 137 | −CONFIG_NFS_FS=y | |
| 138 | −CONFIG_NFS_V3=y | |
| 139 | −CONFIG_NFS_V4=y | |
| 140 | −CONFIG_ROOT_NFS=y | |
| 141 | −# CONFIG_ENABLE_WARN_DEPRECATED is not set | |
| 142 | −# CONFIG_ENABLE_MUST_CHECK is not set | |
| 143 | −CONFIG_SYSCTL_SYSCALL_CHECK=y | |
| 144 | −# CONFIG_CRYPTO_ANSI_CPRNG is not set | |
| @@ -137,6 +137,11 @@ · 136 unmodified lines | ||
| 137 | 137 | disable_irq |
| 138 | 138 | .endm |
| 139 | 139 | |
| 140 | + .macro save_and_disable_irqs_notrace, oldcpsr | |
| 141 | + mrs \oldcpsr, cpsr | |
| 142 | + disable_irq_notrace | |
| 143 | + .endm | |
| 144 | + | |
| 140 | 145 | /* |
| 141 | 146 | * Restore interrupt state previously stored in a register. We don't |
| 142 | 147 | * guarantee that this will preserve the flags. |
| @@ -237,7 +242,7 @@ · 94 unmodified lines | ||
| 237 | 242 | */ |
| 238 | 243 | #ifdef CONFIG_THUMB2_KERNEL |
| 239 | 244 | |
| 240 | − .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T() | |
| 245 | + .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() | |
| 241 | 246 | 9999: |
| 242 | 247 | .if \inc == 1 |
| 243 | 248 | \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] |
| @@ -277,7 +282,7 @@ · 33 unmodified lines | ||
| 277 | 282 | |
| 278 | 283 | #else /* !CONFIG_THUMB2_KERNEL */ |
| 279 | 284 | |
| 280 | − .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=T() | |
| 285 | + .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() | |
| 281 | 286 | .rept \rept |
| 282 | 287 | 9999: |
| 283 | 288 | .if \inc == 1 |
| @@ -83,9 +83,9 @@ · 82 unmodified lines | ||
| 83 | 83 | * instructions (inline assembly) |
| 84 | 84 | */ |
| 85 | 85 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 86 | −#define T(instr) #instr "t" | |
| 86 | +#define TUSER(instr) #instr "t" | |
| 87 | 87 | #else |
| 88 | −#define T(instr) #instr | |
| 88 | +#define TUSER(instr) #instr | |
| 89 | 89 | #endif |
| 90 | 90 | |
| 91 | 91 | #else /* __ASSEMBLY__ */ |
| @@ -95,9 +95,9 @@ · 3 unmodified lines | ||
| 95 | 95 | * instructions |
| 96 | 96 | */ |
| 97 | 97 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 98 | −#define T(instr) instr ## t | |
| 98 | +#define TUSER(instr) instr ## t | |
| 99 | 99 | #else |
| 100 | −#define T(instr) instr | |
| 100 | +#define TUSER(instr) instr | |
| 101 | 101 | #endif |
| 102 | 102 | |
| 103 | 103 | #endif /* __ASSEMBLY__ */ |
| @@ -75,9 +75,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, · 74 unmodified lines | ||
| 75 | 75 | |
| 76 | 76 | #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ |
| 77 | 77 | __asm__ __volatile__( \ |
| 78 | − "1: " T(ldr) " %1, [%3]\n" \ | |
| 78 | + "1: " TUSER(ldr) " %1, [%3]\n" \ | |
| 79 | 79 | " " insn "\n" \ |
| 80 | − "2: " T(str) " %0, [%3]\n" \ | |
| 80 | + "2: " TUSER(str) " %0, [%3]\n" \ | |
| 81 | 81 | " mov %0, #0\n" \ |
| 82 | 82 | __futex_atomic_ex_table("%5") \ |
| 83 | 83 | : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ |
| @@ -95,10 +95,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, · 11 unmodified lines | ||
| 95 | 95 | return -EFAULT; |
| 96 | 96 | |
| 97 | 97 | __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" |
| 98 | − "1: " T(ldr) " %1, [%4]\n" | |
| 98 | + "1: " TUSER(ldr) " %1, [%4]\n" | |
| 99 | 99 | " teq %1, %2\n" |
| 100 | 100 | " it eq @ explicit IT needed for the 2b label\n" |
| 101 | − "2: " T(streq) " %3, [%4]\n" | |
| 101 | + "2: " TUSER(streq) " %3, [%4]\n" | |
| 102 | 102 | __futex_atomic_ex_table("%5") |
| 103 | 103 | : "+r" (ret), "=&r" (val) |
| 104 | 104 | : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) |
| @@ -41,7 +41,7 @@ enum pl330_dstcachectrl { · 40 unmodified lines | ||
| 41 | 41 | DCCTRL1, /* Bufferable only */ |
| 42 | 42 | DCCTRL2, /* Cacheable, but do not allocate */ |
| 43 | 43 | DCCTRL3, /* Cacheable and bufferable, but do not allocate */ |
| 44 | − DINVALID1 = 8, | |
| 44 | + DINVALID1, /* AWCACHE = 0x1000 */ | |
| 45 | 45 | DINVALID2, |
| 46 | 46 | DCCTRL6, /* Cacheable write-through, allocate on writes only */ |
| 47 | 47 | DCCTRL7, /* Cacheable write-back, allocate on writes only */ |
| @@ -24,7 +24,6 @@ · 23 unmodified lines | ||
| 24 | 24 | #define MAX_INSN_SIZE 2 |
| 25 | 25 | #define MAX_STACK_SIZE 64 /* 32 would probably be OK */ |
| 26 | 26 | |
| 27 | −#define regs_return_value(regs) ((regs)->ARM_r0) | |
| 28 | 27 | #define flush_insn_slot(p) do { } while (0) |
| 29 | 28 | #define kretprobe_blacklist_size 0 |
| 30 | 29 | |
| @@ -22,6 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | #include <asm/hw_breakpoint.h> |
| 23 | 23 | #include <asm/ptrace.h> |
| 24 | 24 | #include <asm/types.h> |
| 25 | +#include <asm/system.h> | |
| 25 | 26 | |
| 26 | 27 | #ifdef __KERNEL__ |
| 27 | 28 | #define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ |
| @@ -189,6 +189,11 @@ static inline int valid_user_regs(struct pt_regs *regs) · 188 unmodified lines | ||
| 189 | 189 | return 0; |
| 190 | 190 | } |
| 191 | 191 | |
| 192 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 193 | +{ | |
| 194 | + return regs->ARM_r0; | |
| 195 | +} | |
| 196 | + | |
| 192 | 197 | #define instruction_pointer(regs) (regs)->ARM_pc |
| 193 | 198 | |
| 194 | 199 | #ifdef CONFIG_SMP |
| @@ -70,12 +70,6 @@ extern void platform_secondary_init(unsigned int cpu); · 69 unmodified lines | ||
| 70 | 70 | */ |
| 71 | 71 | extern void platform_smp_prepare_cpus(unsigned int); |
| 72 | 72 | |
| 73 | −/* | |
| 74 | − * Logical CPU mapping. | |
| 75 | − */ | |
| 76 | −extern int __cpu_logical_map[NR_CPUS]; | |
| 77 | −#define cpu_logical_map(cpu) __cpu_logical_map[cpu] | |
| 78 | − | |
| 79 | 73 | /* |
| 80 | 74 | * Initial data for bringing up a secondary CPU. |
| 81 | 75 | */ |
| @@ -43,4 +43,10 @@ static inline int cache_ops_need_broadcast(void) · 42 unmodified lines | ||
| 43 | 43 | } |
| 44 | 44 | #endif |
| 45 | 45 | |
| 46 | +/* | |
| 47 | + * Logical CPU mapping. | |
| 48 | + */ | |
| 49 | +extern int __cpu_logical_map[]; | |
| 50 | +#define cpu_logical_map(cpu) __cpu_logical_map[cpu] | |
| 51 | + | |
| 46 | 52 | #endif |
| @@ -129,6 +129,7 @@ extern void vfp_flush_hwstate(struct thread_info *); · 128 unmodified lines | ||
| 129 | 129 | /* |
| 130 | 130 | * thread information flags: |
| 131 | 131 | * TIF_SYSCALL_TRACE - syscall trace active |
| 132 | + * TIF_SYSCAL_AUDIT - syscall auditing active | |
| 132 | 133 | * TIF_SIGPENDING - signal pending |
| 133 | 134 | * TIF_NEED_RESCHED - rescheduling necessary |
| 134 | 135 | * TIF_NOTIFY_RESUME - callback before returning to user |
| @@ -139,6 +140,7 @@ extern void vfp_flush_hwstate(struct thread_info *); · 4 unmodified lines | ||
| 139 | 140 | #define TIF_NEED_RESCHED 1 |
| 140 | 141 | #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ |
| 141 | 142 | #define TIF_SYSCALL_TRACE 8 |
| 143 | +#define TIF_SYSCALL_AUDIT 9 | |
| 142 | 144 | #define TIF_POLLING_NRFLAG 16 |
| 143 | 145 | #define TIF_USING_IWMMXT 17 |
| 144 | 146 | #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ |
| @@ -149,11 +151,15 @@ extern void vfp_flush_hwstate(struct thread_info *); · 4 unmodified lines | ||
| 149 | 151 | #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) |
| 150 | 152 | #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) |
| 151 | 153 | #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) |
| 154 | +#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) | |
| 152 | 155 | #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) |
| 153 | 156 | #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) |
| 154 | 157 | #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) |
| 155 | 158 | #define _TIF_SECCOMP (1 << TIF_SECCOMP) |
| 156 | 159 | |
| 160 | +/* Checks for any syscall work in entry-common.S */ | |
| 161 | +#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT) | |
| 162 | + | |
| 157 | 163 | /* |
| 158 | 164 | * Change these and you break ASM code in entry-common.S |
| 159 | 165 | */ |
| @@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, · 197 unmodified lines | ||
| 198 | 198 | unsigned long addr) |
| 199 | 199 | { |
| 200 | 200 | pgtable_page_dtor(pte); |
| 201 | − tlb_add_flush(tlb, addr); | |
| 201 | + | |
| 202 | + /* | |
| 203 | + * With the classic ARM MMU, a pte page has two corresponding pmd | |
| 204 | + * entries, each covering 1MB. | |
| 205 | + */ | |
| 206 | + addr &= PMD_MASK; | |
| 207 | + tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE); | |
| 208 | + tlb_add_flush(tlb, addr + SZ_1M); | |
| 209 | + | |
| 202 | 210 | tlb_remove_page(tlb, pte); |
| 203 | 211 | } |
| 204 | 212 | |
| @@ -227,7 +227,7 @@ do { \ · 226 unmodified lines | ||
| 227 | 227 | |
| 228 | 228 | #define __get_user_asm_byte(x,addr,err) \ |
| 229 | 229 | __asm__ __volatile__( \ |
| 230 | − "1: " T(ldrb) " %1,[%2],#0\n" \ | |
| 230 | + "1: " TUSER(ldrb) " %1,[%2],#0\n" \ | |
| 231 | 231 | "2:\n" \ |
| 232 | 232 | " .pushsection .fixup,\"ax\"\n" \ |
| 233 | 233 | " .align 2\n" \ |
| @@ -263,7 +263,7 @@ do { \ · 29 unmodified lines | ||
| 263 | 263 | |
| 264 | 264 | #define __get_user_asm_word(x,addr,err) \ |
| 265 | 265 | __asm__ __volatile__( \ |
| 266 | − "1: " T(ldr) " %1,[%2],#0\n" \ | |
| 266 | + "1: " TUSER(ldr) " %1,[%2],#0\n" \ | |
| 267 | 267 | "2:\n" \ |
| 268 | 268 | " .pushsection .fixup,\"ax\"\n" \ |
| 269 | 269 | " .align 2\n" \ |
| @@ -308,7 +308,7 @@ do { \ · 38 unmodified lines | ||
| 308 | 308 | |
| 309 | 309 | #define __put_user_asm_byte(x,__pu_addr,err) \ |
| 310 | 310 | __asm__ __volatile__( \ |
| 311 | − "1: " T(strb) " %1,[%2],#0\n" \ | |
| 311 | + "1: " TUSER(strb) " %1,[%2],#0\n" \ | |
| 312 | 312 | "2:\n" \ |
| 313 | 313 | " .pushsection .fixup,\"ax\"\n" \ |
| 314 | 314 | " .align 2\n" \ |
| @@ -341,7 +341,7 @@ do { \ · 26 unmodified lines | ||
| 341 | 341 | |
| 342 | 342 | #define __put_user_asm_word(x,__pu_addr,err) \ |
| 343 | 343 | __asm__ __volatile__( \ |
| 344 | − "1: " T(str) " %1,[%2],#0\n" \ | |
| 344 | + "1: " TUSER(str) " %1,[%2],#0\n" \ | |
| 345 | 345 | "2:\n" \ |
| 346 | 346 | " .pushsection .fixup,\"ax\"\n" \ |
| 347 | 347 | " .align 2\n" \ |
| @@ -366,10 +366,10 @@ do { \ · 18 unmodified lines | ||
| 366 | 366 | |
| 367 | 367 | #define __put_user_asm_dword(x,__pu_addr,err) \ |
| 368 | 368 | __asm__ __volatile__( \ |
| 369 | − ARM( "1: " T(str) " " __reg_oper1 ", [%1], #4\n" ) \ | |
| 370 | − ARM( "2: " T(str) " " __reg_oper0 ", [%1]\n" ) \ | |
| 371 | − THUMB( "1: " T(str) " " __reg_oper1 ", [%1]\n" ) \ | |
| 372 | − THUMB( "2: " T(str) " " __reg_oper0 ", [%1, #4]\n" ) \ | |
| 369 | + ARM( "1: " TUSER(str) " " __reg_oper1 ", [%1], #4\n" ) \ | |
| 370 | + ARM( "2: " TUSER(str) " " __reg_oper0 ", [%1]\n" ) \ | |
| 371 | + THUMB( "1: " TUSER(str) " " __reg_oper1 ", [%1]\n" ) \ | |
| 372 | + THUMB( "2: " TUSER(str) " " __reg_oper0 ", [%1, #4]\n" ) \ | |
| 373 | 373 | "3:\n" \ |
| 374 | 374 | " .pushsection .fixup,\"ax\"\n" \ |
| 375 | 375 | " .align 2\n" \ |
| @@ -37,8 +37,8 @@ · 36 unmodified lines | ||
| 37 | 37 | #define THUMB(x...) x |
| 38 | 38 | #ifdef __ASSEMBLY__ |
| 39 | 39 | #define W(instr) instr.w |
| 40 | −#endif | |
| 41 | 40 | #define BSYM(sym) sym + 1 |
| 41 | +#endif | |
| 42 | 42 | |
| 43 | 43 | #else /* !CONFIG_THUMB2_KERNEL */ |
| 44 | 44 | |
| @@ -49,8 +49,8 @@ · 4 unmodified lines | ||
| 49 | 49 | #define THUMB(x...) |
| 50 | 50 | #ifdef __ASSEMBLY__ |
| 51 | 51 | #define W(instr) instr |
| 52 | −#endif | |
| 53 | 52 | #define BSYM(sym) sym |
| 53 | +#endif | |
| 54 | 54 | |
| 55 | 55 | #endif /* CONFIG_THUMB2_KERNEL */ |
| 56 | 56 | |
| @@ -790,7 +790,7 @@ __kuser_cmpxchg64: @ 0xffff0f60 · 789 unmodified lines | ||
| 790 | 790 | smp_dmb arm |
| 791 | 791 | rsbs r0, r3, #0 @ set returned val and C flag |
| 792 | 792 | ldmfd sp!, {r4, r5, r6, r7} |
| 793 | − bx lr | |
| 793 | + usr_ret lr | |
| 794 | 794 | |
| 795 | 795 | #elif !defined(CONFIG_SMP) |
| 796 | 796 | |
| @@ -87,7 +87,7 @@ ENTRY(ret_from_fork) · 86 unmodified lines | ||
| 87 | 87 | get_thread_info tsk |
| 88 | 88 | ldr r1, [tsk, #TI_FLAGS] @ check for syscall tracing |
| 89 | 89 | mov why, #1 |
| 90 | − tst r1, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? | |
| 90 | + tst r1, #_TIF_SYSCALL_WORK @ are we tracing syscalls? | |
| 91 | 91 | beq ret_slow_syscall |
| 92 | 92 | mov r1, sp |
| 93 | 93 | mov r0, #1 @ trace exit [IP = 1] |
| @@ -149,6 +149,11 @@ ENDPROC(ret_from_fork) · 55 unmodified lines | ||
| 149 | 149 | #endif |
| 150 | 150 | #endif |
| 151 | 151 | |
| 152 | +.macro mcount_adjust_addr rd, rn | |
| 153 | + bic \rd, \rn, #1 @ clear the Thumb bit if present | |
| 154 | + sub \rd, \rd, #MCOUNT_INSN_SIZE | |
| 155 | +.endm | |
| 156 | + | |
| 152 | 157 | .macro __mcount suffix |
| 153 | 158 | mcount_enter |
| 154 | 159 | ldr r0, =ftrace_trace_function |
| @@ -173,8 +178,7 @@ ENDPROC(ret_from_fork) · 18 unmodified lines | ||
| 173 | 178 | mcount_exit |
| 174 | 179 | |
| 175 | 180 | 1: mcount_get_lr r1 @ lr of instrumented func |
| 176 | − mov r0, lr @ instrumented function | |
| 177 | − sub r0, r0, #MCOUNT_INSN_SIZE | |
| 181 | + mcount_adjust_addr r0, lr @ instrumented function | |
| 178 | 182 | adr lr, BSYM(2f) |
| 179 | 183 | mov pc, r2 |
| 180 | 184 | 2: mcount_exit |
| @@ -184,8 +188,7 @@ ENDPROC(ret_from_fork) · 3 unmodified lines | ||
| 184 | 188 | mcount_enter |
| 185 | 189 | |
| 186 | 190 | mcount_get_lr r1 @ lr of instrumented func |
| 187 | − mov r0, lr @ instrumented function | |
| 188 | − sub r0, r0, #MCOUNT_INSN_SIZE | |
| 191 | + mcount_adjust_addr r0, lr @ instrumented function | |
| 189 | 192 | |
| 190 | 193 | .globl ftrace_call\suffix |
| 191 | 194 | ftrace_call\suffix: |
| @@ -205,11 +208,11 @@ ftrace_graph_call\suffix: · 13 unmodified lines | ||
| 205 | 208 | #ifdef CONFIG_DYNAMIC_FTRACE |
| 206 | 209 | @ called from __ftrace_caller, saved in mcount_enter |
| 207 | 210 | ldr r1, [sp, #16] @ instrumented routine (func) |
| 211 | + mcount_adjust_addr r1, r1 | |
| 208 | 212 | #else |
| 209 | 213 | @ called from __mcount, untouched in lr |
| 210 | − mov r1, lr @ instrumented routine (func) | |
| 214 | + mcount_adjust_addr r1, lr @ instrumented routine (func) | |
| 211 | 215 | #endif |
| 212 | − sub r1, r1, #MCOUNT_INSN_SIZE | |
| 213 | 216 | mov r2, fp @ frame pointer |
| 214 | 217 | bl prepare_ftrace_return |
| 215 | 218 | mcount_exit |
| @@ -443,7 +446,7 @@ ENTRY(vector_swi) · 227 unmodified lines | ||
| 443 | 446 | 1: |
| 444 | 447 | #endif |
| 445 | 448 | |
| 446 | − tst r10, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? | |
| 449 | + tst r10, #_TIF_SYSCALL_WORK @ are we tracing syscalls? | |
| 447 | 450 | bne __sys_trace |
| 448 | 451 | |
| 449 | 452 | cmp scno, #NR_syscalls @ check upper syscall limit |
| @@ -469,6 +469,20 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] · 468 unmodified lines | ||
| 469 | 469 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
| 470 | 470 | }, |
| 471 | 471 | }, |
| 472 | + [C(NODE)] = { | |
| 473 | + [C(OP_READ)] = { | |
| 474 | + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | |
| 475 | + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | |
| 476 | + }, | |
| 477 | + [C(OP_WRITE)] = { | |
| 478 | + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | |
| 479 | + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | |
| 480 | + }, | |
| 481 | + [C(OP_PREFETCH)] = { | |
| 482 | + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | |
| 483 | + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | |
| 484 | + }, | |
| 485 | + }, | |
| 472 | 486 | }; |
| 473 | 487 | |
| 474 | 488 | /* |
| @@ -579,6 +593,20 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] · 104 unmodified lines | ||
| 579 | 593 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
| 580 | 594 | }, |
| 581 | 595 | }, |
| 596 | + [C(NODE)] = { | |
| 597 | + [C(OP_READ)] = { | |
| 598 | + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | |
| 599 | + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | |
| 600 | + }, | |
| 601 | + [C(OP_WRITE)] = { | |
| 602 | + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | |
| 603 | + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | |
| 604 | + }, | |
| 605 | + [C(OP_PREFETCH)] = { | |
| 606 | + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | |
| 607 | + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | |
| 608 | + }, | |
| 609 | + }, | |
| 582 | 610 | }; |
| 583 | 611 | |
| 584 | 612 | /* |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | #include <linux/perf_event.h> |
| 24 | 24 | #include <linux/hw_breakpoint.h> |
| 25 | 25 | #include <linux/regset.h> |
| 26 | +#include <linux/audit.h> | |
| 26 | 27 | |
| 27 | 28 | #include <asm/pgtable.h> |
| 28 | 29 | #include <asm/system.h> |
| @@ -699,10 +700,13 @@ static int vfp_set(struct task_struct *target, · 670 unmodified lines | ||
| 699 | 700 | { |
| 700 | 701 | int ret; |
| 701 | 702 | struct thread_info *thread = task_thread_info(target); |
| 702 | − struct vfp_hard_struct new_vfp = thread->vfpstate.hard; | |
| 703 | + struct vfp_hard_struct new_vfp; | |
| 703 | 704 | const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); |
| 704 | 705 | const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); |
| 705 | 706 | |
| 707 | + vfp_sync_hwstate(thread); | |
| 708 | + new_vfp = thread->vfpstate.hard; | |
| 709 | + | |
| 706 | 710 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
| 707 | 711 | &new_vfp.fpregs, |
| 708 | 712 | user_fpregs_offset, |
| @@ -723,9 +727,8 @@ static int vfp_set(struct task_struct *target, · 14 unmodified lines | ||
| 723 | 727 | if (ret) |
| 724 | 728 | return ret; |
| 725 | 729 | |
| 726 | − vfp_sync_hwstate(thread); | |
| 727 | − thread->vfpstate.hard = new_vfp; | |
| 728 | 730 | vfp_flush_hwstate(thread); |
| 731 | + thread->vfpstate.hard = new_vfp; | |
| 729 | 732 | |
| 730 | 733 | return 0; |
| 731 | 734 | } |
| @@ -902,15 +905,16 @@ long arch_ptrace(struct task_struct *child, long request, · 170 unmodified lines | ||
| 902 | 905 | return ret; |
| 903 | 906 | } |
| 904 | 907 | |
| 908 | +#ifdef __ARMEB__ | |
| 909 | +#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB | |
| 910 | +#else | |
| 911 | +#define AUDIT_ARCH_NR AUDIT_ARCH_ARM | |
| 912 | +#endif | |
| 913 | + | |
| 905 | 914 | asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) |
| 906 | 915 | { |
| 907 | 916 | unsigned long ip; |
| 908 | 917 | |
| 909 | − if (!test_thread_flag(TIF_SYSCALL_TRACE)) | |
| 910 | − return scno; | |
| 911 | − if (!(current->ptrace & PT_PTRACED)) | |
| 912 | − return scno; | |
| 913 | − | |
| 914 | 918 | /* |
| 915 | 919 | * Save IP. IP is used to denote syscall entry/exit: |
| 916 | 920 | * IP = 0 -> entry, = 1 -> exit |
| @@ -918,6 +922,17 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) · 1 unmodified line | ||
| 918 | 922 | ip = regs->ARM_ip; |
| 919 | 923 | regs->ARM_ip = why; |
| 920 | 924 | |
| 925 | + if (!ip) | |
| 926 | + audit_syscall_exit(regs); | |
| 927 | + else | |
| 928 | + audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0, | |
| 929 | + regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); | |
| 930 | + | |
| 931 | + if (!test_thread_flag(TIF_SYSCALL_TRACE)) | |
| 932 | + return scno; | |
| 933 | + if (!(current->ptrace & PT_PTRACED)) | |
| 934 | + return scno; | |
| 935 | + | |
| 921 | 936 | current_thread_info()->syscall = scno; |
| 922 | 937 | |
| 923 | 938 | /* the 0x80 provides a way for the tracing parent to distinguish |
| @@ -21,7 +21,6 @@ · 20 unmodified lines | ||
| 21 | 21 | #include <linux/init.h> |
| 22 | 22 | #include <linux/kexec.h> |
| 23 | 23 | #include <linux/of_fdt.h> |
| 24 | −#include <linux/crash_dump.h> | |
| 25 | 24 | #include <linux/root_dev.h> |
| 26 | 25 | #include <linux/cpu.h> |
| 27 | 26 | #include <linux/interrupt.h> |
| @@ -160,7 +159,7 @@ static struct resource mem_res[] = { · 132 unmodified lines | ||
| 160 | 159 | .flags = IORESOURCE_MEM |
| 161 | 160 | }, |
| 162 | 161 | { |
| 163 | − .name = "Kernel text", | |
| 162 | + .name = "Kernel code", | |
| 164 | 163 | .start = 0, |
| 165 | 164 | .end = 0, |
| 166 | 165 | .flags = IORESOURCE_MEM |
| @@ -427,6 +426,20 @@ void cpu_init(void) · 260 unmodified lines | ||
| 427 | 426 | : "r14"); |
| 428 | 427 | } |
| 429 | 428 | |
| 429 | +int __cpu_logical_map[NR_CPUS]; | |
| 430 | + | |
| 431 | +void __init smp_setup_processor_id(void) | |
| 432 | +{ | |
| 433 | + int i; | |
| 434 | + u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0; | |
| 435 | + | |
| 436 | + cpu_logical_map(0) = cpu; | |
| 437 | + for (i = 1; i < NR_CPUS; ++i) | |
| 438 | + cpu_logical_map(i) = i == cpu ? 0 : i; | |
| 439 | + | |
| 440 | + printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu); | |
| 441 | +} | |
| 442 | + | |
| 430 | 443 | static void __init setup_processor(void) |
| 431 | 444 | { |
| 432 | 445 | struct proc_info_list *list; |
| @@ -227,6 +227,8 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame) · 226 unmodified lines | ||
| 227 | 227 | if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) |
| 228 | 228 | return -EINVAL; |
| 229 | 229 | |
| 230 | + vfp_flush_hwstate(thread); | |
| 231 | + | |
| 230 | 232 | /* |
| 231 | 233 | * Copy the floating point registers. There can be unused |
| 232 | 234 | * registers see asm/hwcap.h for details. |
| @@ -251,9 +253,6 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame) · 18 unmodified lines | ||
| 251 | 253 | __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); |
| 252 | 254 | __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); |
| 253 | 255 | |
| 254 | − if (!err) | |
| 255 | − vfp_flush_hwstate(thread); | |
| 256 | − | |
| 257 | 256 | return err ? -EFAULT : 0; |
| 258 | 257 | } |
| 259 | 258 | |
| @@ -233,20 +233,6 @@ void __ref cpu_die(void) · 232 unmodified lines | ||
| 233 | 233 | } |
| 234 | 234 | #endif /* CONFIG_HOTPLUG_CPU */ |
| 235 | 235 | |
| 236 | −int __cpu_logical_map[NR_CPUS]; | |
| 237 | − | |
| 238 | −void __init smp_setup_processor_id(void) | |
| 239 | −{ | |
| 240 | − int i; | |
| 241 | − u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0; | |
| 242 | − | |
| 243 | − cpu_logical_map(0) = cpu; | |
| 244 | − for (i = 1; i < NR_CPUS; ++i) | |
| 245 | − cpu_logical_map(i) = i == cpu ? 0 : i; | |
| 246 | − | |
| 247 | − printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu); | |
| 248 | −} | |
| 249 | − | |
| 250 | 236 | /* |
| 251 | 237 | * Called by both boot and secondaries to move global data into |
| 252 | 238 | * per-processor storage. |
| @@ -443,9 +429,7 @@ static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent); · 190 unmodified lines | ||
| 443 | 429 | static void ipi_timer(void) |
| 444 | 430 | { |
| 445 | 431 | struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent); |
| 446 | − irq_enter(); | |
| 447 | 432 | evt->event_handler(evt); |
| 448 | − irq_exit(); | |
| 449 | 433 | } |
| 450 | 434 | |
| 451 | 435 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
| @@ -548,7 +532,9 @@ void handle_IPI(int ipinr, struct pt_regs *regs) · 96 unmodified lines | ||
| 548 | 532 | |
| 549 | 533 | switch (ipinr) { |
| 550 | 534 | case IPI_TIMER: |
| 535 | + irq_enter(); | |
| 551 | 536 | ipi_timer(); |
| 537 | + irq_exit(); | |
| 552 | 538 | break; |
| 553 | 539 | |
| 554 | 540 | case IPI_RESCHEDULE: |
| @@ -556,15 +542,21 @@ void handle_IPI(int ipinr, struct pt_regs *regs) · 1 unmodified line | ||
| 556 | 542 | break; |
| 557 | 543 | |
| 558 | 544 | case IPI_CALL_FUNC: |
| 545 | + irq_enter(); | |
| 559 | 546 | generic_smp_call_function_interrupt(); |
| 547 | + irq_exit(); | |
| 560 | 548 | break; |
| 561 | 549 | |
| 562 | 550 | case IPI_CALL_FUNC_SINGLE: |
| 551 | + irq_enter(); | |
| 563 | 552 | generic_smp_call_function_single_interrupt(); |
| 553 | + irq_exit(); | |
| 564 | 554 | break; |
| 565 | 555 | |
| 566 | 556 | case IPI_CPU_STOP: |
| 557 | + irq_enter(); | |
| 567 | 558 | ipi_cpu_stop(cpu); |
| 559 | + irq_exit(); | |
| 568 | 560 | break; |
| 569 | 561 | |
| 570 | 562 | default: |
| @@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = { · 128 unmodified lines | ||
| 129 | 129 | |
| 130 | 130 | static int twd_cpufreq_init(void) |
| 131 | 131 | { |
| 132 | − if (!IS_ERR(twd_clk)) | |
| 132 | + if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) | |
| 133 | 133 | return cpufreq_register_notifier(&twd_cpufreq_nb, |
| 134 | 134 | CPUFREQ_TRANSITION_NOTIFIER); |
| 135 | 135 | |
| @@ -252,6 +252,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) · 116 unmodified lines | ||
| 252 | 252 | else |
| 253 | 253 | twd_calibrate_rate(); |
| 254 | 254 | |
| 255 | + __raw_writel(0, twd_base + TWD_TIMER_CONTROL); | |
| 256 | + | |
| 255 | 257 | clk->name = "local_timer"; |
| 256 | 258 | clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
| 257 | 259 | CLOCK_EVT_FEAT_C3STOP; |
| @@ -266,6 +266,7 @@ void die(const char *str, struct pt_regs *regs, int err) · 265 unmodified lines | ||
| 266 | 266 | { |
| 267 | 267 | struct thread_info *thread = current_thread_info(); |
| 268 | 268 | int ret; |
| 269 | + enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE; | |
| 269 | 270 | |
| 270 | 271 | oops_enter(); |
| 271 | 272 | |
| @@ -273,7 +274,9 @@ void die(const char *str, struct pt_regs *regs, int err) · 1 unmodified line | ||
| 273 | 274 | console_verbose(); |
| 274 | 275 | bust_spinlocks(1); |
| 275 | 276 | if (!user_mode(regs)) |
| 276 | − report_bug(regs->ARM_pc, regs); | |
| 277 | + bug_type = report_bug(regs->ARM_pc, regs); | |
| 278 | + if (bug_type != BUG_TRAP_TYPE_NONE) | |
| 279 | + str = "Oops - BUG"; | |
| 277 | 280 | ret = __die(str, err, thread, regs); |
| 278 | 281 | |
| 279 | 282 | if (regs && kexec_should_crash(thread->task)) |
| @@ -4,11 +4,13 @@ · 3 unmodified lines | ||
| 4 | 4 | */ |
| 5 | 5 | |
| 6 | 6 | #include <asm-generic/vmlinux.lds.h> |
| 7 | +#include <asm/cache.h> | |
| 7 | 8 | #include <asm/thread_info.h> |
| 8 | 9 | #include <asm/memory.h> |
| 9 | 10 | #include <asm/page.h> |
| 10 | 11 | |
| 11 | 12 | #define PROC_INFO \ |
| 13 | + . = ALIGN(4); \ | |
| 12 | 14 | VMLINUX_SYMBOL(__proc_info_begin) = .; \ |
| 13 | 15 | *(.proc.info.init) \ |
| 14 | 16 | VMLINUX_SYMBOL(__proc_info_end) = .; |
| @@ -181,7 +183,7 @@ SECTIONS · 166 unmodified lines | ||
| 181 | 183 | } |
| 182 | 184 | #endif |
| 183 | 185 | |
| 184 | − PERCPU_SECTION(32) | |
| 186 | + PERCPU_SECTION(L1_CACHE_BYTES) | |
| 185 | 187 | |
| 186 | 188 | #ifdef CONFIG_XIP_KERNEL |
| 187 | 189 | __data_loc = ALIGN(4); /* location in binary */ |
| @@ -212,13 +214,13 @@ SECTIONS · 24 unmodified lines | ||
| 212 | 214 | #endif |
| 213 | 215 | |
| 214 | 216 | NOSAVE_DATA |
| 215 | − CACHELINE_ALIGNED_DATA(32) | |
| 216 | − READ_MOSTLY_DATA(32) | |
| 217 | + CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) | |
| 218 | + READ_MOSTLY_DATA(L1_CACHE_BYTES) | |
| 217 | 219 | |
| 218 | 220 | /* |
| 219 | 221 | * The exception fixup table (might need resorting at runtime) |
| 220 | 222 | */ |
| 221 | − . = ALIGN(32); | |
| 223 | + . = ALIGN(4); | |
| 222 | 224 | __start___ex_table = .; |
| 223 | 225 | #ifdef CONFIG_MMU |
| 224 | 226 | *(__ex_table) |
| @@ -31,18 +31,18 @@ · 30 unmodified lines | ||
| 31 | 31 | #include <asm/domain.h> |
| 32 | 32 | |
| 33 | 33 | ENTRY(__get_user_1) |
| 34 | −1: T(ldrb) r2, [r0] | |
| 34 | +1: TUSER(ldrb) r2, [r0] | |
| 35 | 35 | mov r0, #0 |
| 36 | 36 | mov pc, lr |
| 37 | 37 | ENDPROC(__get_user_1) |
| 38 | 38 | |
| 39 | 39 | ENTRY(__get_user_2) |
| 40 | 40 | #ifdef CONFIG_THUMB2_KERNEL |
| 41 | −2: T(ldrb) r2, [r0] | |
| 42 | −3: T(ldrb) r3, [r0, #1] | |
| 41 | +2: TUSER(ldrb) r2, [r0] | |
| 42 | +3: TUSER(ldrb) r3, [r0, #1] | |
| 43 | 43 | #else |
| 44 | −2: T(ldrb) r2, [r0], #1 | |
| 45 | −3: T(ldrb) r3, [r0] | |
| 44 | +2: TUSER(ldrb) r2, [r0], #1 | |
| 45 | +3: TUSER(ldrb) r3, [r0] | |
| 46 | 46 | #endif |
| 47 | 47 | #ifndef __ARMEB__ |
| 48 | 48 | orr r2, r2, r3, lsl #8 |
| @@ -54,7 +54,7 @@ ENTRY(__get_user_2) · 5 unmodified lines | ||
| 54 | 54 | ENDPROC(__get_user_2) |
| 55 | 55 | |
| 56 | 56 | ENTRY(__get_user_4) |
| 57 | −4: T(ldr) r2, [r0] | |
| 57 | +4: TUSER(ldr) r2, [r0] | |
| 58 | 58 | mov r0, #0 |
| 59 | 59 | mov pc, lr |
| 60 | 60 | ENDPROC(__get_user_4) |
| @@ -31,7 +31,7 @@ · 30 unmodified lines | ||
| 31 | 31 | #include <asm/domain.h> |
| 32 | 32 | |
| 33 | 33 | ENTRY(__put_user_1) |
| 34 | −1: T(strb) r2, [r0] | |
| 34 | +1: TUSER(strb) r2, [r0] | |
| 35 | 35 | mov r0, #0 |
| 36 | 36 | mov pc, lr |
| 37 | 37 | ENDPROC(__put_user_1) |
| @@ -40,19 +40,19 @@ ENTRY(__put_user_2) · 2 unmodified lines | ||
| 40 | 40 | mov ip, r2, lsr #8 |
| 41 | 41 | #ifdef CONFIG_THUMB2_KERNEL |
| 42 | 42 | #ifndef __ARMEB__ |
| 43 | −2: T(strb) r2, [r0] | |
| 44 | −3: T(strb) ip, [r0, #1] | |
| 43 | +2: TUSER(strb) r2, [r0] | |
| 44 | +3: TUSER(strb) ip, [r0, #1] | |
| 45 | 45 | #else |
| 46 | −2: T(strb) ip, [r0] | |
| 47 | −3: T(strb) r2, [r0, #1] | |
| 46 | +2: TUSER(strb) ip, [r0] | |
| 47 | +3: TUSER(strb) r2, [r0, #1] | |
| 48 | 48 | #endif |
| 49 | 49 | #else /* !CONFIG_THUMB2_KERNEL */ |
| 50 | 50 | #ifndef __ARMEB__ |
| 51 | −2: T(strb) r2, [r0], #1 | |
| 52 | −3: T(strb) ip, [r0] | |
| 51 | +2: TUSER(strb) r2, [r0], #1 | |
| 52 | +3: TUSER(strb) ip, [r0] | |
| 53 | 53 | #else |
| 54 | −2: T(strb) ip, [r0], #1 | |
| 55 | −3: T(strb) r2, [r0] | |
| 54 | +2: TUSER(strb) ip, [r0], #1 | |
| 55 | +3: TUSER(strb) r2, [r0] | |
| 56 | 56 | #endif |
| 57 | 57 | #endif /* CONFIG_THUMB2_KERNEL */ |
| 58 | 58 | mov r0, #0 |
| @@ -60,18 +60,18 @@ ENTRY(__put_user_2) · 1 unmodified line | ||
| 60 | 60 | ENDPROC(__put_user_2) |
| 61 | 61 | |
| 62 | 62 | ENTRY(__put_user_4) |
| 63 | −4: T(str) r2, [r0] | |
| 63 | +4: TUSER(str) r2, [r0] | |
| 64 | 64 | mov r0, #0 |
| 65 | 65 | mov pc, lr |
| 66 | 66 | ENDPROC(__put_user_4) |
| 67 | 67 | |
| 68 | 68 | ENTRY(__put_user_8) |
| 69 | 69 | #ifdef CONFIG_THUMB2_KERNEL |
| 70 | −5: T(str) r2, [r0] | |
| 71 | −6: T(str) r3, [r0, #4] | |
| 70 | +5: TUSER(str) r2, [r0] | |
| 71 | +6: TUSER(str) r3, [r0, #4] | |
| 72 | 72 | #else |
| 73 | −5: T(str) r2, [r0], #4 | |
| 74 | −6: T(str) r3, [r0] | |
| 73 | +5: TUSER(str) r2, [r0], #4 | |
| 74 | +6: TUSER(str) r3, [r0] | |
| 75 | 75 | #endif |
| 76 | 76 | mov r0, #0 |
| 77 | 77 | mov pc, lr |
| @@ -32,11 +32,11 @@ · 31 unmodified lines | ||
| 32 | 32 | rsb ip, ip, #4 |
| 33 | 33 | cmp ip, #2 |
| 34 | 34 | ldrb r3, [r1], #1 |
| 35 | −USER( T(strb) r3, [r0], #1) @ May fault | |
| 35 | +USER( TUSER( strb) r3, [r0], #1) @ May fault | |
| 36 | 36 | ldrgeb r3, [r1], #1 |
| 37 | −USER( T(strgeb) r3, [r0], #1) @ May fault | |
| 37 | +USER( TUSER( strgeb) r3, [r0], #1) @ May fault | |
| 38 | 38 | ldrgtb r3, [r1], #1 |
| 39 | −USER( T(strgtb) r3, [r0], #1) @ May fault | |
| 39 | +USER( TUSER( strgtb) r3, [r0], #1) @ May fault | |
| 40 | 40 | sub r2, r2, ip |
| 41 | 41 | b .Lc2u_dest_aligned |
| 42 | 42 | |
| @@ -59,7 +59,7 @@ ENTRY(__copy_to_user) · 16 unmodified lines | ||
| 59 | 59 | addmi ip, r2, #4 |
| 60 | 60 | bmi .Lc2u_0nowords |
| 61 | 61 | ldr r3, [r1], #4 |
| 62 | −USER( T(str) r3, [r0], #4) @ May fault | |
| 62 | +USER( TUSER( str) r3, [r0], #4) @ May fault | |
| 63 | 63 | mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction |
| 64 | 64 | rsb ip, ip, #0 |
| 65 | 65 | movs ip, ip, lsr #32 - PAGE_SHIFT |
| @@ -88,18 +88,18 @@ USER( T(str) r3, [r0], #4) @ May fault · 22 unmodified lines | ||
| 88 | 88 | stmneia r0!, {r3 - r4} @ Shouldnt fault |
| 89 | 89 | tst ip, #4 |
| 90 | 90 | ldrne r3, [r1], #4 |
| 91 | − T(strne) r3, [r0], #4 @ Shouldnt fault | |
| 91 | + TUSER( strne) r3, [r0], #4 @ Shouldnt fault | |
| 92 | 92 | ands ip, ip, #3 |
| 93 | 93 | beq .Lc2u_0fupi |
| 94 | 94 | .Lc2u_0nowords: teq ip, #0 |
| 95 | 95 | beq .Lc2u_finished |
| 96 | 96 | .Lc2u_nowords: cmp ip, #2 |
| 97 | 97 | ldrb r3, [r1], #1 |
| 98 | −USER( T(strb) r3, [r0], #1) @ May fault | |
| 98 | +USER( TUSER( strb) r3, [r0], #1) @ May fault | |
| 99 | 99 | ldrgeb r3, [r1], #1 |
| 100 | −USER( T(strgeb) r3, [r0], #1) @ May fault | |
| 100 | +USER( TUSER( strgeb) r3, [r0], #1) @ May fault | |
| 101 | 101 | ldrgtb r3, [r1], #1 |
| 102 | −USER( T(strgtb) r3, [r0], #1) @ May fault | |
| 102 | +USER( TUSER( strgtb) r3, [r0], #1) @ May fault | |
| 103 | 103 | b .Lc2u_finished |
| 104 | 104 | |
| 105 | 105 | .Lc2u_not_enough: |
| @@ -120,7 +120,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault · 14 unmodified lines | ||
| 120 | 120 | mov r3, r7, pull #8 |
| 121 | 121 | ldr r7, [r1], #4 |
| 122 | 122 | orr r3, r3, r7, push #24 |
| 123 | −USER( T(str) r3, [r0], #4) @ May fault | |
| 123 | +USER( TUSER( str) r3, [r0], #4) @ May fault | |
| 124 | 124 | mov ip, r0, lsl #32 - PAGE_SHIFT |
| 125 | 125 | rsb ip, ip, #0 |
| 126 | 126 | movs ip, ip, lsr #32 - PAGE_SHIFT |
| @@ -155,18 +155,18 @@ USER( T(str) r3, [r0], #4) @ May fault · 28 unmodified lines | ||
| 155 | 155 | movne r3, r7, pull #8 |
| 156 | 156 | ldrne r7, [r1], #4 |
| 157 | 157 | orrne r3, r3, r7, push #24 |
| 158 | − T(strne) r3, [r0], #4 @ Shouldnt fault | |
| 158 | + TUSER( strne) r3, [r0], #4 @ Shouldnt fault | |
| 159 | 159 | ands ip, ip, #3 |
| 160 | 160 | beq .Lc2u_1fupi |
| 161 | 161 | .Lc2u_1nowords: mov r3, r7, get_byte_1 |
| 162 | 162 | teq ip, #0 |
| 163 | 163 | beq .Lc2u_finished |
| 164 | 164 | cmp ip, #2 |
| 165 | −USER( T(strb) r3, [r0], #1) @ May fault | |
| 165 | +USER( TUSER( strb) r3, [r0], #1) @ May fault | |
| 166 | 166 | movge r3, r7, get_byte_2 |
| 167 | −USER( T(strgeb) r3, [r0], #1) @ May fault | |
| 167 | +USER( TUSER( strgeb) r3, [r0], #1) @ May fault | |
| 168 | 168 | movgt r3, r7, get_byte_3 |
| 169 | −USER( T(strgtb) r3, [r0], #1) @ May fault | |
| 169 | +USER( TUSER( strgtb) r3, [r0], #1) @ May fault | |
| 170 | 170 | b .Lc2u_finished |
| 171 | 171 | |
| 172 | 172 | .Lc2u_2fupi: subs r2, r2, #4 |
| @@ -175,7 +175,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault · 2 unmodified lines | ||
| 175 | 175 | mov r3, r7, pull #16 |
| 176 | 176 | ldr r7, [r1], #4 |
| 177 | 177 | orr r3, r3, r7, push #16 |
| 178 | −USER( T(str) r3, [r0], #4) @ May fault | |
| 178 | +USER( TUSER( str) r3, [r0], #4) @ May fault | |
| 179 | 179 | mov ip, r0, lsl #32 - PAGE_SHIFT |
| 180 | 180 | rsb ip, ip, #0 |
| 181 | 181 | movs ip, ip, lsr #32 - PAGE_SHIFT |
| @@ -210,18 +210,18 @@ USER( T(str) r3, [r0], #4) @ May fault · 28 unmodified lines | ||
| 210 | 210 | movne r3, r7, pull #16 |
| 211 | 211 | ldrne r7, [r1], #4 |
| 212 | 212 | orrne r3, r3, r7, push #16 |
| 213 | − T(strne) r3, [r0], #4 @ Shouldnt fault | |
| 213 | + TUSER( strne) r3, [r0], #4 @ Shouldnt fault | |
| 214 | 214 | ands ip, ip, #3 |
| 215 | 215 | beq .Lc2u_2fupi |
| 216 | 216 | .Lc2u_2nowords: mov r3, r7, get_byte_2 |
| 217 | 217 | teq ip, #0 |
| 218 | 218 | beq .Lc2u_finished |
| 219 | 219 | cmp ip, #2 |
| 220 | −USER( T(strb) r3, [r0], #1) @ May fault | |
| 220 | +USER( TUSER( strb) r3, [r0], #1) @ May fault | |
| 221 | 221 | movge r3, r7, get_byte_3 |
| 222 | −USER( T(strgeb) r3, [r0], #1) @ May fault | |
| 222 | +USER( TUSER( strgeb) r3, [r0], #1) @ May fault | |
| 223 | 223 | ldrgtb r3, [r1], #0 |
| 224 | −USER( T(strgtb) r3, [r0], #1) @ May fault | |
| 224 | +USER( TUSER( strgtb) r3, [r0], #1) @ May fault | |
| 225 | 225 | b .Lc2u_finished |
| 226 | 226 | |
| 227 | 227 | .Lc2u_3fupi: subs r2, r2, #4 |
| @@ -230,7 +230,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault · 2 unmodified lines | ||
| 230 | 230 | mov r3, r7, pull #24 |
| 231 | 231 | ldr r7, [r1], #4 |
| 232 | 232 | orr r3, r3, r7, push #8 |
| 233 | −USER( T(str) r3, [r0], #4) @ May fault | |
| 233 | +USER( TUSER( str) r3, [r0], #4) @ May fault | |
| 234 | 234 | mov ip, r0, lsl #32 - PAGE_SHIFT |
| 235 | 235 | rsb ip, ip, #0 |
| 236 | 236 | movs ip, ip, lsr #32 - PAGE_SHIFT |
| @@ -265,18 +265,18 @@ USER( T(str) r3, [r0], #4) @ May fault · 28 unmodified lines | ||
| 265 | 265 | movne r3, r7, pull #24 |
| 266 | 266 | ldrne r7, [r1], #4 |
| 267 | 267 | orrne r3, r3, r7, push #8 |
| 268 | − T(strne) r3, [r0], #4 @ Shouldnt fault | |
| 268 | + TUSER( strne) r3, [r0], #4 @ Shouldnt fault | |
| 269 | 269 | ands ip, ip, #3 |
| 270 | 270 | beq .Lc2u_3fupi |
| 271 | 271 | .Lc2u_3nowords: mov r3, r7, get_byte_3 |
| 272 | 272 | teq ip, #0 |
| 273 | 273 | beq .Lc2u_finished |
| 274 | 274 | cmp ip, #2 |
| 275 | −USER( T(strb) r3, [r0], #1) @ May fault | |
| 275 | +USER( TUSER( strb) r3, [r0], #1) @ May fault | |
| 276 | 276 | ldrgeb r3, [r1], #1 |
| 277 | −USER( T(strgeb) r3, [r0], #1) @ May fault | |
| 277 | +USER( TUSER( strgeb) r3, [r0], #1) @ May fault | |
| 278 | 278 | ldrgtb r3, [r1], #0 |
| 279 | −USER( T(strgtb) r3, [r0], #1) @ May fault | |
| 279 | +USER( TUSER( strgtb) r3, [r0], #1) @ May fault | |
| 280 | 280 | b .Lc2u_finished |
| 281 | 281 | ENDPROC(__copy_to_user) |
| 282 | 282 | |
| @@ -295,11 +295,11 @@ ENDPROC(__copy_to_user) · 12 unmodified lines | ||
| 295 | 295 | .Lcfu_dest_not_aligned: |
| 296 | 296 | rsb ip, ip, #4 |
| 297 | 297 | cmp ip, #2 |
| 298 | −USER( T(ldrb) r3, [r1], #1) @ May fault | |
| 298 | +USER( TUSER( ldrb) r3, [r1], #1) @ May fault | |
| 299 | 299 | strb r3, [r0], #1 |
| 300 | −USER( T(ldrgeb) r3, [r1], #1) @ May fault | |
| 300 | +USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault | |
| 301 | 301 | strgeb r3, [r0], #1 |
| 302 | −USER( T(ldrgtb) r3, [r1], #1) @ May fault | |
| 302 | +USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault | |
| 303 | 303 | strgtb r3, [r0], #1 |
| 304 | 304 | sub r2, r2, ip |
| 305 | 305 | b .Lcfu_dest_aligned |
| @@ -322,7 +322,7 @@ ENTRY(__copy_from_user) · 16 unmodified lines | ||
| 322 | 322 | .Lcfu_0fupi: subs r2, r2, #4 |
| 323 | 323 | addmi ip, r2, #4 |
| 324 | 324 | bmi .Lcfu_0nowords |
| 325 | −USER( T(ldr) r3, [r1], #4) | |
| 325 | +USER( TUSER( ldr) r3, [r1], #4) | |
| 326 | 326 | str r3, [r0], #4 |
| 327 | 327 | mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction |
| 328 | 328 | rsb ip, ip, #0 |
| @@ -351,18 +351,18 @@ USER( T(ldr) r3, [r1], #4) · 22 unmodified lines | ||
| 351 | 351 | ldmneia r1!, {r3 - r4} @ Shouldnt fault |
| 352 | 352 | stmneia r0!, {r3 - r4} |
| 353 | 353 | tst ip, #4 |
| 354 | − T(ldrne) r3, [r1], #4 @ Shouldnt fault | |
| 354 | + TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault | |
| 355 | 355 | strne r3, [r0], #4 |
| 356 | 356 | ands ip, ip, #3 |
| 357 | 357 | beq .Lcfu_0fupi |
| 358 | 358 | .Lcfu_0nowords: teq ip, #0 |
| 359 | 359 | beq .Lcfu_finished |
| 360 | 360 | .Lcfu_nowords: cmp ip, #2 |
| 361 | −USER( T(ldrb) r3, [r1], #1) @ May fault | |
| 361 | +USER( TUSER( ldrb) r3, [r1], #1) @ May fault | |
| 362 | 362 | strb r3, [r0], #1 |
| 363 | −USER( T(ldrgeb) r3, [r1], #1) @ May fault | |
| 363 | +USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault | |
| 364 | 364 | strgeb r3, [r0], #1 |
| 365 | −USER( T(ldrgtb) r3, [r1], #1) @ May fault | |
| 365 | +USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault | |
| 366 | 366 | strgtb r3, [r0], #1 |
| 367 | 367 | b .Lcfu_finished |
| 368 | 368 | |
| @@ -375,7 +375,7 @@ USER( T(ldrgtb) r3, [r1], #1) @ May fault · 6 unmodified lines | ||
| 375 | 375 | |
| 376 | 376 | .Lcfu_src_not_aligned: |
| 377 | 377 | bic r1, r1, #3 |
| 378 | −USER( T(ldr) r7, [r1], #4) @ May fault | |
| 378 | +USER( TUSER( ldr) r7, [r1], #4) @ May fault | |
| 379 | 379 | cmp ip, #2 |
| 380 | 380 | bgt .Lcfu_3fupi |
| 381 | 381 | beq .Lcfu_2fupi |
| @@ -383,7 +383,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault · 1 unmodified line | ||
| 383 | 383 | addmi ip, r2, #4 |
| 384 | 384 | bmi .Lcfu_1nowords |
| 385 | 385 | mov r3, r7, pull #8 |
| 386 | −USER( T(ldr) r7, [r1], #4) @ May fault | |
| 386 | +USER( TUSER( ldr) r7, [r1], #4) @ May fault | |
| 387 | 387 | orr r3, r3, r7, push #24 |
| 388 | 388 | str r3, [r0], #4 |
| 389 | 389 | mov ip, r1, lsl #32 - PAGE_SHIFT |
| @@ -418,7 +418,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault · 28 unmodified lines | ||
| 418 | 418 | stmneia r0!, {r3 - r4} |
| 419 | 419 | tst ip, #4 |
| 420 | 420 | movne r3, r7, pull #8 |
| 421 | −USER( T(ldrne) r7, [r1], #4) @ May fault | |
| 421 | +USER( TUSER( ldrne) r7, [r1], #4) @ May fault | |
| 422 | 422 | orrne r3, r3, r7, push #24 |
| 423 | 423 | strne r3, [r0], #4 |
| 424 | 424 | ands ip, ip, #3 |
| @@ -438,7 +438,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault · 13 unmodified lines | ||
| 438 | 438 | addmi ip, r2, #4 |
| 439 | 439 | bmi .Lcfu_2nowords |
| 440 | 440 | mov r3, r7, pull #16 |
| 441 | −USER( T(ldr) r7, [r1], #4) @ May fault | |
| 441 | +USER( TUSER( ldr) r7, [r1], #4) @ May fault | |
| 442 | 442 | orr r3, r3, r7, push #16 |
| 443 | 443 | str r3, [r0], #4 |
| 444 | 444 | mov ip, r1, lsl #32 - PAGE_SHIFT |
| @@ -474,7 +474,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault · 29 unmodified lines | ||
| 474 | 474 | stmneia r0!, {r3 - r4} |
| 475 | 475 | tst ip, #4 |
| 476 | 476 | movne r3, r7, pull #16 |
| 477 | −USER( T(ldrne) r7, [r1], #4) @ May fault | |
| 477 | +USER( TUSER( ldrne) r7, [r1], #4) @ May fault | |
| 478 | 478 | orrne r3, r3, r7, push #16 |
| 479 | 479 | strne r3, [r0], #4 |
| 480 | 480 | ands ip, ip, #3 |
| @@ -486,7 +486,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault · 5 unmodified lines | ||
| 486 | 486 | strb r3, [r0], #1 |
| 487 | 487 | movge r3, r7, get_byte_3 |
| 488 | 488 | strgeb r3, [r0], #1 |
| 489 | −USER( T(ldrgtb) r3, [r1], #0) @ May fault | |
| 489 | +USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault | |
| 490 | 490 | strgtb r3, [r0], #1 |
| 491 | 491 | b .Lcfu_finished |
| 492 | 492 | |
| @@ -494,7 +494,7 @@ USER( T(ldrgtb) r3, [r1], #0) @ May fault · 1 unmodified line | ||
| 494 | 494 | addmi ip, r2, #4 |
| 495 | 495 | bmi .Lcfu_3nowords |
| 496 | 496 | mov r3, r7, pull #24 |
| 497 | −USER( T(ldr) r7, [r1], #4) @ May fault | |
| 497 | +USER( TUSER( ldr) r7, [r1], #4) @ May fault | |
| 498 | 498 | orr r3, r3, r7, push #8 |
| 499 | 499 | str r3, [r0], #4 |
| 500 | 500 | mov ip, r1, lsl #32 - PAGE_SHIFT |
| @@ -529,7 +529,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault · 28 unmodified lines | ||
| 529 | 529 | stmneia r0!, {r3 - r4} |
| 530 | 530 | tst ip, #4 |
| 531 | 531 | movne r3, r7, pull #24 |
| 532 | −USER( T(ldrne) r7, [r1], #4) @ May fault | |
| 532 | +USER( TUSER( ldrne) r7, [r1], #4) @ May fault | |
| 533 | 533 | orrne r3, r3, r7, push #8 |
| 534 | 534 | strne r3, [r0], #4 |
| 535 | 535 | ands ip, ip, #3 |
| @@ -539,9 +539,9 @@ USER( T(ldrne) r7, [r1], #4) @ May fault · 3 unmodified lines | ||
| 539 | 539 | beq .Lcfu_finished |
| 540 | 540 | cmp ip, #2 |
| 541 | 541 | strb r3, [r0], #1 |
| 542 | −USER( T(ldrgeb) r3, [r1], #1) @ May fault | |
| 542 | +USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault | |
| 543 | 543 | strgeb r3, [r0], #1 |
| 544 | −USER( T(ldrgtb) r3, [r1], #1) @ May fault | |
| 544 | +USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault | |
| 545 | 545 | strgtb r3, [r0], #1 |
| 546 | 546 | b .Lcfu_finished |
| 547 | 547 | ENDPROC(__copy_from_user) |
| @@ -18,6 +18,12 @@ config HAVE_AT91_USART4 · 17 unmodified lines | ||
| 18 | 18 | config HAVE_AT91_USART5 |
| 19 | 19 | bool |
| 20 | 20 | |
| 21 | +config AT91_SAM9_ALT_RESET | |
| 22 | + bool | |
| 23 | + | |
| 24 | +config AT91_SAM9G45_RESET | |
| 25 | + bool | |
| 26 | + | |
| 21 | 27 | menu "Atmel AT91 System-on-Chip" |
| 22 | 28 | |
| 23 | 29 | choice |
| @@ -39,6 +45,7 @@ config ARCH_AT91SAM9260 · 15 unmodified lines | ||
| 39 | 45 | select HAVE_AT91_USART4 |
| 40 | 46 | select HAVE_AT91_USART5 |
| 41 | 47 | select HAVE_NET_MACB |
| 48 | + select AT91_SAM9_ALT_RESET | |
| 42 | 49 | |
| 43 | 50 | config ARCH_AT91SAM9261 |
| 44 | 51 | bool "AT91SAM9261" |
| @@ -46,6 +53,7 @@ config ARCH_AT91SAM9261 · 1 unmodified line | ||
| 46 | 53 | select GENERIC_CLOCKEVENTS |
| 47 | 54 | select HAVE_FB_ATMEL |
| 48 | 55 | select HAVE_AT91_DBGU0 |
| 56 | + select AT91_SAM9_ALT_RESET | |
| 49 | 57 | |
| 50 | 58 | config ARCH_AT91SAM9G10 |
| 51 | 59 | bool "AT91SAM9G10" |
| @@ -53,6 +61,7 @@ config ARCH_AT91SAM9G10 · 1 unmodified line | ||
| 53 | 61 | select GENERIC_CLOCKEVENTS |
| 54 | 62 | select HAVE_AT91_DBGU0 |
| 55 | 63 | select HAVE_FB_ATMEL |
| 64 | + select AT91_SAM9_ALT_RESET | |
| 56 | 65 | |
| 57 | 66 | config ARCH_AT91SAM9263 |
| 58 | 67 | bool "AT91SAM9263" |
| @@ -61,6 +70,7 @@ config ARCH_AT91SAM9263 · 2 unmodified lines | ||
| 61 | 70 | select HAVE_FB_ATMEL |
| 62 | 71 | select HAVE_NET_MACB |
| 63 | 72 | select HAVE_AT91_DBGU1 |
| 73 | + select AT91_SAM9_ALT_RESET | |
| 64 | 74 | |
| 65 | 75 | config ARCH_AT91SAM9RL |
| 66 | 76 | bool "AT91SAM9RL" |
| @@ -69,6 +79,7 @@ config ARCH_AT91SAM9RL · 2 unmodified lines | ||
| 69 | 79 | select HAVE_AT91_USART3 |
| 70 | 80 | select HAVE_FB_ATMEL |
| 71 | 81 | select HAVE_AT91_DBGU0 |
| 82 | + select AT91_SAM9_ALT_RESET | |
| 72 | 83 | |
| 73 | 84 | config ARCH_AT91SAM9G20 |
| 74 | 85 | bool "AT91SAM9G20" |
| @@ -79,6 +90,7 @@ config ARCH_AT91SAM9G20 · 4 unmodified lines | ||
| 79 | 90 | select HAVE_AT91_USART4 |
| 80 | 91 | select HAVE_AT91_USART5 |
| 81 | 92 | select HAVE_NET_MACB |
| 93 | + select AT91_SAM9_ALT_RESET | |
| 82 | 94 | |
| 83 | 95 | config ARCH_AT91SAM9G45 |
| 84 | 96 | bool "AT91SAM9G45" |
| @@ -88,6 +100,7 @@ config ARCH_AT91SAM9G45 · 3 unmodified lines | ||
| 88 | 100 | select HAVE_FB_ATMEL |
| 89 | 101 | select HAVE_NET_MACB |
| 90 | 102 | select HAVE_AT91_DBGU1 |
| 103 | + select AT91_SAM9G45_RESET | |
| 91 | 104 | |
| 92 | 105 | config ARCH_AT91CAP9 |
| 93 | 106 | bool "AT91CAP9" |
| @@ -96,6 +109,7 @@ config ARCH_AT91CAP9 · 2 unmodified lines | ||
| 96 | 109 | select HAVE_FB_ATMEL |
| 97 | 110 | select HAVE_NET_MACB |
| 98 | 111 | select HAVE_AT91_DBGU1 |
| 112 | + select AT91_SAM9G45_RESET | |
| 99 | 113 | |
| 100 | 114 | config ARCH_AT91X40 |
| 101 | 115 | bool "AT91x40" |
| @@ -8,15 +8,17 @@ obj-n := · 7 unmodified lines | ||
| 8 | 8 | obj- := |
| 9 | 9 | |
| 10 | 10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o |
| 11 | +obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o | |
| 12 | +obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o | |
| 11 | 13 | |
| 12 | 14 | # CPU-specific support |
| 13 | 15 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o |
| 14 | −obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o | |
| 15 | −obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o | |
| 16 | −obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o | |
| 17 | −obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o | |
| 18 | −obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o | |
| 19 | −obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o | |
| 16 | +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o | |
| 17 | +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o | |
| 18 | +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o | |
| 19 | +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o | |
| 20 | +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o | |
| 21 | +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o | |
| 20 | 22 | obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o |
| 21 | 23 | obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o |
| 22 | 24 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o |
| @@ -21,7 +21,6 @@ · 20 unmodified lines | ||
| 21 | 21 | #include <mach/cpu.h> |
| 22 | 22 | #include <mach/at91cap9.h> |
| 23 | 23 | #include <mach/at91_pmc.h> |
| 24 | −#include <mach/at91_rstc.h> | |
| 25 | 24 | |
| 26 | 25 | #include "soc.h" |
| 27 | 26 | #include "generic.h" |
| @@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = { · 286 unmodified lines | ||
| 314 | 313 | } |
| 315 | 314 | }; |
| 316 | 315 | |
| 317 | −static void at91cap9_restart(char mode, const char *cmd) | |
| 318 | −{ | |
| 319 | − at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | |
| 320 | −} | |
| 321 | − | |
| 322 | 316 | /* -------------------------------------------------------------------- |
| 323 | 317 | * AT91CAP9 processor initialization |
| 324 | 318 | * -------------------------------------------------------------------- */ |
| @@ -331,13 +325,14 @@ static void __init at91cap9_map_io(void) · 6 unmodified lines | ||
| 331 | 325 | static void __init at91cap9_ioremap_registers(void) |
| 332 | 326 | { |
| 333 | 327 | at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); |
| 328 | + at91_ioremap_rstc(AT91CAP9_BASE_RSTC); | |
| 334 | 329 | at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); |
| 335 | 330 | at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); |
| 336 | 331 | } |
| 337 | 332 | |
| 338 | 333 | static void __init at91cap9_initialize(void) |
| 339 | 334 | { |
| 340 | − arm_pm_restart = at91cap9_restart; | |
| 335 | + arm_pm_restart = at91sam9g45_restart; | |
| 341 | 336 | at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); |
| 342 | 337 | |
| 343 | 338 | /* Register GPIO subsystem */ |
| @@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} · 82 unmodified lines | ||
| 83 | 83 | * USB Device (Gadget) |
| 84 | 84 | * -------------------------------------------------------------------- */ |
| 85 | 85 | |
| 86 | −#ifdef CONFIG_USB_AT91 | |
| 86 | +#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) | |
| 87 | 87 | static struct at91_udc_data udc_data; |
| 88 | 88 | |
| 89 | 89 | static struct resource udc_resources[] = { |
| @@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void) · 322 unmodified lines | ||
| 323 | 323 | static void __init at91sam9260_ioremap_registers(void) |
| 324 | 324 | { |
| 325 | 325 | at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); |
| 326 | + at91_ioremap_rstc(AT91SAM9260_BASE_RSTC); | |
| 326 | 327 | at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); |
| 327 | 328 | at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); |
| 328 | 329 | } |
| @@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} · 83 unmodified lines | ||
| 84 | 84 | * USB Device (Gadget) |
| 85 | 85 | * -------------------------------------------------------------------- */ |
| 86 | 86 | |
| 87 | −#ifdef CONFIG_USB_AT91 | |
| 87 | +#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) | |
| 88 | 88 | static struct at91_udc_data udc_data; |
| 89 | 89 | |
| 90 | 90 | static struct resource udc_resources[] = { |
| @@ -1215,8 +1215,7 @@ void __init at91_add_device_serial(void) {} · 1124 unmodified lines | ||
| 1215 | 1215 | * CF/IDE |
| 1216 | 1216 | * -------------------------------------------------------------------- */ |
| 1217 | 1217 | |
| 1218 | −#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \ | |
| 1219 | − defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ | |
| 1218 | +#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ | |
| 1220 | 1219 | defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) |
| 1221 | 1220 | |
| 1222 | 1221 | static struct at91_cf_data cf0_data; |
| @@ -1313,10 +1312,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data) · 90 unmodified lines | ||
| 1313 | 1312 | if (data->flags & AT91_CF_TRUE_IDE) |
| 1314 | 1313 | #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) |
| 1315 | 1314 | pdev->name = "pata_at91"; |
| 1316 | −#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) | |
| 1317 | − pdev->name = "at91_ide"; | |
| 1318 | 1315 | #else |
| 1319 | −#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91" | |
| 1316 | +#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91" | |
| 1320 | 1317 | #endif |
| 1321 | 1318 | else |
| 1322 | 1319 | pdev->name = "at91_cf"; |
| @@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void) · 280 unmodified lines | ||
| 281 | 281 | static void __init at91sam9261_ioremap_registers(void) |
| 282 | 282 | { |
| 283 | 283 | at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); |
| 284 | + at91_ioremap_rstc(AT91SAM9261_BASE_RSTC); | |
| 284 | 285 | at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); |
| 285 | 286 | at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); |
| 286 | 287 | } |
| @@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} · 86 unmodified lines | ||
| 87 | 87 | * USB Device (Gadget) |
| 88 | 88 | * -------------------------------------------------------------------- */ |
| 89 | 89 | |
| 90 | −#ifdef CONFIG_USB_AT91 | |
| 90 | +#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) | |
| 91 | 91 | static struct at91_udc_data udc_data; |
| 92 | 92 | |
| 93 | 93 | static struct resource udc_resources[] = { |
| @@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void) · 300 unmodified lines | ||
| 301 | 301 | static void __init at91sam9263_ioremap_registers(void) |
| 302 | 302 | { |
| 303 | 303 | at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); |
| 304 | + at91_ioremap_rstc(AT91SAM9263_BASE_RSTC); | |
| 304 | 305 | at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); |
| 305 | 306 | at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); |
| 306 | 307 | at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); |
| @@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} · 91 unmodified lines | ||
| 92 | 92 | * USB Device (Gadget) |
| 93 | 93 | * -------------------------------------------------------------------- */ |
| 94 | 94 | |
| 95 | −#ifdef CONFIG_USB_AT91 | |
| 95 | +#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) | |
| 96 | 96 | static struct at91_udc_data udc_data; |
| 97 | 97 | |
| 98 | 98 | static struct resource udc_resources[] = { |
| @@ -355,8 +355,8 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} · 256 unmodified lines | ||
| 355 | 355 | * Compact Flash (PCMCIA or IDE) |
| 356 | 356 | * -------------------------------------------------------------------- */ |
| 357 | 357 | |
| 358 | −#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \ | |
| 359 | − defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) | |
| 358 | +#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ | |
| 359 | + defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) | |
| 360 | 360 | |
| 361 | 361 | static struct at91_cf_data cf0_data; |
| 362 | 362 | |
| @@ -450,7 +450,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) · 87 unmodified lines | ||
| 450 | 450 | at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ |
| 451 | 451 | at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ |
| 452 | 452 | |
| 453 | − pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf"; | |
| 453 | + pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf"; | |
| 454 | 454 | platform_device_register(pdev); |
| 455 | 455 | } |
| 456 | 456 | #else |
| @@ -23,7 +23,8 @@ · 22 unmodified lines | ||
| 23 | 23 | .globl at91sam9_alt_restart |
| 24 | 24 | |
| 25 | 25 | at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants |
| 26 | − ldr r1, .at91_va_base_rstc_cr | |
| 26 | + ldr r1, =at91_rstc_base | |
| 27 | + ldr r1, [r1] | |
| 27 | 28 | |
| 28 | 29 | mov r2, #1 |
| 29 | 30 | mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN |
| @@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants · 3 unmodified lines | ||
| 33 | 34 | |
| 34 | 35 | str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access |
| 35 | 36 | str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM |
| 36 | − str r4, [r1] @ reset processor | |
| 37 | + str r4, [r1, #AT91_RSTC_CR] @ reset processor | |
| 37 | 38 | |
| 38 | 39 | b . |
| 39 | 40 | |
| 40 | 41 | .at91_va_base_sdramc: |
| 41 | 42 | .word AT91_VA_BASE_SYS + AT91_SDRAMC0 |
| 42 | −.at91_va_base_rstc_cr: | |
| 43 | − .word AT91_VA_BASE_SYS + AT91_RSTC_CR | |
| @@ -18,7 +18,6 @@ · 17 unmodified lines | ||
| 18 | 18 | #include <asm/mach/map.h> |
| 19 | 19 | #include <mach/at91sam9g45.h> |
| 20 | 20 | #include <mach/at91_pmc.h> |
| 21 | −#include <mach/at91_rstc.h> | |
| 22 | 21 | #include <mach/cpu.h> |
| 23 | 22 | |
| 24 | 23 | #include "soc.h" |
| @@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = { · 293 unmodified lines | ||
| 318 | 317 | } |
| 319 | 318 | }; |
| 320 | 319 | |
| 321 | −static void at91sam9g45_restart(char mode, const char *cmd) | |
| 322 | −{ | |
| 323 | − at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | |
| 324 | −} | |
| 325 | − | |
| 326 | 320 | /* -------------------------------------------------------------------- |
| 327 | 321 | * AT91SAM9G45 processor initialization |
| 328 | 322 | * -------------------------------------------------------------------- */ |
| @@ -336,6 +330,7 @@ static void __init at91sam9g45_map_io(void) · 7 unmodified lines | ||
| 336 | 330 | static void __init at91sam9g45_ioremap_registers(void) |
| 337 | 331 | { |
| 338 | 332 | at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); |
| 333 | + at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); | |
| 339 | 334 | at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); |
| 340 | 335 | at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); |
| 341 | 336 | } |
| @@ -0,0 +1,40 @@ | ||
| 1 | +/* | |
| 2 | + * reset AT91SAM9G45 as per errata | |
| 3 | + * | |
| 4 | + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com> | |
| 5 | + * | |
| 6 | + * unless the SDRAM is cleanly shutdown before we hit the | |
| 7 | + * reset register it can be left driving the data bus and | |
| 8 | + * killing the chance of a subsequent boot from NAND | |
| 9 | + * | |
| 10 | + * GPLv2 Only | |
| 11 | + */ | |
| 12 | + | |
| 13 | +#include <linux/linkage.h> | |
| 14 | +#include <mach/hardware.h> | |
| 15 | +#include <mach/at91sam9_ddrsdr.h> | |
| 16 | +#include <mach/at91_rstc.h> | |
| 17 | + | |
| 18 | + .arm | |
| 19 | + | |
| 20 | + .globl at91sam9g45_restart | |
| 21 | + | |
| 22 | +at91sam9g45_restart: | |
| 23 | + ldr r0, .at91_va_base_sdramc0 @ preload constants | |
| 24 | + ldr r1, =at91_rstc_base | |
| 25 | + ldr r1, [r1] | |
| 26 | + | |
| 27 | + mov r2, #1 | |
| 28 | + mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN | |
| 29 | + ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST | |
| 30 | + | |
| 31 | + .balign 32 @ align to cache line | |
| 32 | + | |
| 33 | + str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access | |
| 34 | + str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 | |
| 35 | + str r4, [r1, #AT91_RSTC_CR] @ reset processor | |
| 36 | + | |
| 37 | + b . | |
| 38 | + | |
| 39 | +.at91_va_base_sdramc0: | |
| 40 | + .word AT91_VA_BASE_SYS + AT91_DDRSDRC0 | |
| @@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void) · 285 unmodified lines | ||
| 286 | 286 | static void __init at91sam9rl_ioremap_registers(void) |
| 287 | 287 | { |
| 288 | 288 | at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); |
| 289 | + at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); | |
| 289 | 290 | at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); |
| 290 | 291 | at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); |
| 291 | 292 | } |
| @@ -58,7 +58,9 @@ extern void at91_irq_suspend(void); · 57 unmodified lines | ||
| 58 | 58 | extern void at91_irq_resume(void); |
| 59 | 59 | |
| 60 | 60 | /* reset */ |
| 61 | +extern void at91_ioremap_rstc(u32 base_addr); | |
| 61 | 62 | extern void at91sam9_alt_restart(char, const char *); |
| 63 | +extern void at91sam9g45_restart(char, const char *); | |
| 62 | 64 | |
| 63 | 65 | /* shutdown */ |
| 64 | 66 | extern void at91_ioremap_shdwc(u32 base_addr); |
| @@ -16,13 +16,25 @@ · 15 unmodified lines | ||
| 16 | 16 | #ifndef AT91_RSTC_H |
| 17 | 17 | #define AT91_RSTC_H |
| 18 | 18 | |
| 19 | −#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | |
| 19 | +#ifndef __ASSEMBLY__ | |
| 20 | +extern void __iomem *at91_rstc_base; | |
| 21 | + | |
| 22 | +#define at91_rstc_read(field) \ | |
| 23 | + __raw_readl(at91_rstc_base + field) | |
| 24 | + | |
| 25 | +#define at91_rstc_write(field, value) \ | |
| 26 | + __raw_writel(value, at91_rstc_base + field); | |
| 27 | +#else | |
| 28 | +.extern at91_rstc_base | |
| 29 | +#endif | |
| 30 | + | |
| 31 | +#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ | |
| 20 | 32 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ |
| 21 | 33 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ |
| 22 | 34 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ |
| 23 | 35 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ |
| 24 | 36 | |
| 25 | −#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | |
| 37 | +#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */ | |
| 26 | 38 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ |
| 27 | 39 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ |
| 28 | 40 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) |
| @@ -33,7 +45,7 @@ · 4 unmodified lines | ||
| 33 | 45 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ |
| 34 | 46 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ |
| 35 | 47 | |
| 36 | −#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | |
| 48 | +#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ | |
| 37 | 49 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ |
| 38 | 50 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ |
| 39 | 51 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ |
| @@ -83,7 +83,6 @@ · 82 unmodified lines | ||
| 83 | 83 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
| 84 | 84 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
| 85 | 85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
| 86 | −#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | |
| 87 | 86 | #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ |
| 88 | 87 | (0xfffffd50 - AT91_BASE_SYS) : \ |
| 89 | 88 | (0xfffffd60 - AT91_BASE_SYS)) |
| @@ -96,6 +95,7 @@ · 6 unmodified lines | ||
| 96 | 95 | #define AT91CAP9_BASE_PIOB 0xfffff400 |
| 97 | 96 | #define AT91CAP9_BASE_PIOC 0xfffff600 |
| 98 | 97 | #define AT91CAP9_BASE_PIOD 0xfffff800 |
| 98 | +#define AT91CAP9_BASE_RSTC 0xfffffd00 | |
| 99 | 99 | #define AT91CAP9_BASE_SHDWC 0xfffffd10 |
| 100 | 100 | #define AT91CAP9_BASE_RTT 0xfffffd20 |
| 101 | 101 | #define AT91CAP9_BASE_PIT 0xfffffd30 |
| @@ -1,108 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | |
| 3 | − * | |
| 4 | − * (C) 2008 Andrew Victor | |
| 5 | − * | |
| 6 | − * DDR/SDR Controller (DDRSDRC) - System peripherals registers. | |
| 7 | − * Based on AT91CAP9 datasheet revision B. | |
| 8 | − * | |
| 9 | − * This program is free software; you can redistribute it and/or modify | |
| 10 | − * it under the terms of the GNU General Public License as published by | |
| 11 | − * the Free Software Foundation; either version 2 of the License, or | |
| 12 | − * (at your option) any later version. | |
| 13 | − */ | |
| 14 | − | |
| 15 | −#ifndef AT91CAP9_DDRSDR_H | |
| 16 | −#define AT91CAP9_DDRSDR_H | |
| 17 | − | |
| 18 | −#define AT91_DDRSDRC_MR 0x00 /* Mode Register */ | |
| 19 | −#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ | |
| 20 | −#define AT91_DDRSDRC_MODE_NORMAL 0 | |
| 21 | −#define AT91_DDRSDRC_MODE_NOP 1 | |
| 22 | −#define AT91_DDRSDRC_MODE_PRECHARGE 2 | |
| 23 | −#define AT91_DDRSDRC_MODE_LMR 3 | |
| 24 | −#define AT91_DDRSDRC_MODE_REFRESH 4 | |
| 25 | −#define AT91_DDRSDRC_MODE_EXT_LMR 5 | |
| 26 | −#define AT91_DDRSDRC_MODE_DEEP 6 | |
| 27 | − | |
| 28 | −#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ | |
| 29 | −#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | |
| 30 | − | |
| 31 | −#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ | |
| 32 | −#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ | |
| 33 | −#define AT91_DDRSDRC_NC_SDR8 (0 << 0) | |
| 34 | −#define AT91_DDRSDRC_NC_SDR9 (1 << 0) | |
| 35 | −#define AT91_DDRSDRC_NC_SDR10 (2 << 0) | |
| 36 | −#define AT91_DDRSDRC_NC_SDR11 (3 << 0) | |
| 37 | −#define AT91_DDRSDRC_NC_DDR9 (0 << 0) | |
| 38 | −#define AT91_DDRSDRC_NC_DDR10 (1 << 0) | |
| 39 | −#define AT91_DDRSDRC_NC_DDR11 (2 << 0) | |
| 40 | −#define AT91_DDRSDRC_NC_DDR12 (3 << 0) | |
| 41 | −#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ | |
| 42 | −#define AT91_DDRSDRC_NR_11 (0 << 2) | |
| 43 | −#define AT91_DDRSDRC_NR_12 (1 << 2) | |
| 44 | −#define AT91_DDRSDRC_NR_13 (2 << 2) | |
| 45 | −#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ | |
| 46 | −#define AT91_DDRSDRC_CAS_2 (2 << 4) | |
| 47 | −#define AT91_DDRSDRC_CAS_3 (3 << 4) | |
| 48 | −#define AT91_DDRSDRC_CAS_25 (6 << 4) | |
| 49 | −#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ | |
| 50 | −#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ | |
| 51 | − | |
| 52 | −#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ | |
| 53 | −#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ | |
| 54 | −#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ | |
| 55 | −#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ | |
| 56 | −#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ | |
| 57 | −#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | |
| 58 | −#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | |
| 59 | −#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | |
| 60 | −#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | |
| 61 | − | |
| 62 | −#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ | |
| 63 | −#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ | |
| 64 | −#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ | |
| 65 | −#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ | |
| 66 | −#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ | |
| 67 | − | |
| 68 | −#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */ | |
| 69 | −#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | |
| 70 | −#define AT91_DDRSDRC_LPCB_DISABLE 0 | |
| 71 | −#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | |
| 72 | −#define AT91_DDRSDRC_LPCB_POWER_DOWN 2 | |
| 73 | −#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 | |
| 74 | −#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ | |
| 75 | −#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ | |
| 76 | −#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | |
| 77 | −#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ | |
| 78 | −#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | |
| 79 | −#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) | |
| 80 | −#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) | |
| 81 | −#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) | |
| 82 | − | |
| 83 | −#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */ | |
| 84 | −#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | |
| 85 | −#define AT91_DDRSDRC_MD_SDR 0 | |
| 86 | −#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | |
| 87 | −#define AT91_DDRSDRC_MD_DDR 2 | |
| 88 | −#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | |
| 89 | − | |
| 90 | −#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ | |
| 91 | −#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | |
| 92 | −#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | |
| 93 | −#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | |
| 94 | −#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | |
| 95 | −#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | |
| 96 | −#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | |
| 97 | −#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | |
| 98 | −#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | |
| 99 | −#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | |
| 100 | − | |
| 101 | −/* Register access macros */ | |
| 102 | −#define at91_ramc_read(num, reg) \ | |
| 103 | − at91_sys_read(AT91_DDRSDRC##num + reg) | |
| 104 | −#define at91_ramc_write(num, reg, value) \ | |
| 105 | − at91_sys_write(AT91_DDRSDRC##num + reg, value) | |
| 106 | − | |
| 107 | − | |
| 108 | −#endif | |
| @@ -83,7 +83,6 @@ · 82 unmodified lines | ||
| 83 | 83 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
| 84 | 84 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
| 85 | 85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
| 86 | −#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | |
| 87 | 86 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
| 88 | 87 | |
| 89 | 88 | #define AT91SAM9260_BASE_ECC 0xffffe800 |
| @@ -92,6 +91,7 @@ · 2 unmodified lines | ||
| 92 | 91 | #define AT91SAM9260_BASE_PIOA 0xfffff400 |
| 93 | 92 | #define AT91SAM9260_BASE_PIOB 0xfffff600 |
| 94 | 93 | #define AT91SAM9260_BASE_PIOC 0xfffff800 |
| 94 | +#define AT91SAM9260_BASE_RSTC 0xfffffd00 | |
| 95 | 95 | #define AT91SAM9260_BASE_SHDWC 0xfffffd10 |
| 96 | 96 | #define AT91SAM9260_BASE_RTT 0xfffffd20 |
| 97 | 97 | #define AT91SAM9260_BASE_PIT 0xfffffd30 |
| @@ -68,7 +68,6 @@ · 67 unmodified lines | ||
| 68 | 68 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
| 69 | 69 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
| 70 | 70 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
| 71 | −#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | |
| 72 | 71 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
| 73 | 72 | |
| 74 | 73 | #define AT91SAM9261_BASE_SMC 0xffffec00 |
| @@ -76,6 +75,7 @@ · 1 unmodified line | ||
| 76 | 75 | #define AT91SAM9261_BASE_PIOA 0xfffff400 |
| 77 | 76 | #define AT91SAM9261_BASE_PIOB 0xfffff600 |
| 78 | 77 | #define AT91SAM9261_BASE_PIOC 0xfffff800 |
| 78 | +#define AT91SAM9261_BASE_RSTC 0xfffffd00 | |
| 79 | 79 | #define AT91SAM9261_BASE_SHDWC 0xfffffd10 |
| 80 | 80 | #define AT91SAM9261_BASE_RTT 0xfffffd20 |
| 81 | 81 | #define AT91SAM9261_BASE_PIT 0xfffffd30 |
| @@ -78,7 +78,6 @@ · 77 unmodified lines | ||
| 78 | 78 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) |
| 79 | 79 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) |
| 80 | 80 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
| 81 | −#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | |
| 82 | 81 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
| 83 | 82 | |
| 84 | 83 | #define AT91SAM9263_BASE_ECC0 0xffffe000 |
| @@ -91,6 +90,7 @@ · 6 unmodified lines | ||
| 91 | 90 | #define AT91SAM9263_BASE_PIOC 0xfffff600 |
| 92 | 91 | #define AT91SAM9263_BASE_PIOD 0xfffff800 |
| 93 | 92 | #define AT91SAM9263_BASE_PIOE 0xfffffa00 |
| 93 | +#define AT91SAM9263_BASE_RSTC 0xfffffd00 | |
| 94 | 94 | #define AT91SAM9263_BASE_SHDWC 0xfffffd10 |
| 95 | 95 | #define AT91SAM9263_BASE_RTT0 0xfffffd20 |
| 96 | 96 | #define AT91SAM9263_BASE_PIT 0xfffffd30 |
| @@ -46,10 +46,10 @@ · 45 unmodified lines | ||
| 46 | 46 | #define AT91_DDRSDRC_CAS_25 (6 << 4) |
| 47 | 47 | #define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ |
| 48 | 48 | #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ |
| 49 | −#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */ | |
| 50 | −#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */ | |
| 51 | −#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */ | |
| 52 | −#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */ | |
| 49 | +#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */ | |
| 50 | +#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ | |
| 51 | +#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ | |
| 52 | +#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ | |
| 53 | 53 | |
| 54 | 54 | #define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ |
| 55 | 55 | #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ |
| @@ -59,7 +59,8 @@ · 3 unmodified lines | ||
| 59 | 59 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ |
| 60 | 60 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ |
| 61 | 61 | #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ |
| 62 | −#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */ | |
| 62 | +#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | |
| 63 | +#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ | |
| 63 | 64 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ |
| 64 | 65 | |
| 65 | 66 | #define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ |
| @@ -68,13 +69,14 @@ · 2 unmodified lines | ||
| 68 | 69 | #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ |
| 69 | 70 | #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ |
| 70 | 71 | |
| 71 | −#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */ | |
| 72 | +#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */ | |
| 72 | 73 | #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ |
| 73 | 74 | #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ |
| 74 | 75 | #define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ |
| 75 | 76 | #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ |
| 76 | 77 | |
| 77 | 78 | #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ |
| 79 | +#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */ | |
| 78 | 80 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ |
| 79 | 81 | #define AT91_DDRSDRC_LPCB_DISABLE 0 |
| 80 | 82 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 |
| @@ -92,32 +94,40 @@ · 11 unmodified lines | ||
| 92 | 94 | #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ |
| 93 | 95 | |
| 94 | 96 | #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ |
| 97 | +#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */ | |
| 95 | 98 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ |
| 96 | 99 | #define AT91_DDRSDRC_MD_SDR 0 |
| 97 | 100 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 |
| 101 | +#define AT91CAP9_DDRSDRC_MD_DDR 2 | |
| 98 | 102 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 |
| 99 | −#define AT91_DDRSDRC_MD_DDR2 6 | |
| 103 | +#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ | |
| 100 | 104 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ |
| 101 | 105 | #define AT91_DDRSDRC_DBW_32BITS (0 << 4) |
| 102 | 106 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) |
| 103 | 107 | |
| 104 | 108 | #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ |
| 109 | +#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */ | |
| 105 | 110 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ |
| 106 | 111 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ |
| 107 | 112 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ |
| 113 | +#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | |
| 114 | +#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | |
| 115 | +#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | |
| 108 | 116 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ |
| 117 | +#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | |
| 118 | +#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | |
| 109 | 119 | |
| 110 | −#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */ | |
| 120 | +#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ | |
| 111 | 121 | #define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ |
| 112 | 122 | |
| 113 | 123 | #define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ |
| 114 | 124 | |
| 115 | −#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */ | |
| 125 | +#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */ | |
| 116 | 126 | #define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ |
| 117 | 127 | #define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ |
| 118 | 128 | #define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ |
| 119 | 129 | |
| 120 | −#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */ | |
| 130 | +#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */ | |
| 121 | 131 | #define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ |
| 122 | 132 | #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ |
| 123 | 133 | |
| @@ -18,6 +18,35 @@ · 17 unmodified lines | ||
| 18 | 18 | |
| 19 | 19 | #include <mach/cpu.h> |
| 20 | 20 | |
| 21 | +#ifndef __ASSEMBLY__ | |
| 22 | +struct sam9_smc_config { | |
| 23 | + /* Setup register */ | |
| 24 | + u8 ncs_read_setup; | |
| 25 | + u8 nrd_setup; | |
| 26 | + u8 ncs_write_setup; | |
| 27 | + u8 nwe_setup; | |
| 28 | + | |
| 29 | + /* Pulse register */ | |
| 30 | + u8 ncs_read_pulse; | |
| 31 | + u8 nrd_pulse; | |
| 32 | + u8 ncs_write_pulse; | |
| 33 | + u8 nwe_pulse; | |
| 34 | + | |
| 35 | + /* Cycle register */ | |
| 36 | + u16 read_cycle; | |
| 37 | + u16 write_cycle; | |
| 38 | + | |
| 39 | + /* Mode register */ | |
| 40 | + u32 mode; | |
| 41 | + u8 tdf_cycles:4; | |
| 42 | +}; | |
| 43 | + | |
| 44 | +extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); | |
| 45 | +extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); | |
| 46 | +extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); | |
| 47 | +extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); | |
| 48 | +#endif | |
| 49 | + | |
| 21 | 50 | #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ |
| 22 | 51 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ |
| 23 | 52 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) |
| @@ -90,7 +90,6 @@ · 89 unmodified lines | ||
| 90 | 90 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
| 91 | 91 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
| 92 | 92 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
| 93 | −#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | |
| 94 | 93 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
| 95 | 94 | |
| 96 | 95 | #define AT91SAM9G45_BASE_ECC 0xffffe200 |
| @@ -102,6 +101,7 @@ · 5 unmodified lines | ||
| 102 | 101 | #define AT91SAM9G45_BASE_PIOC 0xfffff600 |
| 103 | 102 | #define AT91SAM9G45_BASE_PIOD 0xfffff800 |
| 104 | 103 | #define AT91SAM9G45_BASE_PIOE 0xfffffa00 |
| 104 | +#define AT91SAM9G45_BASE_RSTC 0xfffffd00 | |
| 105 | 105 | #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 |
| 106 | 106 | #define AT91SAM9G45_BASE_RTT 0xfffffd20 |
| 107 | 107 | #define AT91SAM9G45_BASE_PIT 0xfffffd30 |
| @@ -72,7 +72,6 @@ · 71 unmodified lines | ||
| 72 | 72 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
| 73 | 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
| 74 | 74 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
| 75 | −#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | |
| 76 | 75 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) |
| 77 | 76 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
| 78 | 77 | |
| @@ -84,6 +83,7 @@ · 5 unmodified lines | ||
| 84 | 83 | #define AT91SAM9RL_BASE_PIOB 0xfffff600 |
| 85 | 84 | #define AT91SAM9RL_BASE_PIOC 0xfffff800 |
| 86 | 85 | #define AT91SAM9RL_BASE_PIOD 0xfffffa00 |
| 86 | +#define AT91SAM9RL_BASE_RSTC 0xfffffd00 | |
| 87 | 87 | #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 |
| 88 | 88 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 |
| 89 | 89 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 |
| @@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data); · 87 unmodified lines | ||
| 88 | 88 | struct at91_usbh_data { |
| 89 | 89 | u8 ports; /* number of ports on root hub */ |
| 90 | 90 | int vbus_pin[2]; /* port power-control pin */ |
| 91 | − u8 vbus_pin_inverted; | |
| 91 | + u8 vbus_pin_active_low[2]; | |
| 92 | 92 | u8 overcurrent_supported; |
| 93 | 93 | int overcurrent_pin[2]; |
| 94 | 94 | u8 overcurrent_status[2]; |
| @@ -34,7 +34,6 @@ · 33 unmodified lines | ||
| 34 | 34 | /* |
| 35 | 35 | * Show the reason for the previous system reset. |
| 36 | 36 | */ |
| 37 | −#if defined(AT91_RSTC) | |
| 38 | 37 | |
| 39 | 38 | #include <mach/at91_rstc.h> |
| 40 | 39 | #include <mach/at91_shdwc.h> |
| @@ -58,10 +57,10 @@ static void __init show_reset_status(void) · 17 unmodified lines | ||
| 58 | 57 | char *reason, *r2 = reset; |
| 59 | 58 | u32 reset_type, wake_type; |
| 60 | 59 | |
| 61 | − if (!at91_shdwc_base) | |
| 60 | + if (!at91_shdwc_base || !at91_rstc_base) | |
| 62 | 61 | return; |
| 63 | 62 | |
| 64 | − reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; | |
| 63 | + reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; | |
| 65 | 64 | wake_type = at91_shdwc_read(AT91_SHDW_SR); |
| 66 | 65 | |
| 67 | 66 | switch (reset_type) { |
| @@ -102,10 +101,6 @@ static void __init show_reset_status(void) · 34 unmodified lines | ||
| 102 | 101 | } |
| 103 | 102 | pr_info("AT91: Starting after %s %s\n", reason, r2); |
| 104 | 103 | } |
| 105 | −#else | |
| 106 | −static void __init show_reset_status(void) {} | |
| 107 | −#endif | |
| 108 | − | |
| 109 | 104 | |
| 110 | 105 | static int at91_pm_valid_state(suspend_state_t state) |
| 111 | 106 | { |
| @@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void) · 24 unmodified lines | ||
| 25 | 25 | : : "r" (0)) |
| 26 | 26 | |
| 27 | 27 | #elif defined(CONFIG_ARCH_AT91CAP9) |
| 28 | −#include <mach/at91cap9_ddrsdr.h> | |
| 28 | +#include <mach/at91sam9_ddrsdr.h> | |
| 29 | 29 | |
| 30 | 30 | |
| 31 | 31 | static inline u32 sdram_selfrefresh_enable(void) |
| 32 | 32 | { |
| 33 | 33 | u32 saved_lpr, lpr; |
| 34 | 34 | |
| 35 | − saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); | |
| 35 | + saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR); | |
| 36 | 36 | |
| 37 | 37 | lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; |
| 38 | − at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); | |
| 38 | + at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); | |
| 39 | 39 | return saved_lpr; |
| 40 | 40 | } |
| 41 | 41 | |
| 42 | −#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) | |
| 42 | +#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr) | |
| 43 | 43 | #define wait_for_interrupt_enable() cpu_do_idle() |
| 44 | 44 | |
| 45 | 45 | #elif defined(CONFIG_ARCH_AT91SAM9G45) |
| @@ -18,9 +18,8 @@ · 17 unmodified lines | ||
| 18 | 18 | |
| 19 | 19 | #if defined(CONFIG_ARCH_AT91RM9200) |
| 20 | 20 | #include <mach/at91rm9200_mc.h> |
| 21 | −#elif defined(CONFIG_ARCH_AT91CAP9) | |
| 22 | −#include <mach/at91cap9_ddrsdr.h> | |
| 23 | −#elif defined(CONFIG_ARCH_AT91SAM9G45) | |
| 21 | +#elif defined(CONFIG_ARCH_AT91CAP9) \ | |
| 22 | + || defined(CONFIG_ARCH_AT91SAM9G45) | |
| 24 | 23 | #include <mach/at91sam9_ddrsdr.h> |
| 25 | 24 | #else |
| 26 | 25 | #include <mach/at91sam9_sdramc.h> |
| @@ -2,6 +2,7 @@ · 1 unmodified line | ||
| 2 | 2 | * linux/arch/arm/mach-at91/sam9_smc.c |
| 3 | 3 | * |
| 4 | 4 | * Copyright (C) 2008 Andrew Victor |
| 5 | + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
| 5 | 6 | * |
| 6 | 7 | * This program is free software; you can redistribute it and/or modify |
| 7 | 8 | * it under the terms of the GNU General Public License version 2 as |
| @@ -22,7 +23,22 @@ · 14 unmodified lines | ||
| 22 | 23 | |
| 23 | 24 | static void __iomem *smc_base_addr[2]; |
| 24 | 25 | |
| 25 | −static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) | |
| 26 | +static void sam9_smc_cs_write_mode(void __iomem *base, | |
| 27 | + struct sam9_smc_config *config) | |
| 28 | +{ | |
| 29 | + __raw_writel(config->mode | |
| 30 | + | AT91_SMC_TDF_(config->tdf_cycles), | |
| 31 | + base + AT91_SMC_MODE); | |
| 32 | +} | |
| 33 | + | |
| 34 | +void sam9_smc_write_mode(int id, int cs, | |
| 35 | + struct sam9_smc_config *config) | |
| 36 | +{ | |
| 37 | + sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); | |
| 38 | +} | |
| 39 | + | |
| 40 | +static void sam9_smc_cs_configure(void __iomem *base, | |
| 41 | + struct sam9_smc_config *config) | |
| 26 | 42 | { |
| 27 | 43 | |
| 28 | 44 | /* Setup register */ |
| @@ -45,16 +61,66 @@ static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_con · 16 unmodified lines | ||
| 45 | 61 | base + AT91_SMC_CYCLE); |
| 46 | 62 | |
| 47 | 63 | /* Mode register */ |
| 48 | − __raw_writel(config->mode | |
| 49 | − | AT91_SMC_TDF_(config->tdf_cycles), | |
| 50 | − base + AT91_SMC_MODE); | |
| 64 | + sam9_smc_cs_write_mode(base, config); | |
| 51 | 65 | } |
| 52 | 66 | |
| 53 | −void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) | |
| 67 | +void sam9_smc_configure(int id, int cs, | |
| 68 | + struct sam9_smc_config *config) | |
| 54 | 69 | { |
| 55 | 70 | sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); |
| 56 | 71 | } |
| 57 | 72 | |
| 73 | +static void sam9_smc_cs_read_mode(void __iomem *base, | |
| 74 | + struct sam9_smc_config *config) | |
| 75 | +{ | |
| 76 | + u32 val = __raw_readl(base + AT91_SMC_MODE); | |
| 77 | + | |
| 78 | + config->mode = (val & ~AT91_SMC_NWECYCLE); | |
| 79 | + config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; | |
| 80 | +} | |
| 81 | + | |
| 82 | +void sam9_smc_read_mode(int id, int cs, | |
| 83 | + struct sam9_smc_config *config) | |
| 84 | +{ | |
| 85 | + sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); | |
| 86 | +} | |
| 87 | + | |
| 88 | +static void sam9_smc_cs_read(void __iomem *base, | |
| 89 | + struct sam9_smc_config *config) | |
| 90 | +{ | |
| 91 | + u32 val; | |
| 92 | + | |
| 93 | + /* Setup register */ | |
| 94 | + val = __raw_readl(base + AT91_SMC_SETUP); | |
| 95 | + | |
| 96 | + config->nwe_setup = val & AT91_SMC_NWESETUP; | |
| 97 | + config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8; | |
| 98 | + config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16; | |
| 99 | + config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24; | |
| 100 | + | |
| 101 | + /* Pulse register */ | |
| 102 | + val = __raw_readl(base + AT91_SMC_PULSE); | |
| 103 | + | |
| 104 | + config->nwe_setup = val & AT91_SMC_NWEPULSE; | |
| 105 | + config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; | |
| 106 | + config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; | |
| 107 | + config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; | |
| 108 | + | |
| 109 | + /* Cycle register */ | |
| 110 | + val = __raw_readl(base + AT91_SMC_CYCLE); | |
| 111 | + | |
| 112 | + config->write_cycle = val & AT91_SMC_NWECYCLE; | |
| 113 | + config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16; | |
| 114 | + | |
| 115 | + /* Mode register */ | |
| 116 | + sam9_smc_cs_read_mode(base, config); | |
| 117 | +} | |
| 118 | + | |
| 119 | +void sam9_smc_read(int id, int cs, struct sam9_smc_config *config) | |
| 120 | +{ | |
| 121 | + sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); | |
| 122 | +} | |
| 123 | + | |
| 58 | 124 | void __init at91sam9_ioremap_smc(int id, u32 addr) |
| 59 | 125 | { |
| 60 | 126 | if (id > 1) { |
| @@ -8,27 +8,4 @@ · 7 unmodified lines | ||
| 8 | 8 | * published by the Free Software Foundation. |
| 9 | 9 | */ |
| 10 | 10 | |
| 11 | −struct sam9_smc_config { | |
| 12 | − /* Setup register */ | |
| 13 | − u8 ncs_read_setup; | |
| 14 | − u8 nrd_setup; | |
| 15 | − u8 ncs_write_setup; | |
| 16 | − u8 nwe_setup; | |
| 17 | − | |
| 18 | − /* Pulse register */ | |
| 19 | − u8 ncs_read_pulse; | |
| 20 | − u8 nrd_pulse; | |
| 21 | − u8 ncs_write_pulse; | |
| 22 | − u8 nwe_pulse; | |
| 23 | − | |
| 24 | − /* Cycle register */ | |
| 25 | − u16 read_cycle; | |
| 26 | − u16 write_cycle; | |
| 27 | − | |
| 28 | − /* Mode register */ | |
| 29 | − u32 mode; | |
| 30 | − u8 tdf_cycles:4; | |
| 31 | −}; | |
| 32 | − | |
| 33 | −extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config); | |
| 34 | 11 | extern void __init at91sam9_ioremap_smc(int id, u32 addr); |
| @@ -29,9 +29,12 @@ EXPORT_SYMBOL(at91_soc_initdata); · 28 unmodified lines | ||
| 29 | 29 | void __init at91rm9200_set_type(int type) |
| 30 | 30 | { |
| 31 | 31 | if (type == ARCH_REVISON_9200_PQFP) |
| 32 | − at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; | |
| 33 | − else | |
| 34 | 32 | at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP; |
| 33 | + else | |
| 34 | + at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; | |
| 35 | + | |
| 36 | + pr_info("AT91: filled in soc subtype: %s\n", | |
| 37 | + at91_get_soc_subtype(&at91_soc_initdata)); | |
| 35 | 38 | } |
| 36 | 39 | |
| 37 | 40 | void __init at91_init_irq_default(void) |
| @@ -281,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr) · 243 unmodified lines | ||
| 281 | 284 | pm_power_off = at91sam9_poweroff; |
| 282 | 285 | } |
| 283 | 286 | |
| 287 | +void __iomem *at91_rstc_base; | |
| 288 | + | |
| 289 | +void __init at91_ioremap_rstc(u32 base_addr) | |
| 290 | +{ | |
| 291 | + at91_rstc_base = ioremap(base_addr, 16); | |
| 292 | + if (!at91_rstc_base) | |
| 293 | + panic("Impossible to ioremap at91_rstc_base\n"); | |
| 294 | +} | |
| 295 | + | |
| 284 | 296 | void __init at91_initialize(unsigned long main_clock) |
| 285 | 297 | { |
| 286 | 298 | at91_boot_soc.ioremap_registers(); |
| @@ -194,6 +194,6 @@ MACHINE_START(BCMRING, "BCMRING") · 193 unmodified lines | ||
| 194 | 194 | .init_early = bcmring_init_early, |
| 195 | 195 | .init_irq = bcmring_init_irq, |
| 196 | 196 | .timer = &bcmring_timer, |
| 197 | − .init_machine = bcmring_init_machine | |
| 197 | + .init_machine = bcmring_init_machine, | |
| 198 | 198 | .restart = bcmring_restart, |
| 199 | 199 | MACHINE_END |
| @@ -33,17 +33,11 @@ · 32 unmodified lines | ||
| 33 | 33 | |
| 34 | 34 | #include <mach/timer.h> |
| 35 | 35 | |
| 36 | −#include <linux/mm.h> | |
| 37 | 36 | #include <linux/pfn.h> |
| 38 | 37 | #include <linux/atomic.h> |
| 39 | 38 | #include <linux/sched.h> |
| 40 | 39 | #include <mach/dma.h> |
| 41 | 40 | |
| 42 | −/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */ | |
| 43 | −/* especially since dc4 doesn't use kmalloc'd memory. */ | |
| 44 | − | |
| 45 | −#define ALLOW_MAP_OF_KMALLOC_MEMORY 0 | |
| 46 | − | |
| 47 | 41 | /* ---- Public Variables ------------------------------------------------- */ |
| 48 | 42 | |
| 49 | 43 | /* ---- Private Constants and Types -------------------------------------- */ |
| @@ -53,58 +47,18 @@ · 3 unmodified lines | ||
| 53 | 47 | #define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f) |
| 54 | 48 | #define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f) |
| 55 | 49 | |
| 56 | −#define DMA_MAP_DEBUG 0 | |
| 57 | − | |
| 58 | −#if DMA_MAP_DEBUG | |
| 59 | −# define DMA_MAP_PRINT(fmt, args...) printk("%s: " fmt, __func__, ## args) | |
| 60 | −#else | |
| 61 | −# define DMA_MAP_PRINT(fmt, args...) | |
| 62 | −#endif | |
| 63 | 50 | |
| 64 | 51 | /* ---- Private Variables ------------------------------------------------ */ |
| 65 | 52 | |
| 66 | 53 | static DMA_Global_t gDMA; |
| 67 | 54 | static struct proc_dir_entry *gDmaDir; |
| 68 | 55 | |
| 69 | −static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0); | |
| 70 | −static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0); | |
| 71 | −static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0); | |
| 72 | −static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0); | |
| 73 | − | |
| 74 | 56 | #include "dma_device.c" |
| 75 | 57 | |
| 76 | 58 | /* ---- Private Function Prototypes -------------------------------------- */ |
| 77 | 59 | |
| 78 | 60 | /* ---- Functions ------------------------------------------------------- */ |
| 79 | 61 | |
| 80 | −/****************************************************************************/ | |
| 81 | −/** | |
| 82 | −* Displays information for /proc/dma/mem-type | |
| 83 | −*/ | |
| 84 | −/****************************************************************************/ | |
| 85 | − | |
| 86 | −static int dma_proc_read_mem_type(char *buf, char **start, off_t offset, | |
| 87 | − int count, int *eof, void *data) | |
| 88 | −{ | |
| 89 | − int len = 0; | |
| 90 | − | |
| 91 | − len += sprintf(buf + len, "dma_map_mem statistics\n"); | |
| 92 | − len += | |
| 93 | − sprintf(buf + len, "coherent: %d\n", | |
| 94 | − atomic_read(&gDmaStatMemTypeCoherent)); | |
| 95 | − len += | |
| 96 | − sprintf(buf + len, "kmalloc: %d\n", | |
| 97 | − atomic_read(&gDmaStatMemTypeKmalloc)); | |
| 98 | − len += | |
| 99 | − sprintf(buf + len, "vmalloc: %d\n", | |
| 100 | − atomic_read(&gDmaStatMemTypeVmalloc)); | |
| 101 | − len += | |
| 102 | − sprintf(buf + len, "user: %d\n", | |
| 103 | − atomic_read(&gDmaStatMemTypeUser)); | |
| 104 | − | |
| 105 | − return len; | |
| 106 | −} | |
| 107 | − | |
| 108 | 62 | /****************************************************************************/ |
| 109 | 63 | /** |
| 110 | 64 | * Displays information for /proc/dma/channels |
| @@ -846,8 +800,6 @@ int dma_init(void) · 735 unmodified lines | ||
| 846 | 800 | dma_proc_read_channels, NULL); |
| 847 | 801 | create_proc_read_entry("devices", 0, gDmaDir, |
| 848 | 802 | dma_proc_read_devices, NULL); |
| 849 | − create_proc_read_entry("mem-type", 0, gDmaDir, | |
| 850 | − dma_proc_read_mem_type, NULL); | |
| 851 | 803 | } |
| 852 | 804 | |
| 853 | 805 | out: |
| @@ -1565,767 +1517,3 @@ int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. · 711 unmodified lines | ||
| 1565 | 1517 | } |
| 1566 | 1518 | |
| 1567 | 1519 | EXPORT_SYMBOL(dma_set_device_handler); |
| 1568 | − | |
| 1569 | −/****************************************************************************/ | |
| 1570 | −/** | |
| 1571 | −* Initializes a memory mapping structure | |
| 1572 | −*/ | |
| 1573 | −/****************************************************************************/ | |
| 1574 | − | |
| 1575 | −int dma_init_mem_map(DMA_MemMap_t *memMap) | |
| 1576 | −{ | |
| 1577 | − memset(memMap, 0, sizeof(*memMap)); | |
| 1578 | − | |
| 1579 | − sema_init(&memMap->lock, 1); | |
| 1580 | − | |
| 1581 | − return 0; | |
| 1582 | −} | |
| 1583 | − | |
| 1584 | −EXPORT_SYMBOL(dma_init_mem_map); | |
| 1585 | − | |
| 1586 | −/****************************************************************************/ | |
| 1587 | −/** | |
| 1588 | −* Releases any memory currently being held by a memory mapping structure. | |
| 1589 | −*/ | |
| 1590 | −/****************************************************************************/ | |
| 1591 | − | |
| 1592 | −int dma_term_mem_map(DMA_MemMap_t *memMap) | |
| 1593 | −{ | |
| 1594 | − down(&memMap->lock); /* Just being paranoid */ | |
| 1595 | − | |
| 1596 | − /* Free up any allocated memory */ | |
| 1597 | − | |
| 1598 | − up(&memMap->lock); | |
| 1599 | − memset(memMap, 0, sizeof(*memMap)); | |
| 1600 | − | |
| 1601 | − return 0; | |
| 1602 | −} | |
| 1603 | − | |
| 1604 | −EXPORT_SYMBOL(dma_term_mem_map); | |
| 1605 | − | |
| 1606 | −/****************************************************************************/ | |
| 1607 | −/** | |
| 1608 | −* Looks at a memory address and categorizes it. | |
| 1609 | −* | |
| 1610 | −* @return One of the values from the DMA_MemType_t enumeration. | |
| 1611 | −*/ | |
| 1612 | −/****************************************************************************/ | |
| 1613 | − | |
| 1614 | −DMA_MemType_t dma_mem_type(void *addr) | |
| 1615 | −{ | |
| 1616 | − unsigned long addrVal = (unsigned long)addr; | |
| 1617 | − | |
| 1618 | − if (addrVal >= CONSISTENT_BASE) { | |
| 1619 | − /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */ | |
| 1620 | − | |
| 1621 | − /* dma_alloc_xxx pages are physically and virtually contiguous */ | |
| 1622 | − | |
| 1623 | − return DMA_MEM_TYPE_DMA; | |
| 1624 | − } | |
| 1625 | − | |
| 1626 | − /* Technically, we could add one more classification. Addresses between VMALLOC_END */ | |
| 1627 | − /* and the beginning of the DMA virtual address could be considered to be I/O space. */ | |
| 1628 | − /* Right now, nobody cares about this particular classification, so we ignore it. */ | |
| 1629 | − | |
| 1630 | − if (is_vmalloc_addr(addr)) { | |
| 1631 | − /* Address comes from the vmalloc'd region. Pages are virtually */ | |
| 1632 | − /* contiguous but NOT physically contiguous */ | |
| 1633 | − | |
| 1634 | − return DMA_MEM_TYPE_VMALLOC; | |
| 1635 | − } | |
| 1636 | − | |
| 1637 | − if (addrVal >= PAGE_OFFSET) { | |
| 1638 | − /* PAGE_OFFSET is typically 0xC0000000 */ | |
| 1639 | − | |
| 1640 | − /* kmalloc'd pages are physically contiguous */ | |
| 1641 | − | |
| 1642 | − return DMA_MEM_TYPE_KMALLOC; | |
| 1643 | − } | |
| 1644 | − | |
| 1645 | − return DMA_MEM_TYPE_USER; | |
| 1646 | −} | |
| 1647 | − | |
| 1648 | −EXPORT_SYMBOL(dma_mem_type); | |
| 1649 | − | |
| 1650 | −/****************************************************************************/ | |
| 1651 | −/** | |
| 1652 | −* Looks at a memory address and determines if we support DMA'ing to/from | |
| 1653 | −* that type of memory. | |
| 1654 | −* | |
| 1655 | −* @return boolean - | |
| 1656 | −* return value != 0 means dma supported | |
| 1657 | −* return value == 0 means dma not supported | |
| 1658 | −*/ | |
| 1659 | −/****************************************************************************/ | |
| 1660 | − | |
| 1661 | −int dma_mem_supports_dma(void *addr) | |
| 1662 | −{ | |
| 1663 | − DMA_MemType_t memType = dma_mem_type(addr); | |
| 1664 | − | |
| 1665 | − return (memType == DMA_MEM_TYPE_DMA) | |
| 1666 | −#if ALLOW_MAP_OF_KMALLOC_MEMORY | |
| 1667 | − || (memType == DMA_MEM_TYPE_KMALLOC) | |
| 1668 | −#endif | |
| 1669 | − || (memType == DMA_MEM_TYPE_USER); | |
| 1670 | −} | |
| 1671 | − | |
| 1672 | −EXPORT_SYMBOL(dma_mem_supports_dma); | |
| 1673 | − | |
| 1674 | −/****************************************************************************/ | |
| 1675 | −/** | |
| 1676 | −* Maps in a memory region such that it can be used for performing a DMA. | |
| 1677 | −* | |
| 1678 | −* @return | |
| 1679 | −*/ | |
| 1680 | −/****************************************************************************/ | |
| 1681 | − | |
| 1682 | −int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 1683 | − enum dma_data_direction dir /* Direction that the mapping will be going */ | |
| 1684 | − ) { | |
| 1685 | − int rc; | |
| 1686 | − | |
| 1687 | − down(&memMap->lock); | |
| 1688 | − | |
| 1689 | − DMA_MAP_PRINT("memMap: %p\n", memMap); | |
| 1690 | − | |
| 1691 | − if (memMap->inUse) { | |
| 1692 | − printk(KERN_ERR "%s: memory map %p is already being used\n", | |
| 1693 | − __func__, memMap); | |
| 1694 | − rc = -EBUSY; | |
| 1695 | − goto out; | |
| 1696 | − } | |
| 1697 | − | |
| 1698 | − memMap->inUse = 1; | |
| 1699 | − memMap->dir = dir; | |
| 1700 | − memMap->numRegionsUsed = 0; | |
| 1701 | − | |
| 1702 | − rc = 0; | |
| 1703 | − | |
| 1704 | −out: | |
| 1705 | − | |
| 1706 | − DMA_MAP_PRINT("returning %d", rc); | |
| 1707 | − | |
| 1708 | − up(&memMap->lock); | |
| 1709 | − | |
| 1710 | − return rc; | |
| 1711 | −} | |
| 1712 | − | |
| 1713 | −EXPORT_SYMBOL(dma_map_start); | |
| 1714 | − | |
| 1715 | −/****************************************************************************/ | |
| 1716 | −/** | |
| 1717 | −* Adds a segment of memory to a memory map. Each segment is both | |
| 1718 | −* physically and virtually contiguous. | |
| 1719 | −* | |
| 1720 | −* @return 0 on success, error code otherwise. | |
| 1721 | −*/ | |
| 1722 | −/****************************************************************************/ | |
| 1723 | − | |
| 1724 | −static int dma_map_add_segment(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 1725 | − DMA_Region_t *region, /* Region that the segment belongs to */ | |
| 1726 | − void *virtAddr, /* Virtual address of the segment being added */ | |
| 1727 | − dma_addr_t physAddr, /* Physical address of the segment being added */ | |
| 1728 | − size_t numBytes /* Number of bytes of the segment being added */ | |
| 1729 | − ) { | |
| 1730 | − DMA_Segment_t *segment; | |
| 1731 | − | |
| 1732 | − DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr, | |
| 1733 | − physAddr, numBytes); | |
| 1734 | − | |
| 1735 | − /* Sanity check */ | |
| 1736 | − | |
| 1737 | − if (((unsigned long)virtAddr < (unsigned long)region->virtAddr) | |
| 1738 | − || (((unsigned long)virtAddr + numBytes)) > | |
| 1739 | − ((unsigned long)region->virtAddr + region->numBytes)) { | |
| 1740 | − printk(KERN_ERR | |
| 1741 | − "%s: virtAddr %p is outside region @ %p len: %d\n", | |
| 1742 | − __func__, virtAddr, region->virtAddr, region->numBytes); | |
| 1743 | − return -EINVAL; | |
| 1744 | − } | |
| 1745 | − | |
| 1746 | − if (region->numSegmentsUsed > 0) { | |
| 1747 | − /* Check to see if this segment is physically contiguous with the previous one */ | |
| 1748 | − | |
| 1749 | − segment = ®ion->segment[region->numSegmentsUsed - 1]; | |
| 1750 | − | |
| 1751 | − if ((segment->physAddr + segment->numBytes) == physAddr) { | |
| 1752 | − /* It is - just add on to the end */ | |
| 1753 | − | |
| 1754 | − DMA_MAP_PRINT("appending %d bytes to last segment\n", | |
| 1755 | − numBytes); | |
| 1756 | − | |
| 1757 | − segment->numBytes += numBytes; | |
| 1758 | − | |
| 1759 | − return 0; | |
| 1760 | − } | |
| 1761 | − } | |
| 1762 | − | |
| 1763 | − /* Reallocate to hold more segments, if required. */ | |
| 1764 | − | |
| 1765 | − if (region->numSegmentsUsed >= region->numSegmentsAllocated) { | |
| 1766 | − DMA_Segment_t *newSegment; | |
| 1767 | − size_t oldSize = | |
| 1768 | − region->numSegmentsAllocated * sizeof(*newSegment); | |
| 1769 | − int newAlloc = region->numSegmentsAllocated + 4; | |
| 1770 | − size_t newSize = newAlloc * sizeof(*newSegment); | |
| 1771 | − | |
| 1772 | − newSegment = kmalloc(newSize, GFP_KERNEL); | |
| 1773 | − if (newSegment == NULL) { | |
| 1774 | − return -ENOMEM; | |
| 1775 | − } | |
| 1776 | − memcpy(newSegment, region->segment, oldSize); | |
| 1777 | − memset(&((uint8_t *) newSegment)[oldSize], 0, | |
| 1778 | − newSize - oldSize); | |
| 1779 | − kfree(region->segment); | |
| 1780 | − | |
| 1781 | − region->numSegmentsAllocated = newAlloc; | |
| 1782 | − region->segment = newSegment; | |
| 1783 | − } | |
| 1784 | − | |
| 1785 | − segment = ®ion->segment[region->numSegmentsUsed]; | |
| 1786 | − region->numSegmentsUsed++; | |
| 1787 | − | |
| 1788 | − segment->virtAddr = virtAddr; | |
| 1789 | − segment->physAddr = physAddr; | |
| 1790 | − segment->numBytes = numBytes; | |
| 1791 | − | |
| 1792 | − DMA_MAP_PRINT("returning success\n"); | |
| 1793 | − | |
| 1794 | − return 0; | |
| 1795 | −} | |
| 1796 | − | |
| 1797 | −/****************************************************************************/ | |
| 1798 | −/** | |
| 1799 | −* Adds a region of memory to a memory map. Each region is virtually | |
| 1800 | −* contiguous, but not necessarily physically contiguous. | |
| 1801 | −* | |
| 1802 | −* @return 0 on success, error code otherwise. | |
| 1803 | −*/ | |
| 1804 | −/****************************************************************************/ | |
| 1805 | − | |
| 1806 | −int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 1807 | − void *mem, /* Virtual address that we want to get a map of */ | |
| 1808 | − size_t numBytes /* Number of bytes being mapped */ | |
| 1809 | − ) { | |
| 1810 | − unsigned long addr = (unsigned long)mem; | |
| 1811 | − unsigned int offset; | |
| 1812 | − int rc = 0; | |
| 1813 | − DMA_Region_t *region; | |
| 1814 | − dma_addr_t physAddr; | |
| 1815 | − | |
| 1816 | − down(&memMap->lock); | |
| 1817 | − | |
| 1818 | − DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes); | |
| 1819 | − | |
| 1820 | − if (!memMap->inUse) { | |
| 1821 | − printk(KERN_ERR "%s: Make sure you call dma_map_start first\n", | |
| 1822 | − __func__); | |
| 1823 | − rc = -EINVAL; | |
| 1824 | − goto out; | |
| 1825 | − } | |
| 1826 | − | |
| 1827 | − /* Reallocate to hold more regions. */ | |
| 1828 | − | |
| 1829 | − if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) { | |
| 1830 | − DMA_Region_t *newRegion; | |
| 1831 | − size_t oldSize = | |
| 1832 | − memMap->numRegionsAllocated * sizeof(*newRegion); | |
| 1833 | − int newAlloc = memMap->numRegionsAllocated + 4; | |
| 1834 | − size_t newSize = newAlloc * sizeof(*newRegion); | |
| 1835 | − | |
| 1836 | − newRegion = kmalloc(newSize, GFP_KERNEL); | |
| 1837 | − if (newRegion == NULL) { | |
| 1838 | − rc = -ENOMEM; | |
| 1839 | − goto out; | |
| 1840 | − } | |
| 1841 | − memcpy(newRegion, memMap->region, oldSize); | |
| 1842 | − memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize); | |
| 1843 | − | |
| 1844 | − kfree(memMap->region); | |
| 1845 | − | |
| 1846 | − memMap->numRegionsAllocated = newAlloc; | |
| 1847 | − memMap->region = newRegion; | |
| 1848 | − } | |
| 1849 | − | |
| 1850 | − region = &memMap->region[memMap->numRegionsUsed]; | |
| 1851 | − memMap->numRegionsUsed++; | |
| 1852 | − | |
| 1853 | − offset = addr & ~PAGE_MASK; | |
| 1854 | − | |
| 1855 | − region->memType = dma_mem_type(mem); | |
| 1856 | − region->virtAddr = mem; | |
| 1857 | − region->numBytes = numBytes; | |
| 1858 | − region->numSegmentsUsed = 0; | |
| 1859 | − region->numLockedPages = 0; | |
| 1860 | − region->lockedPages = NULL; | |
| 1861 | − | |
| 1862 | − switch (region->memType) { | |
| 1863 | − case DMA_MEM_TYPE_VMALLOC: | |
| 1864 | − { | |
| 1865 | − atomic_inc(&gDmaStatMemTypeVmalloc); | |
| 1866 | − | |
| 1867 | − /* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */ | |
| 1868 | − | |
| 1869 | − /* vmalloc'd pages are not physically contiguous */ | |
| 1870 | − | |
| 1871 | − rc = -EINVAL; | |
| 1872 | − break; | |
| 1873 | − } | |
| 1874 | − | |
| 1875 | − case DMA_MEM_TYPE_KMALLOC: | |
| 1876 | − { | |
| 1877 | − atomic_inc(&gDmaStatMemTypeKmalloc); | |
| 1878 | − | |
| 1879 | − /* kmalloc'd pages are physically contiguous, so they'll have exactly */ | |
| 1880 | − /* one segment */ | |
| 1881 | − | |
| 1882 | −#if ALLOW_MAP_OF_KMALLOC_MEMORY | |
| 1883 | − physAddr = | |
| 1884 | − dma_map_single(NULL, mem, numBytes, memMap->dir); | |
| 1885 | − rc = dma_map_add_segment(memMap, region, mem, physAddr, | |
| 1886 | − numBytes); | |
| 1887 | −#else | |
| 1888 | − rc = -EINVAL; | |
| 1889 | −#endif | |
| 1890 | − break; | |
| 1891 | − } | |
| 1892 | − | |
| 1893 | − case DMA_MEM_TYPE_DMA: | |
| 1894 | − { | |
| 1895 | − /* dma_alloc_xxx pages are physically contiguous */ | |
| 1896 | − | |
| 1897 | − atomic_inc(&gDmaStatMemTypeCoherent); | |
| 1898 | − | |
| 1899 | − physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset; | |
| 1900 | − | |
| 1901 | − dma_sync_single_for_cpu(NULL, physAddr, numBytes, | |
| 1902 | − memMap->dir); | |
| 1903 | − rc = dma_map_add_segment(memMap, region, mem, physAddr, | |
| 1904 | − numBytes); | |
| 1905 | − break; | |
| 1906 | − } | |
| 1907 | − | |
| 1908 | − case DMA_MEM_TYPE_USER: | |
| 1909 | − { | |
| 1910 | − size_t firstPageOffset; | |
| 1911 | − size_t firstPageSize; | |
| 1912 | − struct page **pages; | |
| 1913 | − struct task_struct *userTask; | |
| 1914 | − | |
| 1915 | − atomic_inc(&gDmaStatMemTypeUser); | |
| 1916 | − | |
| 1917 | −#if 1 | |
| 1918 | − /* If the pages are user pages, then the dma_mem_map_set_user_task function */ | |
| 1919 | − /* must have been previously called. */ | |
| 1920 | − | |
| 1921 | − if (memMap->userTask == NULL) { | |
| 1922 | − printk(KERN_ERR | |
| 1923 | − "%s: must call dma_mem_map_set_user_task when using user-mode memory\n", | |
| 1924 | − __func__); | |
| 1925 | − return -EINVAL; | |
| 1926 | − } | |
| 1927 | − | |
| 1928 | − /* User pages need to be locked. */ | |
| 1929 | − | |
| 1930 | − firstPageOffset = | |
| 1931 | − (unsigned long)region->virtAddr & (PAGE_SIZE - 1); | |
| 1932 | − firstPageSize = PAGE_SIZE - firstPageOffset; | |
| 1933 | − | |
| 1934 | − region->numLockedPages = (firstPageOffset | |
| 1935 | − + region->numBytes + | |
| 1936 | − PAGE_SIZE - 1) / PAGE_SIZE; | |
| 1937 | − pages = | |
| 1938 | − kmalloc(region->numLockedPages * | |
| 1939 | − sizeof(struct page *), GFP_KERNEL); | |
| 1940 | − | |
| 1941 | − if (pages == NULL) { | |
| 1942 | − region->numLockedPages = 0; | |
| 1943 | − return -ENOMEM; | |
| 1944 | − } | |
| 1945 | − | |
| 1946 | − userTask = memMap->userTask; | |
| 1947 | − | |
| 1948 | − down_read(&userTask->mm->mmap_sem); | |
| 1949 | − rc = get_user_pages(userTask, /* task */ | |
| 1950 | − userTask->mm, /* mm */ | |
| 1951 | − (unsigned long)region->virtAddr, /* start */ | |
| 1952 | − region->numLockedPages, /* len */ | |
| 1953 | − memMap->dir == DMA_FROM_DEVICE, /* write */ | |
| 1954 | − 0, /* force */ | |
| 1955 | − pages, /* pages (array of pointers to page) */ | |
| 1956 | − NULL); /* vmas */ | |
| 1957 | − up_read(&userTask->mm->mmap_sem); | |
| 1958 | − | |
| 1959 | − if (rc != region->numLockedPages) { | |
| 1960 | − kfree(pages); | |
| 1961 | − region->numLockedPages = 0; | |
| 1962 | − | |
| 1963 | − if (rc >= 0) { | |
| 1964 | − rc = -EINVAL; | |
| 1965 | − } | |
| 1966 | − } else { | |
| 1967 | − uint8_t *virtAddr = region->virtAddr; | |
| 1968 | − size_t bytesRemaining; | |
| 1969 | − int pageIdx; | |
| 1970 | − | |
| 1971 | − rc = 0; /* Since get_user_pages returns +ve number */ | |
| 1972 | − | |
| 1973 | − region->lockedPages = pages; | |
| 1974 | − | |
| 1975 | − /* We've locked the user pages. Now we need to walk them and figure */ | |
| 1976 | − /* out the physical addresses. */ | |
| 1977 | − | |
| 1978 | − /* The first page may be partial */ | |
| 1979 | − | |
| 1980 | − dma_map_add_segment(memMap, | |
| 1981 | − region, | |
| 1982 | − virtAddr, | |
| 1983 | − PFN_PHYS(page_to_pfn | |
| 1984 | − (pages[0])) + | |
| 1985 | − firstPageOffset, | |
| 1986 | − firstPageSize); | |
| 1987 | − | |
| 1988 | − virtAddr += firstPageSize; | |
| 1989 | − bytesRemaining = | |
| 1990 | − region->numBytes - firstPageSize; | |
| 1991 | − | |
| 1992 | − for (pageIdx = 1; | |
| 1993 | − pageIdx < region->numLockedPages; | |
| 1994 | − pageIdx++) { | |
| 1995 | − size_t bytesThisPage = | |
| 1996 | − (bytesRemaining > | |
| 1997 | − PAGE_SIZE ? PAGE_SIZE : | |
| 1998 | − bytesRemaining); | |
| 1999 | − | |
| 2000 | − DMA_MAP_PRINT | |
| 2001 | − ("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n", | |
| 2002 | − pageIdx, pages[pageIdx], | |
| 2003 | − page_to_pfn(pages[pageIdx]), | |
| 2004 | − PFN_PHYS(page_to_pfn | |
| 2005 | − (pages[pageIdx]))); | |
| 2006 | − | |
| 2007 | − dma_map_add_segment(memMap, | |
| 2008 | − region, | |
| 2009 | − virtAddr, | |
| 2010 | − PFN_PHYS(page_to_pfn | |
| 2011 | − (pages | |
| 2012 | − [pageIdx])), | |
| 2013 | − bytesThisPage); | |
| 2014 | − | |
| 2015 | − virtAddr += bytesThisPage; | |
| 2016 | − bytesRemaining -= bytesThisPage; | |
| 2017 | − } | |
| 2018 | − } | |
| 2019 | −#else | |
| 2020 | − printk(KERN_ERR | |
| 2021 | − "%s: User mode pages are not yet supported\n", | |
| 2022 | − __func__); | |
| 2023 | − | |
| 2024 | − /* user pages are not physically contiguous */ | |
| 2025 | − | |
| 2026 | − rc = -EINVAL; | |
| 2027 | −#endif | |
| 2028 | − break; | |
| 2029 | − } | |
| 2030 | − | |
| 2031 | − default: | |
| 2032 | − { | |
| 2033 | − printk(KERN_ERR "%s: Unsupported memory type: %d\n", | |
| 2034 | − __func__, region->memType); | |
| 2035 | − | |
| 2036 | − rc = -EINVAL; | |
| 2037 | − break; | |
| 2038 | − } | |
| 2039 | − } | |
| 2040 | − | |
| 2041 | − if (rc != 0) { | |
| 2042 | − memMap->numRegionsUsed--; | |
| 2043 | − } | |
| 2044 | − | |
| 2045 | −out: | |
| 2046 | − | |
| 2047 | − DMA_MAP_PRINT("returning %d\n", rc); | |
| 2048 | − | |
| 2049 | − up(&memMap->lock); | |
| 2050 | − | |
| 2051 | − return rc; | |
| 2052 | −} | |
| 2053 | − | |
| 2054 | −EXPORT_SYMBOL(dma_map_add_segment); | |
| 2055 | − | |
| 2056 | −/****************************************************************************/ | |
| 2057 | −/** | |
| 2058 | −* Maps in a memory region such that it can be used for performing a DMA. | |
| 2059 | −* | |
| 2060 | −* @return 0 on success, error code otherwise. | |
| 2061 | −*/ | |
| 2062 | −/****************************************************************************/ | |
| 2063 | − | |
| 2064 | −int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 2065 | − void *mem, /* Virtual address that we want to get a map of */ | |
| 2066 | − size_t numBytes, /* Number of bytes being mapped */ | |
| 2067 | − enum dma_data_direction dir /* Direction that the mapping will be going */ | |
| 2068 | − ) { | |
| 2069 | − int rc; | |
| 2070 | − | |
| 2071 | − rc = dma_map_start(memMap, dir); | |
| 2072 | − if (rc == 0) { | |
| 2073 | − rc = dma_map_add_region(memMap, mem, numBytes); | |
| 2074 | − if (rc < 0) { | |
| 2075 | − /* Since the add fails, this function will fail, and the caller won't */ | |
| 2076 | − /* call unmap, so we need to do it here. */ | |
| 2077 | − | |
| 2078 | − dma_unmap(memMap, 0); | |
| 2079 | − } | |
| 2080 | − } | |
| 2081 | − | |
| 2082 | − return rc; | |
| 2083 | −} | |
| 2084 | − | |
| 2085 | −EXPORT_SYMBOL(dma_map_mem); | |
| 2086 | − | |
| 2087 | −/****************************************************************************/ | |
| 2088 | −/** | |
| 2089 | −* Setup a descriptor ring for a given memory map. | |
| 2090 | −* | |
| 2091 | −* It is assumed that the descriptor ring has already been initialized, and | |
| 2092 | −* this routine will only reallocate a new descriptor ring if the existing | |
| 2093 | −* one is too small. | |
| 2094 | −* | |
| 2095 | −* @return 0 on success, error code otherwise. | |
| 2096 | −*/ | |
| 2097 | −/****************************************************************************/ | |
| 2098 | − | |
| 2099 | −int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */ | |
| 2100 | − DMA_MemMap_t *memMap, /* Memory map that will be used */ | |
| 2101 | − dma_addr_t devPhysAddr /* Physical address of device */ | |
| 2102 | − ) { | |
| 2103 | − int rc; | |
| 2104 | − int numDescriptors; | |
| 2105 | − DMA_DeviceAttribute_t *devAttr; | |
| 2106 | − DMA_Region_t *region; | |
| 2107 | − DMA_Segment_t *segment; | |
| 2108 | − dma_addr_t srcPhysAddr; | |
| 2109 | − dma_addr_t dstPhysAddr; | |
| 2110 | − int regionIdx; | |
| 2111 | − int segmentIdx; | |
| 2112 | − | |
| 2113 | − devAttr = &DMA_gDeviceAttribute[dev]; | |
| 2114 | − | |
| 2115 | − down(&memMap->lock); | |
| 2116 | − | |
| 2117 | − /* Figure out how many descriptors we need */ | |
| 2118 | − | |
| 2119 | − numDescriptors = 0; | |
| 2120 | − for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | |
| 2121 | − region = &memMap->region[regionIdx]; | |
| 2122 | − | |
| 2123 | − for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | |
| 2124 | − segmentIdx++) { | |
| 2125 | − segment = ®ion->segment[segmentIdx]; | |
| 2126 | − | |
| 2127 | − if (memMap->dir == DMA_TO_DEVICE) { | |
| 2128 | − srcPhysAddr = segment->physAddr; | |
| 2129 | − dstPhysAddr = devPhysAddr; | |
| 2130 | − } else { | |
| 2131 | − srcPhysAddr = devPhysAddr; | |
| 2132 | − dstPhysAddr = segment->physAddr; | |
| 2133 | − } | |
| 2134 | − | |
| 2135 | − rc = | |
| 2136 | − dma_calculate_descriptor_count(dev, srcPhysAddr, | |
| 2137 | − dstPhysAddr, | |
| 2138 | − segment-> | |
| 2139 | − numBytes); | |
| 2140 | − if (rc < 0) { | |
| 2141 | − printk(KERN_ERR | |
| 2142 | − "%s: dma_calculate_descriptor_count failed: %d\n", | |
| 2143 | − __func__, rc); | |
| 2144 | − goto out; | |
| 2145 | − } | |
| 2146 | − numDescriptors += rc; | |
| 2147 | − } | |
| 2148 | − } | |
| 2149 | − | |
| 2150 | − /* Adjust the size of the ring, if it isn't big enough */ | |
| 2151 | − | |
| 2152 | − if (numDescriptors > devAttr->ring.descriptorsAllocated) { | |
| 2153 | − dma_free_descriptor_ring(&devAttr->ring); | |
| 2154 | − rc = | |
| 2155 | − dma_alloc_descriptor_ring(&devAttr->ring, | |
| 2156 | − numDescriptors); | |
| 2157 | − if (rc < 0) { | |
| 2158 | − printk(KERN_ERR | |
| 2159 | − "%s: dma_alloc_descriptor_ring failed: %d\n", | |
| 2160 | − __func__, rc); | |
| 2161 | − goto out; | |
| 2162 | − } | |
| 2163 | − } else { | |
| 2164 | − rc = | |
| 2165 | − dma_init_descriptor_ring(&devAttr->ring, | |
| 2166 | − numDescriptors); | |
| 2167 | − if (rc < 0) { | |
| 2168 | − printk(KERN_ERR | |
| 2169 | − "%s: dma_init_descriptor_ring failed: %d\n", | |
| 2170 | − __func__, rc); | |
| 2171 | − goto out; | |
| 2172 | − } | |
| 2173 | − } | |
| 2174 | − | |
| 2175 | − /* Populate the descriptors */ | |
| 2176 | − | |
| 2177 | − for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | |
| 2178 | − region = &memMap->region[regionIdx]; | |
| 2179 | − | |
| 2180 | − for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | |
| 2181 | − segmentIdx++) { | |
| 2182 | − segment = ®ion->segment[segmentIdx]; | |
| 2183 | − | |
| 2184 | − if (memMap->dir == DMA_TO_DEVICE) { | |
| 2185 | − srcPhysAddr = segment->physAddr; | |
| 2186 | − dstPhysAddr = devPhysAddr; | |
| 2187 | − } else { | |
| 2188 | − srcPhysAddr = devPhysAddr; | |
| 2189 | − dstPhysAddr = segment->physAddr; | |
| 2190 | − } | |
| 2191 | − | |
| 2192 | − rc = | |
| 2193 | − dma_add_descriptors(&devAttr->ring, dev, | |
| 2194 | − srcPhysAddr, dstPhysAddr, | |
| 2195 | − segment->numBytes); | |
| 2196 | − if (rc < 0) { | |
| 2197 | − printk(KERN_ERR | |
| 2198 | − "%s: dma_add_descriptors failed: %d\n", | |
| 2199 | − __func__, rc); | |
| 2200 | − goto out; | |
| 2201 | − } | |
| 2202 | − } | |
| 2203 | − } | |
| 2204 | − | |
| 2205 | − rc = 0; | |
| 2206 | − | |
| 2207 | −out: | |
| 2208 | − | |
| 2209 | − up(&memMap->lock); | |
| 2210 | − return rc; | |
| 2211 | −} | |
| 2212 | − | |
| 2213 | −EXPORT_SYMBOL(dma_map_create_descriptor_ring); | |
| 2214 | − | |
| 2215 | −/****************************************************************************/ | |
| 2216 | −/** | |
| 2217 | −* Maps in a memory region such that it can be used for performing a DMA. | |
| 2218 | −* | |
| 2219 | −* @return | |
| 2220 | −*/ | |
| 2221 | −/****************************************************************************/ | |
| 2222 | − | |
| 2223 | −int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 2224 | − int dirtied /* non-zero if any of the pages were modified */ | |
| 2225 | − ) { | |
| 2226 | − | |
| 2227 | − int rc = 0; | |
| 2228 | − int regionIdx; | |
| 2229 | − int segmentIdx; | |
| 2230 | − DMA_Region_t *region; | |
| 2231 | − DMA_Segment_t *segment; | |
| 2232 | − | |
| 2233 | − down(&memMap->lock); | |
| 2234 | − | |
| 2235 | − for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | |
| 2236 | − region = &memMap->region[regionIdx]; | |
| 2237 | − | |
| 2238 | − for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | |
| 2239 | − segmentIdx++) { | |
| 2240 | − segment = ®ion->segment[segmentIdx]; | |
| 2241 | − | |
| 2242 | − switch (region->memType) { | |
| 2243 | − case DMA_MEM_TYPE_VMALLOC: | |
| 2244 | − { | |
| 2245 | − printk(KERN_ERR | |
| 2246 | − "%s: vmalloc'd pages are not yet supported\n", | |
| 2247 | − __func__); | |
| 2248 | − rc = -EINVAL; | |
| 2249 | − goto out; | |
| 2250 | − } | |
| 2251 | − | |
| 2252 | − case DMA_MEM_TYPE_KMALLOC: | |
| 2253 | − { | |
| 2254 | −#if ALLOW_MAP_OF_KMALLOC_MEMORY | |
| 2255 | − dma_unmap_single(NULL, | |
| 2256 | − segment->physAddr, | |
| 2257 | − segment->numBytes, | |
| 2258 | − memMap->dir); | |
| 2259 | −#endif | |
| 2260 | − break; | |
| 2261 | − } | |
| 2262 | − | |
| 2263 | − case DMA_MEM_TYPE_DMA: | |
| 2264 | − { | |
| 2265 | − dma_sync_single_for_cpu(NULL, | |
| 2266 | − segment-> | |
| 2267 | − physAddr, | |
| 2268 | − segment-> | |
| 2269 | − numBytes, | |
| 2270 | − memMap->dir); | |
| 2271 | − break; | |
| 2272 | − } | |
| 2273 | − | |
| 2274 | − case DMA_MEM_TYPE_USER: | |
| 2275 | − { | |
| 2276 | − /* Nothing to do here. */ | |
| 2277 | − | |
| 2278 | − break; | |
| 2279 | − } | |
| 2280 | − | |
| 2281 | − default: | |
| 2282 | − { | |
| 2283 | − printk(KERN_ERR | |
| 2284 | − "%s: Unsupported memory type: %d\n", | |
| 2285 | − __func__, region->memType); | |
| 2286 | − rc = -EINVAL; | |
| 2287 | − goto out; | |
| 2288 | − } | |
| 2289 | − } | |
| 2290 | − | |
| 2291 | − segment->virtAddr = NULL; | |
| 2292 | − segment->physAddr = 0; | |
| 2293 | − segment->numBytes = 0; | |
| 2294 | − } | |
| 2295 | − | |
| 2296 | − if (region->numLockedPages > 0) { | |
| 2297 | − int pageIdx; | |
| 2298 | − | |
| 2299 | − /* Some user pages were locked. We need to go and unlock them now. */ | |
| 2300 | − | |
| 2301 | − for (pageIdx = 0; pageIdx < region->numLockedPages; | |
| 2302 | − pageIdx++) { | |
| 2303 | − struct page *page = | |
| 2304 | − region->lockedPages[pageIdx]; | |
| 2305 | − | |
| 2306 | − if (memMap->dir == DMA_FROM_DEVICE) { | |
| 2307 | − SetPageDirty(page); | |
| 2308 | − } | |
| 2309 | − page_cache_release(page); | |
| 2310 | − } | |
| 2311 | − kfree(region->lockedPages); | |
| 2312 | − region->numLockedPages = 0; | |
| 2313 | − region->lockedPages = NULL; | |
| 2314 | − } | |
| 2315 | − | |
| 2316 | − region->memType = DMA_MEM_TYPE_NONE; | |
| 2317 | − region->virtAddr = NULL; | |
| 2318 | − region->numBytes = 0; | |
| 2319 | − region->numSegmentsUsed = 0; | |
| 2320 | − } | |
| 2321 | − memMap->userTask = NULL; | |
| 2322 | − memMap->numRegionsUsed = 0; | |
| 2323 | − memMap->inUse = 0; | |
| 2324 | − | |
| 2325 | −out: | |
| 2326 | − up(&memMap->lock); | |
| 2327 | − | |
| 2328 | − return rc; | |
| 2329 | −} | |
| 2330 | − | |
| 2331 | −EXPORT_SYMBOL(dma_unmap); | |
| @@ -26,15 +26,9 @@ · 25 unmodified lines | ||
| 26 | 26 | /* ---- Include Files ---------------------------------------------------- */ |
| 27 | 27 | |
| 28 | 28 | #include <linux/kernel.h> |
| 29 | −#include <linux/wait.h> | |
| 30 | 29 | #include <linux/semaphore.h> |
| 31 | 30 | #include <csp/dmacHw.h> |
| 32 | 31 | #include <mach/timer.h> |
| 33 | −#include <linux/scatterlist.h> | |
| 34 | −#include <linux/dma-mapping.h> | |
| 35 | −#include <linux/mm.h> | |
| 36 | −#include <linux/vmalloc.h> | |
| 37 | −#include <linux/pagemap.h> | |
| 38 | 32 | |
| 39 | 33 | /* ---- Constants and Types ---------------------------------------------- */ |
| 40 | 34 | |
| @@ -111,78 +105,6 @@ typedef struct { · 70 unmodified lines | ||
| 111 | 105 | |
| 112 | 106 | } DMA_DescriptorRing_t; |
| 113 | 107 | |
| 114 | −/**************************************************************************** | |
| 115 | −* | |
| 116 | −* The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup | |
| 117 | −* DMA chains from a variety of memory sources. | |
| 118 | −* | |
| 119 | −*****************************************************************************/ | |
| 120 | − | |
| 121 | −#define DMA_MEM_MAP_MIN_SIZE 4096 /* Pages less than this size are better */ | |
| 122 | − /* off not being DMA'd. */ | |
| 123 | − | |
| 124 | −typedef enum { | |
| 125 | − DMA_MEM_TYPE_NONE, /* Not a valid setting */ | |
| 126 | − DMA_MEM_TYPE_VMALLOC, /* Memory came from vmalloc call */ | |
| 127 | − DMA_MEM_TYPE_KMALLOC, /* Memory came from kmalloc call */ | |
| 128 | − DMA_MEM_TYPE_DMA, /* Memory came from dma_alloc_xxx call */ | |
| 129 | − DMA_MEM_TYPE_USER, /* Memory came from user space. */ | |
| 130 | − | |
| 131 | −} DMA_MemType_t; | |
| 132 | − | |
| 133 | −/* A segment represents a physically and virtually contiguous chunk of memory. */ | |
| 134 | −/* i.e. each segment can be DMA'd */ | |
| 135 | −/* A user of the DMA code will add memory regions. Each region may need to be */ | |
| 136 | −/* represented by one or more segments. */ | |
| 137 | − | |
| 138 | −typedef struct { | |
| 139 | − void *virtAddr; /* Virtual address used for this segment */ | |
| 140 | − dma_addr_t physAddr; /* Physical address this segment maps to */ | |
| 141 | − size_t numBytes; /* Size of the segment, in bytes */ | |
| 142 | − | |
| 143 | −} DMA_Segment_t; | |
| 144 | − | |
| 145 | −/* A region represents a virtually contiguous chunk of memory, which may be */ | |
| 146 | −/* made up of multiple segments. */ | |
| 147 | − | |
| 148 | −typedef struct { | |
| 149 | − DMA_MemType_t memType; | |
| 150 | − void *virtAddr; | |
| 151 | − size_t numBytes; | |
| 152 | − | |
| 153 | − /* Each region (virtually contiguous) consists of one or more segments. Each */ | |
| 154 | − /* segment is virtually and physically contiguous. */ | |
| 155 | − | |
| 156 | − int numSegmentsUsed; | |
| 157 | − int numSegmentsAllocated; | |
| 158 | − DMA_Segment_t *segment; | |
| 159 | − | |
| 160 | − /* When a region corresponds to user memory, we need to lock all of the pages */ | |
| 161 | − /* down before we can figure out the physical addresses. The lockedPage array contains */ | |
| 162 | − /* the pages that were locked, and which subsequently need to be unlocked once the */ | |
| 163 | − /* memory is unmapped. */ | |
| 164 | − | |
| 165 | − unsigned numLockedPages; | |
| 166 | − struct page **lockedPages; | |
| 167 | − | |
| 168 | −} DMA_Region_t; | |
| 169 | − | |
| 170 | −typedef struct { | |
| 171 | − int inUse; /* Is this mapping currently being used? */ | |
| 172 | − struct semaphore lock; /* Acquired when using this structure */ | |
| 173 | − enum dma_data_direction dir; /* Direction this transfer is intended for */ | |
| 174 | − | |
| 175 | − /* In the event that we're mapping user memory, we need to know which task */ | |
| 176 | − /* the memory is for, so that we can obtain the correct mm locks. */ | |
| 177 | − | |
| 178 | − struct task_struct *userTask; | |
| 179 | − | |
| 180 | − int numRegionsUsed; | |
| 181 | − int numRegionsAllocated; | |
| 182 | − DMA_Region_t *region; | |
| 183 | − | |
| 184 | −} DMA_MemMap_t; | |
| 185 | − | |
| 186 | 108 | /**************************************************************************** |
| 187 | 109 | * |
| 188 | 110 | * The DMA_DeviceAttribute_t contains information which describes a |
| @@ -568,124 +490,6 @@ int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */ · 379 unmodified lines | ||
| 568 | 490 | size_t numBytes /* Number of bytes in each destination buffer */ |
| 569 | 491 | ); |
| 570 | 492 | |
| 571 | −/****************************************************************************/ | |
| 572 | −/** | |
| 573 | −* Initializes a DMA_MemMap_t data structure | |
| 574 | −*/ | |
| 575 | −/****************************************************************************/ | |
| 576 | − | |
| 577 | −int dma_init_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */ | |
| 578 | − ); | |
| 579 | − | |
| 580 | −/****************************************************************************/ | |
| 581 | −/** | |
| 582 | −* Releases any memory currently being held by a memory mapping structure. | |
| 583 | −*/ | |
| 584 | −/****************************************************************************/ | |
| 585 | − | |
| 586 | −int dma_term_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */ | |
| 587 | − ); | |
| 588 | − | |
| 589 | −/****************************************************************************/ | |
| 590 | −/** | |
| 591 | −* Looks at a memory address and categorizes it. | |
| 592 | −* | |
| 593 | −* @return One of the values from the DMA_MemType_t enumeration. | |
| 594 | −*/ | |
| 595 | −/****************************************************************************/ | |
| 596 | − | |
| 597 | −DMA_MemType_t dma_mem_type(void *addr); | |
| 598 | − | |
| 599 | −/****************************************************************************/ | |
| 600 | −/** | |
| 601 | −* Sets the process (aka userTask) associated with a mem map. This is | |
| 602 | −* required if user-mode segments will be added to the mapping. | |
| 603 | −*/ | |
| 604 | −/****************************************************************************/ | |
| 605 | − | |
| 606 | −static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap, | |
| 607 | − struct task_struct *task) | |
| 608 | −{ | |
| 609 | − memMap->userTask = task; | |
| 610 | −} | |
| 611 | − | |
| 612 | −/****************************************************************************/ | |
| 613 | −/** | |
| 614 | −* Looks at a memory address and determines if we support DMA'ing to/from | |
| 615 | −* that type of memory. | |
| 616 | −* | |
| 617 | −* @return boolean - | |
| 618 | −* return value != 0 means dma supported | |
| 619 | −* return value == 0 means dma not supported | |
| 620 | −*/ | |
| 621 | −/****************************************************************************/ | |
| 622 | − | |
| 623 | −int dma_mem_supports_dma(void *addr); | |
| 624 | − | |
| 625 | −/****************************************************************************/ | |
| 626 | −/** | |
| 627 | −* Initializes a memory map for use. Since this function acquires a | |
| 628 | −* sempaphore within the memory map, it is VERY important that dma_unmap | |
| 629 | −* be called when you're finished using the map. | |
| 630 | −*/ | |
| 631 | −/****************************************************************************/ | |
| 632 | − | |
| 633 | −int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 634 | − enum dma_data_direction dir /* Direction that the mapping will be going */ | |
| 635 | − ); | |
| 636 | − | |
| 637 | −/****************************************************************************/ | |
| 638 | −/** | |
| 639 | −* Adds a segment of memory to a memory map. | |
| 640 | −* | |
| 641 | −* @return 0 on success, error code otherwise. | |
| 642 | −*/ | |
| 643 | −/****************************************************************************/ | |
| 644 | − | |
| 645 | −int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 646 | − void *mem, /* Virtual address that we want to get a map of */ | |
| 647 | − size_t numBytes /* Number of bytes being mapped */ | |
| 648 | − ); | |
| 649 | − | |
| 650 | −/****************************************************************************/ | |
| 651 | −/** | |
| 652 | −* Creates a descriptor ring from a memory mapping. | |
| 653 | −* | |
| 654 | −* @return 0 on success, error code otherwise. | |
| 655 | −*/ | |
| 656 | −/****************************************************************************/ | |
| 657 | − | |
| 658 | −int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */ | |
| 659 | − DMA_MemMap_t *memMap, /* Memory map that will be used */ | |
| 660 | − dma_addr_t devPhysAddr /* Physical address of device */ | |
| 661 | − ); | |
| 662 | − | |
| 663 | −/****************************************************************************/ | |
| 664 | −/** | |
| 665 | −* Maps in a memory region such that it can be used for performing a DMA. | |
| 666 | −* | |
| 667 | −* @return | |
| 668 | −*/ | |
| 669 | −/****************************************************************************/ | |
| 670 | − | |
| 671 | −int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 672 | − void *addr, /* Virtual address that we want to get a map of */ | |
| 673 | − size_t count, /* Number of bytes being mapped */ | |
| 674 | − enum dma_data_direction dir /* Direction that the mapping will be going */ | |
| 675 | − ); | |
| 676 | − | |
| 677 | −/****************************************************************************/ | |
| 678 | −/** | |
| 679 | −* Maps in a memory region such that it can be used for performing a DMA. | |
| 680 | −* | |
| 681 | −* @return | |
| 682 | −*/ | |
| 683 | −/****************************************************************************/ | |
| 684 | − | |
| 685 | −int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */ | |
| 686 | − int dirtied /* non-zero if any of the pages were modified */ | |
| 687 | − ); | |
| 688 | − | |
| 689 | 493 | /****************************************************************************/ |
| 690 | 494 | /** |
| 691 | 495 | * Initiates a transfer when the descriptors have already been setup. |
| @@ -44,7 +44,7 @@ · 43 unmodified lines | ||
| 44 | 44 | #include <mach/aemif.h> |
| 45 | 45 | #include <mach/spi.h> |
| 46 | 46 | |
| 47 | −#define DA850_EVM_PHY_ID "0:00" | |
| 47 | +#define DA850_EVM_PHY_ID "davinci_mdio-0:00" | |
| 48 | 48 | #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) |
| 49 | 49 | #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) |
| 50 | 50 | |
| @@ -54,7 +54,7 @@ static inline int have_tvp7002(void) · 53 unmodified lines | ||
| 54 | 54 | return 0; |
| 55 | 55 | } |
| 56 | 56 | |
| 57 | −#define DM365_EVM_PHY_ID "0:01" | |
| 57 | +#define DM365_EVM_PHY_ID "davinci_mdio-0:01" | |
| 58 | 58 | /* |
| 59 | 59 | * A MAX-II CPLD is used for various board control functions. |
| 60 | 60 | */ |
| @@ -40,7 +40,7 @@ · 39 unmodified lines | ||
| 40 | 40 | #include <mach/usb.h> |
| 41 | 41 | #include <mach/aemif.h> |
| 42 | 42 | |
| 43 | −#define DM644X_EVM_PHY_ID "0:01" | |
| 43 | +#define DM644X_EVM_PHY_ID "davinci_mdio-0:01" | |
| 44 | 44 | #define LXT971_PHY_ID (0x001378e2) |
| 45 | 45 | #define LXT971_PHY_MASK (0xfffffff0) |
| 46 | 46 | |
| @@ -736,7 +736,7 @@ static struct davinci_uart_config uart_config __initdata = { · 735 unmodified lines | ||
| 736 | 736 | .enabled_uarts = (1 << 0), |
| 737 | 737 | }; |
| 738 | 738 | |
| 739 | −#define DM646X_EVM_PHY_ID "0:01" | |
| 739 | +#define DM646X_EVM_PHY_ID "davinci_mdio-0:01" | |
| 740 | 740 | /* |
| 741 | 741 | * The following EDMA channels/slots are not being used by drivers (for |
| 742 | 742 | * example: Timer, GPIO, UART events etc) on dm646x, hence they are being |
| @@ -39,7 +39,7 @@ · 38 unmodified lines | ||
| 39 | 39 | #include <mach/mmc.h> |
| 40 | 40 | #include <mach/usb.h> |
| 41 | 41 | |
| 42 | −#define NEUROS_OSD2_PHY_ID "0:01" | |
| 42 | +#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01" | |
| 43 | 43 | #define LXT971_PHY_ID 0x001378e2 |
| 44 | 44 | #define LXT971_PHY_MASK 0xfffffff0 |
| 45 | 45 | |
| @@ -21,7 +21,7 @@ · 20 unmodified lines | ||
| 21 | 21 | #include <mach/da8xx.h> |
| 22 | 22 | #include <mach/mux.h> |
| 23 | 23 | |
| 24 | −#define HAWKBOARD_PHY_ID "0:07" | |
| 24 | +#define HAWKBOARD_PHY_ID "davinci_mdio-0:07" | |
| 25 | 25 | #define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12) |
| 26 | 26 | #define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13) |
| 27 | 27 | |
| @@ -42,7 +42,7 @@ · 41 unmodified lines | ||
| 42 | 42 | #include <mach/mux.h> |
| 43 | 43 | #include <mach/usb.h> |
| 44 | 44 | |
| 45 | −#define SFFSDR_PHY_ID "0:01" | |
| 45 | +#define SFFSDR_PHY_ID "davinci_mdio-0:01" | |
| 46 | 46 | static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { |
| 47 | 47 | /* U-Boot Environment: Block 0 |
| 48 | 48 | * UBL: Block 1 |
| @@ -153,34 +153,6 @@ static struct clk pll1_sysclk3 = { · 152 unmodified lines | ||
| 153 | 153 | .div_reg = PLLDIV3, |
| 154 | 154 | }; |
| 155 | 155 | |
| 156 | −static struct clk pll1_sysclk4 = { | |
| 157 | − .name = "pll1_sysclk4", | |
| 158 | − .parent = &pll1_clk, | |
| 159 | − .flags = CLK_PLL, | |
| 160 | − .div_reg = PLLDIV4, | |
| 161 | −}; | |
| 162 | − | |
| 163 | −static struct clk pll1_sysclk5 = { | |
| 164 | − .name = "pll1_sysclk5", | |
| 165 | − .parent = &pll1_clk, | |
| 166 | − .flags = CLK_PLL, | |
| 167 | − .div_reg = PLLDIV5, | |
| 168 | −}; | |
| 169 | − | |
| 170 | −static struct clk pll1_sysclk6 = { | |
| 171 | − .name = "pll0_sysclk6", | |
| 172 | − .parent = &pll0_clk, | |
| 173 | − .flags = CLK_PLL, | |
| 174 | − .div_reg = PLLDIV6, | |
| 175 | −}; | |
| 176 | − | |
| 177 | −static struct clk pll1_sysclk7 = { | |
| 178 | − .name = "pll1_sysclk7", | |
| 179 | − .parent = &pll1_clk, | |
| 180 | − .flags = CLK_PLL, | |
| 181 | − .div_reg = PLLDIV7, | |
| 182 | −}; | |
| 183 | − | |
| 184 | 156 | static struct clk i2c0_clk = { |
| 185 | 157 | .name = "i2c0", |
| 186 | 158 | .parent = &pll0_aux_clk, |
| @@ -397,10 +369,6 @@ static struct clk_lookup da850_clks[] = { · 210 unmodified lines | ||
| 397 | 369 | CLK(NULL, "pll1_aux", &pll1_aux_clk), |
| 398 | 370 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), |
| 399 | 371 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), |
| 400 | − CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), | |
| 401 | − CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), | |
| 402 | − CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), | |
| 403 | − CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), | |
| 404 | 372 | CLK("i2c_davinci.1", NULL, &i2c0_clk), |
| 405 | 373 | CLK(NULL, "timer0", &timerp64_0_clk), |
| 406 | 374 | CLK("watchdog", NULL, &timerp64_1_clk), |
| @@ -28,6 +28,7 @@ · 27 unmodified lines | ||
| 28 | 28 | #include <asm/mach/arch.h> |
| 29 | 29 | #include <linux/irq.h> |
| 30 | 30 | #include <plat/time.h> |
| 31 | +#include <plat/ehci-orion.h> | |
| 31 | 32 | #include <plat/common.h> |
| 32 | 33 | #include <plat/addr-map.h> |
| 33 | 34 | #include "common.h" |
| @@ -71,7 +72,7 @@ void __init dove_map_io(void) · 37 unmodified lines | ||
| 71 | 72 | ****************************************************************************/ |
| 72 | 73 | void __init dove_ehci0_init(void) |
| 73 | 74 | { |
| 74 | − orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); | |
| 75 | + orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); | |
| 75 | 76 | } |
| 76 | 77 | |
| 77 | 78 | /***************************************************************************** |
| @@ -37,7 +37,7 @@ · 36 unmodified lines | ||
| 37 | 37 | */ |
| 38 | 38 | struct ep93xx_dma_data { |
| 39 | 39 | int port; |
| 40 | − enum dma_data_direction direction; | |
| 40 | + enum dma_transfer_direction direction; | |
| 41 | 41 | const char *name; |
| 42 | 42 | }; |
| 43 | 43 | |
| @@ -80,14 +80,14 @@ static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan) · 36 unmodified lines | ||
| 80 | 80 | * channel supports given DMA direction. Only M2P channels have such |
| 81 | 81 | * limitation, for M2M channels the direction is configurable. |
| 82 | 82 | */ |
| 83 | −static inline enum dma_data_direction | |
| 83 | +static inline enum dma_transfer_direction | |
| 84 | 84 | ep93xx_dma_chan_direction(struct dma_chan *chan) |
| 85 | 85 | { |
| 86 | 86 | if (!ep93xx_dma_chan_is_m2p(chan)) |
| 87 | 87 | return DMA_NONE; |
| 88 | 88 | |
| 89 | 89 | /* even channels are for TX, odd for RX */ |
| 90 | − return (chan->chan_id % 2 == 0) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
| 90 | + return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; | |
| 91 | 91 | } |
| 92 | 92 | |
| 93 | 93 | #endif /* __ASM_ARCH_DMA_H */ |
| @@ -32,6 +32,7 @@ · 31 unmodified lines | ||
| 32 | 32 | #include <mach/hardware.h> |
| 33 | 33 | #include <mach/fb.h> |
| 34 | 34 | #include <mach/ep93xx_spi.h> |
| 35 | +#include <mach/gpio-ep93xx.h> | |
| 35 | 36 | |
| 36 | 37 | #include <asm/mach-types.h> |
| 37 | 38 | #include <asm/mach/map.h> |
| @@ -153,7 +154,6 @@ static struct i2c_board_info vision_i2c_info[] __initdata = { · 115 unmodified lines | ||
| 153 | 154 | }, { |
| 154 | 155 | I2C_BOARD_INFO("pca9539", 0x74), |
| 155 | 156 | .platform_data = &pca953x_74_gpio_data, |
| 156 | − .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)), | |
| 157 | 157 | }, { |
| 158 | 158 | I2C_BOARD_INFO("pca9539", 0x75), |
| 159 | 159 | .platform_data = &pca953x_75_gpio_data, |
| @@ -348,6 +348,8 @@ static void __init vision_init_machine(void) · 188 unmodified lines | ||
| 348 | 348 | "pca9539:74")) |
| 349 | 349 | pr_warn("cannot request interrupt gpio for pca9539:74\n"); |
| 350 | 350 | |
| 351 | + vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)); | |
| 352 | + | |
| 351 | 353 | ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, |
| 352 | 354 | ARRAY_SIZE(vision_i2c_info)); |
| 353 | 355 | ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, |
| @@ -32,6 +32,7 @@ · 31 unmodified lines | ||
| 32 | 32 | |
| 33 | 33 | #include "common.h" |
| 34 | 34 | |
| 35 | +#ifdef CONFIG_PM_SLEEP | |
| 35 | 36 | static struct sleep_save exynos4210_clock_save[] = { |
| 36 | 37 | SAVE_ITEM(S5P_CLKSRC_IMAGE), |
| 37 | 38 | SAVE_ITEM(S5P_CLKSRC_LCD1), |
| @@ -42,6 +43,7 @@ static struct sleep_save exynos4210_clock_save[] = { · 4 unmodified lines | ||
| 42 | 43 | SAVE_ITEM(S5P_CLKGATE_IP_LCD1), |
| 43 | 44 | SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), |
| 44 | 45 | }; |
| 46 | +#endif | |
| 45 | 47 | |
| 46 | 48 | static struct clksrc_clk *sysclks[] = { |
| 47 | 49 | /* nothing here yet */ |
| @@ -32,12 +32,14 @@ · 31 unmodified lines | ||
| 32 | 32 | |
| 33 | 33 | #include "common.h" |
| 34 | 34 | |
| 35 | +#ifdef CONFIG_PM_SLEEP | |
| 35 | 36 | static struct sleep_save exynos4212_clock_save[] = { |
| 36 | 37 | SAVE_ITEM(S5P_CLKSRC_IMAGE), |
| 37 | 38 | SAVE_ITEM(S5P_CLKDIV_IMAGE), |
| 38 | 39 | SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), |
| 39 | 40 | SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), |
| 40 | 41 | }; |
| 42 | +#endif | |
| 41 | 43 | |
| 42 | 44 | static struct clk *clk_src_mpll_user_list[] = { |
| 43 | 45 | [0] = &clk_fin_mpll, |
| @@ -30,6 +30,7 @@ · 29 unmodified lines | ||
| 30 | 30 | |
| 31 | 31 | #include "common.h" |
| 32 | 32 | |
| 33 | +#ifdef CONFIG_PM_SLEEP | |
| 33 | 34 | static struct sleep_save exynos4_clock_save[] = { |
| 34 | 35 | SAVE_ITEM(S5P_CLKDIV_LEFTBUS), |
| 35 | 36 | SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), |
| @@ -93,6 +94,7 @@ static struct sleep_save exynos4_clock_save[] = { · 57 unmodified lines | ||
| 93 | 94 | SAVE_ITEM(S5P_CLKGATE_SCLKCPU), |
| 94 | 95 | SAVE_ITEM(S5P_CLKGATE_IP_CPU), |
| 95 | 96 | }; |
| 97 | +#endif | |
| 96 | 98 | |
| 97 | 99 | struct clk clk_sclk_hdmi27m = { |
| 98 | 100 | .name = "sclk_hdmi27m", |
| @@ -36,6 +36,8 @@ pen: ldr r7, [r6] · 35 unmodified lines | ||
| 36 | 36 | * should now contain the SVC stack for this core |
| 37 | 37 | */ |
| 38 | 38 | b secondary_startup |
| 39 | +ENDPROC(exynos4_secondary_startup) | |
| 39 | 40 | |
| 41 | + .align 2 | |
| 40 | 42 | 1: .long . |
| 41 | 43 | .long pen_release |
| @@ -16,6 +16,7 @@ · 15 unmodified lines | ||
| 16 | 16 | #include <linux/io.h> |
| 17 | 17 | |
| 18 | 18 | #include <asm/cacheflush.h> |
| 19 | +#include <asm/smp_plat.h> | |
| 19 | 20 | |
| 20 | 21 | #include <mach/regs-pmu.h> |
| 21 | 22 | |
| @@ -15,11 +15,13 @@ · 14 unmodified lines | ||
| 15 | 15 | #include <linux/serial_core.h> |
| 16 | 16 | |
| 17 | 17 | #include <asm/mach/arch.h> |
| 18 | +#include <asm/hardware/gic.h> | |
| 18 | 19 | #include <mach/map.h> |
| 19 | 20 | |
| 20 | 21 | #include <plat/cpu.h> |
| 21 | 22 | #include <plat/regs-serial.h> |
| 22 | −#include <plat/exynos4.h> | |
| 23 | + | |
| 24 | +#include "common.h" | |
| 23 | 25 | |
| 24 | 26 | /* |
| 25 | 27 | * The following lookup table is used to override device names when devices |
| @@ -60,7 +62,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { · 34 unmodified lines | ||
| 60 | 62 | |
| 61 | 63 | static void __init exynos4210_dt_map_io(void) |
| 62 | 64 | { |
| 63 | − s5p_init_io(NULL, 0, S5P_VA_CHIPID); | |
| 65 | + exynos_init_io(NULL, 0); | |
| 64 | 66 | s3c24xx_init_clocks(24000000); |
| 65 | 67 | } |
| 66 | 68 | |
| @@ -79,7 +81,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") · 12 unmodified lines | ||
| 79 | 81 | /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ |
| 80 | 82 | .init_irq = exynos4_init_irq, |
| 81 | 83 | .map_io = exynos4210_dt_map_io, |
| 84 | + .handle_irq = gic_handle_irq, | |
| 82 | 85 | .init_machine = exynos4210_dt_machine_init, |
| 83 | 86 | .timer = &exynos4_timer, |
| 84 | 87 | .dt_compat = exynos4210_dt_compat, |
| 88 | + .restart = exynos4_restart, | |
| 85 | 89 | MACHINE_END |
| @@ -220,14 +220,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = { · 219 unmodified lines | ||
| 220 | 220 | .lower_margin = 1, |
| 221 | 221 | .hsync_len = 48, |
| 222 | 222 | .vsync_len = 3, |
| 223 | − .xres = 1280, | |
| 224 | − .yres = 800, | |
| 223 | + .xres = 1024, | |
| 224 | + .yres = 600, | |
| 225 | 225 | .refresh = 60, |
| 226 | 226 | }, |
| 227 | 227 | .max_bpp = 24, |
| 228 | 228 | .default_bpp = 16, |
| 229 | − .virtual_x = 1280, | |
| 230 | − .virtual_y = 800, | |
| 229 | + .virtual_x = 1024, | |
| 230 | + .virtual_y = 2 * 600, | |
| 231 | 231 | }; |
| 232 | 232 | |
| 233 | 233 | static struct s3c_fb_platdata nuri_fb_pdata __initdata = { |
| @@ -597,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = { · 596 unmodified lines | ||
| 597 | 597 | static struct s3c_fb_platdata origen_lcd_pdata __initdata = { |
| 598 | 598 | .win[0] = &origen_fb_win0, |
| 599 | 599 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, |
| 600 | − .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | |
| 600 | + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | | |
| 601 | + VIDCON1_INV_VCLK, | |
| 601 | 602 | .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, |
| 602 | 603 | }; |
| 603 | 604 | |
| @@ -910,7 +910,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = { · 909 unmodified lines | ||
| 910 | 910 | .bus_type = FIMC_MIPI_CSI2, |
| 911 | 911 | .board_info = &m5mols_board_info, |
| 912 | 912 | .i2c_bus_num = 0, |
| 913 | − .clk_frequency = 21600000UL, | |
| 913 | + .clk_frequency = 24000000UL, | |
| 914 | 914 | .csi_data_align = 32, |
| 915 | 915 | }, |
| 916 | 916 | }; |
| @@ -23,8 +23,8 @@ · 22 unmodified lines | ||
| 23 | 23 | |
| 24 | 24 | #include <asm/cacheflush.h> |
| 25 | 25 | #include <asm/hardware/gic.h> |
| 26 | +#include <asm/smp_plat.h> | |
| 26 | 27 | #include <asm/smp_scu.h> |
| 27 | −#include <asm/unified.h> | |
| 28 | 28 | |
| 29 | 29 | #include <mach/hardware.h> |
| 30 | 30 | #include <mach/regs-clock.h> |
| @@ -137,7 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) · 106 unmodified lines | ||
| 137 | 137 | while (time_before(jiffies, timeout)) { |
| 138 | 138 | smp_rmb(); |
| 139 | 139 | |
| 140 | − __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), | |
| 140 | + __raw_writel(virt_to_phys(exynos4_secondary_startup), | |
| 141 | 141 | CPU1_BOOT_REG); |
| 142 | 142 | gic_raise_softirq(cpumask_of(cpu), 1); |
| 143 | 143 | |
| @@ -192,6 +192,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) · 48 unmodified lines | ||
| 192 | 192 | * until it receives a soft interrupt, and then the |
| 193 | 193 | * secondary CPU branches to this address. |
| 194 | 194 | */ |
| 195 | − __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), | |
| 195 | + __raw_writel(virt_to_phys(exynos4_secondary_startup), | |
| 196 | 196 | CPU1_BOOT_REG); |
| 197 | 197 | } |
| @@ -206,7 +206,7 @@ static void exynos4_pm_prepare(void) · 205 unmodified lines | ||
| 206 | 206 | |
| 207 | 207 | } |
| 208 | 208 | |
| 209 | −static int exynos4_pm_add(struct device *dev) | |
| 209 | +static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif) | |
| 210 | 210 | { |
| 211 | 211 | pm_cpu_prep = exynos4_pm_prepare; |
| 212 | 212 | pm_cpu_sleep = exynos4_cpu_suspend; |
| @@ -384,7 +384,9 @@ static void exynos4_pm_resume(void) · 171 unmodified lines | ||
| 384 | 384 | |
| 385 | 385 | exynos4_restore_pll(); |
| 386 | 386 | |
| 387 | +#ifdef CONFIG_SMP | |
| 387 | 388 | scu_enable(S5P_VA_SCU); |
| 389 | +#endif | |
| 388 | 390 | |
| 389 | 391 | #ifdef CONFIG_CACHE_L2X0 |
| 390 | 392 | s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); |
| @@ -25,7 +25,7 @@ · 24 unmodified lines | ||
| 25 | 25 | #include <linux/smp.h> |
| 26 | 26 | |
| 27 | 27 | #include <asm/cacheflush.h> |
| 28 | −#include <asm/unified.h> | |
| 28 | +#include <asm/smp_plat.h> | |
| 29 | 29 | #include <asm/smp_scu.h> |
| 30 | 30 | #include <asm/hardware/arm_timer.h> |
| 31 | 31 | #include <asm/hardware/timer-sp.h> |
| @@ -73,10 +73,8 @@ static void __init highbank_map_io(void) · 41 unmodified lines | ||
| 73 | 73 | |
| 74 | 74 | void highbank_set_cpu_jump(int cpu, void *jump_addr) |
| 75 | 75 | { |
| 76 | −#ifdef CONFIG_SMP | |
| 77 | 76 | cpu = cpu_logical_map(cpu); |
| 78 | −#endif | |
| 79 | − writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu)); | |
| 77 | + writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); | |
| 80 | 78 | __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); |
| 81 | 79 | outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), |
| 82 | 80 | HB_JUMP_TABLE_PHYS(cpu) + 15); |
| @@ -22,6 +22,18 @@ config ARCH_MX25 · 21 unmodified lines | ||
| 22 | 22 | config MACH_MX27 |
| 23 | 23 | bool |
| 24 | 24 | |
| 25 | +config ARCH_MX5 | |
| 26 | + bool | |
| 27 | + | |
| 28 | +config ARCH_MX50 | |
| 29 | + bool | |
| 30 | + | |
| 31 | +config ARCH_MX51 | |
| 32 | + bool | |
| 33 | + | |
| 34 | +config ARCH_MX53 | |
| 35 | + bool | |
| 36 | + | |
| 25 | 37 | config SOC_IMX1 |
| 26 | 38 | bool |
| 27 | 39 | select ARCH_MX1 |
| @@ -73,6 +85,31 @@ config SOC_IMX35 · 45 unmodified lines | ||
| 73 | 85 | select MXC_AVIC |
| 74 | 86 | select SMP_ON_UP if SMP |
| 75 | 87 | |
| 88 | +config SOC_IMX5 | |
| 89 | + select CPU_V7 | |
| 90 | + select MXC_TZIC | |
| 91 | + select ARCH_MXC_IOMUX_V3 | |
| 92 | + select ARCH_MXC_AUDMUX_V2 | |
| 93 | + select ARCH_HAS_CPUFREQ | |
| 94 | + select ARCH_MX5 | |
| 95 | + bool | |
| 96 | + | |
| 97 | +config SOC_IMX50 | |
| 98 | + bool | |
| 99 | + select SOC_IMX5 | |
| 100 | + select ARCH_MX50 | |
| 101 | + | |
| 102 | +config SOC_IMX51 | |
| 103 | + bool | |
| 104 | + select SOC_IMX5 | |
| 105 | + select ARCH_MX5 | |
| 106 | + select ARCH_MX51 | |
| 107 | + | |
| 108 | +config SOC_IMX53 | |
| 109 | + bool | |
| 110 | + select SOC_IMX5 | |
| 111 | + select ARCH_MX5 | |
| 112 | + select ARCH_MX53 | |
| 76 | 113 | |
| 77 | 114 | if ARCH_IMX_V4_V5 |
| 78 | 115 | |
| @@ -592,6 +629,207 @@ config MACH_VPR200 · 513 unmodified lines | ||
| 592 | 629 | Include support for VPR200 platform. This includes specific |
| 593 | 630 | configurations for the board and its peripherals. |
| 594 | 631 | |
| 632 | +comment "i.MX5 platforms:" | |
| 633 | + | |
| 634 | +config MACH_MX50_RDP | |
| 635 | + bool "Support MX50 reference design platform" | |
| 636 | + depends on BROKEN | |
| 637 | + select SOC_IMX50 | |
| 638 | + select IMX_HAVE_PLATFORM_IMX_I2C | |
| 639 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 640 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 641 | + select IMX_HAVE_PLATFORM_SPI_IMX | |
| 642 | + help | |
| 643 | + Include support for MX50 reference design platform (RDP) board. This | |
| 644 | + includes specific configurations for the board and its peripherals. | |
| 645 | + | |
| 646 | +comment "i.MX51 machines:" | |
| 647 | + | |
| 648 | +config MACH_IMX51_DT | |
| 649 | + bool "Support i.MX51 platforms from device tree" | |
| 650 | + select SOC_IMX51 | |
| 651 | + select USE_OF | |
| 652 | + select MACH_MX51_BABBAGE | |
| 653 | + help | |
| 654 | + Include support for Freescale i.MX51 based platforms | |
| 655 | + using the device tree for discovery | |
| 656 | + | |
| 657 | +config MACH_MX51_BABBAGE | |
| 658 | + bool "Support MX51 BABBAGE platforms" | |
| 659 | + select SOC_IMX51 | |
| 660 | + select IMX_HAVE_PLATFORM_FSL_USB2_UDC | |
| 661 | + select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 662 | + select IMX_HAVE_PLATFORM_IMX_I2C | |
| 663 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 664 | + select IMX_HAVE_PLATFORM_MXC_EHCI | |
| 665 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 666 | + select IMX_HAVE_PLATFORM_SPI_IMX | |
| 667 | + help | |
| 668 | + Include support for MX51 Babbage platform, also known as MX51EVK in | |
| 669 | + u-boot. This includes specific configurations for the board and its | |
| 670 | + peripherals. | |
| 671 | + | |
| 672 | +config MACH_MX51_3DS | |
| 673 | + bool "Support MX51PDK (3DS)" | |
| 674 | + select SOC_IMX51 | |
| 675 | + select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 676 | + select IMX_HAVE_PLATFORM_IMX_KEYPAD | |
| 677 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 678 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 679 | + select IMX_HAVE_PLATFORM_SPI_IMX | |
| 680 | + select MXC_DEBUG_BOARD | |
| 681 | + help | |
| 682 | + Include support for MX51PDK (3DS) platform. This includes specific | |
| 683 | + configurations for the board and its peripherals. | |
| 684 | + | |
| 685 | +config MACH_EUKREA_CPUIMX51 | |
| 686 | + bool "Support Eukrea CPUIMX51 module" | |
| 687 | + select SOC_IMX51 | |
| 688 | + select IMX_HAVE_PLATFORM_FSL_USB2_UDC | |
| 689 | + select IMX_HAVE_PLATFORM_IMX_I2C | |
| 690 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 691 | + select IMX_HAVE_PLATFORM_MXC_EHCI | |
| 692 | + select IMX_HAVE_PLATFORM_MXC_NAND | |
| 693 | + select IMX_HAVE_PLATFORM_SPI_IMX | |
| 694 | + help | |
| 695 | + Include support for Eukrea CPUIMX51 platform. This includes | |
| 696 | + specific configurations for the module and its peripherals. | |
| 697 | + | |
| 698 | +choice | |
| 699 | + prompt "Baseboard" | |
| 700 | + depends on MACH_EUKREA_CPUIMX51 | |
| 701 | + default MACH_EUKREA_MBIMX51_BASEBOARD | |
| 702 | + | |
| 703 | +config MACH_EUKREA_MBIMX51_BASEBOARD | |
| 704 | + prompt "Eukrea MBIMX51 development board" | |
| 705 | + bool | |
| 706 | + select IMX_HAVE_PLATFORM_IMX_KEYPAD | |
| 707 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 708 | + select LEDS_GPIO_REGISTER | |
| 709 | + help | |
| 710 | + This adds board specific devices that can be found on Eukrea's | |
| 711 | + MBIMX51 evaluation board. | |
| 712 | + | |
| 713 | +endchoice | |
| 714 | + | |
| 715 | +config MACH_EUKREA_CPUIMX51SD | |
| 716 | + bool "Support Eukrea CPUIMX51SD module" | |
| 717 | + select SOC_IMX51 | |
| 718 | + select IMX_HAVE_PLATFORM_FSL_USB2_UDC | |
| 719 | + select IMX_HAVE_PLATFORM_IMX_I2C | |
| 720 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 721 | + select IMX_HAVE_PLATFORM_MXC_EHCI | |
| 722 | + select IMX_HAVE_PLATFORM_MXC_NAND | |
| 723 | + select IMX_HAVE_PLATFORM_SPI_IMX | |
| 724 | + help | |
| 725 | + Include support for Eukrea CPUIMX51SD platform. This includes | |
| 726 | + specific configurations for the module and its peripherals. | |
| 727 | + | |
| 728 | +choice | |
| 729 | + prompt "Baseboard" | |
| 730 | + depends on MACH_EUKREA_CPUIMX51SD | |
| 731 | + default MACH_EUKREA_MBIMXSD51_BASEBOARD | |
| 732 | + | |
| 733 | +config MACH_EUKREA_MBIMXSD51_BASEBOARD | |
| 734 | + prompt "Eukrea MBIMXSD development board" | |
| 735 | + bool | |
| 736 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 737 | + select LEDS_GPIO_REGISTER | |
| 738 | + help | |
| 739 | + This adds board specific devices that can be found on Eukrea's | |
| 740 | + MBIMXSD evaluation board. | |
| 741 | + | |
| 742 | +endchoice | |
| 743 | + | |
| 744 | +config MX51_EFIKA_COMMON | |
| 745 | + bool | |
| 746 | + select SOC_IMX51 | |
| 747 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 748 | + select IMX_HAVE_PLATFORM_MXC_EHCI | |
| 749 | + select IMX_HAVE_PLATFORM_PATA_IMX | |
| 750 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 751 | + select IMX_HAVE_PLATFORM_SPI_IMX | |
| 752 | + select MXC_ULPI if USB_ULPI | |
| 753 | + | |
| 754 | +config MACH_MX51_EFIKAMX | |
| 755 | + bool "Support MX51 Genesi Efika MX nettop" | |
| 756 | + select LEDS_GPIO_REGISTER | |
| 757 | + select MX51_EFIKA_COMMON | |
| 758 | + help | |
| 759 | + Include support for Genesi Efika MX nettop. This includes specific | |
| 760 | + configurations for the board and its peripherals. | |
| 761 | + | |
| 762 | +config MACH_MX51_EFIKASB | |
| 763 | + bool "Support MX51 Genesi Efika Smartbook" | |
| 764 | + select LEDS_GPIO_REGISTER | |
| 765 | + select MX51_EFIKA_COMMON | |
| 766 | + help | |
| 767 | + Include support for Genesi Efika Smartbook. This includes specific | |
| 768 | + configurations for the board and its peripherals. | |
| 769 | + | |
| 770 | +comment "i.MX53 machines:" | |
| 771 | + | |
| 772 | +config MACH_IMX53_DT | |
| 773 | + bool "Support i.MX53 platforms from device tree" | |
| 774 | + select SOC_IMX53 | |
| 775 | + select USE_OF | |
| 776 | + select MACH_MX53_ARD | |
| 777 | + select MACH_MX53_EVK | |
| 778 | + select MACH_MX53_LOCO | |
| 779 | + select MACH_MX53_SMD | |
| 780 | + help | |
| 781 | + Include support for Freescale i.MX53 based platforms | |
| 782 | + using the device tree for discovery | |
| 783 | + | |
| 784 | +config MACH_MX53_EVK | |
| 785 | + bool "Support MX53 EVK platforms" | |
| 786 | + select SOC_IMX53 | |
| 787 | + select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 788 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 789 | + select IMX_HAVE_PLATFORM_IMX_I2C | |
| 790 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 791 | + select IMX_HAVE_PLATFORM_SPI_IMX | |
| 792 | + select LEDS_GPIO_REGISTER | |
| 793 | + help | |
| 794 | + Include support for MX53 EVK platform. This includes specific | |
| 795 | + configurations for the board and its peripherals. | |
| 796 | + | |
| 797 | +config MACH_MX53_SMD | |
| 798 | + bool "Support MX53 SMD platforms" | |
| 799 | + select SOC_IMX53 | |
| 800 | + select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 801 | + select IMX_HAVE_PLATFORM_IMX_I2C | |
| 802 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 803 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 804 | + help | |
| 805 | + Include support for MX53 SMD platform. This includes specific | |
| 806 | + configurations for the board and its peripherals. | |
| 807 | + | |
| 808 | +config MACH_MX53_LOCO | |
| 809 | + bool "Support MX53 LOCO platforms" | |
| 810 | + select SOC_IMX53 | |
| 811 | + select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 812 | + select IMX_HAVE_PLATFORM_IMX_I2C | |
| 813 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 814 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 815 | + select IMX_HAVE_PLATFORM_GPIO_KEYS | |
| 816 | + select LEDS_GPIO_REGISTER | |
| 817 | + help | |
| 818 | + Include support for MX53 LOCO platform. This includes specific | |
| 819 | + configurations for the board and its peripherals. | |
| 820 | + | |
| 821 | +config MACH_MX53_ARD | |
| 822 | + bool "Support MX53 ARD platforms" | |
| 823 | + select SOC_IMX53 | |
| 824 | + select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 825 | + select IMX_HAVE_PLATFORM_IMX_I2C | |
| 826 | + select IMX_HAVE_PLATFORM_IMX_UART | |
| 827 | + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 828 | + select IMX_HAVE_PLATFORM_GPIO_KEYS | |
| 829 | + help | |
| 830 | + Include support for MX53 ARD platform. This includes specific | |
| 831 | + configurations for the board and its peripherals. | |
| 832 | + | |
| 595 | 833 | comment "i.MX6 family:" |
| 596 | 834 | |
| 597 | 835 | config SOC_IMX6Q |
| @@ -11,6 +11,8 @@ obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o · 10 unmodified lines | ||
| 11 | 11 | obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o |
| 12 | 12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o |
| 13 | 13 | |
| 14 | +obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o | |
| 15 | + | |
| 14 | 16 | # Support for CMOS sensor interface |
| 15 | 17 | obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o |
| 16 | 18 | |
| @@ -75,3 +77,22 @@ obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o · 58 unmodified lines | ||
| 75 | 77 | ifeq ($(CONFIG_PM),y) |
| 76 | 78 | obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o |
| 77 | 79 | endif |
| 80 | + | |
| 81 | +# i.MX5 based machines | |
| 82 | +obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o | |
| 83 | +obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o | |
| 84 | +obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o | |
| 85 | +obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o | |
| 86 | +obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o | |
| 87 | +obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o | |
| 88 | +obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += mach-cpuimx51.o | |
| 89 | +obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o | |
| 90 | +obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o | |
| 91 | +obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o | |
| 92 | +obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o | |
| 93 | +obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o | |
| 94 | +obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o | |
| 95 | +obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o | |
| 96 | + | |
| 97 | +obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o | |
| 98 | +obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o | |
| @@ -22,6 +22,18 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000 · 21 unmodified lines | ||
| 22 | 22 | params_phys-$(CONFIG_SOC_IMX35) := 0x80000100 |
| 23 | 23 | initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 |
| 24 | 24 | |
| 25 | +zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000 | |
| 26 | +params_phys-$(CONFIG_SOC_IMX50) := 0x70000100 | |
| 27 | +initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000 | |
| 28 | + | |
| 29 | +zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000 | |
| 30 | +params_phys-$(CONFIG_SOC_IMX51) := 0x90000100 | |
| 31 | +initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000 | |
| 32 | + | |
| 33 | +zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000 | |
| 34 | +params_phys-$(CONFIG_SOC_IMX53) := 0x70000100 | |
| 35 | +initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000 | |
| 36 | + | |
| 25 | 37 | zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 |
| 26 | 38 | params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 |
| 27 | 39 | initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 |
| @@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg); · 813 unmodified lines | ||
| 814 | 814 | DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg); |
| 815 | 815 | DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg); |
| 816 | 816 | |
| 817 | +static unsigned long twd_clk_get_rate(struct clk *clk) | |
| 818 | +{ | |
| 819 | + return clk_get_rate(clk->parent) / 2; | |
| 820 | +} | |
| 821 | + | |
| 822 | +static struct clk twd_clk = { | |
| 823 | + .parent = &arm_clk, | |
| 824 | + .get_rate = twd_clk_get_rate, | |
| 825 | +}; | |
| 826 | + | |
| 817 | 827 | static unsigned long pll2_200m_get_rate(struct clk *clk) |
| 818 | 828 | { |
| 819 | 829 | return clk_get_rate(clk->parent) / 2; |
| @@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = { · 1074 unmodified lines | ||
| 1894 | 1904 | _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk), |
| 1895 | 1905 | _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk), |
| 1896 | 1906 | _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk), |
| 1907 | + _REGISTER_CLOCK("smp_twd", NULL, twd_clk), | |
| 1897 | 1908 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk), |
| 1898 | 1909 | _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk), |
| 1899 | 1910 | _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk), |
| @@ -23,7 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | #include <mach/common.h> |
| 24 | 24 | #include <mach/clock.h> |
| 25 | 25 | |
| 26 | −#include "crm_regs.h" | |
| 26 | +#include "crm-regs-imx5.h" | |
| 27 | 27 | |
| 28 | 28 | /* External clock values passed-in by the board code */ |
| 29 | 29 | static unsigned long external_high_reference, external_low_reference; |
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| @@ -32,7 +32,6 @@ · 31 unmodified lines | ||
| 32 | 32 | #include <asm/mach/arch.h> |
| 33 | 33 | #include <asm/mach/time.h> |
| 34 | 34 | |
| 35 | −#include "crm_regs.h" | |
| 36 | 35 | #include "devices-imx53.h" |
| 37 | 36 | |
| 38 | 37 | #define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) |
| @@ -189,8 +188,10 @@ static int weim_cs_config(void) · 150 unmodified lines | ||
| 189 | 188 | return -ENOMEM; |
| 190 | 189 | |
| 191 | 190 | iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); |
| 192 | − if (!iomuxc_base) | |
| 191 | + if (!iomuxc_base) { | |
| 192 | + iounmap(weim_base); | |
| 193 | 193 | return -ENOMEM; |
| 194 | + } | |
| 194 | 195 | |
| 195 | 196 | /* CS1 timings for LAN9220 */ |
| 196 | 197 | writel(0x20001, (weim_base + 0x18)); |
| @@ -37,7 +37,6 @@ · 36 unmodified lines | ||
| 37 | 37 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) |
| 38 | 38 | #define MX53EVK_LED IMX_GPIO_NR(7, 7) |
| 39 | 39 | |
| 40 | −#include "crm_regs.h" | |
| 41 | 40 | #include "devices-imx53.h" |
| 42 | 41 | |
| 43 | 42 | static iomux_v3_cfg_t mx53_evk_pads[] = { |
| @@ -32,7 +32,6 @@ · 31 unmodified lines | ||
| 32 | 32 | #include <asm/mach/arch.h> |
| 33 | 33 | #include <asm/mach/time.h> |
| 34 | 34 | |
| 35 | −#include "crm_regs.h" | |
| 36 | 35 | #include "devices-imx53.h" |
| 37 | 36 | |
| 38 | 37 | #define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) |
| @@ -31,7 +31,6 @@ · 30 unmodified lines | ||
| 31 | 31 | #include <asm/mach/arch.h> |
| 32 | 32 | #include <asm/mach/time.h> |
| 33 | 33 | |
| 34 | −#include "crm_regs.h" | |
| 35 | 34 | #include "devices-imx53.h" |
| 36 | 35 | |
| 37 | 36 | #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) |
File renamed without changes.
File renamed without changes.
| @@ -1,8 +1,6 @@ | ||
| 1 | 1 | /* |
| 2 | − * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 3 | − */ | |
| 4 | − | |
| 5 | −/* | |
| 2 | + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 3 | + * | |
| 6 | 4 | * The code contained herein is licensed under the GNU General Public |
| 7 | 5 | * License. You may obtain a copy of the GNU General Public License |
| 8 | 6 | * Version 2 or later at the following locations: |
| @@ -10,14 +8,22 @@ · 1 unmodified line | ||
| 10 | 8 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | 10 | */ |
| 13 | −#include <linux/platform_device.h> | |
| 11 | +#include <linux/suspend.h> | |
| 12 | +#include <linux/clk.h> | |
| 14 | 13 | #include <linux/io.h> |
| 15 | −#include <mach/hardware.h> | |
| 14 | +#include <linux/err.h> | |
| 15 | +#include <asm/cacheflush.h> | |
| 16 | +#include <asm/tlbflush.h> | |
| 16 | 17 | #include <mach/common.h> |
| 17 | −#include "crm_regs.h" | |
| 18 | +#include <mach/hardware.h> | |
| 19 | +#include "crm-regs-imx5.h" | |
| 20 | + | |
| 21 | +static struct clk *gpc_dvfs_clk; | |
| 18 | 22 | |
| 19 | −/* set cpu low power mode before WFI instruction. This function is called | |
| 20 | − * mx5 because it can be used for mx50, mx51, and mx53.*/ | |
| 23 | +/* | |
| 24 | + * set cpu low power mode before WFI instruction. This function is called | |
| 25 | + * mx5 because it can be used for mx50, mx51, and mx53. | |
| 26 | + */ | |
| 21 | 27 | void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) |
| 22 | 28 | { |
| 23 | 29 | u32 plat_lpc, arm_srpgcr, ccm_clpcr; |
| @@ -80,3 +86,68 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) · 56 unmodified lines | ||
| 80 | 86 | __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); |
| 81 | 87 | } |
| 82 | 88 | } |
| 89 | + | |
| 90 | +static int mx5_suspend_prepare(void) | |
| 91 | +{ | |
| 92 | + return clk_enable(gpc_dvfs_clk); | |
| 93 | +} | |
| 94 | + | |
| 95 | +static int mx5_suspend_enter(suspend_state_t state) | |
| 96 | +{ | |
| 97 | + switch (state) { | |
| 98 | + case PM_SUSPEND_MEM: | |
| 99 | + mx5_cpu_lp_set(STOP_POWER_OFF); | |
| 100 | + break; | |
| 101 | + case PM_SUSPEND_STANDBY: | |
| 102 | + mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | |
| 103 | + break; | |
| 104 | + default: | |
| 105 | + return -EINVAL; | |
| 106 | + } | |
| 107 | + | |
| 108 | + if (state == PM_SUSPEND_MEM) { | |
| 109 | + local_flush_tlb_all(); | |
| 110 | + flush_cache_all(); | |
| 111 | + | |
| 112 | + /*clear the EMPGC0/1 bits */ | |
| 113 | + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); | |
| 114 | + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); | |
| 115 | + } | |
| 116 | + cpu_do_idle(); | |
| 117 | + return 0; | |
| 118 | +} | |
| 119 | + | |
| 120 | +static void mx5_suspend_finish(void) | |
| 121 | +{ | |
| 122 | + clk_disable(gpc_dvfs_clk); | |
| 123 | +} | |
| 124 | + | |
| 125 | +static int mx5_pm_valid(suspend_state_t state) | |
| 126 | +{ | |
| 127 | + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); | |
| 128 | +} | |
| 129 | + | |
| 130 | +static const struct platform_suspend_ops mx5_suspend_ops = { | |
| 131 | + .valid = mx5_pm_valid, | |
| 132 | + .prepare = mx5_suspend_prepare, | |
| 133 | + .enter = mx5_suspend_enter, | |
| 134 | + .finish = mx5_suspend_finish, | |
| 135 | +}; | |
| 136 | + | |
| 137 | +static int __init mx5_pm_init(void) | |
| 138 | +{ | |
| 139 | + if (!cpu_is_mx51() && !cpu_is_mx53()) | |
| 140 | + return 0; | |
| 141 | + | |
| 142 | + if (gpc_dvfs_clk == NULL) | |
| 143 | + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | |
| 144 | + | |
| 145 | + if (!IS_ERR(gpc_dvfs_clk)) { | |
| 146 | + if (cpu_is_mx51()) | |
| 147 | + suspend_set_ops(&mx5_suspend_ops); | |
| 148 | + } else | |
| 149 | + return -EPERM; | |
| 150 | + | |
| 151 | + return 0; | |
| 152 | +} | |
| 153 | +device_initcall(mx5_pm_init); | |
| @@ -15,7 +15,7 @@ · 14 unmodified lines | ||
| 15 | 15 | #include <linux/of.h> |
| 16 | 16 | #include <linux/of_address.h> |
| 17 | 17 | #include <linux/smp.h> |
| 18 | −#include <asm/unified.h> | |
| 18 | +#include <asm/smp_plat.h> | |
| 19 | 19 | |
| 20 | 20 | #define SRC_SCR 0x000 |
| 21 | 21 | #define SRC_GPR1 0x020 |
| @@ -25,10 +25,6 @@ · 3 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | static void __iomem *src_base; |
| 27 | 27 | |
| 28 | −#ifndef CONFIG_SMP | |
| 29 | −#define cpu_logical_map(cpu) 0 | |
| 30 | −#endif | |
| 31 | − | |
| 32 | 28 | void imx_enable_cpu(int cpu, bool enable) |
| 33 | 29 | { |
| 34 | 30 | u32 mask, val; |
| @@ -43,7 +39,7 @@ void imx_enable_cpu(int cpu, bool enable) · 8 unmodified lines | ||
| 43 | 39 | void imx_set_cpu_jump(int cpu, void *jump_addr) |
| 44 | 40 | { |
| 45 | 41 | cpu = cpu_logical_map(cpu); |
| 46 | − writel_relaxed(BSYM(virt_to_phys(jump_addr)), | |
| 42 | + writel_relaxed(virt_to_phys(jump_addr), | |
| 47 | 43 | src_base + SRC_GPR1 + cpu * 8); |
| 48 | 44 | } |
| 49 | 45 | |
| @@ -27,6 +27,7 @@ · 26 unmodified lines | ||
| 27 | 27 | #include <plat/cache-feroceon-l2.h> |
| 28 | 28 | #include <plat/mvsdio.h> |
| 29 | 29 | #include <plat/orion_nand.h> |
| 30 | +#include <plat/ehci-orion.h> | |
| 30 | 31 | #include <plat/common.h> |
| 31 | 32 | #include <plat/time.h> |
| 32 | 33 | #include <plat/addr-map.h> |
| @@ -73,7 +74,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; · 40 unmodified lines | ||
| 73 | 74 | void __init kirkwood_ehci_init(void) |
| 74 | 75 | { |
| 75 | 76 | kirkwood_clk_ctrl |= CGC_USB0; |
| 76 | − orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); | |
| 77 | + orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); | |
| 77 | 78 | } |
| 78 | 79 | |
| 79 | 80 | |
| @@ -31,314 +31,314 @@ · 30 unmodified lines | ||
| 31 | 31 | #define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) |
| 32 | 32 | |
| 33 | 33 | #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 34 | −#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 35 | −#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 34 | +#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 35 | +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 36 | 36 | |
| 37 | 37 | #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 38 | −#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 39 | −#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 38 | +#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 39 | +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 40 | 40 | |
| 41 | 41 | #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 42 | −#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 43 | −#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 42 | +#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 43 | +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 44 | 44 | |
| 45 | 45 | #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 46 | −#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 47 | −#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | |
| 46 | +#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 47 | +#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 48 | 48 | |
| 49 | 49 | #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 50 | −#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 51 | −#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | |
| 52 | −#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | |
| 50 | +#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 51 | +#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 52 | +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 ) | |
| 53 | 53 | #define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 54 | −#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) | |
| 54 | +#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 ) | |
| 55 | 55 | |
| 56 | 56 | #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 57 | −#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 58 | −#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 59 | −#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) | |
| 60 | −#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | |
| 57 | +#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 58 | +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 59 | +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 ) | |
| 60 | +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 ) | |
| 61 | 61 | #define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 62 | 62 | |
| 63 | −#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) | |
| 64 | −#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 65 | −#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) | |
| 63 | +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 64 | +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 65 | +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 ) | |
| 66 | 66 | |
| 67 | 67 | #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 68 | −#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) | |
| 69 | −#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 70 | −#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) | |
| 71 | −#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) | |
| 68 | +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 ) | |
| 69 | +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 70 | +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 ) | |
| 71 | +#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | |
| 72 | 72 | |
| 73 | 73 | #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 74 | −#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 75 | −#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 76 | −#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) | |
| 77 | −#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) | |
| 78 | −#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | |
| 79 | −#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) | |
| 80 | −#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) | |
| 74 | +#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 75 | +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 76 | +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 ) | |
| 77 | +#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 ) | |
| 78 | +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 ) | |
| 79 | +#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 ) | |
| 80 | +#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 ) | |
| 81 | 81 | |
| 82 | 82 | #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 83 | −#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 84 | −#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | |
| 85 | −#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) | |
| 86 | −#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | |
| 87 | −#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) | |
| 88 | −#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) | |
| 83 | +#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 84 | +#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 85 | +#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 ) | |
| 86 | +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 ) | |
| 87 | +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 ) | |
| 88 | +#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 ) | |
| 89 | 89 | |
| 90 | 90 | #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 91 | −#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 92 | −#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) | |
| 93 | −#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | |
| 94 | −#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) | |
| 91 | +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 92 | +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 ) | |
| 93 | +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 ) | |
| 94 | +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 ) | |
| 95 | 95 | |
| 96 | 96 | #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 97 | −#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | |
| 98 | −#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) | |
| 99 | −#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) | |
| 100 | −#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) | |
| 101 | −#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) | |
| 102 | −#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | |
| 97 | +#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 98 | +#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 ) | |
| 99 | +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 ) | |
| 100 | +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 ) | |
| 101 | +#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 ) | |
| 102 | +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 ) | |
| 103 | 103 | |
| 104 | 104 | #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 105 | 105 | #define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) |
| 106 | −#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) | |
| 107 | −#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) | |
| 108 | −#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) | |
| 109 | −#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) | |
| 106 | +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 107 | +#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 ) | |
| 108 | +#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | |
| 109 | +#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 ) | |
| 110 | 110 | |
| 111 | 111 | #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 112 | −#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 113 | −#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) | |
| 114 | −#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) | |
| 115 | −#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) | |
| 112 | +#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 113 | +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 ) | |
| 114 | +#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 ) | |
| 115 | +#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | |
| 116 | 116 | |
| 117 | 117 | #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 118 | −#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 119 | −#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) | |
| 120 | −#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | |
| 121 | −#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) | |
| 122 | −#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) | |
| 123 | −#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) | |
| 118 | +#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 119 | +#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 ) | |
| 120 | +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 121 | +#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 ) | |
| 122 | +#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | |
| 123 | +#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 ) | |
| 124 | 124 | |
| 125 | 125 | #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 126 | −#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 127 | −#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) | |
| 128 | −#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) | |
| 129 | −#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) | |
| 130 | −#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) | |
| 126 | +#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 127 | +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 128 | +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 ) | |
| 129 | +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 ) | |
| 130 | +#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | |
| 131 | 131 | |
| 132 | 132 | #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 133 | −#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 134 | −#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) | |
| 135 | −#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) | |
| 136 | −#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | |
| 137 | −#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) | |
| 138 | −#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) | |
| 133 | +#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 134 | +#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 ) | |
| 135 | +#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 ) | |
| 136 | +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 137 | +#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | |
| 138 | +#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 ) | |
| 139 | 139 | |
| 140 | 140 | #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 141 | −#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 142 | −#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) | |
| 143 | −#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) | |
| 144 | −#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) | |
| 141 | +#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 142 | +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 ) | |
| 143 | +#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 ) | |
| 144 | +#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 ) | |
| 145 | 145 | |
| 146 | 146 | #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 147 | −#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 148 | −#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) | |
| 147 | +#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 148 | +#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 ) | |
| 149 | 149 | |
| 150 | 150 | #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) |
| 151 | −#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) | |
| 151 | +#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 ) | |
| 152 | 152 | |
| 153 | 153 | #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 154 | −#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 155 | −#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 154 | +#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 155 | +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 156 | 156 | #define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 157 | −#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) | |
| 158 | −#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | |
| 157 | +#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 158 | +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 ) | |
| 159 | 159 | #define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 160 | 160 | |
| 161 | 161 | #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 162 | −#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 163 | −#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 162 | +#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 163 | +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 164 | 164 | #define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 165 | −#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | |
| 166 | −#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | |
| 165 | +#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 166 | +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 ) | |
| 167 | 167 | #define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 168 | 168 | |
| 169 | 169 | #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 170 | −#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 171 | −#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 170 | +#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 171 | +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 172 | 172 | #define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 173 | −#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | |
| 174 | −#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) | |
| 173 | +#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 174 | +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 ) | |
| 175 | 175 | #define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 176 | 176 | |
| 177 | 177 | #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 178 | −#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 179 | −#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) | |
| 178 | +#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 179 | +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 180 | 180 | #define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 181 | −#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | |
| 182 | −#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | |
| 181 | +#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 182 | +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 ) | |
| 183 | 183 | #define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 184 | 184 | |
| 185 | 185 | #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 186 | −#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 187 | −#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 186 | +#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 187 | +#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 188 | 188 | #define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 189 | −#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | |
| 189 | +#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 190 | 190 | #define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 191 | 191 | |
| 192 | 192 | #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 193 | −#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 194 | −#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 193 | +#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 194 | +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 195 | 195 | #define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 196 | −#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | |
| 196 | +#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 197 | 197 | #define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 198 | 198 | |
| 199 | 199 | #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 200 | −#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 201 | −#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) | |
| 200 | +#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 201 | +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 202 | 202 | #define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 203 | −#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) | |
| 203 | +#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 204 | 204 | #define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 205 | 205 | |
| 206 | 206 | #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 207 | −#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 208 | −#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 207 | +#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 208 | +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 209 | 209 | #define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 210 | −#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) | |
| 210 | +#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 211 | 211 | #define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 212 | 212 | |
| 213 | 213 | #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 214 | −#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 214 | +#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 215 | 215 | #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
| 216 | 216 | #define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 217 | −#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) | |
| 217 | +#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 ) | |
| 218 | 218 | #define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 219 | 219 | |
| 220 | 220 | #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 221 | −#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 221 | +#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 222 | 222 | #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) |
| 223 | 223 | #define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 224 | 224 | #define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 225 | 225 | |
| 226 | 226 | #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 227 | −#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 228 | −#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) | |
| 227 | +#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 228 | +#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 229 | 229 | #define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 230 | 230 | #define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 231 | 231 | |
| 232 | 232 | #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 233 | −#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 234 | −#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) | |
| 233 | +#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 234 | +#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 235 | 235 | #define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 236 | 236 | #define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 237 | 237 | |
| 238 | 238 | #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 239 | −#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) | |
| 240 | −#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) | |
| 239 | +#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 ) | |
| 240 | +#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 241 | 241 | #define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 242 | 242 | #define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 243 | 243 | |
| 244 | 244 | #define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) |
| 245 | −#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 245 | +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 246 | 246 | #define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 247 | 247 | #define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 248 | 248 | |
| 249 | 249 | #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) |
| 250 | −#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 250 | +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 251 | 251 | #define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 252 | −#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) | |
| 252 | +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 ) | |
| 253 | 253 | #define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 254 | 254 | |
| 255 | 255 | #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) |
| 256 | −#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) | |
| 256 | +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 ) | |
| 257 | 257 | #define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) |
| 258 | −#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) | |
| 258 | +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 ) | |
| 259 | 259 | #define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 260 | −#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) | |
| 260 | +#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 ) | |
| 261 | 261 | |
| 262 | 262 | #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 263 | −#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 264 | −#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | |
| 265 | −#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) | |
| 266 | −#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) | |
| 263 | +#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 264 | +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 265 | +#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 266 | +#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | |
| 267 | 267 | |
| 268 | 268 | #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 269 | −#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 270 | −#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | |
| 271 | −#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | |
| 272 | −#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) | |
| 269 | +#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 270 | +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 271 | +#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 272 | +#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 ) | |
| 273 | 273 | |
| 274 | 274 | #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 275 | −#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 276 | −#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | |
| 277 | −#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | |
| 275 | +#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 276 | +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 277 | +#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 278 | 278 | #define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 279 | 279 | |
| 280 | 280 | #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 281 | −#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 282 | −#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | |
| 283 | −#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | |
| 281 | +#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 282 | +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 283 | +#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 284 | 284 | #define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 285 | 285 | |
| 286 | 286 | #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 287 | −#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 288 | −#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | |
| 289 | −#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | |
| 287 | +#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 288 | +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 289 | +#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 290 | 290 | #define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 291 | 291 | |
| 292 | 292 | #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 293 | −#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 294 | −#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) | |
| 295 | −#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | |
| 293 | +#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 294 | +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 295 | +#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 296 | 296 | #define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 297 | 297 | |
| 298 | 298 | #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 299 | −#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 300 | −#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | |
| 301 | −#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) | |
| 299 | +#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 300 | +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 301 | +#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 302 | 302 | #define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 303 | 303 | |
| 304 | 304 | #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 305 | −#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 305 | +#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 306 | 306 | #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
| 307 | −#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) | |
| 307 | +#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 308 | 308 | #define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 309 | 309 | |
| 310 | 310 | #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) |
| 311 | −#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 311 | +#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 312 | 312 | #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) |
| 313 | −#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) | |
| 313 | +#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 ) | |
| 314 | 314 | #define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 315 | 315 | |
| 316 | 316 | #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) |
| 317 | −#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 318 | −#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) | |
| 317 | +#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 318 | +#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 319 | 319 | #define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 320 | 320 | |
| 321 | 321 | #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) |
| 322 | −#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 323 | −#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) | |
| 322 | +#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 323 | +#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 324 | 324 | #define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 325 | 325 | |
| 326 | 326 | #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) |
| 327 | −#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 328 | −#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) | |
| 327 | +#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 328 | +#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 329 | 329 | #define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 330 | 330 | |
| 331 | 331 | #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) |
| 332 | −#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) | |
| 333 | −#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | |
| 332 | +#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 ) | |
| 333 | +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 334 | 334 | #define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 335 | 335 | |
| 336 | 336 | #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) |
| 337 | 337 | #define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) |
| 338 | −#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) | |
| 339 | −#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) | |
| 340 | −#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) | |
| 341 | −#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) | |
| 338 | +#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 ) | |
| 339 | +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 ) | |
| 340 | +#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 ) | |
| 341 | +#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 ) | |
| 342 | 342 | #define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) |
| 343 | 343 | |
| 344 | 344 | #define MPP_MAX 49 |
| @@ -34,6 +34,7 @@ pen: ldr r7, [r6] · 33 unmodified lines | ||
| 34 | 34 | * should now contain the SVC stack for this core |
| 35 | 35 | */ |
| 36 | 36 | b secondary_startup |
| 37 | +ENDPROC(msm_secondary_startup) | |
| 37 | 38 | |
| 38 | 39 | .align |
| 39 | 40 | 1: .long . |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | ||
| 11 | 11 | #include <linux/smp.h> |
| 12 | 12 | |
| 13 | 13 | #include <asm/cacheflush.h> |
| 14 | +#include <asm/smp_plat.h> | |
| 14 | 15 | |
| 15 | 16 | extern volatile int pen_release; |
| 16 | 17 | |
| @@ -20,6 +20,7 @@ · 19 unmodified lines | ||
| 20 | 20 | #include <asm/cacheflush.h> |
| 21 | 21 | #include <asm/cputype.h> |
| 22 | 22 | #include <asm/mach-types.h> |
| 23 | +#include <asm/smp_plat.h> | |
| 23 | 24 | |
| 24 | 25 | #include <mach/msm_iomap.h> |
| 25 | 26 | |
| @@ -19,6 +19,7 @@ · 18 unmodified lines | ||
| 19 | 19 | #include <linux/device.h> |
| 20 | 20 | #include <linux/init.h> |
| 21 | 21 | #include <linux/debugfs.h> |
| 22 | +#include <linux/module.h> | |
| 22 | 23 | #include <linux/string.h> |
| 23 | 24 | #include <mach/vreg.h> |
| 24 | 25 | |
| @@ -19,6 +19,7 @@ · 18 unmodified lines | ||
| 19 | 19 | #include <mach/mv78xx0.h> |
| 20 | 20 | #include <mach/bridge-regs.h> |
| 21 | 21 | #include <plat/cache-feroceon-l2.h> |
| 22 | +#include <plat/ehci-orion.h> | |
| 22 | 23 | #include <plat/orion_nand.h> |
| 23 | 24 | #include <plat/time.h> |
| 24 | 25 | #include <plat/common.h> |
| @@ -169,7 +170,7 @@ void __init mv78xx0_map_io(void) · 144 unmodified lines | ||
| 169 | 170 | ****************************************************************************/ |
| 170 | 171 | void __init mv78xx0_ehci0_init(void) |
| 171 | 172 | { |
| 172 | − orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); | |
| 173 | + orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); | |
| 173 | 174 | } |
| 174 | 175 | |
| 175 | 176 | |
| @@ -24,296 +24,296 @@ · 23 unmodified lines | ||
| 24 | 24 | #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) |
| 25 | 25 | |
| 26 | 26 | #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) |
| 27 | −#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) | |
| 28 | −#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) | |
| 27 | +#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1) | |
| 28 | +#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1) | |
| 29 | 29 | #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) |
| 30 | 30 | |
| 31 | 31 | #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) |
| 32 | −#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) | |
| 33 | −#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) | |
| 32 | +#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1) | |
| 33 | +#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1) | |
| 34 | 34 | #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) |
| 35 | 35 | |
| 36 | 36 | #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) |
| 37 | −#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) | |
| 38 | −#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) | |
| 37 | +#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1) | |
| 38 | +#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1) | |
| 39 | 39 | #define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) |
| 40 | 40 | |
| 41 | 41 | #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) |
| 42 | −#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) | |
| 43 | −#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) | |
| 42 | +#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1) | |
| 43 | +#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1) | |
| 44 | 44 | #define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) |
| 45 | 45 | |
| 46 | 46 | #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) |
| 47 | −#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) | |
| 48 | −#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) | |
| 47 | +#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1) | |
| 48 | +#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1) | |
| 49 | 49 | #define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) |
| 50 | 50 | |
| 51 | 51 | #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) |
| 52 | −#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) | |
| 53 | −#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) | |
| 52 | +#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1) | |
| 53 | +#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1) | |
| 54 | 54 | #define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) |
| 55 | 55 | |
| 56 | 56 | #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) |
| 57 | −#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) | |
| 58 | −#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) | |
| 57 | +#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1) | |
| 58 | +#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1) | |
| 59 | 59 | #define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) |
| 60 | 60 | |
| 61 | 61 | #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) |
| 62 | −#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) | |
| 63 | −#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) | |
| 62 | +#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1) | |
| 63 | +#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1) | |
| 64 | 64 | #define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) |
| 65 | 65 | |
| 66 | 66 | #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) |
| 67 | −#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) | |
| 68 | −#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) | |
| 67 | +#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1) | |
| 68 | +#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1) | |
| 69 | 69 | #define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) |
| 70 | 70 | |
| 71 | 71 | #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) |
| 72 | −#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) | |
| 73 | −#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) | |
| 72 | +#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1) | |
| 73 | +#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1) | |
| 74 | 74 | #define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) |
| 75 | 75 | |
| 76 | 76 | #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) |
| 77 | −#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) | |
| 78 | −#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) | |
| 77 | +#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1) | |
| 78 | +#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1) | |
| 79 | 79 | #define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) |
| 80 | 80 | |
| 81 | 81 | #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) |
| 82 | −#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) | |
| 83 | −#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) | |
| 82 | +#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1) | |
| 83 | +#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1) | |
| 84 | 84 | #define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) |
| 85 | 85 | |
| 86 | 86 | #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) |
| 87 | −#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) | |
| 88 | −#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) | |
| 89 | −#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) | |
| 90 | −#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) | |
| 87 | +#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1) | |
| 88 | +#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1) | |
| 89 | +#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1) | |
| 90 | +#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1) | |
| 91 | 91 | #define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) |
| 92 | 92 | |
| 93 | 93 | #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) |
| 94 | −#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) | |
| 95 | −#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) | |
| 96 | −#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) | |
| 97 | −#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) | |
| 94 | +#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1) | |
| 95 | +#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1) | |
| 96 | +#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1) | |
| 97 | +#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1) | |
| 98 | 98 | #define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) |
| 99 | 99 | |
| 100 | 100 | #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) |
| 101 | −#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) | |
| 102 | −#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) | |
| 103 | −#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) | |
| 104 | −#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) | |
| 101 | +#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1) | |
| 102 | +#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1) | |
| 103 | +#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1) | |
| 104 | +#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1) | |
| 105 | 105 | #define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) |
| 106 | 106 | |
| 107 | 107 | #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) |
| 108 | −#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) | |
| 109 | −#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) | |
| 110 | −#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) | |
| 111 | −#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) | |
| 108 | +#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1) | |
| 109 | +#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1) | |
| 110 | +#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1) | |
| 111 | +#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1) | |
| 112 | 112 | #define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) |
| 113 | 113 | |
| 114 | 114 | #define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) |
| 115 | −#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) | |
| 116 | −#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) | |
| 117 | −#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) | |
| 118 | −#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) | |
| 115 | +#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1) | |
| 116 | +#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1) | |
| 117 | +#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1) | |
| 118 | +#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1) | |
| 119 | 119 | #define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) |
| 120 | 120 | |
| 121 | 121 | |
| 122 | 122 | #define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) |
| 123 | −#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) | |
| 124 | −#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) | |
| 125 | −#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) | |
| 126 | −#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) | |
| 123 | +#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1) | |
| 124 | +#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1) | |
| 125 | +#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1) | |
| 126 | +#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1) | |
| 127 | 127 | #define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) |
| 128 | 128 | |
| 129 | 129 | |
| 130 | 130 | #define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) |
| 131 | −#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) | |
| 132 | −#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) | |
| 131 | +#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1) | |
| 132 | +#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1) | |
| 133 | 133 | #define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) |
| 134 | 134 | |
| 135 | 135 | |
| 136 | 136 | |
| 137 | 137 | #define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) |
| 138 | −#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) | |
| 139 | −#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) | |
| 138 | +#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1) | |
| 139 | +#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1) | |
| 140 | 140 | #define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) |
| 141 | 141 | |
| 142 | 142 | |
| 143 | 143 | #define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) |
| 144 | −#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) | |
| 145 | −#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) | |
| 144 | +#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1) | |
| 145 | +#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0) | |
| 146 | 146 | #define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) |
| 147 | 147 | |
| 148 | 148 | |
| 149 | 149 | |
| 150 | 150 | #define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) |
| 151 | −#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) | |
| 152 | −#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) | |
| 151 | +#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1) | |
| 152 | +#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0) | |
| 153 | 153 | #define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) |
| 154 | 154 | |
| 155 | 155 | |
| 156 | 156 | |
| 157 | 157 | #define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) |
| 158 | −#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) | |
| 159 | −#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) | |
| 160 | −#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) | |
| 158 | +#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1) | |
| 159 | +#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1) | |
| 160 | +#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1) | |
| 161 | 161 | #define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) |
| 162 | 162 | |
| 163 | 163 | |
| 164 | 164 | |
| 165 | 165 | #define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) |
| 166 | −#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) | |
| 167 | −#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) | |
| 168 | −#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) | |
| 166 | +#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1) | |
| 167 | +#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1) | |
| 168 | +#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1) | |
| 169 | 169 | #define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) |
| 170 | 170 | |
| 171 | 171 | |
| 172 | 172 | #define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) |
| 173 | −#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) | |
| 174 | −#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) | |
| 173 | +#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1) | |
| 174 | +#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1) | |
| 175 | 175 | #define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) |
| 176 | 176 | |
| 177 | 177 | |
| 178 | 178 | #define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) |
| 179 | −#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) | |
| 180 | −#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) | |
| 179 | +#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1) | |
| 180 | +#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1) | |
| 181 | 181 | #define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) |
| 182 | 182 | |
| 183 | 183 | |
| 184 | 184 | #define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) |
| 185 | −#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) | |
| 186 | −#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) | |
| 185 | +#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1) | |
| 186 | +#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1) | |
| 187 | 187 | #define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) |
| 188 | 188 | |
| 189 | 189 | |
| 190 | 190 | #define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) |
| 191 | −#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) | |
| 192 | −#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) | |
| 191 | +#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1) | |
| 192 | +#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1) | |
| 193 | 193 | #define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) |
| 194 | 194 | |
| 195 | 195 | |
| 196 | 196 | #define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) |
| 197 | −#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) | |
| 198 | −#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) | |
| 197 | +#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1) | |
| 198 | +#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1) | |
| 199 | 199 | #define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) |
| 200 | 200 | |
| 201 | 201 | #define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) |
| 202 | −#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) | |
| 203 | −#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) | |
| 204 | −#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) | |
| 202 | +#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1) | |
| 203 | +#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1) | |
| 204 | +#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1) | |
| 205 | 205 | #define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) |
| 206 | 206 | |
| 207 | 207 | #define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) |
| 208 | −#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) | |
| 208 | +#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1) | |
| 209 | 209 | #define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) |
| 210 | 210 | |
| 211 | 211 | #define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) |
| 212 | −#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) | |
| 213 | −#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) | |
| 212 | +#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1) | |
| 213 | +#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1) | |
| 214 | 214 | #define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) |
| 215 | 215 | |
| 216 | 216 | |
| 217 | 217 | #define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) |
| 218 | −#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) | |
| 219 | −#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) | |
| 220 | −#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) | |
| 218 | +#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1) | |
| 219 | +#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1) | |
| 220 | +#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1) | |
| 221 | 221 | #define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) |
| 222 | 222 | |
| 223 | 223 | |
| 224 | 224 | #define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) |
| 225 | −#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) | |
| 226 | −#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) | |
| 225 | +#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1) | |
| 226 | +#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1) | |
| 227 | 227 | #define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) |
| 228 | 228 | |
| 229 | 229 | |
| 230 | 230 | |
| 231 | 231 | #define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) |
| 232 | −#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) | |
| 233 | −#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) | |
| 232 | +#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1) | |
| 233 | +#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1) | |
| 234 | 234 | #define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) |
| 235 | 235 | |
| 236 | 236 | |
| 237 | 237 | |
| 238 | 238 | #define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) |
| 239 | −#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) | |
| 240 | −#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) | |
| 239 | +#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1) | |
| 240 | +#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1) | |
| 241 | 241 | #define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) |
| 242 | 242 | |
| 243 | 243 | #define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) |
| 244 | −#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) | |
| 245 | −#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) | |
| 246 | −#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) | |
| 244 | +#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1) | |
| 245 | +#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1) | |
| 246 | +#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1) | |
| 247 | 247 | #define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) |
| 248 | 248 | |
| 249 | 249 | |
| 250 | 250 | #define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) |
| 251 | −#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) | |
| 252 | −#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) | |
| 253 | −#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) | |
| 254 | −#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) | |
| 251 | +#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1) | |
| 252 | +#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1) | |
| 253 | +#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1) | |
| 254 | +#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1) | |
| 255 | 255 | #define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) |
| 256 | 256 | |
| 257 | 257 | |
| 258 | 258 | |
| 259 | 259 | |
| 260 | 260 | #define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) |
| 261 | −#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) | |
| 262 | −#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) | |
| 263 | −#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) | |
| 264 | −#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) | |
| 261 | +#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1) | |
| 262 | +#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1) | |
| 263 | +#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1) | |
| 264 | +#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1) | |
| 265 | 265 | #define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) |
| 266 | 266 | |
| 267 | 267 | |
| 268 | 268 | |
| 269 | 269 | |
| 270 | 270 | #define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) |
| 271 | −#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) | |
| 272 | −#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) | |
| 273 | −#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) | |
| 274 | −#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) | |
| 271 | +#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1) | |
| 272 | +#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1) | |
| 273 | +#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1) | |
| 274 | +#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1) | |
| 275 | 275 | #define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) |
| 276 | 276 | |
| 277 | 277 | |
| 278 | 278 | |
| 279 | 279 | #define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) |
| 280 | −#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) | |
| 280 | +#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1) | |
| 281 | 281 | #define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) |
| 282 | 282 | |
| 283 | 283 | |
| 284 | 284 | |
| 285 | 285 | #define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) |
| 286 | −#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) | |
| 286 | +#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1) | |
| 287 | 287 | #define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) |
| 288 | 288 | |
| 289 | 289 | |
| 290 | 290 | |
| 291 | 291 | #define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) |
| 292 | −#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) | |
| 292 | +#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1) | |
| 293 | 293 | #define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) |
| 294 | 294 | |
| 295 | 295 | |
| 296 | 296 | |
| 297 | 297 | #define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) |
| 298 | −#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) | |
| 298 | +#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1) | |
| 299 | 299 | #define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) |
| 300 | 300 | |
| 301 | 301 | |
| 302 | 302 | |
| 303 | 303 | #define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) |
| 304 | −#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) | |
| 304 | +#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1) | |
| 305 | 305 | #define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) |
| 306 | 306 | |
| 307 | 307 | |
| 308 | 308 | |
| 309 | 309 | #define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) |
| 310 | −#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) | |
| 311 | −#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) | |
| 310 | +#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1) | |
| 311 | +#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1) | |
| 312 | 312 | #define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) |
| 313 | 313 | |
| 314 | 314 | |
| 315 | 315 | #define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) |
| 316 | −#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) | |
| 316 | +#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1) | |
| 317 | 317 | #define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) |
| 318 | 318 | |
| 319 | 319 | |
| @@ -323,14 +323,14 @@ · 3 unmodified lines | ||
| 323 | 323 | |
| 324 | 324 | |
| 325 | 325 | #define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) |
| 326 | −#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) | |
| 326 | +#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1) | |
| 327 | 327 | #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) |
| 328 | 328 | |
| 329 | 329 | |
| 330 | 330 | |
| 331 | 331 | #define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) |
| 332 | −#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) | |
| 333 | −#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) | |
| 332 | +#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1) | |
| 333 | +#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1) | |
| 334 | 334 | #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) |
| 335 | 335 | |
| 336 | 336 | |
| @@ -1,244 +0,0 @@ | ||
| 1 | −if ARCH_MX5 | |
| 2 | − | |
| 3 | −# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single | |
| 4 | −# image. So for most time, SOC_IMX50/51/53 should be used. | |
| 5 | − | |
| 6 | −config ARCH_MX51 | |
| 7 | − bool | |
| 8 | − | |
| 9 | −config ARCH_MX50 | |
| 10 | − bool | |
| 11 | − | |
| 12 | −config ARCH_MX53 | |
| 13 | − bool | |
| 14 | − | |
| 15 | −config SOC_IMX50 | |
| 16 | − bool | |
| 17 | − select CPU_V7 | |
| 18 | − select ARM_L1_CACHE_SHIFT_6 | |
| 19 | − select MXC_TZIC | |
| 20 | − select ARCH_MXC_IOMUX_V3 | |
| 21 | − select ARCH_MXC_AUDMUX_V2 | |
| 22 | − select ARCH_HAS_CPUFREQ | |
| 23 | − select ARCH_MX50 | |
| 24 | − | |
| 25 | −config SOC_IMX51 | |
| 26 | − bool | |
| 27 | − select CPU_V7 | |
| 28 | − select ARM_L1_CACHE_SHIFT_6 | |
| 29 | − select MXC_TZIC | |
| 30 | − select ARCH_MXC_IOMUX_V3 | |
| 31 | − select ARCH_MXC_AUDMUX_V2 | |
| 32 | − select ARCH_HAS_CPUFREQ | |
| 33 | − select ARCH_MX51 | |
| 34 | − | |
| 35 | −config SOC_IMX53 | |
| 36 | − bool | |
| 37 | − select CPU_V7 | |
| 38 | − select ARM_L1_CACHE_SHIFT_6 | |
| 39 | − select MXC_TZIC | |
| 40 | − select ARCH_MXC_IOMUX_V3 | |
| 41 | − select ARCH_MX53 | |
| 42 | − | |
| 43 | −#comment "i.MX50 machines:" | |
| 44 | − | |
| 45 | −config MACH_MX50_RDP | |
| 46 | − bool "Support MX50 reference design platform" | |
| 47 | − depends on BROKEN | |
| 48 | − select SOC_IMX50 | |
| 49 | − select IMX_HAVE_PLATFORM_IMX_I2C | |
| 50 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 51 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 52 | − select IMX_HAVE_PLATFORM_SPI_IMX | |
| 53 | − help | |
| 54 | − Include support for MX50 reference design platform (RDP) board. This | |
| 55 | − includes specific configurations for the board and its peripherals. | |
| 56 | − | |
| 57 | −comment "i.MX51 machines:" | |
| 58 | − | |
| 59 | −config MACH_IMX51_DT | |
| 60 | − bool "Support i.MX51 platforms from device tree" | |
| 61 | − select SOC_IMX51 | |
| 62 | − select USE_OF | |
| 63 | − select MACH_MX51_BABBAGE | |
| 64 | − help | |
| 65 | − Include support for Freescale i.MX51 based platforms | |
| 66 | − using the device tree for discovery | |
| 67 | − | |
| 68 | −config MACH_MX51_BABBAGE | |
| 69 | − bool "Support MX51 BABBAGE platforms" | |
| 70 | − select SOC_IMX51 | |
| 71 | − select IMX_HAVE_PLATFORM_FSL_USB2_UDC | |
| 72 | − select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 73 | − select IMX_HAVE_PLATFORM_IMX_I2C | |
| 74 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 75 | − select IMX_HAVE_PLATFORM_MXC_EHCI | |
| 76 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 77 | − select IMX_HAVE_PLATFORM_SPI_IMX | |
| 78 | − help | |
| 79 | − Include support for MX51 Babbage platform, also known as MX51EVK in | |
| 80 | − u-boot. This includes specific configurations for the board and its | |
| 81 | − peripherals. | |
| 82 | − | |
| 83 | −config MACH_MX51_3DS | |
| 84 | − bool "Support MX51PDK (3DS)" | |
| 85 | − select SOC_IMX51 | |
| 86 | − select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 87 | − select IMX_HAVE_PLATFORM_IMX_KEYPAD | |
| 88 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 89 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 90 | − select IMX_HAVE_PLATFORM_SPI_IMX | |
| 91 | − select MXC_DEBUG_BOARD | |
| 92 | − help | |
| 93 | − Include support for MX51PDK (3DS) platform. This includes specific | |
| 94 | − configurations for the board and its peripherals. | |
| 95 | − | |
| 96 | −config MACH_EUKREA_CPUIMX51 | |
| 97 | − bool "Support Eukrea CPUIMX51 module" | |
| 98 | − select SOC_IMX51 | |
| 99 | − select IMX_HAVE_PLATFORM_FSL_USB2_UDC | |
| 100 | − select IMX_HAVE_PLATFORM_IMX_I2C | |
| 101 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 102 | − select IMX_HAVE_PLATFORM_MXC_EHCI | |
| 103 | − select IMX_HAVE_PLATFORM_MXC_NAND | |
| 104 | − select IMX_HAVE_PLATFORM_SPI_IMX | |
| 105 | − help | |
| 106 | − Include support for Eukrea CPUIMX51 platform. This includes | |
| 107 | − specific configurations for the module and its peripherals. | |
| 108 | − | |
| 109 | −choice | |
| 110 | − prompt "Baseboard" | |
| 111 | − depends on MACH_EUKREA_CPUIMX51 | |
| 112 | − default MACH_EUKREA_MBIMX51_BASEBOARD | |
| 113 | − | |
| 114 | −config MACH_EUKREA_MBIMX51_BASEBOARD | |
| 115 | − prompt "Eukrea MBIMX51 development board" | |
| 116 | − bool | |
| 117 | − select IMX_HAVE_PLATFORM_IMX_KEYPAD | |
| 118 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 119 | − select LEDS_GPIO_REGISTER | |
| 120 | − help | |
| 121 | − This adds board specific devices that can be found on Eukrea's | |
| 122 | − MBIMX51 evaluation board. | |
| 123 | − | |
| 124 | −endchoice | |
| 125 | − | |
| 126 | −config MACH_EUKREA_CPUIMX51SD | |
| 127 | − bool "Support Eukrea CPUIMX51SD module" | |
| 128 | − select SOC_IMX51 | |
| 129 | − select IMX_HAVE_PLATFORM_FSL_USB2_UDC | |
| 130 | − select IMX_HAVE_PLATFORM_IMX_I2C | |
| 131 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 132 | − select IMX_HAVE_PLATFORM_MXC_EHCI | |
| 133 | − select IMX_HAVE_PLATFORM_MXC_NAND | |
| 134 | − select IMX_HAVE_PLATFORM_SPI_IMX | |
| 135 | − help | |
| 136 | − Include support for Eukrea CPUIMX51SD platform. This includes | |
| 137 | − specific configurations for the module and its peripherals. | |
| 138 | − | |
| 139 | −choice | |
| 140 | − prompt "Baseboard" | |
| 141 | − depends on MACH_EUKREA_CPUIMX51SD | |
| 142 | − default MACH_EUKREA_MBIMXSD51_BASEBOARD | |
| 143 | − | |
| 144 | −config MACH_EUKREA_MBIMXSD51_BASEBOARD | |
| 145 | − prompt "Eukrea MBIMXSD development board" | |
| 146 | − bool | |
| 147 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 148 | − select LEDS_GPIO_REGISTER | |
| 149 | − help | |
| 150 | − This adds board specific devices that can be found on Eukrea's | |
| 151 | − MBIMXSD evaluation board. | |
| 152 | − | |
| 153 | −endchoice | |
| 154 | − | |
| 155 | −config MX51_EFIKA_COMMON | |
| 156 | − bool | |
| 157 | − select SOC_IMX51 | |
| 158 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 159 | − select IMX_HAVE_PLATFORM_MXC_EHCI | |
| 160 | − select IMX_HAVE_PLATFORM_PATA_IMX | |
| 161 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 162 | − select IMX_HAVE_PLATFORM_SPI_IMX | |
| 163 | − select MXC_ULPI if USB_ULPI | |
| 164 | − | |
| 165 | −config MACH_MX51_EFIKAMX | |
| 166 | − bool "Support MX51 Genesi Efika MX nettop" | |
| 167 | − select LEDS_GPIO_REGISTER | |
| 168 | − select MX51_EFIKA_COMMON | |
| 169 | − help | |
| 170 | − Include support for Genesi Efika MX nettop. This includes specific | |
| 171 | − configurations for the board and its peripherals. | |
| 172 | − | |
| 173 | −config MACH_MX51_EFIKASB | |
| 174 | − bool "Support MX51 Genesi Efika Smartbook" | |
| 175 | − select LEDS_GPIO_REGISTER | |
| 176 | − select MX51_EFIKA_COMMON | |
| 177 | − help | |
| 178 | − Include support for Genesi Efika Smartbook. This includes specific | |
| 179 | − configurations for the board and its peripherals. | |
| 180 | − | |
| 181 | −comment "i.MX53 machines:" | |
| 182 | − | |
| 183 | −config MACH_IMX53_DT | |
| 184 | − bool "Support i.MX53 platforms from device tree" | |
| 185 | − select SOC_IMX53 | |
| 186 | − select USE_OF | |
| 187 | − select MACH_MX53_ARD | |
| 188 | − select MACH_MX53_EVK | |
| 189 | − select MACH_MX53_LOCO | |
| 190 | − select MACH_MX53_SMD | |
| 191 | − help | |
| 192 | − Include support for Freescale i.MX53 based platforms | |
| 193 | − using the device tree for discovery | |
| 194 | − | |
| 195 | −config MACH_MX53_EVK | |
| 196 | − bool "Support MX53 EVK platforms" | |
| 197 | − select SOC_IMX53 | |
| 198 | − select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 199 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 200 | − select IMX_HAVE_PLATFORM_IMX_I2C | |
| 201 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 202 | − select IMX_HAVE_PLATFORM_SPI_IMX | |
| 203 | − select LEDS_GPIO_REGISTER | |
| 204 | − help | |
| 205 | − Include support for MX53 EVK platform. This includes specific | |
| 206 | − configurations for the board and its peripherals. | |
| 207 | − | |
| 208 | −config MACH_MX53_SMD | |
| 209 | − bool "Support MX53 SMD platforms" | |
| 210 | − select SOC_IMX53 | |
| 211 | − select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 212 | − select IMX_HAVE_PLATFORM_IMX_I2C | |
| 213 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 214 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 215 | − help | |
| 216 | − Include support for MX53 SMD platform. This includes specific | |
| 217 | − configurations for the board and its peripherals. | |
| 218 | − | |
| 219 | −config MACH_MX53_LOCO | |
| 220 | − bool "Support MX53 LOCO platforms" | |
| 221 | − select SOC_IMX53 | |
| 222 | − select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 223 | − select IMX_HAVE_PLATFORM_IMX_I2C | |
| 224 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 225 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 226 | − select IMX_HAVE_PLATFORM_GPIO_KEYS | |
| 227 | − select LEDS_GPIO_REGISTER | |
| 228 | − help | |
| 229 | − Include support for MX53 LOCO platform. This includes specific | |
| 230 | − configurations for the board and its peripherals. | |
| 231 | − | |
| 232 | −config MACH_MX53_ARD | |
| 233 | − bool "Support MX53 ARD platforms" | |
| 234 | − select SOC_IMX53 | |
| 235 | − select IMX_HAVE_PLATFORM_IMX2_WDT | |
| 236 | − select IMX_HAVE_PLATFORM_IMX_I2C | |
| 237 | − select IMX_HAVE_PLATFORM_IMX_UART | |
| 238 | − select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |
| 239 | − select IMX_HAVE_PLATFORM_GPIO_KEYS | |
| 240 | − help | |
| 241 | − Include support for MX53 ARD platform. This includes specific | |
| 242 | − configurations for the board and its peripherals. | |
| 243 | − | |
| 244 | −endif | |
| @@ -1,26 +0,0 @@ | ||
| 1 | −# | |
| 2 | −# Makefile for the linux kernel. | |
| 3 | −# | |
| 4 | − | |
| 5 | −# Object file lists. | |
| 6 | −obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o | |
| 7 | − | |
| 8 | −obj-$(CONFIG_PM) += pm-imx5.o | |
| 9 | −obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o | |
| 10 | −obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o | |
| 11 | −obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o | |
| 12 | −obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o | |
| 13 | −obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o | |
| 14 | −obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o | |
| 15 | −obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o | |
| 16 | −obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o | |
| 17 | −obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o | |
| 18 | −obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o | |
| 19 | −obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o | |
| 20 | −obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o | |
| 21 | −obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o | |
| 22 | −obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o | |
| 23 | −obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o | |
| 24 | − | |
| 25 | −obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o | |
| 26 | −obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o | |
| @@ -1,9 +0,0 @@ | ||
| 1 | − zreladdr-$(CONFIG_ARCH_MX50) += 0x70008000 | |
| 2 | −params_phys-$(CONFIG_ARCH_MX50) := 0x70000100 | |
| 3 | −initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000 | |
| 4 | − zreladdr-$(CONFIG_ARCH_MX51) += 0x90008000 | |
| 5 | −params_phys-$(CONFIG_ARCH_MX51) := 0x90000100 | |
| 6 | −initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000 | |
| 7 | − zreladdr-$(CONFIG_ARCH_MX53) += 0x70008000 | |
| 8 | −params_phys-$(CONFIG_ARCH_MX53) := 0x70000100 | |
| 9 | −initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000 | |
| @@ -1,83 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 3 | − * | |
| 4 | − * The code contained herein is licensed under the GNU General Public | |
| 5 | − * License. You may obtain a copy of the GNU General Public License | |
| 6 | − * Version 2 or later at the following locations: | |
| 7 | − * | |
| 8 | − * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | − * http://www.gnu.org/copyleft/gpl.html | |
| 10 | − */ | |
| 11 | −#include <linux/suspend.h> | |
| 12 | −#include <linux/clk.h> | |
| 13 | −#include <linux/io.h> | |
| 14 | −#include <linux/err.h> | |
| 15 | −#include <asm/cacheflush.h> | |
| 16 | −#include <asm/tlbflush.h> | |
| 17 | −#include <mach/common.h> | |
| 18 | −#include <mach/hardware.h> | |
| 19 | −#include "crm_regs.h" | |
| 20 | − | |
| 21 | −static struct clk *gpc_dvfs_clk; | |
| 22 | − | |
| 23 | −static int mx5_suspend_prepare(void) | |
| 24 | −{ | |
| 25 | − return clk_enable(gpc_dvfs_clk); | |
| 26 | −} | |
| 27 | − | |
| 28 | −static int mx5_suspend_enter(suspend_state_t state) | |
| 29 | −{ | |
| 30 | − switch (state) { | |
| 31 | − case PM_SUSPEND_MEM: | |
| 32 | − mx5_cpu_lp_set(STOP_POWER_OFF); | |
| 33 | − break; | |
| 34 | − case PM_SUSPEND_STANDBY: | |
| 35 | − mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | |
| 36 | − break; | |
| 37 | − default: | |
| 38 | − return -EINVAL; | |
| 39 | − } | |
| 40 | − | |
| 41 | − if (state == PM_SUSPEND_MEM) { | |
| 42 | − local_flush_tlb_all(); | |
| 43 | − flush_cache_all(); | |
| 44 | − | |
| 45 | − /*clear the EMPGC0/1 bits */ | |
| 46 | − __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); | |
| 47 | − __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); | |
| 48 | − } | |
| 49 | − cpu_do_idle(); | |
| 50 | − return 0; | |
| 51 | −} | |
| 52 | − | |
| 53 | −static void mx5_suspend_finish(void) | |
| 54 | −{ | |
| 55 | − clk_disable(gpc_dvfs_clk); | |
| 56 | −} | |
| 57 | − | |
| 58 | −static int mx5_pm_valid(suspend_state_t state) | |
| 59 | −{ | |
| 60 | − return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); | |
| 61 | −} | |
| 62 | − | |
| 63 | −static const struct platform_suspend_ops mx5_suspend_ops = { | |
| 64 | − .valid = mx5_pm_valid, | |
| 65 | − .prepare = mx5_suspend_prepare, | |
| 66 | − .enter = mx5_suspend_enter, | |
| 67 | − .finish = mx5_suspend_finish, | |
| 68 | −}; | |
| 69 | − | |
| 70 | −static int __init mx5_pm_init(void) | |
| 71 | −{ | |
| 72 | − if (gpc_dvfs_clk == NULL) | |
| 73 | − gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | |
| 74 | − | |
| 75 | − if (!IS_ERR(gpc_dvfs_clk)) { | |
| 76 | − if (cpu_is_mx51()) | |
| 77 | − suspend_set_ops(&mx5_suspend_ops); | |
| 78 | − } else | |
| 79 | − return -EPERM; | |
| 80 | − | |
| 81 | − return 0; | |
| 82 | −} | |
| 83 | −device_initcall(mx5_pm_init); | |
| @@ -33,7 +33,6 @@ config ARCH_OMAP3 · 32 unmodified lines | ||
| 33 | 33 | default y |
| 34 | 34 | select CPU_V7 |
| 35 | 35 | select USB_ARCH_HAS_EHCI |
| 36 | − select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 | |
| 37 | 36 | select ARCH_HAS_OPP |
| 38 | 37 | select PM_OPP if PM |
| 39 | 38 | select ARM_CPU_SUSPEND if PM |
| @@ -214,13 +213,12 @@ config MACH_OMAP3_PANDORA · 174 unmodified lines | ||
| 214 | 213 | depends on ARCH_OMAP3 |
| 215 | 214 | default y |
| 216 | 215 | select OMAP_PACKAGE_CBB |
| 217 | − select REGULATOR_FIXED_VOLTAGE | |
| 216 | + select REGULATOR_FIXED_VOLTAGE if REGULATOR | |
| 218 | 217 | |
| 219 | 218 | config MACH_OMAP3_TOUCHBOOK |
| 220 | 219 | bool "OMAP3 Touch Book" |
| 221 | 220 | depends on ARCH_OMAP3 |
| 222 | 221 | default y |
| 223 | − select BACKLIGHT_CLASS_DEVICE | |
| 224 | 222 | |
| 225 | 223 | config MACH_OMAP_3430SDP |
| 226 | 224 | bool "OMAP 3430 SDP board" |
| @@ -266,7 +264,7 @@ config MACH_OMAP_ZOOM2 · 39 unmodified lines | ||
| 266 | 264 | select SERIAL_8250 |
| 267 | 265 | select SERIAL_CORE_CONSOLE |
| 268 | 266 | select SERIAL_8250_CONSOLE |
| 269 | − select REGULATOR_FIXED_VOLTAGE | |
| 267 | + select REGULATOR_FIXED_VOLTAGE if REGULATOR | |
| 270 | 268 | |
| 271 | 269 | config MACH_OMAP_ZOOM3 |
| 272 | 270 | bool "OMAP3630 Zoom3 board" |
| @@ -276,7 +274,7 @@ config MACH_OMAP_ZOOM3 · 3 unmodified lines | ||
| 276 | 274 | select SERIAL_8250 |
| 277 | 275 | select SERIAL_CORE_CONSOLE |
| 278 | 276 | select SERIAL_8250_CONSOLE |
| 279 | − select REGULATOR_FIXED_VOLTAGE | |
| 277 | + select REGULATOR_FIXED_VOLTAGE if REGULATOR | |
| 280 | 278 | |
| 281 | 279 | config MACH_CM_T35 |
| 282 | 280 | bool "CompuLab CM-T35/CM-T3730 modules" |
| @@ -335,7 +333,7 @@ config MACH_OMAP_4430SDP · 52 unmodified lines | ||
| 335 | 333 | depends on ARCH_OMAP4 |
| 336 | 334 | select OMAP_PACKAGE_CBL |
| 337 | 335 | select OMAP_PACKAGE_CBS |
| 338 | − select REGULATOR_FIXED_VOLTAGE | |
| 336 | + select REGULATOR_FIXED_VOLTAGE if REGULATOR | |
| 339 | 337 | |
| 340 | 338 | config MACH_OMAP4_PANDA |
| 341 | 339 | bool "OMAP4 Panda Board" |
| @@ -343,7 +341,7 @@ config MACH_OMAP4_PANDA · 1 unmodified line | ||
| 343 | 341 | depends on ARCH_OMAP4 |
| 344 | 342 | select OMAP_PACKAGE_CBL |
| 345 | 343 | select OMAP_PACKAGE_CBS |
| 346 | − select REGULATOR_FIXED_VOLTAGE | |
| 344 | + select REGULATOR_FIXED_VOLTAGE if REGULATOR | |
| 347 | 345 | |
| 348 | 346 | config OMAP3_EMU |
| 349 | 347 | bool "OMAP3 debugging peripherals" |
| @@ -11,9 +11,9 @@ hwmod-common = omap_hwmod.o \ · 10 unmodified lines | ||
| 11 | 11 | omap_hwmod_common_data.o |
| 12 | 12 | clock-common = clock.o clock_common_data.o \ |
| 13 | 13 | clkt_dpll.o clkt_clksel.o |
| 14 | −secure-common = omap-smc.o omap-secure.o | |
| 14 | +secure-common = omap-smc.o omap-secure.o | |
| 15 | 15 | |
| 16 | −obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) | |
| 16 | +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) | |
| 17 | 17 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) |
| 18 | 18 | obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) |
| 19 | 19 | |
| @@ -52,8 +52,9 @@ · 51 unmodified lines | ||
| 52 | 52 | #define ETH_KS8851_QUART 138 |
| 53 | 53 | #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 |
| 54 | 54 | #define OMAP4_SFH7741_ENABLE_GPIO 188 |
| 55 | −#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ | |
| 55 | +#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */ | |
| 56 | 56 | #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ |
| 57 | +#define HDMI_GPIO_HPD 63 /* Hotplug detect */ | |
| 57 | 58 | #define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */ |
| 58 | 59 | #define DLP_POWER_ON_GPIO 40 |
| 59 | 60 | |
| @@ -603,8 +604,9 @@ static void __init omap_sfh7741prox_init(void) · 543 unmodified lines | ||
| 603 | 604 | } |
| 604 | 605 | |
| 605 | 606 | static struct gpio sdp4430_hdmi_gpios[] = { |
| 606 | − { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, | |
| 607 | + { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, | |
| 607 | 608 | { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, |
| 609 | + { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, | |
| 608 | 610 | }; |
| 609 | 611 | |
| 610 | 612 | static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) |
| @@ -621,8 +623,7 @@ static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) · 10 unmodified lines | ||
| 621 | 623 | |
| 622 | 624 | static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) |
| 623 | 625 | { |
| 624 | − gpio_free(HDMI_GPIO_LS_OE); | |
| 625 | − gpio_free(HDMI_GPIO_HPD); | |
| 626 | + gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios)); | |
| 626 | 627 | } |
| 627 | 628 | |
| 628 | 629 | static struct nokia_dsi_panel_data dsi1_panel = { |
| @@ -738,6 +739,10 @@ static void sdp4430_lcd_init(void) · 109 unmodified lines | ||
| 738 | 739 | pr_err("%s: Could not get lcd2_reset_gpio\n", __func__); |
| 739 | 740 | } |
| 740 | 741 | |
| 742 | +static struct omap_dss_hdmi_data sdp4430_hdmi_data = { | |
| 743 | + .hpd_gpio = HDMI_GPIO_HPD, | |
| 744 | +}; | |
| 745 | + | |
| 741 | 746 | static struct omap_dss_device sdp4430_hdmi_device = { |
| 742 | 747 | .name = "hdmi", |
| 743 | 748 | .driver_name = "hdmi_panel", |
| @@ -745,6 +750,7 @@ static struct omap_dss_device sdp4430_hdmi_device = { · 1 unmodified line | ||
| 745 | 750 | .platform_enable = sdp4430_panel_enable_hdmi, |
| 746 | 751 | .platform_disable = sdp4430_panel_disable_hdmi, |
| 747 | 752 | .channel = OMAP_DSS_CHANNEL_DIGIT, |
| 753 | + .data = &sdp4430_hdmi_data, | |
| 748 | 754 | }; |
| 749 | 755 | |
| 750 | 756 | static struct picodlp_panel_data sdp4430_picodlp_pdata = { |
| @@ -808,7 +814,7 @@ static struct omap_dss_board_info sdp4430_dss_data = { · 57 unmodified lines | ||
| 808 | 814 | .default_device = &sdp4430_lcd_device, |
| 809 | 815 | }; |
| 810 | 816 | |
| 811 | −static void omap_4430sdp_display_init(void) | |
| 817 | +static void __init omap_4430sdp_display_init(void) | |
| 812 | 818 | { |
| 813 | 819 | int r; |
| 814 | 820 | |
| @@ -829,6 +835,10 @@ static void omap_4430sdp_display_init(void) · 14 unmodified lines | ||
| 829 | 835 | omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); |
| 830 | 836 | else |
| 831 | 837 | omap_hdmi_init(0); |
| 838 | + | |
| 839 | + omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); | |
| 840 | + omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); | |
| 841 | + omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); | |
| 832 | 842 | } |
| 833 | 843 | |
| 834 | 844 | #ifdef CONFIG_OMAP_MUX |
| @@ -841,7 +851,7 @@ static struct omap_board_mux board_mux[] __initdata = { · 6 unmodified lines | ||
| 841 | 851 | #define board_mux NULL |
| 842 | 852 | #endif |
| 843 | 853 | |
| 844 | −static void omap4_sdp4430_wifi_mux_init(void) | |
| 854 | +static void __init omap4_sdp4430_wifi_mux_init(void) | |
| 845 | 855 | { |
| 846 | 856 | omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT | |
| 847 | 857 | OMAP_PIN_OFF_WAKEUPENABLE); |
| @@ -868,12 +878,17 @@ static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = { · 20 unmodified lines | ||
| 868 | 878 | .board_tcxo_clock = WL12XX_TCXOCLOCK_26, |
| 869 | 879 | }; |
| 870 | 880 | |
| 871 | −static void omap4_sdp4430_wifi_init(void) | |
| 881 | +static void __init omap4_sdp4430_wifi_init(void) | |
| 872 | 882 | { |
| 883 | + int ret; | |
| 884 | + | |
| 873 | 885 | omap4_sdp4430_wifi_mux_init(); |
| 874 | − if (wl12xx_set_platform_data(&omap4_sdp4430_wlan_data)) | |
| 875 | − pr_err("Error setting wl12xx data\n"); | |
| 876 | − platform_device_register(&omap_vwlan_device); | |
| 886 | + ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data); | |
| 887 | + if (ret) | |
| 888 | + pr_err("Error setting wl12xx data: %d\n", ret); | |
| 889 | + ret = platform_device_register(&omap_vwlan_device); | |
| 890 | + if (ret) | |
| 891 | + pr_err("Error registering wl12xx device: %d\n", ret); | |
| 877 | 892 | } |
| 878 | 893 | |
| 879 | 894 | static void __init omap_4430sdp_init(void) |
| @@ -437,7 +437,7 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = { · 436 unmodified lines | ||
| 437 | 437 | .reset_gpio_port[2] = -EINVAL |
| 438 | 438 | }; |
| 439 | 439 | |
| 440 | −static void cm_t35_init_usbh(void) | |
| 440 | +static void __init cm_t35_init_usbh(void) | |
| 441 | 441 | { |
| 442 | 442 | int err; |
| 443 | 443 | |
| @@ -17,6 +17,7 @@ · 16 unmodified lines | ||
| 17 | 17 | #include <linux/i2c/twl.h> |
| 18 | 18 | |
| 19 | 19 | #include <mach/hardware.h> |
| 20 | +#include <asm/hardware/gic.h> | |
| 20 | 21 | #include <asm/mach/arch.h> |
| 21 | 22 | |
| 22 | 23 | #include <plat/board.h> |
| @@ -102,6 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") · 79 unmodified lines | ||
| 102 | 103 | .map_io = omap242x_map_io, |
| 103 | 104 | .init_early = omap2420_init_early, |
| 104 | 105 | .init_irq = omap2_init_irq, |
| 106 | + .handle_irq = omap2_intc_handle_irq, | |
| 105 | 107 | .init_machine = omap_generic_init, |
| 106 | 108 | .timer = &omap2_timer, |
| 107 | 109 | .dt_compat = omap242x_boards_compat, |
| @@ -141,6 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") · 33 unmodified lines | ||
| 141 | 143 | .map_io = omap3_map_io, |
| 142 | 144 | .init_early = omap3430_init_early, |
| 143 | 145 | .init_irq = omap3_init_irq, |
| 146 | + .handle_irq = omap3_intc_handle_irq, | |
| 144 | 147 | .init_machine = omap3_init, |
| 145 | 148 | .timer = &omap3_timer, |
| 146 | 149 | .dt_compat = omap3_boards_compat, |
| @@ -160,6 +163,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") · 13 unmodified lines | ||
| 160 | 163 | .map_io = omap4_map_io, |
| 161 | 164 | .init_early = omap4430_init_early, |
| 162 | 165 | .init_irq = gic_init_irq, |
| 166 | + .handle_irq = gic_handle_irq, | |
| 163 | 167 | .init_machine = omap4_init, |
| 164 | 168 | .timer = &omap4_timer, |
| 165 | 169 | .dt_compat = omap4_boards_compat, |
| @@ -617,6 +617,21 @@ static struct gpio omap3_evm_ehci_gpios[] __initdata = { · 616 unmodified lines | ||
| 617 | 617 | { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" }, |
| 618 | 618 | }; |
| 619 | 619 | |
| 620 | +static void __init omap3_evm_wl12xx_init(void) | |
| 621 | +{ | |
| 622 | +#ifdef CONFIG_WL12XX_PLATFORM_DATA | |
| 623 | + int ret; | |
| 624 | + | |
| 625 | + /* WL12xx WLAN Init */ | |
| 626 | + ret = wl12xx_set_platform_data(&omap3evm_wlan_data); | |
| 627 | + if (ret) | |
| 628 | + pr_err("error setting wl12xx data: %d\n", ret); | |
| 629 | + ret = platform_device_register(&omap3evm_wlan_regulator); | |
| 630 | + if (ret) | |
| 631 | + pr_err("error registering wl12xx device: %d\n", ret); | |
| 632 | +#endif | |
| 633 | +} | |
| 634 | + | |
| 620 | 635 | static void __init omap3_evm_init(void) |
| 621 | 636 | { |
| 622 | 637 | omap3_evm_get_revision(); |
| @@ -665,13 +680,7 @@ static void __init omap3_evm_init(void) · 42 unmodified lines | ||
| 665 | 680 | omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); |
| 666 | 681 | omap3evm_init_smsc911x(); |
| 667 | 682 | omap3_evm_display_init(); |
| 668 | − | |
| 669 | −#ifdef CONFIG_WL12XX_PLATFORM_DATA | |
| 670 | − /* WL12xx WLAN Init */ | |
| 671 | − if (wl12xx_set_platform_data(&omap3evm_wlan_data)) | |
| 672 | − pr_err("error setting wl12xx data\n"); | |
| 673 | − platform_device_register(&omap3evm_wlan_regulator); | |
| 674 | −#endif | |
| 683 | + omap3_evm_wl12xx_init(); | |
| 675 | 684 | } |
| 676 | 685 | |
| 677 | 686 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") |
| @@ -51,8 +51,9 @@ · 50 unmodified lines | ||
| 51 | 51 | #define GPIO_HUB_NRESET 62 |
| 52 | 52 | #define GPIO_WIFI_PMENA 43 |
| 53 | 53 | #define GPIO_WIFI_IRQ 53 |
| 54 | −#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ | |
| 54 | +#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */ | |
| 55 | 55 | #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ |
| 56 | +#define HDMI_GPIO_HPD 63 /* Hotplug detect */ | |
| 56 | 57 | |
| 57 | 58 | /* wl127x BT, FM, GPS connectivity chip */ |
| 58 | 59 | static int wl1271_gpios[] = {46, -1, -1}; |
| @@ -413,8 +414,9 @@ int __init omap4_panda_dvi_init(void) · 354 unmodified lines | ||
| 413 | 414 | } |
| 414 | 415 | |
| 415 | 416 | static struct gpio panda_hdmi_gpios[] = { |
| 416 | − { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, | |
| 417 | + { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, | |
| 417 | 418 | { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, |
| 419 | + { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, | |
| 418 | 420 | }; |
| 419 | 421 | |
| 420 | 422 | static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) |
| @@ -431,10 +433,13 @@ static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) · 10 unmodified lines | ||
| 431 | 433 | |
| 432 | 434 | static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) |
| 433 | 435 | { |
| 434 | − gpio_free(HDMI_GPIO_LS_OE); | |
| 435 | − gpio_free(HDMI_GPIO_HPD); | |
| 436 | + gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios)); | |
| 436 | 437 | } |
| 437 | 438 | |
| 439 | +static struct omap_dss_hdmi_data omap4_panda_hdmi_data = { | |
| 440 | + .hpd_gpio = HDMI_GPIO_HPD, | |
| 441 | +}; | |
| 442 | + | |
| 438 | 443 | static struct omap_dss_device omap4_panda_hdmi_device = { |
| 439 | 444 | .name = "hdmi", |
| 440 | 445 | .driver_name = "hdmi_panel", |
| @@ -442,6 +447,7 @@ static struct omap_dss_device omap4_panda_hdmi_device = { · 1 unmodified line | ||
| 442 | 447 | .platform_enable = omap4_panda_panel_enable_hdmi, |
| 443 | 448 | .platform_disable = omap4_panda_panel_disable_hdmi, |
| 444 | 449 | .channel = OMAP_DSS_CHANNEL_DIGIT, |
| 450 | + .data = &omap4_panda_hdmi_data, | |
| 445 | 451 | }; |
| 446 | 452 | |
| 447 | 453 | static struct omap_dss_device *omap4_panda_dss_devices[] = { |
| @@ -473,18 +479,24 @@ void omap4_panda_display_init(void) · 25 unmodified lines | ||
| 473 | 479 | omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); |
| 474 | 480 | else |
| 475 | 481 | omap_hdmi_init(0); |
| 482 | + | |
| 483 | + omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); | |
| 484 | + omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); | |
| 485 | + omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); | |
| 476 | 486 | } |
| 477 | 487 | |
| 478 | 488 | static void __init omap4_panda_init(void) |
| 479 | 489 | { |
| 480 | 490 | int package = OMAP_PACKAGE_CBS; |
| 491 | + int ret; | |
| 481 | 492 | |
| 482 | 493 | if (omap_rev() == OMAP4430_REV_ES1_0) |
| 483 | 494 | package = OMAP_PACKAGE_CBL; |
| 484 | 495 | omap4_mux_init(board_mux, NULL, package); |
| 485 | 496 | |
| 486 | − if (wl12xx_set_platform_data(&omap_panda_wlan_data)) | |
| 487 | − pr_err("error setting wl12xx data\n"); | |
| 497 | + ret = wl12xx_set_platform_data(&omap_panda_wlan_data); | |
| 498 | + if (ret) | |
| 499 | + pr_err("error setting wl12xx data: %d\n", ret); | |
| 488 | 500 | |
| 489 | 501 | omap4_panda_i2c_init(); |
| 490 | 502 | platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); |
| @@ -296,8 +296,10 @@ static void enable_board_wakeup_source(void) · 295 unmodified lines | ||
| 296 | 296 | |
| 297 | 297 | void __init zoom_peripherals_init(void) |
| 298 | 298 | { |
| 299 | − if (wl12xx_set_platform_data(&omap_zoom_wlan_data)) | |
| 300 | − pr_err("error setting wl12xx data\n"); | |
| 299 | + int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data); | |
| 300 | + | |
| 301 | + if (ret) | |
| 302 | + pr_err("error setting wl12xx data: %d\n", ret); | |
| 301 | 303 | |
| 302 | 304 | omap_i2c_init(); |
| 303 | 305 | platform_device_register(&omap_vwlan_device); |
| @@ -405,6 +405,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) · 404 unmodified lines | ||
| 405 | 405 | break; |
| 406 | 406 | default: |
| 407 | 407 | pr_err("Invalid McSPI Revision value\n"); |
| 408 | + kfree(pdata); | |
| 408 | 409 | return -EINVAL; |
| 409 | 410 | } |
| 410 | 411 | |
| @@ -103,12 +103,8 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags) · 102 unmodified lines | ||
| 103 | 103 | u32 reg; |
| 104 | 104 | u16 control_i2c_1; |
| 105 | 105 | |
| 106 | − /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ | |
| 107 | − omap_mux_init_signal("hdmi_hpd", | |
| 108 | − OMAP_PIN_INPUT_PULLUP); | |
| 109 | 106 | omap_mux_init_signal("hdmi_cec", |
| 110 | 107 | OMAP_PIN_INPUT_PULLUP); |
| 111 | − /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ | |
| 112 | 108 | omap_mux_init_signal("hdmi_ddc_scl", |
| 113 | 109 | OMAP_PIN_INPUT_PULLUP); |
| 114 | 110 | omap_mux_init_signal("hdmi_ddc_sda", |
| @@ -528,7 +528,13 @@ int gpmc_cs_configure(int cs, int cmd, int wval) · 527 unmodified lines | ||
| 528 | 528 | |
| 529 | 529 | case GPMC_CONFIG_DEV_SIZE: |
| 530 | 530 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); |
| 531 | + | |
| 532 | + /* clear 2 target bits */ | |
| 533 | + regval &= ~GPMC_CONFIG1_DEVICESIZE(3); | |
| 534 | + | |
| 535 | + /* set the proper value */ | |
| 531 | 536 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); |
| 537 | + | |
| 532 | 538 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); |
| 533 | 539 | break; |
| 534 | 540 | |
| @@ -175,14 +175,15 @@ static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) · 174 unmodified lines | ||
| 175 | 175 | { |
| 176 | 176 | u32 reg; |
| 177 | 177 | |
| 178 | − if (mmc->slots[0].internal_clock) { | |
| 179 | − reg = omap_ctrl_readl(control_devconf1_offset); | |
| 178 | + reg = omap_ctrl_readl(control_devconf1_offset); | |
| 179 | + if (mmc->slots[0].internal_clock) | |
| 180 | 180 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; |
| 181 | − omap_ctrl_writel(reg, control_devconf1_offset); | |
| 182 | − } | |
| 181 | + else | |
| 182 | + reg &= ~OMAP2_MMCSDIO2ADPCLKISEL; | |
| 183 | + omap_ctrl_writel(reg, control_devconf1_offset); | |
| 183 | 184 | } |
| 184 | 185 | |
| 185 | −static void hsmmc23_before_set_reg(struct device *dev, int slot, | |
| 186 | +static void hsmmc2_before_set_reg(struct device *dev, int slot, | |
| 186 | 187 | int power_on, int vdd) |
| 187 | 188 | { |
| 188 | 189 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
| @@ -292,8 +293,8 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, · 103 unmodified lines | ||
| 292 | 293 | } |
| 293 | 294 | } |
| 294 | 295 | |
| 295 | −static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | |
| 296 | − struct omap_mmc_platform_data *mmc) | |
| 296 | +static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | |
| 297 | + struct omap_mmc_platform_data *mmc) | |
| 297 | 298 | { |
| 298 | 299 | char *hc_name; |
| 299 | 300 | |
| @@ -407,14 +408,13 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, · 107 unmodified lines | ||
| 407 | 408 | c->caps &= ~MMC_CAP_8_BIT_DATA; |
| 408 | 409 | c->caps |= MMC_CAP_4_BIT_DATA; |
| 409 | 410 | } |
| 410 | − /* FALLTHROUGH */ | |
| 411 | − case 3: | |
| 412 | 411 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { |
| 413 | 412 | /* off-chip level shifting, or none */ |
| 414 | − mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; | |
| 413 | + mmc->slots[0].before_set_reg = hsmmc2_before_set_reg; | |
| 415 | 414 | mmc->slots[0].after_set_reg = NULL; |
| 416 | 415 | } |
| 417 | 416 | break; |
| 417 | + case 3: | |
| 418 | 418 | case 4: |
| 419 | 419 | case 5: |
| 420 | 420 | mmc->slots[0].before_set_reg = NULL; |
| @@ -430,7 +430,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, · 9 unmodified lines | ||
| 430 | 430 | |
| 431 | 431 | #define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 |
| 432 | 432 | |
| 433 | −void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) | |
| 433 | +void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) | |
| 434 | 434 | { |
| 435 | 435 | struct omap_hwmod *oh; |
| 436 | 436 | struct platform_device *pdev; |
| @@ -487,7 +487,7 @@ done: · 50 unmodified lines | ||
| 487 | 487 | kfree(mmc_data); |
| 488 | 488 | } |
| 489 | 489 | |
| 490 | −void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) | |
| 490 | +void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) | |
| 491 | 491 | { |
| 492 | 492 | u32 reg; |
| 493 | 493 | |
| @@ -388,7 +388,7 @@ static void __init omap_hwmod_init_postsetup(void) · 387 unmodified lines | ||
| 388 | 388 | omap_pm_if_early_init(); |
| 389 | 389 | } |
| 390 | 390 | |
| 391 | −#ifdef CONFIG_ARCH_OMAP2 | |
| 391 | +#ifdef CONFIG_SOC_OMAP2420 | |
| 392 | 392 | void __init omap2420_init_early(void) |
| 393 | 393 | { |
| 394 | 394 | omap2_set_globals_242x(); |
| @@ -400,7 +400,9 @@ void __init omap2420_init_early(void) · 5 unmodified lines | ||
| 400 | 400 | omap_hwmod_init_postsetup(); |
| 401 | 401 | omap2420_clk_init(); |
| 402 | 402 | } |
| 403 | +#endif | |
| 403 | 404 | |
| 405 | +#ifdef CONFIG_SOC_OMAP2430 | |
| 404 | 406 | void __init omap2430_init_early(void) |
| 405 | 407 | { |
| 406 | 408 | omap2_set_globals_243x(); |
| @@ -100,8 +100,8 @@ void omap_mux_write_array(struct omap_mux_partition *partition, · 99 unmodified lines | ||
| 100 | 100 | |
| 101 | 101 | static char *omap_mux_options; |
| 102 | 102 | |
| 103 | −static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, | |
| 104 | − int gpio, int val) | |
| 103 | +static int _omap_mux_init_gpio(struct omap_mux_partition *partition, | |
| 104 | + int gpio, int val) | |
| 105 | 105 | { |
| 106 | 106 | struct omap_mux_entry *e; |
| 107 | 107 | struct omap_mux *gpio_mux = NULL; |
| @@ -145,7 +145,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, · 37 unmodified lines | ||
| 145 | 145 | return 0; |
| 146 | 146 | } |
| 147 | 147 | |
| 148 | −int __init omap_mux_init_gpio(int gpio, int val) | |
| 148 | +int omap_mux_init_gpio(int gpio, int val) | |
| 149 | 149 | { |
| 150 | 150 | struct omap_mux_partition *partition; |
| 151 | 151 | int ret; |
| @@ -159,9 +159,9 @@ int __init omap_mux_init_gpio(int gpio, int val) · 7 unmodified lines | ||
| 159 | 159 | return -ENODEV; |
| 160 | 160 | } |
| 161 | 161 | |
| 162 | −static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, | |
| 163 | − const char *muxname, | |
| 164 | − struct omap_mux **found_mux) | |
| 162 | +static int _omap_mux_get_by_name(struct omap_mux_partition *partition, | |
| 163 | + const char *muxname, | |
| 164 | + struct omap_mux **found_mux) | |
| 165 | 165 | { |
| 166 | 166 | struct omap_mux *mux = NULL; |
| 167 | 167 | struct omap_mux_entry *e; |
| @@ -240,7 +240,7 @@ omap_mux_get_by_name(const char *muxname, · 72 unmodified lines | ||
| 240 | 240 | return -ENODEV; |
| 241 | 241 | } |
| 242 | 242 | |
| 243 | −int __init omap_mux_init_signal(const char *muxname, int val) | |
| 243 | +int omap_mux_init_signal(const char *muxname, int val) | |
| 244 | 244 | { |
| 245 | 245 | struct omap_mux_partition *partition = NULL; |
| 246 | 246 | struct omap_mux *mux = NULL; |
| @@ -1094,8 +1094,8 @@ static void omap_mux_init_package(struct omap_mux *superset, · 847 unmodified lines | ||
| 1094 | 1094 | omap_mux_package_init_balls(package_balls, superset); |
| 1095 | 1095 | } |
| 1096 | 1096 | |
| 1097 | −static void omap_mux_init_signals(struct omap_mux_partition *partition, | |
| 1098 | − struct omap_board_mux *board_mux) | |
| 1097 | +static void __init omap_mux_init_signals(struct omap_mux_partition *partition, | |
| 1098 | + struct omap_board_mux *board_mux) | |
| 1099 | 1099 | { |
| 1100 | 1100 | omap_mux_set_cmdline_signals(); |
| 1101 | 1101 | omap_mux_write_array(partition, board_mux); |
| @@ -1109,8 +1109,8 @@ static void omap_mux_init_package(struct omap_mux *superset, · 7 unmodified lines | ||
| 1109 | 1109 | { |
| 1110 | 1110 | } |
| 1111 | 1111 | |
| 1112 | −static void omap_mux_init_signals(struct omap_mux_partition *partition, | |
| 1113 | − struct omap_board_mux *board_mux) | |
| 1112 | +static void __init omap_mux_init_signals(struct omap_mux_partition *partition, | |
| 1113 | + struct omap_board_mux *board_mux) | |
| 1114 | 1114 | { |
| 1115 | 1115 | } |
| 1116 | 1116 | |
| @@ -18,6 +18,7 @@ · 17 unmodified lines | ||
| 18 | 18 | #include <linux/linkage.h> |
| 19 | 19 | #include <linux/init.h> |
| 20 | 20 | |
| 21 | + __CPUINIT | |
| 21 | 22 | /* |
| 22 | 23 | * OMAP4 specific entry point for secondary CPU to jump from ROM |
| 23 | 24 | * code. This routine also provides a holding flag into which |
| @@ -1517,8 +1517,8 @@ static int _enable(struct omap_hwmod *oh) · 1516 unmodified lines | ||
| 1517 | 1517 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
| 1518 | 1518 | oh->_state != _HWMOD_STATE_IDLE && |
| 1519 | 1519 | oh->_state != _HWMOD_STATE_DISABLED) { |
| 1520 | − WARN(1, "omap_hwmod: %s: enabled state can only be entered " | |
| 1521 | − "from initialized, idle, or disabled state\n", oh->name); | |
| 1520 | + WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", | |
| 1521 | + oh->name); | |
| 1522 | 1522 | return -EINVAL; |
| 1523 | 1523 | } |
| 1524 | 1524 | |
| @@ -1600,8 +1600,8 @@ static int _idle(struct omap_hwmod *oh) · 75 unmodified lines | ||
| 1600 | 1600 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
| 1601 | 1601 | |
| 1602 | 1602 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
| 1603 | − WARN(1, "omap_hwmod: %s: idle state can only be entered from " | |
| 1604 | − "enabled state\n", oh->name); | |
| 1603 | + WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", | |
| 1604 | + oh->name); | |
| 1605 | 1605 | return -EINVAL; |
| 1606 | 1606 | } |
| 1607 | 1607 | |
| @@ -1682,8 +1682,8 @@ static int _shutdown(struct omap_hwmod *oh) · 74 unmodified lines | ||
| 1682 | 1682 | |
| 1683 | 1683 | if (oh->_state != _HWMOD_STATE_IDLE && |
| 1684 | 1684 | oh->_state != _HWMOD_STATE_ENABLED) { |
| 1685 | − WARN(1, "omap_hwmod: %s: disabled state can only be entered " | |
| 1686 | − "from idle, or enabled state\n", oh->name); | |
| 1685 | + WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", | |
| 1686 | + oh->name); | |
| 1687 | 1687 | return -EINVAL; |
| 1688 | 1688 | } |
| 1689 | 1689 | |
| @@ -2240,8 +2240,8 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) · 550 unmodified lines | ||
| 2240 | 2240 | BUG_ON(!oh); |
| 2241 | 2241 | |
| 2242 | 2242 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
| 2243 | − WARN(1, "omap_device: %s: OCP barrier impossible due to " | |
| 2244 | − "device configuration\n", oh->name); | |
| 2243 | + WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", | |
| 2244 | + oh->name); | |
| 2245 | 2245 | return; |
| 2246 | 2246 | } |
| 2247 | 2247 | |
| @@ -55,27 +55,6 @@ struct omap_hwmod_class omap2_dss_hwmod_class = { · 54 unmodified lines | ||
| 55 | 55 | .reset = omap_dss_reset, |
| 56 | 56 | }; |
| 57 | 57 | |
| 58 | −/* | |
| 59 | − * 'dispc' class | |
| 60 | − * display controller | |
| 61 | − */ | |
| 62 | − | |
| 63 | −static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = { | |
| 64 | − .rev_offs = 0x0000, | |
| 65 | − .sysc_offs = 0x0010, | |
| 66 | − .syss_offs = 0x0014, | |
| 67 | − .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
| 68 | − SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
| 69 | − .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
| 70 | − MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
| 71 | − .sysc_fields = &omap_hwmod_sysc_type1, | |
| 72 | −}; | |
| 73 | − | |
| 74 | −struct omap_hwmod_class omap2_dispc_hwmod_class = { | |
| 75 | − .name = "dispc", | |
| 76 | − .sysc = &omap2_dispc_sysc, | |
| 77 | −}; | |
| 78 | − | |
| 79 | 58 | /* |
| 80 | 59 | * 'rfbi' class |
| 81 | 60 | * remote frame buffer interface |
| @@ -28,6 +28,28 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { · 27 unmodified lines | ||
| 28 | 28 | { .name = "dispc", .dma_req = 5 }, |
| 29 | 29 | { .dma_req = -1 } |
| 30 | 30 | }; |
| 31 | + | |
| 32 | +/* | |
| 33 | + * 'dispc' class | |
| 34 | + * display controller | |
| 35 | + */ | |
| 36 | + | |
| 37 | +static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = { | |
| 38 | + .rev_offs = 0x0000, | |
| 39 | + .sysc_offs = 0x0010, | |
| 40 | + .syss_offs = 0x0014, | |
| 41 | + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
| 42 | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
| 43 | + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
| 44 | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
| 45 | + .sysc_fields = &omap_hwmod_sysc_type1, | |
| 46 | +}; | |
| 47 | + | |
| 48 | +struct omap_hwmod_class omap2_dispc_hwmod_class = { | |
| 49 | + .name = "dispc", | |
| 50 | + .sysc = &omap2_dispc_sysc, | |
| 51 | +}; | |
| 52 | + | |
| 31 | 53 | /* OMAP2xxx Timer Common */ |
| 32 | 54 | static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { |
| 33 | 55 | .rev_offs = 0x0000, |
| @@ -1480,6 +1480,28 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { · 1479 unmodified lines | ||
| 1480 | 1480 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), |
| 1481 | 1481 | }; |
| 1482 | 1482 | |
| 1483 | +/* | |
| 1484 | + * 'dispc' class | |
| 1485 | + * display controller | |
| 1486 | + */ | |
| 1487 | + | |
| 1488 | +static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { | |
| 1489 | + .rev_offs = 0x0000, | |
| 1490 | + .sysc_offs = 0x0010, | |
| 1491 | + .syss_offs = 0x0014, | |
| 1492 | + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
| 1493 | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
| 1494 | + SYSC_HAS_ENAWAKEUP), | |
| 1495 | + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
| 1496 | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
| 1497 | + .sysc_fields = &omap_hwmod_sysc_type1, | |
| 1498 | +}; | |
| 1499 | + | |
| 1500 | +static struct omap_hwmod_class omap3_dispc_hwmod_class = { | |
| 1501 | + .name = "dispc", | |
| 1502 | + .sysc = &omap3_dispc_sysc, | |
| 1503 | +}; | |
| 1504 | + | |
| 1483 | 1505 | /* l4_core -> dss_dispc */ |
| 1484 | 1506 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { |
| 1485 | 1507 | .master = &omap3xxx_l4_core_hwmod, |
| @@ -1503,7 +1525,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { · 17 unmodified lines | ||
| 1503 | 1525 | |
| 1504 | 1526 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
| 1505 | 1527 | .name = "dss_dispc", |
| 1506 | − .class = &omap2_dispc_hwmod_class, | |
| 1528 | + .class = &omap3_dispc_hwmod_class, | |
| 1507 | 1529 | .mpu_irqs = omap2_dispc_irqs, |
| 1508 | 1530 | .main_clk = "dss1_alwon_fck", |
| 1509 | 1531 | .prcm = { |
| @@ -3523,12 +3545,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { · 2013 unmodified lines | ||
| 3523 | 3545 | &omap3xxx_uart2_hwmod, |
| 3524 | 3546 | &omap3xxx_uart3_hwmod, |
| 3525 | 3547 | |
| 3526 | − /* dss class */ | |
| 3527 | − &omap3xxx_dss_dispc_hwmod, | |
| 3528 | − &omap3xxx_dss_dsi1_hwmod, | |
| 3529 | − &omap3xxx_dss_rfbi_hwmod, | |
| 3530 | − &omap3xxx_dss_venc_hwmod, | |
| 3531 | − | |
| 3532 | 3548 | /* i2c class */ |
| 3533 | 3549 | &omap3xxx_i2c1_hwmod, |
| 3534 | 3550 | &omap3xxx_i2c2_hwmod, |
| @@ -3635,6 +3651,15 @@ static __initdata struct omap_hwmod *am35xx_hwmods[] = { · 100 unmodified lines | ||
| 3635 | 3651 | NULL |
| 3636 | 3652 | }; |
| 3637 | 3653 | |
| 3654 | +static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { | |
| 3655 | + /* dss class */ | |
| 3656 | + &omap3xxx_dss_dispc_hwmod, | |
| 3657 | + &omap3xxx_dss_dsi1_hwmod, | |
| 3658 | + &omap3xxx_dss_rfbi_hwmod, | |
| 3659 | + &omap3xxx_dss_venc_hwmod, | |
| 3660 | + NULL | |
| 3661 | +}; | |
| 3662 | + | |
| 3638 | 3663 | int __init omap3xxx_hwmod_init(void) |
| 3639 | 3664 | { |
| 3640 | 3665 | int r; |
| @@ -3708,6 +3733,21 @@ int __init omap3xxx_hwmod_init(void) · 67 unmodified lines | ||
| 3708 | 3733 | |
| 3709 | 3734 | if (h) |
| 3710 | 3735 | r = omap_hwmod_register(h); |
| 3736 | + if (r < 0) | |
| 3737 | + return r; | |
| 3738 | + | |
| 3739 | + /* | |
| 3740 | + * DSS code presumes that dss_core hwmod is handled first, | |
| 3741 | + * _before_ any other DSS related hwmods so register common | |
| 3742 | + * DSS hwmods last to ensure that dss_core is already registered. | |
| 3743 | + * Otherwise some change things may happen, for ex. if dispc | |
| 3744 | + * is handled before dss_core and DSS is enabled in bootloader | |
| 3745 | + * DIPSC will be reset with outputs enabled which sometimes leads | |
| 3746 | + * to unrecoverable L3 error. | |
| 3747 | + * XXX The long-term fix to this is to ensure modules are set up | |
| 3748 | + * in dependency order in the hwmod core code. | |
| 3749 | + */ | |
| 3750 | + r = omap_hwmod_register(omap3xxx_dss_hwmods); | |
| 3711 | 3751 | |
| 3712 | 3752 | return r; |
| 3713 | 3753 | } |
| @@ -1031,6 +1031,7 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { · 1030 unmodified lines | ||
| 1031 | 1031 | |
| 1032 | 1032 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { |
| 1033 | 1033 | { |
| 1034 | + .name = "mpu", | |
| 1034 | 1035 | .pa_start = 0x4012e000, |
| 1035 | 1036 | .pa_end = 0x4012e07f, |
| 1036 | 1037 | .flags = ADDR_TYPE_RT |
| @@ -1049,6 +1050,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { · 12 unmodified lines | ||
| 1049 | 1050 | |
| 1050 | 1051 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { |
| 1051 | 1052 | { |
| 1053 | + .name = "dma", | |
| 1052 | 1054 | .pa_start = 0x4902e000, |
| 1053 | 1055 | .pa_end = 0x4902e07f, |
| 1054 | 1056 | .flags = ADDR_TYPE_RT |
| @@ -82,13 +82,7 @@ static int omap2_fclks_active(void) · 81 unmodified lines | ||
| 82 | 82 | f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
| 83 | 83 | f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
| 84 | 84 | |
| 85 | − /* Ignore UART clocks. These are handled by UART core (serial.c) */ | |
| 86 | − f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); | |
| 87 | − f2 &= ~OMAP24XX_EN_UART3_MASK; | |
| 88 | − | |
| 89 | − if (f1 | f2) | |
| 90 | − return 1; | |
| 91 | − return 0; | |
| 85 | + return (f1 | f2) ? 1 : 0; | |
| 92 | 86 | } |
| 93 | 87 | |
| 94 | 88 | static void omap2_enter_full_retention(void) |
| @@ -19,6 +19,7 @@ · 18 unmodified lines | ||
| 19 | 19 | #include "common.h" |
| 20 | 20 | #include <plat/cpu.h> |
| 21 | 21 | #include <plat/prcm.h> |
| 22 | +#include <plat/irqs.h> | |
| 22 | 23 | |
| 23 | 24 | #include "vp.h" |
| 24 | 25 | |
| @@ -19,6 +19,7 @@ · 18 unmodified lines | ||
| 19 | 19 | |
| 20 | 20 | #include "common.h" |
| 21 | 21 | #include <plat/cpu.h> |
| 22 | +#include <plat/irqs.h> | |
| 22 | 23 | #include <plat/prcm.h> |
| 23 | 24 | |
| 24 | 25 | #include "vp.h" |
| @@ -107,18 +107,18 @@ static void omap_uart_set_noidle(struct platform_device *pdev) · 106 unmodified lines | ||
| 107 | 107 | omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); |
| 108 | 108 | } |
| 109 | 109 | |
| 110 | −static void omap_uart_set_forceidle(struct platform_device *pdev) | |
| 110 | +static void omap_uart_set_smartidle(struct platform_device *pdev) | |
| 111 | 111 | { |
| 112 | 112 | struct omap_device *od = to_omap_device(pdev); |
| 113 | 113 | |
| 114 | − omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE); | |
| 114 | + omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART); | |
| 115 | 115 | } |
| 116 | 116 | |
| 117 | 117 | #else |
| 118 | 118 | static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) |
| 119 | 119 | {} |
| 120 | 120 | static void omap_uart_set_noidle(struct platform_device *pdev) {} |
| 121 | −static void omap_uart_set_forceidle(struct platform_device *pdev) {} | |
| 121 | +static void omap_uart_set_smartidle(struct platform_device *pdev) {} | |
| 122 | 122 | #endif /* CONFIG_PM */ |
| 123 | 123 | |
| 124 | 124 | #ifdef CONFIG_OMAP_MUX |
| @@ -349,7 +349,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, · 224 unmodified lines | ||
| 349 | 349 | omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; |
| 350 | 350 | omap_up.flags = UPF_BOOT_AUTOCONF; |
| 351 | 351 | omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count; |
| 352 | − omap_up.set_forceidle = omap_uart_set_forceidle; | |
| 352 | + omap_up.set_forceidle = omap_uart_set_smartidle; | |
| 353 | 353 | omap_up.set_noidle = omap_uart_set_noidle; |
| 354 | 354 | omap_up.enable_wakeup = omap_uart_enable_wakeup; |
| 355 | 355 | omap_up.dma_rx_buf_size = info->dma_rx_buf_size; |
| @@ -897,7 +897,7 @@ static int __init omap_sr_probe(struct platform_device *pdev) · 896 unmodified lines | ||
| 897 | 897 | ret = sr_late_init(sr_info); |
| 898 | 898 | if (ret) { |
| 899 | 899 | pr_warning("%s: Error in SR late init\n", __func__); |
| 900 | − return ret; | |
| 900 | + goto err_iounmap; | |
| 901 | 901 | } |
| 902 | 902 | } |
| 903 | 903 | |
| @@ -270,7 +270,7 @@ static struct clocksource clocksource_gpt = { · 269 unmodified lines | ||
| 270 | 270 | static u32 notrace dmtimer_read_sched_clock(void) |
| 271 | 271 | { |
| 272 | 272 | if (clksrc.reserved) |
| 273 | − return __omap_dm_timer_read_counter(clksrc.io_base, 1); | |
| 273 | + return __omap_dm_timer_read_counter(&clksrc, 1); | |
| 274 | 274 | |
| 275 | 275 | return 0; |
| 276 | 276 | } |
| @@ -247,7 +247,7 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) · 246 unmodified lines | ||
| 247 | 247 | * omap_vc_i2c_init - initialize I2C interface to PMIC |
| 248 | 248 | * @voltdm: voltage domain containing VC data |
| 249 | 249 | * |
| 250 | − * Use PMIC supplied seetings for I2C high-speed mode and | |
| 250 | + * Use PMIC supplied settings for I2C high-speed mode and | |
| 251 | 251 | * master code (if set) and program the VC I2C configuration |
| 252 | 252 | * register. |
| 253 | 253 | * |
| @@ -265,8 +265,8 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) · 11 unmodified lines | ||
| 265 | 265 | |
| 266 | 266 | if (initialized) { |
| 267 | 267 | if (voltdm->pmic->i2c_high_speed != i2c_high_speed) |
| 268 | − pr_warn("%s: I2C config for all channels must match.", | |
| 269 | − __func__); | |
| 268 | + pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).", | |
| 269 | + __func__, voltdm->name, i2c_high_speed); | |
| 270 | 270 | return; |
| 271 | 271 | } |
| 272 | 272 | |
| @@ -292,9 +292,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) · 19 unmodified lines | ||
| 292 | 292 | u32 val; |
| 293 | 293 | |
| 294 | 294 | if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { |
| 295 | − pr_err("%s: PMIC info requried to configure vc for" | |
| 296 | − "vdd_%s not populated.Hence cannot initialize vc\n", | |
| 297 | − __func__, voltdm->name); | |
| 295 | + pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); | |
| 298 | 296 | return; |
| 299 | 297 | } |
| 300 | 298 | |
| @@ -108,6 +108,7 @@ void __init omap3xxx_voltagedomains_init(void) · 107 unmodified lines | ||
| 108 | 108 | * XXX Will depend on the process, validation, and binning |
| 109 | 109 | * for the currently-running IC |
| 110 | 110 | */ |
| 111 | +#ifdef CONFIG_PM_OPP | |
| 111 | 112 | if (cpu_is_omap3630()) { |
| 112 | 113 | omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data; |
| 113 | 114 | omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data; |
| @@ -115,6 +116,7 @@ void __init omap3xxx_voltagedomains_init(void) · 1 unmodified line | ||
| 115 | 116 | omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data; |
| 116 | 117 | omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; |
| 117 | 118 | } |
| 119 | +#endif | |
| 118 | 120 | |
| 119 | 121 | if (cpu_is_omap3517() || cpu_is_omap3505()) |
| 120 | 122 | voltdms = voltagedomains_am35xx; |
| @@ -100,9 +100,11 @@ void __init omap44xx_voltagedomains_init(void) · 99 unmodified lines | ||
| 100 | 100 | * XXX Will depend on the process, validation, and binning |
| 101 | 101 | * for the currently-running IC |
| 102 | 102 | */ |
| 103 | +#ifdef CONFIG_PM_OPP | |
| 103 | 104 | omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; |
| 104 | 105 | omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; |
| 105 | 106 | omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; |
| 107 | +#endif | |
| 106 | 108 | |
| 107 | 109 | for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) |
| 108 | 110 | voltdm->sys_clk.name = sys_clk_name; |
| @@ -41,6 +41,11 @@ void __init omap_vp_init(struct voltagedomain *voltdm) · 40 unmodified lines | ||
| 41 | 41 | u32 val, sys_clk_rate, timeout, waittime; |
| 42 | 42 | u32 vddmin, vddmax, vstepmin, vstepmax; |
| 43 | 43 | |
| 44 | + if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { | |
| 45 | + pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); | |
| 46 | + return; | |
| 47 | + } | |
| 48 | + | |
| 44 | 49 | if (!voltdm->read || !voltdm->write) { |
| 45 | 50 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", |
| 46 | 51 | __func__, voltdm->name); |
| @@ -29,6 +29,7 @@ · 28 unmodified lines | ||
| 29 | 29 | #include <mach/hardware.h> |
| 30 | 30 | #include <mach/orion5x.h> |
| 31 | 31 | #include <plat/orion_nand.h> |
| 32 | +#include <plat/ehci-orion.h> | |
| 32 | 33 | #include <plat/time.h> |
| 33 | 34 | #include <plat/common.h> |
| 34 | 35 | #include <plat/addr-map.h> |
| @@ -72,7 +73,8 @@ void __init orion5x_map_io(void) · 37 unmodified lines | ||
| 72 | 73 | ****************************************************************************/ |
| 73 | 74 | void __init orion5x_ehci0_init(void) |
| 74 | 75 | { |
| 75 | − orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); | |
| 76 | + orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, | |
| 77 | + EHCI_PHY_ORION); | |
| 76 | 78 | } |
| 77 | 79 | |
| 78 | 80 | |
| @@ -67,7 +67,7 @@ static void picoxcell_add_clocksource(struct device_node *source_timer) · 66 unmodified lines | ||
| 67 | 67 | |
| 68 | 68 | static void __iomem *sched_io_base; |
| 69 | 69 | |
| 70 | −unsigned u32 notrace picoxcell_read_sched_clock(void) | |
| 70 | +static u32 picoxcell_read_sched_clock(void) | |
| 71 | 71 | { |
| 72 | 72 | return __raw_readl(sched_io_base); |
| 73 | 73 | } |
| @@ -415,29 +415,9 @@ static struct resource pxa_rtc_resources[] = { · 414 unmodified lines | ||
| 415 | 415 | }, |
| 416 | 416 | }; |
| 417 | 417 | |
| 418 | −static struct resource sa1100_rtc_resources[] = { | |
| 419 | − [0] = { | |
| 420 | − .start = 0x40900000, | |
| 421 | − .end = 0x409000ff, | |
| 422 | − .flags = IORESOURCE_MEM, | |
| 423 | − }, | |
| 424 | − [1] = { | |
| 425 | − .start = IRQ_RTC1Hz, | |
| 426 | − .end = IRQ_RTC1Hz, | |
| 427 | − .flags = IORESOURCE_IRQ, | |
| 428 | − }, | |
| 429 | − [2] = { | |
| 430 | − .start = IRQ_RTCAlrm, | |
| 431 | − .end = IRQ_RTCAlrm, | |
| 432 | − .flags = IORESOURCE_IRQ, | |
| 433 | − }, | |
| 434 | −}; | |
| 435 | − | |
| 436 | 418 | struct platform_device sa1100_device_rtc = { |
| 437 | 419 | .name = "sa1100-rtc", |
| 438 | 420 | .id = -1, |
| 439 | − .num_resources = ARRAY_SIZE(sa1100_rtc_resources), | |
| 440 | − .resource = sa1100_rtc_resources, | |
| 441 | 421 | }; |
| 442 | 422 | |
| 443 | 423 | struct platform_device pxa_device_rtc = { |
| @@ -209,8 +209,6 @@ static struct clk_lookup pxa25x_clkregs[] = { · 208 unmodified lines | ||
| 209 | 209 | INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), |
| 210 | 210 | INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), |
| 211 | 211 | INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), |
| 212 | − INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), | |
| 213 | − INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | |
| 214 | 212 | }; |
| 215 | 213 | |
| 216 | 214 | static struct clk_lookup pxa25x_hwuart_clkreg = |
| @@ -230,8 +230,6 @@ static struct clk_lookup pxa27x_clkregs[] = { · 229 unmodified lines | ||
| 230 | 230 | INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), |
| 231 | 231 | INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), |
| 232 | 232 | INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), |
| 233 | − INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), | |
| 234 | − INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | |
| 235 | 233 | }; |
| 236 | 234 | |
| 237 | 235 | #ifdef CONFIG_PM |
| @@ -89,7 +89,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0); · 88 unmodified lines | ||
| 89 | 89 | static struct clk_lookup common_clkregs[] = { |
| 90 | 90 | INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL), |
| 91 | 91 | INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), |
| 92 | − INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | |
| 93 | 92 | }; |
| 94 | 93 | |
| 95 | 94 | static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); |
| @@ -83,7 +83,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0); · 82 unmodified lines | ||
| 83 | 83 | static struct clk_lookup pxa320_clkregs[] = { |
| 84 | 84 | INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL), |
| 85 | 85 | INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), |
| 86 | − INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | |
| 87 | 86 | }; |
| 88 | 87 | |
| 89 | 88 | static int __init pxa320_init(void) |
| @@ -67,7 +67,6 @@ static struct clk_lookup pxa3xx_clkregs[] = { · 66 unmodified lines | ||
| 67 | 67 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), |
| 68 | 68 | /* Power I2C clock is always on */ |
| 69 | 69 | INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), |
| 70 | − INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | |
| 71 | 70 | INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), |
| 72 | 71 | INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), |
| 73 | 72 | INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), |
| @@ -217,7 +217,6 @@ static struct clk_lookup pxa95x_clkregs[] = { · 216 unmodified lines | ||
| 217 | 217 | INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"), |
| 218 | 218 | /* Power I2C clock is always on */ |
| 219 | 219 | INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), |
| 220 | − INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | |
| 221 | 220 | INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL), |
| 222 | 221 | INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL), |
| 223 | 222 | INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL), |
| @@ -13,6 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | #include <linux/smp.h> |
| 14 | 14 | |
| 15 | 15 | #include <asm/cacheflush.h> |
| 16 | +#include <asm/smp_plat.h> | |
| 16 | 17 | |
| 17 | 18 | extern volatile int pen_release; |
| 18 | 19 | |
| @@ -47,21 +47,23 @@ · 46 unmodified lines | ||
| 47 | 47 | #define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */ |
| 48 | 48 | |
| 49 | 49 | #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB |
| 50 | −#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ | |
| 51 | −#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ | |
| 52 | −#define REALVIEW_EB11MP_TWD_BASE 0x10100600 | |
| 53 | −#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ | |
| 50 | +#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000 | |
| 54 | 51 | #define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ |
| 55 | 52 | #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ |
| 56 | 53 | #else |
| 57 | −#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */ | |
| 58 | −#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ | |
| 59 | −#define REALVIEW_EB11MP_TWD_BASE 0x1F000600 | |
| 60 | −#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ | |
| 54 | +#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000 | |
| 61 | 55 | #define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ |
| 62 | 56 | #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ |
| 63 | 57 | #endif |
| 64 | 58 | |
| 59 | +#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K | |
| 60 | +#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x)) | |
| 61 | + | |
| 62 | +#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */ | |
| 63 | +#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */ | |
| 64 | +#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600) | |
| 65 | +#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */ | |
| 66 | + | |
| 65 | 67 | /* |
| 66 | 68 | * Core tile identification (REALVIEW_SYS_PROCID) |
| 67 | 69 | */ |
| @@ -75,6 +75,8 @@ · 74 unmodified lines | ||
| 75 | 75 | /* |
| 76 | 76 | * Testchip peripheral and fpga gic regions |
| 77 | 77 | */ |
| 78 | +#define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000 | |
| 79 | +#define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K | |
| 78 | 80 | #define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ |
| 79 | 81 | #define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ |
| 80 | 82 | #define REALVIEW_TC11MP_TWD_BASE 0x1F000600 |
| @@ -17,7 +17,6 @@ · 16 unmodified lines | ||
| 17 | 17 | #include <asm/hardware/gic.h> |
| 18 | 18 | #include <asm/mach-types.h> |
| 19 | 19 | #include <asm/smp_scu.h> |
| 20 | −#include <asm/unified.h> | |
| 21 | 20 | |
| 22 | 21 | #include <mach/board-eb.h> |
| 23 | 22 | #include <mach/board-pb11mp.h> |
| @@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) · 51 unmodified lines | ||
| 75 | 74 | * until it receives a soft interrupt, and then the |
| 76 | 75 | * secondary CPU branches to this address. |
| 77 | 76 | */ |
| 78 | − __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)), | |
| 77 | + __raw_writel(virt_to_phys(versatile_secondary_startup), | |
| 79 | 78 | __io_address(REALVIEW_SYS_FLAGSSET)); |
| 80 | 79 | } |
| @@ -91,14 +91,9 @@ static struct map_desc realview_eb_io_desc[] __initdata = { · 90 unmodified lines | ||
| 91 | 91 | |
| 92 | 92 | static struct map_desc realview_eb11mp_io_desc[] __initdata = { |
| 93 | 93 | { |
| 94 | − .virtual = IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE), | |
| 95 | − .pfn = __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE), | |
| 96 | − .length = SZ_4K, | |
| 97 | − .type = MT_DEVICE, | |
| 98 | − }, { | |
| 99 | − .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE), | |
| 100 | − .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE), | |
| 101 | − .length = SZ_4K, | |
| 94 | + .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE), | |
| 95 | + .pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE), | |
| 96 | + .length = REALVIEW_EB11MP_PRIV_MEM_SIZE, | |
| 102 | 97 | .type = MT_DEVICE, |
| 103 | 98 | }, { |
| 104 | 99 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE), |
| @@ -64,15 +64,10 @@ static struct map_desc realview_pb11mp_io_desc[] __initdata = { · 63 unmodified lines | ||
| 64 | 64 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE), |
| 65 | 65 | .length = SZ_4K, |
| 66 | 66 | .type = MT_DEVICE, |
| 67 | − }, { | |
| 68 | − .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE), | |
| 69 | − .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE), | |
| 70 | − .length = SZ_4K, | |
| 71 | − .type = MT_DEVICE, | |
| 72 | − }, { | |
| 73 | − .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE), | |
| 74 | − .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE), | |
| 75 | − .length = SZ_4K, | |
| 67 | + }, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */ | |
| 68 | + .virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE), | |
| 69 | + .pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE), | |
| 70 | + .length = REALVIEW_TC11MP_PRIV_MEM_SIZE, | |
| 76 | 71 | .type = MT_DEVICE, |
| 77 | 72 | }, { |
| 78 | 73 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), |
| @@ -115,7 +115,8 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = { · 114 unmodified lines | ||
| 115 | 115 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), |
| 116 | 116 | }; |
| 117 | 117 | |
| 118 | −static int s3c2410_cpufreq_add(struct device *dev) | |
| 118 | +static int s3c2410_cpufreq_add(struct device *dev, | |
| 119 | + struct subsys_interface *sif) | |
| 119 | 120 | { |
| 120 | 121 | return s3c_cpufreq_register(&s3c2410_cpufreq_info); |
| 121 | 122 | } |
| @@ -133,7 +134,8 @@ static int __init s3c2410_cpufreq_init(void) · 11 unmodified lines | ||
| 133 | 134 | |
| 134 | 135 | arch_initcall(s3c2410_cpufreq_init); |
| 135 | 136 | |
| 136 | −static int s3c2410a_cpufreq_add(struct device *dev) | |
| 137 | +static int s3c2410a_cpufreq_add(struct device *dev, | |
| 138 | + struct subsys_interface *sif) | |
| 137 | 139 | { |
| 138 | 140 | /* alter the maximum freq settings for S3C2410A. If a board knows |
| 139 | 141 | * it only has a maximum of 200, then it should register its own |
| @@ -144,7 +146,7 @@ static int s3c2410a_cpufreq_add(struct device *dev) · 4 unmodified lines | ||
| 144 | 146 | s3c2410_cpufreq_info.max.pclk = 66500000; |
| 145 | 147 | s3c2410_cpufreq_info.name = "s3c2410a"; |
| 146 | 148 | |
| 147 | − return s3c2410_cpufreq_add(dev); | |
| 149 | + return s3c2410_cpufreq_add(dev, sif); | |
| 148 | 150 | } |
| 149 | 151 | |
| 150 | 152 | static struct subsys_interface s3c2410a_cpufreq_interface = { |
| @@ -132,7 +132,8 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = { · 131 unmodified lines | ||
| 132 | 132 | }, |
| 133 | 133 | }; |
| 134 | 134 | |
| 135 | −static int __init s3c2410_dma_add(struct device *dev) | |
| 135 | +static int __init s3c2410_dma_add(struct device *dev, | |
| 136 | + struct subsys_interface *sif) | |
| 136 | 137 | { |
| 137 | 138 | s3c2410_dma_init(); |
| 138 | 139 | s3c24xx_dma_order_set(&s3c2410_dma_order); |
| @@ -148,7 +149,7 @@ static struct subsys_interface s3c2410_dma_interface = { · 9 unmodified lines | ||
| 148 | 149 | |
| 149 | 150 | static int __init s3c2410_dma_drvinit(void) |
| 150 | 151 | { |
| 151 | − return subsys_interface_register(&s3c2410_interface); | |
| 152 | + return subsys_interface_register(&s3c2410_dma_interface); | |
| 152 | 153 | } |
| 153 | 154 | |
| 154 | 155 | arch_initcall(s3c2410_dma_drvinit); |
| @@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = { · 65 unmodified lines | ||
| 66 | 66 | { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, |
| 67 | 67 | }; |
| 68 | 68 | |
| 69 | −static int s3c2410_plls_add(struct device *dev) | |
| 69 | +static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif) | |
| 70 | 70 | { |
| 71 | 71 | return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); |
| 72 | 72 | } |
| @@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = { · 110 unmodified lines | ||
| 111 | 111 | .resume = s3c2410_pm_resume, |
| 112 | 112 | }; |
| 113 | 113 | |
| 114 | −static int s3c2410_pm_add(struct device *dev) | |
| 114 | +static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif) | |
| 115 | 115 | { |
| 116 | 116 | pm_cpu_prep = s3c2410_pm_prepare; |
| 117 | 117 | pm_cpu_sleep = s3c2410_cpu_suspend; |
| @@ -194,7 +194,8 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = { · 193 unmodified lines | ||
| 194 | 194 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), |
| 195 | 195 | }; |
| 196 | 196 | |
| 197 | −static int s3c2412_cpufreq_add(struct device *dev) | |
| 197 | +static int s3c2412_cpufreq_add(struct device *dev, | |
| 198 | + struct subsys_interface *sif) | |
| 198 | 199 | { |
| 199 | 200 | unsigned long fclk_rate; |
| 200 | 201 | |
| @@ -159,7 +159,8 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { · 158 unmodified lines | ||
| 159 | 159 | .map_size = ARRAY_SIZE(s3c2412_dma_mappings), |
| 160 | 160 | }; |
| 161 | 161 | |
| 162 | −static int __init s3c2412_dma_add(struct device *dev) | |
| 162 | +static int __init s3c2412_dma_add(struct device *dev, | |
| 163 | + struct subsys_interface *sif) | |
| 163 | 164 | { |
| 164 | 165 | s3c2410_dma_init(); |
| 165 | 166 | return s3c24xx_dma_init_map(&s3c2412_dma_sel); |
| @@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state) · 169 unmodified lines | ||
| 170 | 170 | |
| 171 | 171 | static struct irq_chip s3c2412_irq_rtc_chip; |
| 172 | 172 | |
| 173 | −static int s3c2412_irq_add(struct device *dev) | |
| 173 | +static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif) | |
| 174 | 174 | { |
| 175 | 175 | unsigned int irqno; |
| 176 | 176 | |
| @@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void) · 55 unmodified lines | ||
| 56 | 56 | { |
| 57 | 57 | } |
| 58 | 58 | |
| 59 | −static int s3c2412_pm_add(struct device *dev) | |
| 59 | +static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif) | |
| 60 | 60 | { |
| 61 | 61 | pm_cpu_prep = s3c2412_pm_prepare; |
| 62 | 62 | pm_cpu_sleep = s3c2412_cpu_suspend; |
| @@ -213,7 +213,8 @@ static int __init s3c2416_add_sub(unsigned int base, · 212 unmodified lines | ||
| 213 | 213 | return 0; |
| 214 | 214 | } |
| 215 | 215 | |
| 216 | −static int __init s3c2416_irq_add(struct device *dev) | |
| 216 | +static int __init s3c2416_irq_add(struct device *dev, | |
| 217 | + struct subsys_interface *sif) | |
| 217 | 218 | { |
| 218 | 219 | printk(KERN_INFO "S3C2416: IRQ Support\n"); |
| 219 | 220 | |
| @@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void) · 47 unmodified lines | ||
| 48 | 48 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); |
| 49 | 49 | } |
| 50 | 50 | |
| 51 | −static int s3c2416_pm_add(struct device *dev) | |
| 51 | +static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif) | |
| 52 | 52 | { |
| 53 | 53 | pm_cpu_prep = s3c2416_pm_prepare; |
| 54 | 54 | pm_cpu_sleep = s3c2416_cpu_suspend; |
| @@ -149,7 +149,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = { · 148 unmodified lines | ||
| 149 | 149 | CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), |
| 150 | 150 | }; |
| 151 | 151 | |
| 152 | −static int s3c2440_clk_add(struct device *dev) | |
| 152 | +static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif) | |
| 153 | 153 | { |
| 154 | 154 | struct clk *clock_upll; |
| 155 | 155 | struct clk *clock_h; |
| @@ -174,7 +174,8 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = { · 173 unmodified lines | ||
| 174 | 174 | }, |
| 175 | 175 | }; |
| 176 | 176 | |
| 177 | −static int __init s3c2440_dma_add(struct device *dev) | |
| 177 | +static int __init s3c2440_dma_add(struct device *dev, | |
| 178 | + struct subsys_interface *sif) | |
| 178 | 179 | { |
| 179 | 180 | s3c2410_dma_init(); |
| 180 | 181 | s3c24xx_dma_order_set(&s3c2440_dma_order); |
| @@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = { · 91 unmodified lines | ||
| 92 | 92 | .irq_ack = s3c_irq_wdtac97_ack, |
| 93 | 93 | }; |
| 94 | 94 | |
| 95 | −static int s3c2440_irq_add(struct device *dev) | |
| 95 | +static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif) | |
| 96 | 96 | { |
| 97 | 97 | unsigned int irqno; |
| 98 | 98 | |
| @@ -270,7 +270,8 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = { · 269 unmodified lines | ||
| 270 | 270 | .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), |
| 271 | 271 | }; |
| 272 | 272 | |
| 273 | −static int s3c2440_cpufreq_add(struct device *dev) | |
| 273 | +static int s3c2440_cpufreq_add(struct device *dev, | |
| 274 | + struct subsys_interface *sif) | |
| 274 | 275 | { |
| 275 | 276 | xtal = s3c_cpufreq_clk_get(NULL, "xtal"); |
| 276 | 277 | hclk = s3c_cpufreq_clk_get(NULL, "hclk"); |
| @@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { · 50 unmodified lines | ||
| 51 | 51 | { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ |
| 52 | 52 | }; |
| 53 | 53 | |
| 54 | −static int s3c2440_plls12_add(struct device *dev) | |
| 54 | +static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif) | |
| 55 | 55 | { |
| 56 | 56 | struct clk *xtal_clk; |
| 57 | 57 | unsigned long xtal; |
| @@ -79,7 +79,8 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { · 78 unmodified lines | ||
| 79 | 79 | { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ |
| 80 | 80 | }; |
| 81 | 81 | |
| 82 | −static int s3c2440_plls169344_add(struct device *dev) | |
| 82 | +static int s3c2440_plls169344_add(struct device *dev, | |
| 83 | + struct subsys_interface *sif) | |
| 83 | 84 | { |
| 84 | 85 | struct clk *xtal_clk; |
| 85 | 86 | unsigned long xtal; |
| @@ -122,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = { · 121 unmodified lines | ||
| 122 | 122 | }, |
| 123 | 123 | }; |
| 124 | 124 | |
| 125 | −static int s3c2442_clk_add(struct device *dev) | |
| 125 | +static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif) | |
| 126 | 126 | { |
| 127 | 127 | struct clk *clock_upll; |
| 128 | 128 | struct clk *clock_h; |
| @@ -72,7 +72,7 @@ static struct clk clk_arm = { · 71 unmodified lines | ||
| 72 | 72 | }, |
| 73 | 73 | }; |
| 74 | 74 | |
| 75 | −static int s3c244x_clk_add(struct device *dev) | |
| 75 | +static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif) | |
| 76 | 76 | { |
| 77 | 77 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); |
| 78 | 78 | unsigned long clkdivn; |
| @@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = { · 90 unmodified lines | ||
| 91 | 91 | .irq_ack = s3c_irq_cam_ack, |
| 92 | 92 | }; |
| 93 | 93 | |
| 94 | −static int s3c244x_irq_add(struct device *dev) | |
| 94 | +static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif) | |
| 95 | 95 | { |
| 96 | 96 | unsigned int irqno; |
| 97 | 97 | |
| @@ -135,7 +135,8 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = { · 134 unmodified lines | ||
| 135 | 135 | .map_size = ARRAY_SIZE(s3c2443_dma_mappings), |
| 136 | 136 | }; |
| 137 | 137 | |
| 138 | −static int __init s3c2443_dma_add(struct device *dev) | |
| 138 | +static int __init s3c2443_dma_add(struct device *dev, | |
| 139 | + struct subsys_interface *sif) | |
| 139 | 140 | { |
| 140 | 141 | s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); |
| 141 | 142 | return s3c24xx_dma_init_map(&s3c2443_dma_sel); |
| @@ -241,7 +241,8 @@ static int __init s3c2443_add_sub(unsigned int base, · 240 unmodified lines | ||
| 241 | 241 | return 0; |
| 242 | 242 | } |
| 243 | 243 | |
| 244 | −static int __init s3c2443_irq_add(struct device *dev) | |
| 244 | +static int __init s3c2443_irq_add(struct device *dev, | |
| 245 | + struct subsys_interface *sif) | |
| 245 | 246 | { |
| 246 | 247 | printk("S3C2443: IRQ Support\n"); |
| 247 | 248 | |
| @@ -138,6 +138,11 @@ static struct clk init_clocks_off[] = { · 137 unmodified lines | ||
| 138 | 138 | .ctrlbit = S3C_CLKCON_PCLK_TSADC, |
| 139 | 139 | }, { |
| 140 | 140 | .name = "i2c", |
| 141 | +#ifdef CONFIG_S3C_DEV_I2C1 | |
| 142 | + .devname = "s3c2440-i2c.0", | |
| 143 | +#else | |
| 144 | + .devname = "s3c2440-i2c", | |
| 145 | +#endif | |
| 141 | 146 | .parent = &clk_p, |
| 142 | 147 | .enable = s3c64xx_pclk_ctrl, |
| 143 | 148 | .ctrlbit = S3C_CLKCON_PCLK_IIC, |
| @@ -49,7 +49,7 @@ · 48 unmodified lines | ||
| 49 | 49 | |
| 50 | 50 | /* uart registration process */ |
| 51 | 51 | |
| 52 | −void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |
| 52 | +static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |
| 53 | 53 | { |
| 54 | 54 | s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); |
| 55 | 55 | } |
| @@ -21,5 +21,6 @@ · 20 unmodified lines | ||
| 21 | 21 | #define CODEC_GPIO_BASE (GPIO_BOARD_START + 8) |
| 22 | 22 | #define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 32) |
| 23 | 23 | #define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 64) |
| 24 | +#define MMGPIO_GPIO_BASE (GPIO_BOARD_START + 96) | |
| 24 | 25 | |
| 25 | 26 | #endif |
| @@ -260,6 +260,7 @@ static struct platform_device crag6410_dm9k_device = { · 259 unmodified lines | ||
| 260 | 260 | |
| 261 | 261 | static struct resource crag6410_mmgpio_resource[] = { |
| 262 | 262 | [0] = { |
| 263 | + .name = "dat", | |
| 263 | 264 | .start = S3C64XX_PA_XM0CSN4 + 1, |
| 264 | 265 | .end = S3C64XX_PA_XM0CSN4 + 1, |
| 265 | 266 | .flags = IORESOURCE_MEM, |
| @@ -272,7 +273,7 @@ static struct platform_device crag6410_mmgpio = { · 6 unmodified lines | ||
| 272 | 273 | .resource = crag6410_mmgpio_resource, |
| 273 | 274 | .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource), |
| 274 | 275 | .dev.platform_data = &(struct bgpio_pdata) { |
| 275 | − .base = -1, | |
| 276 | + .base = MMGPIO_GPIO_BASE, | |
| 276 | 277 | }, |
| 277 | 278 | }; |
| 278 | 279 | |
| @@ -328,7 +329,6 @@ static struct platform_device wallvdd_device = { · 49 unmodified lines | ||
| 328 | 329 | |
| 329 | 330 | static struct platform_device *crag6410_devices[] __initdata = { |
| 330 | 331 | &s3c_device_hsmmc0, |
| 331 | − &s3c_device_hsmmc1, | |
| 332 | 332 | &s3c_device_hsmmc2, |
| 333 | 333 | &s3c_device_i2c0, |
| 334 | 334 | &s3c_device_i2c1, |
| @@ -355,7 +355,7 @@ static struct platform_device *crag6410_devices[] __initdata = { · 20 unmodified lines | ||
| 355 | 355 | |
| 356 | 356 | static struct pca953x_platform_data crag6410_pca_data = { |
| 357 | 357 | .gpio_base = PCA935X_GPIO_BASE, |
| 358 | − .irq_base = 0, | |
| 358 | + .irq_base = -1, | |
| 359 | 359 | }; |
| 360 | 360 | |
| 361 | 361 | /* VDDARM is controlled by DVS1 connected to GPK(0) */ |
| @@ -683,12 +683,6 @@ static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = { · 321 unmodified lines | ||
| 683 | 683 | .cd_type = S3C_SDHCI_CD_PERMANENT, |
| 684 | 684 | }; |
| 685 | 685 | |
| 686 | −static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = { | |
| 687 | − .max_width = 4, | |
| 688 | − .cd_type = S3C_SDHCI_CD_GPIO, | |
| 689 | − .ext_cd_gpio = S3C64XX_GPF(11), | |
| 690 | −}; | |
| 691 | − | |
| 692 | 686 | static void crag6410_cfg_sdhci0(struct platform_device *dev, int width) |
| 693 | 687 | { |
| 694 | 688 | /* Set all the necessary GPG pins to special-function 2 */ |
| @@ -723,7 +717,6 @@ static void __init crag6410_machine_init(void) · 28 unmodified lines | ||
| 723 | 717 | gpio_direction_output(S3C64XX_GPF(10), 1); |
| 724 | 718 | |
| 725 | 719 | s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata); |
| 726 | − s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata); | |
| 727 | 720 | s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata); |
| 728 | 721 | |
| 729 | 722 | s3c_i2c0_set_platdata(&i2c0_pdata); |
| @@ -346,23 +346,10 @@ int __init s3c64xx_pm_init(void) · 345 unmodified lines | ||
| 346 | 346 | |
| 347 | 347 | static __init int s3c64xx_pm_initcall(void) |
| 348 | 348 | { |
| 349 | − u32 val; | |
| 350 | − | |
| 351 | 349 | pm_cpu_prep = s3c64xx_pm_prepare; |
| 352 | 350 | pm_cpu_sleep = s3c64xx_cpu_suspend; |
| 353 | 351 | pm_uart_udivslot = 1; |
| 354 | 352 | |
| 355 | − /* | |
| 356 | − * Unconditionally disable power domains that contain only | |
| 357 | − * blocks which have no mainline driver support. | |
| 358 | − */ | |
| 359 | − val = __raw_readl(S3C64XX_NORMAL_CFG); | |
| 360 | − val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON | | |
| 361 | − S3C64XX_NORMALCFG_DOMAIN_V_ON | | |
| 362 | − S3C64XX_NORMALCFG_DOMAIN_I_ON | | |
| 363 | − S3C64XX_NORMALCFG_DOMAIN_P_ON); | |
| 364 | − __raw_writel(val, S3C64XX_NORMAL_CFG); | |
| 365 | − | |
| 366 | 353 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK |
| 367 | 354 | gpio_request(S3C64XX_GPN(12), "DEBUG_LED0"); |
| 368 | 355 | gpio_request(S3C64XX_GPN(13), "DEBUG_LED1"); |
| @@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void) · 159 unmodified lines | ||
| 160 | 160 | |
| 161 | 161 | } |
| 162 | 162 | |
| 163 | −static int s5p64x0_pm_add(struct device *dev) | |
| 163 | +static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif) | |
| 164 | 164 | { |
| 165 | 165 | pm_cpu_prep = s5p64x0_pm_prepare; |
| 166 | 166 | pm_cpu_sleep = s5p64x0_cpu_suspend; |
| @@ -175,7 +175,7 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) · 174 unmodified lines | ||
| 175 | 175 | return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); |
| 176 | 176 | } |
| 177 | 177 | |
| 178 | −static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) | |
| 178 | +static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable) | |
| 179 | 179 | { |
| 180 | 180 | return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); |
| 181 | 181 | } |
| @@ -372,7 +372,7 @@ static struct clk init_clocks_off[] = { · 190 unmodified lines | ||
| 372 | 372 | }, { |
| 373 | 373 | .name = "hdmiphy", |
| 374 | 374 | .devname = "s5pv210-hdmi", |
| 375 | − .enable = exynos4_clk_hdmiphy_ctrl, | |
| 375 | + .enable = s5pv210_clk_hdmiphy_ctrl, | |
| 376 | 376 | .ctrlbit = (1 << 0), |
| 377 | 377 | }, { |
| 378 | 378 | .name = "dacphy", |
| @@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void) · 132 unmodified lines | ||
| 133 | 133 | s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); |
| 134 | 134 | } |
| 135 | 135 | |
| 136 | −static int s5pv210_pm_add(struct device *dev) | |
| 136 | +static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif) | |
| 137 | 137 | { |
| 138 | 138 | pm_cpu_prep = s5pv210_pm_prepare; |
| 139 | 139 | pm_cpu_sleep = s5pv210_cpu_suspend; |
| @@ -202,7 +202,6 @@ static struct irda_platform_data assabet_irda_data = { · 201 unmodified lines | ||
| 202 | 202 | static struct mcp_plat_data assabet_mcp_data = { |
| 203 | 203 | .mccr0 = MCCR0_ADM, |
| 204 | 204 | .sclk_rate = 11981000, |
| 205 | − .codec = "ucb1x00", | |
| 206 | 205 | }; |
| 207 | 206 | |
| 208 | 207 | static void __init assabet_init(void) |
| @@ -253,17 +252,6 @@ static void __init assabet_init(void) · 44 unmodified lines | ||
| 253 | 252 | sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources, |
| 254 | 253 | ARRAY_SIZE(assabet_flash_resources)); |
| 255 | 254 | sa11x0_register_irda(&assabet_irda_data); |
| 256 | − | |
| 257 | − /* | |
| 258 | − * Setup the PPC unit correctly. | |
| 259 | − */ | |
| 260 | − PPDR &= ~PPC_RXD4; | |
| 261 | − PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | |
| 262 | − PSDR |= PPC_RXD4; | |
| 263 | − PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 264 | − PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 265 | − | |
| 266 | − ASSABET_BCR_set(ASSABET_BCR_CODEC_RST); | |
| 267 | 255 | sa11x0_register_mcp(&assabet_mcp_data); |
| 268 | 256 | } |
| 269 | 257 | |
| @@ -124,23 +124,12 @@ static void __init cerf_map_io(void) · 123 unmodified lines | ||
| 124 | 124 | static struct mcp_plat_data cerf_mcp_data = { |
| 125 | 125 | .mccr0 = MCCR0_ADM, |
| 126 | 126 | .sclk_rate = 11981000, |
| 127 | − .codec = "ucb1x00", | |
| 128 | 127 | }; |
| 129 | 128 | |
| 130 | 129 | static void __init cerf_init(void) |
| 131 | 130 | { |
| 132 | 131 | platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices)); |
| 133 | 132 | sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1); |
| 134 | − | |
| 135 | − /* | |
| 136 | − * Setup the PPC unit correctly. | |
| 137 | − */ | |
| 138 | − PPDR &= ~PPC_RXD4; | |
| 139 | − PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | |
| 140 | − PSDR |= PPC_RXD4; | |
| 141 | − PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 142 | − PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 143 | − | |
| 144 | 133 | sa11x0_register_mcp(&cerf_mcp_data); |
| 145 | 134 | } |
| 146 | 135 | |
| @@ -11,39 +11,17 @@ · 10 unmodified lines | ||
| 11 | 11 | #include <linux/clk.h> |
| 12 | 12 | #include <linux/spinlock.h> |
| 13 | 13 | #include <linux/mutex.h> |
| 14 | −#include <linux/io.h> | |
| 15 | −#include <linux/clkdev.h> | |
| 16 | 14 | |
| 17 | 15 | #include <mach/hardware.h> |
| 18 | 16 | |
| 19 | −struct clkops { | |
| 20 | − void (*enable)(struct clk *); | |
| 21 | − void (*disable)(struct clk *); | |
| 22 | − unsigned long (*getrate)(struct clk *); | |
| 23 | −}; | |
| 24 | − | |
| 17 | +/* | |
| 18 | + * Very simple clock implementation - we only have one clock to deal with. | |
| 19 | + */ | |
| 25 | 20 | struct clk { |
| 26 | − const struct clkops *ops; | |
| 27 | − unsigned long rate; | |
| 28 | 21 | unsigned int enabled; |
| 29 | 22 | }; |
| 30 | 23 | |
| 31 | −#define INIT_CLKREG(_clk, _devname, _conname) \ | |
| 32 | − { \ | |
| 33 | − .clk = _clk, \ | |
| 34 | − .dev_id = _devname, \ | |
| 35 | − .con_id = _conname, \ | |
| 36 | − } | |
| 37 | − | |
| 38 | −#define DEFINE_CLK(_name, _ops, _rate) \ | |
| 39 | −struct clk clk_##_name = { \ | |
| 40 | − .ops = _ops, \ | |
| 41 | − .rate = _rate, \ | |
| 42 | − } | |
| 43 | − | |
| 44 | −static DEFINE_SPINLOCK(clocks_lock); | |
| 45 | − | |
| 46 | −static void clk_gpio27_enable(struct clk *clk) | |
| 24 | +static void clk_gpio27_enable(void) | |
| 47 | 25 | { |
| 48 | 26 | /* |
| 49 | 27 | * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: |
| @@ -54,22 +32,38 @@ static void clk_gpio27_enable(struct clk *clk) · 4 unmodified lines | ||
| 54 | 32 | TUCR = TUCR_3_6864MHz; |
| 55 | 33 | } |
| 56 | 34 | |
| 57 | −static void clk_gpio27_disable(struct clk *clk) | |
| 35 | +static void clk_gpio27_disable(void) | |
| 58 | 36 | { |
| 59 | 37 | TUCR = 0; |
| 60 | 38 | GPDR &= ~GPIO_32_768kHz; |
| 61 | 39 | GAFR &= ~GPIO_32_768kHz; |
| 62 | 40 | } |
| 63 | 41 | |
| 42 | +static struct clk clk_gpio27; | |
| 43 | + | |
| 44 | +static DEFINE_SPINLOCK(clocks_lock); | |
| 45 | + | |
| 46 | +struct clk *clk_get(struct device *dev, const char *id) | |
| 47 | +{ | |
| 48 | + const char *devname = dev_name(dev); | |
| 49 | + | |
| 50 | + return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27; | |
| 51 | +} | |
| 52 | +EXPORT_SYMBOL(clk_get); | |
| 53 | + | |
| 54 | +void clk_put(struct clk *clk) | |
| 55 | +{ | |
| 56 | +} | |
| 57 | +EXPORT_SYMBOL(clk_put); | |
| 58 | + | |
| 64 | 59 | int clk_enable(struct clk *clk) |
| 65 | 60 | { |
| 66 | 61 | unsigned long flags; |
| 67 | 62 | |
| 68 | 63 | spin_lock_irqsave(&clocks_lock, flags); |
| 69 | 64 | if (clk->enabled++ == 0) |
| 70 | − clk->ops->enable(clk); | |
| 65 | + clk_gpio27_enable(); | |
| 71 | 66 | spin_unlock_irqrestore(&clocks_lock, flags); |
| 72 | − | |
| 73 | 67 | return 0; |
| 74 | 68 | } |
| 75 | 69 | EXPORT_SYMBOL(clk_enable); |
| @@ -82,48 +76,13 @@ void clk_disable(struct clk *clk) · 6 unmodified lines | ||
| 82 | 76 | |
| 83 | 77 | spin_lock_irqsave(&clocks_lock, flags); |
| 84 | 78 | if (--clk->enabled == 0) |
| 85 | − clk->ops->disable(clk); | |
| 79 | + clk_gpio27_disable(); | |
| 86 | 80 | spin_unlock_irqrestore(&clocks_lock, flags); |
| 87 | 81 | } |
| 88 | 82 | EXPORT_SYMBOL(clk_disable); |
| 89 | 83 | |
| 90 | 84 | unsigned long clk_get_rate(struct clk *clk) |
| 91 | 85 | { |
| 92 | − unsigned long rate; | |
| 93 | − | |
| 94 | − rate = clk->rate; | |
| 95 | − if (clk->ops->getrate) | |
| 96 | − rate = clk->ops->getrate(clk); | |
| 97 | − | |
| 98 | − return rate; | |
| 86 | + return 3686400; | |
| 99 | 87 | } |
| 100 | 88 | EXPORT_SYMBOL(clk_get_rate); |
| 101 | − | |
| 102 | −const struct clkops clk_gpio27_ops = { | |
| 103 | − .enable = clk_gpio27_enable, | |
| 104 | − .disable = clk_gpio27_disable, | |
| 105 | −}; | |
| 106 | − | |
| 107 | −static void clk_dummy_enable(struct clk *clk) { } | |
| 108 | −static void clk_dummy_disable(struct clk *clk) { } | |
| 109 | − | |
| 110 | −const struct clkops clk_dummy_ops = { | |
| 111 | − .enable = clk_dummy_enable, | |
| 112 | − .disable = clk_dummy_disable, | |
| 113 | −}; | |
| 114 | − | |
| 115 | −static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400); | |
| 116 | −static DEFINE_CLK(dummy, &clk_dummy_ops, 0); | |
| 117 | − | |
| 118 | −static struct clk_lookup sa11xx_clkregs[] = { | |
| 119 | − INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL), | |
| 120 | − INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), | |
| 121 | −}; | |
| 122 | − | |
| 123 | −static int __init sa11xx_clk_init(void) | |
| 124 | −{ | |
| 125 | − clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); | |
| 126 | − return 0; | |
| 127 | −} | |
| 128 | − | |
| 129 | −postcore_initcall(sa11xx_clk_init); | |
| @@ -27,7 +27,6 @@ · 26 unmodified lines | ||
| 27 | 27 | #include <linux/timer.h> |
| 28 | 28 | #include <linux/gpio.h> |
| 29 | 29 | #include <linux/pda_power.h> |
| 30 | −#include <linux/mfd/ucb1x00.h> | |
| 31 | 30 | |
| 32 | 31 | #include <mach/hardware.h> |
| 33 | 32 | #include <asm/mach-types.h> |
| @@ -86,15 +85,10 @@ static struct scoop_pcmcia_config collie_pcmcia_config = { · 52 unmodified lines | ||
| 86 | 85 | .num_devs = 1, |
| 87 | 86 | }; |
| 88 | 87 | |
| 89 | −static struct ucb1x00_plat_data collie_ucb1x00_data = { | |
| 90 | − .gpio_base = COLLIE_TC35143_GPIO_BASE, | |
| 91 | −}; | |
| 92 | − | |
| 93 | 88 | static struct mcp_plat_data collie_mcp_data = { |
| 94 | 89 | .mccr0 = MCCR0_ADM | MCCR0_ExtClk, |
| 95 | 90 | .sclk_rate = 9216000, |
| 96 | − .codec = "ucb1x00", | |
| 97 | − .codec_pdata = &collie_ucb1x00_data, | |
| 91 | + .gpio_base = COLLIE_TC35143_GPIO_BASE, | |
| 98 | 92 | }; |
| 99 | 93 | |
| 100 | 94 | /* |
| @@ -144,8 +138,6 @@ static struct pda_power_pdata collie_power_data = { · 43 unmodified lines | ||
| 144 | 138 | static struct resource collie_power_resource[] = { |
| 145 | 139 | { |
| 146 | 140 | .name = "ac", |
| 147 | − .start = gpio_to_irq(COLLIE_GPIO_AC_IN), | |
| 148 | − .end = gpio_to_irq(COLLIE_GPIO_AC_IN), | |
| 149 | 141 | .flags = IORESOURCE_IRQ | |
| 150 | 142 | IORESOURCE_IRQ_HIGHEDGE | |
| 151 | 143 | IORESOURCE_IRQ_LOWEDGE, |
| @@ -347,7 +339,8 @@ static void __init collie_init(void) · 195 unmodified lines | ||
| 347 | 339 | |
| 348 | 340 | GPSR |= _COLLIE_GPIO_UCB1x00_RESET; |
| 349 | 341 | |
| 350 | − | |
| 342 | + collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN); | |
| 343 | + collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN); | |
| 351 | 344 | platform_scoop_config = &collie_pcmcia_config; |
| 352 | 345 | |
| 353 | 346 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
| @@ -357,16 +350,6 @@ static void __init collie_init(void) · 3 unmodified lines | ||
| 357 | 350 | |
| 358 | 351 | sa11x0_register_mtd(&collie_flash_data, collie_flash_resources, |
| 359 | 352 | ARRAY_SIZE(collie_flash_resources)); |
| 360 | − | |
| 361 | − /* | |
| 362 | − * Setup the PPC unit correctly. | |
| 363 | − */ | |
| 364 | − PPDR &= ~PPC_RXD4; | |
| 365 | − PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | |
| 366 | − PSDR |= PPC_RXD4; | |
| 367 | − PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 368 | − PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 369 | − | |
| 370 | 353 | sa11x0_register_mcp(&collie_mcp_data); |
| 371 | 354 | |
| 372 | 355 | sharpsl_save_param(); |
| @@ -228,7 +228,7 @@ static int __init sa1100_cpu_init(struct cpufreq_policy *policy) · 227 unmodified lines | ||
| 228 | 228 | return 0; |
| 229 | 229 | } |
| 230 | 230 | |
| 231 | −static struct cpufreq_driver sa1100_driver = { | |
| 231 | +static struct cpufreq_driver sa1100_driver __refdata = { | |
| 232 | 232 | .flags = CPUFREQ_STICKY, |
| 233 | 233 | .verify = sa11x0_verify_speed, |
| 234 | 234 | .target = sa1100_target, |
| @@ -217,15 +217,10 @@ static struct platform_device sa11x0uart3_device = { · 216 unmodified lines | ||
| 217 | 217 | static struct resource sa11x0mcp_resources[] = { |
| 218 | 218 | [0] = { |
| 219 | 219 | .start = __PREG(Ser4MCCR0), |
| 220 | − .end = __PREG(Ser4MCCR0) + 0x1C - 1, | |
| 220 | + .end = __PREG(Ser4MCCR0) + 0xffff, | |
| 221 | 221 | .flags = IORESOURCE_MEM, |
| 222 | 222 | }, |
| 223 | 223 | [1] = { |
| 224 | − .start = __PREG(Ser4MCCR1), | |
| 225 | − .end = __PREG(Ser4MCCR1) + 0x4 - 1, | |
| 226 | − .flags = IORESOURCE_MEM, | |
| 227 | − }, | |
| 228 | − [2] = { | |
| 229 | 224 | .start = IRQ_Ser4MCP, |
| 230 | 225 | .end = IRQ_Ser4MCP, |
| 231 | 226 | .flags = IORESOURCE_IRQ, |
| @@ -350,29 +345,9 @@ void sa11x0_register_irda(struct irda_platform_data *irda) · 118 unmodified lines | ||
| 350 | 345 | sa11x0_register_device(&sa11x0ir_device, irda); |
| 351 | 346 | } |
| 352 | 347 | |
| 353 | −static struct resource sa11x0rtc_resources[] = { | |
| 354 | − [0] = { | |
| 355 | − .start = 0x90010000, | |
| 356 | − .end = 0x900100ff, | |
| 357 | − .flags = IORESOURCE_MEM, | |
| 358 | − }, | |
| 359 | − [1] = { | |
| 360 | − .start = IRQ_RTC1Hz, | |
| 361 | − .end = IRQ_RTC1Hz, | |
| 362 | − .flags = IORESOURCE_IRQ, | |
| 363 | − }, | |
| 364 | − [2] = { | |
| 365 | − .start = IRQ_RTCAlrm, | |
| 366 | − .end = IRQ_RTCAlrm, | |
| 367 | − .flags = IORESOURCE_IRQ, | |
| 368 | − }, | |
| 369 | −}; | |
| 370 | − | |
| 371 | 348 | static struct platform_device sa11x0rtc_device = { |
| 372 | 349 | .name = "sa1100-rtc", |
| 373 | 350 | .id = -1, |
| 374 | − .resource = sa11x0rtc_resources, | |
| 375 | − .num_resources = ARRAY_SIZE(sa11x0rtc_resources), | |
| 376 | 351 | }; |
| 377 | 352 | |
| 378 | 353 | static struct platform_device *sa11x0_devices[] __initdata = { |
| @@ -17,8 +17,6 @@ struct mcp_plat_data { · 16 unmodified lines | ||
| 17 | 17 | u32 mccr1; |
| 18 | 18 | unsigned int sclk_rate; |
| 19 | 19 | int gpio_base; |
| 20 | − const char *codec; | |
| 21 | − void *codec_pdata; | |
| 22 | 20 | }; |
| 23 | 21 | |
| 24 | 22 | #endif |
| @@ -198,3 +198,5 @@ static int __init jornada_ssp_init(void) · 197 unmodified lines | ||
| 198 | 198 | { |
| 199 | 199 | return platform_driver_register(&jornadassp_driver); |
| 200 | 200 | } |
| 201 | + | |
| 202 | +module_init(jornada_ssp_init); | |
| @@ -24,20 +24,10 @@ · 23 unmodified lines | ||
| 24 | 24 | static struct mcp_plat_data lart_mcp_data = { |
| 25 | 25 | .mccr0 = MCCR0_ADM, |
| 26 | 26 | .sclk_rate = 11981000, |
| 27 | − .codec = "ucb1x00", | |
| 28 | 27 | }; |
| 29 | 28 | |
| 30 | 29 | static void __init lart_init(void) |
| 31 | 30 | { |
| 32 | − /* | |
| 33 | − * Setup the PPC unit correctly. | |
| 34 | − */ | |
| 35 | − PPDR &= ~PPC_RXD4; | |
| 36 | − PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | |
| 37 | − PSDR |= PPC_RXD4; | |
| 38 | − PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 39 | − PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 40 | − | |
| 41 | 31 | sa11x0_register_mcp(&lart_mcp_data); |
| 42 | 32 | } |
| 43 | 33 | |
| @@ -55,22 +55,11 @@ static struct resource shannon_flash_resource = { · 54 unmodified lines | ||
| 55 | 55 | static struct mcp_plat_data shannon_mcp_data = { |
| 56 | 56 | .mccr0 = MCCR0_ADM, |
| 57 | 57 | .sclk_rate = 11981000, |
| 58 | − .codec = "ucb1x00", | |
| 59 | 58 | }; |
| 60 | 59 | |
| 61 | 60 | static void __init shannon_init(void) |
| 62 | 61 | { |
| 63 | 62 | sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1); |
| 64 | − | |
| 65 | − /* | |
| 66 | − * Setup the PPC unit correctly. | |
| 67 | − */ | |
| 68 | − PPDR &= ~PPC_RXD4; | |
| 69 | − PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | |
| 70 | − PSDR |= PPC_RXD4; | |
| 71 | − PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 72 | − PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 73 | − | |
| 74 | 63 | sa11x0_register_mcp(&shannon_mcp_data); |
| 75 | 64 | } |
| 76 | 65 | |
| @@ -14,7 +14,6 @@ · 13 unmodified lines | ||
| 14 | 14 | #include <linux/mtd/partitions.h> |
| 15 | 15 | #include <linux/io.h> |
| 16 | 16 | #include <linux/gpio.h> |
| 17 | −#include <linux/mfd/ucb1x00.h> | |
| 18 | 17 | |
| 19 | 18 | #include <asm/irq.h> |
| 20 | 19 | #include <mach/hardware.h> |
| @@ -188,15 +187,10 @@ static struct resource simpad_flash_resources [] = { · 167 unmodified lines | ||
| 188 | 187 | } |
| 189 | 188 | }; |
| 190 | 189 | |
| 191 | −static struct ucb1x00_plat_data simpad_ucb1x00_data = { | |
| 192 | − .gpio_base = SIMPAD_UCB1X00_GPIO_BASE, | |
| 193 | −}; | |
| 194 | − | |
| 195 | 190 | static struct mcp_plat_data simpad_mcp_data = { |
| 196 | 191 | .mccr0 = MCCR0_ADM, |
| 197 | 192 | .sclk_rate = 11981000, |
| 198 | − .codec = "ucb1300", | |
| 199 | − .codec_pdata = &simpad_ucb1x00_data, | |
| 193 | + .gpio_base = SIMPAD_UCB1X00_GPIO_BASE, | |
| 200 | 194 | }; |
| 201 | 195 | |
| 202 | 196 | |
| @@ -384,16 +378,6 @@ static int __init simpad_init(void) · 181 unmodified lines | ||
| 384 | 378 | |
| 385 | 379 | sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, |
| 386 | 380 | ARRAY_SIZE(simpad_flash_resources)); |
| 387 | − | |
| 388 | − /* | |
| 389 | − * Setup the PPC unit correctly. | |
| 390 | − */ | |
| 391 | − PPDR &= ~PPC_RXD4; | |
| 392 | − PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | |
| 393 | − PSDR |= PPC_RXD4; | |
| 394 | − PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 395 | − PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | |
| 396 | − | |
| 397 | 381 | sa11x0_register_mcp(&simpad_mcp_data); |
| 398 | 382 | |
| 399 | 383 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
| @@ -445,31 +445,39 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { · 444 unmodified lines | ||
| 445 | 445 | }, |
| 446 | 446 | }; |
| 447 | 447 | |
| 448 | +#define SH7372_CHCLR 0x220 | |
| 449 | + | |
| 448 | 450 | static const struct sh_dmae_channel sh7372_dmae_channels[] = { |
| 449 | 451 | { |
| 450 | 452 | .offset = 0, |
| 451 | 453 | .dmars = 0, |
| 452 | 454 | .dmars_bit = 0, |
| 455 | + .chclr_offset = SH7372_CHCLR + 0, | |
| 453 | 456 | }, { |
| 454 | 457 | .offset = 0x10, |
| 455 | 458 | .dmars = 0, |
| 456 | 459 | .dmars_bit = 8, |
| 460 | + .chclr_offset = SH7372_CHCLR + 0x10, | |
| 457 | 461 | }, { |
| 458 | 462 | .offset = 0x20, |
| 459 | 463 | .dmars = 4, |
| 460 | 464 | .dmars_bit = 0, |
| 465 | + .chclr_offset = SH7372_CHCLR + 0x20, | |
| 461 | 466 | }, { |
| 462 | 467 | .offset = 0x30, |
| 463 | 468 | .dmars = 4, |
| 464 | 469 | .dmars_bit = 8, |
| 470 | + .chclr_offset = SH7372_CHCLR + 0x30, | |
| 465 | 471 | }, { |
| 466 | 472 | .offset = 0x50, |
| 467 | 473 | .dmars = 8, |
| 468 | 474 | .dmars_bit = 0, |
| 475 | + .chclr_offset = SH7372_CHCLR + 0x50, | |
| 469 | 476 | }, { |
| 470 | 477 | .offset = 0x60, |
| 471 | 478 | .dmars = 8, |
| 472 | 479 | .dmars_bit = 8, |
| 480 | + .chclr_offset = SH7372_CHCLR + 0x60, | |
| 473 | 481 | } |
| 474 | 482 | }; |
| 475 | 483 | |
| @@ -487,6 +495,7 @@ static struct sh_dmae_pdata dma_platform_data = { · 11 unmodified lines | ||
| 487 | 495 | .ts_shift = ts_shift, |
| 488 | 496 | .ts_shift_num = ARRAY_SIZE(ts_shift), |
| 489 | 497 | .dmaor_init = DMAOR_DME, |
| 498 | + .chclr_present = 1, | |
| 490 | 499 | }; |
| 491 | 500 | |
| 492 | 501 | /* Resource order important! */ |
| @@ -494,7 +503,7 @@ static struct resource sh7372_dmae0_resources[] = { · 1 unmodified line | ||
| 494 | 503 | { |
| 495 | 504 | /* Channel registers and DMAOR */ |
| 496 | 505 | .start = 0xfe008020, |
| 497 | − .end = 0xfe00808f, | |
| 506 | + .end = 0xfe00828f, | |
| 498 | 507 | .flags = IORESOURCE_MEM, |
| 499 | 508 | }, |
| 500 | 509 | { |
| @@ -522,7 +531,7 @@ static struct resource sh7372_dmae1_resources[] = { · 21 unmodified lines | ||
| 522 | 531 | { |
| 523 | 532 | /* Channel registers and DMAOR */ |
| 524 | 533 | .start = 0xfe018020, |
| 525 | − .end = 0xfe01808f, | |
| 534 | + .end = 0xfe01828f, | |
| 526 | 535 | .flags = IORESOURCE_MEM, |
| 527 | 536 | }, |
| 528 | 537 | { |
| @@ -550,7 +559,7 @@ static struct resource sh7372_dmae2_resources[] = { · 21 unmodified lines | ||
| 550 | 559 | { |
| 551 | 560 | /* Channel registers and DMAOR */ |
| 552 | 561 | .start = 0xfe028020, |
| 553 | − .end = 0xfe02808f, | |
| 562 | + .end = 0xfe02828f, | |
| 554 | 563 | .flags = IORESOURCE_MEM, |
| 555 | 564 | }, |
| 556 | 565 | { |
| @@ -653,6 +662,7 @@ static struct sh_dmae_pdata usb_dma0_platform_data = { · 96 unmodified lines | ||
| 653 | 662 | .dmaor_is_32bit = 1, |
| 654 | 663 | .needs_tend_set = 1, |
| 655 | 664 | .no_dmars = 1, |
| 665 | + .slave_only = 1, | |
| 656 | 666 | }; |
| 657 | 667 | |
| 658 | 668 | static struct resource sh7372_usb_dmae0_resources[] = { |
| @@ -714,6 +724,7 @@ static struct sh_dmae_pdata usb_dma1_platform_data = { · 55 unmodified lines | ||
| 714 | 724 | .dmaor_is_32bit = 1, |
| 715 | 725 | .needs_tend_set = 1, |
| 716 | 726 | .no_dmars = 1, |
| 727 | + .slave_only = 1, | |
| 717 | 728 | }; |
| 718 | 729 | |
| 719 | 730 | static struct resource sh7372_usb_dmae1_resources[] = { |
| @@ -25,6 +25,7 @@ · 24 unmodified lines | ||
| 25 | 25 | #include <linux/delay.h> |
| 26 | 26 | #include <mach/common.h> |
| 27 | 27 | #include <mach/r8a7779.h> |
| 28 | +#include <asm/smp_plat.h> | |
| 28 | 29 | #include <asm/smp_scu.h> |
| 29 | 30 | #include <asm/smp_twd.h> |
| 30 | 31 | #include <asm/hardware/gic.h> |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | #include <linux/spinlock.h> |
| 24 | 24 | #include <linux/io.h> |
| 25 | 25 | #include <mach/common.h> |
| 26 | +#include <asm/smp_plat.h> | |
| 26 | 27 | #include <asm/smp_scu.h> |
| 27 | 28 | #include <asm/smp_twd.h> |
| 28 | 29 | #include <asm/hardware/gic.h> |
| @@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { · 59 unmodified lines | ||
| 60 | 60 | .uartclk = 216000000, |
| 61 | 61 | }, { |
| 62 | 62 | /* serial port on mini-pcie */ |
| 63 | − .membase = IO_ADDRESS(TEGRA_UARTD_BASE), | |
| 64 | − .mapbase = TEGRA_UARTD_BASE, | |
| 65 | − .irq = INT_UARTD, | |
| 63 | + .membase = IO_ADDRESS(TEGRA_UARTC_BASE), | |
| 64 | + .mapbase = TEGRA_UARTC_BASE, | |
| 65 | + .irq = INT_UARTC, | |
| 66 | 66 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, |
| 67 | 67 | .type = PORT_TEGRA, |
| 68 | 68 | .iotype = UPIO_MEM, |
| @@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline, · 105 unmodified lines | ||
| 174 | 174 | static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { |
| 175 | 175 | /* name parent rate enabled */ |
| 176 | 176 | { "uarta", "pll_p", 216000000, true }, |
| 177 | − { "uartd", "pll_p", 216000000, true }, | |
| 177 | + { "uartc", "pll_p", 216000000, true }, | |
| 178 | 178 | |
| 179 | 179 | { "pll_p_out4", "pll_p", 24000000, true }, |
| 180 | 180 | { "usbd", "clk_m", 12000000, false }, |
| @@ -22,7 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | /* SDCARD */ |
| 23 | 23 | #define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 |
| 24 | 24 | #define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 |
| 25 | −#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 | |
| 25 | +#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1 | |
| 26 | 26 | |
| 27 | 27 | /* ULPI */ |
| 28 | 28 | #define TEGRA_ULPI_RST TEGRA_GPIO_PV0 |
| @@ -23,11 +23,6 @@ · 22 unmodified lines | ||
| 23 | 23 | |
| 24 | 24 | #include <linux/list.h> |
| 25 | 25 | |
| 26 | −#if defined(CONFIG_TEGRA_SYSTEM_DMA) | |
| 27 | − | |
| 28 | −struct tegra_dma_req; | |
| 29 | −struct tegra_dma_channel; | |
| 30 | − | |
| 31 | 26 | #define TEGRA_DMA_REQ_SEL_CNTR 0 |
| 32 | 27 | #define TEGRA_DMA_REQ_SEL_I2S_2 1 |
| 33 | 28 | #define TEGRA_DMA_REQ_SEL_I2S_1 2 |
| @@ -56,6 +51,11 @@ struct tegra_dma_channel; · 22 unmodified lines | ||
| 56 | 51 | #define TEGRA_DMA_REQ_SEL_OWR 25 |
| 57 | 52 | #define TEGRA_DMA_REQ_SEL_INVALID 31 |
| 58 | 53 | |
| 54 | +#if defined(CONFIG_TEGRA_SYSTEM_DMA) | |
| 55 | + | |
| 56 | +struct tegra_dma_req; | |
| 57 | +struct tegra_dma_channel; | |
| 58 | + | |
| 59 | 59 | enum tegra_dma_mode { |
| 60 | 60 | TEGRA_DMA_SHARED = 1, |
| 61 | 61 | TEGRA_DMA_MODE_CONTINOUS = 2, |
| @@ -7,6 +7,7 @@ config UX500_SOC_COMMON · 6 unmodified lines | ||
| 7 | 7 | select HAS_MTU |
| 8 | 8 | select ARM_ERRATA_753970 |
| 9 | 9 | select ARM_ERRATA_754322 |
| 10 | + select ARM_ERRATA_764369 | |
| 10 | 11 | |
| 11 | 12 | menu "Ux500 SoC" |
| 12 | 13 | |
| @@ -261,6 +261,8 @@ void __init mop500_sdi_init(void) · 260 unmodified lines | ||
| 261 | 261 | |
| 262 | 262 | void __init snowball_sdi_init(void) |
| 263 | 263 | { |
| 264 | + /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */ | |
| 265 | + mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED; | |
| 264 | 266 | /* On-board eMMC */ |
| 265 | 267 | db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); |
| 266 | 268 | /* External Micro SD slot */ |
| @@ -12,44 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | |
| 13 | 13 | static void __iomem *l2x0_base; |
| 14 | 14 | |
| 15 | −static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) | |
| 16 | −{ | |
| 17 | − /* wait for the operation to complete */ | |
| 18 | − while (readl_relaxed(reg) & mask) | |
| 19 | − cpu_relax(); | |
| 20 | −} | |
| 21 | − | |
| 22 | −static inline void ux500_cache_sync(void) | |
| 23 | −{ | |
| 24 | − writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC); | |
| 25 | − ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1); | |
| 26 | −} | |
| 27 | − | |
| 28 | −/* | |
| 29 | − * The L2 cache cannot be turned off in the non-secure world. | |
| 30 | − * Dummy until a secure service is in place. | |
| 31 | − */ | |
| 32 | −static void ux500_l2x0_disable(void) | |
| 33 | −{ | |
| 34 | −} | |
| 35 | − | |
| 36 | −/* | |
| 37 | − * This is only called when doing a kexec, just after turning off the L2 | |
| 38 | − * and L1 cache, and it is surrounded by a spinlock in the generic version. | |
| 39 | − * However, we're not really turning off the L2 cache right now and the | |
| 40 | − * PL310 does not support exclusive accesses (used to implement the spinlock). | |
| 41 | − * So, the invalidation needs to be done without the spinlock. | |
| 42 | − */ | |
| 43 | −static void ux500_l2x0_inv_all(void) | |
| 44 | −{ | |
| 45 | − uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ | |
| 46 | − | |
| 47 | − /* invalidate all ways */ | |
| 48 | − writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); | |
| 49 | − ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); | |
| 50 | − ux500_cache_sync(); | |
| 51 | −} | |
| 52 | − | |
| 53 | 15 | static int __init ux500_l2x0_unlock(void) |
| 54 | 16 | { |
| 55 | 17 | int i; |
| @@ -85,9 +47,13 @@ static int __init ux500_l2x0_init(void) · 29 unmodified lines | ||
| 85 | 47 | /* 64KB way size, 8 way associativity, force WA */ |
| 86 | 48 | l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); |
| 87 | 49 | |
| 88 | − /* Override invalidate function */ | |
| 89 | − outer_cache.disable = ux500_l2x0_disable; | |
| 90 | − outer_cache.inv_all = ux500_l2x0_inv_all; | |
| 50 | + /* | |
| 51 | + * We can't disable l2 as we are in non secure mode, currently | |
| 52 | + * this seems be called only during kexec path. So let's | |
| 53 | + * override outer.disable with nasty assignment until we have | |
| 54 | + * some SMI service available. | |
| 55 | + */ | |
| 56 | + outer_cache.disable = NULL; | |
| 91 | 57 | |
| 92 | 58 | return 0; |
| 93 | 59 | } |
| @@ -32,6 +32,8 @@ pen: ldr r7, [r6] · 31 unmodified lines | ||
| 32 | 32 | * should now contain the SVC stack for this core |
| 33 | 33 | */ |
| 34 | 34 | b secondary_startup |
| 35 | +ENDPROC(u8500_secondary_startup) | |
| 35 | 36 | |
| 37 | + .align 2 | |
| 36 | 38 | 1: .long . |
| 37 | 39 | .long pen_release |
| @@ -13,6 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | #include <linux/smp.h> |
| 14 | 14 | |
| 15 | 15 | #include <asm/cacheflush.h> |
| 16 | +#include <asm/smp_plat.h> | |
| 16 | 17 | |
| 17 | 18 | extern volatile int pen_release; |
| 18 | 19 | |
| @@ -19,6 +19,7 @@ · 18 unmodified lines | ||
| 19 | 19 | |
| 20 | 20 | #include <asm/cacheflush.h> |
| 21 | 21 | #include <asm/hardware/gic.h> |
| 22 | +#include <asm/smp_plat.h> | |
| 22 | 23 | #include <asm/smp_scu.h> |
| 23 | 24 | #include <mach/hardware.h> |
| 24 | 25 | #include <mach/setup.h> |
| @@ -95,13 +95,7 @@ static struct musb_hdrc_config musb_hdrc_config = { · 94 unmodified lines | ||
| 95 | 95 | }; |
| 96 | 96 | |
| 97 | 97 | static struct musb_hdrc_platform_data musb_platform_data = { |
| 98 | −#if defined(CONFIG_USB_MUSB_OTG) | |
| 99 | 98 | .mode = MUSB_OTG, |
| 100 | −#elif defined(CONFIG_USB_MUSB_PERIPHERAL) | |
| 101 | − .mode = MUSB_PERIPHERAL, | |
| 102 | −#else /* defined(CONFIG_USB_MUSB_HOST) */ | |
| 103 | − .mode = MUSB_HOST, | |
| 104 | −#endif | |
| 105 | 99 | .config = &musb_hdrc_config, |
| 106 | 100 | .board_data = &musb_board_data, |
| 107 | 101 | }; |
| @@ -217,7 +217,7 @@ static void __init ct_ca9x4_init(void) · 216 unmodified lines | ||
| 217 | 217 | } |
| 218 | 218 | |
| 219 | 219 | #ifdef CONFIG_SMP |
| 220 | −static void ct_ca9x4_init_cpu_map(void) | |
| 220 | +static void __init ct_ca9x4_init_cpu_map(void) | |
| 221 | 221 | { |
| 222 | 222 | int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); |
| 223 | 223 | |
| @@ -233,7 +233,7 @@ static void ct_ca9x4_init_cpu_map(void) · 9 unmodified lines | ||
| 233 | 233 | set_smp_cross_call(gic_raise_softirq); |
| 234 | 234 | } |
| 235 | 235 | |
| 236 | −static void ct_ca9x4_smp_enable(unsigned int max_cpus) | |
| 236 | +static void __init ct_ca9x4_smp_enable(unsigned int max_cpus) | |
| 237 | 237 | { |
| 238 | 238 | scu_enable(MMIO_P2V(A9_MPCORE_SCU)); |
| 239 | 239 | } |
| @@ -13,6 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | #include <linux/smp.h> |
| 14 | 14 | |
| 15 | 15 | #include <asm/cacheflush.h> |
| 16 | +#include <asm/smp_plat.h> | |
| 16 | 17 | #include <asm/system.h> |
| 17 | 18 | |
| 18 | 19 | extern volatile int pen_release; |
| @@ -13,8 +13,6 @@ · 12 unmodified lines | ||
| 13 | 13 | #include <linux/smp.h> |
| 14 | 14 | #include <linux/io.h> |
| 15 | 15 | |
| 16 | −#include <asm/unified.h> | |
| 17 | − | |
| 18 | 16 | #include <mach/motherboard.h> |
| 19 | 17 | #define V2M_PA_CS7 0x10000000 |
| 20 | 18 | |
| @@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) · 25 unmodified lines | ||
| 46 | 44 | * secondary CPU branches to this address. |
| 47 | 45 | */ |
| 48 | 46 | writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); |
| 49 | − writel(BSYM(virt_to_phys(versatile_secondary_startup)), | |
| 47 | + writel(virt_to_phys(versatile_secondary_startup), | |
| 50 | 48 | MMIO_P2V(V2M_SYS_FLAGSSET)); |
| 51 | 49 | } |
| @@ -631,7 +631,8 @@ comment "Processor Features" · 630 unmodified lines | ||
| 631 | 631 | |
| 632 | 632 | config ARM_LPAE |
| 633 | 633 | bool "Support for the Large Physical Address Extension" |
| 634 | − depends on MMU && CPU_V7 | |
| 634 | + depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ | |
| 635 | + !CPU_32v4 && !CPU_32v3 | |
| 635 | 636 | help |
| 636 | 637 | Say Y if you have an ARMv7 processor supporting the LPAE page |
| 637 | 638 | table format and you would like to access memory beyond the |
| @@ -882,6 +883,7 @@ config CACHE_XSC3L2 · 244 unmodified lines | ||
| 882 | 883 | |
| 883 | 884 | config ARM_L1_CACHE_SHIFT_6 |
| 884 | 885 | bool |
| 886 | + default y if CPU_V7 | |
| 885 | 887 | help |
| 886 | 888 | Setting ARM L1 cache line size to 64 Bytes. |
| 887 | 889 | |
| @@ -54,9 +54,15 @@ loop1: · 53 unmodified lines | ||
| 54 | 54 | and r1, r1, #7 @ mask of the bits for current cache only |
| 55 | 55 | cmp r1, #2 @ see what cache we have at this level |
| 56 | 56 | blt skip @ skip if no cache, or just i-cache |
| 57 | +#ifdef CONFIG_PREEMPT | |
| 58 | + save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic | |
| 59 | +#endif | |
| 57 | 60 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr |
| 58 | 61 | isb @ isb to sych the new cssr&csidr |
| 59 | 62 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr |
| 63 | +#ifdef CONFIG_PREEMPT | |
| 64 | + restore_irqs_notrace r9 | |
| 65 | +#endif | |
| 60 | 66 | and r2, r1, #7 @ extract the length of the cache lines |
| 61 | 67 | add r2, r2, #4 @ add 4 (line length offset) |
| 62 | 68 | ldr r4, =0x3ff |
| @@ -310,7 +310,7 @@ static void arm_memory_present(void) · 309 unmodified lines | ||
| 310 | 310 | |
| 311 | 311 | static bool arm_memblock_steal_permitted = true; |
| 312 | 312 | |
| 313 | −phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align) | |
| 313 | +phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align) | |
| 314 | 314 | { |
| 315 | 315 | phys_addr_t phys; |
| 316 | 316 | |
| @@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume) · 147 unmodified lines | ||
| 148 | 148 | * Initialise TLB, Caches, and MMU state ready to switch the MMU |
| 149 | 149 | * on. Return in r0 the new CP15 C1 control register setting. |
| 150 | 150 | * |
| 151 | − * We automatically detect if we have a Harvard cache, and use the | |
| 152 | − * Harvard cache control instructions insead of the unified cache | |
| 153 | − * control instructions. | |
| 154 | − * | |
| 155 | 151 | * This should be able to cover all ARMv7 cores. |
| 156 | 152 | * |
| 157 | 153 | * It is assumed that: |
| @@ -251,9 +247,7 @@ __v7_setup: · 93 unmodified lines | ||
| 251 | 247 | #endif |
| 252 | 248 | |
| 253 | 249 | 3: mov r10, #0 |
| 254 | −#ifdef HARVARD_CACHE | |
| 255 | 250 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |
| 256 | −#endif | |
| 257 | 251 | dsb |
| 258 | 252 | #ifdef CONFIG_MMU |
| 259 | 253 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
| @@ -329,16 +323,6 @@ __v7_ca5mp_proc_info: · 69 unmodified lines | ||
| 329 | 323 | __v7_proc __v7_ca5mp_setup |
| 330 | 324 | .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info |
| 331 | 325 | |
| 332 | − /* | |
| 333 | − * ARM Ltd. Cortex A7 processor. | |
| 334 | − */ | |
| 335 | − .type __v7_ca7mp_proc_info, #object | |
| 336 | −__v7_ca7mp_proc_info: | |
| 337 | − .long 0x410fc070 | |
| 338 | − .long 0xff0ffff0 | |
| 339 | − __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV | |
| 340 | − .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info | |
| 341 | − | |
| 342 | 326 | /* |
| 343 | 327 | * ARM Ltd. Cortex A9 processor. |
| 344 | 328 | */ |
| @@ -350,6 +334,16 @@ __v7_ca9mp_proc_info: · 5 unmodified lines | ||
| 350 | 334 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
| 351 | 335 | #endif /* CONFIG_ARM_LPAE */ |
| 352 | 336 | |
| 337 | + /* | |
| 338 | + * ARM Ltd. Cortex A7 processor. | |
| 339 | + */ | |
| 340 | + .type __v7_ca7mp_proc_info, #object | |
| 341 | +__v7_ca7mp_proc_info: | |
| 342 | + .long 0x410fc070 | |
| 343 | + .long 0xff0ffff0 | |
| 344 | + __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV | |
| 345 | + .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info | |
| 346 | + | |
| 353 | 347 | /* |
| 354 | 348 | * ARM Ltd. Cortex A15 processor. |
| 355 | 349 | */ |
| @@ -17,26 +17,17 @@ config ARCH_IMX_V4_V5 · 16 unmodified lines | ||
| 17 | 17 | and ARMv5 SoCs |
| 18 | 18 | |
| 19 | 19 | config ARCH_IMX_V6_V7 |
| 20 | − bool "i.MX3, i.MX6" | |
| 20 | + bool "i.MX3, i.MX5, i.MX6" | |
| 21 | 21 | select AUTO_ZRELADDR if !ZBOOT_ROM |
| 22 | 22 | select ARM_PATCH_PHYS_VIRT |
| 23 | 23 | select MIGHT_HAVE_CACHE_L2X0 |
| 24 | 24 | help |
| 25 | − This enables support for systems based on the Freescale i.MX3 and i.MX6 | |
| 26 | − family. | |
| 27 | − | |
| 28 | −config ARCH_MX5 | |
| 29 | − bool "i.MX50, i.MX51, i.MX53" | |
| 30 | − select AUTO_ZRELADDR if !ZBOOT_ROM | |
| 31 | − select ARM_PATCH_PHYS_VIRT | |
| 32 | − help | |
| 33 | − This enables support for machines using Freescale's i.MX50 and i.MX53 | |
| 34 | − processors. | |
| 25 | + This enables support for systems based on the Freescale i.MX3, i.MX5 | |
| 26 | + and i.MX6 family. | |
| 35 | 27 | |
| 36 | 28 | endchoice |
| 37 | 29 | |
| 38 | 30 | source "arch/arm/mach-imx/Kconfig" |
| 39 | −source "arch/arm/mach-mx5/Kconfig" | |
| 40 | 31 | |
| 41 | 32 | endmenu |
| 42 | 33 | |
| @@ -96,6 +96,6 @@ extern int mxc_gpio_mode(int gpio_mode); · 95 unmodified lines | ||
| 96 | 96 | extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, |
| 97 | 97 | const char *label); |
| 98 | 98 | |
| 99 | −extern int __init imx_iomuxv1_init(void __iomem *base, int numports); | |
| 99 | +extern int imx_iomuxv1_init(void __iomem *base, int numports); | |
| 100 | 100 | |
| 101 | 101 | #endif /* __MACH_IOMUX_V1_H__ */ |
| @@ -22,6 +22,20 @@ · 21 unmodified lines | ||
| 22 | 22 | #define FB_SYNC_SWAP_RGB 0x04000000 |
| 23 | 23 | #define FB_SYNC_CLK_SEL_EN 0x02000000 |
| 24 | 24 | |
| 25 | +/* | |
| 26 | + * Specify the way your display is connected. The IPU can arbitrarily | |
| 27 | + * map the internal colors to the external data lines. We only support | |
| 28 | + * the following mappings at the moment. | |
| 29 | + */ | |
| 30 | +enum disp_data_mapping { | |
| 31 | + /* blue -> d[0..5], green -> d[6..11], red -> d[12..17] */ | |
| 32 | + IPU_DISP_DATA_MAPPING_RGB666, | |
| 33 | + /* blue -> d[0..4], green -> d[5..10], red -> d[11..15] */ | |
| 34 | + IPU_DISP_DATA_MAPPING_RGB565, | |
| 35 | + /* blue -> d[0..7], green -> d[8..15], red -> d[16..23] */ | |
| 36 | + IPU_DISP_DATA_MAPPING_RGB888, | |
| 37 | +}; | |
| 38 | + | |
| 25 | 39 | /** |
| 26 | 40 | * struct mx3fb_platform_data - mx3fb platform data |
| 27 | 41 | * |
| @@ -33,6 +47,7 @@ struct mx3fb_platform_data { · 5 unmodified lines | ||
| 33 | 47 | const char *name; |
| 34 | 48 | const struct fb_videomode *mode; |
| 35 | 49 | int num_modes; |
| 50 | + enum disp_data_mapping disp_data_fmt; | |
| 36 | 51 | }; |
| 37 | 52 | |
| 38 | 53 | #endif |
| @@ -113,7 +113,8 @@ struct stedma40_half_channel_info { · 112 unmodified lines | ||
| 113 | 113 | * @dst_dev_type: Dst device type |
| 114 | 114 | * @src_info: Parameters for dst half channel |
| 115 | 115 | * @dst_info: Parameters for dst half channel |
| 116 | − * | |
| 116 | + * @use_fixed_channel: if true, use physical channel specified by phy_channel | |
| 117 | + * @phy_channel: physical channel to use, only if use_fixed_channel is true | |
| 117 | 118 | * |
| 118 | 119 | * This structure has to be filled by the client drivers. |
| 119 | 120 | * It is recommended to do all dma configurations for clients in the machine. |
| @@ -129,6 +130,9 @@ struct stedma40_chan_cfg { · 9 unmodified lines | ||
| 129 | 130 | int dst_dev_type; |
| 130 | 131 | struct stedma40_half_channel_info src_info; |
| 131 | 132 | struct stedma40_half_channel_info dst_info; |
| 133 | + | |
| 134 | + bool use_fixed_channel; | |
| 135 | + int phy_channel; | |
| 132 | 136 | }; |
| 133 | 137 | |
| 134 | 138 | /** |
| @@ -153,6 +157,7 @@ struct stedma40_platform_data { · 18 unmodified lines | ||
| 153 | 157 | struct stedma40_chan_cfg *memcpy_conf_phy; |
| 154 | 158 | struct stedma40_chan_cfg *memcpy_conf_log; |
| 155 | 159 | int disabled_channels[STEDMA40_MAX_PHYS]; |
| 160 | + bool use_esram_lcla; | |
| 156 | 161 | }; |
| 157 | 162 | |
| 158 | 163 | #ifdef CONFIG_STE_DMA40 |
| @@ -187,7 +192,7 @@ static inline struct · 28 unmodified lines | ||
| 187 | 192 | dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, |
| 188 | 193 | dma_addr_t addr, |
| 189 | 194 | unsigned int size, |
| 190 | − enum dma_data_direction direction, | |
| 195 | + enum dma_transfer_direction direction, | |
| 191 | 196 | unsigned long flags) |
| 192 | 197 | { |
| 193 | 198 | struct scatterlist sg; |
| @@ -209,7 +214,7 @@ static inline struct · 15 unmodified lines | ||
| 209 | 214 | dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, |
| 210 | 215 | dma_addr_t addr, |
| 211 | 216 | unsigned int size, |
| 212 | − enum dma_data_direction direction, | |
| 217 | + enum dma_transfer_direction direction, | |
| 213 | 218 | unsigned long flags) |
| 214 | 219 | { |
| 215 | 220 | return NULL; |
| @@ -3,7 +3,7 @@ · 2 unmodified lines | ||
| 3 | 3 | |
| 4 | 4 | #include <linux/types.h> |
| 5 | 5 | |
| 6 | −#ifdef CONFIG_ARCH_OMAP2PLUS | |
| 6 | +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | |
| 7 | 7 | extern int omap_secure_ram_reserve_memblock(void); |
| 8 | 8 | #else |
| 9 | 9 | static inline void omap_secure_ram_reserve_memblock(void) |
| @@ -789,10 +789,7 @@ void __init orion_xor1_init(unsigned long mapbase_low, · 788 unmodified lines | ||
| 789 | 789 | /***************************************************************************** |
| 790 | 790 | * EHCI |
| 791 | 791 | ****************************************************************************/ |
| 792 | −static struct orion_ehci_data orion_ehci_data = { | |
| 793 | − .phy_version = EHCI_PHY_NA, | |
| 794 | −}; | |
| 795 | − | |
| 792 | +static struct orion_ehci_data orion_ehci_data; | |
| 796 | 793 | static u64 ehci_dmamask = DMA_BIT_MASK(32); |
| 797 | 794 | |
| 798 | 795 | |
| @@ -812,8 +809,10 @@ static struct platform_device orion_ehci = { · 13 unmodified lines | ||
| 812 | 809 | }; |
| 813 | 810 | |
| 814 | 811 | void __init orion_ehci_init(unsigned long mapbase, |
| 815 | − unsigned long irq) | |
| 812 | + unsigned long irq, | |
| 813 | + enum orion_ehci_phy_ver phy_version) | |
| 816 | 814 | { |
| 815 | + orion_ehci_data.phy_version = phy_version; | |
| 817 | 816 | fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, |
| 818 | 817 | irq); |
| 819 | 818 | |
| @@ -89,7 +89,8 @@ void __init orion_xor1_init(unsigned long mapbase_low, · 88 unmodified lines | ||
| 89 | 89 | unsigned long irq_1); |
| 90 | 90 | |
| 91 | 91 | void __init orion_ehci_init(unsigned long mapbase, |
| 92 | − unsigned long irq); | |
| 92 | + unsigned long irq, | |
| 93 | + enum orion_ehci_phy_ver phy_version); | |
| 93 | 94 | |
| 94 | 95 | void __init orion_ehci_1_init(unsigned long mapbase, |
| 95 | 96 | unsigned long irq); |
| @@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, · 63 unmodified lines | ||
| 64 | 64 | gpio_mode |= GPIO_INPUT_OK; |
| 65 | 65 | if (*mpp_list & MPP_OUTPUT_MASK) |
| 66 | 66 | gpio_mode |= GPIO_OUTPUT_OK; |
| 67 | − if (sel != 0) | |
| 68 | − gpio_mode = 0; | |
| 67 | + | |
| 69 | 68 | orion_gpio_set_valid(num, gpio_mode); |
| 70 | 69 | } |
| 71 | 70 | |
| @@ -468,8 +468,10 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) · 467 unmodified lines | ||
| 468 | 468 | { |
| 469 | 469 | struct s3c2410_platform_i2c *npd; |
| 470 | 470 | |
| 471 | − if (!pd) | |
| 471 | + if (!pd) { | |
| 472 | 472 | pd = &default_i2c_data; |
| 473 | + pd->bus_num = 0; | |
| 474 | + } | |
| 473 | 475 | |
| 474 | 476 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
| 475 | 477 | &s3c_device_i2c0); |
| @@ -37,14 +37,14 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch, · 36 unmodified lines | ||
| 37 | 37 | (void *)dma_ch; |
| 38 | 38 | chan = dma_request_channel(mask, pl330_filter, filter_param); |
| 39 | 39 | |
| 40 | − if (info->direction == DMA_FROM_DEVICE) { | |
| 40 | + if (info->direction == DMA_DEV_TO_MEM) { | |
| 41 | 41 | memset(&slave_config, 0, sizeof(struct dma_slave_config)); |
| 42 | 42 | slave_config.direction = info->direction; |
| 43 | 43 | slave_config.src_addr = info->fifo; |
| 44 | 44 | slave_config.src_addr_width = info->width; |
| 45 | 45 | slave_config.src_maxburst = 1; |
| 46 | 46 | dmaengine_slave_config(chan, &slave_config); |
| 47 | − } else if (info->direction == DMA_TO_DEVICE) { | |
| 47 | + } else if (info->direction == DMA_MEM_TO_DEV) { | |
| 48 | 48 | memset(&slave_config, 0, sizeof(struct dma_slave_config)); |
| 49 | 49 | slave_config.direction = info->direction; |
| 50 | 50 | slave_config.dst_addr = info->fifo; |
| @@ -14,10 +14,11 @@ · 13 unmodified lines | ||
| 14 | 14 | #define __SAMSUNG_DMA_OPS_H_ __FILE__ |
| 15 | 15 | |
| 16 | 16 | #include <linux/dmaengine.h> |
| 17 | +#include <mach/dma.h> | |
| 17 | 18 | |
| 18 | 19 | struct samsung_dma_prep_info { |
| 19 | 20 | enum dma_transaction_type cap; |
| 20 | − enum dma_data_direction direction; | |
| 21 | + enum dma_transfer_direction direction; | |
| 21 | 22 | dma_addr_t buf; |
| 22 | 23 | unsigned long period; |
| 23 | 24 | unsigned long len; |
| @@ -27,7 +28,7 @@ struct samsung_dma_prep_info { · 3 unmodified lines | ||
| 27 | 28 | |
| 28 | 29 | struct samsung_dma_info { |
| 29 | 30 | enum dma_transaction_type cap; |
| 30 | − enum dma_data_direction direction; | |
| 31 | + enum dma_transfer_direction direction; | |
| 31 | 32 | enum dma_slave_buswidth width; |
| 32 | 33 | dma_addr_t fifo; |
| 33 | 34 | struct s3c2410_dma_client *client; |
| @@ -10,6 +10,9 @@ · 9 unmodified lines | ||
| 10 | 10 | * published by the Free Software Foundation. |
| 11 | 11 | */ |
| 12 | 12 | |
| 13 | +#ifndef __PLAT_DMA_H | |
| 14 | +#define __PLAT_DMA_H | |
| 15 | + | |
| 13 | 16 | #include <linux/dma-mapping.h> |
| 14 | 17 | |
| 15 | 18 | enum s3c2410_dma_buffresult { |
| @@ -122,5 +125,6 @@ extern int s3c2410_dma_getposition(enum dma_ch channel, · 106 unmodified lines | ||
| 122 | 125 | extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn); |
| 123 | 126 | extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn); |
| 124 | 127 | |
| 125 | − | |
| 126 | 128 | #include <plat/dma-ops.h> |
| 129 | + | |
| 130 | +#endif | |
| @@ -11,6 +11,8 @@ · 10 unmodified lines | ||
| 11 | 11 | #ifndef __S3C64XX_PLAT_SPI_H |
| 12 | 12 | #define __S3C64XX_PLAT_SPI_H |
| 13 | 13 | |
| 14 | +struct platform_device; | |
| 15 | + | |
| 14 | 16 | /** |
| 15 | 17 | * struct s3c64xx_spi_csinfo - ChipSelect description |
| 16 | 18 | * @fb_delay: Slave specific feedback delay. |
| @@ -38,3 +38,4 @@ pen: ldr r7, [r6] · 37 unmodified lines | ||
| 38 | 38 | .align |
| 39 | 39 | 1: .long . |
| 40 | 40 | .long pen_release |
| 41 | +ENDPROC(versatile_secondary_startup) | |
| @@ -16,6 +16,7 @@ · 15 unmodified lines | ||
| 16 | 16 | #include <linux/smp.h> |
| 17 | 17 | |
| 18 | 18 | #include <asm/cacheflush.h> |
| 19 | +#include <asm/smp_plat.h> | |
| 19 | 20 | #include <asm/hardware/gic.h> |
| 20 | 21 | |
| 21 | 22 | /* |
| @@ -8,6 +8,7 @@ config AVR32 · 7 unmodified lines | ||
| 8 | 8 | select HAVE_KPROBES |
| 9 | 9 | select HAVE_GENERIC_HARDIRQS |
| 10 | 10 | select GENERIC_IRQ_PROBE |
| 11 | + select GENERIC_ATOMIC64 | |
| 11 | 12 | select HARDIRQS_SW_RESEND |
| 12 | 13 | select GENERIC_IRQ_SHOW |
| 13 | 14 | select ARCH_HAVE_NMI_SAFE_CMPXCHG |
| @@ -246,7 +246,18 @@ static inline unsigned long user_stack_pointer(struct pt_regs *regs) · 245 unmodified lines | ||
| 246 | 246 | return regs->ar_bspstore; |
| 247 | 247 | } |
| 248 | 248 | |
| 249 | −#define regs_return_value(regs) ((regs)->r8) | |
| 249 | +static inline int is_syscall_success(struct pt_regs *regs) | |
| 250 | +{ | |
| 251 | + return regs->r10 != -1; | |
| 252 | +} | |
| 253 | + | |
| 254 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 255 | +{ | |
| 256 | + if (is_syscall_success(regs)) | |
| 257 | + return regs->r8; | |
| 258 | + else | |
| 259 | + return -regs->r8; | |
| 260 | +} | |
| 250 | 261 | |
| 251 | 262 | /* Conserve space in histogram by encoding slot bits in address |
| 252 | 263 | * bits 2 and 3 rather than bits 0 and 1. |
| @@ -429,22 +429,24 @@ static u32 __devinitdata pxm_flag[PXM_FLAG_LEN]; · 428 unmodified lines | ||
| 429 | 429 | static struct acpi_table_slit __initdata *slit_table; |
| 430 | 430 | cpumask_t early_cpu_possible_map = CPU_MASK_NONE; |
| 431 | 431 | |
| 432 | −static int get_processor_proximity_domain(struct acpi_srat_cpu_affinity *pa) | |
| 432 | +static int __init | |
| 433 | +get_processor_proximity_domain(struct acpi_srat_cpu_affinity *pa) | |
| 433 | 434 | { |
| 434 | 435 | int pxm; |
| 435 | 436 | |
| 436 | 437 | pxm = pa->proximity_domain_lo; |
| 437 | − if (ia64_platform_is("sn2")) | |
| 438 | + if (ia64_platform_is("sn2") || acpi_srat_revision >= 2) | |
| 438 | 439 | pxm += pa->proximity_domain_hi[0] << 8; |
| 439 | 440 | return pxm; |
| 440 | 441 | } |
| 441 | 442 | |
| 442 | −static int get_memory_proximity_domain(struct acpi_srat_mem_affinity *ma) | |
| 443 | +static int __init | |
| 444 | +get_memory_proximity_domain(struct acpi_srat_mem_affinity *ma) | |
| 443 | 445 | { |
| 444 | 446 | int pxm; |
| 445 | 447 | |
| 446 | 448 | pxm = ma->proximity_domain; |
| 447 | − if (!ia64_platform_is("sn2")) | |
| 449 | + if (!ia64_platform_is("sn2") && acpi_srat_revision <= 1) | |
| 448 | 450 | pxm &= 0xff; |
| 449 | 451 | |
| 450 | 452 | return pxm; |
| @@ -1246,15 +1246,8 @@ syscall_trace_enter (long arg0, long arg1, long arg2, long arg3, · 1245 unmodified lines | ||
| 1246 | 1246 | if (test_thread_flag(TIF_RESTORE_RSE)) |
| 1247 | 1247 | ia64_sync_krbs(); |
| 1248 | 1248 | |
| 1249 | − if (unlikely(current->audit_context)) { | |
| 1250 | − long syscall; | |
| 1251 | − int arch; | |
| 1252 | 1249 | |
| 1253 | − syscall = regs.r15; | |
| 1254 | − arch = AUDIT_ARCH_IA64; | |
| 1255 | − | |
| 1256 | − audit_syscall_entry(arch, syscall, arg0, arg1, arg2, arg3); | |
| 1257 | − } | |
| 1250 | + audit_syscall_entry(AUDIT_ARCH_IA64, regs.r15, arg0, arg1, arg2, arg3); | |
| 1258 | 1251 | |
| 1259 | 1252 | return 0; |
| 1260 | 1253 | } |
| @@ -1268,14 +1261,7 @@ syscall_trace_leave (long arg0, long arg1, long arg2, long arg3, · 7 unmodified lines | ||
| 1268 | 1261 | { |
| 1269 | 1262 | int step; |
| 1270 | 1263 | |
| 1271 | − if (unlikely(current->audit_context)) { | |
| 1272 | − int success = AUDITSC_RESULT(regs.r10); | |
| 1273 | − long result = regs.r8; | |
| 1274 | − | |
| 1275 | − if (success != AUDITSC_SUCCESS) | |
| 1276 | − result = -result; | |
| 1277 | − audit_syscall_exit(success, result); | |
| 1278 | − } | |
| 1264 | + audit_syscall_exit(®s); | |
| 1279 | 1265 | |
| 1280 | 1266 | step = test_thread_flag(TIF_SINGLESTEP); |
| 1281 | 1267 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) |
| @@ -414,9 +414,9 @@ void __init config_atari(void) · 413 unmodified lines | ||
| 414 | 414 | * FDC val = 4 -> Supervisor only */ |
| 415 | 415 | asm volatile ("\n" |
| 416 | 416 | " .chip 68030\n" |
| 417 | − " pmove %0@,%/tt1\n" | |
| 417 | + " pmove %0,%/tt1\n" | |
| 418 | 418 | " .chip 68k" |
| 419 | − : : "a" (&tt1_val)); | |
| 419 | + : : "m" (tt1_val)); | |
| 420 | 420 | } else { |
| 421 | 421 | asm volatile ("\n" |
| 422 | 422 | " .chip 68040\n" |
| @@ -569,10 +569,10 @@ static void atari_reset(void) · 146 unmodified lines | ||
| 569 | 569 | : "d0"); |
| 570 | 570 | } else |
| 571 | 571 | asm volatile ("\n" |
| 572 | − " pmove %0@,%%tc\n" | |
| 572 | + " pmove %0,%%tc\n" | |
| 573 | 573 | " jmp %1@" |
| 574 | 574 | : /* no outputs */ |
| 575 | − : "a" (&tc_val), "a" (reset_addr)); | |
| 575 | + : "m" (tc_val), "a" (reset_addr)); | |
| 576 | 576 | } |
| 577 | 577 | |
| 578 | 578 | |
| @@ -50,19 +50,6 @@ · 49 unmodified lines | ||
| 50 | 50 | |
| 51 | 51 | #define IRQ_USER 8 |
| 52 | 52 | |
| 53 | −/* | |
| 54 | − * various flags for request_irq() - the Amiga now uses the standard | |
| 55 | − * mechanism like all other architectures - IRQF_DISABLED and | |
| 56 | − * IRQF_SHARED are your friends. | |
| 57 | − */ | |
| 58 | −#ifndef MACH_AMIGA_ONLY | |
| 59 | −#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */ | |
| 60 | −#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */ | |
| 61 | −#define IRQ_FLG_FAST (0x0004) | |
| 62 | −#define IRQ_FLG_SLOW (0x0008) | |
| 63 | −#define IRQ_FLG_STD (0x8000) /* internally used */ | |
| 64 | −#endif | |
| 65 | − | |
| 66 | 53 | struct irq_data; |
| 67 | 54 | struct irq_chip; |
| 68 | 55 | struct irq_desc; |
| @@ -78,7 +78,8 @@ · 77 unmodified lines | ||
| 78 | 78 | | CF_PAGE_READABLE \ |
| 79 | 79 | | CF_PAGE_WRITABLE \ |
| 80 | 80 | | CF_PAGE_EXEC \ |
| 81 | − | CF_PAGE_SYSTEM) | |
| 81 | + | CF_PAGE_SYSTEM \ | |
| 82 | + | CF_PAGE_SHARED) | |
| 82 | 83 | |
| 83 | 84 | #define PAGE_COPY __pgprot(CF_PAGE_VALID \ |
| 84 | 85 | | CF_PAGE_ACCESSED \ |
| @@ -172,7 +172,7 @@ void flush_thread(void) · 171 unmodified lines | ||
| 172 | 172 | |
| 173 | 173 | current->thread.fs = __USER_DS; |
| 174 | 174 | if (!FPU_IS_EMU) |
| 175 | − asm volatile ("frestore %0@" : : "a" (&zero) : "memory"); | |
| 175 | + asm volatile("frestore %0": :"m" (zero)); | |
| 176 | 176 | } |
| 177 | 177 | |
| 178 | 178 | /* |
| @@ -163,8 +163,8 @@ void flush_thread(void) · 162 unmodified lines | ||
| 163 | 163 | #ifdef CONFIG_FPU |
| 164 | 164 | if (!FPU_IS_EMU) |
| 165 | 165 | asm volatile (".chip 68k/68881\n\t" |
| 166 | − "frestore %0@\n\t" | |
| 167 | − ".chip 68k" : : "a" (&zero)); | |
| 166 | + "frestore %0\n\t" | |
| 167 | + ".chip 68k" : : "m" (zero)); | |
| 168 | 168 | #endif |
| 169 | 169 | } |
| 170 | 170 | |
| @@ -552,13 +552,13 @@ static inline void bus_error030 (struct frame *fp) · 551 unmodified lines | ||
| 552 | 552 | |
| 553 | 553 | #ifdef DEBUG |
| 554 | 554 | asm volatile ("ptestr %3,%2@,#7,%0\n\t" |
| 555 | − "pmove %%psr,%1@" | |
| 556 | − : "=a&" (desc) | |
| 557 | − : "a" (&temp), "a" (addr), "d" (ssw)); | |
| 555 | + "pmove %%psr,%1" | |
| 556 | + : "=a&" (desc), "=m" (temp) | |
| 557 | + : "a" (addr), "d" (ssw)); | |
| 558 | 558 | #else |
| 559 | 559 | asm volatile ("ptestr %2,%1@,#7\n\t" |
| 560 | − "pmove %%psr,%0@" | |
| 561 | − : : "a" (&temp), "a" (addr), "d" (ssw)); | |
| 560 | + "pmove %%psr,%0" | |
| 561 | + : "=m" (temp) : "a" (addr), "d" (ssw)); | |
| 562 | 562 | #endif |
| 563 | 563 | mmusr = temp; |
| 564 | 564 | |
| @@ -605,20 +605,18 @@ static inline void bus_error030 (struct frame *fp) · 40 unmodified lines | ||
| 605 | 605 | !(ssw & RW) ? "write" : "read", addr, |
| 606 | 606 | fp->ptregs.pc, ssw); |
| 607 | 607 | asm volatile ("ptestr #1,%1@,#0\n\t" |
| 608 | − "pmove %%psr,%0@" | |
| 609 | − : /* no outputs */ | |
| 610 | − : "a" (&temp), "a" (addr)); | |
| 608 | + "pmove %%psr,%0" | |
| 609 | + : "=m" (temp) | |
| 610 | + : "a" (addr)); | |
| 611 | 611 | mmusr = temp; |
| 612 | 612 | |
| 613 | 613 | printk ("level 0 mmusr is %#x\n", mmusr); |
| 614 | 614 | #if 0 |
| 615 | − asm volatile ("pmove %%tt0,%0@" | |
| 616 | − : /* no outputs */ | |
| 617 | − : "a" (&tlong)); | |
| 615 | + asm volatile ("pmove %%tt0,%0" | |
| 616 | + : "=m" (tlong)); | |
| 618 | 617 | printk("tt0 is %#lx, ", tlong); |
| 619 | − asm volatile ("pmove %%tt1,%0@" | |
| 620 | − : /* no outputs */ | |
| 621 | − : "a" (&tlong)); | |
| 618 | + asm volatile ("pmove %%tt1,%0" | |
| 619 | + : "=m" (tlong)); | |
| 622 | 620 | printk("tt1 is %#lx\n", tlong); |
| 623 | 621 | #endif |
| 624 | 622 | #ifdef DEBUG |
| @@ -668,13 +666,13 @@ static inline void bus_error030 (struct frame *fp) · 43 unmodified lines | ||
| 668 | 666 | |
| 669 | 667 | #ifdef DEBUG |
| 670 | 668 | asm volatile ("ptestr #1,%2@,#7,%0\n\t" |
| 671 | − "pmove %%psr,%1@" | |
| 672 | − : "=a&" (desc) | |
| 673 | − : "a" (&temp), "a" (addr)); | |
| 669 | + "pmove %%psr,%1" | |
| 670 | + : "=a&" (desc), "=m" (temp) | |
| 671 | + : "a" (addr)); | |
| 674 | 672 | #else |
| 675 | 673 | asm volatile ("ptestr #1,%1@,#7\n\t" |
| 676 | − "pmove %%psr,%0@" | |
| 677 | − : : "a" (&temp), "a" (addr)); | |
| 674 | + "pmove %%psr,%0" | |
| 675 | + : "=m" (temp) : "a" (addr)); | |
| 678 | 676 | #endif |
| 679 | 677 | mmusr = temp; |
| 680 | 678 | |
| @@ -52,9 +52,9 @@ static unsigned long virt_to_phys_slow(unsigned long vaddr) · 51 unmodified lines | ||
| 52 | 52 | unsigned long *descaddr; |
| 53 | 53 | |
| 54 | 54 | asm volatile ("ptestr %3,%2@,#7,%0\n\t" |
| 55 | − "pmove %%psr,%1@" | |
| 56 | − : "=a&" (descaddr) | |
| 57 | − : "a" (&mmusr), "a" (vaddr), "d" (get_fs().seg)); | |
| 55 | + "pmove %%psr,%1" | |
| 56 | + : "=a&" (descaddr), "=m" (mmusr) | |
| 57 | + : "a" (vaddr), "d" (get_fs().seg)); | |
| 58 | 58 | if (mmusr & (MMU_I|MMU_B|MMU_L)) |
| 59 | 59 | return 0; |
| 60 | 60 | descaddr = phys_to_virt((unsigned long)descaddr); |
| @@ -87,7 +87,7 @@ void __init paging_init(void) · 86 unmodified lines | ||
| 87 | 87 | |
| 88 | 88 | int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word) |
| 89 | 89 | { |
| 90 | − unsigned long flags, mmuar; | |
| 90 | + unsigned long flags, mmuar, mmutr; | |
| 91 | 91 | struct mm_struct *mm; |
| 92 | 92 | pgd_t *pgd; |
| 93 | 93 | pmd_t *pmd; |
| @@ -137,9 +137,10 @@ int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word) · 43 unmodified lines | ||
| 137 | 137 | if (!pte_dirty(*pte) && !KMAPAREA(mmuar)) |
| 138 | 138 | set_pte(pte, pte_wrprotect(*pte)); |
| 139 | 139 | |
| 140 | − mmu_write(MMUTR, (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) | | |
| 141 | − (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK) | |
| 142 | − >> CF_PAGE_MMUTR_SHIFT) | MMUTR_V); | |
| 140 | + mmutr = (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) | MMUTR_V; | |
| 141 | + if ((mmuar < TASK_UNMAPPED_BASE) || (mmuar >= TASK_SIZE)) | |
| 142 | + mmutr |= (pte->pte & CF_PAGE_MMUTR_MASK) >> CF_PAGE_MMUTR_SHIFT; | |
| 143 | + mmu_write(MMUTR, mmutr); | |
| 143 | 144 | |
| 144 | 145 | mmu_write(MMUDR, (pte_val(*pte) & PAGE_MASK) | |
| 145 | 146 | ((pte->pte) & CF_PAGE_MMUDR_MASK) | MMUDR_SZ_8KB | MMUDR_X); |
| @@ -136,7 +136,7 @@ Luser_return: · 135 unmodified lines | ||
| 136 | 136 | movel %sp,%d1 /* get thread_info pointer */ |
| 137 | 137 | andl #-THREAD_SIZE,%d1 /* at base of kernel stack */ |
| 138 | 138 | movel %d1,%a0 |
| 139 | − movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */ | |
| 139 | + moveb %a0@(TINFO_FLAGS+3),%d1 /* thread_info->flags (low 8 bits) */ | |
| 140 | 140 | jne Lwork_to_do /* still work to do */ |
| 141 | 141 | |
| 142 | 142 | Lreturn: |
| @@ -148,8 +148,6 @@ Lwork_to_do: · 5 unmodified lines | ||
| 148 | 148 | btst #TIF_NEED_RESCHED,%d1 |
| 149 | 149 | jne reschedule |
| 150 | 150 | |
| 151 | − /* GERG: do we need something here for TRACEing?? */ | |
| 152 | − | |
| 153 | 151 | Lsignal_return: |
| 154 | 152 | subql #4,%sp /* dummy return address */ |
| 155 | 153 | SAVE_SWITCH_STACK |
| @@ -19,6 +19,7 @@ config MICROBLAZE · 18 unmodified lines | ||
| 19 | 19 | select GENERIC_IRQ_SHOW |
| 20 | 20 | select GENERIC_PCI_IOMAP |
| 21 | 21 | select GENERIC_CPU_DEVICES |
| 22 | + select GENERIC_ATOMIC64 | |
| 22 | 23 | |
| 23 | 24 | config SWAP |
| 24 | 25 | def_bool n |
| @@ -2,6 +2,7 @@ · 1 unmodified line | ||
| 2 | 2 | #define _ASM_MICROBLAZE_ATOMIC_H |
| 3 | 3 | |
| 4 | 4 | #include <asm-generic/atomic.h> |
| 5 | +#include <asm-generic/atomic64.h> | |
| 5 | 6 | |
| 6 | 7 | /* |
| 7 | 8 | * Atomically test *v and decrement if it is greater than 0. |
| @@ -61,6 +61,11 @@ struct pt_regs { · 60 unmodified lines | ||
| 61 | 61 | #define instruction_pointer(regs) ((regs)->pc) |
| 62 | 62 | #define profile_pc(regs) instruction_pointer(regs) |
| 63 | 63 | |
| 64 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 65 | +{ | |
| 66 | + return regs->r3; | |
| 67 | +} | |
| 68 | + | |
| 64 | 69 | #else /* __KERNEL__ */ |
| 65 | 70 | |
| 66 | 71 | /* pt_regs offsets used by gdbserver etc in ptrace syscalls */ |
| @@ -147,10 +147,8 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) · 146 unmodified lines | ||
| 147 | 147 | */ |
| 148 | 148 | ret = -1L; |
| 149 | 149 | |
| 150 | − if (unlikely(current->audit_context)) | |
| 151 | − audit_syscall_entry(EM_MICROBLAZE, regs->r12, | |
| 152 | − regs->r5, regs->r6, | |
| 153 | − regs->r7, regs->r8); | |
| 150 | + audit_syscall_entry(EM_MICROBLAZE, regs->r12, regs->r5, regs->r6, | |
| 151 | + regs->r7, regs->r8); | |
| 154 | 152 | |
| 155 | 153 | return ret ?: regs->r12; |
| 156 | 154 | } |
| @@ -159,8 +157,7 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) · 2 unmodified lines | ||
| 159 | 157 | { |
| 160 | 158 | int step; |
| 161 | 159 | |
| 162 | − if (unlikely(current->audit_context)) | |
| 163 | − audit_syscall_exit(AUDITSC_RESULT(regs->r3), regs->r3); | |
| 160 | + audit_syscall_exit(regs); | |
| 164 | 161 | |
| 165 | 162 | step = test_thread_flag(TIF_SINGLESTEP); |
| 166 | 163 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) |
| @@ -2356,6 +2356,7 @@ config PCI · 2355 unmodified lines | ||
| 2356 | 2356 | depends on HW_HAS_PCI |
| 2357 | 2357 | select PCI_DOMAINS |
| 2358 | 2358 | select GENERIC_PCI_IOMAP |
| 2359 | + select NO_GENERIC_PCI_IOPORT_MAP | |
| 2359 | 2360 | help |
| 2360 | 2361 | Find out whether you have a PCI motherboard. PCI is the name of a |
| 2361 | 2362 | bus system, i.e. the way the CPU talks to the other stuff inside |
| @@ -137,7 +137,19 @@ extern int ptrace_set_watch_regs(struct task_struct *child, · 136 unmodified lines | ||
| 137 | 137 | */ |
| 138 | 138 | #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) |
| 139 | 139 | |
| 140 | −#define regs_return_value(_regs) ((_regs)->regs[2]) | |
| 140 | +static inline int is_syscall_success(struct pt_regs *regs) | |
| 141 | +{ | |
| 142 | + return !regs->regs[7]; | |
| 143 | +} | |
| 144 | + | |
| 145 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 146 | +{ | |
| 147 | + if (is_syscall_success(regs)) | |
| 148 | + return regs->regs[2]; | |
| 149 | + else | |
| 150 | + return -regs->regs[2]; | |
| 151 | +} | |
| 152 | + | |
| 141 | 153 | #define instruction_pointer(regs) ((regs)->cp0_epc) |
| 142 | 154 | #define profile_pc(regs) instruction_pointer(regs) |
| 143 | 155 | |
| @@ -560,10 +560,9 @@ asmlinkage void syscall_trace_enter(struct pt_regs *regs) · 559 unmodified lines | ||
| 560 | 560 | } |
| 561 | 561 | |
| 562 | 562 | out: |
| 563 | − if (unlikely(current->audit_context)) | |
| 564 | − audit_syscall_entry(audit_arch(), regs->regs[2], | |
| 565 | − regs->regs[4], regs->regs[5], | |
| 566 | − regs->regs[6], regs->regs[7]); | |
| 563 | + audit_syscall_entry(audit_arch(), regs->regs[2], | |
| 564 | + regs->regs[4], regs->regs[5], | |
| 565 | + regs->regs[6], regs->regs[7]); | |
| 567 | 566 | } |
| 568 | 567 | |
| 569 | 568 | /* |
| @@ -572,9 +571,7 @@ out: · 2 unmodified lines | ||
| 572 | 571 | */ |
| 573 | 572 | asmlinkage void syscall_trace_leave(struct pt_regs *regs) |
| 574 | 573 | { |
| 575 | − if (unlikely(current->audit_context)) | |
| 576 | − audit_syscall_exit(AUDITSC_RESULT(regs->regs[7]), | |
| 577 | − -regs->regs[2]); | |
| 574 | + audit_syscall_exit(regs); | |
| 578 | 575 | |
| 579 | 576 | if (!(current->ptrace & PT_PTRACED)) |
| 580 | 577 | return; |
| @@ -10,8 +10,8 @@ · 9 unmodified lines | ||
| 10 | 10 | #include <linux/module.h> |
| 11 | 11 | #include <asm/io.h> |
| 12 | 12 | |
| 13 | −static void __iomem *ioport_map_pci(struct pci_dev *dev, | |
| 14 | − unsigned long port, unsigned int nr) | |
| 13 | +void __iomem *__pci_ioport_map(struct pci_dev *dev, | |
| 14 | + unsigned long port, unsigned int nr) | |
| 15 | 15 | { |
| 16 | 16 | struct pci_controller *ctrl = dev->bus->sysdata; |
| 17 | 17 | unsigned long base = ctrl->io_map_base; |
| @@ -236,6 +236,10 @@ · 235 unmodified lines | ||
| 236 | 236 | }; |
| 237 | 237 | |
| 238 | 238 | /include/ "pq3-esdhc-0.dtsi" |
| 239 | + sdhc@2e000 { | |
| 240 | + compatible = "fsl,mpc8536-esdhc", "fsl,esdhc"; | |
| 241 | + }; | |
| 242 | + | |
| 239 | 243 | /include/ "pq3-sec3.0-0.dtsi" |
| 240 | 244 | /include/ "pq3-mpic.dtsi" |
| 241 | 245 | /include/ "pq3-mpic-timer-B.dtsi" |
| @@ -158,7 +158,8 @@ · 157 unmodified lines | ||
| 158 | 158 | /include/ "pq3-usb2-dr-0.dtsi" |
| 159 | 159 | /include/ "pq3-esdhc-0.dtsi" |
| 160 | 160 | sdhc@2e000 { |
| 161 | − fsl,sdhci-auto-cmd12; | |
| 161 | + compatible = "fsl,p1010-esdhc", "fsl,esdhc"; | |
| 162 | + sdhci,auto-cmd12; | |
| 162 | 163 | }; |
| 163 | 164 | |
| 164 | 165 | /include/ "pq3-sec4.4-0.dtsi" |
| @@ -145,6 +145,10 @@ · 144 unmodified lines | ||
| 145 | 145 | /include/ "pq3-usb2-dr-1.dtsi" |
| 146 | 146 | |
| 147 | 147 | /include/ "pq3-esdhc-0.dtsi" |
| 148 | + sdhc@2e000 { | |
| 149 | + compatible = "fsl,p1020-esdhc", "fsl,esdhc"; | |
| 150 | + sdhci,auto-cmd12; | |
| 151 | + }; | |
| 148 | 152 | /include/ "pq3-sec3.3-0.dtsi" |
| 149 | 153 | |
| 150 | 154 | /include/ "pq3-mpic.dtsi" |
| @@ -203,7 +203,8 @@ · 202 unmodified lines | ||
| 203 | 203 | |
| 204 | 204 | /include/ "pq3-esdhc-0.dtsi" |
| 205 | 205 | sdhc@2e000 { |
| 206 | − fsl,sdhci-auto-cmd12; | |
| 206 | + compatible = "fsl,p1022-esdhc", "fsl,esdhc"; | |
| 207 | + sdhci,auto-cmd12; | |
| 207 | 208 | }; |
| 208 | 209 | |
| 209 | 210 | /include/ "pq3-sec3.3-0.dtsi" |
| @@ -182,6 +182,10 @@ · 181 unmodified lines | ||
| 182 | 182 | /include/ "pq3-etsec1-1.dtsi" |
| 183 | 183 | /include/ "pq3-etsec1-2.dtsi" |
| 184 | 184 | /include/ "pq3-esdhc-0.dtsi" |
| 185 | + sdhc@2e000 { | |
| 186 | + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; | |
| 187 | + }; | |
| 188 | + | |
| 185 | 189 | /include/ "pq3-sec3.1-0.dtsi" |
| 186 | 190 | /include/ "pq3-mpic.dtsi" |
| 187 | 191 | /include/ "pq3-mpic-timer-B.dtsi" |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | /* |
| 2 | 2 | * P1020 RDB Device Tree Source stub (no addresses or top-level ranges) |
| 3 | 3 | * |
| 4 | − * Copyright 2011 Freescale Semiconductor Inc. | |
| 4 | + * Copyright 2011-2012 Freescale Semiconductor Inc. | |
| 5 | 5 | * |
| 6 | 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | 7 | * modification, are permitted provided that the following conditions are met: |
| @@ -190,17 +190,16 @@ · 182 unmodified lines | ||
| 190 | 190 | |
| 191 | 191 | usb@22000 { |
| 192 | 192 | phy_type = "ulpi"; |
| 193 | + dr_mode = "host"; | |
| 193 | 194 | }; |
| 194 | 195 | |
| 195 | − /* USB2 is shared with localbus, so it must be disabled | |
| 196 | − by default. We can't put 'status = "disabled";' here | |
| 197 | − since U-Boot doesn't clear the status property when | |
| 198 | − it enables USB2. OTOH, U-Boot does create a new node | |
| 199 | − when there isn't any. So, just comment it out. | |
| 196 | + /* USB2 is shared with localbus. It is used | |
| 197 | + only in case of SPI and SD boot after | |
| 198 | + appropriate device-tree fixup done by uboot */ | |
| 200 | 199 | usb@23000 { |
| 201 | 200 | phy_type = "ulpi"; |
| 201 | + dr_mode = "host"; | |
| 202 | 202 | }; |
| 203 | − */ | |
| 204 | 203 | |
| 205 | 204 | mdio@24000 { |
| 206 | 205 | phy0: ethernet-phy@0 { |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | /* |
| 2 | 2 | * P1021 MDS Device Tree Source |
| 3 | 3 | * |
| 4 | − * Copyright 2010 Freescale Semiconductor Inc. | |
| 4 | + * Copyright 2010,2012 Freescale Semiconductor Inc. | |
| 5 | 5 | * |
| 6 | 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | 7 | * under the terms of the GNU General Public License as published by the |
| @@ -151,6 +151,7 @@ · 143 unmodified lines | ||
| 151 | 151 | |
| 152 | 152 | usb@22000 { |
| 153 | 153 | phy_type = "ulpi"; |
| 154 | + dr_mode = "host"; | |
| 154 | 155 | }; |
| 155 | 156 | |
| 156 | 157 | mdio@24000 { |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | /* |
| 2 | 2 | * P2020DS Device Tree Source stub (no addresses or top-level ranges) |
| 3 | 3 | * |
| 4 | − * Copyright 2011 Freescale Semiconductor Inc. | |
| 4 | + * Copyright 2011-2012 Freescale Semiconductor Inc. | |
| 5 | 5 | * |
| 6 | 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | 7 | * modification, are permitted provided that the following conditions are met: |
| @@ -134,6 +134,7 @@ · 126 unmodified lines | ||
| 134 | 134 | &board_soc { |
| 135 | 135 | usb@22000 { |
| 136 | 136 | phy_type = "ulpi"; |
| 137 | + dr_mode = "host"; | |
| 137 | 138 | }; |
| 138 | 139 | |
| 139 | 140 | mdio@24520 { |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | /* |
| 2 | 2 | * P2020 RDB Device Tree Source |
| 3 | 3 | * |
| 4 | − * Copyright 2009-2011 Freescale Semiconductor Inc. | |
| 4 | + * Copyright 2009-2012 Freescale Semiconductor Inc. | |
| 5 | 5 | * |
| 6 | 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | 7 | * under the terms of the GNU General Public License as published by the |
| @@ -197,6 +197,7 @@ · 189 unmodified lines | ||
| 197 | 197 | |
| 198 | 198 | usb@22000 { |
| 199 | 199 | phy_type = "ulpi"; |
| 200 | + dr_mode = "host"; | |
| 200 | 201 | }; |
| 201 | 202 | |
| 202 | 203 | mdio@24520 { |
| @@ -24,10 +24,6 @@ CONFIG_PPC_SPLPAR=y · 23 unmodified lines | ||
| 24 | 24 | CONFIG_SCANLOG=m |
| 25 | 25 | CONFIG_PPC_SMLPAR=y |
| 26 | 26 | CONFIG_DTL=y |
| 27 | −CONFIG_PPC_ISERIES=y | |
| 28 | −CONFIG_VIODASD=y | |
| 29 | −CONFIG_VIOCD=m | |
| 30 | −CONFIG_VIOTAPE=m | |
| 31 | 27 | CONFIG_PPC_MAPLE=y |
| 32 | 28 | CONFIG_PPC_PASEMI=y |
| 33 | 29 | CONFIG_PPC_PASEMI_IOMMU=y |
| @@ -259,7 +255,6 @@ CONFIG_PASEMI_MAC=y · 225 unmodified lines | ||
| 259 | 255 | CONFIG_MLX4_EN=m |
| 260 | 256 | CONFIG_QLGE=m |
| 261 | 257 | CONFIG_BE2NET=m |
| 262 | −CONFIG_ISERIES_VETH=m | |
| 263 | 258 | CONFIG_PPP=m |
| 264 | 259 | CONFIG_PPP_ASYNC=m |
| 265 | 260 | CONFIG_PPP_SYNC_TTY=m |
| @@ -142,6 +142,11 @@ static inline const char *eeh_pci_name(struct pci_dev *pdev) · 141 unmodified lines | ||
| 142 | 142 | return pdev ? pci_name(pdev) : "<null>"; |
| 143 | 143 | } |
| 144 | 144 | |
| 145 | +static inline const char *eeh_driver_name(struct pci_dev *pdev) | |
| 146 | +{ | |
| 147 | + return (pdev && pdev->driver) ? pdev->driver->name : "<null>"; | |
| 148 | +} | |
| 149 | + | |
| 145 | 150 | #endif /* CONFIG_EEH */ |
| 146 | 151 | |
| 147 | 152 | #else /* CONFIG_PCI */ |
| @@ -83,17 +83,32 @@ struct pt_regs { · 82 unmodified lines | ||
| 83 | 83 | |
| 84 | 84 | #ifndef __ASSEMBLY__ |
| 85 | 85 | |
| 86 | −#define instruction_pointer(regs) ((regs)->nip) | |
| 87 | −#define user_stack_pointer(regs) ((regs)->gpr[1]) | |
| 88 | −#define kernel_stack_pointer(regs) ((regs)->gpr[1]) | |
| 89 | −#define regs_return_value(regs) ((regs)->gpr[3]) | |
| 86 | +#define GET_IP(regs) ((regs)->nip) | |
| 87 | +#define GET_USP(regs) ((regs)->gpr[1]) | |
| 88 | +#define GET_FP(regs) (0) | |
| 89 | +#define SET_FP(regs, val) | |
| 90 | 90 | |
| 91 | 91 | #ifdef CONFIG_SMP |
| 92 | 92 | extern unsigned long profile_pc(struct pt_regs *regs); |
| 93 | −#else | |
| 94 | −#define profile_pc(regs) instruction_pointer(regs) | |
| 93 | +#define profile_pc profile_pc | |
| 95 | 94 | #endif |
| 96 | 95 | |
| 96 | +#include <asm-generic/ptrace.h> | |
| 97 | + | |
| 98 | +#define kernel_stack_pointer(regs) ((regs)->gpr[1]) | |
| 99 | +static inline int is_syscall_success(struct pt_regs *regs) | |
| 100 | +{ | |
| 101 | + return !(regs->ccr & 0x10000000); | |
| 102 | +} | |
| 103 | + | |
| 104 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 105 | +{ | |
| 106 | + if (is_syscall_success(regs)) | |
| 107 | + return regs->gpr[3]; | |
| 108 | + else | |
| 109 | + return -regs->gpr[3]; | |
| 110 | +} | |
| 111 | + | |
| 97 | 112 | #ifdef __powerpc64__ |
| 98 | 113 | #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1) |
| 99 | 114 | #else |
| @@ -46,7 +46,6 @@ · 45 unmodified lines | ||
| 46 | 46 | |
| 47 | 47 | /* This keeps a track of which one is the crashing cpu. */ |
| 48 | 48 | int crashing_cpu = -1; |
| 49 | −static atomic_t cpus_in_crash; | |
| 50 | 49 | static int time_to_dump; |
| 51 | 50 | |
| 52 | 51 | #define CRASH_HANDLER_MAX 3 |
| @@ -66,6 +65,7 @@ static int handle_fault(struct pt_regs *regs) · 13 unmodified lines | ||
| 66 | 65 | |
| 67 | 66 | #ifdef CONFIG_SMP |
| 68 | 67 | |
| 68 | +static atomic_t cpus_in_crash; | |
| 69 | 69 | void crash_ipi_callback(struct pt_regs *regs) |
| 70 | 70 | { |
| 71 | 71 | static cpumask_t cpus_state_saved = CPU_MASK_NONE; |
| @@ -1213,7 +1213,7 @@ do_user_signal: /* r10 contains MSR_KERNEL here */ · 1212 unmodified lines | ||
| 1213 | 1213 | stw r3,_TRAP(r1) |
| 1214 | 1214 | 2: addi r3,r1,STACK_FRAME_OVERHEAD |
| 1215 | 1215 | mr r4,r9 |
| 1216 | − bl do_signal | |
| 1216 | + bl do_notify_resume | |
| 1217 | 1217 | REST_NVGPRS(r1) |
| 1218 | 1218 | b recheck |
| 1219 | 1219 | |
| @@ -751,12 +751,16 @@ user_work: · 750 unmodified lines | ||
| 751 | 751 | |
| 752 | 752 | andi. r0,r4,_TIF_NEED_RESCHED |
| 753 | 753 | beq 1f |
| 754 | + li r5,1 | |
| 755 | + TRACE_AND_RESTORE_IRQ(r5); | |
| 754 | 756 | bl .schedule |
| 755 | 757 | b .ret_from_except_lite |
| 756 | 758 | |
| 757 | 759 | 1: bl .save_nvgprs |
| 760 | + li r5,1 | |
| 761 | + TRACE_AND_RESTORE_IRQ(r5); | |
| 758 | 762 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 759 | − bl .do_signal | |
| 763 | + bl .do_notify_resume | |
| 760 | 764 | b .ret_from_except |
| 761 | 765 | |
| 762 | 766 | unrecov_restore: |
| @@ -774,8 +774,8 @@ alignment_common: · 773 unmodified lines | ||
| 774 | 774 | program_check_common: |
| 775 | 775 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) |
| 776 | 776 | bl .save_nvgprs |
| 777 | + DISABLE_INTS | |
| 777 | 778 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 778 | − ENABLE_INTS | |
| 779 | 779 | bl .program_check_exception |
| 780 | 780 | b .ret_from_except |
| 781 | 781 | |
| @@ -118,10 +118,14 @@ static inline notrace void set_soft_enabled(unsigned long enable) · 117 unmodified lines | ||
| 118 | 118 | static inline notrace void decrementer_check_overflow(void) |
| 119 | 119 | { |
| 120 | 120 | u64 now = get_tb_or_rtc(); |
| 121 | − u64 *next_tb = &__get_cpu_var(decrementers_next_tb); | |
| 121 | + u64 *next_tb; | |
| 122 | + | |
| 123 | + preempt_disable(); | |
| 124 | + next_tb = &__get_cpu_var(decrementers_next_tb); | |
| 122 | 125 | |
| 123 | 126 | if (now >= *next_tb) |
| 124 | 127 | set_dec(1); |
| 128 | + preempt_enable(); | |
| 125 | 129 | } |
| 126 | 130 | |
| 127 | 131 | notrace void arch_local_irq_restore(unsigned long en) |
| @@ -442,8 +442,10 @@ static void __init fixup_port_irq(int index, · 441 unmodified lines | ||
| 442 | 442 | |
| 443 | 443 | port->irq = virq; |
| 444 | 444 | |
| 445 | +#ifdef CONFIG_SERIAL_8250_FSL | |
| 445 | 446 | if (of_device_is_compatible(np, "fsl,ns16550")) |
| 446 | 447 | port->handle_irq = fsl8250_handle_irq; |
| 448 | +#endif | |
| 447 | 449 | } |
| 448 | 450 | |
| 449 | 451 | static void __init fixup_port_pio(int index, |
| @@ -865,6 +865,7 @@ static void power_pmu_start(struct perf_event *event, int ef_flags) · 864 unmodified lines | ||
| 865 | 865 | { |
| 866 | 866 | unsigned long flags; |
| 867 | 867 | s64 left; |
| 868 | + unsigned long val; | |
| 868 | 869 | |
| 869 | 870 | if (!event->hw.idx || !event->hw.sample_period) |
| 870 | 871 | return; |
| @@ -880,7 +881,12 @@ static void power_pmu_start(struct perf_event *event, int ef_flags) · 9 unmodified lines | ||
| 880 | 881 | |
| 881 | 882 | event->hw.state = 0; |
| 882 | 883 | left = local64_read(&event->hw.period_left); |
| 883 | − write_pmc(event->hw.idx, left); | |
| 884 | + | |
| 885 | + val = 0; | |
| 886 | + if (left < 0x80000000L) | |
| 887 | + val = 0x80000000L - left; | |
| 888 | + | |
| 889 | + write_pmc(event->hw.idx, val); | |
| 884 | 890 | |
| 885 | 891 | perf_event_update_userpage(event); |
| 886 | 892 | perf_pmu_enable(event->pmu); |
| @@ -566,12 +566,12 @@ static void show_instructions(struct pt_regs *regs) · 565 unmodified lines | ||
| 566 | 566 | */ |
| 567 | 567 | if (!__kernel_text_address(pc) || |
| 568 | 568 | __get_user(instr, (unsigned int __user *)pc)) { |
| 569 | − printk("XXXXXXXX "); | |
| 569 | + printk(KERN_CONT "XXXXXXXX "); | |
| 570 | 570 | } else { |
| 571 | 571 | if (regs->nip == pc) |
| 572 | − printk("<%08x> ", instr); | |
| 572 | + printk(KERN_CONT "<%08x> ", instr); | |
| 573 | 573 | else |
| 574 | − printk("%08x ", instr); | |
| 574 | + printk(KERN_CONT "%08x ", instr); | |
| 575 | 575 | } |
| 576 | 576 | |
| 577 | 577 | pc += sizeof(int); |
| @@ -1724,22 +1724,20 @@ long do_syscall_trace_enter(struct pt_regs *regs) · 1723 unmodified lines | ||
| 1724 | 1724 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 1725 | 1725 | trace_sys_enter(regs, regs->gpr[0]); |
| 1726 | 1726 | |
| 1727 | − if (unlikely(current->audit_context)) { | |
| 1728 | 1727 | #ifdef CONFIG_PPC64 |
| 1729 | − if (!is_32bit_task()) | |
| 1730 | − audit_syscall_entry(AUDIT_ARCH_PPC64, | |
| 1731 | − regs->gpr[0], | |
| 1732 | − regs->gpr[3], regs->gpr[4], | |
| 1733 | − regs->gpr[5], regs->gpr[6]); | |
| 1734 | − else | |
| 1728 | + if (!is_32bit_task()) | |
| 1729 | + audit_syscall_entry(AUDIT_ARCH_PPC64, | |
| 1730 | + regs->gpr[0], | |
| 1731 | + regs->gpr[3], regs->gpr[4], | |
| 1732 | + regs->gpr[5], regs->gpr[6]); | |
| 1733 | + else | |
| 1735 | 1734 | #endif |
| 1736 | − audit_syscall_entry(AUDIT_ARCH_PPC, | |
| 1737 | − regs->gpr[0], | |
| 1738 | − regs->gpr[3] & 0xffffffff, | |
| 1739 | − regs->gpr[4] & 0xffffffff, | |
| 1740 | − regs->gpr[5] & 0xffffffff, | |
| 1741 | − regs->gpr[6] & 0xffffffff); | |
| 1742 | − } | |
| 1735 | + audit_syscall_entry(AUDIT_ARCH_PPC, | |
| 1736 | + regs->gpr[0], | |
| 1737 | + regs->gpr[3] & 0xffffffff, | |
| 1738 | + regs->gpr[4] & 0xffffffff, | |
| 1739 | + regs->gpr[5] & 0xffffffff, | |
| 1740 | + regs->gpr[6] & 0xffffffff); | |
| 1743 | 1741 | |
| 1744 | 1742 | return ret ?: regs->gpr[0]; |
| 1745 | 1743 | } |
| @@ -1748,9 +1746,7 @@ void do_syscall_trace_leave(struct pt_regs *regs) · 2 unmodified lines | ||
| 1748 | 1746 | { |
| 1749 | 1747 | int step; |
| 1750 | 1748 | |
| 1751 | − if (unlikely(current->audit_context)) | |
| 1752 | − audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS, | |
| 1753 | − regs->result); | |
| 1749 | + audit_syscall_exit(regs); | |
| 1754 | 1750 | |
| 1755 | 1751 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 1756 | 1752 | trace_sys_exit(regs, regs->result); |
| @@ -716,7 +716,6 @@ static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_w · 715 unmodified lines | ||
| 716 | 716 | int cpu; |
| 717 | 717 | |
| 718 | 718 | slb_set_size(SLB_MIN_SIZE); |
| 719 | − stop_topology_update(); | |
| 720 | 719 | printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n", smp_processor_id()); |
| 721 | 720 | |
| 722 | 721 | while (rc == H_MULTI_THREADS_ACTIVE && !atomic_read(&data->done) && |
| @@ -732,7 +731,6 @@ static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_w · 9 unmodified lines | ||
| 732 | 731 | rc = atomic_read(&data->error); |
| 733 | 732 | |
| 734 | 733 | atomic_set(&data->error, rc); |
| 735 | − start_topology_update(); | |
| 736 | 734 | pSeries_coalesce_init(); |
| 737 | 735 | |
| 738 | 736 | if (wake_when_done) { |
| @@ -846,6 +844,7 @@ int rtas_ibm_suspend_me(struct rtas_args *args) · 107 unmodified lines | ||
| 846 | 844 | atomic_set(&data.error, 0); |
| 847 | 845 | data.token = rtas_token("ibm,suspend-me"); |
| 848 | 846 | data.complete = &done; |
| 847 | + stop_topology_update(); | |
| 849 | 848 | |
| 850 | 849 | /* Call function on all CPUs. One of us will make the |
| 851 | 850 | * rtas call |
| @@ -858,6 +857,8 @@ int rtas_ibm_suspend_me(struct rtas_args *args) · 6 unmodified lines | ||
| 858 | 857 | if (atomic_read(&data.error) != 0) |
| 859 | 858 | printk(KERN_ERR "Error doing global join\n"); |
| 860 | 859 | |
| 860 | + start_topology_update(); | |
| 861 | + | |
| 861 | 862 | return atomic_read(&data.error); |
| 862 | 863 | } |
| 863 | 864 | #else /* CONFIG_PPC_PSERIES */ |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | ||
| 11 | 11 | |
| 12 | 12 | #include <linux/tracehook.h> |
| 13 | 13 | #include <linux/signal.h> |
| 14 | +#include <linux/key.h> | |
| 14 | 15 | #include <asm/hw_breakpoint.h> |
| 15 | 16 | #include <asm/uaccess.h> |
| 16 | 17 | #include <asm/unistd.h> |
| @@ -113,8 +114,9 @@ static void check_syscall_restart(struct pt_regs *regs, struct k_sigaction *ka, · 96 unmodified lines | ||
| 113 | 114 | } |
| 114 | 115 | } |
| 115 | 116 | |
| 116 | −static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs) | |
| 117 | +static int do_signal(struct pt_regs *regs) | |
| 117 | 118 | { |
| 119 | + sigset_t *oldset; | |
| 118 | 120 | siginfo_t info; |
| 119 | 121 | int signr; |
| 120 | 122 | struct k_sigaction ka; |
| @@ -123,7 +125,7 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs) · 2 unmodified lines | ||
| 123 | 125 | |
| 124 | 126 | if (current_thread_info()->local_flags & _TLF_RESTORE_SIGMASK) |
| 125 | 127 | oldset = ¤t->saved_sigmask; |
| 126 | − else if (!oldset) | |
| 128 | + else | |
| 127 | 129 | oldset = ¤t->blocked; |
| 128 | 130 | |
| 129 | 131 | signr = get_signal_to_deliver(&info, &ka, regs, NULL); |
| @@ -191,14 +193,16 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs) · 61 unmodified lines | ||
| 191 | 193 | return ret; |
| 192 | 194 | } |
| 193 | 195 | |
| 194 | −void do_signal(struct pt_regs *regs, unsigned long thread_info_flags) | |
| 196 | +void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags) | |
| 195 | 197 | { |
| 196 | 198 | if (thread_info_flags & _TIF_SIGPENDING) |
| 197 | − do_signal_pending(NULL, regs); | |
| 199 | + do_signal(regs); | |
| 198 | 200 | |
| 199 | 201 | if (thread_info_flags & _TIF_NOTIFY_RESUME) { |
| 200 | 202 | clear_thread_flag(TIF_NOTIFY_RESUME); |
| 201 | 203 | tracehook_notify_resume(regs); |
| 204 | + if (current->replacement_session_keyring) | |
| 205 | + key_replace_session_keyring(); | |
| 202 | 206 | } |
| 203 | 207 | } |
| 204 | 208 | |
| @@ -12,7 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | |
| 13 | 13 | #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) |
| 14 | 14 | |
| 15 | −extern void do_signal(struct pt_regs *regs, unsigned long thread_info_flags); | |
| 15 | +extern void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags); | |
| 16 | 16 | |
| 17 | 17 | extern void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, |
| 18 | 18 | size_t frame_size, int is_32); |
| @@ -25,6 +25,7 @@ · 24 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | #include <sysdev/fsl_soc.h> |
| 27 | 27 | #include <sysdev/fsl_pci.h> |
| 28 | +#include <asm/udbg.h> | |
| 28 | 29 | #include <asm/fsl_guts.h> |
| 29 | 30 | #include "smp.h" |
| 30 | 31 | |
| @@ -204,11 +204,10 @@ static void __devinit pnv_ioda_offset_bus(struct pci_bus *bus, · 203 unmodified lines | ||
| 204 | 204 | pr_devel(" -> OBR %s [%x] +%016llx\n", |
| 205 | 205 | bus->self ? pci_name(bus->self) : "root", flags, offset); |
| 206 | 206 | |
| 207 | − for (i = 0; i < 2; i++) { | |
| 208 | − r = bus->resource[i]; | |
| 207 | + pci_bus_for_each_resource(bus, r, i) { | |
| 209 | 208 | if (r && (r->flags & flags)) { |
| 210 | − bus->resource[i]->start += offset; | |
| 211 | − bus->resource[i]->end += offset; | |
| 209 | + r->start += offset; | |
| 210 | + r->end += offset; | |
| 212 | 211 | } |
| 213 | 212 | } |
| 214 | 213 | list_for_each_entry(dev, &bus->devices, bus_list) |
| @@ -288,12 +287,17 @@ static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags, · 73 unmodified lines | ||
| 288 | 287 | * assignment algorithm is going to be uber-trivial for now, we |
| 289 | 288 | * can try to be smarter later at filling out holes. |
| 290 | 289 | */ |
| 291 | − start = bus->self ? 0 : bus->resource[bres]->start; | |
| 292 | − | |
| 293 | − /* Don't hand out IO 0 */ | |
| 294 | − if ((flags & IORESOURCE_IO) && !bus->self) | |
| 295 | − start += 0x1000; | |
| 296 | − | |
| 290 | + if (bus->self) { | |
| 291 | + /* No offset for downstream bridges */ | |
| 292 | + start = 0; | |
| 293 | + } else { | |
| 294 | + /* Offset from the root */ | |
| 295 | + if (flags & IORESOURCE_IO) | |
| 296 | + /* Don't hand out IO 0 */ | |
| 297 | + start = hose->io_resource.start + 0x1000; | |
| 298 | + else | |
| 299 | + start = hose->mem_resources[0].start; | |
| 300 | + } | |
| 297 | 301 | while(!list_empty(&head)) { |
| 298 | 302 | w = list_first_entry(&head, struct resource_wrap, link); |
| 299 | 303 | list_del(&w->link); |
| @@ -321,13 +325,20 @@ static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags, · 21 unmodified lines | ||
| 321 | 325 | empty: |
| 322 | 326 | /* Only setup P2P's, not the PHB itself */ |
| 323 | 327 | if (bus->self) { |
| 324 | − WARN_ON(bus->resource[bres] == NULL); | |
| 325 | − bus->resource[bres]->start = 0; | |
| 326 | − bus->resource[bres]->flags = (*size) ? flags : 0; | |
| 327 | − bus->resource[bres]->end = (*size) ? (*size - 1) : 0; | |
| 328 | + struct resource *res = bus->resource[bres]; | |
| 329 | + | |
| 330 | + if (WARN_ON(res == NULL)) | |
| 331 | + return; | |
| 328 | 332 | |
| 329 | − /* Clear prefetch bus resources for now */ | |
| 330 | − bus->resource[2]->flags = 0; | |
| 333 | + /* | |
| 334 | + * FIXME: We should probably export and call | |
| 335 | + * pci_bridge_check_ranges() to properly re-initialize | |
| 336 | + * the PCI portion of the flags here, and to detect | |
| 337 | + * what the bridge actually supports. | |
| 338 | + */ | |
| 339 | + res->start = 0; | |
| 340 | + res->flags = (*size) ? flags : 0; | |
| 341 | + res->end = (*size) ? (*size - 1) : 0; | |
| 331 | 342 | } |
| 332 | 343 | |
| 333 | 344 | pr_devel("<- CBR %s [%x] *size=%016llx *align=%016llx\n", |
| @@ -52,32 +52,38 @@ static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type) · 51 unmodified lines | ||
| 52 | 52 | |
| 53 | 53 | static unsigned int pnv_get_one_msi(struct pnv_phb *phb) |
| 54 | 54 | { |
| 55 | − unsigned int id; | |
| 55 | + unsigned long flags; | |
| 56 | + unsigned int id, rc; | |
| 57 | + | |
| 58 | + spin_lock_irqsave(&phb->lock, flags); | |
| 56 | 59 | |
| 57 | − spin_lock(&phb->lock); | |
| 58 | 60 | id = find_next_zero_bit(phb->msi_map, phb->msi_count, phb->msi_next); |
| 59 | 61 | if (id >= phb->msi_count && phb->msi_next) |
| 60 | 62 | id = find_next_zero_bit(phb->msi_map, phb->msi_count, 0); |
| 61 | 63 | if (id >= phb->msi_count) { |
| 62 | − spin_unlock(&phb->lock); | |
| 63 | − return 0; | |
| 64 | + rc = 0; | |
| 65 | + goto out; | |
| 64 | 66 | } |
| 65 | 67 | __set_bit(id, phb->msi_map); |
| 66 | − spin_unlock(&phb->lock); | |
| 67 | − return id + phb->msi_base; | |
| 68 | + rc = id + phb->msi_base; | |
| 69 | +out: | |
| 70 | + spin_unlock_irqrestore(&phb->lock, flags); | |
| 71 | + return rc; | |
| 68 | 72 | } |
| 69 | 73 | |
| 70 | 74 | static void pnv_put_msi(struct pnv_phb *phb, unsigned int hwirq) |
| 71 | 75 | { |
| 76 | + unsigned long flags; | |
| 72 | 77 | unsigned int id; |
| 73 | 78 | |
| 74 | 79 | if (WARN_ON(hwirq < phb->msi_base || |
| 75 | 80 | hwirq >= (phb->msi_base + phb->msi_count))) |
| 76 | 81 | return; |
| 77 | 82 | id = hwirq - phb->msi_base; |
| 78 | − spin_lock(&phb->lock); | |
| 83 | + | |
| 84 | + spin_lock_irqsave(&phb->lock, flags); | |
| 79 | 85 | __clear_bit(id, phb->msi_map); |
| 80 | − spin_unlock(&phb->lock); | |
| 86 | + spin_unlock_irqrestore(&phb->lock, flags); | |
| 81 | 87 | } |
| 82 | 88 | |
| 83 | 89 | static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) |
| @@ -122,7 +122,7 @@ config DTL · 121 unmodified lines | ||
| 122 | 122 | Say N if you are unsure. |
| 123 | 123 | |
| 124 | 124 | config PSERIES_IDLE |
| 125 | − tristate "Cpuidle driver for pSeries platforms" | |
| 125 | + bool "Cpuidle driver for pSeries platforms" | |
| 126 | 126 | depends on CPU_IDLE |
| 127 | 127 | depends on PPC_PSERIES |
| 128 | 128 | default y |
| @@ -551,9 +551,9 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) · 550 unmodified lines | ||
| 551 | 551 | printk (KERN_ERR "EEH: %d reads ignored for recovering device at " |
| 552 | 552 | "location=%s driver=%s pci addr=%s\n", |
| 553 | 553 | pdn->eeh_check_count, location, |
| 554 | − dev->driver->name, eeh_pci_name(dev)); | |
| 554 | + eeh_driver_name(dev), eeh_pci_name(dev)); | |
| 555 | 555 | printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
| 556 | − dev->driver->name); | |
| 556 | + eeh_driver_name(dev)); | |
| 557 | 557 | dump_stack(); |
| 558 | 558 | } |
| 559 | 559 | goto dn_unlock; |
| @@ -24,6 +24,7 @@ · 23 unmodified lines | ||
| 24 | 24 | #include <asm/machdep.h> |
| 25 | 25 | #include <asm/mmu.h> |
| 26 | 26 | #include <asm/rtas.h> |
| 27 | +#include <asm/topology.h> | |
| 27 | 28 | |
| 28 | 29 | static u64 stream_id; |
| 29 | 30 | static struct device suspend_dev; |
| @@ -138,8 +139,11 @@ static ssize_t store_hibernate(struct device *dev, · 108 unmodified lines | ||
| 138 | 139 | ssleep(1); |
| 139 | 140 | } while (rc == -EAGAIN); |
| 140 | 141 | |
| 141 | − if (!rc) | |
| 142 | + if (!rc) { | |
| 143 | + stop_topology_update(); | |
| 142 | 144 | rc = pm_suspend(PM_SUSPEND_MEM); |
| 145 | + start_topology_update(); | |
| 146 | + } | |
| 143 | 147 | |
| 144 | 148 | stream_id = 0; |
| 145 | 149 | |
| @@ -346,7 +346,7 @@ static int wsp_chip_set_affinity(struct irq_data *d, · 345 unmodified lines | ||
| 346 | 346 | * For the moment only implement delivery to all cpus or one cpu. |
| 347 | 347 | * Get current irq_server for the given irq |
| 348 | 348 | */ |
| 349 | − ret = cache_hwirq_map(ics, d->irq, cpumask); | |
| 349 | + ret = cache_hwirq_map(ics, hw_irq, cpumask); | |
| 350 | 350 | if (ret == -1) { |
| 351 | 351 | char cpulist[128]; |
| 352 | 352 | cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask); |
| @@ -71,7 +71,7 @@ int __devinit smp_a2_kick_cpu(int nr) · 70 unmodified lines | ||
| 71 | 71 | |
| 72 | 72 | static int __init smp_a2_probe(void) |
| 73 | 73 | { |
| 74 | − return cpus_weight(cpu_possible_map); | |
| 74 | + return num_possible_cpus(); | |
| 75 | 75 | } |
| 76 | 76 | |
| 77 | 77 | static struct smp_ops_t a2_smp_ops = { |
| @@ -468,15 +468,15 @@ static void __init wsp_pcie_configure_hw(struct pci_controller *hose) · 467 unmodified lines | ||
| 468 | 468 | #define DUMP_REG(x) \ |
| 469 | 469 | pr_debug("%-30s : 0x%016llx\n", #x, in_be64(hose->cfg_data + x)) |
| 470 | 470 | |
| 471 | −#ifdef CONFIG_WSP_DD1_WORKAROUND_BAD_PCIE_CLASS | |
| 472 | − /* WSP DD1 has a bogus class code by default in the PCI-E | |
| 473 | − * root complex's built-in P2P bridge */ | |
| 471 | + /* | |
| 472 | + * Some WSP variants has a bogus class code by default in the PCI-E | |
| 473 | + * root complex's built-in P2P bridge | |
| 474 | + */ | |
| 474 | 475 | val = in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1); |
| 475 | 476 | pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", val); |
| 476 | 477 | out_be64(hose->cfg_data + PCIE_REG_SYS_CFG1, |
| 477 | 478 | (val & ~PCIE_REG_SYS_CFG1_CLASS_CODE) | (PCI_CLASS_BRIDGE_PCI << 8)); |
| 478 | 479 | pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1)); |
| 479 | −#endif /* CONFIG_WSP_DD1_WORKAROUND_BAD_PCIE_CLASS */ | |
| 480 | 480 | |
| 481 | 481 | #ifdef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS |
| 482 | 482 | /* XXX Disable TCE caching, it doesn't work on DD1 */ |
| @@ -205,12 +205,12 @@ static void __init setup_pci_atmu(struct pci_controller *hose, · 204 unmodified lines | ||
| 205 | 205 | |
| 206 | 206 | if (paddr_hi == paddr_lo) { |
| 207 | 207 | pr_err("%s: No outbound window space\n", name); |
| 208 | − return ; | |
| 208 | + goto out; | |
| 209 | 209 | } |
| 210 | 210 | |
| 211 | 211 | if (paddr_lo == 0) { |
| 212 | 212 | pr_err("%s: No space for inbound window\n", name); |
| 213 | − return ; | |
| 213 | + goto out; | |
| 214 | 214 | } |
| 215 | 215 | |
| 216 | 216 | /* setup PCSRBAR/PEXCSRBAR */ |
| @@ -357,6 +357,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose, · 140 unmodified lines | ||
| 357 | 357 | (u64)hose->dma_window_size); |
| 358 | 358 | } |
| 359 | 359 | |
| 360 | +out: | |
| 360 | 361 | iounmap(pci); |
| 361 | 362 | } |
| 362 | 363 | |
| @@ -384,26 +385,36 @@ static void __init setup_pci_cmd(struct pci_controller *hose) · 21 unmodified lines | ||
| 384 | 385 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) |
| 385 | 386 | { |
| 386 | 387 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 387 | − int i; | |
| 388 | − | |
| 389 | − if ((bus->parent == hose->bus) && | |
| 390 | − ((fsl_pcie_bus_fixup && | |
| 391 | − early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) || | |
| 392 | − (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK))) | |
| 393 | − { | |
| 394 | − for (i = 0; i < 4; ++i) { | |
| 388 | + int i, is_pcie = 0, no_link; | |
| 389 | + | |
| 390 | + /* The root complex bridge comes up with bogus resources, | |
| 391 | + * we copy the PHB ones in. | |
| 392 | + * | |
| 393 | + * With the current generic PCI code, the PHB bus no longer | |
| 394 | + * has bus->resource[0..4] set, so things are a bit more | |
| 395 | + * tricky. | |
| 396 | + */ | |
| 397 | + | |
| 398 | + if (fsl_pcie_bus_fixup) | |
| 399 | + is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); | |
| 400 | + no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); | |
| 401 | + | |
| 402 | + if (bus->parent == hose->bus && (is_pcie || no_link)) { | |
| 403 | + for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { | |
| 395 | 404 | struct resource *res = bus->resource[i]; |
| 396 | − struct resource *par = bus->parent->resource[i]; | |
| 397 | − if (res) { | |
| 398 | − res->start = 0; | |
| 399 | − res->end = 0; | |
| 400 | − res->flags = 0; | |
| 401 | − } | |
| 402 | − if (res && par) { | |
| 403 | − res->start = par->start; | |
| 404 | − res->end = par->end; | |
| 405 | − res->flags = par->flags; | |
| 406 | − } | |
| 405 | + struct resource *par; | |
| 406 | + | |
| 407 | + if (!res) | |
| 408 | + continue; | |
| 409 | + if (i == 0) | |
| 410 | + par = &hose->io_resource; | |
| 411 | + else if (i < 4) | |
| 412 | + par = &hose->mem_resources[i-1]; | |
| 413 | + else par = NULL; | |
| 414 | + | |
| 415 | + res->start = par ? par->start : 0; | |
| 416 | + res->end = par ? par->end : 0; | |
| 417 | + res->flags = par ? par->flags : 0; | |
| 407 | 418 | } |
| 408 | 419 | } |
| 409 | 420 | } |
| @@ -88,7 +88,6 @@ KBUILD_CFLAGS += -pipe -fno-strength-reduce -Wno-sign-compare · 87 unmodified lines | ||
| 88 | 88 | KBUILD_AFLAGS += $(aflags-y) |
| 89 | 89 | |
| 90 | 90 | OBJCOPYFLAGS := -O binary |
| 91 | −LDFLAGS_vmlinux := -e start | |
| 92 | 91 | |
| 93 | 92 | head-y := arch/s390/kernel/head.o |
| 94 | 93 | head-y += arch/s390/kernel/$(if $(CONFIG_64BIT),head64.o,head31.o) |
| @@ -42,6 +42,24 @@ · 41 unmodified lines | ||
| 42 | 42 | /* The native architecture */ |
| 43 | 43 | #define KEXEC_ARCH KEXEC_ARCH_S390 |
| 44 | 44 | |
| 45 | +/* | |
| 46 | + * Size for s390x ELF notes per CPU | |
| 47 | + * | |
| 48 | + * Seven notes plus zero note at the end: prstatus, fpregset, timer, | |
| 49 | + * tod_cmp, tod_reg, control regs, and prefix | |
| 50 | + */ | |
| 51 | +#define KEXEC_NOTE_BYTES \ | |
| 52 | + (ALIGN(sizeof(struct elf_note), 4) * 8 + \ | |
| 53 | + ALIGN(sizeof("CORE"), 4) * 7 + \ | |
| 54 | + ALIGN(sizeof(struct elf_prstatus), 4) + \ | |
| 55 | + ALIGN(sizeof(elf_fpregset_t), 4) + \ | |
| 56 | + ALIGN(sizeof(u64), 4) + \ | |
| 57 | + ALIGN(sizeof(u64), 4) + \ | |
| 58 | + ALIGN(sizeof(u32), 4) + \ | |
| 59 | + ALIGN(sizeof(u64) * 16, 4) + \ | |
| 60 | + ALIGN(sizeof(u32), 4) \ | |
| 61 | + ) | |
| 62 | + | |
| 45 | 63 | /* Provide a dummy definition to avoid build failures. */ |
| 46 | 64 | static inline void crash_setup_regs(struct pt_regs *newregs, |
| 47 | 65 | struct pt_regs *oldregs) { } |
| @@ -541,9 +541,13 @@ struct user_regs_struct · 540 unmodified lines | ||
| 541 | 541 | #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0) |
| 542 | 542 | #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN) |
| 543 | 543 | #define user_stack_pointer(regs)((regs)->gprs[15]) |
| 544 | −#define regs_return_value(regs)((regs)->gprs[2]) | |
| 545 | 544 | #define profile_pc(regs) instruction_pointer(regs) |
| 546 | 545 | |
| 546 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 547 | +{ | |
| 548 | + return regs->gprs[2]; | |
| 549 | +} | |
| 550 | + | |
| 547 | 551 | int regs_query_register_offset(const char *name); |
| 548 | 552 | const char *regs_query_register_name(unsigned int offset); |
| 549 | 553 | unsigned long regs_get_register(struct pt_regs *regs, unsigned int offset); |
| @@ -662,7 +662,7 @@ ENTRY(sys32_getresuid16_wrapper) · 661 unmodified lines | ||
| 662 | 662 | ENTRY(sys32_poll_wrapper) |
| 663 | 663 | llgtr %r2,%r2 # struct pollfd * |
| 664 | 664 | llgfr %r3,%r3 # unsigned int |
| 665 | − lgfr %r4,%r4 # long | |
| 665 | + lgfr %r4,%r4 # int | |
| 666 | 666 | jg sys_poll # branch to system call |
| 667 | 667 | |
| 668 | 668 | ENTRY(sys32_setresgid16_wrapper) |
| @@ -76,7 +76,6 @@ static void default_idle(void) · 75 unmodified lines | ||
| 76 | 76 | if (test_thread_flag(TIF_MCCK_PENDING)) { |
| 77 | 77 | local_mcck_enable(); |
| 78 | 78 | local_irq_enable(); |
| 79 | − s390_handle_mcck(); | |
| 80 | 79 | return; |
| 81 | 80 | } |
| 82 | 81 | trace_hardirqs_on(); |
| @@ -93,10 +92,12 @@ void cpu_idle(void) · 10 unmodified lines | ||
| 93 | 92 | for (;;) { |
| 94 | 93 | tick_nohz_idle_enter(); |
| 95 | 94 | rcu_idle_enter(); |
| 96 | − while (!need_resched()) | |
| 95 | + while (!need_resched() && !test_thread_flag(TIF_MCCK_PENDING)) | |
| 97 | 96 | default_idle(); |
| 98 | 97 | rcu_idle_exit(); |
| 99 | 98 | tick_nohz_idle_exit(); |
| 99 | + if (test_thread_flag(TIF_MCCK_PENDING)) | |
| 100 | + s390_handle_mcck(); | |
| 100 | 101 | preempt_enable_no_resched(); |
| 101 | 102 | schedule(); |
| 102 | 103 | preempt_disable(); |
| @@ -740,20 +740,17 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) · 739 unmodified lines | ||
| 740 | 740 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 741 | 741 | trace_sys_enter(regs, regs->gprs[2]); |
| 742 | 742 | |
| 743 | − if (unlikely(current->audit_context)) | |
| 744 | − audit_syscall_entry(is_compat_task() ? | |
| 745 | − AUDIT_ARCH_S390 : AUDIT_ARCH_S390X, | |
| 746 | − regs->gprs[2], regs->orig_gpr2, | |
| 747 | − regs->gprs[3], regs->gprs[4], | |
| 748 | − regs->gprs[5]); | |
| 743 | + audit_syscall_entry(is_compat_task() ? | |
| 744 | + AUDIT_ARCH_S390 : AUDIT_ARCH_S390X, | |
| 745 | + regs->gprs[2], regs->orig_gpr2, | |
| 746 | + regs->gprs[3], regs->gprs[4], | |
| 747 | + regs->gprs[5]); | |
| 749 | 748 | return ret ?: regs->gprs[2]; |
| 750 | 749 | } |
| 751 | 750 | |
| 752 | 751 | asmlinkage void do_syscall_trace_exit(struct pt_regs *regs) |
| 753 | 752 | { |
| 754 | − if (unlikely(current->audit_context)) | |
| 755 | − audit_syscall_exit(AUDITSC_RESULT(regs->gprs[2]), | |
| 756 | − regs->gprs[2]); | |
| 753 | + audit_syscall_exit(regs); | |
| 757 | 754 | |
| 758 | 755 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 759 | 756 | trace_sys_exit(regs, regs->gprs[2]); |
| @@ -113,11 +113,14 @@ static void fixup_clock_comparator(unsigned long long delta) · 112 unmodified lines | ||
| 113 | 113 | static int s390_next_ktime(ktime_t expires, |
| 114 | 114 | struct clock_event_device *evt) |
| 115 | 115 | { |
| 116 | + struct timespec ts; | |
| 116 | 117 | u64 nsecs; |
| 117 | 118 | |
| 118 | − nsecs = ktime_to_ns(ktime_sub(expires, ktime_get_monotonic_offset())); | |
| 119 | + ts.tv_sec = ts.tv_nsec = 0; | |
| 120 | + monotonic_to_bootbased(&ts); | |
| 121 | + nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires)); | |
| 119 | 122 | do_div(nsecs, 125); |
| 120 | − S390_lowcore.clock_comparator = TOD_UNIX_EPOCH + (nsecs << 9); | |
| 123 | + S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9); | |
| 121 | 124 | set_clock_comparator(S390_lowcore.clock_comparator); |
| 122 | 125 | return 0; |
| 123 | 126 | } |
| @@ -9,12 +9,12 @@ · 8 unmodified lines | ||
| 9 | 9 | #ifndef CONFIG_64BIT |
| 10 | 10 | OUTPUT_FORMAT("elf32-s390", "elf32-s390", "elf32-s390") |
| 11 | 11 | OUTPUT_ARCH(s390) |
| 12 | −ENTRY(_start) | |
| 12 | +ENTRY(startup) | |
| 13 | 13 | jiffies = jiffies_64 + 4; |
| 14 | 14 | #else |
| 15 | 15 | OUTPUT_FORMAT("elf64-s390", "elf64-s390", "elf64-s390") |
| 16 | 16 | OUTPUT_ARCH(s390:64-bit) |
| 17 | −ENTRY(_start) | |
| 17 | +ENTRY(startup) | |
| 18 | 18 | jiffies = jiffies_64; |
| 19 | 19 | #endif |
| 20 | 20 | |
| @@ -574,7 +574,7 @@ static inline void page_table_free_pgste(unsigned long *table) · 573 unmodified lines | ||
| 574 | 574 | page = pfn_to_page(__pa(table) >> PAGE_SHIFT); |
| 575 | 575 | mp = (struct gmap_pgtable *) page->index; |
| 576 | 576 | BUG_ON(!list_empty(&mp->mapper)); |
| 577 | − pgtable_page_ctor(page); | |
| 577 | + pgtable_page_dtor(page); | |
| 578 | 578 | atomic_set(&page->_mapcount, -1); |
| 579 | 579 | kfree(mp); |
| 580 | 580 | __free_page(page); |
| @@ -408,7 +408,7 @@ ENTRY(handle_sys) · 407 unmodified lines | ||
| 408 | 408 | sw r9, [r0, PT_EPC] |
| 409 | 409 | |
| 410 | 410 | cmpi.c r27, __NR_syscalls # check syscall number |
| 411 | − bgtu illegal_syscall | |
| 411 | + bgeu illegal_syscall | |
| 412 | 412 | |
| 413 | 413 | slli r8, r27, 2 # get syscall routine |
| 414 | 414 | la r11, sys_call_table |
| @@ -859,6 +859,7 @@ config PCI · 858 unmodified lines | ||
| 859 | 859 | depends on SYS_SUPPORTS_PCI |
| 860 | 860 | select PCI_DOMAINS |
| 861 | 861 | select GENERIC_PCI_IOMAP |
| 862 | + select NO_GENERIC_PCI_IOPORT_MAP | |
| 862 | 863 | help |
| 863 | 864 | Find out whether you have a PCI motherboard. PCI is the name of a |
| 864 | 865 | bus system, i.e. the way the CPU talks to the other stuff inside |
| @@ -356,8 +356,8 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, · 355 unmodified lines | ||
| 356 | 356 | |
| 357 | 357 | #ifndef CONFIG_GENERIC_IOMAP |
| 358 | 358 | |
| 359 | −static void __iomem *ioport_map_pci(struct pci_dev *dev, | |
| 360 | − unsigned long port, unsigned int nr) | |
| 359 | +void __iomem *__pci_ioport_map(struct pci_dev *dev, | |
| 360 | + unsigned long port, unsigned int nr) | |
| 361 | 361 | { |
| 362 | 362 | struct pci_channel *chan = dev->sysdata; |
| 363 | 363 | |
| @@ -76,7 +76,10 @@ struct pt_dspregs { · 75 unmodified lines | ||
| 76 | 76 | #ifdef __KERNEL__ |
| 77 | 77 | |
| 78 | 78 | #define MAX_REG_OFFSET offsetof(struct pt_regs, tra) |
| 79 | −#define regs_return_value(_regs) ((_regs)->regs[0]) | |
| 79 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 80 | +{ | |
| 81 | + return regs->regs[0]; | |
| 82 | +} | |
| 80 | 83 | |
| 81 | 84 | #endif /* __KERNEL__ */ |
| 82 | 85 | |
| @@ -13,7 +13,10 @@ struct pt_regs { · 12 unmodified lines | ||
| 13 | 13 | #ifdef __KERNEL__ |
| 14 | 14 | |
| 15 | 15 | #define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7]) |
| 16 | −#define regs_return_value(_regs) ((_regs)->regs[3]) | |
| 16 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 17 | +{ | |
| 18 | + return regs->regs[3]; | |
| 19 | +} | |
| 17 | 20 | |
| 18 | 21 | #endif /* __KERNEL__ */ |
| 19 | 22 | |
| @@ -518,10 +518,9 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) · 517 unmodified lines | ||
| 518 | 518 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 519 | 519 | trace_sys_enter(regs, regs->regs[0]); |
| 520 | 520 | |
| 521 | − if (unlikely(current->audit_context)) | |
| 522 | − audit_syscall_entry(audit_arch(), regs->regs[3], | |
| 523 | − regs->regs[4], regs->regs[5], | |
| 524 | − regs->regs[6], regs->regs[7]); | |
| 521 | + audit_syscall_entry(audit_arch(), regs->regs[3], | |
| 522 | + regs->regs[4], regs->regs[5], | |
| 523 | + regs->regs[6], regs->regs[7]); | |
| 525 | 524 | |
| 526 | 525 | return ret ?: regs->regs[0]; |
| 527 | 526 | } |
| @@ -530,9 +529,7 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) · 2 unmodified lines | ||
| 530 | 529 | { |
| 531 | 530 | int step; |
| 532 | 531 | |
| 533 | − if (unlikely(current->audit_context)) | |
| 534 | − audit_syscall_exit(AUDITSC_RESULT(regs->regs[0]), | |
| 535 | − regs->regs[0]); | |
| 532 | + audit_syscall_exit(regs); | |
| 536 | 533 | |
| 537 | 534 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 538 | 535 | trace_sys_exit(regs, regs->regs[0]); |
| @@ -536,10 +536,9 @@ asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs) · 535 unmodified lines | ||
| 536 | 536 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 537 | 537 | trace_sys_enter(regs, regs->regs[9]); |
| 538 | 538 | |
| 539 | − if (unlikely(current->audit_context)) | |
| 540 | − audit_syscall_entry(audit_arch(), regs->regs[1], | |
| 541 | − regs->regs[2], regs->regs[3], | |
| 542 | − regs->regs[4], regs->regs[5]); | |
| 539 | + audit_syscall_entry(audit_arch(), regs->regs[1], | |
| 540 | + regs->regs[2], regs->regs[3], | |
| 541 | + regs->regs[4], regs->regs[5]); | |
| 543 | 542 | |
| 544 | 543 | return ret ?: regs->regs[9]; |
| 545 | 544 | } |
| @@ -548,9 +547,7 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) · 2 unmodified lines | ||
| 548 | 547 | { |
| 549 | 548 | int step; |
| 550 | 549 | |
| 551 | − if (unlikely(current->audit_context)) | |
| 552 | − audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]), | |
| 553 | − regs->regs[9]); | |
| 550 | + audit_syscall_exit(regs); | |
| 554 | 551 | |
| 555 | 552 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 556 | 553 | trace_sys_exit(regs, regs->regs[9]); |
| @@ -33,6 +33,7 @@ config SPARC · 32 unmodified lines | ||
| 33 | 33 | config SPARC32 |
| 34 | 34 | def_bool !64BIT |
| 35 | 35 | select GENERIC_ATOMIC64 |
| 36 | + select CLZ_TAB | |
| 36 | 37 | |
| 37 | 38 | config SPARC64 |
| 38 | 39 | def_bool 64BIT |
| @@ -207,7 +207,15 @@ do { current_thread_info()->syscall_noerror = 1; \ · 206 unmodified lines | ||
| 207 | 207 | #define instruction_pointer(regs) ((regs)->tpc) |
| 208 | 208 | #define instruction_pointer_set(regs, val) ((regs)->tpc = (val)) |
| 209 | 209 | #define user_stack_pointer(regs) ((regs)->u_regs[UREG_FP]) |
| 210 | −#define regs_return_value(regs) ((regs)->u_regs[UREG_I0]) | |
| 210 | +static inline int is_syscall_success(struct pt_regs *regs) | |
| 211 | +{ | |
| 212 | + return !(regs->tstate & (TSTATE_XCARRY | TSTATE_ICARRY)); | |
| 213 | +} | |
| 214 | + | |
| 215 | +static inline long regs_return_value(struct pt_regs *regs) | |
| 216 | +{ | |
| 217 | + return regs->u_regs[UREG_I0]; | |
| 218 | +} | |
| 211 | 219 | #ifdef CONFIG_SMP |
| 212 | 220 | extern unsigned long profile_pc(struct pt_regs *); |
| 213 | 221 | #else |
| @@ -1071,32 +1071,22 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs) · 1070 unmodified lines | ||
| 1071 | 1071 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 1072 | 1072 | trace_sys_enter(regs, regs->u_regs[UREG_G1]); |
| 1073 | 1073 | |
| 1074 | − if (unlikely(current->audit_context) && !ret) | |
| 1075 | − audit_syscall_entry((test_thread_flag(TIF_32BIT) ? | |
| 1076 | − AUDIT_ARCH_SPARC : | |
| 1077 | − AUDIT_ARCH_SPARC64), | |
| 1078 | − regs->u_regs[UREG_G1], | |
| 1079 | − regs->u_regs[UREG_I0], | |
| 1080 | − regs->u_regs[UREG_I1], | |
| 1081 | − regs->u_regs[UREG_I2], | |
| 1082 | − regs->u_regs[UREG_I3]); | |
| 1074 | + audit_syscall_entry((test_thread_flag(TIF_32BIT) ? | |
| 1075 | + AUDIT_ARCH_SPARC : | |
| 1076 | + AUDIT_ARCH_SPARC64), | |
| 1077 | + regs->u_regs[UREG_G1], | |
| 1078 | + regs->u_regs[UREG_I0], | |
| 1079 | + regs->u_regs[UREG_I1], | |
| 1080 | + regs->u_regs[UREG_I2], | |
| 1081 | + regs->u_regs[UREG_I3]); | |
| 1083 | 1082 | |
| 1084 | 1083 | return ret; |
| 1085 | 1084 | } |
| 1086 | 1085 | |
| 1087 | 1086 | asmlinkage void syscall_trace_leave(struct pt_regs *regs) |
| 1088 | 1087 | { |
| 1089 | −#ifdef CONFIG_AUDITSYSCALL | |
| 1090 | − if (unlikely(current->audit_context)) { | |
| 1091 | − unsigned long tstate = regs->tstate; | |
| 1092 | − int result = AUDITSC_SUCCESS; | |
| 1088 | + audit_syscall_exit(regs); | |
| 1093 | 1089 | |
| 1094 | − if (unlikely(tstate & (TSTATE_XCARRY | TSTATE_ICARRY))) | |
| 1095 | − result = AUDITSC_FAILURE; | |
| 1096 | − | |
| 1097 | − audit_syscall_exit(result, regs->u_regs[UREG_I0]); | |
| 1098 | − } | |
| 1099 | −#endif | |
| 1100 | 1090 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 1101 | 1091 | trace_sys_exit(regs, regs->u_regs[UREG_G1]); |
| 1102 | 1092 | |
| @@ -399,6 +399,9 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn) · 398 unmodified lines | ||
| 399 | 399 | timers_global = (void __iomem *) |
| 400 | 400 | (unsigned long) addr[num_cpu_timers]; |
| 401 | 401 | |
| 402 | + /* Every per-cpu timer works in timer mode */ | |
| 403 | + sbus_writel(0x00000000, &timers_global->timer_config); | |
| 404 | + | |
| 402 | 405 | sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit); |
| 403 | 406 | |
| 404 | 407 | master_l10_counter = &timers_global->l10_count; |
| @@ -17,23 +17,9 @@ along with GNU CC; see the file COPYING. If not, write to · 16 unmodified lines | ||
| 17 | 17 | the Free Software Foundation, 59 Temple Place - Suite 330, |
| 18 | 18 | Boston, MA 02111-1307, USA. */ |
| 19 | 19 | |
| 20 | − .data | |
| 21 | − .align 8 | |
| 22 | − .globl __clz_tab | |
| 23 | −__clz_tab: | |
| 24 | − .byte 0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5 | |
| 25 | − .byte 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6 | |
| 26 | − .byte 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7 | |
| 27 | − .byte 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7 | |
| 28 | − .byte 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8 | |
| 29 | − .byte 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8 | |
| 30 | − .byte 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8 | |
| 31 | − .byte 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8 | |
| 32 | − .size __clz_tab,256 | |
| 33 | − .global .udiv | |
| 34 | − | |
| 35 | 20 | .text |
| 36 | 21 | .align 4 |
| 22 | + .global .udiv | |
| 37 | 23 | .globl __divdi3 |
| 38 | 24 | __divdi3: |
| 39 | 25 | save %sp,-104,%sp |
| @@ -167,17 +167,15 @@ void syscall_trace(struct uml_pt_regs *regs, int entryexit) · 166 unmodified lines | ||
| 167 | 167 | int is_singlestep = (current->ptrace & PT_DTRACE) && entryexit; |
| 168 | 168 | int tracesysgood; |
| 169 | 169 | |
| 170 | − if (unlikely(current->audit_context)) { | |
| 171 | − if (!entryexit) | |
| 172 | − audit_syscall_entry(HOST_AUDIT_ARCH, | |
| 173 | − UPT_SYSCALL_NR(regs), | |
| 174 | − UPT_SYSCALL_ARG1(regs), | |
| 175 | − UPT_SYSCALL_ARG2(regs), | |
| 176 | − UPT_SYSCALL_ARG3(regs), | |
| 177 | − UPT_SYSCALL_ARG4(regs)); | |
| 178 | − else audit_syscall_exit(AUDITSC_RESULT(UPT_SYSCALL_RET(regs)), | |
| 179 | − UPT_SYSCALL_RET(regs)); | |
| 180 | − } | |
| 170 | + if (!entryexit) | |
| 171 | + audit_syscall_entry(HOST_AUDIT_ARCH, | |
| 172 | + UPT_SYSCALL_NR(regs), | |
| 173 | + UPT_SYSCALL_ARG1(regs), | |
| 174 | + UPT_SYSCALL_ARG2(regs), | |
| 175 | + UPT_SYSCALL_ARG3(regs), | |
| 176 | + UPT_SYSCALL_ARG4(regs)); | |
| 177 | + else | |
| 178 | + audit_syscall_exit(regs); | |
| 181 | 179 | |
| 182 | 180 | /* Fake a debug trap */ |
| 183 | 181 | if (is_singlestep) |
| @@ -1,3 +1,4 @@ | ||
| 1 | 1 | boot/compressed/vmlinux |
| 2 | 2 | tools/test_get_len |
| 3 | +tools/insn_sanity | |
| 3 | 4 | |
| @@ -125,16 +125,6 @@ config HAVE_LATENCYTOP_SUPPORT · 124 unmodified lines | ||
| 125 | 125 | config MMU |
| 126 | 126 | def_bool y |
| 127 | 127 | |
| 128 | −config ZONE_DMA | |
| 129 | − bool "DMA memory allocation support" if EXPERT | |
| 130 | − default y | |
| 131 | − help | |
| 132 | − DMA memory allocation support allows devices with less than 32-bit | |
| 133 | − addressing to allocate within the first 16MB of address space. | |
| 134 | − Disable if no such devices will be used. | |
| 135 | − | |
| 136 | − If unsure, say Y. | |
| 137 | − | |
| 138 | 128 | config SBUS |
| 139 | 129 | bool |
| 140 | 130 | |
| @@ -255,6 +245,16 @@ source "kernel/Kconfig.freezer" · 114 unmodified lines | ||
| 255 | 245 | |
| 256 | 246 | menu "Processor type and features" |
| 257 | 247 | |
| 248 | +config ZONE_DMA | |
| 249 | + bool "DMA memory allocation support" if EXPERT | |
| 250 | + default y | |
| 251 | + help | |
| 252 | + DMA memory allocation support allows devices with less than 32-bit | |
| 253 | + addressing to allocate within the first 16MB of address space. | |
| 254 | + Disable if no such devices will be used. | |
| 255 | + | |
| 256 | + If unsure, say Y. | |
| 257 | + | |
| 258 | 258 | source "kernel/time/Kconfig" |
| 259 | 259 | |
| 260 | 260 | config SMP |
| @@ -360,7 +360,6 @@ config X86_NUMACHIP · 99 unmodified lines | ||
| 360 | 360 | depends on NUMA |
| 361 | 361 | depends on SMP |
| 362 | 362 | depends on X86_X2APIC |
| 363 | − depends on !EDAC_AMD64 | |
| 364 | 363 | ---help--- |
| 365 | 364 | Adds support for Numascale NumaChip large-SMP systems. Needed to |
| 366 | 365 | enable more than ~168 cores. |
| @@ -321,6 +321,8 @@ static void parse_elf(void *output) · 320 unmodified lines | ||
| 321 | 321 | default: /* Ignore other PT_* */ break; |
| 322 | 322 | } |
| 323 | 323 | } |
| 324 | + | |
| 325 | + free(phdrs); | |
| 324 | 326 | } |
| 325 | 327 | |
| 326 | 328 | asmlinkage void decompress_kernel(void *rmode, memptr heap, |
| @@ -14,6 +14,7 @@ · 13 unmodified lines | ||
| 14 | 14 | #include <asm/segment.h> |
| 15 | 15 | #include <asm/irqflags.h> |
| 16 | 16 | #include <linux/linkage.h> |
| 17 | +#include <linux/err.h> | |
| 17 | 18 | |
| 18 | 19 | /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */ |
| 19 | 20 | #include <linux/elf-em.h> |
| @@ -189,7 +190,7 @@ sysexit_from_sys_call: · 169 unmodified lines | ||
| 189 | 190 | movl %ebx,%edx /* 3rd arg: 1st syscall arg */ |
| 190 | 191 | movl %eax,%esi /* 2nd arg: syscall number */ |
| 191 | 192 | movl $AUDIT_ARCH_I386,%edi /* 1st arg: audit arch */ |
| 192 | − call audit_syscall_entry | |
| 193 | + call __audit_syscall_entry | |
| 193 | 194 | movl RAX-ARGOFFSET(%rsp),%eax /* reload syscall number */ |
| 194 | 195 | cmpq $(IA32_NR_syscalls-1),%rax |
| 195 | 196 | ja ia32_badsys |
| @@ -206,12 +207,13 @@ sysexit_from_sys_call: · 10 unmodified lines | ||
| 206 | 207 | TRACE_IRQS_ON |
| 207 | 208 | sti |
| 208 | 209 | movl %eax,%esi /* second arg, syscall return value */ |
| 209 | − cmpl $0,%eax /* is it < 0? */ | |
| 210 | − setl %al /* 1 if so, 0 if not */ | |
| 210 | + cmpl $-MAX_ERRNO,%eax /* is it an error ? */ | |
| 211 | + jbe 1f | |
| 212 | + movslq %eax, %rsi /* if error sign extend to 64 bits */ | |
| 213 | +1: setbe %al /* 1 if error, 0 if not */ | |
| 211 | 214 | movzbl %al,%edi /* zero-extend that into %edi */ |
| 212 | − inc %edi /* first arg, 0->1(AUDITSC_SUCCESS), 1->2(AUDITSC_FAILURE) */ | |
| 213 | − call audit_syscall_exit | |
| 214 | − movl RAX-ARGOFFSET(%rsp),%eax /* reload syscall return value */ | |
| 215 | + call __audit_syscall_exit | |
| 216 | + movq RAX-ARGOFFSET(%rsp),%rax /* reload syscall return value */ | |
| 215 | 217 | movl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),%edi |
| 216 | 218 | cli |
| 217 | 219 | TRACE_IRQS_OFF |
| @@ -145,13 +145,13 @@ extern void __add_wrong_size(void) · 144 unmodified lines | ||
| 145 | 145 | |
| 146 | 146 | #ifdef __HAVE_ARCH_CMPXCHG |
| 147 | 147 | #define cmpxchg(ptr, old, new) \ |
| 148 | − __cmpxchg((ptr), (old), (new), sizeof(*ptr)) | |
| 148 | + __cmpxchg(ptr, old, new, sizeof(*(ptr))) | |
| 149 | 149 | |
| 150 | 150 | #define sync_cmpxchg(ptr, old, new) \ |
| 151 | − __sync_cmpxchg((ptr), (old), (new), sizeof(*ptr)) | |
| 151 | + __sync_cmpxchg(ptr, old, new, sizeof(*(ptr))) | |
| 152 | 152 | |
| 153 | 153 | #define cmpxchg_local(ptr, old, new) \ |
| 154 | − __cmpxchg_local((ptr), (old), (new), sizeof(*ptr)) | |
| 154 | + __cmpxchg_local(ptr, old, new, sizeof(*(ptr))) | |
| 155 | 155 | #endif |
| 156 | 156 | |
| 157 | 157 | /* |
| @@ -159,6 +159,7 @@ · 158 unmodified lines | ||
| 159 | 159 | #define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ |
| 160 | 160 | #define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ |
| 161 | 161 | #define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ |
| 162 | +#define X86_FEATURE_TCE (6*32+17) /* translation cache extension */ | |
| 162 | 163 | #define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ |
| 163 | 164 | #define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ |
| 164 | 165 | #define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ |
| @@ -29,10 +29,11 @@ extern unsigned int sig_xstate_size; · 28 unmodified lines | ||
| 29 | 29 | extern void fpu_init(void); |
| 30 | 30 | extern void mxcsr_feature_mask_init(void); |
| 31 | 31 | extern int init_fpu(struct task_struct *child); |
| 32 | −extern asmlinkage void math_state_restore(void); | |
| 33 | −extern void __math_state_restore(void); | |
| 32 | +extern void math_state_restore(void); | |
| 34 | 33 | extern int dump_fpu(struct pt_regs *, struct user_i387_struct *); |
| 35 | 34 | |
| 35 | +DECLARE_PER_CPU(struct task_struct *, fpu_owner_task); | |
| 36 | + | |
| 36 | 37 | extern user_regset_active_fn fpregs_active, xfpregs_active; |
| 37 | 38 | extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get, |
| 38 | 39 | xstateregs_get; |
| @@ -212,19 +213,11 @@ static inline void fpu_fxsave(struct fpu *fpu) · 173 unmodified lines | ||
| 212 | 213 | |
| 213 | 214 | #endif /* CONFIG_X86_64 */ |
| 214 | 215 | |
| 215 | −/* We need a safe address that is cheap to find and that is already | |
| 216 | − in L1 during context switch. The best choices are unfortunately | |
| 217 | − different for UP and SMP */ | |
| 218 | −#ifdef CONFIG_SMP | |
| 219 | −#define safe_address (__per_cpu_offset[0]) | |
| 220 | −#else | |
| 221 | −#define safe_address (__get_cpu_var(kernel_cpustat).cpustat[CPUTIME_USER]) | |
| 222 | −#endif | |
| 223 | − | |
| 224 | 216 | /* |
| 225 | − * These must be called with preempt disabled | |
| 217 | + * These must be called with preempt disabled. Returns | |
| 218 | + * 'true' if the FPU state is still intact. | |
| 226 | 219 | */ |
| 227 | −static inline void fpu_save_init(struct fpu *fpu) | |
| 220 | +static inline int fpu_save_init(struct fpu *fpu) | |
| 228 | 221 | { |
| 229 | 222 | if (use_xsave()) { |
| 230 | 223 | fpu_xsave(fpu); |
| @@ -233,33 +226,33 @@ static inline void fpu_save_init(struct fpu *fpu) · 2 unmodified lines | ||
| 233 | 226 | * xsave header may indicate the init state of the FP. |
| 234 | 227 | */ |
| 235 | 228 | if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP)) |
| 236 | − return; | |
| 229 | + return 1; | |
| 237 | 230 | } else if (use_fxsr()) { |
| 238 | 231 | fpu_fxsave(fpu); |
| 239 | 232 | } else { |
| 240 | 233 | asm volatile("fnsave %[fx]; fwait" |
| 241 | 234 | : [fx] "=m" (fpu->state->fsave)); |
| 242 | − return; | |
| 235 | + return 0; | |
| 243 | 236 | } |
| 244 | 237 | |
| 245 | − if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) | |
| 238 | + /* | |
| 239 | + * If exceptions are pending, we need to clear them so | |
| 240 | + * that we don't randomly get exceptions later. | |
| 241 | + * | |
| 242 | + * FIXME! Is this perhaps only true for the old-style | |
| 243 | + * irq13 case? Maybe we could leave the x87 state | |
| 244 | + * intact otherwise? | |
| 245 | + */ | |
| 246 | + if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) { | |
| 246 | 247 | asm volatile("fnclex"); |
| 247 | − | |
| 248 | − /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception | |
| 249 | − is pending. Clear the x87 state here by setting it to fixed | |
| 250 | − values. safe_address is a random variable that should be in L1 */ | |
| 251 | − alternative_input( | |
| 252 | − ASM_NOP8 ASM_NOP2, | |
| 253 | − "emms\n\t" /* clear stack tags */ | |
| 254 | − "fildl %P[addr]", /* set F?P to defined value */ | |
| 255 | − X86_FEATURE_FXSAVE_LEAK, | |
| 256 | − [addr] "m" (safe_address)); | |
| 248 | + return 0; | |
| 249 | + } | |
| 250 | + return 1; | |
| 257 | 251 | } |
| 258 | 252 | |
| 259 | −static inline void __save_init_fpu(struct task_struct *tsk) | |
| 253 | +static inline int __save_init_fpu(struct task_struct *tsk) | |
| 260 | 254 | { |
| 261 | − fpu_save_init(&tsk->thread.fpu); | |
| 262 | − task_thread_info(tsk)->status &= ~TS_USEDFPU; | |
| 255 | + return fpu_save_init(&tsk->thread.fpu); | |
| 263 | 256 | } |
| 264 | 257 | |
| 265 | 258 | static inline int fpu_fxrstor_checking(struct fpu *fpu) |
| @@ -277,44 +270,212 @@ static inline int fpu_restore_checking(struct fpu *fpu) · 11 unmodified lines | ||
| 277 | 270 | |
| 278 | 271 | static inline int restore_fpu_checking(struct task_struct *tsk) |
| 279 | 272 | { |
| 273 | + /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception | |
| 274 | + is pending. Clear the x87 state here by setting it to fixed | |
| 275 | + values. "m" is a random variable that should be in L1 */ | |
| 276 | + alternative_input( | |
| 277 | + ASM_NOP8 ASM_NOP2, | |
| 278 | + "emms\n\t" /* clear stack tags */ | |
| 279 | + "fildl %P[addr]", /* set F?P to defined value */ | |
| 280 | + X86_FEATURE_FXSAVE_LEAK, | |
| 281 | + [addr] "m" (tsk->thread.fpu.has_fpu)); | |
| 282 | + | |
| 280 | 283 | return fpu_restore_checking(&tsk->thread.fpu); |
| 281 | 284 | } |
| 282 | 285 | |
| 283 | 286 | /* |
| 284 | − * Signal frame handlers... | |
| 287 | + * Software FPU state helpers. Careful: these need to | |
| 288 | + * be preemption protection *and* they need to be | |
| 289 | + * properly paired with the CR0.TS changes! | |
| 285 | 290 | */ |
| 286 | −extern int save_i387_xstate(void __user *buf); | |
| 287 | −extern int restore_i387_xstate(void __user *buf); | |
| 291 | +static inline int __thread_has_fpu(struct task_struct *tsk) | |
| 292 | +{ | |
| 293 | + return tsk->thread.fpu.has_fpu; | |
| 294 | +} | |
| 288 | 295 | |
| 289 | −static inline void __unlazy_fpu(struct task_struct *tsk) | |
| 296 | +/* Must be paired with an 'stts' after! */ | |
| 297 | +static inline void __thread_clear_has_fpu(struct task_struct *tsk) | |
| 290 | 298 | { |
| 291 | − if (task_thread_info(tsk)->status & TS_USEDFPU) { | |
| 292 | − __save_init_fpu(tsk); | |
| 293 | − stts(); | |
| 294 | − } else | |
| 295 | − tsk->fpu_counter = 0; | |
| 299 | + tsk->thread.fpu.has_fpu = 0; | |
| 300 | + percpu_write(fpu_owner_task, NULL); | |
| 301 | +} | |
| 302 | + | |
| 303 | +/* Must be paired with a 'clts' before! */ | |
| 304 | +static inline void __thread_set_has_fpu(struct task_struct *tsk) | |
| 305 | +{ | |
| 306 | + tsk->thread.fpu.has_fpu = 1; | |
| 307 | + percpu_write(fpu_owner_task, tsk); | |
| 308 | +} | |
| 309 | + | |
| 310 | +/* | |
| 311 | + * Encapsulate the CR0.TS handling together with the | |
| 312 | + * software flag. | |
| 313 | + * | |
| 314 | + * These generally need preemption protection to work, | |
| 315 | + * do try to avoid using these on their own. | |
| 316 | + */ | |
| 317 | +static inline void __thread_fpu_end(struct task_struct *tsk) | |
| 318 | +{ | |
| 319 | + __thread_clear_has_fpu(tsk); | |
| 320 | + stts(); | |
| 321 | +} | |
| 322 | + | |
| 323 | +static inline void __thread_fpu_begin(struct task_struct *tsk) | |
| 324 | +{ | |
| 325 | + clts(); | |
| 326 | + __thread_set_has_fpu(tsk); | |
| 327 | +} | |
| 328 | + | |
| 329 | +/* | |
| 330 | + * FPU state switching for scheduling. | |
| 331 | + * | |
| 332 | + * This is a two-stage process: | |
| 333 | + * | |
| 334 | + * - switch_fpu_prepare() saves the old state and | |
| 335 | + * sets the new state of the CR0.TS bit. This is | |
| 336 | + * done within the context of the old process. | |
| 337 | + * | |
| 338 | + * - switch_fpu_finish() restores the new state as | |
| 339 | + * necessary. | |
| 340 | + */ | |
| 341 | +typedef struct { int preload; } fpu_switch_t; | |
| 342 | + | |
| 343 | +/* | |
| 344 | + * FIXME! We could do a totally lazy restore, but we need to | |
| 345 | + * add a per-cpu "this was the task that last touched the FPU | |
| 346 | + * on this CPU" variable, and the task needs to have a "I last | |
| 347 | + * touched the FPU on this CPU" and check them. | |
| 348 | + * | |
| 349 | + * We don't do that yet, so "fpu_lazy_restore()" always returns | |
| 350 | + * false, but some day.. | |
| 351 | + */ | |
| 352 | +static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu) | |
| 353 | +{ | |
| 354 | + return new == percpu_read_stable(fpu_owner_task) && | |
| 355 | + cpu == new->thread.fpu.last_cpu; | |
| 356 | +} | |
| 357 | + | |
| 358 | +static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu) | |
| 359 | +{ | |
| 360 | + fpu_switch_t fpu; | |
| 361 | + | |
| 362 | + fpu.preload = tsk_used_math(new) && new->fpu_counter > 5; | |
| 363 | + if (__thread_has_fpu(old)) { | |
| 364 | + if (!__save_init_fpu(old)) | |
| 365 | + cpu = ~0; | |
| 366 | + old->thread.fpu.last_cpu = cpu; | |
| 367 | + old->thread.fpu.has_fpu = 0; /* But leave fpu_owner_task! */ | |
| 368 | + | |
| 369 | + /* Don't change CR0.TS if we just switch! */ | |
| 370 | + if (fpu.preload) { | |
| 371 | + new->fpu_counter++; | |
| 372 | + __thread_set_has_fpu(new); | |
| 373 | + prefetch(new->thread.fpu.state); | |
| 374 | + } else | |
| 375 | + stts(); | |
| 376 | + } else { | |
| 377 | + old->fpu_counter = 0; | |
| 378 | + old->thread.fpu.last_cpu = ~0; | |
| 379 | + if (fpu.preload) { | |
| 380 | + new->fpu_counter++; | |
| 381 | + if (fpu_lazy_restore(new, cpu)) | |
| 382 | + fpu.preload = 0; | |
| 383 | + else | |
| 384 | + prefetch(new->thread.fpu.state); | |
| 385 | + __thread_fpu_begin(new); | |
| 386 | + } | |
| 387 | + } | |
| 388 | + return fpu; | |
| 389 | +} | |
| 390 | + | |
| 391 | +/* | |
| 392 | + * By the time this gets called, we've already cleared CR0.TS and | |
| 393 | + * given the process the FPU if we are going to preload the FPU | |
| 394 | + * state - all we need to do is to conditionally restore the register | |
| 395 | + * state itself. | |
| 396 | + */ | |
| 397 | +static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu) | |
| 398 | +{ | |
| 399 | + if (fpu.preload) { | |
| 400 | + if (unlikely(restore_fpu_checking(new))) | |
| 401 | + __thread_fpu_end(new); | |
| 402 | + } | |
| 296 | 403 | } |
| 297 | 404 | |
| 405 | +/* | |
| 406 | + * Signal frame handlers... | |
| 407 | + */ | |
| 408 | +extern int save_i387_xstate(void __user *buf); | |
| 409 | +extern int restore_i387_xstate(void __user *buf); | |
| 410 | + | |
| 298 | 411 | static inline void __clear_fpu(struct task_struct *tsk) |
| 299 | 412 | { |
| 300 | − if (task_thread_info(tsk)->status & TS_USEDFPU) { | |
| 413 | + if (__thread_has_fpu(tsk)) { | |
| 301 | 414 | /* Ignore delayed exceptions from user space */ |
| 302 | 415 | asm volatile("1: fwait\n" |
| 303 | 416 | "2:\n" |
| 304 | 417 | _ASM_EXTABLE(1b, 2b)); |
| 305 | − task_thread_info(tsk)->status &= ~TS_USEDFPU; | |
| 306 | − stts(); | |
| 418 | + __thread_fpu_end(tsk); | |
| 307 | 419 | } |
| 308 | 420 | } |
| 309 | 421 | |
| 422 | +/* | |
| 423 | + * Were we in an interrupt that interrupted kernel mode? | |
| 424 | + * | |
| 425 | + * We can do a kernel_fpu_begin/end() pair *ONLY* if that | |
| 426 | + * pair does nothing at all: the thread must not have fpu (so | |
| 427 | + * that we don't try to save the FPU state), and TS must | |
| 428 | + * be set (so that the clts/stts pair does nothing that is | |
| 429 | + * visible in the interrupted kernel thread). | |
| 430 | + */ | |
| 431 | +static inline bool interrupted_kernel_fpu_idle(void) | |
| 432 | +{ | |
| 433 | + return !__thread_has_fpu(current) && | |
| 434 | + (read_cr0() & X86_CR0_TS); | |
| 435 | +} | |
| 436 | + | |
| 437 | +/* | |
| 438 | + * Were we in user mode (or vm86 mode) when we were | |
| 439 | + * interrupted? | |
| 440 | + * | |
| 441 | + * Doing kernel_fpu_begin/end() is ok if we are running | |
| 442 | + * in an interrupt context from user mode - we'll just | |
| 443 | + * save the FPU state as required. | |
| 444 | + */ | |
| 445 | +static inline bool interrupted_user_mode(void) | |
| 446 | +{ | |
| 447 | + struct pt_regs *regs = get_irq_regs(); | |
| 448 | + return regs && user_mode_vm(regs); | |
| 449 | +} | |
| 450 | + | |
| 451 | +/* | |
| 452 | + * Can we use the FPU in kernel mode with the | |
| 453 | + * whole "kernel_fpu_begin/end()" sequence? | |
| 454 | + * | |
| 455 | + * It's always ok in process context (ie "not interrupt") | |
| 456 | + * but it is sometimes ok even from an irq. | |
| 457 | + */ | |
| 458 | +static inline bool irq_fpu_usable(void) | |
| 459 | +{ | |
| 460 | + return !in_interrupt() || | |
| 461 | + interrupted_user_mode() || | |
| 462 | + interrupted_kernel_fpu_idle(); | |
| 463 | +} | |
| 464 | + | |
| 310 | 465 | static inline void kernel_fpu_begin(void) |
| 311 | 466 | { |
| 312 | − struct thread_info *me = current_thread_info(); | |
| 467 | + struct task_struct *me = current; | |
| 468 | + | |
| 469 | + WARN_ON_ONCE(!irq_fpu_usable()); | |
| 313 | 470 | preempt_disable(); |
| 314 | − if (me->status & TS_USEDFPU) | |
| 315 | − __save_init_fpu(me->task); | |
| 316 | − else | |
| 471 | + if (__thread_has_fpu(me)) { | |
| 472 | + __save_init_fpu(me); | |
| 473 | + __thread_clear_has_fpu(me); | |
| 474 | + /* We do 'stts()' in kernel_fpu_end() */ | |
| 475 | + } else { | |
| 476 | + percpu_write(fpu_owner_task, NULL); | |
| 317 | 477 | clts(); |
| 478 | + } | |
| 318 | 479 | } |
| 319 | 480 | |
| 320 | 481 | static inline void kernel_fpu_end(void) |
| @@ -323,14 +484,6 @@ static inline void kernel_fpu_end(void) · 2 unmodified lines | ||
| 323 | 484 | preempt_enable(); |
| 324 | 485 | } |
| 325 | 486 | |
| 326 | −static inline bool irq_fpu_usable(void) | |
| 327 | −{ | |
| 328 | − struct pt_regs *regs; | |
| 329 | − | |
| 330 | − return !in_interrupt() || !(regs = get_irq_regs()) || \ | |
| 331 | − user_mode(regs) || (read_cr0() & X86_CR0_TS); | |
| 332 | −} | |
| 333 | − | |
| 334 | 487 | /* |
| 335 | 488 | * Some instructions like VIA's padlock instructions generate a spurious |
| 336 | 489 | * DNA fault but don't modify SSE registers. And these instructions |
| @@ -362,21 +515,65 @@ static inline void irq_ts_restore(int TS_state) · 25 unmodified lines | ||
| 362 | 515 | stts(); |
| 363 | 516 | } |
| 364 | 517 | |
| 518 | +/* | |
| 519 | + * The question "does this thread have fpu access?" | |
| 520 | + * is slightly racy, since preemption could come in | |
| 521 | + * and revoke it immediately after the test. | |
| 522 | + * | |
| 523 | + * However, even in that very unlikely scenario, | |
| 524 | + * we can just assume we have FPU access - typically | |
| 525 | + * to save the FP state - we'll just take a #NM | |
| 526 | + * fault and get the FPU access back. | |
| 527 | + * | |
| 528 | + * The actual user_fpu_begin/end() functions | |
| 529 | + * need to be preemption-safe, though. | |
| 530 | + * | |
| 531 | + * NOTE! user_fpu_end() must be used only after you | |
| 532 | + * have saved the FP state, and user_fpu_begin() must | |
| 533 | + * be used only immediately before restoring it. | |
| 534 | + * These functions do not do any save/restore on | |
| 535 | + * their own. | |
| 536 | + */ | |
| 537 | +static inline int user_has_fpu(void) | |
| 538 | +{ | |
| 539 | + return __thread_has_fpu(current); | |
| 540 | +} | |
| 541 | + | |
| 542 | +static inline void user_fpu_end(void) | |
| 543 | +{ | |
| 544 | + preempt_disable(); | |
| 545 | + __thread_fpu_end(current); | |
| 546 | + preempt_enable(); | |
| 547 | +} | |
| 548 | + | |
| 549 | +static inline void user_fpu_begin(void) | |
| 550 | +{ | |
| 551 | + preempt_disable(); | |
| 552 | + if (!user_has_fpu()) | |
| 553 | + __thread_fpu_begin(current); | |
| 554 | + preempt_enable(); | |
| 555 | +} | |
| 556 | + | |
| 365 | 557 | /* |
| 366 | 558 | * These disable preemption on their own and are safe |
| 367 | 559 | */ |
| 368 | 560 | static inline void save_init_fpu(struct task_struct *tsk) |
| 369 | 561 | { |
| 562 | + WARN_ON_ONCE(!__thread_has_fpu(tsk)); | |
| 370 | 563 | preempt_disable(); |
| 371 | 564 | __save_init_fpu(tsk); |
| 372 | − stts(); | |
| 565 | + __thread_fpu_end(tsk); | |
| 373 | 566 | preempt_enable(); |
| 374 | 567 | } |
| 375 | 568 | |
| 376 | 569 | static inline void unlazy_fpu(struct task_struct *tsk) |
| 377 | 570 | { |
| 378 | 571 | preempt_disable(); |
| 379 | − __unlazy_fpu(tsk); | |
| 572 | + if (__thread_has_fpu(tsk)) { | |
| 573 | + __save_init_fpu(tsk); | |
| 574 | + __thread_fpu_end(tsk); | |
| 575 | + } else | |
| 576 | + tsk->fpu_counter = 0; | |
| 380 | 577 | preempt_enable(); |
| 381 | 578 | } |
| 382 | 579 | |
| @@ -190,6 +190,9 @@ struct x86_emulate_ops { · 189 unmodified lines | ||
| 190 | 190 | int (*intercept)(struct x86_emulate_ctxt *ctxt, |
| 191 | 191 | struct x86_instruction_info *info, |
| 192 | 192 | enum x86_intercept_stage stage); |
| 193 | + | |
| 194 | + bool (*get_cpuid)(struct x86_emulate_ctxt *ctxt, | |
| 195 | + u32 *eax, u32 *ebx, u32 *ecx, u32 *edx); | |
| 193 | 196 | }; |
| 194 | 197 | |
| 195 | 198 | typedef u32 __attribute__((vector_size(16))) sse128_t; |
| @@ -298,6 +301,19 @@ struct x86_emulate_ctxt { · 102 unmodified lines | ||
| 298 | 301 | #define X86EMUL_MODE_PROT (X86EMUL_MODE_PROT16|X86EMUL_MODE_PROT32| \ |
| 299 | 302 | X86EMUL_MODE_PROT64) |
| 300 | 303 | |
| 304 | +/* CPUID vendors */ | |
| 305 | +#define X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx 0x68747541 | |
| 306 | +#define X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163 | |
| 307 | +#define X86EMUL_CPUID_VENDOR_AuthenticAMD_edx 0x69746e65 | |
| 308 | + | |
| 309 | +#define X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx 0x69444d41 | |
| 310 | +#define X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx 0x21726574 | |
| 311 | +#define X86EMUL_CPUID_VENDOR_AMDisbetterI_edx 0x74656273 | |
| 312 | + | |
| 313 | +#define X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 0x756e6547 | |
| 314 | +#define X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 0x6c65746e | |
| 315 | +#define X86EMUL_CPUID_VENDOR_GenuineIntel_edx 0x49656e69 | |
| 316 | + | |
| 301 | 317 | enum x86_intercept_stage { |
| 302 | 318 | X86_ICTP_NONE = 0, /* Allow zero-init to not match anything */ |
| 303 | 319 | X86_ICPT_PRE_EXCEPT, |
| @@ -374,6 +374,8 @@ union thread_xstate { · 373 unmodified lines | ||
| 374 | 374 | }; |
| 375 | 375 | |
| 376 | 376 | struct fpu { |
| 377 | + unsigned int last_cpu; | |
| 378 | + unsigned int has_fpu; | |
| 377 | 379 | union thread_xstate *state; |
| 378 | 380 | }; |
| 379 | 381 | |
| @@ -247,8 +247,6 @@ static inline struct thread_info *current_thread_info(void) · 246 unmodified lines | ||
| 247 | 247 | * ever touches our thread-synchronous status, so we don't |
| 248 | 248 | * have to worry about atomic accesses. |
| 249 | 249 | */ |
| 250 | −#define TS_USEDFPU 0x0001 /* FPU was used by this task | |
| 251 | − this quantum (SMP) */ | |
| 252 | 250 | #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ |
| 253 | 251 | #define TS_POLLING 0x0004 /* idle task polling need_resched, |
| 254 | 252 | skip sending interrupt */ |
| @@ -7,6 +7,7 @@ · 6 unmodified lines | ||
| 7 | 7 | # include <asm/unistd_32.h> |
| 8 | 8 | # define __ARCH_WANT_IPC_PARSE_VERSION |
| 9 | 9 | # define __ARCH_WANT_STAT64 |
| 10 | +# define __ARCH_WANT_SYS_IPC | |
| 10 | 11 | # define __ARCH_WANT_SYS_OLD_MMAP |
| 11 | 12 | # define __ARCH_WANT_SYS_OLD_SELECT |
| 12 | 13 | |
| @@ -65,7 +65,7 @@ · 64 unmodified lines | ||
| 65 | 65 | * UV2: Bit 19 selects between |
| 66 | 66 | * (0): 10 microsecond timebase and |
| 67 | 67 | * (1): 80 microseconds |
| 68 | − * we're using 655us, similar to UV1: 65 units of 10us | |
| 68 | + * we're using 560us, similar to UV1: 65 units of 10us | |
| 69 | 69 | */ |
| 70 | 70 | #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL) |
| 71 | 71 | #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL) |
| @@ -167,6 +167,7 @@ · 95 unmodified lines | ||
| 167 | 167 | #define FLUSH_RETRY_TIMEOUT 2 |
| 168 | 168 | #define FLUSH_GIVEUP 3 |
| 169 | 169 | #define FLUSH_COMPLETE 4 |
| 170 | +#define FLUSH_RETRY_BUSYBUG 5 | |
| 170 | 171 | |
| 171 | 172 | /* |
| 172 | 173 | * tuning the action when the numalink network is extremely delayed |
| @@ -235,10 +236,10 @@ struct bau_msg_payload { · 62 unmodified lines | ||
| 235 | 236 | |
| 236 | 237 | |
| 237 | 238 | /* |
| 238 | − * Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor) | |
| 239 | + * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor) | |
| 239 | 240 | * see table 4.2.3.0.1 in broacast_assist spec. |
| 240 | 241 | */ |
| 241 | −struct bau_msg_header { | |
| 242 | +struct uv1_bau_msg_header { | |
| 242 | 243 | unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */ |
| 243 | 244 | /* bits 5:0 */ |
| 244 | 245 | unsigned int base_dest_nasid:15; /* nasid of the first bit */ |
| @@ -317,20 +318,88 @@ struct bau_msg_header { · 72 unmodified lines | ||
| 317 | 318 | /* bits 127:107 */ |
| 318 | 319 | }; |
| 319 | 320 | |
| 321 | +/* | |
| 322 | + * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor) | |
| 323 | + * see figure 9-2 of harp_sys.pdf | |
| 324 | + */ | |
| 325 | +struct uv2_bau_msg_header { | |
| 326 | + unsigned int base_dest_nasid:15; /* nasid of the first bit */ | |
| 327 | + /* bits 14:0 */ /* in uvhub map */ | |
| 328 | + unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */ | |
| 329 | + /* bits 19:15 */ | |
| 330 | + unsigned int rsvd_1:1; /* must be zero */ | |
| 331 | + /* bit 20 */ | |
| 332 | + /* Address bits 59:21 */ | |
| 333 | + /* bits 25:2 of address (44:21) are payload */ | |
| 334 | + /* these next 24 bits become bytes 12-14 of msg */ | |
| 335 | + /* bits 28:21 land in byte 12 */ | |
| 336 | + unsigned int replied_to:1; /* sent as 0 by the source to | |
| 337 | + byte 12 */ | |
| 338 | + /* bit 21 */ | |
| 339 | + unsigned int msg_type:3; /* software type of the | |
| 340 | + message */ | |
| 341 | + /* bits 24:22 */ | |
| 342 | + unsigned int canceled:1; /* message canceled, resource | |
| 343 | + is to be freed*/ | |
| 344 | + /* bit 25 */ | |
| 345 | + unsigned int payload_1:3; /* not currently used */ | |
| 346 | + /* bits 28:26 */ | |
| 347 | + | |
| 348 | + /* bits 36:29 land in byte 13 */ | |
| 349 | + unsigned int payload_2a:3; /* not currently used */ | |
| 350 | + unsigned int payload_2b:5; /* not currently used */ | |
| 351 | + /* bits 36:29 */ | |
| 352 | + | |
| 353 | + /* bits 44:37 land in byte 14 */ | |
| 354 | + unsigned int payload_3:8; /* not currently used */ | |
| 355 | + /* bits 44:37 */ | |
| 356 | + | |
| 357 | + unsigned int rsvd_2:7; /* reserved */ | |
| 358 | + /* bits 51:45 */ | |
| 359 | + unsigned int swack_flag:1; /* software acknowledge flag */ | |
| 360 | + /* bit 52 */ | |
| 361 | + unsigned int rsvd_3a:3; /* must be zero */ | |
| 362 | + unsigned int rsvd_3b:8; /* must be zero */ | |
| 363 | + unsigned int rsvd_3c:8; /* must be zero */ | |
| 364 | + unsigned int rsvd_3d:3; /* must be zero */ | |
| 365 | + /* bits 74:53 */ | |
| 366 | + unsigned int fairness:3; /* usually zero */ | |
| 367 | + /* bits 77:75 */ | |
| 368 | + | |
| 369 | + unsigned int sequence:16; /* message sequence number */ | |
| 370 | + /* bits 93:78 Suppl_A */ | |
| 371 | + unsigned int chaining:1; /* next descriptor is part of | |
| 372 | + this activation*/ | |
| 373 | + /* bit 94 */ | |
| 374 | + unsigned int multilevel:1; /* multi-level multicast | |
| 375 | + format */ | |
| 376 | + /* bit 95 */ | |
| 377 | + unsigned int rsvd_4:24; /* ordered / source node / | |
| 378 | + source subnode / aging | |
| 379 | + must be zero */ | |
| 380 | + /* bits 119:96 */ | |
| 381 | + unsigned int command:8; /* message type */ | |
| 382 | + /* bits 127:120 */ | |
| 383 | +}; | |
| 384 | + | |
| 320 | 385 | /* |
| 321 | 386 | * The activation descriptor: |
| 322 | 387 | * The format of the message to send, plus all accompanying control |
| 323 | 388 | * Should be 64 bytes |
| 324 | 389 | */ |
| 325 | 390 | struct bau_desc { |
| 326 | − struct pnmask distribution; | |
| 391 | + struct pnmask distribution; | |
| 327 | 392 | /* |
| 328 | 393 | * message template, consisting of header and payload: |
| 329 | 394 | */ |
| 330 | − struct bau_msg_header header; | |
| 331 | − struct bau_msg_payload payload; | |
| 395 | + union bau_msg_header { | |
| 396 | + struct uv1_bau_msg_header uv1_hdr; | |
| 397 | + struct uv2_bau_msg_header uv2_hdr; | |
| 398 | + } header; | |
| 399 | + | |
| 400 | + struct bau_msg_payload payload; | |
| 332 | 401 | }; |
| 333 | −/* | |
| 402 | +/* UV1: | |
| 334 | 403 | * -payload-- ---------header------ |
| 335 | 404 | * bytes 0-11 bits 41-56 bits 58-81 |
| 336 | 405 | * A B (2) C (3) |
| @@ -340,6 +409,16 @@ struct bau_desc { · 3 unmodified lines | ||
| 340 | 409 | * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector) |
| 341 | 410 | * ------------payload queue----------- |
| 342 | 411 | */ |
| 412 | +/* UV2: | |
| 413 | + * -payload-- ---------header------ | |
| 414 | + * bytes 0-11 bits 70-78 bits 21-44 | |
| 415 | + * A B (2) C (3) | |
| 416 | + * | |
| 417 | + * A/B/C are moved to: | |
| 418 | + * A C B | |
| 419 | + * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector) | |
| 420 | + * ------------payload queue----------- | |
| 421 | + */ | |
| 343 | 422 | |
| 344 | 423 | /* |
| 345 | 424 | * The payload queue on the destination side is an array of these. |
| @@ -385,7 +464,6 @@ struct bau_pq_entry { · 39 unmodified lines | ||
| 385 | 464 | struct msg_desc { |
| 386 | 465 | struct bau_pq_entry *msg; |
| 387 | 466 | int msg_slot; |
| 388 | − int swack_slot; | |
| 389 | 467 | struct bau_pq_entry *queue_first; |
| 390 | 468 | struct bau_pq_entry *queue_last; |
| 391 | 469 | }; |
| @@ -405,6 +483,7 @@ struct ptc_stats { · 13 unmodified lines | ||
| 405 | 483 | requests */ |
| 406 | 484 | unsigned long s_stimeout; /* source side timeouts */ |
| 407 | 485 | unsigned long s_dtimeout; /* destination side timeouts */ |
| 486 | + unsigned long s_strongnacks; /* number of strong nack's */ | |
| 408 | 487 | unsigned long s_time; /* time spent in sending side */ |
| 409 | 488 | unsigned long s_retriesok; /* successful retries */ |
| 410 | 489 | unsigned long s_ntargcpu; /* total number of cpu's |
| @@ -439,6 +518,9 @@ struct ptc_stats { · 28 unmodified lines | ||
| 439 | 518 | unsigned long s_retry_messages; /* retry broadcasts */ |
| 440 | 519 | unsigned long s_bau_reenabled; /* for bau enable/disable */ |
| 441 | 520 | unsigned long s_bau_disabled; /* for bau enable/disable */ |
| 521 | + unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */ | |
| 522 | + unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */ | |
| 523 | + unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */ | |
| 442 | 524 | /* destination statistics */ |
| 443 | 525 | unsigned long d_alltlb; /* times all tlb's on this |
| 444 | 526 | cpu were flushed */ |
| @@ -511,9 +593,12 @@ struct bau_control { · 66 unmodified lines | ||
| 511 | 593 | short osnode; |
| 512 | 594 | short uvhub_cpu; |
| 513 | 595 | short uvhub; |
| 596 | + short uvhub_version; | |
| 514 | 597 | short cpus_in_socket; |
| 515 | 598 | short cpus_in_uvhub; |
| 516 | 599 | short partition_base_pnode; |
| 600 | + short using_desc; /* an index, like uvhub_cpu */ | |
| 601 | + unsigned int inuse_map; | |
| 517 | 602 | unsigned short message_number; |
| 518 | 603 | unsigned short uvhub_quiesce; |
| 519 | 604 | short socket_acknowledge_count[DEST_Q_SIZE]; |
| @@ -531,6 +616,7 @@ struct bau_control { · 11 unmodified lines | ||
| 531 | 616 | int cong_response_us; |
| 532 | 617 | int cong_reps; |
| 533 | 618 | int cong_period; |
| 619 | + unsigned long clocks_per_100_usec; | |
| 534 | 620 | cycles_t period_time; |
| 535 | 621 | long period_requests; |
| 536 | 622 | struct hub_and_pnode *thp; |
| @@ -591,6 +677,11 @@ static inline void write_mmr_sw_ack(unsigned long mr) · 54 unmodified lines | ||
| 591 | 677 | uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); |
| 592 | 678 | } |
| 593 | 679 | |
| 680 | +static inline void write_gmmr_sw_ack(int pnode, unsigned long mr) | |
| 681 | +{ | |
| 682 | + write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); | |
| 683 | +} | |
| 684 | + | |
| 594 | 685 | static inline unsigned long read_mmr_sw_ack(void) |
| 595 | 686 | { |
| 596 | 687 | return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); |
| @@ -318,13 +318,13 @@ uv_gpa_in_mmr_space(unsigned long gpa) · 317 unmodified lines | ||
| 318 | 318 | /* UV global physical address --> socket phys RAM */ |
| 319 | 319 | static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) |
| 320 | 320 | { |
| 321 | − unsigned long paddr = gpa & uv_hub_info->gpa_mask; | |
| 321 | + unsigned long paddr; | |
| 322 | 322 | unsigned long remap_base = uv_hub_info->lowmem_remap_base; |
| 323 | 323 | unsigned long remap_top = uv_hub_info->lowmem_remap_top; |
| 324 | 324 | |
| 325 | 325 | gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | |
| 326 | 326 | ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); |
| 327 | − gpa = gpa & uv_hub_info->gpa_mask; | |
| 327 | + paddr = gpa & uv_hub_info->gpa_mask; | |
| 328 | 328 | if (paddr >= remap_base && paddr < remap_base + remap_top) |
| 329 | 329 | paddr -= remap_base; |
| 330 | 330 | return paddr; |
| @@ -1044,6 +1044,9 @@ DEFINE_PER_CPU(char *, irq_stack_ptr) = · 1043 unmodified lines | ||
| 1044 | 1044 | |
| 1045 | 1045 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
| 1046 | 1046 | |
| 1047 | +DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); | |
| 1048 | +EXPORT_PER_CPU_SYMBOL(fpu_owner_task); | |
| 1049 | + | |
| 1047 | 1050 | /* |
| 1048 | 1051 | * Special IST stacks which the CPU switches to when it calls |
| 1049 | 1052 | * an IST-marked descriptor entry. Up to 7 stacks (hardware |
| @@ -1111,6 +1114,8 @@ void debug_stack_reset(void) · 61 unmodified lines | ||
| 1111 | 1114 | |
| 1112 | 1115 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
| 1113 | 1116 | EXPORT_PER_CPU_SYMBOL(current_task); |
| 1117 | +DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); | |
| 1118 | +EXPORT_PER_CPU_SYMBOL(fpu_owner_task); | |
| 1114 | 1119 | |
| 1115 | 1120 | #ifdef CONFIG_CC_STACKPROTECTOR |
| 1116 | 1121 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
| @@ -439,7 +439,6 @@ void intel_pmu_pebs_enable(struct perf_event *event) · 438 unmodified lines | ||
| 439 | 439 | hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; |
| 440 | 440 | |
| 441 | 441 | cpuc->pebs_enabled |= 1ULL << hwc->idx; |
| 442 | − WARN_ON_ONCE(cpuc->enabled); | |
| 443 | 442 | |
| 444 | 443 | if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1) |
| 445 | 444 | intel_pmu_lbr_enable(event); |
| @@ -72,8 +72,6 @@ void intel_pmu_lbr_enable(struct perf_event *event) · 71 unmodified lines | ||
| 72 | 72 | if (!x86_pmu.lbr_nr) |
| 73 | 73 | return; |
| 74 | 74 | |
| 75 | − WARN_ON_ONCE(cpuc->enabled); | |
| 76 | − | |
| 77 | 75 | /* |
| 78 | 76 | * Reset the LBR stack if we changed task context to |
| 79 | 77 | * avoid data leaks. |
| @@ -252,7 +252,8 @@ int __kprobes __die(const char *str, struct pt_regs *regs, long err) · 251 unmodified lines | ||
| 252 | 252 | unsigned short ss; |
| 253 | 253 | unsigned long sp; |
| 254 | 254 | #endif |
| 255 | − printk(KERN_EMERG "%s: %04lx [#%d] ", str, err & 0xffff, ++die_counter); | |
| 255 | + printk(KERN_DEFAULT | |
| 256 | + "%s: %04lx [#%d] ", str, err & 0xffff, ++die_counter); | |
| 256 | 257 | #ifdef CONFIG_PREEMPT |
| 257 | 258 | printk("PREEMPT "); |
| 258 | 259 | #endif |
| @@ -129,7 +129,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs, · 128 unmodified lines | ||
| 129 | 129 | if (!stack) { |
| 130 | 130 | if (regs) |
| 131 | 131 | stack = (unsigned long *)regs->sp; |
| 132 | − else if (task && task != current) | |
| 132 | + else if (task != current) | |
| 133 | 133 | stack = (unsigned long *)task->thread.sp; |
| 134 | 134 | else |
| 135 | 135 | stack = &dummy; |
| @@ -269,11 +269,11 @@ void show_registers(struct pt_regs *regs) · 133 unmodified lines | ||
| 269 | 269 | unsigned char c; |
| 270 | 270 | u8 *ip; |
| 271 | 271 | |
| 272 | − printk(KERN_EMERG "Stack:\n"); | |
| 272 | + printk(KERN_DEFAULT "Stack:\n"); | |
| 273 | 273 | show_stack_log_lvl(NULL, regs, (unsigned long *)sp, |
| 274 | − 0, KERN_EMERG); | |
| 274 | + 0, KERN_DEFAULT); | |
| 275 | 275 | |
| 276 | − printk(KERN_EMERG "Code: "); | |
| 276 | + printk(KERN_DEFAULT "Code: "); | |
| 277 | 277 | |
| 278 | 278 | ip = (u8 *)regs->ip - code_prologue; |
| 279 | 279 | if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) { |
| @@ -703,7 +703,7 @@ void __init e820_mark_nosave_regions(unsigned long limit_pfn) · 702 unmodified lines | ||
| 703 | 703 | } |
| 704 | 704 | #endif |
| 705 | 705 | |
| 706 | −#ifdef CONFIG_HIBERNATION | |
| 706 | +#ifdef CONFIG_ACPI | |
| 707 | 707 | /** |
| 708 | 708 | * Mark ACPI NVS memory region, so that we can save/restore it during |
| 709 | 709 | * hibernation and the subsequent resume. |
| @@ -716,7 +716,7 @@ static int __init e820_mark_nvs_memory(void) · 6 unmodified lines | ||
| 716 | 716 | struct e820entry *ei = &e820.map[i]; |
| 717 | 717 | |
| 718 | 718 | if (ei->type == E820_NVS) |
| 719 | − suspend_nvs_register(ei->addr, ei->size); | |
| 719 | + acpi_nvs_register(ei->addr, ei->size); | |
| 720 | 720 | } |
| 721 | 721 | |
| 722 | 722 | return 0; |
| @@ -42,6 +42,7 @@ · 41 unmodified lines | ||
| 42 | 42 | */ |
| 43 | 43 | |
| 44 | 44 | #include <linux/linkage.h> |
| 45 | +#include <linux/err.h> | |
| 45 | 46 | #include <asm/thread_info.h> |
| 46 | 47 | #include <asm/irqflags.h> |
| 47 | 48 | #include <asm/errno.h> |
| @@ -453,7 +454,7 @@ sysenter_audit: · 405 unmodified lines | ||
| 453 | 454 | movl %ebx,%ecx /* 3rd arg: 1st syscall arg */ |
| 454 | 455 | movl %eax,%edx /* 2nd arg: syscall number */ |
| 455 | 456 | movl $AUDIT_ARCH_I386,%eax /* 1st arg: audit arch */ |
| 456 | − call audit_syscall_entry | |
| 457 | + call __audit_syscall_entry | |
| 457 | 458 | pushl_cfi %ebx |
| 458 | 459 | movl PT_EAX(%esp),%eax /* reload syscall number */ |
| 459 | 460 | jmp sysenter_do_call |
| @@ -464,11 +465,10 @@ sysexit_audit: · 4 unmodified lines | ||
| 464 | 465 | TRACE_IRQS_ON |
| 465 | 466 | ENABLE_INTERRUPTS(CLBR_ANY) |
| 466 | 467 | movl %eax,%edx /* second arg, syscall return value */ |
| 467 | − cmpl $0,%eax /* is it < 0? */ | |
| 468 | − setl %al /* 1 if so, 0 if not */ | |
| 468 | + cmpl $-MAX_ERRNO,%eax /* is it an error ? */ | |
| 469 | + setbe %al /* 1 if so, 0 if not */ | |
| 469 | 470 | movzbl %al,%eax /* zero-extend that */ |
| 470 | − inc %eax /* first arg, 0->1(AUDITSC_SUCCESS), 1->2(AUDITSC_FAILURE) */ | |
| 471 | − call audit_syscall_exit | |
| 471 | + call __audit_syscall_exit | |
| 472 | 472 | DISABLE_INTERRUPTS(CLBR_ANY) |
| 473 | 473 | TRACE_IRQS_OFF |
| 474 | 474 | movl TI_flags(%ebp), %ecx |
| @@ -55,6 +55,7 @@ · 54 unmodified lines | ||
| 55 | 55 | #include <asm/paravirt.h> |
| 56 | 56 | #include <asm/ftrace.h> |
| 57 | 57 | #include <asm/percpu.h> |
| 58 | +#include <linux/err.h> | |
| 58 | 59 | |
| 59 | 60 | /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */ |
| 60 | 61 | #include <linux/elf-em.h> |
| @@ -548,7 +549,7 @@ badsys: · 487 unmodified lines | ||
| 548 | 549 | #ifdef CONFIG_AUDITSYSCALL |
| 549 | 550 | /* |
| 550 | 551 | * Fast path for syscall audit without full syscall trace. |
| 551 | − * We just call audit_syscall_entry() directly, and then | |
| 552 | + * We just call __audit_syscall_entry() directly, and then | |
| 552 | 553 | * jump back to the normal fast path. |
| 553 | 554 | */ |
| 554 | 555 | auditsys: |
| @@ -558,22 +559,21 @@ auditsys: · 3 unmodified lines | ||
| 558 | 559 | movq %rdi,%rdx /* 3rd arg: 1st syscall arg */ |
| 559 | 560 | movq %rax,%rsi /* 2nd arg: syscall number */ |
| 560 | 561 | movl $AUDIT_ARCH_X86_64,%edi /* 1st arg: audit arch */ |
| 561 | − call audit_syscall_entry | |
| 562 | + call __audit_syscall_entry | |
| 562 | 563 | LOAD_ARGS 0 /* reload call-clobbered registers */ |
| 563 | 564 | jmp system_call_fastpath |
| 564 | 565 | |
| 565 | 566 | /* |
| 566 | − * Return fast path for syscall audit. Call audit_syscall_exit() | |
| 567 | + * Return fast path for syscall audit. Call __audit_syscall_exit() | |
| 567 | 568 | * directly and then jump back to the fast path with TIF_SYSCALL_AUDIT |
| 568 | 569 | * masked off. |
| 569 | 570 | */ |
| 570 | 571 | sysret_audit: |
| 571 | 572 | movq RAX-ARGOFFSET(%rsp),%rsi /* second arg, syscall return value */ |
| 572 | − cmpq $0,%rsi /* is it < 0? */ | |
| 573 | − setl %al /* 1 if so, 0 if not */ | |
| 573 | + cmpq $-MAX_ERRNO,%rsi /* is it < -MAX_ERRNO? */ | |
| 574 | + setbe %al /* 1 if so, 0 if not */ | |
| 574 | 575 | movzbl %al,%edi /* zero-extend that into %edi */ |
| 575 | − inc %edi /* first arg, 0->1(AUDITSC_SUCCESS), 1->2(AUDITSC_FAILURE) */ | |
| 576 | − call audit_syscall_exit | |
| 576 | + call __audit_syscall_exit | |
| 577 | 577 | movl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),%edi |
| 578 | 578 | jmp sysret_check |
| 579 | 579 | #endif /* CONFIG_AUDITSYSCALL */ |
| @@ -311,13 +311,33 @@ out: · 310 unmodified lines | ||
| 311 | 311 | return state; |
| 312 | 312 | } |
| 313 | 313 | |
| 314 | +/* | |
| 315 | + * AMD microcode firmware naming convention, up to family 15h they are in | |
| 316 | + * the legacy file: | |
| 317 | + * | |
| 318 | + * amd-ucode/microcode_amd.bin | |
| 319 | + * | |
| 320 | + * This legacy file is always smaller than 2K in size. | |
| 321 | + * | |
| 322 | + * Starting at family 15h they are in family specific firmware files: | |
| 323 | + * | |
| 324 | + * amd-ucode/microcode_amd_fam15h.bin | |
| 325 | + * amd-ucode/microcode_amd_fam16h.bin | |
| 326 | + * ... | |
| 327 | + * | |
| 328 | + * These might be larger than 2K. | |
| 329 | + */ | |
| 314 | 330 | static enum ucode_state request_microcode_amd(int cpu, struct device *device) |
| 315 | 331 | { |
| 316 | − const char *fw_name = "amd-ucode/microcode_amd.bin"; | |
| 332 | + char fw_name[36] = "amd-ucode/microcode_amd.bin"; | |
| 317 | 333 | const struct firmware *fw; |
| 318 | 334 | enum ucode_state ret = UCODE_NFOUND; |
| 335 | + struct cpuinfo_x86 *c = &cpu_data(cpu); | |
| 336 | + | |
| 337 | + if (c->x86 >= 0x15) | |
| 338 | + snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); | |
| 319 | 339 | |
| 320 | − if (request_firmware(&fw, fw_name, device)) { | |
| 340 | + if (request_firmware(&fw, (const char *)fw_name, device)) { | |
| 321 | 341 | pr_err("failed to load file %s\n", fw_name); |
| 322 | 342 | goto out; |
| 323 | 343 | } |
| @@ -214,6 +214,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, · 213 unmodified lines | ||
| 214 | 214 | |
| 215 | 215 | task_user_gs(p) = get_user_gs(regs); |
| 216 | 216 | |
| 217 | + p->fpu_counter = 0; | |
| 217 | 218 | p->thread.io_bitmap_ptr = NULL; |
| 218 | 219 | tsk = current; |
| 219 | 220 | err = -ENOMEM; |
| @@ -299,22 +300,11 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) · 79 unmodified lines | ||
| 299 | 300 | *next = &next_p->thread; |
| 300 | 301 | int cpu = smp_processor_id(); |
| 301 | 302 | struct tss_struct *tss = &per_cpu(init_tss, cpu); |
| 302 | − bool preload_fpu; | |
| 303 | + fpu_switch_t fpu; | |
| 303 | 304 | |
| 304 | 305 | /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */ |
| 305 | 306 | |
| 306 | − /* | |
| 307 | − * If the task has used fpu the last 5 timeslices, just do a full | |
| 308 | − * restore of the math state immediately to avoid the trap; the | |
| 309 | − * chances of needing FPU soon are obviously high now | |
| 310 | − */ | |
| 311 | − preload_fpu = tsk_used_math(next_p) && next_p->fpu_counter > 5; | |
| 312 | − | |
| 313 | − __unlazy_fpu(prev_p); | |
| 314 | − | |
| 315 | − /* we're going to use this soon, after a few expensive things */ | |
| 316 | − if (preload_fpu) | |
| 317 | − prefetch(next->fpu.state); | |
| 307 | + fpu = switch_fpu_prepare(prev_p, next_p, cpu); | |
| 318 | 308 | |
| 319 | 309 | /* |
| 320 | 310 | * Reload esp0. |
| @@ -354,11 +344,6 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) · 33 unmodified lines | ||
| 354 | 344 | task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT)) |
| 355 | 345 | __switch_to_xtra(prev_p, next_p, tss); |
| 356 | 346 | |
| 357 | − /* If we're going to preload the fpu context, make sure clts | |
| 358 | − is run while we're batching the cpu state updates. */ | |
| 359 | − if (preload_fpu) | |
| 360 | − clts(); | |
| 361 | − | |
| 362 | 347 | /* |
| 363 | 348 | * Leave lazy mode, flushing any hypercalls made here. |
| 364 | 349 | * This must be done before restoring TLS segments so |
| @@ -368,15 +353,14 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) · 3 unmodified lines | ||
| 368 | 353 | */ |
| 369 | 354 | arch_end_context_switch(next_p); |
| 370 | 355 | |
| 371 | − if (preload_fpu) | |
| 372 | − __math_state_restore(); | |
| 373 | − | |
| 374 | 356 | /* |
| 375 | 357 | * Restore %gs if needed (which is common) |
| 376 | 358 | */ |
| 377 | 359 | if (prev->gs | next->gs) |
| 378 | 360 | lazy_load_gs(next->gs); |
| 379 | 361 | |
| 362 | + switch_fpu_finish(next_p, fpu); | |
| 363 | + | |
| 380 | 364 | percpu_write(current_task, next_p); |
| 381 | 365 | |
| 382 | 366 | return prev_p; |
| @@ -286,6 +286,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, · 285 unmodified lines | ||
| 286 | 286 | |
| 287 | 287 | set_tsk_thread_flag(p, TIF_FORK); |
| 288 | 288 | |
| 289 | + p->fpu_counter = 0; | |
| 289 | 290 | p->thread.io_bitmap_ptr = NULL; |
| 290 | 291 | |
| 291 | 292 | savesegment(gs, p->thread.gsindex); |
| @@ -386,18 +387,9 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) · 94 unmodified lines | ||
| 386 | 387 | int cpu = smp_processor_id(); |
| 387 | 388 | struct tss_struct *tss = &per_cpu(init_tss, cpu); |
| 388 | 389 | unsigned fsindex, gsindex; |
| 389 | − bool preload_fpu; | |
| 390 | + fpu_switch_t fpu; | |
| 390 | 391 | |
| 391 | − /* | |
| 392 | − * If the task has used fpu the last 5 timeslices, just do a full | |
| 393 | − * restore of the math state immediately to avoid the trap; the | |
| 394 | − * chances of needing FPU soon are obviously high now | |
| 395 | − */ | |
| 396 | − preload_fpu = tsk_used_math(next_p) && next_p->fpu_counter > 5; | |
| 397 | − | |
| 398 | − /* we're going to use this soon, after a few expensive things */ | |
| 399 | − if (preload_fpu) | |
| 400 | − prefetch(next->fpu.state); | |
| 392 | + fpu = switch_fpu_prepare(prev_p, next_p, cpu); | |
| 401 | 393 | |
| 402 | 394 | /* |
| 403 | 395 | * Reload esp0, LDT and the page table pointer: |
| @@ -427,13 +419,6 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) · 23 unmodified lines | ||
| 427 | 419 | |
| 428 | 420 | load_TLS(next, cpu); |
| 429 | 421 | |
| 430 | − /* Must be after DS reload */ | |
| 431 | − __unlazy_fpu(prev_p); | |
| 432 | − | |
| 433 | − /* Make sure cpu is ready for new context */ | |
| 434 | − if (preload_fpu) | |
| 435 | − clts(); | |
| 436 | − | |
| 437 | 422 | /* |
| 438 | 423 | * Leave lazy mode, flushing any hypercalls made here. |
| 439 | 424 | * This must be done before restoring TLS segments so |
| @@ -474,6 +459,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) · 34 unmodified lines | ||
| 474 | 459 | wrmsrl(MSR_KERNEL_GS_BASE, next->gs); |
| 475 | 460 | prev->gsindex = gsindex; |
| 476 | 461 | |
| 462 | + switch_fpu_finish(next_p, fpu); | |
| 463 | + | |
| 477 | 464 | /* |
| 478 | 465 | * Switch the PDA and FPU contexts. |
| 479 | 466 | */ |
| @@ -492,13 +479,6 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) · 12 unmodified lines | ||
| 492 | 479 | task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV)) |
| 493 | 480 | __switch_to_xtra(prev_p, next_p, tss); |
| 494 | 481 | |
| 495 | − /* | |
| 496 | − * Preload the FPU context, now that we've determined that the | |
| 497 | − * task is likely to be using it. | |
| 498 | − */ | |
| 499 | − if (preload_fpu) | |
| 500 | − __math_state_restore(); | |
| 501 | − | |
| 502 | 482 | return prev_p; |
| 503 | 483 | } |
| 504 | 484 | |
| @@ -1392,20 +1392,18 @@ long syscall_trace_enter(struct pt_regs *regs) · 1391 unmodified lines | ||
| 1392 | 1392 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 1393 | 1393 | trace_sys_enter(regs, regs->orig_ax); |
| 1394 | 1394 | |
| 1395 | − if (unlikely(current->audit_context)) { | |
| 1396 | − if (IS_IA32) | |
| 1397 | − audit_syscall_entry(AUDIT_ARCH_I386, | |
| 1398 | − regs->orig_ax, | |
| 1399 | − regs->bx, regs->cx, | |
| 1400 | − regs->dx, regs->si); | |
| 1395 | + if (IS_IA32) | |
| 1396 | + audit_syscall_entry(AUDIT_ARCH_I386, | |
| 1397 | + regs->orig_ax, | |
| 1398 | + regs->bx, regs->cx, | |
| 1399 | + regs->dx, regs->si); | |
| 1401 | 1400 | #ifdef CONFIG_X86_64 |
| 1402 | − else | |
| 1403 | − audit_syscall_entry(AUDIT_ARCH_X86_64, | |
| 1404 | − regs->orig_ax, | |
| 1405 | − regs->di, regs->si, | |
| 1406 | − regs->dx, regs->r10); | |
| 1401 | + else | |
| 1402 | + audit_syscall_entry(AUDIT_ARCH_X86_64, | |
| 1403 | + regs->orig_ax, | |
| 1404 | + regs->di, regs->si, | |
| 1405 | + regs->dx, regs->r10); | |
| 1407 | 1406 | #endif |
| 1408 | − } | |
| 1409 | 1407 | |
| 1410 | 1408 | return ret ?: regs->orig_ax; |
| 1411 | 1409 | } |
| @@ -1414,8 +1412,7 @@ void syscall_trace_leave(struct pt_regs *regs) · 2 unmodified lines | ||
| 1414 | 1412 | { |
| 1415 | 1413 | bool step; |
| 1416 | 1414 | |
| 1417 | − if (unlikely(current->audit_context)) | |
| 1418 | − audit_syscall_exit(AUDITSC_RESULT(regs->ax), regs->ax); | |
| 1415 | + audit_syscall_exit(regs); | |
| 1419 | 1416 | |
| 1420 | 1417 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
| 1421 | 1418 | trace_sys_exit(regs, regs->ax); |
| @@ -39,6 +39,14 @@ static int reboot_mode; · 38 unmodified lines | ||
| 39 | 39 | enum reboot_type reboot_type = BOOT_ACPI; |
| 40 | 40 | int reboot_force; |
| 41 | 41 | |
| 42 | +/* This variable is used privately to keep track of whether or not | |
| 43 | + * reboot_type is still set to its default value (i.e., reboot= hasn't | |
| 44 | + * been set on the command line). This is needed so that we can | |
| 45 | + * suppress DMI scanning for reboot quirks. Without it, it's | |
| 46 | + * impossible to override a faulty reboot quirk without recompiling. | |
| 47 | + */ | |
| 48 | +static int reboot_default = 1; | |
| 49 | + | |
| 42 | 50 | #if defined(CONFIG_X86_32) && defined(CONFIG_SMP) |
| 43 | 51 | static int reboot_cpu = -1; |
| 44 | 52 | #endif |
| @@ -67,6 +75,12 @@ bool port_cf9_safe = false; · 22 unmodified lines | ||
| 67 | 75 | static int __init reboot_setup(char *str) |
| 68 | 76 | { |
| 69 | 77 | for (;;) { |
| 78 | + /* Having anything passed on the command line via | |
| 79 | + * reboot= will cause us to disable DMI checking | |
| 80 | + * below. | |
| 81 | + */ | |
| 82 | + reboot_default = 0; | |
| 83 | + | |
| 70 | 84 | switch (*str) { |
| 71 | 85 | case 'w': |
| 72 | 86 | reboot_mode = 0x1234; |
| @@ -295,14 +309,6 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { · 222 unmodified lines | ||
| 295 | 309 | DMI_MATCH(DMI_BOARD_NAME, "P4S800"), |
| 296 | 310 | }, |
| 297 | 311 | }, |
| 298 | − { /* Handle problems with rebooting on VersaLogic Menlow boards */ | |
| 299 | − .callback = set_bios_reboot, | |
| 300 | − .ident = "VersaLogic Menlow based board", | |
| 301 | − .matches = { | |
| 302 | − DMI_MATCH(DMI_BOARD_VENDOR, "VersaLogic Corporation"), | |
| 303 | − DMI_MATCH(DMI_BOARD_NAME, "VersaLogic Menlow board"), | |
| 304 | − }, | |
| 305 | − }, | |
| 306 | 312 | { /* Handle reboot issue on Acer Aspire one */ |
| 307 | 313 | .callback = set_kbd_reboot, |
| 308 | 314 | .ident = "Acer Aspire One A110", |
| @@ -316,7 +322,12 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { · 7 unmodified lines | ||
| 316 | 322 | |
| 317 | 323 | static int __init reboot_init(void) |
| 318 | 324 | { |
| 319 | − dmi_check_system(reboot_dmi_table); | |
| 325 | + /* Only do the DMI check if reboot_type hasn't been overridden | |
| 326 | + * on the command line | |
| 327 | + */ | |
| 328 | + if (reboot_default) { | |
| 329 | + dmi_check_system(reboot_dmi_table); | |
| 330 | + } | |
| 320 | 331 | return 0; |
| 321 | 332 | } |
| 322 | 333 | core_initcall(reboot_init); |
| @@ -465,7 +476,12 @@ static struct dmi_system_id __initdata pci_reboot_dmi_table[] = { · 142 unmodified lines | ||
| 465 | 476 | |
| 466 | 477 | static int __init pci_reboot_init(void) |
| 467 | 478 | { |
| 468 | − dmi_check_system(pci_reboot_dmi_table); | |
| 479 | + /* Only do the DMI check if reboot_type hasn't been overridden | |
| 480 | + * on the command line | |
| 481 | + */ | |
| 482 | + if (reboot_default) { | |
| 483 | + dmi_check_system(pci_reboot_dmi_table); | |
| 484 | + } | |
| 469 | 485 | return 0; |
| 470 | 486 | } |
| 471 | 487 | core_initcall(pci_reboot_init); |
| @@ -570,28 +570,6 @@ asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void) · 569 unmodified lines | ||
| 570 | 570 | { |
| 571 | 571 | } |
| 572 | 572 | |
| 573 | −/* | |
| 574 | − * __math_state_restore assumes that cr0.TS is already clear and the | |
| 575 | − * fpu state is all ready for use. Used during context switch. | |
| 576 | − */ | |
| 577 | −void __math_state_restore(void) | |
| 578 | −{ | |
| 579 | − struct thread_info *thread = current_thread_info(); | |
| 580 | − struct task_struct *tsk = thread->task; | |
| 581 | − | |
| 582 | − /* | |
| 583 | − * Paranoid restore. send a SIGSEGV if we fail to restore the state. | |
| 584 | − */ | |
| 585 | − if (unlikely(restore_fpu_checking(tsk))) { | |
| 586 | − stts(); | |
| 587 | − force_sig(SIGSEGV, tsk); | |
| 588 | − return; | |
| 589 | − } | |
| 590 | − | |
| 591 | − thread->status |= TS_USEDFPU; /* So we fnsave on switch_to() */ | |
| 592 | − tsk->fpu_counter++; | |
| 593 | −} | |
| 594 | − | |
| 595 | 573 | /* |
| 596 | 574 | * 'math_state_restore()' saves the current math information in the |
| 597 | 575 | * old math state array, and gets the new ones from the current task |
| @@ -599,13 +577,12 @@ void __math_state_restore(void) · 1 unmodified line | ||
| 599 | 577 | * Careful.. There are problems with IBM-designed IRQ13 behaviour. |
| 600 | 578 | * Don't touch unless you *really* know how it works. |
| 601 | 579 | * |
| 602 | − * Must be called with kernel preemption disabled (in this case, | |
| 603 | − * local interrupts are disabled at the call-site in entry.S). | |
| 580 | + * Must be called with kernel preemption disabled (eg with local | |
| 581 | + * local interrupts as in the case of do_device_not_available). | |
| 604 | 582 | */ |
| 605 | −asmlinkage void math_state_restore(void) | |
| 583 | +void math_state_restore(void) | |
| 606 | 584 | { |
| 607 | − struct thread_info *thread = current_thread_info(); | |
| 608 | − struct task_struct *tsk = thread->task; | |
| 585 | + struct task_struct *tsk = current; | |
| 609 | 586 | |
| 610 | 587 | if (!tsk_used_math(tsk)) { |
| 611 | 588 | local_irq_enable(); |
| @@ -622,9 +599,17 @@ asmlinkage void math_state_restore(void) · 10 unmodified lines | ||
| 622 | 599 | local_irq_disable(); |
| 623 | 600 | } |
| 624 | 601 | |
| 625 | − clts(); /* Allow maths ops (or we recurse) */ | |
| 602 | + __thread_fpu_begin(tsk); | |
| 603 | + /* | |
| 604 | + * Paranoid restore. send a SIGSEGV if we fail to restore the state. | |
| 605 | + */ | |
| 606 | + if (unlikely(restore_fpu_checking(tsk))) { | |
| 607 | + __thread_fpu_end(tsk); | |
| 608 | + force_sig(SIGSEGV, tsk); | |
| 609 | + return; | |
| 610 | + } | |
| 626 | 611 | |
| 627 | − __math_state_restore(); | |
| 612 | + tsk->fpu_counter++; | |
| 628 | 613 | } |
| 629 | 614 | EXPORT_SYMBOL_GPL(math_state_restore); |
| 630 | 615 | |
| @@ -290,14 +290,15 @@ static inline int pit_verify_msb(unsigned char val) · 289 unmodified lines | ||
| 290 | 290 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
| 291 | 291 | { |
| 292 | 292 | int count; |
| 293 | − u64 tsc = 0; | |
| 293 | + u64 tsc = 0, prev_tsc = 0; | |
| 294 | 294 | |
| 295 | 295 | for (count = 0; count < 50000; count++) { |
| 296 | 296 | if (!pit_verify_msb(val)) |
| 297 | 297 | break; |
| 298 | + prev_tsc = tsc; | |
| 298 | 299 | tsc = get_cycles(); |
| 299 | 300 | } |
| 300 | − *deltap = get_cycles() - tsc; | |
| 301 | + *deltap = get_cycles() - prev_tsc; | |
| 301 | 302 | *tscp = tsc; |
| 302 | 303 | |
| 303 | 304 | /* |
| @@ -311,9 +312,9 @@ static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *de · 7 unmodified lines | ||
| 311 | 312 | * How many MSB values do we want to see? We aim for |
| 312 | 313 | * a maximum error rate of 500ppm (in practice the |
| 313 | 314 | * real error is much smaller), but refuse to spend |
| 314 | − * more than 25ms on it. | |
| 315 | + * more than 50ms on it. | |
| 315 | 316 | */ |
| 316 | −#define MAX_QUICK_PIT_MS 25 | |
| 317 | +#define MAX_QUICK_PIT_MS 50 | |
| 317 | 318 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
| 318 | 319 | |
| 319 | 320 | static unsigned long quick_pit_calibrate(void) |
| @@ -383,15 +384,12 @@ success: · 63 unmodified lines | ||
| 383 | 384 | * |
| 384 | 385 | * As a result, we can depend on there not being |
| 385 | 386 | * any odd delays anywhere, and the TSC reads are |
| 386 | − * reliable (within the error). We also adjust the | |
| 387 | − * delta to the middle of the error bars, just | |
| 388 | − * because it looks nicer. | |
| 387 | + * reliable (within the error). | |
| 389 | 388 | * |
| 390 | 389 | * kHz = ticks / time-in-seconds / 1000; |
| 391 | 390 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 |
| 392 | 391 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) |
| 393 | 392 | */ |
| 394 | − delta += (long)(d2 - d1)/2; | |
| 395 | 393 | delta *= PIT_TICK_RATE; |
| 396 | 394 | do_div(delta, i*256*1000); |
| 397 | 395 | printk("Fast TSC calibration using PIT\n"); |
| @@ -335,9 +335,11 @@ static void do_sys_vm86(struct kernel_vm86_struct *info, struct task_struct *tsk · 334 unmodified lines | ||
| 335 | 335 | if (info->flags & VM86_SCREEN_BITMAP) |
| 336 | 336 | mark_screen_rdonly(tsk->mm); |
| 337 | 337 | |
| 338 | − /*call audit_syscall_exit since we do not exit via the normal paths */ | |
| 338 | + /*call __audit_syscall_exit since we do not exit via the normal paths */ | |
| 339 | +#ifdef CONFIG_AUDITSYSCALL | |
| 339 | 340 | if (unlikely(current->audit_context)) |
| 340 | − audit_syscall_exit(AUDITSC_RESULT(0), 0); | |
| 341 | + __audit_syscall_exit(1, 0); | |
| 342 | +#endif | |
| 341 | 343 | |
| 342 | 344 | __asm__ __volatile__( |
| 343 | 345 | "movl %0,%%esp\n\t" |
| @@ -47,7 +47,7 @@ void __sanitize_i387_state(struct task_struct *tsk) · 46 unmodified lines | ||
| 47 | 47 | if (!fx) |
| 48 | 48 | return; |
| 49 | 49 | |
| 50 | − BUG_ON(task_thread_info(tsk)->status & TS_USEDFPU); | |
| 50 | + BUG_ON(__thread_has_fpu(tsk)); | |
| 51 | 51 | |
| 52 | 52 | xstate_bv = tsk->thread.fpu.state->xsave.xsave_hdr.xstate_bv; |
| 53 | 53 | |
| @@ -168,7 +168,7 @@ int save_i387_xstate(void __user *buf) · 114 unmodified lines | ||
| 168 | 168 | if (!used_math()) |
| 169 | 169 | return 0; |
| 170 | 170 | |
| 171 | − if (task_thread_info(tsk)->status & TS_USEDFPU) { | |
| 171 | + if (user_has_fpu()) { | |
| 172 | 172 | if (use_xsave()) |
| 173 | 173 | err = xsave_user(buf); |
| 174 | 174 | else |
| @@ -176,8 +176,7 @@ int save_i387_xstate(void __user *buf) · 1 unmodified line | ||
| 176 | 176 | |
| 177 | 177 | if (err) |
| 178 | 178 | return err; |
| 179 | − task_thread_info(tsk)->status &= ~TS_USEDFPU; | |
| 180 | − stts(); | |
| 179 | + user_fpu_end(); | |
| 181 | 180 | } else { |
| 182 | 181 | sanitize_i387_state(tsk); |
| 183 | 182 | if (__copy_to_user(buf, &tsk->thread.fpu.state->fxsave, |
| @@ -292,10 +291,7 @@ int restore_i387_xstate(void __user *buf) · 108 unmodified lines | ||
| 292 | 291 | return err; |
| 293 | 292 | } |
| 294 | 293 | |
| 295 | − if (!(task_thread_info(current)->status & TS_USEDFPU)) { | |
| 296 | − clts(); | |
| 297 | − task_thread_info(current)->status |= TS_USEDFPU; | |
| 298 | − } | |
| 294 | + user_fpu_begin(); | |
| 299 | 295 | if (use_xsave()) |
| 300 | 296 | err = restore_user_xstate(buf); |
| 301 | 297 | else |
| @@ -1891,6 +1891,51 @@ setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, · 1890 unmodified lines | ||
| 1891 | 1891 | ss->p = 1; |
| 1892 | 1892 | } |
| 1893 | 1893 | |
| 1894 | +static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) | |
| 1895 | +{ | |
| 1896 | + struct x86_emulate_ops *ops = ctxt->ops; | |
| 1897 | + u32 eax, ebx, ecx, edx; | |
| 1898 | + | |
| 1899 | + /* | |
| 1900 | + * syscall should always be enabled in longmode - so only become | |
| 1901 | + * vendor specific (cpuid) if other modes are active... | |
| 1902 | + */ | |
| 1903 | + if (ctxt->mode == X86EMUL_MODE_PROT64) | |
| 1904 | + return true; | |
| 1905 | + | |
| 1906 | + eax = 0x00000000; | |
| 1907 | + ecx = 0x00000000; | |
| 1908 | + if (ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)) { | |
| 1909 | + /* | |
| 1910 | + * Intel ("GenuineIntel") | |
| 1911 | + * remark: Intel CPUs only support "syscall" in 64bit | |
| 1912 | + * longmode. Also an 64bit guest with a | |
| 1913 | + * 32bit compat-app running will #UD !! While this | |
| 1914 | + * behaviour can be fixed (by emulating) into AMD | |
| 1915 | + * response - CPUs of AMD can't behave like Intel. | |
| 1916 | + */ | |
| 1917 | + if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && | |
| 1918 | + ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && | |
| 1919 | + edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) | |
| 1920 | + return false; | |
| 1921 | + | |
| 1922 | + /* AMD ("AuthenticAMD") */ | |
| 1923 | + if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && | |
| 1924 | + ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && | |
| 1925 | + edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) | |
| 1926 | + return true; | |
| 1927 | + | |
| 1928 | + /* AMD ("AMDisbetter!") */ | |
| 1929 | + if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && | |
| 1930 | + ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && | |
| 1931 | + edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) | |
| 1932 | + return true; | |
| 1933 | + } | |
| 1934 | + | |
| 1935 | + /* default: (not Intel, not AMD), apply Intel's stricter rules... */ | |
| 1936 | + return false; | |
| 1937 | +} | |
| 1938 | + | |
| 1894 | 1939 | static int em_syscall(struct x86_emulate_ctxt *ctxt) |
| 1895 | 1940 | { |
| 1896 | 1941 | struct x86_emulate_ops *ops = ctxt->ops; |
| @@ -1904,9 +1949,15 @@ static int em_syscall(struct x86_emulate_ctxt *ctxt) · 7 unmodified lines | ||
| 1904 | 1949 | ctxt->mode == X86EMUL_MODE_VM86) |
| 1905 | 1950 | return emulate_ud(ctxt); |
| 1906 | 1951 | |
| 1952 | + if (!(em_syscall_is_enabled(ctxt))) | |
| 1953 | + return emulate_ud(ctxt); | |
| 1954 | + | |
| 1907 | 1955 | ops->get_msr(ctxt, MSR_EFER, &efer); |
| 1908 | 1956 | setup_syscalls_segments(ctxt, &cs, &ss); |
| 1909 | 1957 | |
| 1958 | + if (!(efer & EFER_SCE)) | |
| 1959 | + return emulate_ud(ctxt); | |
| 1960 | + | |
| 1910 | 1961 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
| 1911 | 1962 | msr_data >>= 32; |
| 1912 | 1963 | cs_sel = (u16)(msr_data & 0xfffc); |
| @@ -1457,7 +1457,7 @@ static void __vmx_load_host_state(struct vcpu_vmx *vmx) · 1456 unmodified lines | ||
| 1457 | 1457 | #ifdef CONFIG_X86_64 |
| 1458 | 1458 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
| 1459 | 1459 | #endif |
| 1460 | − if (current_thread_info()->status & TS_USEDFPU) | |
| 1460 | + if (__thread_has_fpu(current)) | |
| 1461 | 1461 | clts(); |
| 1462 | 1462 | load_gdt(&__get_cpu_var(host_gdt)); |
| 1463 | 1463 | } |
| @@ -1495,6 +1495,8 @@ static void record_steal_time(struct kvm_vcpu *vcpu) · 1494 unmodified lines | ||
| 1495 | 1495 | |
| 1496 | 1496 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
| 1497 | 1497 | { |
| 1498 | + bool pr = false; | |
| 1499 | + | |
| 1498 | 1500 | switch (msr) { |
| 1499 | 1501 | case MSR_EFER: |
| 1500 | 1502 | return set_efer(vcpu, data); |
| @@ -1635,6 +1637,18 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) · 134 unmodified lines | ||
| 1635 | 1637 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
| 1636 | 1638 | "0x%x data 0x%llx\n", msr, data); |
| 1637 | 1639 | break; |
| 1640 | + case MSR_P6_PERFCTR0: | |
| 1641 | + case MSR_P6_PERFCTR1: | |
| 1642 | + pr = true; | |
| 1643 | + case MSR_P6_EVNTSEL0: | |
| 1644 | + case MSR_P6_EVNTSEL1: | |
| 1645 | + if (kvm_pmu_msr(vcpu, msr)) | |
| 1646 | + return kvm_pmu_set_msr(vcpu, msr, data); | |
| 1647 | + | |
| 1648 | + if (pr || data != 0) | |
| 1649 | + pr_unimpl(vcpu, "disabled perfctr wrmsr: " | |
| 1650 | + "0x%x data 0x%llx\n", msr, data); | |
| 1651 | + break; | |
| 1638 | 1652 | case MSR_K7_CLK_CTL: |
| 1639 | 1653 | /* |
| 1640 | 1654 | * Ignore all writes to this no longer documented MSR. |
| @@ -1835,6 +1849,14 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) · 194 unmodified lines | ||
| 1835 | 1849 | case MSR_FAM10H_MMIO_CONF_BASE: |
| 1836 | 1850 | data = 0; |
| 1837 | 1851 | break; |
| 1852 | + case MSR_P6_PERFCTR0: | |
| 1853 | + case MSR_P6_PERFCTR1: | |
| 1854 | + case MSR_P6_EVNTSEL0: | |
| 1855 | + case MSR_P6_EVNTSEL1: | |
| 1856 | + if (kvm_pmu_msr(vcpu, msr)) | |
| 1857 | + return kvm_pmu_get_msr(vcpu, msr, pdata); | |
| 1858 | + data = 0; | |
| 1859 | + break; | |
| 1838 | 1860 | case MSR_IA32_UCODE_REV: |
| 1839 | 1861 | data = 0x100000000ULL; |
| 1840 | 1862 | break; |
| @@ -4180,6 +4202,28 @@ static int emulator_intercept(struct x86_emulate_ctxt *ctxt, · 2339 unmodified lines | ||
| 4180 | 4202 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
| 4181 | 4203 | } |
| 4182 | 4204 | |
| 4205 | +static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, | |
| 4206 | + u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) | |
| 4207 | +{ | |
| 4208 | + struct kvm_cpuid_entry2 *cpuid = NULL; | |
| 4209 | + | |
| 4210 | + if (eax && ecx) | |
| 4211 | + cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt), | |
| 4212 | + *eax, *ecx); | |
| 4213 | + | |
| 4214 | + if (cpuid) { | |
| 4215 | + *eax = cpuid->eax; | |
| 4216 | + *ecx = cpuid->ecx; | |
| 4217 | + if (ebx) | |
| 4218 | + *ebx = cpuid->ebx; | |
| 4219 | + if (edx) | |
| 4220 | + *edx = cpuid->edx; | |
| 4221 | + return true; | |
| 4222 | + } | |
| 4223 | + | |
| 4224 | + return false; | |
| 4225 | +} | |
| 4226 | + | |
| 4183 | 4227 | static struct x86_emulate_ops emulate_ops = { |
| 4184 | 4228 | .read_std = kvm_read_guest_virt_system, |
| 4185 | 4229 | .write_std = kvm_write_guest_virt_system, |
| @@ -4211,6 +4255,7 @@ static struct x86_emulate_ops emulate_ops = { · 25 unmodified lines | ||
| 4211 | 4255 | .get_fpu = emulator_get_fpu, |
| 4212 | 4256 | .put_fpu = emulator_put_fpu, |
| 4213 | 4257 | .intercept = emulator_intercept, |
| 4258 | + .get_cpuid = emulator_get_cpuid, | |
| 4214 | 4259 | }; |
| 4215 | 4260 | |
| 4216 | 4261 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
| @@ -219,7 +219,9 @@ ab: STOS/W/D/Q Yv,rAX · 218 unmodified lines | ||
| 219 | 219 | ac: LODS/B AL,Xb |
| 220 | 220 | ad: LODS/W/D/Q rAX,Xv |
| 221 | 221 | ae: SCAS/B AL,Yb |
| 222 | −af: SCAS/W/D/Q rAX,Xv | |
| 222 | +# Note: The May 2011 Intel manual shows Xv for the second parameter of the | |
| 223 | +# next instruction but Yv is correct | |
| 224 | +af: SCAS/W/D/Q rAX,Yv | |
| 223 | 225 | # 0xb0 - 0xbf |
| 224 | 226 | b0: MOV AL/R8L,Ib |
| 225 | 227 | b1: MOV CL/R9L,Ib |
| @@ -729,8 +731,8 @@ de: VAESDEC Vdq,Hdq,Wdq (66),(v1) · 503 unmodified lines | ||
| 729 | 731 | df: VAESDECLAST Vdq,Hdq,Wdq (66),(v1) |
| 730 | 732 | f0: MOVBE Gy,My | MOVBE Gw,Mw (66) | CRC32 Gd,Eb (F2) |
| 731 | 733 | f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) |
| 732 | −f3: ANDN Gy,By,Ey (v) | |
| 733 | −f4: Grp17 (1A) | |
| 734 | +f2: ANDN Gy,By,Ey (v) | |
| 735 | +f3: Grp17 (1A) | |
| 734 | 736 | f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) |
| 735 | 737 | f6: MULX By,Gy,rDX,Ey (F2),(v) |
| 736 | 738 | f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v) |
| @@ -673,7 +673,7 @@ no_context(struct pt_regs *regs, unsigned long error_code, · 672 unmodified lines | ||
| 673 | 673 | |
| 674 | 674 | stackend = end_of_stack(tsk); |
| 675 | 675 | if (tsk != &init_task && *stackend != STACK_END_MAGIC) |
| 676 | − printk(KERN_ALERT "Thread overran stack, or stack corrupted\n"); | |
| 676 | + printk(KERN_EMERG "Thread overran stack, or stack corrupted\n"); | |
| 677 | 677 | |
| 678 | 678 | tsk->thread.cr2 = address; |
| 679 | 679 | tsk->thread.trap_no = 14; |
| @@ -684,7 +684,7 @@ no_context(struct pt_regs *regs, unsigned long error_code, · 4 unmodified lines | ||
| 684 | 684 | sig = 0; |
| 685 | 685 | |
| 686 | 686 | /* Executive summary in case the body of the oops scrolled away */ |
| 687 | − printk(KERN_EMERG "CR2: %016lx\n", address); | |
| 687 | + printk(KERN_DEFAULT "CR2: %016lx\n", address); | |
| 688 | 688 | |
| 689 | 689 | oops_end(flags, regs, sig); |
| 690 | 690 | } |
| @@ -109,6 +109,8 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *pa) · 108 unmodified lines | ||
| 109 | 109 | if ((pa->flags & ACPI_SRAT_CPU_ENABLED) == 0) |
| 110 | 110 | return; |
| 111 | 111 | pxm = pa->proximity_domain_lo; |
| 112 | + if (acpi_srat_revision >= 2) | |
| 113 | + pxm |= *((unsigned int*)pa->proximity_domain_hi) << 8; | |
| 112 | 114 | node = setup_node(pxm); |
| 113 | 115 | if (node < 0) { |
| 114 | 116 | printk(KERN_ERR "SRAT: Too many proximity domains %x\n", pxm); |
| @@ -160,6 +162,8 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma) · 45 unmodified lines | ||
| 160 | 162 | start = ma->base_address; |
| 161 | 163 | end = start + ma->length; |
| 162 | 164 | pxm = ma->proximity_domain; |
| 165 | + if (acpi_srat_revision <= 1) | |
| 166 | + pxm &= 0xff; | |
| 163 | 167 | node = setup_node(pxm); |
| 164 | 168 | if (node < 0) { |
| 165 | 169 | printk(KERN_ERR "SRAT: Too many proximity domains.\n"); |
| @@ -151,17 +151,18 @@ void bpf_jit_compile(struct sk_filter *fp) · 150 unmodified lines | ||
| 151 | 151 | cleanup_addr = proglen; /* epilogue address */ |
| 152 | 152 | |
| 153 | 153 | for (pass = 0; pass < 10; pass++) { |
| 154 | + u8 seen_or_pass0 = (pass == 0) ? (SEEN_XREG | SEEN_DATAREF | SEEN_MEM) : seen; | |
| 154 | 155 | /* no prologue/epilogue for trivial filters (RET something) */ |
| 155 | 156 | proglen = 0; |
| 156 | 157 | prog = temp; |
| 157 | 158 | |
| 158 | − if (seen) { | |
| 159 | + if (seen_or_pass0) { | |
| 159 | 160 | EMIT4(0x55, 0x48, 0x89, 0xe5); /* push %rbp; mov %rsp,%rbp */ |
| 160 | 161 | EMIT4(0x48, 0x83, 0xec, 96); /* subq $96,%rsp */ |
| 161 | 162 | /* note : must save %rbx in case bpf_error is hit */ |
| 162 | − if (seen & (SEEN_XREG | SEEN_DATAREF)) | |
| 163 | + if (seen_or_pass0 & (SEEN_XREG | SEEN_DATAREF)) | |
| 163 | 164 | EMIT4(0x48, 0x89, 0x5d, 0xf8); /* mov %rbx, -8(%rbp) */ |
| 164 | − if (seen & SEEN_XREG) | |
| 165 | + if (seen_or_pass0 & SEEN_XREG) | |
| 165 | 166 | CLEAR_X(); /* make sure we dont leek kernel memory */ |
| 166 | 167 | |
| 167 | 168 | /* |
| @@ -170,7 +171,7 @@ void bpf_jit_compile(struct sk_filter *fp) · 2 unmodified lines | ||
| 170 | 171 | * r9 = skb->len - skb->data_len |
| 171 | 172 | * r8 = skb->data |
| 172 | 173 | */ |
| 173 | − if (seen & SEEN_DATAREF) { | |
| 174 | + if (seen_or_pass0 & SEEN_DATAREF) { | |
| 174 | 175 | if (offsetof(struct sk_buff, len) <= 127) |
| 175 | 176 | /* mov off8(%rdi),%r9d */ |
| 176 | 177 | EMIT4(0x44, 0x8b, 0x4f, offsetof(struct sk_buff, len)); |
| @@ -260,9 +261,14 @@ void bpf_jit_compile(struct sk_filter *fp) · 83 unmodified lines | ||
| 260 | 261 | case BPF_S_ALU_DIV_X: /* A /= X; */ |
| 261 | 262 | seen |= SEEN_XREG; |
| 262 | 263 | EMIT2(0x85, 0xdb); /* test %ebx,%ebx */ |
| 263 | − if (pc_ret0 != -1) | |
| 264 | − EMIT_COND_JMP(X86_JE, addrs[pc_ret0] - (addrs[i] - 4)); | |
| 265 | − else { | |
| 264 | + if (pc_ret0 > 0) { | |
| 265 | + /* addrs[pc_ret0 - 1] is start address of target | |
| 266 | + * (addrs[i] - 4) is the address following this jmp | |
| 267 | + * ("xor %edx,%edx; div %ebx" being 4 bytes long) | |
| 268 | + */ | |
| 269 | + EMIT_COND_JMP(X86_JE, addrs[pc_ret0 - 1] - | |
| 270 | + (addrs[i] - 4)); | |
| 271 | + } else { | |
| 266 | 272 | EMIT_COND_JMP(X86_JNE, 2 + 5); |
| 267 | 273 | CLEAR_A(); |
| 268 | 274 | EMIT1_off32(0xe9, cleanup_addr - (addrs[i] - 4)); /* jmp .+off32 */ |
| @@ -335,12 +341,12 @@ void bpf_jit_compile(struct sk_filter *fp) · 66 unmodified lines | ||
| 335 | 341 | } |
| 336 | 342 | /* fallinto */ |
| 337 | 343 | case BPF_S_RET_A: |
| 338 | − if (seen) { | |
| 344 | + if (seen_or_pass0) { | |
| 339 | 345 | if (i != flen - 1) { |
| 340 | 346 | EMIT_JMP(cleanup_addr - addrs[i]); |
| 341 | 347 | break; |
| 342 | 348 | } |
| 343 | − if (seen & SEEN_XREG) | |
| 349 | + if (seen_or_pass0 & SEEN_XREG) | |
| 344 | 350 | EMIT4(0x48, 0x8b, 0x5d, 0xf8); /* mov -8(%rbp),%rbx */ |
| 345 | 351 | EMIT1(0xc9); /* leaveq */ |
| 346 | 352 | } |
| @@ -483,8 +489,9 @@ common_load: seen |= SEEN_DATAREF; · 136 unmodified lines | ||
| 483 | 489 | goto common_load; |
| 484 | 490 | case BPF_S_LDX_B_MSH: |
| 485 | 491 | if ((int)K < 0) { |
| 486 | − if (pc_ret0 != -1) { | |
| 487 | − EMIT_JMP(addrs[pc_ret0] - addrs[i]); | |
| 492 | + if (pc_ret0 > 0) { | |
| 493 | + /* addrs[pc_ret0 - 1] is the start address */ | |
| 494 | + EMIT_JMP(addrs[pc_ret0 - 1] - addrs[i]); | |
| 488 | 495 | break; |
| 489 | 496 | } |
| 490 | 497 | CLEAR_A(); |
| @@ -599,13 +606,14 @@ cond_branch: f_offset = addrs[i + filter[i].jf] - addrs[i]; · 108 unmodified lines | ||
| 599 | 606 | * use it to give the cleanup instruction(s) addr |
| 600 | 607 | */ |
| 601 | 608 | cleanup_addr = proglen - 1; /* ret */ |
| 602 | − if (seen) | |
| 609 | + if (seen_or_pass0) | |
| 603 | 610 | cleanup_addr -= 1; /* leaveq */ |
| 604 | − if (seen & SEEN_XREG) | |
| 611 | + if (seen_or_pass0 & SEEN_XREG) | |
| 605 | 612 | cleanup_addr -= 4; /* mov -8(%rbp),%rbx */ |
| 606 | 613 | |
| 607 | 614 | if (image) { |
| 608 | − WARN_ON(proglen != oldproglen); | |
| 615 | + if (proglen != oldproglen) | |
| 616 | + pr_err("bpb_jit_compile proglen=%u != oldproglen=%u\n", proglen, oldproglen); | |
| 609 | 617 | break; |
| 610 | 618 | } |
| 611 | 619 | if (proglen == oldproglen) { |
| @@ -374,7 +374,7 @@ int __init pci_xen_init(void) · 373 unmodified lines | ||
| 374 | 374 | |
| 375 | 375 | int __init pci_xen_hvm_init(void) |
| 376 | 376 | { |
| 377 | − if (!xen_feature(XENFEAT_hvm_pirqs)) | |
| 377 | + if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs)) | |
| 378 | 378 | return 0; |
| 379 | 379 | |
| 380 | 380 | #ifdef CONFIG_ACPI |
| @@ -157,13 +157,14 @@ static int __init uvhub_to_first_apicid(int uvhub) · 156 unmodified lines | ||
| 157 | 157 | * clear of the Timeout bit (as well) will free the resource. No reply will |
| 158 | 158 | * be sent (the hardware will only do one reply per message). |
| 159 | 159 | */ |
| 160 | −static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp) | |
| 160 | +static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp, | |
| 161 | + int do_acknowledge) | |
| 161 | 162 | { |
| 162 | 163 | unsigned long dw; |
| 163 | 164 | struct bau_pq_entry *msg; |
| 164 | 165 | |
| 165 | 166 | msg = mdp->msg; |
| 166 | − if (!msg->canceled) { | |
| 167 | + if (!msg->canceled && do_acknowledge) { | |
| 167 | 168 | dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec; |
| 168 | 169 | write_mmr_sw_ack(dw); |
| 169 | 170 | } |
| @@ -212,8 +213,8 @@ static void bau_process_retry_msg(struct msg_desc *mdp, · 42 unmodified lines | ||
| 212 | 213 | if (mmr & (msg_res << UV_SW_ACK_NPENDING)) { |
| 213 | 214 | unsigned long mr; |
| 214 | 215 | /* |
| 215 | − * is the resource timed out? | |
| 216 | − * make everyone ignore the cancelled message. | |
| 216 | + * Is the resource timed out? | |
| 217 | + * Make everyone ignore the cancelled message. | |
| 217 | 218 | */ |
| 218 | 219 | msg2->canceled = 1; |
| 219 | 220 | stat->d_canceled++; |
| @@ -231,8 +232,8 @@ static void bau_process_retry_msg(struct msg_desc *mdp, · 11 unmodified lines | ||
| 231 | 232 | * Do all the things a cpu should do for a TLB shootdown message. |
| 232 | 233 | * Other cpu's may come here at the same time for this message. |
| 233 | 234 | */ |
| 234 | −static void bau_process_message(struct msg_desc *mdp, | |
| 235 | − struct bau_control *bcp) | |
| 235 | +static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp, | |
| 236 | + int do_acknowledge) | |
| 236 | 237 | { |
| 237 | 238 | short socket_ack_count = 0; |
| 238 | 239 | short *sp; |
| @@ -284,8 +285,9 @@ static void bau_process_message(struct msg_desc *mdp, · 45 unmodified lines | ||
| 284 | 285 | if (msg_ack_count == bcp->cpus_in_uvhub) { |
| 285 | 286 | /* |
| 286 | 287 | * All cpus in uvhub saw it; reply |
| 288 | + * (unless we are in the UV2 workaround) | |
| 287 | 289 | */ |
| 288 | − reply_to_message(mdp, bcp); | |
| 290 | + reply_to_message(mdp, bcp, do_acknowledge); | |
| 289 | 291 | } |
| 290 | 292 | } |
| 291 | 293 | |
| @@ -491,27 +493,138 @@ static int uv1_wait_completion(struct bau_desc *bau_desc, · 199 unmodified lines | ||
| 491 | 493 | /* |
| 492 | 494 | * UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register. |
| 493 | 495 | */ |
| 494 | −static unsigned long uv2_read_status(unsigned long offset, int rshft, int cpu) | |
| 496 | +static unsigned long uv2_read_status(unsigned long offset, int rshft, int desc) | |
| 495 | 497 | { |
| 496 | 498 | unsigned long descriptor_status; |
| 497 | 499 | unsigned long descriptor_status2; |
| 498 | 500 | |
| 499 | 501 | descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK); |
| 500 | − descriptor_status2 = (read_mmr_uv2_status() >> cpu) & 0x1UL; | |
| 502 | + descriptor_status2 = (read_mmr_uv2_status() >> desc) & 0x1UL; | |
| 501 | 503 | descriptor_status = (descriptor_status << 1) | descriptor_status2; |
| 502 | 504 | return descriptor_status; |
| 503 | 505 | } |
| 504 | 506 | |
| 507 | +/* | |
| 508 | + * Return whether the status of the descriptor that is normally used for this | |
| 509 | + * cpu (the one indexed by its hub-relative cpu number) is busy. | |
| 510 | + * The status of the original 32 descriptors is always reflected in the 64 | |
| 511 | + * bits of UVH_LB_BAU_SB_ACTIVATION_STATUS_0. | |
| 512 | + * The bit provided by the activation_status_2 register is irrelevant to | |
| 513 | + * the status if it is only being tested for busy or not busy. | |
| 514 | + */ | |
| 515 | +int normal_busy(struct bau_control *bcp) | |
| 516 | +{ | |
| 517 | + int cpu = bcp->uvhub_cpu; | |
| 518 | + int mmr_offset; | |
| 519 | + int right_shift; | |
| 520 | + | |
| 521 | + mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; | |
| 522 | + right_shift = cpu * UV_ACT_STATUS_SIZE; | |
| 523 | + return (((((read_lmmr(mmr_offset) >> right_shift) & | |
| 524 | + UV_ACT_STATUS_MASK)) << 1) == UV2H_DESC_BUSY); | |
| 525 | +} | |
| 526 | + | |
| 527 | +/* | |
| 528 | + * Entered when a bau descriptor has gone into a permanent busy wait because | |
| 529 | + * of a hardware bug. | |
| 530 | + * Workaround the bug. | |
| 531 | + */ | |
| 532 | +int handle_uv2_busy(struct bau_control *bcp) | |
| 533 | +{ | |
| 534 | + int busy_one = bcp->using_desc; | |
| 535 | + int normal = bcp->uvhub_cpu; | |
| 536 | + int selected = -1; | |
| 537 | + int i; | |
| 538 | + unsigned long descriptor_status; | |
| 539 | + unsigned long status; | |
| 540 | + int mmr_offset; | |
| 541 | + struct bau_desc *bau_desc_old; | |
| 542 | + struct bau_desc *bau_desc_new; | |
| 543 | + struct bau_control *hmaster = bcp->uvhub_master; | |
| 544 | + struct ptc_stats *stat = bcp->statp; | |
| 545 | + cycles_t ttm; | |
| 546 | + | |
| 547 | + stat->s_uv2_wars++; | |
| 548 | + spin_lock(&hmaster->uvhub_lock); | |
| 549 | + /* try for the original first */ | |
| 550 | + if (busy_one != normal) { | |
| 551 | + if (!normal_busy(bcp)) | |
| 552 | + selected = normal; | |
| 553 | + } | |
| 554 | + if (selected < 0) { | |
| 555 | + /* can't use the normal, select an alternate */ | |
| 556 | + mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; | |
| 557 | + descriptor_status = read_lmmr(mmr_offset); | |
| 558 | + | |
| 559 | + /* scan available descriptors 32-63 */ | |
| 560 | + for (i = 0; i < UV_CPUS_PER_AS; i++) { | |
| 561 | + if ((hmaster->inuse_map & (1 << i)) == 0) { | |
| 562 | + status = ((descriptor_status >> | |
| 563 | + (i * UV_ACT_STATUS_SIZE)) & | |
| 564 | + UV_ACT_STATUS_MASK) << 1; | |
| 565 | + if (status != UV2H_DESC_BUSY) { | |
| 566 | + selected = i + UV_CPUS_PER_AS; | |
| 567 | + break; | |
| 568 | + } | |
| 569 | + } | |
| 570 | + } | |
| 571 | + } | |
| 572 | + | |
| 573 | + if (busy_one != normal) | |
| 574 | + /* mark the busy alternate as not in-use */ | |
| 575 | + hmaster->inuse_map &= ~(1 << (busy_one - UV_CPUS_PER_AS)); | |
| 576 | + | |
| 577 | + if (selected >= 0) { | |
| 578 | + /* switch to the selected descriptor */ | |
| 579 | + if (selected != normal) { | |
| 580 | + /* set the selected alternate as in-use */ | |
| 581 | + hmaster->inuse_map |= | |
| 582 | + (1 << (selected - UV_CPUS_PER_AS)); | |
| 583 | + if (selected > stat->s_uv2_wars_hw) | |
| 584 | + stat->s_uv2_wars_hw = selected; | |
| 585 | + } | |
| 586 | + bau_desc_old = bcp->descriptor_base; | |
| 587 | + bau_desc_old += (ITEMS_PER_DESC * busy_one); | |
| 588 | + bcp->using_desc = selected; | |
| 589 | + bau_desc_new = bcp->descriptor_base; | |
| 590 | + bau_desc_new += (ITEMS_PER_DESC * selected); | |
| 591 | + *bau_desc_new = *bau_desc_old; | |
| 592 | + } else { | |
| 593 | + /* | |
| 594 | + * All are busy. Wait for the normal one for this cpu to | |
| 595 | + * free up. | |
| 596 | + */ | |
| 597 | + stat->s_uv2_war_waits++; | |
| 598 | + spin_unlock(&hmaster->uvhub_lock); | |
| 599 | + ttm = get_cycles(); | |
| 600 | + do { | |
| 601 | + cpu_relax(); | |
| 602 | + } while (normal_busy(bcp)); | |
| 603 | + spin_lock(&hmaster->uvhub_lock); | |
| 604 | + /* switch to the original descriptor */ | |
| 605 | + bcp->using_desc = normal; | |
| 606 | + bau_desc_old = bcp->descriptor_base; | |
| 607 | + bau_desc_old += (ITEMS_PER_DESC * bcp->using_desc); | |
| 608 | + bcp->using_desc = (ITEMS_PER_DESC * normal); | |
| 609 | + bau_desc_new = bcp->descriptor_base; | |
| 610 | + bau_desc_new += (ITEMS_PER_DESC * normal); | |
| 611 | + *bau_desc_new = *bau_desc_old; /* copy the entire descriptor */ | |
| 612 | + } | |
| 613 | + spin_unlock(&hmaster->uvhub_lock); | |
| 614 | + return FLUSH_RETRY_BUSYBUG; | |
| 615 | +} | |
| 616 | + | |
| 505 | 617 | static int uv2_wait_completion(struct bau_desc *bau_desc, |
| 506 | 618 | unsigned long mmr_offset, int right_shift, |
| 507 | 619 | struct bau_control *bcp, long try) |
| 508 | 620 | { |
| 509 | 621 | unsigned long descriptor_stat; |
| 510 | 622 | cycles_t ttm; |
| 511 | − int cpu = bcp->uvhub_cpu; | |
| 623 | + int desc = bcp->using_desc; | |
| 624 | + long busy_reps = 0; | |
| 512 | 625 | struct ptc_stats *stat = bcp->statp; |
| 513 | 626 | |
| 514 | − descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu); | |
| 627 | + descriptor_stat = uv2_read_status(mmr_offset, right_shift, desc); | |
| 515 | 628 | |
| 516 | 629 | /* spin on the status MMR, waiting for it to go idle */ |
| 517 | 630 | while (descriptor_stat != UV2H_DESC_IDLE) { |
| @@ -522,32 +635,35 @@ static int uv2_wait_completion(struct bau_desc *bau_desc, · 4 unmodified lines | ||
| 522 | 635 | * our message and its state will stay IDLE. |
| 523 | 636 | */ |
| 524 | 637 | if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) || |
| 525 | − (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) || | |
| 526 | 638 | (descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) { |
| 527 | 639 | stat->s_stimeout++; |
| 528 | 640 | return FLUSH_GIVEUP; |
| 641 | + } else if (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) { | |
| 642 | + stat->s_strongnacks++; | |
| 643 | + bcp->conseccompletes = 0; | |
| 644 | + return FLUSH_GIVEUP; | |
| 529 | 645 | } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) { |
| 530 | 646 | stat->s_dtimeout++; |
| 531 | − ttm = get_cycles(); | |
| 532 | − /* | |
| 533 | − * Our retries may be blocked by all destination | |
| 534 | − * swack resources being consumed, and a timeout | |
| 535 | − * pending. In that case hardware returns the | |
| 536 | − * ERROR that looks like a destination timeout. | |
| 537 | − */ | |
| 538 | − if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { | |
| 539 | − bcp->conseccompletes = 0; | |
| 540 | − return FLUSH_RETRY_PLUGGED; | |
| 541 | − } | |
| 542 | 647 | bcp->conseccompletes = 0; |
| 543 | 648 | return FLUSH_RETRY_TIMEOUT; |
| 544 | 649 | } else { |
| 650 | + busy_reps++; | |
| 651 | + if (busy_reps > 1000000) { | |
| 652 | + /* not to hammer on the clock */ | |
| 653 | + busy_reps = 0; | |
| 654 | + ttm = get_cycles(); | |
| 655 | + if ((ttm - bcp->send_message) > | |
| 656 | + (bcp->clocks_per_100_usec)) { | |
| 657 | + return handle_uv2_busy(bcp); | |
| 658 | + } | |
| 659 | + } | |
| 545 | 660 | /* |
| 546 | 661 | * descriptor_stat is still BUSY |
| 547 | 662 | */ |
| 548 | 663 | cpu_relax(); |
| 549 | 664 | } |
| 550 | − descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu); | |
| 665 | + descriptor_stat = uv2_read_status(mmr_offset, right_shift, | |
| 666 | + desc); | |
| 551 | 667 | } |
| 552 | 668 | bcp->conseccompletes++; |
| 553 | 669 | return FLUSH_COMPLETE; |
| @@ -563,17 +679,17 @@ static int wait_completion(struct bau_desc *bau_desc, · 9 unmodified lines | ||
| 563 | 679 | { |
| 564 | 680 | int right_shift; |
| 565 | 681 | unsigned long mmr_offset; |
| 566 | − int cpu = bcp->uvhub_cpu; | |
| 682 | + int desc = bcp->using_desc; | |
| 567 | 683 | |
| 568 | − if (cpu < UV_CPUS_PER_AS) { | |
| 684 | + if (desc < UV_CPUS_PER_AS) { | |
| 569 | 685 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; |
| 570 | − right_shift = cpu * UV_ACT_STATUS_SIZE; | |
| 686 | + right_shift = desc * UV_ACT_STATUS_SIZE; | |
| 571 | 687 | } else { |
| 572 | 688 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; |
| 573 | − right_shift = ((cpu - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE); | |
| 689 | + right_shift = ((desc - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE); | |
| 574 | 690 | } |
| 575 | 691 | |
| 576 | − if (is_uv1_hub()) | |
| 692 | + if (bcp->uvhub_version == 1) | |
| 577 | 693 | return uv1_wait_completion(bau_desc, mmr_offset, right_shift, |
| 578 | 694 | bcp, try); |
| 579 | 695 | else |
| @@ -752,19 +868,22 @@ static void handle_cmplt(int completion_status, struct bau_desc *bau_desc, · 172 unmodified lines | ||
| 752 | 868 | * Returns 1 if it gives up entirely and the original cpu mask is to be |
| 753 | 869 | * returned to the kernel. |
| 754 | 870 | */ |
| 755 | −int uv_flush_send_and_wait(struct bau_desc *bau_desc, | |
| 756 | − struct cpumask *flush_mask, struct bau_control *bcp) | |
| 871 | +int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp) | |
| 757 | 872 | { |
| 758 | 873 | int seq_number = 0; |
| 759 | 874 | int completion_stat = 0; |
| 875 | + int uv1 = 0; | |
| 760 | 876 | long try = 0; |
| 761 | 877 | unsigned long index; |
| 762 | 878 | cycles_t time1; |
| 763 | 879 | cycles_t time2; |
| 764 | 880 | struct ptc_stats *stat = bcp->statp; |
| 765 | 881 | struct bau_control *hmaster = bcp->uvhub_master; |
| 882 | + struct uv1_bau_msg_header *uv1_hdr = NULL; | |
| 883 | + struct uv2_bau_msg_header *uv2_hdr = NULL; | |
| 884 | + struct bau_desc *bau_desc; | |
| 766 | 885 | |
| 767 | − if (is_uv1_hub()) | |
| 886 | + if (bcp->uvhub_version == 1) | |
| 768 | 887 | uv1_throttle(hmaster, stat); |
| 769 | 888 | |
| 770 | 889 | while (hmaster->uvhub_quiesce) |
| @@ -772,22 +891,39 @@ int uv_flush_send_and_wait(struct bau_desc *bau_desc, · 1 unmodified line | ||
| 772 | 891 | |
| 773 | 892 | time1 = get_cycles(); |
| 774 | 893 | do { |
| 775 | − if (try == 0) { | |
| 776 | − bau_desc->header.msg_type = MSG_REGULAR; | |
| 894 | + bau_desc = bcp->descriptor_base; | |
| 895 | + bau_desc += (ITEMS_PER_DESC * bcp->using_desc); | |
| 896 | + if (bcp->uvhub_version == 1) { | |
| 897 | + uv1 = 1; | |
| 898 | + uv1_hdr = &bau_desc->header.uv1_hdr; | |
| 899 | + } else | |
| 900 | + uv2_hdr = &bau_desc->header.uv2_hdr; | |
| 901 | + if ((try == 0) || (completion_stat == FLUSH_RETRY_BUSYBUG)) { | |
| 902 | + if (uv1) | |
| 903 | + uv1_hdr->msg_type = MSG_REGULAR; | |
| 904 | + else | |
| 905 | + uv2_hdr->msg_type = MSG_REGULAR; | |
| 777 | 906 | seq_number = bcp->message_number++; |
| 778 | 907 | } else { |
| 779 | − bau_desc->header.msg_type = MSG_RETRY; | |
| 908 | + if (uv1) | |
| 909 | + uv1_hdr->msg_type = MSG_RETRY; | |
| 910 | + else | |
| 911 | + uv2_hdr->msg_type = MSG_RETRY; | |
| 780 | 912 | stat->s_retry_messages++; |
| 781 | 913 | } |
| 782 | 914 | |
| 783 | − bau_desc->header.sequence = seq_number; | |
| 784 | − index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu; | |
| 915 | + if (uv1) | |
| 916 | + uv1_hdr->sequence = seq_number; | |
| 917 | + else | |
| 918 | + uv2_hdr->sequence = seq_number; | |
| 919 | + index = (1UL << AS_PUSH_SHIFT) | bcp->using_desc; | |
| 785 | 920 | bcp->send_message = get_cycles(); |
| 786 | 921 | |
| 787 | 922 | write_mmr_activation(index); |
| 788 | 923 | |
| 789 | 924 | try++; |
| 790 | 925 | completion_stat = wait_completion(bau_desc, bcp, try); |
| 926 | + /* UV2: wait_completion() may change the bcp->using_desc */ | |
| 791 | 927 | |
| 792 | 928 | handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat); |
| 793 | 929 | |
| @@ -798,6 +934,7 @@ int uv_flush_send_and_wait(struct bau_desc *bau_desc, · 4 unmodified lines | ||
| 798 | 934 | } |
| 799 | 935 | cpu_relax(); |
| 800 | 936 | } while ((completion_stat == FLUSH_RETRY_PLUGGED) || |
| 937 | + (completion_stat == FLUSH_RETRY_BUSYBUG) || | |
| 801 | 938 | (completion_stat == FLUSH_RETRY_TIMEOUT)); |
| 802 | 939 | |
| 803 | 940 | time2 = get_cycles(); |
| @@ -812,6 +949,7 @@ int uv_flush_send_and_wait(struct bau_desc *bau_desc, · 8 unmodified lines | ||
| 812 | 949 | record_send_stats(time1, time2, bcp, stat, completion_stat, try); |
| 813 | 950 | |
| 814 | 951 | if (completion_stat == FLUSH_GIVEUP) |
| 952 | + /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */ | |
| 815 | 953 | return 1; |
| 816 | 954 | return 0; |
| 817 | 955 | } |
| @@ -967,7 +1105,7 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, · 149 unmodified lines | ||
| 967 | 1105 | stat->s_ntargself++; |
| 968 | 1106 | |
| 969 | 1107 | bau_desc = bcp->descriptor_base; |
| 970 | − bau_desc += ITEMS_PER_DESC * bcp->uvhub_cpu; | |
| 1108 | + bau_desc += (ITEMS_PER_DESC * bcp->using_desc); | |
| 971 | 1109 | bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); |
| 972 | 1110 | if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) |
| 973 | 1111 | return NULL; |
| @@ -980,12 +1118,85 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, · 6 unmodified lines | ||
| 980 | 1118 | * uv_flush_send_and_wait returns 0 if all cpu's were messaged, |
| 981 | 1119 | * or 1 if it gave up and the original cpumask should be returned. |
| 982 | 1120 | */ |
| 983 | − if (!uv_flush_send_and_wait(bau_desc, flush_mask, bcp)) | |
| 1121 | + if (!uv_flush_send_and_wait(flush_mask, bcp)) | |
| 984 | 1122 | return NULL; |
| 985 | 1123 | else |
| 986 | 1124 | return cpumask; |
| 987 | 1125 | } |
| 988 | 1126 | |
| 1127 | +/* | |
| 1128 | + * Search the message queue for any 'other' message with the same software | |
| 1129 | + * acknowledge resource bit vector. | |
| 1130 | + */ | |
| 1131 | +struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg, | |
| 1132 | + struct bau_control *bcp, unsigned char swack_vec) | |
| 1133 | +{ | |
| 1134 | + struct bau_pq_entry *msg_next = msg + 1; | |
| 1135 | + | |
| 1136 | + if (msg_next > bcp->queue_last) | |
| 1137 | + msg_next = bcp->queue_first; | |
| 1138 | + while ((msg_next->swack_vec != 0) && (msg_next != msg)) { | |
| 1139 | + if (msg_next->swack_vec == swack_vec) | |
| 1140 | + return msg_next; | |
| 1141 | + msg_next++; | |
| 1142 | + if (msg_next > bcp->queue_last) | |
| 1143 | + msg_next = bcp->queue_first; | |
| 1144 | + } | |
| 1145 | + return NULL; | |
| 1146 | +} | |
| 1147 | + | |
| 1148 | +/* | |
| 1149 | + * UV2 needs to work around a bug in which an arriving message has not | |
| 1150 | + * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register. | |
| 1151 | + * Such a message must be ignored. | |
| 1152 | + */ | |
| 1153 | +void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp) | |
| 1154 | +{ | |
| 1155 | + unsigned long mmr_image; | |
| 1156 | + unsigned char swack_vec; | |
| 1157 | + struct bau_pq_entry *msg = mdp->msg; | |
| 1158 | + struct bau_pq_entry *other_msg; | |
| 1159 | + | |
| 1160 | + mmr_image = read_mmr_sw_ack(); | |
| 1161 | + swack_vec = msg->swack_vec; | |
| 1162 | + | |
| 1163 | + if ((swack_vec & mmr_image) == 0) { | |
| 1164 | + /* | |
| 1165 | + * This message was assigned a swack resource, but no | |
| 1166 | + * reserved acknowlegment is pending. | |
| 1167 | + * The bug has prevented this message from setting the MMR. | |
| 1168 | + * And no other message has used the same sw_ack resource. | |
| 1169 | + * Do the requested shootdown but do not reply to the msg. | |
| 1170 | + * (the 0 means make no acknowledge) | |
| 1171 | + */ | |
| 1172 | + bau_process_message(mdp, bcp, 0); | |
| 1173 | + return; | |
| 1174 | + } | |
| 1175 | + | |
| 1176 | + /* | |
| 1177 | + * Some message has set the MMR 'pending' bit; it might have been | |
| 1178 | + * another message. Look for that message. | |
| 1179 | + */ | |
| 1180 | + other_msg = find_another_by_swack(msg, bcp, msg->swack_vec); | |
| 1181 | + if (other_msg) { | |
| 1182 | + /* There is another. Do not ack the current one. */ | |
| 1183 | + bau_process_message(mdp, bcp, 0); | |
| 1184 | + /* | |
| 1185 | + * Let the natural processing of that message acknowledge | |
| 1186 | + * it. Don't get the processing of sw_ack's out of order. | |
| 1187 | + */ | |
| 1188 | + return; | |
| 1189 | + } | |
| 1190 | + | |
| 1191 | + /* | |
| 1192 | + * There is no other message using this sw_ack, so it is safe to | |
| 1193 | + * acknowledge it. | |
| 1194 | + */ | |
| 1195 | + bau_process_message(mdp, bcp, 1); | |
| 1196 | + | |
| 1197 | + return; | |
| 1198 | +} | |
| 1199 | + | |
| 989 | 1200 | /* |
| 990 | 1201 | * The BAU message interrupt comes here. (registered by set_intr_gate) |
| 991 | 1202 | * See entry_64.S |
| @@ -1009,6 +1220,7 @@ void uv_bau_message_interrupt(struct pt_regs *regs) · 17 unmodified lines | ||
| 1009 | 1220 | struct ptc_stats *stat; |
| 1010 | 1221 | struct msg_desc msgdesc; |
| 1011 | 1222 | |
| 1223 | + ack_APIC_irq(); | |
| 1012 | 1224 | time_start = get_cycles(); |
| 1013 | 1225 | |
| 1014 | 1226 | bcp = &per_cpu(bau_control, smp_processor_id()); |
| @@ -1022,9 +1234,11 @@ void uv_bau_message_interrupt(struct pt_regs *regs) · 7 unmodified lines | ||
| 1022 | 1234 | count++; |
| 1023 | 1235 | |
| 1024 | 1236 | msgdesc.msg_slot = msg - msgdesc.queue_first; |
| 1025 | − msgdesc.swack_slot = ffs(msg->swack_vec) - 1; | |
| 1026 | 1237 | msgdesc.msg = msg; |
| 1027 | − bau_process_message(&msgdesc, bcp); | |
| 1238 | + if (bcp->uvhub_version == 2) | |
| 1239 | + process_uv2_message(&msgdesc, bcp); | |
| 1240 | + else | |
| 1241 | + bau_process_message(&msgdesc, bcp, 1); | |
| 1028 | 1242 | |
| 1029 | 1243 | msg++; |
| 1030 | 1244 | if (msg > msgdesc.queue_last) |
| @@ -1036,8 +1250,6 @@ void uv_bau_message_interrupt(struct pt_regs *regs) · 5 unmodified lines | ||
| 1036 | 1250 | stat->d_nomsg++; |
| 1037 | 1251 | else if (count > 1) |
| 1038 | 1252 | stat->d_multmsg++; |
| 1039 | − | |
| 1040 | − ack_APIC_irq(); | |
| 1041 | 1253 | } |
| 1042 | 1254 | |
| 1043 | 1255 | /* |
| @@ -1083,7 +1295,7 @@ static void __init enable_timeouts(void) · 39 unmodified lines | ||
| 1083 | 1295 | */ |
| 1084 | 1296 | mmr_image |= (1L << SOFTACK_MSHIFT); |
| 1085 | 1297 | if (is_uv2_hub()) { |
| 1086 | − mmr_image |= (1L << UV2_LEG_SHFT); | |
| 1298 | + mmr_image &= ~(1L << UV2_LEG_SHFT); | |
| 1087 | 1299 | mmr_image |= (1L << UV2_EXT_SHFT); |
| 1088 | 1300 | } |
| 1089 | 1301 | write_mmr_misc_control(pnode, mmr_image); |
| @@ -1136,13 +1348,13 @@ static int ptc_seq_show(struct seq_file *file, void *data) · 46 unmodified lines | ||
| 1136 | 1348 | seq_printf(file, |
| 1137 | 1349 | "remotehub numuvhubs numuvhubs16 numuvhubs8 "); |
| 1138 | 1350 | seq_printf(file, |
| 1139 | − "numuvhubs4 numuvhubs2 numuvhubs1 dto retries rok "); | |
| 1351 | + "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries rok "); | |
| 1140 | 1352 | seq_printf(file, |
| 1141 | 1353 | "resetp resett giveup sto bz throt swack recv rtime "); |
| 1142 | 1354 | seq_printf(file, |
| 1143 | 1355 | "all one mult none retry canc nocan reset rcan "); |
| 1144 | 1356 | seq_printf(file, |
| 1145 | − "disable enable\n"); | |
| 1357 | + "disable enable wars warshw warwaits\n"); | |
| 1146 | 1358 | } |
| 1147 | 1359 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { |
| 1148 | 1360 | stat = &per_cpu(ptcstats, cpu); |
| @@ -1154,10 +1366,10 @@ static int ptc_seq_show(struct seq_file *file, void *data) · 5 unmodified lines | ||
| 1154 | 1366 | stat->s_ntargremotes, stat->s_ntargcpu, |
| 1155 | 1367 | stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub, |
| 1156 | 1368 | stat->s_ntarguvhub, stat->s_ntarguvhub16); |
| 1157 | − seq_printf(file, "%ld %ld %ld %ld %ld ", | |
| 1369 | + seq_printf(file, "%ld %ld %ld %ld %ld %ld ", | |
| 1158 | 1370 | stat->s_ntarguvhub8, stat->s_ntarguvhub4, |
| 1159 | 1371 | stat->s_ntarguvhub2, stat->s_ntarguvhub1, |
| 1160 | − stat->s_dtimeout); | |
| 1372 | + stat->s_dtimeout, stat->s_strongnacks); | |
| 1161 | 1373 | seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ", |
| 1162 | 1374 | stat->s_retry_messages, stat->s_retriesok, |
| 1163 | 1375 | stat->s_resets_plug, stat->s_resets_timeout, |
| @@ -1173,8 +1385,10 @@ static int ptc_seq_show(struct seq_file *file, void *data) · 9 unmodified lines | ||
| 1173 | 1385 | stat->d_nomsg, stat->d_retries, stat->d_canceled, |
| 1174 | 1386 | stat->d_nocanceled, stat->d_resets, |
| 1175 | 1387 | stat->d_rcanceled); |
| 1176 | − seq_printf(file, "%ld %ld\n", | |
| 1177 | − stat->s_bau_disabled, stat->s_bau_reenabled); | |
| 1388 | + seq_printf(file, "%ld %ld %ld %ld %ld\n", | |
| 1389 | + stat->s_bau_disabled, stat->s_bau_reenabled, | |
| 1390 | + stat->s_uv2_wars, stat->s_uv2_wars_hw, | |
| 1391 | + stat->s_uv2_war_waits); | |
| 1178 | 1392 | } |
| 1179 | 1393 | return 0; |
| 1180 | 1394 | } |
| @@ -1432,12 +1646,15 @@ static void activation_descriptor_init(int node, int pnode, int base_pnode) · 251 unmodified lines | ||
| 1432 | 1646 | { |
| 1433 | 1647 | int i; |
| 1434 | 1648 | int cpu; |
| 1649 | + int uv1 = 0; | |
| 1435 | 1650 | unsigned long gpa; |
| 1436 | 1651 | unsigned long m; |
| 1437 | 1652 | unsigned long n; |
| 1438 | 1653 | size_t dsize; |
| 1439 | 1654 | struct bau_desc *bau_desc; |
| 1440 | 1655 | struct bau_desc *bd2; |
| 1656 | + struct uv1_bau_msg_header *uv1_hdr; | |
| 1657 | + struct uv2_bau_msg_header *uv2_hdr; | |
| 1441 | 1658 | struct bau_control *bcp; |
| 1442 | 1659 | |
| 1443 | 1660 | /* |
| @@ -1451,6 +1668,8 @@ static void activation_descriptor_init(int node, int pnode, int base_pnode) · 7 unmodified lines | ||
| 1451 | 1668 | gpa = uv_gpa(bau_desc); |
| 1452 | 1669 | n = uv_gpa_to_gnode(gpa); |
| 1453 | 1670 | m = uv_gpa_to_offset(gpa); |
| 1671 | + if (is_uv1_hub()) | |
| 1672 | + uv1 = 1; | |
| 1454 | 1673 | |
| 1455 | 1674 | /* the 14-bit pnode */ |
| 1456 | 1675 | write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m)); |
| @@ -1461,21 +1680,33 @@ static void activation_descriptor_init(int node, int pnode, int base_pnode) · 4 unmodified lines | ||
| 1461 | 1680 | */ |
| 1462 | 1681 | for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) { |
| 1463 | 1682 | memset(bd2, 0, sizeof(struct bau_desc)); |
| 1464 | − bd2->header.swack_flag = 1; | |
| 1465 | − /* | |
| 1466 | − * The base_dest_nasid set in the message header is the nasid | |
| 1467 | − * of the first uvhub in the partition. The bit map will | |
| 1468 | − * indicate destination pnode numbers relative to that base. | |
| 1469 | − * They may not be consecutive if nasid striding is being used. | |
| 1470 | − */ | |
| 1471 | − bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode); | |
| 1472 | − bd2->header.dest_subnodeid = UV_LB_SUBNODEID; | |
| 1473 | − bd2->header.command = UV_NET_ENDPOINT_INTD; | |
| 1474 | − bd2->header.int_both = 1; | |
| 1475 | − /* | |
| 1476 | − * all others need to be set to zero: | |
| 1477 | − * fairness chaining multilevel count replied_to | |
| 1478 | − */ | |
| 1683 | + if (uv1) { | |
| 1684 | + uv1_hdr = &bd2->header.uv1_hdr; | |
| 1685 | + uv1_hdr->swack_flag = 1; | |
| 1686 | + /* | |
| 1687 | + * The base_dest_nasid set in the message header | |
| 1688 | + * is the nasid of the first uvhub in the partition. | |
| 1689 | + * The bit map will indicate destination pnode numbers | |
| 1690 | + * relative to that base. They may not be consecutive | |
| 1691 | + * if nasid striding is being used. | |
| 1692 | + */ | |
| 1693 | + uv1_hdr->base_dest_nasid = | |
| 1694 | + UV_PNODE_TO_NASID(base_pnode); | |
| 1695 | + uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID; | |
| 1696 | + uv1_hdr->command = UV_NET_ENDPOINT_INTD; | |
| 1697 | + uv1_hdr->int_both = 1; | |
| 1698 | + /* | |
| 1699 | + * all others need to be set to zero: | |
| 1700 | + * fairness chaining multilevel count replied_to | |
| 1701 | + */ | |
| 1702 | + } else { | |
| 1703 | + uv2_hdr = &bd2->header.uv2_hdr; | |
| 1704 | + uv2_hdr->swack_flag = 1; | |
| 1705 | + uv2_hdr->base_dest_nasid = | |
| 1706 | + UV_PNODE_TO_NASID(base_pnode); | |
| 1707 | + uv2_hdr->dest_subnodeid = UV_LB_SUBNODEID; | |
| 1708 | + uv2_hdr->command = UV_NET_ENDPOINT_INTD; | |
| 1709 | + } | |
| 1479 | 1710 | } |
| 1480 | 1711 | for_each_present_cpu(cpu) { |
| 1481 | 1712 | if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu))) |
| @@ -1531,6 +1762,7 @@ static void pq_init(int node, int pnode) · 49 unmodified lines | ||
| 1531 | 1762 | write_mmr_payload_first(pnode, pn_first); |
| 1532 | 1763 | write_mmr_payload_tail(pnode, first); |
| 1533 | 1764 | write_mmr_payload_last(pnode, last); |
| 1765 | + write_gmmr_sw_ack(pnode, 0xffffUL); | |
| 1534 | 1766 | |
| 1535 | 1767 | /* in effect, all msg_type's are set to MSG_NOOP */ |
| 1536 | 1768 | memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE); |
| @@ -1584,14 +1816,14 @@ static int calculate_destination_timeout(void) · 47 unmodified lines | ||
| 1584 | 1816 | ts_ns = base * mult1 * mult2; |
| 1585 | 1817 | ret = ts_ns / 1000; |
| 1586 | 1818 | } else { |
| 1587 | − /* 4 bits 0/1 for 10/80us, 3 bits of multiplier */ | |
| 1588 | − mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); | |
| 1819 | + /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */ | |
| 1820 | + mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL); | |
| 1589 | 1821 | mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT; |
| 1590 | 1822 | if (mmr_image & (1L << UV2_ACK_UNITS_SHFT)) |
| 1591 | − mult1 = 80; | |
| 1823 | + base = 80; | |
| 1592 | 1824 | else |
| 1593 | − mult1 = 10; | |
| 1594 | − base = mmr_image & UV2_ACK_MASK; | |
| 1825 | + base = 10; | |
| 1826 | + mult1 = mmr_image & UV2_ACK_MASK; | |
| 1595 | 1827 | ret = mult1 * base; |
| 1596 | 1828 | } |
| 1597 | 1829 | return ret; |
| @@ -1618,6 +1850,9 @@ static void __init init_per_cpu_tunables(void) · 20 unmodified lines | ||
| 1618 | 1850 | bcp->cong_response_us = congested_respns_us; |
| 1619 | 1851 | bcp->cong_reps = congested_reps; |
| 1620 | 1852 | bcp->cong_period = congested_period; |
| 1853 | + bcp->clocks_per_100_usec = usec_2_cycles(100); | |
| 1854 | + spin_lock_init(&bcp->queue_lock); | |
| 1855 | + spin_lock_init(&bcp->uvhub_lock); | |
| 1621 | 1856 | } |
| 1622 | 1857 | } |
| 1623 | 1858 | |
| @@ -1728,8 +1963,17 @@ static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp, · 104 unmodified lines | ||
| 1728 | 1963 | bcp->cpus_in_socket = sdp->num_cpus; |
| 1729 | 1964 | bcp->socket_master = *smasterp; |
| 1730 | 1965 | bcp->uvhub = bdp->uvhub; |
| 1966 | + if (is_uv1_hub()) | |
| 1967 | + bcp->uvhub_version = 1; | |
| 1968 | + else if (is_uv2_hub()) | |
| 1969 | + bcp->uvhub_version = 2; | |
| 1970 | + else { | |
| 1971 | + printk(KERN_EMERG "uvhub version not 1 or 2\n"); | |
| 1972 | + return 1; | |
| 1973 | + } | |
| 1731 | 1974 | bcp->uvhub_master = *hmasterp; |
| 1732 | 1975 | bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id; |
| 1976 | + bcp->using_desc = bcp->uvhub_cpu; | |
| 1733 | 1977 | if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { |
| 1734 | 1978 | printk(KERN_EMERG "%d cpus per uvhub invalid\n", |
| 1735 | 1979 | bcp->uvhub_cpu); |
| @@ -1845,6 +2089,8 @@ static int __init uv_bau_init(void) · 109 unmodified lines | ||
| 1845 | 2089 | uv_base_pnode = uv_blade_to_pnode(uvhub); |
| 1846 | 2090 | } |
| 1847 | 2091 | |
| 2092 | + enable_timeouts(); | |
| 2093 | + | |
| 1848 | 2094 | if (init_per_cpu(nuvhubs, uv_base_pnode)) { |
| 1849 | 2095 | nobau = 1; |
| 1850 | 2096 | return 0; |
| @@ -1855,7 +2101,6 @@ static int __init uv_bau_init(void) · 4 unmodified lines | ||
| 1855 | 2101 | if (uv_blade_nr_possible_cpus(uvhub)) |
| 1856 | 2102 | init_uvhub(uvhub, vector, uv_base_pnode); |
| 1857 | 2103 | |
| 1858 | − enable_timeouts(); | |
| 1859 | 2104 | alloc_intr_gate(vector, uv_bau_message_intr1); |
| 1860 | 2105 | |
| 1861 | 2106 | for_each_possible_blade(uvhub) { |
| @@ -1867,7 +2112,8 @@ static int __init uv_bau_init(void) · 5 unmodified lines | ||
| 1867 | 2112 | val = 1L << 63; |
| 1868 | 2113 | write_gmmr_activation(pnode, val); |
| 1869 | 2114 | mmr = 1; /* should be 1 to broadcast to both sockets */ |
| 1870 | − write_mmr_data_broadcast(pnode, mmr); | |
| 2115 | + if (!is_uv1_hub()) | |
| 2116 | + write_mmr_data_broadcast(pnode, mmr); | |
| 1871 | 2117 | } |
| 1872 | 2118 | } |
| 1873 | 2119 | |
| @@ -25,7 +25,7 @@ struct uv_irq_2_mmr_pnode{ · 24 unmodified lines | ||
| 25 | 25 | int irq; |
| 26 | 26 | }; |
| 27 | 27 | |
| 28 | −static spinlock_t uv_irq_lock; | |
| 28 | +static DEFINE_SPINLOCK(uv_irq_lock); | |
| 29 | 29 | static struct rb_root uv_irq_root; |
| 30 | 30 | |
| 31 | 31 | static int uv_set_irq_affinity(struct irq_data *, const struct cpumask *, bool); |
| @@ -1,5 +1,15 @@ | ||
| 1 | +#ifndef __SYSDEP_X86_PTRACE_H | |
| 2 | +#define __SYSDEP_X86_PTRACE_H | |
| 3 | + | |
| 1 | 4 | #ifdef __i386__ |
| 2 | 5 | #include "ptrace_32.h" |
| 3 | 6 | #else |
| 4 | 7 | #include "ptrace_64.h" |
| 5 | 8 | #endif |
| 9 | + | |
| 10 | +static inline long regs_return_value(struct uml_pt_regs *regs) | |
| 11 | +{ | |
| 12 | + return UPT_SYSCALL_RET(regs); | |
| 13 | +} | |
| 14 | + | |
| 15 | +#endif /* __SYSDEP_X86_PTRACE_H */ | |
| @@ -409,6 +409,13 @@ static void __cpuinit xen_play_dead(void) /* used only with HOTPLUG_CPU */ · 408 unmodified lines | ||
| 409 | 409 | play_dead_common(); |
| 410 | 410 | HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL); |
| 411 | 411 | cpu_bringup(); |
| 412 | + /* | |
| 413 | + * Balance out the preempt calls - as we are running in cpu_idle | |
| 414 | + * loop which has been called at bootup from cpu_bringup_and_idle. | |
| 415 | + * The cpucpu_bringup_and_idle called cpu_bringup which made a | |
| 416 | + * preempt_disable() So this preempt_enable will balance it out. | |
| 417 | + */ | |
| 418 | + preempt_enable(); | |
| 412 | 419 | } |
| 413 | 420 | |
| 414 | 421 | #else /* !CONFIG_HOTPLUG_CPU */ |
| @@ -116,9 +116,26 @@ static inline void spin_time_accum_blocked(u64 start) · 115 unmodified lines | ||
| 116 | 116 | } |
| 117 | 117 | #endif /* CONFIG_XEN_DEBUG_FS */ |
| 118 | 118 | |
| 119 | +/* | |
| 120 | + * Size struct xen_spinlock so it's the same as arch_spinlock_t. | |
| 121 | + */ | |
| 122 | +#if NR_CPUS < 256 | |
| 123 | +typedef u8 xen_spinners_t; | |
| 124 | +# define inc_spinners(xl) \ | |
| 125 | + asm(LOCK_PREFIX " incb %0" : "+m" ((xl)->spinners) : : "memory"); | |
| 126 | +# define dec_spinners(xl) \ | |
| 127 | + asm(LOCK_PREFIX " decb %0" : "+m" ((xl)->spinners) : : "memory"); | |
| 128 | +#else | |
| 129 | +typedef u16 xen_spinners_t; | |
| 130 | +# define inc_spinners(xl) \ | |
| 131 | + asm(LOCK_PREFIX " incw %0" : "+m" ((xl)->spinners) : : "memory"); | |
| 132 | +# define dec_spinners(xl) \ | |
| 133 | + asm(LOCK_PREFIX " decw %0" : "+m" ((xl)->spinners) : : "memory"); | |
| 134 | +#endif | |
| 135 | + | |
| 119 | 136 | struct xen_spinlock { |
| 120 | 137 | unsigned char lock; /* 0 -> free; 1 -> locked */ |
| 121 | − unsigned short spinners; /* count of waiting cpus */ | |
| 138 | + xen_spinners_t spinners; /* count of waiting cpus */ | |
| 122 | 139 | }; |
| 123 | 140 | |
| 124 | 141 | static int xen_spin_is_locked(struct arch_spinlock *lock) |
| @@ -164,8 +181,7 @@ static inline struct xen_spinlock *spinning_lock(struct xen_spinlock *xl) · 39 unmodified lines | ||
| 164 | 181 | |
| 165 | 182 | wmb(); /* set lock of interest before count */ |
| 166 | 183 | |
| 167 | − asm(LOCK_PREFIX " incw %0" | |
| 168 | − : "+m" (xl->spinners) : : "memory"); | |
| 184 | + inc_spinners(xl); | |
| 169 | 185 | |
| 170 | 186 | return prev; |
| 171 | 187 | } |
| @@ -176,8 +192,7 @@ static inline struct xen_spinlock *spinning_lock(struct xen_spinlock *xl) · 4 unmodified lines | ||
| 176 | 192 | */ |
| 177 | 193 | static inline void unspinning_lock(struct xen_spinlock *xl, struct xen_spinlock *prev) |
| 178 | 194 | { |
| 179 | − asm(LOCK_PREFIX " decw %0" | |
| 180 | − : "+m" (xl->spinners) : : "memory"); | |
| 195 | + dec_spinners(xl); | |
| 181 | 196 | wmb(); /* decrement count before restoring lock */ |
| 182 | 197 | __this_cpu_write(lock_spinners, prev); |
| 183 | 198 | } |
| @@ -373,6 +388,8 @@ void xen_uninit_lock_cpu(int cpu) · 189 unmodified lines | ||
| 373 | 388 | |
| 374 | 389 | void __init xen_init_spinlocks(void) |
| 375 | 390 | { |
| 391 | + BUILD_BUG_ON(sizeof(struct xen_spinlock) > sizeof(arch_spinlock_t)); | |
| 392 | + | |
| 376 | 393 | pv_lock_ops.spin_is_locked = xen_spin_is_locked; |
| 377 | 394 | pv_lock_ops.spin_is_contended = xen_spin_is_contended; |
| 378 | 395 | pv_lock_ops.spin_lock = xen_spin_lock; |
| @@ -118,7 +118,4 @@ extern void *memmove(void *__dest, __const__ void *__src, size_t __n); · 117 unmodified lines | ||
| 118 | 118 | /* Don't build bcopy at all ... */ |
| 119 | 119 | #define __HAVE_ARCH_BCOPY |
| 120 | 120 | |
| 121 | −#define __HAVE_ARCH_MEMSCAN | |
| 122 | −#define memscan memchr | |
| 123 | − | |
| 124 | 121 | #endif /* _XTENSA_STRING_H */ |
| @@ -334,8 +334,7 @@ void do_syscall_trace_enter(struct pt_regs *regs) · 333 unmodified lines | ||
| 334 | 334 | do_syscall_trace(); |
| 335 | 335 | |
| 336 | 336 | #if 0 |
| 337 | − if (unlikely(current->audit_context)) | |
| 338 | − audit_syscall_entry(current, AUDIT_ARCH_XTENSA..); | |
| 337 | + audit_syscall_entry(current, AUDIT_ARCH_XTENSA..); | |
| 339 | 338 | #endif |
| 340 | 339 | } |
| 341 | 340 | |
| @@ -1659,7 +1659,7 @@ static void blkiocg_attach(struct cgroup_subsys *ss, struct cgroup *cgrp, · 1658 unmodified lines | ||
| 1659 | 1659 | ioc = get_task_io_context(task, GFP_ATOMIC, NUMA_NO_NODE); |
| 1660 | 1660 | if (ioc) { |
| 1661 | 1661 | ioc_cgroup_changed(ioc); |
| 1662 | − put_io_context(ioc, NULL); | |
| 1662 | + put_io_context(ioc); | |
| 1663 | 1663 | } |
| 1664 | 1664 | } |
| 1665 | 1665 | } |
| @@ -642,7 +642,7 @@ static inline void blk_free_request(struct request_queue *q, struct request *rq) · 641 unmodified lines | ||
| 642 | 642 | if (rq->cmd_flags & REQ_ELVPRIV) { |
| 643 | 643 | elv_put_request(q, rq); |
| 644 | 644 | if (rq->elv.icq) |
| 645 | − put_io_context(rq->elv.icq->ioc, q); | |
| 645 | + put_io_context(rq->elv.icq->ioc); | |
| 646 | 646 | } |
| 647 | 647 | |
| 648 | 648 | mempool_free(rq, q->rq.rq_pool); |
| @@ -872,13 +872,15 @@ retry: · 223 unmodified lines | ||
| 872 | 872 | spin_unlock_irq(q->queue_lock); |
| 873 | 873 | |
| 874 | 874 | /* create icq if missing */ |
| 875 | − if (unlikely(et->icq_cache && !icq)) | |
| 875 | + if ((rw_flags & REQ_ELVPRIV) && unlikely(et->icq_cache && !icq)) { | |
| 876 | 876 | icq = ioc_create_icq(q, gfp_mask); |
| 877 | + if (!icq) | |
| 878 | + goto fail_icq; | |
| 879 | + } | |
| 877 | 880 | |
| 878 | − /* rqs are guaranteed to have icq on elv_set_request() if requested */ | |
| 879 | − if (likely(!et->icq_cache || icq)) | |
| 880 | − rq = blk_alloc_request(q, icq, rw_flags, gfp_mask); | |
| 881 | + rq = blk_alloc_request(q, icq, rw_flags, gfp_mask); | |
| 881 | 882 | |
| 883 | +fail_icq: | |
| 882 | 884 | if (unlikely(!rq)) { |
| 883 | 885 | /* |
| 884 | 886 | * Allocation failed presumably due to memory. Undo anything |
| @@ -1210,7 +1212,6 @@ static bool bio_attempt_back_merge(struct request_queue *q, struct request *req, · 325 unmodified lines | ||
| 1210 | 1212 | req->ioprio = ioprio_best(req->ioprio, bio_prio(bio)); |
| 1211 | 1213 | |
| 1212 | 1214 | drive_stat_acct(req, 0); |
| 1213 | − elv_bio_merged(q, req, bio); | |
| 1214 | 1215 | return true; |
| 1215 | 1216 | } |
| 1216 | 1217 | |
| @@ -1241,7 +1242,6 @@ static bool bio_attempt_front_merge(struct request_queue *q, · 24 unmodified lines | ||
| 1241 | 1242 | req->ioprio = ioprio_best(req->ioprio, bio_prio(bio)); |
| 1242 | 1243 | |
| 1243 | 1244 | drive_stat_acct(req, 0); |
| 1244 | − elv_bio_merged(q, req, bio); | |
| 1245 | 1245 | return true; |
| 1246 | 1246 | } |
| 1247 | 1247 | |
| @@ -1255,13 +1255,12 @@ static bool bio_attempt_front_merge(struct request_queue *q, · 7 unmodified lines | ||
| 1255 | 1255 | * on %current's plugged list. Returns %true if merge was successful, |
| 1256 | 1256 | * otherwise %false. |
| 1257 | 1257 | * |
| 1258 | − * This function is called without @q->queue_lock; however, elevator is | |
| 1259 | − * accessed iff there already are requests on the plugged list which in | |
| 1260 | − * turn guarantees validity of the elevator. | |
| 1261 | − * | |
| 1262 | − * Note that, on successful merge, elevator operation | |
| 1263 | − * elevator_bio_merged_fn() will be called without queue lock. Elevator | |
| 1264 | − * must be ready for this. | |
| 1258 | + * Plugging coalesces IOs from the same issuer for the same purpose without | |
| 1259 | + * going through @q->queue_lock. As such it's more of an issuing mechanism | |
| 1260 | + * than scheduling, and the request, while may have elvpriv data, is not | |
| 1261 | + * added on the elevator at this point. In addition, we don't have | |
| 1262 | + * reliable access to the elevator outside queue lock. Only check basic | |
| 1263 | + * merging parameters without querying the elevator. | |
| 1265 | 1264 | */ |
| 1266 | 1265 | static bool attempt_plug_merge(struct request_queue *q, struct bio *bio, |
| 1267 | 1266 | unsigned int *request_count) |
| @@ -1280,10 +1279,10 @@ static bool attempt_plug_merge(struct request_queue *q, struct bio *bio, · 12 unmodified lines | ||
| 1280 | 1279 | |
| 1281 | 1280 | (*request_count)++; |
| 1282 | 1281 | |
| 1283 | − if (rq->q != q) | |
| 1282 | + if (rq->q != q || !blk_rq_merge_ok(rq, bio)) | |
| 1284 | 1283 | continue; |
| 1285 | 1284 | |
| 1286 | − el_ret = elv_try_merge(rq, bio); | |
| 1285 | + el_ret = blk_try_merge(rq, bio); | |
| 1287 | 1286 | if (el_ret == ELEVATOR_BACK_MERGE) { |
| 1288 | 1287 | ret = bio_attempt_back_merge(q, rq, bio); |
| 1289 | 1288 | if (ret) |
| @@ -1345,12 +1344,14 @@ void blk_queue_bio(struct request_queue *q, struct bio *bio) · 55 unmodified lines | ||
| 1345 | 1344 | el_ret = elv_merge(q, &req, bio); |
| 1346 | 1345 | if (el_ret == ELEVATOR_BACK_MERGE) { |
| 1347 | 1346 | if (bio_attempt_back_merge(q, req, bio)) { |
| 1347 | + elv_bio_merged(q, req, bio); | |
| 1348 | 1348 | if (!attempt_back_merge(q, req)) |
| 1349 | 1349 | elv_merged_request(q, req, el_ret); |
| 1350 | 1350 | goto out_unlock; |
| 1351 | 1351 | } |
| 1352 | 1352 | } else if (el_ret == ELEVATOR_FRONT_MERGE) { |
| 1353 | 1353 | if (bio_attempt_front_merge(q, req, bio)) { |
| 1354 | + elv_bio_merged(q, req, bio); | |
| 1354 | 1355 | if (!attempt_front_merge(q, req)) |
| 1355 | 1356 | elv_merged_request(q, req, el_ret); |
| 1356 | 1357 | goto out_unlock; |
| @@ -29,21 +29,6 @@ void get_io_context(struct io_context *ioc) · 28 unmodified lines | ||
| 29 | 29 | } |
| 30 | 30 | EXPORT_SYMBOL(get_io_context); |
| 31 | 31 | |
| 32 | −/* | |
| 33 | − * Releasing ioc may nest into another put_io_context() leading to nested | |
| 34 | − * fast path release. As the ioc's can't be the same, this is okay but | |
| 35 | − * makes lockdep whine. Keep track of nesting and use it as subclass. | |
| 36 | − */ | |
| 37 | −#ifdef CONFIG_LOCKDEP | |
| 38 | −#define ioc_release_depth(q) ((q) ? (q)->ioc_release_depth : 0) | |
| 39 | −#define ioc_release_depth_inc(q) (q)->ioc_release_depth++ | |
| 40 | −#define ioc_release_depth_dec(q) (q)->ioc_release_depth-- | |
| 41 | −#else | |
| 42 | −#define ioc_release_depth(q) 0 | |
| 43 | −#define ioc_release_depth_inc(q) do { } while (0) | |
| 44 | −#define ioc_release_depth_dec(q) do { } while (0) | |
| 45 | −#endif | |
| 46 | − | |
| 47 | 32 | static void icq_free_icq_rcu(struct rcu_head *head) |
| 48 | 33 | { |
| 49 | 34 | struct io_cq *icq = container_of(head, struct io_cq, __rcu_head); |
| @@ -75,11 +60,8 @@ static void ioc_exit_icq(struct io_cq *icq) · 25 unmodified lines | ||
| 75 | 60 | if (rcu_dereference_raw(ioc->icq_hint) == icq) |
| 76 | 61 | rcu_assign_pointer(ioc->icq_hint, NULL); |
| 77 | 62 | |
| 78 | − if (et->ops.elevator_exit_icq_fn) { | |
| 79 | − ioc_release_depth_inc(q); | |
| 63 | + if (et->ops.elevator_exit_icq_fn) | |
| 80 | 64 | et->ops.elevator_exit_icq_fn(icq); |
| 81 | − ioc_release_depth_dec(q); | |
| 82 | − } | |
| 83 | 65 | |
| 84 | 66 | /* |
| 85 | 67 | * @icq->q might have gone away by the time RCU callback runs |
| @@ -98,8 +80,15 @@ static void ioc_release_fn(struct work_struct *work) · 12 unmodified lines | ||
| 98 | 80 | struct io_context *ioc = container_of(work, struct io_context, |
| 99 | 81 | release_work); |
| 100 | 82 | struct request_queue *last_q = NULL; |
| 83 | + unsigned long flags; | |
| 101 | 84 | |
| 102 | − spin_lock_irq(&ioc->lock); | |
| 85 | + /* | |
| 86 | + * Exiting icq may call into put_io_context() through elevator | |
| 87 | + * which will trigger lockdep warning. The ioc's are guaranteed to | |
| 88 | + * be different, use a different locking subclass here. Use | |
| 89 | + * irqsave variant as there's no spin_lock_irq_nested(). | |
| 90 | + */ | |
| 91 | + spin_lock_irqsave_nested(&ioc->lock, flags, 1); | |
| 103 | 92 | |
| 104 | 93 | while (!hlist_empty(&ioc->icq_list)) { |
| 105 | 94 | struct io_cq *icq = hlist_entry(ioc->icq_list.first, |
| @@ -121,15 +110,15 @@ static void ioc_release_fn(struct work_struct *work) · 15 unmodified lines | ||
| 121 | 110 | */ |
| 122 | 111 | if (last_q) { |
| 123 | 112 | spin_unlock(last_q->queue_lock); |
| 124 | − spin_unlock_irq(&ioc->lock); | |
| 113 | + spin_unlock_irqrestore(&ioc->lock, flags); | |
| 125 | 114 | blk_put_queue(last_q); |
| 126 | 115 | } else { |
| 127 | − spin_unlock_irq(&ioc->lock); | |
| 116 | + spin_unlock_irqrestore(&ioc->lock, flags); | |
| 128 | 117 | } |
| 129 | 118 | |
| 130 | 119 | last_q = this_q; |
| 131 | − spin_lock_irq(this_q->queue_lock); | |
| 132 | − spin_lock(&ioc->lock); | |
| 120 | + spin_lock_irqsave(this_q->queue_lock, flags); | |
| 121 | + spin_lock_nested(&ioc->lock, 1); | |
| 133 | 122 | continue; |
| 134 | 123 | } |
| 135 | 124 | ioc_exit_icq(icq); |
| @@ -137,10 +126,10 @@ static void ioc_release_fn(struct work_struct *work) · 1 unmodified line | ||
| 137 | 126 | |
| 138 | 127 | if (last_q) { |
| 139 | 128 | spin_unlock(last_q->queue_lock); |
| 140 | − spin_unlock_irq(&ioc->lock); | |
| 129 | + spin_unlock_irqrestore(&ioc->lock, flags); | |
| 141 | 130 | blk_put_queue(last_q); |
| 142 | 131 | } else { |
| 143 | − spin_unlock_irq(&ioc->lock); | |
| 132 | + spin_unlock_irqrestore(&ioc->lock, flags); | |
| 144 | 133 | } |
| 145 | 134 | |
| 146 | 135 | kmem_cache_free(iocontext_cachep, ioc); |
| @@ -149,79 +138,29 @@ static void ioc_release_fn(struct work_struct *work) · 2 unmodified lines | ||
| 149 | 138 | /** |
| 150 | 139 | * put_io_context - put a reference of io_context |
| 151 | 140 | * @ioc: io_context to put |
| 152 | − * @locked_q: request_queue the caller is holding queue_lock of (hint) | |
| 153 | 141 | * |
| 154 | 142 | * Decrement reference count of @ioc and release it if the count reaches |
| 155 | − * zero. If the caller is holding queue_lock of a queue, it can indicate | |
| 156 | − * that with @locked_q. This is an optimization hint and the caller is | |
| 157 | − * allowed to pass in %NULL even when it's holding a queue_lock. | |
| 143 | + * zero. | |
| 158 | 144 | */ |
| 159 | −void put_io_context(struct io_context *ioc, struct request_queue *locked_q) | |
| 145 | +void put_io_context(struct io_context *ioc) | |
| 160 | 146 | { |
| 161 | − struct request_queue *last_q = locked_q; | |
| 162 | 147 | unsigned long flags; |
| 163 | 148 | |
| 164 | 149 | if (ioc == NULL) |
| 165 | 150 | return; |
| 166 | 151 | |
| 167 | 152 | BUG_ON(atomic_long_read(&ioc->refcount) <= 0); |
| 168 | − if (locked_q) | |
| 169 | − lockdep_assert_held(locked_q->queue_lock); | |
| 170 | − | |
| 171 | − if (!atomic_long_dec_and_test(&ioc->refcount)) | |
| 172 | − return; | |
| 173 | 153 | |
| 174 | 154 | /* |
| 175 | − * Destroy @ioc. This is a bit messy because icq's are chained | |
| 176 | − * from both ioc and queue, and ioc->lock nests inside queue_lock. | |
| 177 | − * The inner ioc->lock should be held to walk our icq_list and then | |
| 178 | − * for each icq the outer matching queue_lock should be grabbed. | |
| 179 | − * ie. We need to do reverse-order double lock dancing. | |
| 180 | − * | |
| 181 | − * Another twist is that we are often called with one of the | |
| 182 | − * matching queue_locks held as indicated by @locked_q, which | |
| 183 | − * prevents performing double-lock dance for other queues. | |
| 184 | − * | |
| 185 | − * So, we do it in two stages. The fast path uses the queue_lock | |
| 186 | − * the caller is holding and, if other queues need to be accessed, | |
| 187 | − * uses trylock to avoid introducing locking dependency. This can | |
| 188 | − * handle most cases, especially if @ioc was performing IO on only | |
| 189 | − * single device. | |
| 190 | − * | |
| 191 | − * If trylock doesn't cut it, we defer to @ioc->release_work which | |
| 192 | − * can do all the double-locking dancing. | |
| 155 | + * Releasing ioc requires reverse order double locking and we may | |
| 156 | + * already be holding a queue_lock. Do it asynchronously from wq. | |
| 193 | 157 | */ |
| 194 | − spin_lock_irqsave_nested(&ioc->lock, flags, | |
| 195 | − ioc_release_depth(locked_q)); | |
| 196 | − | |
| 197 | − while (!hlist_empty(&ioc->icq_list)) { | |
| 198 | − struct io_cq *icq = hlist_entry(ioc->icq_list.first, | |
| 199 | − struct io_cq, ioc_node); | |
| 200 | − struct request_queue *this_q = icq->q; | |
| 201 | − | |
| 202 | − if (this_q != last_q) { | |
| 203 | − if (last_q && last_q != locked_q) | |
| 204 | − spin_unlock(last_q->queue_lock); | |
| 205 | − last_q = NULL; | |
| 206 | − | |
| 207 | − if (!spin_trylock(this_q->queue_lock)) | |
| 208 | − break; | |
| 209 | − last_q = this_q; | |
| 210 | − continue; | |
| 211 | − } | |
| 212 | − ioc_exit_icq(icq); | |
| 158 | + if (atomic_long_dec_and_test(&ioc->refcount)) { | |
| 159 | + spin_lock_irqsave(&ioc->lock, flags); | |
| 160 | + if (!hlist_empty(&ioc->icq_list)) | |
| 161 | + schedule_work(&ioc->release_work); | |
| 162 | + spin_unlock_irqrestore(&ioc->lock, flags); | |
| 213 | 163 | } |
| 214 | − | |
| 215 | − if (last_q && last_q != locked_q) | |
| 216 | − spin_unlock(last_q->queue_lock); | |
| 217 | − | |
| 218 | − spin_unlock_irqrestore(&ioc->lock, flags); | |
| 219 | − | |
| 220 | − /* if no icq is left, we're done; otherwise, kick release_work */ | |
| 221 | − if (hlist_empty(&ioc->icq_list)) | |
| 222 | − kmem_cache_free(iocontext_cachep, ioc); | |
| 223 | − else | |
| 224 | − schedule_work(&ioc->release_work); | |
| 225 | 164 | } |
| 226 | 165 | EXPORT_SYMBOL(put_io_context); |
| 227 | 166 | |
| @@ -236,7 +175,7 @@ void exit_io_context(struct task_struct *task) · 8 unmodified lines | ||
| 236 | 175 | task_unlock(task); |
| 237 | 176 | |
| 238 | 177 | atomic_dec(&ioc->nr_tasks); |
| 239 | − put_io_context(ioc, NULL); | |
| 178 | + put_io_context(ioc); | |
| 240 | 179 | } |
| 241 | 180 | |
| 242 | 181 | /** |
| @@ -471,3 +471,40 @@ int blk_attempt_req_merge(struct request_queue *q, struct request *rq, · 470 unmodified lines | ||
| 471 | 471 | { |
| 472 | 472 | return attempt_merge(q, rq, next); |
| 473 | 473 | } |
| 474 | + | |
| 475 | +bool blk_rq_merge_ok(struct request *rq, struct bio *bio) | |
| 476 | +{ | |
| 477 | + if (!rq_mergeable(rq)) | |
| 478 | + return false; | |
| 479 | + | |
| 480 | + /* don't merge file system requests and discard requests */ | |
| 481 | + if ((bio->bi_rw & REQ_DISCARD) != (rq->bio->bi_rw & REQ_DISCARD)) | |
| 482 | + return false; | |
| 483 | + | |
| 484 | + /* don't merge discard requests and secure discard requests */ | |
| 485 | + if ((bio->bi_rw & REQ_SECURE) != (rq->bio->bi_rw & REQ_SECURE)) | |
| 486 | + return false; | |
| 487 | + | |
| 488 | + /* different data direction or already started, don't merge */ | |
| 489 | + if (bio_data_dir(bio) != rq_data_dir(rq)) | |
| 490 | + return false; | |
| 491 | + | |
| 492 | + /* must be same device and not a special request */ | |
| 493 | + if (rq->rq_disk != bio->bi_bdev->bd_disk || rq->special) | |
| 494 | + return false; | |
| 495 | + | |
| 496 | + /* only merge integrity protected bio into ditto rq */ | |
| 497 | + if (bio_integrity(bio) != blk_integrity_rq(rq)) | |
| 498 | + return false; | |
| 499 | + | |
| 500 | + return true; | |
| 501 | +} | |
| 502 | + | |
| 503 | +int blk_try_merge(struct request *rq, struct bio *bio) | |
| 504 | +{ | |
| 505 | + if (blk_rq_pos(rq) + blk_rq_sectors(rq) == bio->bi_sector) | |
| 506 | + return ELEVATOR_BACK_MERGE; | |
| 507 | + else if (blk_rq_pos(rq) - bio_sectors(bio) == bio->bi_sector) | |
| 508 | + return ELEVATOR_FRONT_MERGE; | |
| 509 | + return ELEVATOR_NO_MERGE; | |
| 510 | +} | |
| @@ -137,6 +137,8 @@ int blk_attempt_req_merge(struct request_queue *q, struct request *rq, · 136 unmodified lines | ||
| 137 | 137 | struct request *next); |
| 138 | 138 | void blk_recalc_rq_segments(struct request *rq); |
| 139 | 139 | void blk_rq_set_mixed_merge(struct request *rq); |
| 140 | +bool blk_rq_merge_ok(struct request *rq, struct bio *bio); | |
| 141 | +int blk_try_merge(struct request *rq, struct bio *bio); | |
| 140 | 142 | |
| 141 | 143 | void blk_queue_congestion_threshold(struct request_queue *q); |
| 142 | 144 | |
| @@ -983,7 +983,8 @@ void bsg_unregister_queue(struct request_queue *q) · 982 unmodified lines | ||
| 983 | 983 | |
| 984 | 984 | mutex_lock(&bsg_mutex); |
| 985 | 985 | idr_remove(&bsg_minor_idr, bcd->minor); |
| 986 | − sysfs_remove_link(&q->kobj, "bsg"); | |
| 986 | + if (q->kobj.sd) | |
| 987 | + sysfs_remove_link(&q->kobj, "bsg"); | |
| 987 | 988 | device_unregister(bcd->class_dev); |
| 988 | 989 | bcd->class_dev = NULL; |
| 989 | 990 | kref_put(&bcd->ref, bsg_kref_release_function); |
| @@ -1699,18 +1699,11 @@ static int cfq_allow_merge(struct request_queue *q, struct request *rq, · 1698 unmodified lines | ||
| 1699 | 1699 | |
| 1700 | 1700 | /* |
| 1701 | 1701 | * Lookup the cfqq that this bio will be queued with and allow |
| 1702 | − * merge only if rq is queued there. This function can be called | |
| 1703 | − * from plug merge without queue_lock. In such cases, ioc of @rq | |
| 1704 | − * and %current are guaranteed to be equal. Avoid lookup which | |
| 1705 | − * requires queue_lock by using @rq's cic. | |
| 1702 | + * merge only if rq is queued there. | |
| 1706 | 1703 | */ |
| 1707 | − if (current->io_context == RQ_CIC(rq)->icq.ioc) { | |
| 1708 | − cic = RQ_CIC(rq); | |
| 1709 | − } else { | |
| 1710 | − cic = cfq_cic_lookup(cfqd, current->io_context); | |
| 1711 | − if (!cic) | |
| 1712 | − return false; | |
| 1713 | − } | |
| 1704 | + cic = cfq_cic_lookup(cfqd, current->io_context); | |
| 1705 | + if (!cic) | |
| 1706 | + return false; | |
| 1714 | 1707 | |
| 1715 | 1708 | cfqq = cic_to_cfqq(cic, cfq_bio_sync(bio)); |
| 1716 | 1709 | return cfqq == RQ_CFQQ(rq); |
| @@ -1794,7 +1787,7 @@ __cfq_slice_expired(struct cfq_data *cfqd, struct cfq_queue *cfqq, · 77 unmodified lines | ||
| 1794 | 1787 | cfqd->active_queue = NULL; |
| 1795 | 1788 | |
| 1796 | 1789 | if (cfqd->active_cic) { |
| 1797 | − put_io_context(cfqd->active_cic->icq.ioc, cfqd->queue); | |
| 1790 | + put_io_context(cfqd->active_cic->icq.ioc); | |
| 1798 | 1791 | cfqd->active_cic = NULL; |
| 1799 | 1792 | } |
| 1800 | 1793 | } |
| @@ -3117,7 +3110,7 @@ cfq_should_preempt(struct cfq_data *cfqd, struct cfq_queue *new_cfqq, · 1316 unmodified lines | ||
| 3117 | 3110 | */ |
| 3118 | 3111 | static void cfq_preempt_queue(struct cfq_data *cfqd, struct cfq_queue *cfqq) |
| 3119 | 3112 | { |
| 3120 | − struct cfq_queue *old_cfqq = cfqd->active_queue; | |
| 3113 | + enum wl_type_t old_type = cfqq_type(cfqd->active_queue); | |
| 3121 | 3114 | |
| 3122 | 3115 | cfq_log_cfqq(cfqd, cfqq, "preempt"); |
| 3123 | 3116 | cfq_slice_expired(cfqd, 1); |
| @@ -3126,7 +3119,7 @@ static void cfq_preempt_queue(struct cfq_data *cfqd, struct cfq_queue *cfqq) · 2 unmodified lines | ||
| 3126 | 3119 | * workload type is changed, don't save slice, otherwise preempt |
| 3127 | 3120 | * doesn't happen |
| 3128 | 3121 | */ |
| 3129 | − if (cfqq_type(old_cfqq) != cfqq_type(cfqq)) | |
| 3122 | + if (old_type != cfqq_type(cfqq)) | |
| 3130 | 3123 | cfqq->cfqg->saved_workload_slice = 0; |
| 3131 | 3124 | |
| 3132 | 3125 | /* |
| @@ -70,39 +70,9 @@ static int elv_iosched_allow_merge(struct request *rq, struct bio *bio) · 69 unmodified lines | ||
| 70 | 70 | /* |
| 71 | 71 | * can we safely merge with this request? |
| 72 | 72 | */ |
| 73 | −int elv_rq_merge_ok(struct request *rq, struct bio *bio) | |
| 73 | +bool elv_rq_merge_ok(struct request *rq, struct bio *bio) | |
| 74 | 74 | { |
| 75 | − if (!rq_mergeable(rq)) | |
| 76 | − return 0; | |
| 77 | − | |
| 78 | − /* | |
| 79 | − * Don't merge file system requests and discard requests | |
| 80 | − */ | |
| 81 | − if ((bio->bi_rw & REQ_DISCARD) != (rq->bio->bi_rw & REQ_DISCARD)) | |
| 82 | − return 0; | |
| 83 | − | |
| 84 | − /* | |
| 85 | − * Don't merge discard requests and secure discard requests | |
| 86 | − */ | |
| 87 | − if ((bio->bi_rw & REQ_SECURE) != (rq->bio->bi_rw & REQ_SECURE)) | |
| 88 | − return 0; | |
| 89 | − | |
| 90 | − /* | |
| 91 | − * different data direction or already started, don't merge | |
| 92 | − */ | |
| 93 | − if (bio_data_dir(bio) != rq_data_dir(rq)) | |
| 94 | − return 0; | |
| 95 | − | |
| 96 | − /* | |
| 97 | − * must be same device and not a special request | |
| 98 | − */ | |
| 99 | − if (rq->rq_disk != bio->bi_bdev->bd_disk || rq->special) | |
| 100 | − return 0; | |
| 101 | − | |
| 102 | − /* | |
| 103 | − * only merge integrity protected bio into ditto rq | |
| 104 | − */ | |
| 105 | − if (bio_integrity(bio) != blk_integrity_rq(rq)) | |
| 75 | + if (!blk_rq_merge_ok(rq, bio)) | |
| 106 | 76 | return 0; |
| 107 | 77 | |
| 108 | 78 | if (!elv_iosched_allow_merge(rq, bio)) |
| @@ -112,23 +82,6 @@ int elv_rq_merge_ok(struct request *rq, struct bio *bio) · 3 unmodified lines | ||
| 112 | 82 | } |
| 113 | 83 | EXPORT_SYMBOL(elv_rq_merge_ok); |
| 114 | 84 | |
| 115 | −int elv_try_merge(struct request *__rq, struct bio *bio) | |
| 116 | −{ | |
| 117 | − int ret = ELEVATOR_NO_MERGE; | |
| 118 | − | |
| 119 | − /* | |
| 120 | − * we can merge and sequence is ok, check if it's possible | |
| 121 | − */ | |
| 122 | − if (elv_rq_merge_ok(__rq, bio)) { | |
| 123 | − if (blk_rq_pos(__rq) + blk_rq_sectors(__rq) == bio->bi_sector) | |
| 124 | − ret = ELEVATOR_BACK_MERGE; | |
| 125 | − else if (blk_rq_pos(__rq) - bio_sectors(bio) == bio->bi_sector) | |
| 126 | − ret = ELEVATOR_FRONT_MERGE; | |
| 127 | − } | |
| 128 | − | |
| 129 | − return ret; | |
| 130 | −} | |
| 131 | − | |
| 132 | 85 | static struct elevator_type *elevator_find(const char *name) |
| 133 | 86 | { |
| 134 | 87 | struct elevator_type *e; |
| @@ -478,8 +431,8 @@ int elv_merge(struct request_queue *q, struct request **req, struct bio *bio) · 343 unmodified lines | ||
| 478 | 431 | /* |
| 479 | 432 | * First try one-hit cache. |
| 480 | 433 | */ |
| 481 | − if (q->last_merge) { | |
| 482 | − ret = elv_try_merge(q->last_merge, bio); | |
| 434 | + if (q->last_merge && elv_rq_merge_ok(q->last_merge, bio)) { | |
| 435 | + ret = blk_try_merge(q->last_merge, bio); | |
| 483 | 436 | if (ret != ELEVATOR_NO_MERGE) { |
| 484 | 437 | *req = q->last_merge; |
| 485 | 438 | return ret; |
| @@ -21,8 +21,6 @@ · 20 unmodified lines | ||
| 21 | 21 | #include <linux/percpu.h> |
| 22 | 22 | #include <asm/byteorder.h> |
| 23 | 23 | |
| 24 | −static DEFINE_PER_CPU(u64[80], msg_schedule); | |
| 25 | − | |
| 26 | 24 | static inline u64 Ch(u64 x, u64 y, u64 z) |
| 27 | 25 | { |
| 28 | 26 | return z ^ (x & (y ^ z)); |
| @@ -33,11 +31,6 @@ static inline u64 Maj(u64 x, u64 y, u64 z) · 4 unmodified lines | ||
| 33 | 31 | return (x & y) | (z & (x | y)); |
| 34 | 32 | } |
| 35 | 33 | |
| 36 | −static inline u64 RORu64(u64 x, u64 y) | |
| 37 | −{ | |
| 38 | − return (x >> y) | (x << (64 - y)); | |
| 39 | −} | |
| 40 | − | |
| 41 | 34 | static const u64 sha512_K[80] = { |
| 42 | 35 | 0x428a2f98d728ae22ULL, 0x7137449123ef65cdULL, 0xb5c0fbcfec4d3b2fULL, |
| 43 | 36 | 0xe9b5dba58189dbbcULL, 0x3956c25bf348b538ULL, 0x59f111f1b605d019ULL, |
| @@ -68,10 +61,10 @@ static const u64 sha512_K[80] = { · 24 unmodified lines | ||
| 68 | 61 | 0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL, |
| 69 | 62 | }; |
| 70 | 63 | |
| 71 | −#define e0(x) (RORu64(x,28) ^ RORu64(x,34) ^ RORu64(x,39)) | |
| 72 | −#define e1(x) (RORu64(x,14) ^ RORu64(x,18) ^ RORu64(x,41)) | |
| 73 | −#define s0(x) (RORu64(x, 1) ^ RORu64(x, 8) ^ (x >> 7)) | |
| 74 | −#define s1(x) (RORu64(x,19) ^ RORu64(x,61) ^ (x >> 6)) | |
| 64 | +#define e0(x) (ror64(x,28) ^ ror64(x,34) ^ ror64(x,39)) | |
| 65 | +#define e1(x) (ror64(x,14) ^ ror64(x,18) ^ ror64(x,41)) | |
| 66 | +#define s0(x) (ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7)) | |
| 67 | +#define s1(x) (ror64(x,19) ^ ror64(x,61) ^ (x >> 6)) | |
| 75 | 68 | |
| 76 | 69 | static inline void LOAD_OP(int I, u64 *W, const u8 *input) |
| 77 | 70 | { |
| @@ -80,7 +73,7 @@ static inline void LOAD_OP(int I, u64 *W, const u8 *input) · 2 unmodified lines | ||
| 80 | 73 | |
| 81 | 74 | static inline void BLEND_OP(int I, u64 *W) |
| 82 | 75 | { |
| 83 | − W[I] = s1(W[I-2]) + W[I-7] + s0(W[I-15]) + W[I-16]; | |
| 76 | + W[I & 15] += s1(W[(I-2) & 15]) + W[(I-7) & 15] + s0(W[(I-15) & 15]); | |
| 84 | 77 | } |
| 85 | 78 | |
| 86 | 79 | static void |
| @@ -89,15 +82,7 @@ sha512_transform(u64 *state, const u8 *input) · 2 unmodified lines | ||
| 89 | 82 | u64 a, b, c, d, e, f, g, h, t1, t2; |
| 90 | 83 | |
| 91 | 84 | int i; |
| 92 | − u64 *W = get_cpu_var(msg_schedule); | |
| 93 | − | |
| 94 | − /* load the input */ | |
| 95 | − for (i = 0; i < 16; i++) | |
| 96 | − LOAD_OP(i, W, input); | |
| 97 | − | |
| 98 | − for (i = 16; i < 80; i++) { | |
| 99 | − BLEND_OP(i, W); | |
| 100 | − } | |
| 85 | + u64 W[16]; | |
| 101 | 86 | |
| 102 | 87 | /* load the state into our registers */ |
| 103 | 88 | a=state[0]; b=state[1]; c=state[2]; d=state[3]; |
| @@ -105,21 +90,35 @@ sha512_transform(u64 *state, const u8 *input) · 1 unmodified line | ||
| 105 | 90 | |
| 106 | 91 | /* now iterate */ |
| 107 | 92 | for (i=0; i<80; i+=8) { |
| 108 | − t1 = h + e1(e) + Ch(e,f,g) + sha512_K[i ] + W[i ]; | |
| 93 | + if (!(i & 8)) { | |
| 94 | + int j; | |
| 95 | + | |
| 96 | + if (i < 16) { | |
| 97 | + /* load the input */ | |
| 98 | + for (j = 0; j < 16; j++) | |
| 99 | + LOAD_OP(i + j, W, input); | |
| 100 | + } else { | |
| 101 | + for (j = 0; j < 16; j++) { | |
| 102 | + BLEND_OP(i + j, W); | |
| 103 | + } | |
| 104 | + } | |
| 105 | + } | |
| 106 | + | |
| 107 | + t1 = h + e1(e) + Ch(e,f,g) + sha512_K[i ] + W[(i & 15)]; | |
| 109 | 108 | t2 = e0(a) + Maj(a,b,c); d+=t1; h=t1+t2; |
| 110 | − t1 = g + e1(d) + Ch(d,e,f) + sha512_K[i+1] + W[i+1]; | |
| 109 | + t1 = g + e1(d) + Ch(d,e,f) + sha512_K[i+1] + W[(i & 15) + 1]; | |
| 111 | 110 | t2 = e0(h) + Maj(h,a,b); c+=t1; g=t1+t2; |
| 112 | − t1 = f + e1(c) + Ch(c,d,e) + sha512_K[i+2] + W[i+2]; | |
| 111 | + t1 = f + e1(c) + Ch(c,d,e) + sha512_K[i+2] + W[(i & 15) + 2]; | |
| 113 | 112 | t2 = e0(g) + Maj(g,h,a); b+=t1; f=t1+t2; |
| 114 | − t1 = e + e1(b) + Ch(b,c,d) + sha512_K[i+3] + W[i+3]; | |
| 113 | + t1 = e + e1(b) + Ch(b,c,d) + sha512_K[i+3] + W[(i & 15) + 3]; | |
| 115 | 114 | t2 = e0(f) + Maj(f,g,h); a+=t1; e=t1+t2; |
| 116 | − t1 = d + e1(a) + Ch(a,b,c) + sha512_K[i+4] + W[i+4]; | |
| 115 | + t1 = d + e1(a) + Ch(a,b,c) + sha512_K[i+4] + W[(i & 15) + 4]; | |
| 117 | 116 | t2 = e0(e) + Maj(e,f,g); h+=t1; d=t1+t2; |
| 118 | − t1 = c + e1(h) + Ch(h,a,b) + sha512_K[i+5] + W[i+5]; | |
| 117 | + t1 = c + e1(h) + Ch(h,a,b) + sha512_K[i+5] + W[(i & 15) + 5]; | |
| 119 | 118 | t2 = e0(d) + Maj(d,e,f); g+=t1; c=t1+t2; |
| 120 | − t1 = b + e1(g) + Ch(g,h,a) + sha512_K[i+6] + W[i+6]; | |
| 119 | + t1 = b + e1(g) + Ch(g,h,a) + sha512_K[i+6] + W[(i & 15) + 6]; | |
| 121 | 120 | t2 = e0(c) + Maj(c,d,e); f+=t1; b=t1+t2; |
| 122 | − t1 = a + e1(f) + Ch(f,g,h) + sha512_K[i+7] + W[i+7]; | |
| 121 | + t1 = a + e1(f) + Ch(f,g,h) + sha512_K[i+7] + W[(i & 15) + 7]; | |
| 123 | 122 | t2 = e0(b) + Maj(b,c,d); e+=t1; a=t1+t2; |
| 124 | 123 | } |
| 125 | 124 | |
| @@ -128,8 +127,6 @@ sha512_transform(u64 *state, const u8 *input) · 2 unmodified lines | ||
| 128 | 127 | |
| 129 | 128 | /* erase our data */ |
| 130 | 129 | a = b = c = d = e = f = g = h = t1 = t2 = 0; |
| 131 | − memset(W, 0, sizeof(__get_cpu_var(msg_schedule))); | |
| 132 | − put_cpu_var(msg_schedule); | |
| 133 | 130 | } |
| 134 | 131 | |
| 135 | 132 | static int |
| @@ -19,12 +19,12 @@ obj-y += acpi.o \ · 18 unmodified lines | ||
| 19 | 19 | |
| 20 | 20 | # All the builtin files are in the "acpi." module_param namespace. |
| 21 | 21 | acpi-y += osl.o utils.o reboot.o |
| 22 | −acpi-y += atomicio.o | |
| 22 | +acpi-y += nvs.o | |
| 23 | 23 | |
| 24 | 24 | # sleep related files |
| 25 | 25 | acpi-y += wakeup.o |
| 26 | 26 | acpi-y += sleep.o |
| 27 | −acpi-$(CONFIG_ACPI_SLEEP) += proc.o nvs.o | |
| 27 | +acpi-$(CONFIG_ACPI_SLEEP) += proc.o | |
| 28 | 28 | |
| 29 | 29 | |
| 30 | 30 | # |
| @@ -8,41 +8,151 @@ ccflags-$(CONFIG_ACPI_DEBUG) += -DACPI_DEBUG_OUTPUT · 7 unmodified lines | ||
| 8 | 8 | # use acpi.o to put all files here into acpi.o modparam namespace |
| 9 | 9 | obj-y += acpi.o |
| 10 | 10 | |
| 11 | −acpi-y := dsfield.o dsmthdat.o dsopcode.o dswexec.o dswscope.o \ | |
| 12 | − dsmethod.o dsobject.o dsutils.o dswload.o dswstate.o \ | |
| 13 | − dsinit.o dsargs.o dscontrol.o dswload2.o | |
| 11 | +acpi-y := \ | |
| 12 | + dsargs.o \ | |
| 13 | + dscontrol.o \ | |
| 14 | + dsfield.o \ | |
| 15 | + dsinit.o \ | |
| 16 | + dsmethod.o \ | |
| 17 | + dsmthdat.o \ | |
| 18 | + dsobject.o \ | |
| 19 | + dsopcode.o \ | |
| 20 | + dsutils.o \ | |
| 21 | + dswexec.o \ | |
| 22 | + dswload.o \ | |
| 23 | + dswload2.o \ | |
| 24 | + dswscope.o \ | |
| 25 | + dswstate.o | |
| 14 | 26 | |
| 15 | −acpi-y += evevent.o evregion.o evsci.o evxfevnt.o \ | |
| 16 | − evmisc.o evrgnini.o evxface.o evxfregn.o \ | |
| 17 | − evgpe.o evgpeblk.o evgpeinit.o evgpeutil.o evxfgpe.o evglock.o | |
| 27 | +acpi-y += \ | |
| 28 | + evevent.o \ | |
| 29 | + evgpe.o \ | |
| 30 | + evgpeblk.o \ | |
| 31 | + evgpeinit.o \ | |
| 32 | + evgpeutil.o \ | |
| 33 | + evglock.o \ | |
| 34 | + evmisc.o \ | |
| 35 | + evregion.o \ | |
| 36 | + evrgnini.o \ | |
| 37 | + evsci.o \ | |
| 38 | + evxface.o \ | |
| 39 | + evxfevnt.o \ | |
| 40 | + evxfgpe.o \ | |
| 41 | + evxfregn.o | |
| 18 | 42 | |
| 19 | −acpi-y += exconfig.o exfield.o exnames.o exoparg6.o exresolv.o exstorob.o\ | |
| 20 | − exconvrt.o exfldio.o exoparg1.o exprep.o exresop.o exsystem.o\ | |
| 21 | − excreate.o exmisc.o exoparg2.o exregion.o exstore.o exutils.o \ | |
| 22 | − exdump.o exmutex.o exoparg3.o exresnte.o exstoren.o exdebug.o | |
| 43 | +acpi-y += \ | |
| 44 | + exconfig.o \ | |
| 45 | + exconvrt.o \ | |
| 46 | + excreate.o \ | |
| 47 | + exdebug.o \ | |
| 48 | + exdump.o \ | |
| 49 | + exfield.o \ | |
| 50 | + exfldio.o \ | |
| 51 | + exmutex.o \ | |
| 52 | + exnames.o \ | |
| 53 | + exoparg1.o \ | |
| 54 | + exoparg2.o \ | |
| 55 | + exoparg3.o \ | |
| 56 | + exoparg6.o \ | |
| 57 | + exprep.o \ | |
| 58 | + exmisc.o \ | |
| 59 | + exregion.o \ | |
| 60 | + exresnte.o \ | |
| 61 | + exresolv.o \ | |
| 62 | + exresop.o \ | |
| 63 | + exstore.o \ | |
| 64 | + exstoren.o \ | |
| 65 | + exstorob.o \ | |
| 66 | + exsystem.o \ | |
| 67 | + exutils.o | |
| 23 | 68 | |
| 24 | −acpi-y += hwacpi.o hwgpe.o hwregs.o hwsleep.o hwxface.o hwvalid.o hwpci.o | |
| 69 | +acpi-y += \ | |
| 70 | + hwacpi.o \ | |
| 71 | + hwgpe.o \ | |
| 72 | + hwpci.o \ | |
| 73 | + hwregs.o \ | |
| 74 | + hwsleep.o \ | |
| 75 | + hwvalid.o \ | |
| 76 | + hwxface.o | |
| 25 | 77 | |
| 26 | 78 | acpi-$(ACPI_FUTURE_USAGE) += hwtimer.o |
| 27 | 79 | |
| 28 | −acpi-y += nsaccess.o nsload.o nssearch.o nsxfeval.o \ | |
| 29 | − nsalloc.o nseval.o nsnames.o nsutils.o nsxfname.o \ | |
| 30 | − nsdump.o nsinit.o nsobject.o nswalk.o nsxfobj.o \ | |
| 31 | − nsparse.o nspredef.o nsrepair.o nsrepair2.o | |
| 80 | +acpi-y += \ | |
| 81 | + nsaccess.o \ | |
| 82 | + nsalloc.o \ | |
| 83 | + nsdump.o \ | |
| 84 | + nseval.o \ | |
| 85 | + nsinit.o \ | |
| 86 | + nsload.o \ | |
| 87 | + nsnames.o \ | |
| 88 | + nsobject.o \ | |
| 89 | + nsparse.o \ | |
| 90 | + nspredef.o \ | |
| 91 | + nsrepair.o \ | |
| 92 | + nsrepair2.o \ | |
| 93 | + nssearch.o \ | |
| 94 | + nsutils.o \ | |
| 95 | + nswalk.o \ | |
| 96 | + nsxfeval.o \ | |
| 97 | + nsxfname.o \ | |
| 98 | + nsxfobj.o | |
| 32 | 99 | |
| 33 | 100 | acpi-$(ACPI_FUTURE_USAGE) += nsdumpdv.o |
| 34 | 101 | |
| 35 | −acpi-y += psargs.o psparse.o psloop.o pstree.o pswalk.o \ | |
| 36 | − psopcode.o psscope.o psutils.o psxface.o | |
| 102 | +acpi-y += \ | |
| 103 | + psargs.o \ | |
| 104 | + psloop.o \ | |
| 105 | + psopcode.o \ | |
| 106 | + psparse.o \ | |
| 107 | + psscope.o \ | |
| 108 | + pstree.o \ | |
| 109 | + psutils.o \ | |
| 110 | + pswalk.o \ | |
| 111 | + psxface.o | |
| 37 | 112 | |
| 38 | −acpi-y += rsaddr.o rscreate.o rsinfo.o rsio.o rslist.o rsmisc.o rsxface.o \ | |
| 39 | − rscalc.o rsirq.o rsmemory.o rsutils.o | |
| 113 | +acpi-y += \ | |
| 114 | + rsaddr.o \ | |
| 115 | + rscalc.o \ | |
| 116 | + rscreate.o \ | |
| 117 | + rsinfo.o \ | |
| 118 | + rsio.o \ | |
| 119 | + rsirq.o \ | |
| 120 | + rslist.o \ | |
| 121 | + rsmemory.o \ | |
| 122 | + rsmisc.o \ | |
| 123 | + rsserial.o \ | |
| 124 | + rsutils.o \ | |
| 125 | + rsxface.o | |
| 40 | 126 | |
| 41 | 127 | acpi-$(ACPI_FUTURE_USAGE) += rsdump.o |
| 42 | 128 | |
| 43 | −acpi-y += tbxface.o tbinstal.o tbutils.o tbfind.o tbfadt.o tbxfroot.o | |
| 129 | +acpi-y += \ | |
| 130 | + tbfadt.o \ | |
| 131 | + tbfind.o \ | |
| 132 | + tbinstal.o \ | |
| 133 | + tbutils.o \ | |
| 134 | + tbxface.o \ | |
| 135 | + tbxfroot.o | |
| 44 | 136 | |
| 45 | −acpi-y += utalloc.o utdebug.o uteval.o utinit.o utmisc.o utxface.o \ | |
| 46 | − utcopy.o utdelete.o utglobal.o utmath.o utobject.o \ | |
| 47 | − utstate.o utmutex.o utobject.o utresrc.o utlock.o utids.o \ | |
| 48 | − utosi.o utxferror.o utdecode.o | |
| 137 | +acpi-y += \ | |
| 138 | + utaddress.o \ | |
| 139 | + utalloc.o \ | |
| 140 | + utcopy.o \ | |
| 141 | + utdebug.o \ | |
| 142 | + utdecode.o \ | |
| 143 | + utdelete.o \ | |
| 144 | + uteval.o \ | |
| 145 | + utglobal.o \ | |
| 146 | + utids.o \ | |
| 147 | + utinit.o \ | |
| 148 | + utlock.o \ | |
| 149 | + utmath.o \ | |
| 150 | + utmisc.o \ | |
| 151 | + utmutex.o \ | |
| 152 | + utobject.o \ | |
| 153 | + utosi.o \ | |
| 154 | + utresrc.o \ | |
| 155 | + utstate.o \ | |
| 156 | + utxface.o \ | |
| 157 | + utxferror.o \ | |
| 158 | + utxfmutex.o | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -123,6 +123,10 @@ · 111 unmodified lines | ||
| 123 | 123 | |
| 124 | 124 | #define ACPI_MAX_SLEEP 2000 /* Two seconds */ |
| 125 | 125 | |
| 126 | +/* Address Range lists are per-space_id (Memory and I/O only) */ | |
| 127 | + | |
| 128 | +#define ACPI_ADDRESS_RANGE_MAX 2 | |
| 129 | + | |
| 126 | 130 | /****************************************************************************** |
| 127 | 131 | * |
| 128 | 132 | * ACPI Specification constants (Do not change unless the specification changes) |
| @@ -202,9 +206,10 @@ · 73 unmodified lines | ||
| 202 | 206 | #define ACPI_RSDP_CHECKSUM_LENGTH 20 |
| 203 | 207 | #define ACPI_RSDP_XCHECKSUM_LENGTH 36 |
| 204 | 208 | |
| 205 | −/* SMBus and IPMI bidirectional buffer size */ | |
| 209 | +/* SMBus, GSBus and IPMI bidirectional buffer size */ | |
| 206 | 210 | |
| 207 | 211 | #define ACPI_SMBUS_BUFFER_SIZE 34 |
| 212 | +#define ACPI_GSBUS_BUFFER_SIZE 34 | |
| 208 | 213 | #define ACPI_IPMI_BUFFER_SIZE 66 |
| 209 | 214 | |
| 210 | 215 | /* _sx_d and _sx_w control methods */ |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -162,6 +162,7 @@ acpi_status acpi_ev_initialize_op_regions(void); · 150 unmodified lines | ||
| 162 | 162 | |
| 163 | 163 | acpi_status |
| 164 | 164 | acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj, |
| 165 | + union acpi_operand_object *field_obj, | |
| 165 | 166 | u32 function, |
| 166 | 167 | u32 region_offset, u32 bit_width, u64 *value); |
| 167 | 168 | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -140,8 +140,19 @@ u32 acpi_gbl_trace_flags; · 128 unmodified lines | ||
| 140 | 140 | acpi_name acpi_gbl_trace_method_name; |
| 141 | 141 | u8 acpi_gbl_system_awake_and_running; |
| 142 | 142 | |
| 143 | +/* | |
| 144 | + * ACPI 5.0 introduces the concept of a "reduced hardware platform", meaning | |
| 145 | + * that the ACPI hardware is no longer required. A flag in the FADT indicates | |
| 146 | + * a reduced HW machine, and that flag is duplicated here for convenience. | |
| 147 | + */ | |
| 148 | +u8 acpi_gbl_reduced_hardware; | |
| 149 | + | |
| 143 | 150 | #endif |
| 144 | 151 | |
| 152 | +/* Do not disassemble buffers to resource descriptors */ | |
| 153 | + | |
| 154 | +ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_no_resource_disassembly, FALSE); | |
| 155 | + | |
| 145 | 156 | /***************************************************************************** |
| 146 | 157 | * |
| 147 | 158 | * Debug support |
| @@ -207,7 +218,7 @@ ACPI_EXTERN struct acpi_rw_lock acpi_gbl_namespace_rw_lock; · 59 unmodified lines | ||
| 207 | 218 | |
| 208 | 219 | /***************************************************************************** |
| 209 | 220 | * |
| 210 | − * Mutual exlusion within ACPICA subsystem | |
| 221 | + * Mutual exclusion within ACPICA subsystem | |
| 211 | 222 | * |
| 212 | 223 | ****************************************************************************/ |
| 213 | 224 | |
| @@ -295,6 +306,8 @@ ACPI_EXTERN u8 acpi_gbl_acpi_hardware_present; · 81 unmodified lines | ||
| 295 | 306 | ACPI_EXTERN u8 acpi_gbl_events_initialized; |
| 296 | 307 | ACPI_EXTERN u8 acpi_gbl_osi_data; |
| 297 | 308 | ACPI_EXTERN struct acpi_interface_info *acpi_gbl_supported_interfaces; |
| 309 | +ACPI_EXTERN struct acpi_address_range | |
| 310 | + *acpi_gbl_address_range_list[ACPI_ADDRESS_RANGE_MAX]; | |
| 298 | 311 | |
| 299 | 312 | #ifndef DEFINE_ACPI_GLOBALS |
| 300 | 313 | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -468,6 +468,8 @@ void acpi_ex_eisa_id_to_string(char *dest, u64 compressed_id); · 456 unmodified lines | ||
| 468 | 468 | |
| 469 | 469 | void acpi_ex_integer_to_string(char *dest, u64 value); |
| 470 | 470 | |
| 471 | +u8 acpi_is_valid_space_id(u8 space_id); | |
| 472 | + | |
| 471 | 473 | /* |
| 472 | 474 | * exregion - default op_region handlers |
| 473 | 475 | */ |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -53,7 +53,7 @@ typedef u32 acpi_mutex_handle; · 41 unmodified lines | ||
| 53 | 53 | |
| 54 | 54 | /* Total number of aml opcodes defined */ |
| 55 | 55 | |
| 56 | −#define AML_NUM_OPCODES 0x7F | |
| 56 | +#define AML_NUM_OPCODES 0x81 | |
| 57 | 57 | |
| 58 | 58 | /* Forward declarations */ |
| 59 | 59 | |
| @@ -249,12 +249,16 @@ struct acpi_create_field_info { · 189 unmodified lines | ||
| 249 | 249 | struct acpi_namespace_node *field_node; |
| 250 | 250 | struct acpi_namespace_node *register_node; |
| 251 | 251 | struct acpi_namespace_node *data_register_node; |
| 252 | + struct acpi_namespace_node *connection_node; | |
| 253 | + u8 *resource_buffer; | |
| 252 | 254 | u32 bank_value; |
| 253 | 255 | u32 field_bit_position; |
| 254 | 256 | u32 field_bit_length; |
| 257 | + u16 resource_length; | |
| 255 | 258 | u8 field_flags; |
| 256 | 259 | u8 attribute; |
| 257 | 260 | u8 field_type; |
| 261 | + u8 access_length; | |
| 258 | 262 | }; |
| 259 | 263 | |
| 260 | 264 | typedef |
| @@ -315,7 +319,8 @@ struct acpi_name_info { · 54 unmodified lines | ||
| 315 | 319 | |
| 316 | 320 | /* |
| 317 | 321 | * Used for ACPI_PTYPE1_FIXED, ACPI_PTYPE1_VAR, ACPI_PTYPE2, |
| 318 | − * ACPI_PTYPE2_MIN, ACPI_PTYPE2_PKG_COUNT, ACPI_PTYPE2_COUNT | |
| 322 | + * ACPI_PTYPE2_MIN, ACPI_PTYPE2_PKG_COUNT, ACPI_PTYPE2_COUNT, | |
| 323 | + * ACPI_PTYPE2_FIX_VAR | |
| 319 | 324 | */ |
| 320 | 325 | struct acpi_package_info { |
| 321 | 326 | u8 type; |
| @@ -625,6 +630,15 @@ union acpi_generic_state { · 303 unmodified lines | ||
| 625 | 630 | |
| 626 | 631 | typedef acpi_status(*ACPI_EXECUTE_OP) (struct acpi_walk_state * walk_state); |
| 627 | 632 | |
| 633 | +/* Address Range info block */ | |
| 634 | + | |
| 635 | +struct acpi_address_range { | |
| 636 | + struct acpi_address_range *next; | |
| 637 | + struct acpi_namespace_node *region_node; | |
| 638 | + acpi_physical_address start_address; | |
| 639 | + acpi_physical_address end_address; | |
| 640 | +}; | |
| 641 | + | |
| 628 | 642 | /***************************************************************************** |
| 629 | 643 | * |
| 630 | 644 | * Parser typedefs and structs |
| @@ -951,7 +965,7 @@ struct acpi_port_info { · 320 unmodified lines | ||
| 951 | 965 | #define ACPI_RESOURCE_NAME_END_DEPENDENT 0x38 |
| 952 | 966 | #define ACPI_RESOURCE_NAME_IO 0x40 |
| 953 | 967 | #define ACPI_RESOURCE_NAME_FIXED_IO 0x48 |
| 954 | −#define ACPI_RESOURCE_NAME_RESERVED_S1 0x50 | |
| 968 | +#define ACPI_RESOURCE_NAME_FIXED_DMA 0x50 | |
| 955 | 969 | #define ACPI_RESOURCE_NAME_RESERVED_S2 0x58 |
| 956 | 970 | #define ACPI_RESOURCE_NAME_RESERVED_S3 0x60 |
| 957 | 971 | #define ACPI_RESOURCE_NAME_RESERVED_S4 0x68 |
| @@ -973,7 +987,9 @@ struct acpi_port_info { · 15 unmodified lines | ||
| 973 | 987 | #define ACPI_RESOURCE_NAME_EXTENDED_IRQ 0x89 |
| 974 | 988 | #define ACPI_RESOURCE_NAME_ADDRESS64 0x8A |
| 975 | 989 | #define ACPI_RESOURCE_NAME_EXTENDED_ADDRESS64 0x8B |
| 976 | −#define ACPI_RESOURCE_NAME_LARGE_MAX 0x8B | |
| 990 | +#define ACPI_RESOURCE_NAME_GPIO 0x8C | |
| 991 | +#define ACPI_RESOURCE_NAME_SERIAL_BUS 0x8E | |
| 992 | +#define ACPI_RESOURCE_NAME_LARGE_MAX 0x8E | |
| 977 | 993 | |
| 978 | 994 | /***************************************************************************** |
| 979 | 995 | * |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -254,6 +254,7 @@ ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO}; · 241 unmodified lines | ||
| 254 | 254 | u32 base_byte_offset; /* Byte offset within containing object */\ |
| 255 | 255 | u32 value; /* Value to store into the Bank or Index register */\ |
| 256 | 256 | u8 start_field_bit_offset;/* Bit offset within first field datum (0-63) */\ |
| 257 | + u8 access_length; /* For serial regions/fields */ | |
| 257 | 258 | |
| 258 | 259 | |
| 259 | 260 | struct acpi_object_field_common { /* COMMON FIELD (for BUFFER, REGION, BANK, and INDEX fields) */ |
| @@ -261,7 +262,9 @@ struct acpi_object_field_common { /* COMMON FIELD (for BUFFER, REGION, BANK, and · 1 unmodified line | ||
| 261 | 262 | }; |
| 262 | 263 | |
| 263 | 264 | struct acpi_object_region_field { |
| 264 | − ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO union acpi_operand_object *region_obj; /* Containing op_region object */ | |
| 265 | + ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO u16 resource_length; | |
| 266 | + union acpi_operand_object *region_obj; /* Containing op_region object */ | |
| 267 | + u8 *resource_buffer; /* resource_template for serial regions/fields */ | |
| 265 | 268 | }; |
| 266 | 269 | |
| 267 | 270 | struct acpi_object_bank_field { |
| @@ -358,6 +361,7 @@ typedef enum { · 90 unmodified lines | ||
| 358 | 361 | */ |
| 359 | 362 | struct acpi_object_extra { |
| 360 | 363 | ACPI_OBJECT_COMMON_HEADER struct acpi_namespace_node *method_REG; /* _REG method for this region (if any) */ |
| 364 | + struct acpi_namespace_node *scope_node; | |
| 361 | 365 | void *region_context; /* Region-specific data */ |
| 362 | 366 | u8 *aml_start; |
| 363 | 367 | u32 aml_length; |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -93,6 +93,7 @@ · 81 unmodified lines | ||
| 93 | 93 | #define ARGP_CONCAT_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) |
| 94 | 94 | #define ARGP_CONCAT_RES_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) |
| 95 | 95 | #define ARGP_COND_REF_OF_OP ARGP_LIST2 (ARGP_SUPERNAME, ARGP_SUPERNAME) |
| 96 | +#define ARGP_CONNECTFIELD_OP ARGP_LIST1 (ARGP_NAMESTRING) | |
| 96 | 97 | #define ARGP_CONTINUE_OP ARG_NONE |
| 97 | 98 | #define ARGP_COPY_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_SIMPLENAME) |
| 98 | 99 | #define ARGP_CREATE_BIT_FIELD_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_NAME) |
| @@ -164,6 +165,7 @@ · 65 unmodified lines | ||
| 164 | 165 | #define ARGP_RETURN_OP ARGP_LIST1 (ARGP_TERMARG) |
| 165 | 166 | #define ARGP_REVISION_OP ARG_NONE |
| 166 | 167 | #define ARGP_SCOPE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_TERMLIST) |
| 168 | +#define ARGP_SERIALFIELD_OP ARGP_LIST1 (ARGP_NAMESTRING) | |
| 167 | 169 | #define ARGP_SHIFT_LEFT_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) |
| 168 | 170 | #define ARGP_SHIFT_RIGHT_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) |
| 169 | 171 | #define ARGP_SIGNAL_OP ARGP_LIST1 (ARGP_SUPERNAME) |
| @@ -223,6 +225,7 @@ · 53 unmodified lines | ||
| 223 | 225 | #define ARGI_CONCAT_OP ARGI_LIST3 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA, ARGI_TARGETREF) |
| 224 | 226 | #define ARGI_CONCAT_RES_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_BUFFER, ARGI_TARGETREF) |
| 225 | 227 | #define ARGI_COND_REF_OF_OP ARGI_LIST2 (ARGI_OBJECT_REF, ARGI_TARGETREF) |
| 228 | +#define ARGI_CONNECTFIELD_OP ARGI_INVALID_OPCODE | |
| 226 | 229 | #define ARGI_CONTINUE_OP ARGI_INVALID_OPCODE |
| 227 | 230 | #define ARGI_COPY_OP ARGI_LIST2 (ARGI_ANYTYPE, ARGI_SIMPLE_TARGET) |
| 228 | 231 | #define ARGI_CREATE_BIT_FIELD_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_REFERENCE) |
| @@ -294,6 +297,7 @@ · 65 unmodified lines | ||
| 294 | 297 | #define ARGI_RETURN_OP ARGI_INVALID_OPCODE |
| 295 | 298 | #define ARGI_REVISION_OP ARG_NONE |
| 296 | 299 | #define ARGI_SCOPE_OP ARGI_INVALID_OPCODE |
| 300 | +#define ARGI_SERIALFIELD_OP ARGI_INVALID_OPCODE | |
| 297 | 301 | #define ARGI_SHIFT_LEFT_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) |
| 298 | 302 | #define ARGI_SHIFT_RIGHT_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) |
| 299 | 303 | #define ARGI_SIGNAL_OP ARGI_LIST1 (ARGI_EVENT) |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -94,6 +94,14 @@ · 81 unmodified lines | ||
| 94 | 94 | * ACPI_PTYPE2_REV_FIXED: Revision at start, each subpackage is Fixed-length |
| 95 | 95 | * (Used for _ART, _FPS) |
| 96 | 96 | * |
| 97 | + * ACPI_PTYPE2_FIX_VAR: Each subpackage consists of some fixed-length elements | |
| 98 | + * followed by an optional element | |
| 99 | + * object type | |
| 100 | + * count | |
| 101 | + * object type | |
| 102 | + * count = 0 (optional) | |
| 103 | + * (Used for _DLM) | |
| 104 | + * | |
| 97 | 105 | *****************************************************************************/ |
| 98 | 106 | |
| 99 | 107 | enum acpi_return_package_types { |
| @@ -105,7 +113,8 @@ enum acpi_return_package_types { · 5 unmodified lines | ||
| 105 | 113 | ACPI_PTYPE2_PKG_COUNT = 6, |
| 106 | 114 | ACPI_PTYPE2_FIXED = 7, |
| 107 | 115 | ACPI_PTYPE2_MIN = 8, |
| 108 | − ACPI_PTYPE2_REV_FIXED = 9 | |
| 116 | + ACPI_PTYPE2_REV_FIXED = 9, | |
| 117 | + ACPI_PTYPE2_FIX_VAR = 10 | |
| 109 | 118 | }; |
| 110 | 119 | |
| 111 | 120 | #ifdef ACPI_CREATE_PREDEFINED_TABLE |
| @@ -154,6 +163,7 @@ static const union acpi_predefined_info predefined_names[] = · 42 unmodified lines | ||
| 154 | 163 | {{"_AC8", 0, ACPI_RTYPE_INTEGER}}, |
| 155 | 164 | {{"_AC9", 0, ACPI_RTYPE_INTEGER}}, |
| 156 | 165 | {{"_ADR", 0, ACPI_RTYPE_INTEGER}}, |
| 166 | + {{"_AEI", 0, ACPI_RTYPE_BUFFER}}, | |
| 157 | 167 | {{"_AL0", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ |
| 158 | 168 | {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, |
| 159 | 169 | |
| @@ -229,6 +239,13 @@ static const union acpi_predefined_info predefined_names[] = · 69 unmodified lines | ||
| 229 | 239 | {{"_CID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING | ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints/Strs) */ |
| 230 | 240 | {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING, 0,0}, 0,0}}, |
| 231 | 241 | |
| 242 | + {{"_CLS", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (3 Int) */ | |
| 243 | + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 3, 0}, 0, 0}}, | |
| 244 | + | |
| 245 | + {{"_CPC", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints/Bufs) */ | |
| 246 | + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER | ACPI_RTYPE_BUFFER, 0, 0}, 0, | |
| 247 | + 0}}, | |
| 248 | + | |
| 232 | 249 | {{"_CRS", 0, ACPI_RTYPE_BUFFER}}, |
| 233 | 250 | {{"_CRT", 0, ACPI_RTYPE_INTEGER}}, |
| 234 | 251 | {{"_CSD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (1 Int(n), n-1 Int) */ |
| @@ -237,12 +254,21 @@ static const union acpi_predefined_info predefined_names[] = · 2 unmodified lines | ||
| 237 | 254 | {{"_CST", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (1 Int(n), n Pkg (1 Buf/3 Int) */ |
| 238 | 255 | {{{ACPI_PTYPE2_PKG_COUNT,ACPI_RTYPE_BUFFER, 1, ACPI_RTYPE_INTEGER}, 3,0}}, |
| 239 | 256 | |
| 257 | + {{"_CWS", 1, ACPI_RTYPE_INTEGER}}, | |
| 240 | 258 | {{"_DCK", 1, ACPI_RTYPE_INTEGER}}, |
| 241 | 259 | {{"_DCS", 0, ACPI_RTYPE_INTEGER}}, |
| 242 | 260 | {{"_DDC", 1, ACPI_RTYPE_INTEGER | ACPI_RTYPE_BUFFER}}, |
| 243 | 261 | {{"_DDN", 0, ACPI_RTYPE_STRING}}, |
| 262 | + {{"_DEP", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ | |
| 263 | + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0}, 0, 0}}, | |
| 264 | + | |
| 244 | 265 | {{"_DGS", 0, ACPI_RTYPE_INTEGER}}, |
| 245 | 266 | {{"_DIS", 0, 0}}, |
| 267 | + | |
| 268 | + {{"_DLM", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (1 Ref, 0/1 Optional Buf/Ref) */ | |
| 269 | + {{{ACPI_PTYPE2_FIX_VAR, ACPI_RTYPE_REFERENCE, 1, | |
| 270 | + ACPI_RTYPE_REFERENCE | ACPI_RTYPE_BUFFER}, 0, 0}}, | |
| 271 | + | |
| 246 | 272 | {{"_DMA", 0, ACPI_RTYPE_BUFFER}}, |
| 247 | 273 | {{"_DOD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints) */ |
| 248 | 274 | {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0,0}, 0,0}}, |
| @@ -262,6 +288,7 @@ static const union acpi_predefined_info predefined_names[] = · 13 unmodified lines | ||
| 262 | 288 | {{"_EJ3", 1, 0}}, |
| 263 | 289 | {{"_EJ4", 1, 0}}, |
| 264 | 290 | {{"_EJD", 0, ACPI_RTYPE_STRING}}, |
| 291 | + {{"_EVT", 1, 0}}, | |
| 265 | 292 | {{"_FDE", 0, ACPI_RTYPE_BUFFER}}, |
| 266 | 293 | {{"_FDI", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (16 Int) */ |
| 267 | 294 | {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 16,0}, 0,0}}, |
| @@ -281,14 +308,17 @@ static const union acpi_predefined_info predefined_names[] = · 13 unmodified lines | ||
| 281 | 308 | {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 3, 0}, 0, 0}}, |
| 282 | 309 | |
| 283 | 310 | {{"_GAI", 0, ACPI_RTYPE_INTEGER}}, |
| 311 | + {{"_GCP", 0, ACPI_RTYPE_INTEGER}}, | |
| 284 | 312 | {{"_GHL", 0, ACPI_RTYPE_INTEGER}}, |
| 285 | 313 | {{"_GLK", 0, ACPI_RTYPE_INTEGER}}, |
| 286 | 314 | {{"_GPD", 0, ACPI_RTYPE_INTEGER}}, |
| 287 | 315 | {{"_GPE", 0, ACPI_RTYPE_INTEGER}}, /* _GPE method, not _GPE scope */ |
| 316 | + {{"_GRT", 0, ACPI_RTYPE_BUFFER}}, | |
| 288 | 317 | {{"_GSB", 0, ACPI_RTYPE_INTEGER}}, |
| 289 | 318 | {{"_GTF", 0, ACPI_RTYPE_BUFFER}}, |
| 290 | 319 | {{"_GTM", 0, ACPI_RTYPE_BUFFER}}, |
| 291 | 320 | {{"_GTS", 1, 0}}, |
| 321 | + {{"_GWS", 1, ACPI_RTYPE_INTEGER}}, | |
| 292 | 322 | {{"_HID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING}}, |
| 293 | 323 | {{"_HOT", 0, ACPI_RTYPE_INTEGER}}, |
| 294 | 324 | {{"_HPP", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (4 Int) */ |
| @@ -303,6 +333,7 @@ static const union acpi_predefined_info predefined_names[] = · 8 unmodified lines | ||
| 303 | 333 | {{"_HPX", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (var Ints) */ |
| 304 | 334 | {{{ACPI_PTYPE2_MIN, ACPI_RTYPE_INTEGER, 5,0}, 0,0}}, |
| 305 | 335 | |
| 336 | + {{"_HRV", 0, ACPI_RTYPE_INTEGER}}, | |
| 306 | 337 | {{"_IFT", 0, ACPI_RTYPE_INTEGER}}, /* See IPMI spec */ |
| 307 | 338 | {{"_INI", 0, 0}}, |
| 308 | 339 | {{"_IRC", 0, 0}}, |
| @@ -361,6 +392,9 @@ static const union acpi_predefined_info predefined_names[] = · 52 unmodified lines | ||
| 361 | 392 | {{"_PR3", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ |
| 362 | 393 | {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0}, 0, 0}}, |
| 363 | 394 | |
| 395 | + {{"_PRE", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ | |
| 396 | + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0}, 0, 0}}, | |
| 397 | + | |
| 364 | 398 | {{"_PRL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ |
| 365 | 399 | {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0}, 0, 0}}, |
| 366 | 400 | |
| @@ -391,6 +425,7 @@ static const union acpi_predefined_info predefined_names[] = · 24 unmodified lines | ||
| 391 | 425 | {{"_PSD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (5 Int) with count */ |
| 392 | 426 | {{{ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER,0,0}, 0,0}}, |
| 393 | 427 | |
| 428 | + {{"_PSE", 1, 0}}, | |
| 394 | 429 | {{"_PSL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ |
| 395 | 430 | {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, |
| 396 | 431 | |
| @@ -457,6 +492,7 @@ static const union acpi_predefined_info predefined_names[] = · 60 unmodified lines | ||
| 457 | 492 | {{"_SLI", 0, ACPI_RTYPE_BUFFER}}, |
| 458 | 493 | {{"_SPD", 1, ACPI_RTYPE_INTEGER}}, |
| 459 | 494 | {{"_SRS", 1, 0}}, |
| 495 | + {{"_SRT", 1, ACPI_RTYPE_INTEGER}}, | |
| 460 | 496 | {{"_SRV", 0, ACPI_RTYPE_INTEGER}}, /* See IPMI spec */ |
| 461 | 497 | {{"_SST", 1, 0}}, |
| 462 | 498 | {{"_STA", 0, ACPI_RTYPE_INTEGER}}, |
| @@ -464,6 +500,7 @@ static const union acpi_predefined_info predefined_names[] = · 1 unmodified line | ||
| 464 | 500 | {{"_STP", 2, ACPI_RTYPE_INTEGER}}, |
| 465 | 501 | {{"_STR", 0, ACPI_RTYPE_BUFFER}}, |
| 466 | 502 | {{"_STV", 2, ACPI_RTYPE_INTEGER}}, |
| 503 | + {{"_SUB", 0, ACPI_RTYPE_STRING}}, | |
| 467 | 504 | {{"_SUN", 0, ACPI_RTYPE_INTEGER}}, |
| 468 | 505 | {{"_SWS", 0, ACPI_RTYPE_INTEGER}}, |
| 469 | 506 | {{"_TC1", 0, ACPI_RTYPE_INTEGER}}, |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -73,28 +73,40 @@ typedef const struct acpi_rsconvert_info { · 61 unmodified lines | ||
| 73 | 73 | |
| 74 | 74 | /* Resource conversion opcodes */ |
| 75 | 75 | |
| 76 | −#define ACPI_RSC_INITGET 0 | |
| 77 | −#define ACPI_RSC_INITSET 1 | |
| 78 | −#define ACPI_RSC_FLAGINIT 2 | |
| 79 | −#define ACPI_RSC_1BITFLAG 3 | |
| 80 | −#define ACPI_RSC_2BITFLAG 4 | |
| 81 | −#define ACPI_RSC_COUNT 5 | |
| 82 | −#define ACPI_RSC_COUNT16 6 | |
| 83 | −#define ACPI_RSC_LENGTH 7 | |
| 84 | −#define ACPI_RSC_MOVE8 8 | |
| 85 | −#define ACPI_RSC_MOVE16 9 | |
| 86 | −#define ACPI_RSC_MOVE32 10 | |
| 87 | −#define ACPI_RSC_MOVE64 11 | |
| 88 | −#define ACPI_RSC_SET8 12 | |
| 89 | −#define ACPI_RSC_DATA8 13 | |
| 90 | −#define ACPI_RSC_ADDRESS 14 | |
| 91 | −#define ACPI_RSC_SOURCE 15 | |
| 92 | −#define ACPI_RSC_SOURCEX 16 | |
| 93 | −#define ACPI_RSC_BITMASK 17 | |
| 94 | −#define ACPI_RSC_BITMASK16 18 | |
| 95 | −#define ACPI_RSC_EXIT_NE 19 | |
| 96 | −#define ACPI_RSC_EXIT_LE 20 | |
| 97 | −#define ACPI_RSC_EXIT_EQ 21 | |
| 76 | +typedef enum { | |
| 77 | + ACPI_RSC_INITGET = 0, | |
| 78 | + ACPI_RSC_INITSET, | |
| 79 | + ACPI_RSC_FLAGINIT, | |
| 80 | + ACPI_RSC_1BITFLAG, | |
| 81 | + ACPI_RSC_2BITFLAG, | |
| 82 | + ACPI_RSC_3BITFLAG, | |
| 83 | + ACPI_RSC_ADDRESS, | |
| 84 | + ACPI_RSC_BITMASK, | |
| 85 | + ACPI_RSC_BITMASK16, | |
| 86 | + ACPI_RSC_COUNT, | |
| 87 | + ACPI_RSC_COUNT16, | |
| 88 | + ACPI_RSC_COUNT_GPIO_PIN, | |
| 89 | + ACPI_RSC_COUNT_GPIO_RES, | |
| 90 | + ACPI_RSC_COUNT_GPIO_VEN, | |
| 91 | + ACPI_RSC_COUNT_SERIAL_RES, | |
| 92 | + ACPI_RSC_COUNT_SERIAL_VEN, | |
| 93 | + ACPI_RSC_DATA8, | |
| 94 | + ACPI_RSC_EXIT_EQ, | |
| 95 | + ACPI_RSC_EXIT_LE, | |
| 96 | + ACPI_RSC_EXIT_NE, | |
| 97 | + ACPI_RSC_LENGTH, | |
| 98 | + ACPI_RSC_MOVE_GPIO_PIN, | |
| 99 | + ACPI_RSC_MOVE_GPIO_RES, | |
| 100 | + ACPI_RSC_MOVE_SERIAL_RES, | |
| 101 | + ACPI_RSC_MOVE_SERIAL_VEN, | |
| 102 | + ACPI_RSC_MOVE8, | |
| 103 | + ACPI_RSC_MOVE16, | |
| 104 | + ACPI_RSC_MOVE32, | |
| 105 | + ACPI_RSC_MOVE64, | |
| 106 | + ACPI_RSC_SET8, | |
| 107 | + ACPI_RSC_SOURCE, | |
| 108 | + ACPI_RSC_SOURCEX | |
| 109 | +} ACPI_RSCONVERT_OPCODES; | |
| 98 | 110 | |
| 99 | 111 | /* Resource Conversion sub-opcodes */ |
| 100 | 112 | |
| @@ -106,6 +118,9 @@ typedef const struct acpi_rsconvert_info { · 5 unmodified lines | ||
| 106 | 118 | #define ACPI_RS_OFFSET(f) (u8) ACPI_OFFSET (struct acpi_resource,f) |
| 107 | 119 | #define AML_OFFSET(f) (u8) ACPI_OFFSET (union aml_resource,f) |
| 108 | 120 | |
| 121 | +/* | |
| 122 | + * Individual entry for the resource dump tables | |
| 123 | + */ | |
| 109 | 124 | typedef const struct acpi_rsdump_info { |
| 110 | 125 | u8 opcode; |
| 111 | 126 | u8 offset; |
| @@ -116,20 +131,25 @@ typedef const struct acpi_rsdump_info { · 4 unmodified lines | ||
| 116 | 131 | |
| 117 | 132 | /* Values for the Opcode field above */ |
| 118 | 133 | |
| 119 | −#define ACPI_RSD_TITLE 0 | |
| 120 | −#define ACPI_RSD_LITERAL 1 | |
| 121 | −#define ACPI_RSD_STRING 2 | |
| 122 | −#define ACPI_RSD_UINT8 3 | |
| 123 | −#define ACPI_RSD_UINT16 4 | |
| 124 | −#define ACPI_RSD_UINT32 5 | |
| 125 | −#define ACPI_RSD_UINT64 6 | |
| 126 | −#define ACPI_RSD_1BITFLAG 7 | |
| 127 | −#define ACPI_RSD_2BITFLAG 8 | |
| 128 | −#define ACPI_RSD_SHORTLIST 9 | |
| 129 | −#define ACPI_RSD_LONGLIST 10 | |
| 130 | −#define ACPI_RSD_DWORDLIST 11 | |
| 131 | −#define ACPI_RSD_ADDRESS 12 | |
| 132 | −#define ACPI_RSD_SOURCE 13 | |
| 134 | +typedef enum { | |
| 135 | + ACPI_RSD_TITLE = 0, | |
| 136 | + ACPI_RSD_1BITFLAG, | |
| 137 | + ACPI_RSD_2BITFLAG, | |
| 138 | + ACPI_RSD_3BITFLAG, | |
| 139 | + ACPI_RSD_ADDRESS, | |
| 140 | + ACPI_RSD_DWORDLIST, | |
| 141 | + ACPI_RSD_LITERAL, | |
| 142 | + ACPI_RSD_LONGLIST, | |
| 143 | + ACPI_RSD_SHORTLIST, | |
| 144 | + ACPI_RSD_SHORTLISTX, | |
| 145 | + ACPI_RSD_SOURCE, | |
| 146 | + ACPI_RSD_STRING, | |
| 147 | + ACPI_RSD_UINT8, | |
| 148 | + ACPI_RSD_UINT16, | |
| 149 | + ACPI_RSD_UINT32, | |
| 150 | + ACPI_RSD_UINT64, | |
| 151 | + ACPI_RSD_WORDLIST | |
| 152 | +} ACPI_RSDUMP_OPCODES; | |
| 133 | 153 | |
| 134 | 154 | /* restore default alignment */ |
| 135 | 155 | |
| @@ -138,13 +158,18 @@ typedef const struct acpi_rsdump_info { · 2 unmodified lines | ||
| 138 | 158 | /* Resource tables indexed by internal resource type */ |
| 139 | 159 | |
| 140 | 160 | extern const u8 acpi_gbl_aml_resource_sizes[]; |
| 161 | +extern const u8 acpi_gbl_aml_resource_serial_bus_sizes[]; | |
| 141 | 162 | extern struct acpi_rsconvert_info *acpi_gbl_set_resource_dispatch[]; |
| 142 | 163 | |
| 143 | 164 | /* Resource tables indexed by raw AML resource descriptor type */ |
| 144 | 165 | |
| 145 | 166 | extern const u8 acpi_gbl_resource_struct_sizes[]; |
| 167 | +extern const u8 acpi_gbl_resource_struct_serial_bus_sizes[]; | |
| 146 | 168 | extern struct acpi_rsconvert_info *acpi_gbl_get_resource_dispatch[]; |
| 147 | 169 | |
| 170 | +extern struct acpi_rsconvert_info | |
| 171 | + *acpi_gbl_convert_resource_serial_bus_dispatch[]; | |
| 172 | + | |
| 148 | 173 | struct acpi_vendor_walk_info { |
| 149 | 174 | struct acpi_vendor_uuid *uuid; |
| 150 | 175 | struct acpi_buffer *buffer; |
| @@ -190,6 +215,10 @@ acpi_status · 39 unmodified lines | ||
| 190 | 215 | acpi_rs_set_srs_method_data(struct acpi_namespace_node *node, |
| 191 | 216 | struct acpi_buffer *ret_buffer); |
| 192 | 217 | |
| 218 | +acpi_status | |
| 219 | +acpi_rs_get_aei_method_data(struct acpi_namespace_node *node, | |
| 220 | + struct acpi_buffer *ret_buffer); | |
| 221 | + | |
| 193 | 222 | /* |
| 194 | 223 | * rscalc |
| 195 | 224 | */ |
| @@ -293,6 +322,11 @@ extern struct acpi_rsconvert_info acpi_rs_convert_address16[]; · 97 unmodified lines | ||
| 293 | 322 | extern struct acpi_rsconvert_info acpi_rs_convert_ext_irq[]; |
| 294 | 323 | extern struct acpi_rsconvert_info acpi_rs_convert_address64[]; |
| 295 | 324 | extern struct acpi_rsconvert_info acpi_rs_convert_ext_address64[]; |
| 325 | +extern struct acpi_rsconvert_info acpi_rs_convert_gpio[]; | |
| 326 | +extern struct acpi_rsconvert_info acpi_rs_convert_fixed_dma[]; | |
| 327 | +extern struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_bus[]; | |
| 328 | +extern struct acpi_rsconvert_info acpi_rs_convert_spi_serial_bus[]; | |
| 329 | +extern struct acpi_rsconvert_info acpi_rs_convert_uart_serial_bus[]; | |
| 296 | 330 | |
| 297 | 331 | /* These resources require separate get/set tables */ |
| 298 | 332 | |
| @@ -310,6 +344,7 @@ extern struct acpi_rsconvert_info acpi_rs_set_vendor[]; · 11 unmodified lines | ||
| 310 | 344 | * rsinfo |
| 311 | 345 | */ |
| 312 | 346 | extern struct acpi_rsdump_info *acpi_gbl_dump_resource_dispatch[]; |
| 347 | +extern struct acpi_rsdump_info *acpi_gbl_dump_serial_bus_dispatch[]; | |
| 313 | 348 | |
| 314 | 349 | /* |
| 315 | 350 | * rsdump |
| @@ -331,6 +366,12 @@ extern struct acpi_rsdump_info acpi_rs_dump_address64[]; · 15 unmodified lines | ||
| 331 | 366 | extern struct acpi_rsdump_info acpi_rs_dump_ext_address64[]; |
| 332 | 367 | extern struct acpi_rsdump_info acpi_rs_dump_ext_irq[]; |
| 333 | 368 | extern struct acpi_rsdump_info acpi_rs_dump_generic_reg[]; |
| 369 | +extern struct acpi_rsdump_info acpi_rs_dump_gpio[]; | |
| 370 | +extern struct acpi_rsdump_info acpi_rs_dump_fixed_dma[]; | |
| 371 | +extern struct acpi_rsdump_info acpi_rs_dump_common_serial_bus[]; | |
| 372 | +extern struct acpi_rsdump_info acpi_rs_dump_i2c_serial_bus[]; | |
| 373 | +extern struct acpi_rsdump_info acpi_rs_dump_spi_serial_bus[]; | |
| 374 | +extern struct acpi_rsdump_info acpi_rs_dump_uart_serial_bus[]; | |
| 334 | 375 | #endif |
| 335 | 376 | |
| 336 | 377 | #endif /* __ACRESRC_H__ */ |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -45,6 +45,7 @@ · 33 unmodified lines | ||
| 45 | 45 | #define _ACUTILS_H |
| 46 | 46 | |
| 47 | 47 | extern const u8 acpi_gbl_resource_aml_sizes[]; |
| 48 | +extern const u8 acpi_gbl_resource_aml_serial_bus_sizes[]; | |
| 48 | 49 | |
| 49 | 50 | /* Strings used by the disassembler and debugger resource dump routines */ |
| 50 | 51 | |
| @@ -578,6 +579,24 @@ acpi_ut_create_list(char *list_name, · 527 unmodified lines | ||
| 578 | 579 | |
| 579 | 580 | #endif /* ACPI_DBG_TRACK_ALLOCATIONS */ |
| 580 | 581 | |
| 582 | +/* | |
| 583 | + * utaddress - address range check | |
| 584 | + */ | |
| 585 | +acpi_status | |
| 586 | +acpi_ut_add_address_range(acpi_adr_space_type space_id, | |
| 587 | + acpi_physical_address address, | |
| 588 | + u32 length, struct acpi_namespace_node *region_node); | |
| 589 | + | |
| 590 | +void | |
| 591 | +acpi_ut_remove_address_range(acpi_adr_space_type space_id, | |
| 592 | + struct acpi_namespace_node *region_node); | |
| 593 | + | |
| 594 | +u32 | |
| 595 | +acpi_ut_check_address_range(acpi_adr_space_type space_id, | |
| 596 | + acpi_physical_address address, u32 length, u8 warn); | |
| 597 | + | |
| 598 | +void acpi_ut_delete_address_lists(void); | |
| 599 | + | |
| 581 | 600 | /* |
| 582 | 601 | * utxferror - various error/warning output functions |
| 583 | 602 | */ |
| @@ -7,7 +7,7 @@ · 6 unmodified lines | ||
| 7 | 7 | *****************************************************************************/ |
| 8 | 8 | |
| 9 | 9 | /* |
| 10 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 10 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 11 | 11 | * All rights reserved. |
| 12 | 12 | * |
| 13 | 13 | * Redistribution and use in source and binary forms, with or without |
| @@ -188,6 +188,14 @@ · 174 unmodified lines | ||
| 188 | 188 | #define AML_LLESSEQUAL_OP (u16) 0x9294 |
| 189 | 189 | #define AML_LNOTEQUAL_OP (u16) 0x9293 |
| 190 | 190 | |
| 191 | +/* | |
| 192 | + * Opcodes for "Field" operators | |
| 193 | + */ | |
| 194 | +#define AML_FIELD_OFFSET_OP (u8) 0x00 | |
| 195 | +#define AML_FIELD_ACCESS_OP (u8) 0x01 | |
| 196 | +#define AML_FIELD_CONNECTION_OP (u8) 0x02 /* ACPI 5.0 */ | |
| 197 | +#define AML_FIELD_EXT_ACCESS_OP (u8) 0x03 /* ACPI 5.0 */ | |
| 198 | + | |
| 191 | 199 | /* |
| 192 | 200 | * Internal opcodes |
| 193 | 201 | * Use only "Unknown" AML opcodes, don't attempt to use |
| @@ -202,6 +210,8 @@ · 8 unmodified lines | ||
| 202 | 210 | #define AML_INT_METHODCALL_OP (u16) 0x0035 |
| 203 | 211 | #define AML_INT_RETURN_VALUE_OP (u16) 0x0036 |
| 204 | 212 | #define AML_INT_EVAL_SUBTREE_OP (u16) 0x0037 |
| 213 | +#define AML_INT_CONNECTION_OP (u16) 0x0038 | |
| 214 | +#define AML_INT_EXTACCESSFIELD_OP (u16) 0x0039 | |
| 205 | 215 | |
| 206 | 216 | #define ARG_NONE 0x0 |
| 207 | 217 | |
| @@ -456,13 +466,16 @@ typedef enum { · 248 unmodified lines | ||
| 456 | 466 | * access_as keyword |
| 457 | 467 | */ |
| 458 | 468 | typedef enum { |
| 459 | − AML_FIELD_ATTRIB_SMB_QUICK = 0x02, | |
| 460 | − AML_FIELD_ATTRIB_SMB_SEND_RCV = 0x04, | |
| 461 | − AML_FIELD_ATTRIB_SMB_BYTE = 0x06, | |
| 462 | − AML_FIELD_ATTRIB_SMB_WORD = 0x08, | |
| 463 | − AML_FIELD_ATTRIB_SMB_BLOCK = 0x0A, | |
| 464 | − AML_FIELD_ATTRIB_SMB_WORD_CALL = 0x0C, | |
| 465 | − AML_FIELD_ATTRIB_SMB_BLOCK_CALL = 0x0D | |
| 469 | + AML_FIELD_ATTRIB_QUICK = 0x02, | |
| 470 | + AML_FIELD_ATTRIB_SEND_RCV = 0x04, | |
| 471 | + AML_FIELD_ATTRIB_BYTE = 0x06, | |
| 472 | + AML_FIELD_ATTRIB_WORD = 0x08, | |
| 473 | + AML_FIELD_ATTRIB_BLOCK = 0x0A, | |
| 474 | + AML_FIELD_ATTRIB_MULTIBYTE = 0x0B, | |
| 475 | + AML_FIELD_ATTRIB_WORD_CALL = 0x0C, | |
| 476 | + AML_FIELD_ATTRIB_BLOCK_CALL = 0x0D, | |
| 477 | + AML_FIELD_ATTRIB_RAW_BYTES = 0x0E, | |
| 478 | + AML_FIELD_ATTRIB_RAW_PROCESS = 0x0F | |
| 466 | 479 | } AML_ACCESS_ATTRIBUTE; |
| 467 | 480 | |
| 468 | 481 | /* Bit fields in the AML method_flags byte */ |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -58,29 +58,48 @@ · 45 unmodified lines | ||
| 58 | 58 | #define ACPI_RESTAG_TYPESPECIFICATTRIBUTES "_ATT" |
| 59 | 59 | #define ACPI_RESTAG_BASEADDRESS "_BAS" |
| 60 | 60 | #define ACPI_RESTAG_BUSMASTER "_BM_" /* Master(1), Slave(0) */ |
| 61 | +#define ACPI_RESTAG_DEBOUNCETIME "_DBT" | |
| 61 | 62 | #define ACPI_RESTAG_DECODE "_DEC" |
| 63 | +#define ACPI_RESTAG_DEVICEPOLARITY "_DPL" | |
| 62 | 64 | #define ACPI_RESTAG_DMA "_DMA" |
| 63 | 65 | #define ACPI_RESTAG_DMATYPE "_TYP" /* Compatible(0), A(1), B(2), F(3) */ |
| 66 | +#define ACPI_RESTAG_DRIVESTRENGTH "_DRS" | |
| 67 | +#define ACPI_RESTAG_ENDIANNESS "_END" | |
| 68 | +#define ACPI_RESTAG_FLOWCONTROL "_FLC" | |
| 64 | 69 | #define ACPI_RESTAG_GRANULARITY "_GRA" |
| 65 | 70 | #define ACPI_RESTAG_INTERRUPT "_INT" |
| 66 | 71 | #define ACPI_RESTAG_INTERRUPTLEVEL "_LL_" /* active_lo(1), active_hi(0) */ |
| 67 | 72 | #define ACPI_RESTAG_INTERRUPTSHARE "_SHR" /* Shareable(1), no_share(0) */ |
| 68 | 73 | #define ACPI_RESTAG_INTERRUPTTYPE "_HE_" /* Edge(1), Level(0) */ |
| 74 | +#define ACPI_RESTAG_IORESTRICTION "_IOR" | |
| 69 | 75 | #define ACPI_RESTAG_LENGTH "_LEN" |
| 76 | +#define ACPI_RESTAG_LINE "_LIN" | |
| 70 | 77 | #define ACPI_RESTAG_MEMATTRIBUTES "_MTP" /* Memory(0), Reserved(1), ACPI(2), NVS(3) */ |
| 71 | 78 | #define ACPI_RESTAG_MEMTYPE "_MEM" /* non_cache(0), Cacheable(1) Cache+combine(2), Cache+prefetch(3) */ |
| 72 | 79 | #define ACPI_RESTAG_MAXADDR "_MAX" |
| 73 | 80 | #define ACPI_RESTAG_MINADDR "_MIN" |
| 74 | 81 | #define ACPI_RESTAG_MAXTYPE "_MAF" |
| 75 | 82 | #define ACPI_RESTAG_MINTYPE "_MIF" |
| 83 | +#define ACPI_RESTAG_MODE "_MOD" | |
| 84 | +#define ACPI_RESTAG_PARITY "_PAR" | |
| 85 | +#define ACPI_RESTAG_PHASE "_PHA" | |
| 86 | +#define ACPI_RESTAG_PIN "_PIN" | |
| 87 | +#define ACPI_RESTAG_PINCONFIG "_PPI" | |
| 88 | +#define ACPI_RESTAG_POLARITY "_POL" | |
| 76 | 89 | #define ACPI_RESTAG_REGISTERBITOFFSET "_RBO" |
| 77 | 90 | #define ACPI_RESTAG_REGISTERBITWIDTH "_RBW" |
| 78 | 91 | #define ACPI_RESTAG_RANGETYPE "_RNG" |
| 79 | 92 | #define ACPI_RESTAG_READWRITETYPE "_RW_" /* read_only(0), Writeable (1) */ |
| 93 | +#define ACPI_RESTAG_LENGTH_RX "_RXL" | |
| 94 | +#define ACPI_RESTAG_LENGTH_TX "_TXL" | |
| 95 | +#define ACPI_RESTAG_SLAVEMODE "_SLV" | |
| 96 | +#define ACPI_RESTAG_SPEED "_SPE" | |
| 97 | +#define ACPI_RESTAG_STOPBITS "_STB" | |
| 80 | 98 | #define ACPI_RESTAG_TRANSLATION "_TRA" |
| 81 | 99 | #define ACPI_RESTAG_TRANSTYPE "_TRS" /* Sparse(1), Dense(0) */ |
| 82 | 100 | #define ACPI_RESTAG_TYPE "_TTP" /* Translation(1), Static (0) */ |
| 83 | 101 | #define ACPI_RESTAG_XFERTYPE "_SIZ" /* 8(0), 8_and16(1), 16(2) */ |
| 102 | +#define ACPI_RESTAG_VENDORDATA "_VEN" | |
| 84 | 103 | |
| 85 | 104 | /* Default sizes for "small" resource descriptors */ |
| 86 | 105 | |
| @@ -90,6 +109,7 @@ · 3 unmodified lines | ||
| 90 | 109 | #define ASL_RDESC_END_DEPEND_SIZE 0x00 |
| 91 | 110 | #define ASL_RDESC_IO_SIZE 0x07 |
| 92 | 111 | #define ASL_RDESC_FIXED_IO_SIZE 0x03 |
| 112 | +#define ASL_RDESC_FIXED_DMA_SIZE 0x05 | |
| 93 | 113 | #define ASL_RDESC_END_TAG_SIZE 0x01 |
| 94 | 114 | |
| 95 | 115 | struct asl_resource_node { |
| @@ -164,6 +184,12 @@ struct aml_resource_end_tag { · 68 unmodified lines | ||
| 164 | 184 | AML_RESOURCE_SMALL_HEADER_COMMON u8 checksum; |
| 165 | 185 | }; |
| 166 | 186 | |
| 187 | +struct aml_resource_fixed_dma { | |
| 188 | + AML_RESOURCE_SMALL_HEADER_COMMON u16 request_lines; | |
| 189 | + u16 channels; | |
| 190 | + u8 width; | |
| 191 | +}; | |
| 192 | + | |
| 167 | 193 | /* |
| 168 | 194 | * LARGE descriptors |
| 169 | 195 | */ |
| @@ -263,6 +289,110 @@ struct aml_resource_generic_register { · 93 unmodified lines | ||
| 263 | 289 | u64 address; |
| 264 | 290 | }; |
| 265 | 291 | |
| 292 | +/* Common descriptor for gpio_int and gpio_io (ACPI 5.0) */ | |
| 293 | + | |
| 294 | +struct aml_resource_gpio { | |
| 295 | + AML_RESOURCE_LARGE_HEADER_COMMON u8 revision_id; | |
| 296 | + u8 connection_type; | |
| 297 | + u16 flags; | |
| 298 | + u16 int_flags; | |
| 299 | + u8 pin_config; | |
| 300 | + u16 drive_strength; | |
| 301 | + u16 debounce_timeout; | |
| 302 | + u16 pin_table_offset; | |
| 303 | + u8 res_source_index; | |
| 304 | + u16 res_source_offset; | |
| 305 | + u16 vendor_offset; | |
| 306 | + u16 vendor_length; | |
| 307 | + /* | |
| 308 | + * Optional fields follow immediately: | |
| 309 | + * 1) PIN list (Words) | |
| 310 | + * 2) Resource Source String | |
| 311 | + * 3) Vendor Data bytes | |
| 312 | + */ | |
| 313 | +}; | |
| 314 | + | |
| 315 | +#define AML_RESOURCE_GPIO_REVISION 1 /* ACPI 5.0 */ | |
| 316 | + | |
| 317 | +/* Values for connection_type above */ | |
| 318 | + | |
| 319 | +#define AML_RESOURCE_GPIO_TYPE_INT 0 | |
| 320 | +#define AML_RESOURCE_GPIO_TYPE_IO 1 | |
| 321 | +#define AML_RESOURCE_MAX_GPIOTYPE 1 | |
| 322 | + | |
| 323 | +/* Common preamble for all serial descriptors (ACPI 5.0) */ | |
| 324 | + | |
| 325 | +#define AML_RESOURCE_SERIAL_COMMON \ | |
| 326 | + u8 revision_id; \ | |
| 327 | + u8 res_source_index; \ | |
| 328 | + u8 type; \ | |
| 329 | + u8 flags; \ | |
| 330 | + u16 type_specific_flags; \ | |
| 331 | + u8 type_revision_id; \ | |
| 332 | + u16 type_data_length; \ | |
| 333 | + | |
| 334 | +/* Values for the type field above */ | |
| 335 | + | |
| 336 | +#define AML_RESOURCE_I2C_SERIALBUSTYPE 1 | |
| 337 | +#define AML_RESOURCE_SPI_SERIALBUSTYPE 2 | |
| 338 | +#define AML_RESOURCE_UART_SERIALBUSTYPE 3 | |
| 339 | +#define AML_RESOURCE_MAX_SERIALBUSTYPE 3 | |
| 340 | +#define AML_RESOURCE_VENDOR_SERIALBUSTYPE 192 /* Vendor defined is 0xC0-0xFF (NOT SUPPORTED) */ | |
| 341 | + | |
| 342 | +struct aml_resource_common_serialbus { | |
| 343 | +AML_RESOURCE_LARGE_HEADER_COMMON AML_RESOURCE_SERIAL_COMMON}; | |
| 344 | + | |
| 345 | +struct aml_resource_i2c_serialbus { | |
| 346 | + AML_RESOURCE_LARGE_HEADER_COMMON | |
| 347 | + AML_RESOURCE_SERIAL_COMMON u32 connection_speed; | |
| 348 | + u16 slave_address; | |
| 349 | + /* | |
| 350 | + * Optional fields follow immediately: | |
| 351 | + * 1) Vendor Data bytes | |
| 352 | + * 2) Resource Source String | |
| 353 | + */ | |
| 354 | +}; | |
| 355 | + | |
| 356 | +#define AML_RESOURCE_I2C_REVISION 1 /* ACPI 5.0 */ | |
| 357 | +#define AML_RESOURCE_I2C_TYPE_REVISION 1 /* ACPI 5.0 */ | |
| 358 | +#define AML_RESOURCE_I2C_MIN_DATA_LEN 6 | |
| 359 | + | |
| 360 | +struct aml_resource_spi_serialbus { | |
| 361 | + AML_RESOURCE_LARGE_HEADER_COMMON | |
| 362 | + AML_RESOURCE_SERIAL_COMMON u32 connection_speed; | |
| 363 | + u8 data_bit_length; | |
| 364 | + u8 clock_phase; | |
| 365 | + u8 clock_polarity; | |
| 366 | + u16 device_selection; | |
| 367 | + /* | |
| 368 | + * Optional fields follow immediately: | |
| 369 | + * 1) Vendor Data bytes | |
| 370 | + * 2) Resource Source String | |
| 371 | + */ | |
| 372 | +}; | |
| 373 | + | |
| 374 | +#define AML_RESOURCE_SPI_REVISION 1 /* ACPI 5.0 */ | |
| 375 | +#define AML_RESOURCE_SPI_TYPE_REVISION 1 /* ACPI 5.0 */ | |
| 376 | +#define AML_RESOURCE_SPI_MIN_DATA_LEN 9 | |
| 377 | + | |
| 378 | +struct aml_resource_uart_serialbus { | |
| 379 | + AML_RESOURCE_LARGE_HEADER_COMMON | |
| 380 | + AML_RESOURCE_SERIAL_COMMON u32 default_baud_rate; | |
| 381 | + u16 rx_fifo_size; | |
| 382 | + u16 tx_fifo_size; | |
| 383 | + u8 parity; | |
| 384 | + u8 lines_enabled; | |
| 385 | + /* | |
| 386 | + * Optional fields follow immediately: | |
| 387 | + * 1) Vendor Data bytes | |
| 388 | + * 2) Resource Source String | |
| 389 | + */ | |
| 390 | +}; | |
| 391 | + | |
| 392 | +#define AML_RESOURCE_UART_REVISION 1 /* ACPI 5.0 */ | |
| 393 | +#define AML_RESOURCE_UART_TYPE_REVISION 1 /* ACPI 5.0 */ | |
| 394 | +#define AML_RESOURCE_UART_MIN_DATA_LEN 10 | |
| 395 | + | |
| 266 | 396 | /* restore default alignment */ |
| 267 | 397 | |
| 268 | 398 | #pragma pack() |
| @@ -284,6 +414,7 @@ union aml_resource { · 15 unmodified lines | ||
| 284 | 414 | struct aml_resource_end_dependent end_dpf; |
| 285 | 415 | struct aml_resource_io io; |
| 286 | 416 | struct aml_resource_fixed_io fixed_io; |
| 417 | + struct aml_resource_fixed_dma fixed_dma; | |
| 287 | 418 | struct aml_resource_vendor_small vendor_small; |
| 288 | 419 | struct aml_resource_end_tag end_tag; |
| 289 | 420 | |
| @@ -299,6 +430,11 @@ union aml_resource { · 9 unmodified lines | ||
| 299 | 430 | struct aml_resource_address64 address64; |
| 300 | 431 | struct aml_resource_extended_address64 ext_address64; |
| 301 | 432 | struct aml_resource_extended_irq extended_irq; |
| 433 | + struct aml_resource_gpio gpio; | |
| 434 | + struct aml_resource_i2c_serialbus i2c_serial_bus; | |
| 435 | + struct aml_resource_spi_serialbus spi_serial_bus; | |
| 436 | + struct aml_resource_uart_serialbus uart_serial_bus; | |
| 437 | + struct aml_resource_common_serialbus common_serial_bus; | |
| 302 | 438 | |
| 303 | 439 | /* Utility overlays */ |
| 304 | 440 | |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -250,6 +250,13 @@ acpi_ds_get_bank_field_arguments(union acpi_operand_object *obj_desc) · 237 unmodified lines | ||
| 250 | 250 | status = acpi_ds_execute_arguments(node, node->parent, |
| 251 | 251 | extra_desc->extra.aml_length, |
| 252 | 252 | extra_desc->extra.aml_start); |
| 253 | + if (ACPI_FAILURE(status)) { | |
| 254 | + return_ACPI_STATUS(status); | |
| 255 | + } | |
| 256 | + | |
| 257 | + status = acpi_ut_add_address_range(obj_desc->region.space_id, | |
| 258 | + obj_desc->region.address, | |
| 259 | + obj_desc->region.length, node); | |
| 253 | 260 | return_ACPI_STATUS(status); |
| 254 | 261 | } |
| 255 | 262 | |
| @@ -384,8 +391,15 @@ acpi_status acpi_ds_get_region_arguments(union acpi_operand_object *obj_desc) · 128 unmodified lines | ||
| 384 | 391 | |
| 385 | 392 | /* Execute the argument AML */ |
| 386 | 393 | |
| 387 | − status = acpi_ds_execute_arguments(node, node->parent, | |
| 394 | + status = acpi_ds_execute_arguments(node, extra_desc->extra.scope_node, | |
| 388 | 395 | extra_desc->extra.aml_length, |
| 389 | 396 | extra_desc->extra.aml_start); |
| 397 | + if (ACPI_FAILURE(status)) { | |
| 398 | + return_ACPI_STATUS(status); | |
| 399 | + } | |
| 400 | + | |
| 401 | + status = acpi_ut_add_address_range(obj_desc->region.space_id, | |
| 402 | + obj_desc->region.address, | |
| 403 | + obj_desc->region.length, node); | |
| 390 | 404 | return_ACPI_STATUS(status); |
| 391 | 405 | } |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -221,6 +221,7 @@ acpi_ds_get_field_names(struct acpi_create_field_info *info, · 209 unmodified lines | ||
| 221 | 221 | { |
| 222 | 222 | acpi_status status; |
| 223 | 223 | u64 position; |
| 224 | + union acpi_parse_object *child; | |
| 224 | 225 | |
| 225 | 226 | ACPI_FUNCTION_TRACE_PTR(ds_get_field_names, info); |
| 226 | 227 | |
| @@ -232,10 +233,11 @@ acpi_ds_get_field_names(struct acpi_create_field_info *info, · 5 unmodified lines | ||
| 232 | 233 | |
| 233 | 234 | while (arg) { |
| 234 | 235 | /* |
| 235 | − * Three types of field elements are handled: | |
| 236 | − * 1) Offset - specifies a bit offset | |
| 237 | − * 2) access_as - changes the access mode | |
| 238 | − * 3) Name - Enters a new named field into the namespace | |
| 236 | + * Four types of field elements are handled: | |
| 237 | + * 1) Name - Enters a new named field into the namespace | |
| 238 | + * 2) Offset - specifies a bit offset | |
| 239 | + * 3) access_as - changes the access mode/attributes | |
| 240 | + * 4) Connection - Associate a resource template with the field | |
| 239 | 241 | */ |
| 240 | 242 | switch (arg->common.aml_opcode) { |
| 241 | 243 | case AML_INT_RESERVEDFIELD_OP: |
| @@ -253,21 +255,70 @@ acpi_ds_get_field_names(struct acpi_create_field_info *info, · 11 unmodified lines | ||
| 253 | 255 | break; |
| 254 | 256 | |
| 255 | 257 | case AML_INT_ACCESSFIELD_OP: |
| 256 | − | |
| 258 | + case AML_INT_EXTACCESSFIELD_OP: | |
| 257 | 259 | /* |
| 258 | − * Get a new access_type and access_attribute -- to be used for all | |
| 259 | − * field units that follow, until field end or another access_as | |
| 260 | − * keyword. | |
| 260 | + * Get new access_type, access_attribute, and access_length fields | |
| 261 | + * -- to be used for all field units that follow, until the | |
| 262 | + * end-of-field or another access_as keyword is encountered. | |
| 263 | + * NOTE. These three bytes are encoded in the integer value | |
| 264 | + * of the parseop for convenience. | |
| 261 | 265 | * |
| 262 | 266 | * In field_flags, preserve the flag bits other than the |
| 263 | − * ACCESS_TYPE bits | |
| 267 | + * ACCESS_TYPE bits. | |
| 264 | 268 | */ |
| 269 | + | |
| 270 | + /* access_type (byte_acc, word_acc, etc.) */ | |
| 271 | + | |
| 265 | 272 | info->field_flags = (u8) |
| 266 | 273 | ((info-> |
| 267 | 274 | field_flags & ~(AML_FIELD_ACCESS_TYPE_MASK)) | |
| 268 | − ((u8) ((u32) arg->common.value.integer >> 8))); | |
| 275 | + ((u8)((u32)(arg->common.value.integer & 0x07)))); | |
| 276 | + | |
| 277 | + /* access_attribute (attrib_quick, attrib_byte, etc.) */ | |
| 278 | + | |
| 279 | + info->attribute = | |
| 280 | + (u8)((arg->common.value.integer >> 8) & 0xFF); | |
| 281 | + | |
| 282 | + /* access_length (for serial/buffer protocols) */ | |
| 283 | + | |
| 284 | + info->access_length = | |
| 285 | + (u8)((arg->common.value.integer >> 16) & 0xFF); | |
| 286 | + break; | |
| 287 | + | |
| 288 | + case AML_INT_CONNECTION_OP: | |
| 289 | + /* | |
| 290 | + * Clear any previous connection. New connection is used for all | |
| 291 | + * fields that follow, similar to access_as | |
| 292 | + */ | |
| 293 | + info->resource_buffer = NULL; | |
| 294 | + info->connection_node = NULL; | |
| 269 | 295 | |
| 270 | − info->attribute = (u8) (arg->common.value.integer); | |
| 296 | + /* | |
| 297 | + * A Connection() is either an actual resource descriptor (buffer) | |
| 298 | + * or a named reference to a resource template | |
| 299 | + */ | |
| 300 | + child = arg->common.value.arg; | |
| 301 | + if (child->common.aml_opcode == AML_INT_BYTELIST_OP) { | |
| 302 | + info->resource_buffer = child->named.data; | |
| 303 | + info->resource_length = | |
| 304 | + (u16)child->named.value.integer; | |
| 305 | + } else { | |
| 306 | + /* Lookup the Connection() namepath, it should already exist */ | |
| 307 | + | |
| 308 | + status = acpi_ns_lookup(walk_state->scope_info, | |
| 309 | + child->common.value. | |
| 310 | + name, ACPI_TYPE_ANY, | |
| 311 | + ACPI_IMODE_EXECUTE, | |
| 312 | + ACPI_NS_DONT_OPEN_SCOPE, | |
| 313 | + walk_state, | |
| 314 | + &info->connection_node); | |
| 315 | + if (ACPI_FAILURE(status)) { | |
| 316 | + ACPI_ERROR_NAMESPACE(child->common. | |
| 317 | + value.name, | |
| 318 | + status); | |
| 319 | + return_ACPI_STATUS(status); | |
| 320 | + } | |
| 321 | + } | |
| 271 | 322 | break; |
| 272 | 323 | |
| 273 | 324 | case AML_INT_NAMEDFIELD_OP: |
| @@ -374,6 +425,8 @@ acpi_ds_create_field(union acpi_parse_object *op, · 100 unmodified lines | ||
| 374 | 425 | } |
| 375 | 426 | } |
| 376 | 427 | |
| 428 | + ACPI_MEMSET(&info, 0, sizeof(struct acpi_create_field_info)); | |
| 429 | + | |
| 377 | 430 | /* Second arg is the field flags */ |
| 378 | 431 | |
| 379 | 432 | arg = arg->common.next; |
| @@ -386,7 +439,6 @@ acpi_ds_create_field(union acpi_parse_object *op, · 6 unmodified lines | ||
| 386 | 439 | info.region_node = region_node; |
| 387 | 440 | |
| 388 | 441 | status = acpi_ds_get_field_names(&info, walk_state, arg->common.next); |
| 389 | − | |
| 390 | 442 | return_ACPI_STATUS(status); |
| 391 | 443 | } |
| 392 | 444 | |
| @@ -474,8 +526,8 @@ acpi_ds_init_field_objects(union acpi_parse_object *op, · 81 unmodified lines | ||
| 474 | 526 | */ |
| 475 | 527 | while (arg) { |
| 476 | 528 | /* |
| 477 | − * Ignore OFFSET and ACCESSAS terms here; we are only interested in the | |
| 478 | − * field names in order to enter them into the namespace. | |
| 529 | + * Ignore OFFSET/ACCESSAS/CONNECTION terms here; we are only interested | |
| 530 | + * in the field names in order to enter them into the namespace. | |
| 479 | 531 | */ |
| 480 | 532 | if (arg->common.aml_opcode == AML_INT_NAMEDFIELD_OP) { |
| 481 | 533 | status = acpi_ns_lookup(walk_state->scope_info, |
| @@ -651,6 +703,5 @@ acpi_ds_create_index_field(union acpi_parse_object *op, · 169 unmodified lines | ||
| 651 | 703 | info.region_node = region_node; |
| 652 | 704 | |
| 653 | 705 | status = acpi_ds_get_field_names(&info, walk_state, arg->common.next); |
| 654 | − | |
| 655 | 706 | return_ACPI_STATUS(status); |
| 656 | 707 | } |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -71,6 +71,12 @@ acpi_status acpi_ev_initialize_events(void) · 59 unmodified lines | ||
| 71 | 71 | |
| 72 | 72 | ACPI_FUNCTION_TRACE(ev_initialize_events); |
| 73 | 73 | |
| 74 | + /* If Hardware Reduced flag is set, there are no fixed events */ | |
| 75 | + | |
| 76 | + if (acpi_gbl_reduced_hardware) { | |
| 77 | + return_ACPI_STATUS(AE_OK); | |
| 78 | + } | |
| 79 | + | |
| 74 | 80 | /* |
| 75 | 81 | * Initialize the Fixed and General Purpose Events. This is done prior to |
| 76 | 82 | * enabling SCIs to prevent interrupts from occurring before the handlers |
| @@ -111,6 +117,12 @@ acpi_status acpi_ev_install_xrupt_handlers(void) · 34 unmodified lines | ||
| 111 | 117 | |
| 112 | 118 | ACPI_FUNCTION_TRACE(ev_install_xrupt_handlers); |
| 113 | 119 | |
| 120 | + /* If Hardware Reduced flag is set, there is no ACPI h/w */ | |
| 121 | + | |
| 122 | + if (acpi_gbl_reduced_hardware) { | |
| 123 | + return_ACPI_STATUS(AE_OK); | |
| 124 | + } | |
| 125 | + | |
| 114 | 126 | /* Install the SCI handler */ |
| 115 | 127 | |
| 116 | 128 | status = acpi_ev_install_sci_handler(); |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -70,6 +70,12 @@ acpi_status acpi_ev_init_global_lock_handler(void) · 58 unmodified lines | ||
| 70 | 70 | |
| 71 | 71 | ACPI_FUNCTION_TRACE(ev_init_global_lock_handler); |
| 72 | 72 | |
| 73 | + /* If Hardware Reduced flag is set, there is no global lock */ | |
| 74 | + | |
| 75 | + if (acpi_gbl_reduced_hardware) { | |
| 76 | + return_ACPI_STATUS(AE_OK); | |
| 77 | + } | |
| 78 | + | |
| 73 | 79 | /* Attempt installation of the global lock handler */ |
| 74 | 80 | |
| 75 | 81 | status = acpi_install_fixed_event_handler(ACPI_EVENT_GLOBAL, |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -329,6 +329,7 @@ acpi_ev_execute_reg_method(union acpi_operand_object *region_obj, u32 function) · 317 unmodified lines | ||
| 329 | 329 | * FUNCTION: acpi_ev_address_space_dispatch |
| 330 | 330 | * |
| 331 | 331 | * PARAMETERS: region_obj - Internal region object |
| 332 | + * field_obj - Corresponding field. Can be NULL. | |
| 332 | 333 | * Function - Read or Write operation |
| 333 | 334 | * region_offset - Where in the region to read or write |
| 334 | 335 | * bit_width - Field width in bits (8, 16, 32, or 64) |
| @@ -344,6 +345,7 @@ acpi_ev_execute_reg_method(union acpi_operand_object *region_obj, u32 function) · 9 unmodified lines | ||
| 344 | 345 | |
| 345 | 346 | acpi_status |
| 346 | 347 | acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj, |
| 348 | + union acpi_operand_object *field_obj, | |
| 347 | 349 | u32 function, |
| 348 | 350 | u32 region_offset, u32 bit_width, u64 *value) |
| 349 | 351 | { |
| @@ -353,6 +355,7 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj, · 3 unmodified lines | ||
| 353 | 355 | union acpi_operand_object *handler_desc; |
| 354 | 356 | union acpi_operand_object *region_obj2; |
| 355 | 357 | void *region_context = NULL; |
| 358 | + struct acpi_connection_info *context; | |
| 356 | 359 | |
| 357 | 360 | ACPI_FUNCTION_TRACE(ev_address_space_dispatch); |
| 358 | 361 | |
| @@ -375,6 +378,8 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj, · 16 unmodified lines | ||
| 375 | 378 | return_ACPI_STATUS(AE_NOT_EXIST); |
| 376 | 379 | } |
| 377 | 380 | |
| 381 | + context = handler_desc->address_space.context; | |
| 382 | + | |
| 378 | 383 | /* |
| 379 | 384 | * It may be the case that the region has never been initialized. |
| 380 | 385 | * Some types of regions require special init code |
| @@ -404,8 +409,7 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj, · 23 unmodified lines | ||
| 404 | 409 | acpi_ex_exit_interpreter(); |
| 405 | 410 | |
| 406 | 411 | status = region_setup(region_obj, ACPI_REGION_ACTIVATE, |
| 407 | − handler_desc->address_space.context, | |
| 408 | − ®ion_context); | |
| 412 | + context, ®ion_context); | |
| 409 | 413 | |
| 410 | 414 | /* Re-enter the interpreter */ |
| 411 | 415 | |
| @@ -455,6 +459,25 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj, · 43 unmodified lines | ||
| 455 | 459 | acpi_ut_get_region_name(region_obj->region. |
| 456 | 460 | space_id))); |
| 457 | 461 | |
| 462 | + /* | |
| 463 | + * Special handling for generic_serial_bus and general_purpose_io: | |
| 464 | + * There are three extra parameters that must be passed to the | |
| 465 | + * handler via the context: | |
| 466 | + * 1) Connection buffer, a resource template from Connection() op. | |
| 467 | + * 2) Length of the above buffer. | |
| 468 | + * 3) Actual access length from the access_as() op. | |
| 469 | + */ | |
| 470 | + if (((region_obj->region.space_id == ACPI_ADR_SPACE_GSBUS) || | |
| 471 | + (region_obj->region.space_id == ACPI_ADR_SPACE_GPIO)) && | |
| 472 | + context && field_obj) { | |
| 473 | + | |
| 474 | + /* Get the Connection (resource_template) buffer */ | |
| 475 | + | |
| 476 | + context->connection = field_obj->field.resource_buffer; | |
| 477 | + context->length = field_obj->field.resource_length; | |
| 478 | + context->access_length = field_obj->field.access_length; | |
| 479 | + } | |
| 480 | + | |
| 458 | 481 | if (!(handler_desc->address_space.handler_flags & |
| 459 | 482 | ACPI_ADDR_HANDLER_DEFAULT_INSTALLED)) { |
| 460 | 483 | /* |
| @@ -469,7 +492,7 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj, · 8 unmodified lines | ||
| 469 | 492 | |
| 470 | 493 | status = handler(function, |
| 471 | 494 | (region_obj->region.address + region_offset), |
| 472 | − bit_width, value, handler_desc->address_space.context, | |
| 495 | + bit_width, value, context, | |
| 473 | 496 | region_obj2->extra.region_context); |
| 474 | 497 | |
| 475 | 498 | if (ACPI_FAILURE(status)) { |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | ******************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -297,9 +297,9 @@ acpi_ex_region_read(union acpi_operand_object *obj_desc, u32 length, u8 *buffer) · 285 unmodified lines | ||
| 297 | 297 | /* Bytewise reads */ |
| 298 | 298 | |
| 299 | 299 | for (i = 0; i < length; i++) { |
| 300 | − status = acpi_ev_address_space_dispatch(obj_desc, ACPI_READ, | |
| 301 | − region_offset, 8, | |
| 302 | − &value); | |
| 300 | + status = | |
| 301 | + acpi_ev_address_space_dispatch(obj_desc, NULL, ACPI_READ, | |
| 302 | + region_offset, 8, &value); | |
| 303 | 303 | if (ACPI_FAILURE(status)) { |
| 304 | 304 | return status; |
| 305 | 305 | } |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -267,7 +267,7 @@ acpi_status acpi_ex_create_mutex(struct acpi_walk_state *walk_state) · 255 unmodified lines | ||
| 267 | 267 | * |
| 268 | 268 | * PARAMETERS: aml_start - Pointer to the region declaration AML |
| 269 | 269 | * aml_length - Max length of the declaration AML |
| 270 | − * region_space - space_iD for the region | |
| 270 | + * space_id - Address space ID for the region | |
| 271 | 271 | * walk_state - Current state |
| 272 | 272 | * |
| 273 | 273 | * RETURN: Status |
| @@ -279,7 +279,7 @@ acpi_status acpi_ex_create_mutex(struct acpi_walk_state *walk_state) · 5 unmodified lines | ||
| 279 | 279 | acpi_status |
| 280 | 280 | acpi_ex_create_region(u8 * aml_start, |
| 281 | 281 | u32 aml_length, |
| 282 | − u8 region_space, struct acpi_walk_state *walk_state) | |
| 282 | + u8 space_id, struct acpi_walk_state *walk_state) | |
| 283 | 283 | { |
| 284 | 284 | acpi_status status; |
| 285 | 285 | union acpi_operand_object *obj_desc; |
| @@ -304,16 +304,19 @@ acpi_ex_create_region(u8 * aml_start, · 18 unmodified lines | ||
| 304 | 304 | * Space ID must be one of the predefined IDs, or in the user-defined |
| 305 | 305 | * range |
| 306 | 306 | */ |
| 307 | − if ((region_space >= ACPI_NUM_PREDEFINED_REGIONS) && | |
| 308 | − (region_space < ACPI_USER_REGION_BEGIN) && | |
| 309 | − (region_space != ACPI_ADR_SPACE_DATA_TABLE)) { | |
| 310 | − ACPI_ERROR((AE_INFO, "Invalid AddressSpace type 0x%X", | |
| 311 | − region_space)); | |
| 312 | − return_ACPI_STATUS(AE_AML_INVALID_SPACE_ID); | |
| 307 | + if (!acpi_is_valid_space_id(space_id)) { | |
| 308 | + /* | |
| 309 | + * Print an error message, but continue. We don't want to abort | |
| 310 | + * a table load for this exception. Instead, if the region is | |
| 311 | + * actually used at runtime, abort the executing method. | |
| 312 | + */ | |
| 313 | + ACPI_ERROR((AE_INFO, | |
| 314 | + "Invalid/unknown Address Space ID: 0x%2.2X", | |
| 315 | + space_id)); | |
| 313 | 316 | } |
| 314 | 317 | |
| 315 | 318 | ACPI_DEBUG_PRINT((ACPI_DB_LOAD, "Region Type - %s (0x%X)\n", |
| 316 | − acpi_ut_get_region_name(region_space), region_space)); | |
| 319 | + acpi_ut_get_region_name(space_id), space_id)); | |
| 317 | 320 | |
| 318 | 321 | /* Create the region descriptor */ |
| 319 | 322 | |
| @@ -330,10 +333,16 @@ acpi_ex_create_region(u8 * aml_start, · 10 unmodified lines | ||
| 330 | 333 | region_obj2 = obj_desc->common.next_object; |
| 331 | 334 | region_obj2->extra.aml_start = aml_start; |
| 332 | 335 | region_obj2->extra.aml_length = aml_length; |
| 336 | + if (walk_state->scope_info) { | |
| 337 | + region_obj2->extra.scope_node = | |
| 338 | + walk_state->scope_info->scope.node; | |
| 339 | + } else { | |
| 340 | + region_obj2->extra.scope_node = node; | |
| 341 | + } | |
| 333 | 342 | |
| 334 | 343 | /* Init the region from the operands */ |
| 335 | 344 | |
| 336 | − obj_desc->region.space_id = region_space; | |
| 345 | + obj_desc->region.space_id = space_id; | |
| 337 | 346 | obj_desc->region.address = 0; |
| 338 | 347 | obj_desc->region.length = 0; |
| 339 | 348 | obj_desc->region.node = node; |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -192,10 +192,13 @@ static struct acpi_exdump_info acpi_ex_dump_buffer_field[3] = { · 180 unmodified lines | ||
| 192 | 192 | "Buffer Object"} |
| 193 | 193 | }; |
| 194 | 194 | |
| 195 | −static struct acpi_exdump_info acpi_ex_dump_region_field[3] = { | |
| 195 | +static struct acpi_exdump_info acpi_ex_dump_region_field[5] = { | |
| 196 | 196 | {ACPI_EXD_INIT, ACPI_EXD_TABLE_SIZE(acpi_ex_dump_region_field), NULL}, |
| 197 | 197 | {ACPI_EXD_FIELD, 0, NULL}, |
| 198 | − {ACPI_EXD_POINTER, ACPI_EXD_OFFSET(field.region_obj), "Region Object"} | |
| 198 | + {ACPI_EXD_UINT8, ACPI_EXD_OFFSET(field.access_length), "AccessLength"}, | |
| 199 | + {ACPI_EXD_POINTER, ACPI_EXD_OFFSET(field.region_obj), "Region Object"}, | |
| 200 | + {ACPI_EXD_POINTER, ACPI_EXD_OFFSET(field.resource_buffer), | |
| 201 | + "ResourceBuffer"} | |
| 199 | 202 | }; |
| 200 | 203 | |
| 201 | 204 | static struct acpi_exdump_info acpi_ex_dump_bank_field[5] = { |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -100,18 +100,25 @@ acpi_ex_read_data_from_field(struct acpi_walk_state *walk_state, · 88 unmodified lines | ||
| 100 | 100 | (obj_desc->field.region_obj->region.space_id == |
| 101 | 101 | ACPI_ADR_SPACE_SMBUS |
| 102 | 102 | || obj_desc->field.region_obj->region.space_id == |
| 103 | + ACPI_ADR_SPACE_GSBUS | |
| 104 | + || obj_desc->field.region_obj->region.space_id == | |
| 103 | 105 | ACPI_ADR_SPACE_IPMI)) { |
| 104 | 106 | /* |
| 105 | − * This is an SMBus or IPMI read. We must create a buffer to hold | |
| 107 | + * This is an SMBus, GSBus or IPMI read. We must create a buffer to hold | |
| 106 | 108 | * the data and then directly access the region handler. |
| 107 | 109 | * |
| 108 | − * Note: Smbus protocol value is passed in upper 16-bits of Function | |
| 110 | + * Note: SMBus and GSBus protocol value is passed in upper 16-bits of Function | |
| 109 | 111 | */ |
| 110 | 112 | if (obj_desc->field.region_obj->region.space_id == |
| 111 | 113 | ACPI_ADR_SPACE_SMBUS) { |
| 112 | 114 | length = ACPI_SMBUS_BUFFER_SIZE; |
| 113 | 115 | function = |
| 114 | 116 | ACPI_READ | (obj_desc->field.attribute << 16); |
| 117 | + } else if (obj_desc->field.region_obj->region.space_id == | |
| 118 | + ACPI_ADR_SPACE_GSBUS) { | |
| 119 | + length = ACPI_GSBUS_BUFFER_SIZE; | |
| 120 | + function = | |
| 121 | + ACPI_READ | (obj_desc->field.attribute << 16); | |
| 115 | 122 | } else { /* IPMI */ |
| 116 | 123 | |
| 117 | 124 | length = ACPI_IPMI_BUFFER_SIZE; |
| @@ -248,21 +255,23 @@ acpi_ex_write_data_to_field(union acpi_operand_object *source_desc, · 130 unmodified lines | ||
| 248 | 255 | (obj_desc->field.region_obj->region.space_id == |
| 249 | 256 | ACPI_ADR_SPACE_SMBUS |
| 250 | 257 | || obj_desc->field.region_obj->region.space_id == |
| 258 | + ACPI_ADR_SPACE_GSBUS | |
| 259 | + || obj_desc->field.region_obj->region.space_id == | |
| 251 | 260 | ACPI_ADR_SPACE_IPMI)) { |
| 252 | 261 | /* |
| 253 | − * This is an SMBus or IPMI write. We will bypass the entire field | |
| 262 | + * This is an SMBus, GSBus or IPMI write. We will bypass the entire field | |
| 254 | 263 | * mechanism and handoff the buffer directly to the handler. For |
| 255 | 264 | * these address spaces, the buffer is bi-directional; on a write, |
| 256 | 265 | * return data is returned in the same buffer. |
| 257 | 266 | * |
| 258 | 267 | * Source must be a buffer of sufficient size: |
| 259 | − * ACPI_SMBUS_BUFFER_SIZE or ACPI_IPMI_BUFFER_SIZE. | |
| 268 | + * ACPI_SMBUS_BUFFER_SIZE, ACPI_GSBUS_BUFFER_SIZE, or ACPI_IPMI_BUFFER_SIZE. | |
| 260 | 269 | * |
| 261 | − * Note: SMBus protocol type is passed in upper 16-bits of Function | |
| 270 | + * Note: SMBus and GSBus protocol type is passed in upper 16-bits of Function | |
| 262 | 271 | */ |
| 263 | 272 | if (source_desc->common.type != ACPI_TYPE_BUFFER) { |
| 264 | 273 | ACPI_ERROR((AE_INFO, |
| 265 | − "SMBus or IPMI write requires Buffer, found type %s", | |
| 274 | + "SMBus/IPMI/GenericSerialBus write requires Buffer, found type %s", | |
| 266 | 275 | acpi_ut_get_object_type_name(source_desc))); |
| 267 | 276 | |
| 268 | 277 | return_ACPI_STATUS(AE_AML_OPERAND_TYPE); |
| @@ -273,6 +282,11 @@ acpi_ex_write_data_to_field(union acpi_operand_object *source_desc, · 4 unmodified lines | ||
| 273 | 282 | length = ACPI_SMBUS_BUFFER_SIZE; |
| 274 | 283 | function = |
| 275 | 284 | ACPI_WRITE | (obj_desc->field.attribute << 16); |
| 285 | + } else if (obj_desc->field.region_obj->region.space_id == | |
| 286 | + ACPI_ADR_SPACE_GSBUS) { | |
| 287 | + length = ACPI_GSBUS_BUFFER_SIZE; | |
| 288 | + function = | |
| 289 | + ACPI_WRITE | (obj_desc->field.attribute << 16); | |
| 276 | 290 | } else { /* IPMI */ |
| 277 | 291 | |
| 278 | 292 | length = ACPI_IPMI_BUFFER_SIZE; |
| @@ -281,7 +295,7 @@ acpi_ex_write_data_to_field(union acpi_operand_object *source_desc, · 2 unmodified lines | ||
| 281 | 295 | |
| 282 | 296 | if (source_desc->buffer.length < length) { |
| 283 | 297 | ACPI_ERROR((AE_INFO, |
| 284 | − "SMBus or IPMI write requires Buffer of length %u, found length %u", | |
| 298 | + "SMBus/IPMI/GenericSerialBus write requires Buffer of length %u, found length %u", | |
| 285 | 299 | length, source_desc->buffer.length)); |
| 286 | 300 | |
| 287 | 301 | return_ACPI_STATUS(AE_AML_BUFFER_LIMIT); |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -86,6 +86,7 @@ acpi_ex_setup_region(union acpi_operand_object *obj_desc, · 74 unmodified lines | ||
| 86 | 86 | { |
| 87 | 87 | acpi_status status = AE_OK; |
| 88 | 88 | union acpi_operand_object *rgn_desc; |
| 89 | + u8 space_id; | |
| 89 | 90 | |
| 90 | 91 | ACPI_FUNCTION_TRACE_U32(ex_setup_region, field_datum_byte_offset); |
| 91 | 92 | |
| @@ -101,6 +102,17 @@ acpi_ex_setup_region(union acpi_operand_object *obj_desc, · 9 unmodified lines | ||
| 101 | 102 | return_ACPI_STATUS(AE_AML_OPERAND_TYPE); |
| 102 | 103 | } |
| 103 | 104 | |
| 105 | + space_id = rgn_desc->region.space_id; | |
| 106 | + | |
| 107 | + /* Validate the Space ID */ | |
| 108 | + | |
| 109 | + if (!acpi_is_valid_space_id(space_id)) { | |
| 110 | + ACPI_ERROR((AE_INFO, | |
| 111 | + "Invalid/unknown Address Space ID: 0x%2.2X", | |
| 112 | + space_id)); | |
| 113 | + return_ACPI_STATUS(AE_AML_INVALID_SPACE_ID); | |
| 114 | + } | |
| 115 | + | |
| 104 | 116 | /* |
| 105 | 117 | * If the Region Address and Length have not been previously evaluated, |
| 106 | 118 | * evaluate them now and save the results. |
| @@ -119,11 +131,12 @@ acpi_ex_setup_region(union acpi_operand_object *obj_desc, · 12 unmodified lines | ||
| 119 | 131 | } |
| 120 | 132 | |
| 121 | 133 | /* |
| 122 | − * Exit now for SMBus or IPMI address space, it has a non-linear | |
| 134 | + * Exit now for SMBus, GSBus or IPMI address space, it has a non-linear | |
| 123 | 135 | * address space and the request cannot be directly validated |
| 124 | 136 | */ |
| 125 | − if (rgn_desc->region.space_id == ACPI_ADR_SPACE_SMBUS || | |
| 126 | − rgn_desc->region.space_id == ACPI_ADR_SPACE_IPMI) { | |
| 137 | + if (space_id == ACPI_ADR_SPACE_SMBUS || | |
| 138 | + space_id == ACPI_ADR_SPACE_GSBUS || | |
| 139 | + space_id == ACPI_ADR_SPACE_IPMI) { | |
| 127 | 140 | |
| 128 | 141 | /* SMBus or IPMI has a non-linear address space */ |
| 129 | 142 | |
| @@ -271,11 +284,12 @@ acpi_ex_access_region(union acpi_operand_object *obj_desc, · 141 unmodified lines | ||
| 271 | 284 | |
| 272 | 285 | /* Invoke the appropriate address_space/op_region handler */ |
| 273 | 286 | |
| 274 | − status = | |
| 275 | − acpi_ev_address_space_dispatch(rgn_desc, function, region_offset, | |
| 276 | − ACPI_MUL_8(obj_desc->common_field. | |
| 277 | − access_byte_width), | |
| 278 | − value); | |
| 287 | + status = acpi_ev_address_space_dispatch(rgn_desc, obj_desc, | |
| 288 | + function, region_offset, | |
| 289 | + ACPI_MUL_8(obj_desc-> | |
| 290 | + common_field. | |
| 291 | + access_byte_width), | |
| 292 | + value); | |
| 279 | 293 | |
| 280 | 294 | if (ACPI_FAILURE(status)) { |
| 281 | 295 | if (status == AE_NOT_IMPLEMENTED) { |
| @@ -316,6 +330,7 @@ acpi_ex_access_region(union acpi_operand_object *obj_desc, · 34 unmodified lines | ||
| 316 | 330 | static u8 |
| 317 | 331 | acpi_ex_register_overflow(union acpi_operand_object *obj_desc, u64 value) |
| 318 | 332 | { |
| 333 | + ACPI_FUNCTION_NAME(ex_register_overflow); | |
| 319 | 334 | |
| 320 | 335 | if (obj_desc->common_field.bit_length >= ACPI_INTEGER_BIT_SIZE) { |
| 321 | 336 | /* |
| @@ -330,6 +345,11 @@ acpi_ex_register_overflow(union acpi_operand_object *obj_desc, u64 value) · 8 unmodified lines | ||
| 330 | 345 | * The Value is larger than the maximum value that can fit into |
| 331 | 346 | * the register. |
| 332 | 347 | */ |
| 348 | + ACPI_ERROR((AE_INFO, | |
| 349 | + "Index value 0x%8.8X%8.8X overflows field width 0x%X", | |
| 350 | + ACPI_FORMAT_UINT64(value), | |
| 351 | + obj_desc->common_field.bit_length)); | |
| 352 | + | |
| 333 | 353 | return (TRUE); |
| 334 | 354 | } |
| 335 | 355 | |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -47,6 +47,7 @@ · 34 unmodified lines | ||
| 47 | 47 | #include "acinterp.h" |
| 48 | 48 | #include "amlcode.h" |
| 49 | 49 | #include "acnamesp.h" |
| 50 | +#include "acdispat.h" | |
| 50 | 51 | |
| 51 | 52 | #define _COMPONENT ACPI_EXECUTER |
| 52 | 53 | ACPI_MODULE_NAME("exprep") |
| @@ -455,6 +456,30 @@ acpi_status acpi_ex_prep_field_value(struct acpi_create_field_info *info) · 402 unmodified lines | ||
| 455 | 456 | obj_desc->field.region_obj = |
| 456 | 457 | acpi_ns_get_attached_object(info->region_node); |
| 457 | 458 | |
| 459 | + /* Fields specific to generic_serial_bus fields */ | |
| 460 | + | |
| 461 | + obj_desc->field.access_length = info->access_length; | |
| 462 | + | |
| 463 | + if (info->connection_node) { | |
| 464 | + second_desc = info->connection_node->object; | |
| 465 | + if (!(second_desc->common.flags & AOPOBJ_DATA_VALID)) { | |
| 466 | + status = | |
| 467 | + acpi_ds_get_buffer_arguments(second_desc); | |
| 468 | + if (ACPI_FAILURE(status)) { | |
| 469 | + acpi_ut_delete_object_desc(obj_desc); | |
| 470 | + return_ACPI_STATUS(status); | |
| 471 | + } | |
| 472 | + } | |
| 473 | + | |
| 474 | + obj_desc->field.resource_buffer = | |
| 475 | + second_desc->buffer.pointer; | |
| 476 | + obj_desc->field.resource_length = | |
| 477 | + (u16)second_desc->buffer.length; | |
| 478 | + } else if (info->resource_buffer) { | |
| 479 | + obj_desc->field.resource_buffer = info->resource_buffer; | |
| 480 | + obj_desc->field.resource_length = info->resource_length; | |
| 481 | + } | |
| 482 | + | |
| 458 | 483 | /* Allow full data read from EC address space */ |
| 459 | 484 | |
| 460 | 485 | if ((obj_desc->field.region_obj->region.space_id == |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -7,7 +7,7 @@ · 6 unmodified lines | ||
| 7 | 7 | *****************************************************************************/ |
| 8 | 8 | |
| 9 | 9 | /* |
| 10 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 10 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 11 | 11 | * All rights reserved. |
| 12 | 12 | * |
| 13 | 13 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -435,4 +435,29 @@ void acpi_ex_integer_to_string(char *out_string, u64 value) · 422 unmodified lines | ||
| 435 | 435 | } |
| 436 | 436 | } |
| 437 | 437 | |
| 438 | +/******************************************************************************* | |
| 439 | + * | |
| 440 | + * FUNCTION: acpi_is_valid_space_id | |
| 441 | + * | |
| 442 | + * PARAMETERS: space_id - ID to be validated | |
| 443 | + * | |
| 444 | + * RETURN: TRUE if valid/supported ID. | |
| 445 | + * | |
| 446 | + * DESCRIPTION: Validate an operation region space_iD. | |
| 447 | + * | |
| 448 | + ******************************************************************************/ | |
| 449 | + | |
| 450 | +u8 acpi_is_valid_space_id(u8 space_id) | |
| 451 | +{ | |
| 452 | + | |
| 453 | + if ((space_id >= ACPI_NUM_PREDEFINED_REGIONS) && | |
| 454 | + (space_id < ACPI_USER_REGION_BEGIN) && | |
| 455 | + (space_id != ACPI_ADR_SPACE_DATA_TABLE) && | |
| 456 | + (space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) { | |
| 457 | + return (FALSE); | |
| 458 | + } | |
| 459 | + | |
| 460 | + return (TRUE); | |
| 461 | +} | |
| 462 | + | |
| 438 | 463 | #endif |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -7,7 +7,7 @@ · 6 unmodified lines | ||
| 7 | 7 | ******************************************************************************/ |
| 8 | 8 | |
| 9 | 9 | /* |
| 10 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 10 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 11 | 11 | * All rights reserved. |
| 12 | 12 | * |
| 13 | 13 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -134,6 +134,8 @@ acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width) · 121 unmodified lines | ||
| 134 | 134 | /* Supported widths are 8/16/32 */ |
| 135 | 135 | |
| 136 | 136 | if ((bit_width != 8) && (bit_width != 16) && (bit_width != 32)) { |
| 137 | + ACPI_ERROR((AE_INFO, | |
| 138 | + "Bad BitWidth parameter: %8.8X", bit_width)); | |
| 137 | 139 | return AE_BAD_PARAMETER; |
| 138 | 140 | } |
| 139 | 141 | |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | ******************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -620,6 +620,7 @@ acpi_ns_check_package(struct acpi_predefined_data *data, · 607 unmodified lines | ||
| 620 | 620 | case ACPI_PTYPE2_FIXED: |
| 621 | 621 | case ACPI_PTYPE2_MIN: |
| 622 | 622 | case ACPI_PTYPE2_COUNT: |
| 623 | + case ACPI_PTYPE2_FIX_VAR: | |
| 623 | 624 | |
| 624 | 625 | /* |
| 625 | 626 | * These types all return a single Package that consists of a |
| @@ -759,6 +760,34 @@ acpi_ns_check_package_list(struct acpi_predefined_data *data, · 133 unmodified lines | ||
| 759 | 760 | } |
| 760 | 761 | break; |
| 761 | 762 | |
| 763 | + case ACPI_PTYPE2_FIX_VAR: | |
| 764 | + /* | |
| 765 | + * Each subpackage has a fixed number of elements and an | |
| 766 | + * optional element | |
| 767 | + */ | |
| 768 | + expected_count = | |
| 769 | + package->ret_info.count1 + package->ret_info.count2; | |
| 770 | + if (sub_package->package.count < expected_count) { | |
| 771 | + goto package_too_small; | |
| 772 | + } | |
| 773 | + | |
| 774 | + status = | |
| 775 | + acpi_ns_check_package_elements(data, sub_elements, | |
| 776 | + package->ret_info. | |
| 777 | + object_type1, | |
| 778 | + package->ret_info. | |
| 779 | + count1, | |
| 780 | + package->ret_info. | |
| 781 | + object_type2, | |
| 782 | + sub_package->package. | |
| 783 | + count - | |
| 784 | + package->ret_info. | |
| 785 | + count1, 0); | |
| 786 | + if (ACPI_FAILURE(status)) { | |
| 787 | + return (status); | |
| 788 | + } | |
| 789 | + break; | |
| 790 | + | |
| 762 | 791 | case ACPI_PTYPE2_FIXED: |
| 763 | 792 | |
| 764 | 793 | /* Each sub-package has a fixed length */ |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -634,6 +634,7 @@ acpi_ns_remove_null_elements(struct acpi_predefined_data *data, · 622 unmodified lines | ||
| 634 | 634 | case ACPI_PTYPE2_FIXED: |
| 635 | 635 | case ACPI_PTYPE2_MIN: |
| 636 | 636 | case ACPI_PTYPE2_REV_FIXED: |
| 637 | + case ACPI_PTYPE2_FIX_VAR: | |
| 637 | 638 | break; |
| 638 | 639 | |
| 639 | 640 | default: |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -467,11 +467,12 @@ acpi_ns_repair_HID(struct acpi_predefined_data *data, · 454 unmodified lines | ||
| 467 | 467 | } |
| 468 | 468 | |
| 469 | 469 | /* |
| 470 | − * Copy and uppercase the string. From the ACPI specification: | |
| 470 | + * Copy and uppercase the string. From the ACPI 5.0 specification: | |
| 471 | 471 | * |
| 472 | 472 | * A valid PNP ID must be of the form "AAA####" where A is an uppercase |
| 473 | 473 | * letter and # is a hex digit. A valid ACPI ID must be of the form |
| 474 | − * "ACPI####" where # is a hex digit. | |
| 474 | + * "NNNN####" where N is an uppercase letter or decimal digit, and | |
| 475 | + * # is a hex digit. | |
| 475 | 476 | */ |
| 476 | 477 | for (dest = new_string->string.pointer; *source; dest++, source++) { |
| 477 | 478 | *dest = (char)ACPI_TOUPPER(*source); |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | ******************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | ******************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -484,34 +484,54 @@ acpi_ps_get_next_simple_arg(struct acpi_parse_state *parser_state, · 472 unmodified lines | ||
| 484 | 484 | static union acpi_parse_object *acpi_ps_get_next_field(struct acpi_parse_state |
| 485 | 485 | *parser_state) |
| 486 | 486 | { |
| 487 | − u32 aml_offset = (u32) | |
| 488 | − ACPI_PTR_DIFF(parser_state->aml, | |
| 489 | − parser_state->aml_start); | |
| 487 | + u32 aml_offset; | |
| 490 | 488 | union acpi_parse_object *field; |
| 489 | + union acpi_parse_object *arg = NULL; | |
| 491 | 490 | u16 opcode; |
| 492 | 491 | u32 name; |
| 492 | + u8 access_type; | |
| 493 | + u8 access_attribute; | |
| 494 | + u8 access_length; | |
| 495 | + u32 pkg_length; | |
| 496 | + u8 *pkg_end; | |
| 497 | + u32 buffer_length; | |
| 493 | 498 | |
| 494 | 499 | ACPI_FUNCTION_TRACE(ps_get_next_field); |
| 495 | 500 | |
| 501 | + aml_offset = | |
| 502 | + (u32)ACPI_PTR_DIFF(parser_state->aml, parser_state->aml_start); | |
| 503 | + | |
| 496 | 504 | /* Determine field type */ |
| 497 | 505 | |
| 498 | 506 | switch (ACPI_GET8(parser_state->aml)) { |
| 499 | − default: | |
| 507 | + case AML_FIELD_OFFSET_OP: | |
| 500 | 508 | |
| 501 | − opcode = AML_INT_NAMEDFIELD_OP; | |
| 509 | + opcode = AML_INT_RESERVEDFIELD_OP; | |
| 510 | + parser_state->aml++; | |
| 502 | 511 | break; |
| 503 | 512 | |
| 504 | − case 0x00: | |
| 513 | + case AML_FIELD_ACCESS_OP: | |
| 505 | 514 | |
| 506 | − opcode = AML_INT_RESERVEDFIELD_OP; | |
| 515 | + opcode = AML_INT_ACCESSFIELD_OP; | |
| 507 | 516 | parser_state->aml++; |
| 508 | 517 | break; |
| 509 | 518 | |
| 510 | − case 0x01: | |
| 519 | + case AML_FIELD_CONNECTION_OP: | |
| 511 | 520 | |
| 512 | − opcode = AML_INT_ACCESSFIELD_OP; | |
| 521 | + opcode = AML_INT_CONNECTION_OP; | |
| 522 | + parser_state->aml++; | |
| 523 | + break; | |
| 524 | + | |
| 525 | + case AML_FIELD_EXT_ACCESS_OP: | |
| 526 | + | |
| 527 | + opcode = AML_INT_EXTACCESSFIELD_OP; | |
| 513 | 528 | parser_state->aml++; |
| 514 | 529 | break; |
| 530 | + | |
| 531 | + default: | |
| 532 | + | |
| 533 | + opcode = AML_INT_NAMEDFIELD_OP; | |
| 534 | + break; | |
| 515 | 535 | } |
| 516 | 536 | |
| 517 | 537 | /* Allocate a new field op */ |
| @@ -549,16 +569,111 @@ static union acpi_parse_object *acpi_ps_get_next_field(struct acpi_parse_state · 31 unmodified lines | ||
| 549 | 569 | break; |
| 550 | 570 | |
| 551 | 571 | case AML_INT_ACCESSFIELD_OP: |
| 572 | + case AML_INT_EXTACCESSFIELD_OP: | |
| 552 | 573 | |
| 553 | 574 | /* |
| 554 | 575 | * Get access_type and access_attrib and merge into the field Op |
| 555 | − * access_type is first operand, access_attribute is second | |
| 576 | + * access_type is first operand, access_attribute is second. stuff | |
| 577 | + * these bytes into the node integer value for convenience. | |
| 556 | 578 | */ |
| 557 | − field->common.value.integer = | |
| 558 | − (((u32) ACPI_GET8(parser_state->aml) << 8)); | |
| 579 | + | |
| 580 | + /* Get the two bytes (Type/Attribute) */ | |
| 581 | + | |
| 582 | + access_type = ACPI_GET8(parser_state->aml); | |
| 559 | 583 | parser_state->aml++; |
| 560 | − field->common.value.integer |= ACPI_GET8(parser_state->aml); | |
| 584 | + access_attribute = ACPI_GET8(parser_state->aml); | |
| 561 | 585 | parser_state->aml++; |
| 586 | + | |
| 587 | + field->common.value.integer = (u8)access_type; | |
| 588 | + field->common.value.integer |= (u16)(access_attribute << 8); | |
| 589 | + | |
| 590 | + /* This opcode has a third byte, access_length */ | |
| 591 | + | |
| 592 | + if (opcode == AML_INT_EXTACCESSFIELD_OP) { | |
| 593 | + access_length = ACPI_GET8(parser_state->aml); | |
| 594 | + parser_state->aml++; | |
| 595 | + | |
| 596 | + field->common.value.integer |= | |
| 597 | + (u32)(access_length << 16); | |
| 598 | + } | |
| 599 | + break; | |
| 600 | + | |
| 601 | + case AML_INT_CONNECTION_OP: | |
| 602 | + | |
| 603 | + /* | |
| 604 | + * Argument for Connection operator can be either a Buffer | |
| 605 | + * (resource descriptor), or a name_string. | |
| 606 | + */ | |
| 607 | + if (ACPI_GET8(parser_state->aml) == AML_BUFFER_OP) { | |
| 608 | + parser_state->aml++; | |
| 609 | + | |
| 610 | + pkg_end = parser_state->aml; | |
| 611 | + pkg_length = | |
| 612 | + acpi_ps_get_next_package_length(parser_state); | |
| 613 | + pkg_end += pkg_length; | |
| 614 | + | |
| 615 | + if (parser_state->aml < pkg_end) { | |
| 616 | + | |
| 617 | + /* Non-empty list */ | |
| 618 | + | |
| 619 | + arg = acpi_ps_alloc_op(AML_INT_BYTELIST_OP); | |
| 620 | + if (!arg) { | |
| 621 | + return_PTR(NULL); | |
| 622 | + } | |
| 623 | + | |
| 624 | + /* Get the actual buffer length argument */ | |
| 625 | + | |
| 626 | + opcode = ACPI_GET8(parser_state->aml); | |
| 627 | + parser_state->aml++; | |
| 628 | + | |
| 629 | + switch (opcode) { | |
| 630 | + case AML_BYTE_OP: /* AML_BYTEDATA_ARG */ | |
| 631 | + buffer_length = | |
| 632 | + ACPI_GET8(parser_state->aml); | |
| 633 | + parser_state->aml += 1; | |
| 634 | + break; | |
| 635 | + | |
| 636 | + case AML_WORD_OP: /* AML_WORDDATA_ARG */ | |
| 637 | + buffer_length = | |
| 638 | + ACPI_GET16(parser_state->aml); | |
| 639 | + parser_state->aml += 2; | |
| 640 | + break; | |
| 641 | + | |
| 642 | + case AML_DWORD_OP: /* AML_DWORDATA_ARG */ | |
| 643 | + buffer_length = | |
| 644 | + ACPI_GET32(parser_state->aml); | |
| 645 | + parser_state->aml += 4; | |
| 646 | + break; | |
| 647 | + | |
| 648 | + default: | |
| 649 | + buffer_length = 0; | |
| 650 | + break; | |
| 651 | + } | |
| 652 | + | |
| 653 | + /* Fill in bytelist data */ | |
| 654 | + | |
| 655 | + arg->named.value.size = buffer_length; | |
| 656 | + arg->named.data = parser_state->aml; | |
| 657 | + } | |
| 658 | + | |
| 659 | + /* Skip to End of byte data */ | |
| 660 | + | |
| 661 | + parser_state->aml = pkg_end; | |
| 662 | + } else { | |
| 663 | + arg = acpi_ps_alloc_op(AML_INT_NAMEPATH_OP); | |
| 664 | + if (!arg) { | |
| 665 | + return_PTR(NULL); | |
| 666 | + } | |
| 667 | + | |
| 668 | + /* Get the Namestring argument */ | |
| 669 | + | |
| 670 | + arg->common.value.name = | |
| 671 | + acpi_ps_get_next_namestring(parser_state); | |
| 672 | + } | |
| 673 | + | |
| 674 | + /* Link the buffer/namestring to parent (CONNECTION_OP) */ | |
| 675 | + | |
| 676 | + acpi_ps_append_arg(field, arg); | |
| 562 | 677 | break; |
| 563 | 678 | |
| 564 | 679 | default: |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -638,7 +638,16 @@ const struct acpi_opcode_info acpi_gbl_aml_op_info[AML_NUM_OPCODES] = { · 626 unmodified lines | ||
| 638 | 638 | |
| 639 | 639 | /* 7E */ ACPI_OP("Timer", ARGP_TIMER_OP, ARGI_TIMER_OP, ACPI_TYPE_ANY, |
| 640 | 640 | AML_CLASS_EXECUTE, AML_TYPE_EXEC_0A_0T_1R, |
| 641 | − AML_FLAGS_EXEC_0A_0T_1R) | |
| 641 | + AML_FLAGS_EXEC_0A_0T_1R), | |
| 642 | + | |
| 643 | +/* ACPI 5.0 opcodes */ | |
| 644 | + | |
| 645 | +/* 7F */ ACPI_OP("-ConnectField-", ARGP_CONNECTFIELD_OP, | |
| 646 | + ARGI_CONNECTFIELD_OP, ACPI_TYPE_ANY, | |
| 647 | + AML_CLASS_INTERNAL, AML_TYPE_BOGUS, AML_HAS_ARGS), | |
| 648 | +/* 80 */ ACPI_OP("-ExtAccessField-", ARGP_CONNECTFIELD_OP, | |
| 649 | + ARGI_CONNECTFIELD_OP, ACPI_TYPE_ANY, | |
| 650 | + AML_CLASS_INTERNAL, AML_TYPE_BOGUS, 0) | |
| 642 | 651 | |
| 643 | 652 | /*! [End] no source code translation !*/ |
| 644 | 653 | }; |
| @@ -657,7 +666,7 @@ static const u8 acpi_gbl_short_op_index[256] = { · 12 unmodified lines | ||
| 657 | 666 | /* 0x20 */ _UNK, _UNK, _UNK, _UNK, _UNK, _UNK, _UNK, _UNK, |
| 658 | 667 | /* 0x28 */ _UNK, _UNK, _UNK, _UNK, _UNK, 0x63, _PFX, _PFX, |
| 659 | 668 | /* 0x30 */ 0x67, 0x66, 0x68, 0x65, 0x69, 0x64, 0x6A, 0x7D, |
| 660 | −/* 0x38 */ _UNK, _UNK, _UNK, _UNK, _UNK, _UNK, _UNK, _UNK, | |
| 669 | +/* 0x38 */ 0x7F, 0x80, _UNK, _UNK, _UNK, _UNK, _UNK, _UNK, | |
| 661 | 670 | /* 0x40 */ _UNK, _ASC, _ASC, _ASC, _ASC, _ASC, _ASC, _ASC, |
| 662 | 671 | /* 0x48 */ _ASC, _ASC, _ASC, _ASC, _ASC, _ASC, _ASC, _ASC, |
| 663 | 672 | /* 0x50 */ _ASC, _ASC, _ASC, _ASC, _ASC, _ASC, _ASC, _ASC, |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -74,6 +74,12 @@ union acpi_parse_object *acpi_ps_get_arg(union acpi_parse_object *op, u32 argn) · 62 unmodified lines | ||
| 74 | 74 | |
| 75 | 75 | ACPI_FUNCTION_ENTRY(); |
| 76 | 76 | |
| 77 | +/* | |
| 78 | + if (Op->Common.aml_opcode == AML_INT_CONNECTION_OP) | |
| 79 | + { | |
| 80 | + return (Op->Common.Value.Arg); | |
| 81 | + } | |
| 82 | +*/ | |
| 77 | 83 | /* Get the info structure for this opcode */ |
| 78 | 84 | |
| 79 | 85 | op_info = acpi_ps_get_opcode_info(op->common.aml_opcode); |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -313,6 +313,38 @@ acpi_rs_get_aml_length(struct acpi_resource * resource, acpi_size * size_needed) · 301 unmodified lines | ||
| 313 | 313 | resource_source)); |
| 314 | 314 | break; |
| 315 | 315 | |
| 316 | + case ACPI_RESOURCE_TYPE_GPIO: | |
| 317 | + | |
| 318 | + total_size = | |
| 319 | + (acpi_rs_length) (total_size + | |
| 320 | + (resource->data.gpio. | |
| 321 | + pin_table_length * 2) + | |
| 322 | + resource->data.gpio. | |
| 323 | + resource_source.string_length + | |
| 324 | + resource->data.gpio. | |
| 325 | + vendor_length); | |
| 326 | + | |
| 327 | + break; | |
| 328 | + | |
| 329 | + case ACPI_RESOURCE_TYPE_SERIAL_BUS: | |
| 330 | + | |
| 331 | + total_size = | |
| 332 | + acpi_gbl_aml_resource_serial_bus_sizes[resource-> | |
| 333 | + data. | |
| 334 | + common_serial_bus. | |
| 335 | + type]; | |
| 336 | + | |
| 337 | + total_size = (acpi_rs_length) (total_size + | |
| 338 | + resource->data. | |
| 339 | + i2c_serial_bus. | |
| 340 | + resource_source. | |
| 341 | + string_length + | |
| 342 | + resource->data. | |
| 343 | + i2c_serial_bus. | |
| 344 | + vendor_length); | |
| 345 | + | |
| 346 | + break; | |
| 347 | + | |
| 316 | 348 | default: |
| 317 | 349 | break; |
| 318 | 350 | } |
| @@ -362,10 +394,11 @@ acpi_rs_get_list_length(u8 * aml_buffer, · 43 unmodified lines | ||
| 362 | 394 | u32 extra_struct_bytes; |
| 363 | 395 | u8 resource_index; |
| 364 | 396 | u8 minimum_aml_resource_length; |
| 397 | + union aml_resource *aml_resource; | |
| 365 | 398 | |
| 366 | 399 | ACPI_FUNCTION_TRACE(rs_get_list_length); |
| 367 | 400 | |
| 368 | − *size_needed = 0; | |
| 401 | + *size_needed = ACPI_RS_SIZE_MIN; /* Minimum size is one end_tag */ | |
| 369 | 402 | end_aml = aml_buffer + aml_buffer_length; |
| 370 | 403 | |
| 371 | 404 | /* Walk the list of AML resource descriptors */ |
| @@ -376,9 +409,15 @@ acpi_rs_get_list_length(u8 * aml_buffer, · 4 unmodified lines | ||
| 376 | 409 | |
| 377 | 410 | status = acpi_ut_validate_resource(aml_buffer, &resource_index); |
| 378 | 411 | if (ACPI_FAILURE(status)) { |
| 412 | + /* | |
| 413 | + * Exit on failure. Cannot continue because the descriptor length | |
| 414 | + * may be bogus also. | |
| 415 | + */ | |
| 379 | 416 | return_ACPI_STATUS(status); |
| 380 | 417 | } |
| 381 | 418 | |
| 419 | + aml_resource = (void *)aml_buffer; | |
| 420 | + | |
| 382 | 421 | /* Get the resource length and base (minimum) AML size */ |
| 383 | 422 | |
| 384 | 423 | resource_length = acpi_ut_get_resource_length(aml_buffer); |
| @@ -422,10 +461,8 @@ acpi_rs_get_list_length(u8 * aml_buffer, · 37 unmodified lines | ||
| 422 | 461 | |
| 423 | 462 | case ACPI_RESOURCE_NAME_END_TAG: |
| 424 | 463 | /* |
| 425 | − * End Tag: | |
| 426 | − * This is the normal exit, add size of end_tag | |
| 464 | + * End Tag: This is the normal exit | |
| 427 | 465 | */ |
| 428 | − *size_needed += ACPI_RS_SIZE_MIN; | |
| 429 | 466 | return_ACPI_STATUS(AE_OK); |
| 430 | 467 | |
| 431 | 468 | case ACPI_RESOURCE_NAME_ADDRESS32: |
| @@ -457,6 +494,33 @@ acpi_rs_get_list_length(u8 * aml_buffer, · 25 unmodified lines | ||
| 457 | 494 | minimum_aml_resource_length); |
| 458 | 495 | break; |
| 459 | 496 | |
| 497 | + case ACPI_RESOURCE_NAME_GPIO: | |
| 498 | + | |
| 499 | + /* Vendor data is optional */ | |
| 500 | + | |
| 501 | + if (aml_resource->gpio.vendor_length) { | |
| 502 | + extra_struct_bytes += | |
| 503 | + aml_resource->gpio.vendor_offset - | |
| 504 | + aml_resource->gpio.pin_table_offset + | |
| 505 | + aml_resource->gpio.vendor_length; | |
| 506 | + } else { | |
| 507 | + extra_struct_bytes += | |
| 508 | + aml_resource->large_header.resource_length + | |
| 509 | + sizeof(struct aml_resource_large_header) - | |
| 510 | + aml_resource->gpio.pin_table_offset; | |
| 511 | + } | |
| 512 | + break; | |
| 513 | + | |
| 514 | + case ACPI_RESOURCE_NAME_SERIAL_BUS: | |
| 515 | + | |
| 516 | + minimum_aml_resource_length = | |
| 517 | + acpi_gbl_resource_aml_serial_bus_sizes | |
| 518 | + [aml_resource->common_serial_bus.type]; | |
| 519 | + extra_struct_bytes += | |
| 520 | + aml_resource->common_serial_bus.resource_length - | |
| 521 | + minimum_aml_resource_length; | |
| 522 | + break; | |
| 523 | + | |
| 460 | 524 | default: |
| 461 | 525 | break; |
| 462 | 526 | } |
| @@ -467,9 +531,18 @@ acpi_rs_get_list_length(u8 * aml_buffer, · 4 unmodified lines | ||
| 467 | 531 | * Important: Round the size up for the appropriate alignment. This |
| 468 | 532 | * is a requirement on IA64. |
| 469 | 533 | */ |
| 470 | − buffer_size = acpi_gbl_resource_struct_sizes[resource_index] + | |
| 471 | − extra_struct_bytes; | |
| 472 | − buffer_size = (u32) ACPI_ROUND_UP_TO_NATIVE_WORD(buffer_size); | |
| 534 | + if (acpi_ut_get_resource_type(aml_buffer) == | |
| 535 | + ACPI_RESOURCE_NAME_SERIAL_BUS) { | |
| 536 | + buffer_size = | |
| 537 | + acpi_gbl_resource_struct_serial_bus_sizes | |
| 538 | + [aml_resource->common_serial_bus.type] + | |
| 539 | + extra_struct_bytes; | |
| 540 | + } else { | |
| 541 | + buffer_size = | |
| 542 | + acpi_gbl_resource_struct_sizes[resource_index] + | |
| 543 | + extra_struct_bytes; | |
| 544 | + } | |
| 545 | + buffer_size = (u32)ACPI_ROUND_UP_TO_NATIVE_WORD(buffer_size); | |
| 473 | 546 | |
| 474 | 547 | *size_needed += buffer_size; |
| 475 | 548 | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -49,6 +49,70 @@ · 37 unmodified lines | ||
| 49 | 49 | #define _COMPONENT ACPI_RESOURCES |
| 50 | 50 | ACPI_MODULE_NAME("rscreate") |
| 51 | 51 | |
| 52 | +/******************************************************************************* | |
| 53 | + * | |
| 54 | + * FUNCTION: acpi_buffer_to_resource | |
| 55 | + * | |
| 56 | + * PARAMETERS: aml_buffer - Pointer to the resource byte stream | |
| 57 | + * aml_buffer_length - Length of the aml_buffer | |
| 58 | + * resource_ptr - Where the converted resource is returned | |
| 59 | + * | |
| 60 | + * RETURN: Status | |
| 61 | + * | |
| 62 | + * DESCRIPTION: Convert a raw AML buffer to a resource list | |
| 63 | + * | |
| 64 | + ******************************************************************************/ | |
| 65 | +acpi_status | |
| 66 | +acpi_buffer_to_resource(u8 *aml_buffer, | |
| 67 | + u16 aml_buffer_length, | |
| 68 | + struct acpi_resource **resource_ptr) | |
| 69 | +{ | |
| 70 | + acpi_status status; | |
| 71 | + acpi_size list_size_needed; | |
| 72 | + void *resource; | |
| 73 | + void *current_resource_ptr; | |
| 74 | + | |
| 75 | + /* | |
| 76 | + * Note: we allow AE_AML_NO_RESOURCE_END_TAG, since an end tag | |
| 77 | + * is not required here. | |
| 78 | + */ | |
| 79 | + | |
| 80 | + /* Get the required length for the converted resource */ | |
| 81 | + | |
| 82 | + status = acpi_rs_get_list_length(aml_buffer, aml_buffer_length, | |
| 83 | + &list_size_needed); | |
| 84 | + if (status == AE_AML_NO_RESOURCE_END_TAG) { | |
| 85 | + status = AE_OK; | |
| 86 | + } | |
| 87 | + if (ACPI_FAILURE(status)) { | |
| 88 | + return (status); | |
| 89 | + } | |
| 90 | + | |
| 91 | + /* Allocate a buffer for the converted resource */ | |
| 92 | + | |
| 93 | + resource = ACPI_ALLOCATE_ZEROED(list_size_needed); | |
| 94 | + current_resource_ptr = resource; | |
| 95 | + if (!resource) { | |
| 96 | + return (AE_NO_MEMORY); | |
| 97 | + } | |
| 98 | + | |
| 99 | + /* Perform the AML-to-Resource conversion */ | |
| 100 | + | |
| 101 | + status = acpi_ut_walk_aml_resources(aml_buffer, aml_buffer_length, | |
| 102 | + acpi_rs_convert_aml_to_resources, | |
| 103 | + ¤t_resource_ptr); | |
| 104 | + if (status == AE_AML_NO_RESOURCE_END_TAG) { | |
| 105 | + status = AE_OK; | |
| 106 | + } | |
| 107 | + if (ACPI_FAILURE(status)) { | |
| 108 | + ACPI_FREE(resource); | |
| 109 | + } else { | |
| 110 | + *resource_ptr = resource; | |
| 111 | + } | |
| 112 | + | |
| 113 | + return (status); | |
| 114 | +} | |
| 115 | + | |
| 52 | 116 | /******************************************************************************* |
| 53 | 117 | * |
| 54 | 118 | * FUNCTION: acpi_rs_create_resource_list |
| @@ -66,9 +130,10 @@ ACPI_MODULE_NAME("rscreate") · 11 unmodified lines | ||
| 66 | 130 | * of device resources. |
| 67 | 131 | * |
| 68 | 132 | ******************************************************************************/ |
| 133 | + | |
| 69 | 134 | acpi_status |
| 70 | 135 | acpi_rs_create_resource_list(union acpi_operand_object *aml_buffer, |
| 71 | − struct acpi_buffer *output_buffer) | |
| 136 | + struct acpi_buffer * output_buffer) | |
| 72 | 137 | { |
| 73 | 138 | |
| 74 | 139 | acpi_status status; |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -61,11 +61,13 @@ static void acpi_rs_out_integer64(char *title, u64 value); · 49 unmodified lines | ||
| 61 | 61 | |
| 62 | 62 | static void acpi_rs_out_title(char *title); |
| 63 | 63 | |
| 64 | −static void acpi_rs_dump_byte_list(u16 length, u8 * data); | |
| 64 | +static void acpi_rs_dump_byte_list(u16 length, u8 *data); | |
| 65 | 65 | |
| 66 | −static void acpi_rs_dump_dword_list(u8 length, u32 * data); | |
| 66 | +static void acpi_rs_dump_word_list(u16 length, u16 *data); | |
| 67 | 67 | |
| 68 | −static void acpi_rs_dump_short_byte_list(u8 length, u8 * data); | |
| 68 | +static void acpi_rs_dump_dword_list(u8 length, u32 *data); | |
| 69 | + | |
| 70 | +static void acpi_rs_dump_short_byte_list(u8 length, u8 *data); | |
| 69 | 71 | |
| 70 | 72 | static void |
| 71 | 73 | acpi_rs_dump_resource_source(struct acpi_resource_source *resource_source); |
| @@ -309,6 +311,125 @@ struct acpi_rsdump_info acpi_rs_dump_generic_reg[6] = { · 237 unmodified lines | ||
| 309 | 311 | {ACPI_RSD_UINT64, ACPI_RSD_OFFSET(generic_reg.address), "Address", NULL} |
| 310 | 312 | }; |
| 311 | 313 | |
| 314 | +struct acpi_rsdump_info acpi_rs_dump_gpio[16] = { | |
| 315 | + {ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_gpio), "GPIO", NULL}, | |
| 316 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(gpio.revision_id), "RevisionId", NULL}, | |
| 317 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(gpio.connection_type), | |
| 318 | + "ConnectionType", acpi_gbl_ct_decode}, | |
| 319 | + {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(gpio.producer_consumer), | |
| 320 | + "ProducerConsumer", acpi_gbl_consume_decode}, | |
| 321 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(gpio.pin_config), "PinConfig", | |
| 322 | + acpi_gbl_ppc_decode}, | |
| 323 | + {ACPI_RSD_2BITFLAG, ACPI_RSD_OFFSET(gpio.sharable), "Sharable", | |
| 324 | + acpi_gbl_shr_decode}, | |
| 325 | + {ACPI_RSD_2BITFLAG, ACPI_RSD_OFFSET(gpio.io_restriction), | |
| 326 | + "IoRestriction", acpi_gbl_ior_decode}, | |
| 327 | + {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(gpio.triggering), "Triggering", | |
| 328 | + acpi_gbl_he_decode}, | |
| 329 | + {ACPI_RSD_2BITFLAG, ACPI_RSD_OFFSET(gpio.polarity), "Polarity", | |
| 330 | + acpi_gbl_ll_decode}, | |
| 331 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(gpio.drive_strength), "DriveStrength", | |
| 332 | + NULL}, | |
| 333 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(gpio.debounce_timeout), | |
| 334 | + "DebounceTimeout", NULL}, | |
| 335 | + {ACPI_RSD_SOURCE, ACPI_RSD_OFFSET(gpio.resource_source), | |
| 336 | + "ResourceSource", NULL}, | |
| 337 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(gpio.pin_table_length), | |
| 338 | + "PinTableLength", NULL}, | |
| 339 | + {ACPI_RSD_WORDLIST, ACPI_RSD_OFFSET(gpio.pin_table), "PinTable", NULL}, | |
| 340 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(gpio.vendor_length), "VendorLength", | |
| 341 | + NULL}, | |
| 342 | + {ACPI_RSD_SHORTLISTX, ACPI_RSD_OFFSET(gpio.vendor_data), "VendorData", | |
| 343 | + NULL}, | |
| 344 | +}; | |
| 345 | + | |
| 346 | +struct acpi_rsdump_info acpi_rs_dump_fixed_dma[4] = { | |
| 347 | + {ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_fixed_dma), | |
| 348 | + "FixedDma", NULL}, | |
| 349 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(fixed_dma.request_lines), | |
| 350 | + "RequestLines", NULL}, | |
| 351 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(fixed_dma.channels), "Channels", | |
| 352 | + NULL}, | |
| 353 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(fixed_dma.width), "TransferWidth", | |
| 354 | + acpi_gbl_dts_decode}, | |
| 355 | +}; | |
| 356 | + | |
| 357 | +#define ACPI_RS_DUMP_COMMON_SERIAL_BUS \ | |
| 358 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET (common_serial_bus.revision_id), "RevisionId", NULL}, \ | |
| 359 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET (common_serial_bus.type), "Type", acpi_gbl_sbt_decode}, \ | |
| 360 | + {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET (common_serial_bus.producer_consumer), "ProducerConsumer", acpi_gbl_consume_decode}, \ | |
| 361 | + {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET (common_serial_bus.slave_mode), "SlaveMode", acpi_gbl_sm_decode}, \ | |
| 362 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET (common_serial_bus.type_revision_id), "TypeRevisionId", NULL}, \ | |
| 363 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET (common_serial_bus.type_data_length), "TypeDataLength", NULL}, \ | |
| 364 | + {ACPI_RSD_SOURCE, ACPI_RSD_OFFSET (common_serial_bus.resource_source), "ResourceSource", NULL}, \ | |
| 365 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET (common_serial_bus.vendor_length), "VendorLength", NULL}, \ | |
| 366 | + {ACPI_RSD_SHORTLISTX,ACPI_RSD_OFFSET (common_serial_bus.vendor_data), "VendorData", NULL}, | |
| 367 | + | |
| 368 | +struct acpi_rsdump_info acpi_rs_dump_common_serial_bus[10] = { | |
| 369 | + {ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_common_serial_bus), | |
| 370 | + "Common Serial Bus", NULL}, | |
| 371 | + ACPI_RS_DUMP_COMMON_SERIAL_BUS | |
| 372 | +}; | |
| 373 | + | |
| 374 | +struct acpi_rsdump_info acpi_rs_dump_i2c_serial_bus[13] = { | |
| 375 | + {ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_i2c_serial_bus), | |
| 376 | + "I2C Serial Bus", NULL}, | |
| 377 | + ACPI_RS_DUMP_COMMON_SERIAL_BUS {ACPI_RSD_1BITFLAG, | |
| 378 | + ACPI_RSD_OFFSET(i2c_serial_bus. | |
| 379 | + access_mode), | |
| 380 | + "AccessMode", acpi_gbl_am_decode}, | |
| 381 | + {ACPI_RSD_UINT32, ACPI_RSD_OFFSET(i2c_serial_bus.connection_speed), | |
| 382 | + "ConnectionSpeed", NULL}, | |
| 383 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(i2c_serial_bus.slave_address), | |
| 384 | + "SlaveAddress", NULL}, | |
| 385 | +}; | |
| 386 | + | |
| 387 | +struct acpi_rsdump_info acpi_rs_dump_spi_serial_bus[17] = { | |
| 388 | + {ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_spi_serial_bus), | |
| 389 | + "Spi Serial Bus", NULL}, | |
| 390 | + ACPI_RS_DUMP_COMMON_SERIAL_BUS {ACPI_RSD_1BITFLAG, | |
| 391 | + ACPI_RSD_OFFSET(spi_serial_bus. | |
| 392 | + wire_mode), "WireMode", | |
| 393 | + acpi_gbl_wm_decode}, | |
| 394 | + {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(spi_serial_bus.device_polarity), | |
| 395 | + "DevicePolarity", acpi_gbl_dp_decode}, | |
| 396 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(spi_serial_bus.data_bit_length), | |
| 397 | + "DataBitLength", NULL}, | |
| 398 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(spi_serial_bus.clock_phase), | |
| 399 | + "ClockPhase", acpi_gbl_cph_decode}, | |
| 400 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(spi_serial_bus.clock_polarity), | |
| 401 | + "ClockPolarity", acpi_gbl_cpo_decode}, | |
| 402 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(spi_serial_bus.device_selection), | |
| 403 | + "DeviceSelection", NULL}, | |
| 404 | + {ACPI_RSD_UINT32, ACPI_RSD_OFFSET(spi_serial_bus.connection_speed), | |
| 405 | + "ConnectionSpeed", NULL}, | |
| 406 | +}; | |
| 407 | + | |
| 408 | +struct acpi_rsdump_info acpi_rs_dump_uart_serial_bus[19] = { | |
| 409 | + {ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_uart_serial_bus), | |
| 410 | + "Uart Serial Bus", NULL}, | |
| 411 | + ACPI_RS_DUMP_COMMON_SERIAL_BUS {ACPI_RSD_2BITFLAG, | |
| 412 | + ACPI_RSD_OFFSET(uart_serial_bus. | |
| 413 | + flow_control), | |
| 414 | + "FlowControl", acpi_gbl_fc_decode}, | |
| 415 | + {ACPI_RSD_2BITFLAG, ACPI_RSD_OFFSET(uart_serial_bus.stop_bits), | |
| 416 | + "StopBits", acpi_gbl_sb_decode}, | |
| 417 | + {ACPI_RSD_3BITFLAG, ACPI_RSD_OFFSET(uart_serial_bus.data_bits), | |
| 418 | + "DataBits", acpi_gbl_bpb_decode}, | |
| 419 | + {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(uart_serial_bus.endian), "Endian", | |
| 420 | + acpi_gbl_ed_decode}, | |
| 421 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(uart_serial_bus.parity), "Parity", | |
| 422 | + acpi_gbl_pt_decode}, | |
| 423 | + {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(uart_serial_bus.lines_enabled), | |
| 424 | + "LinesEnabled", NULL}, | |
| 425 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(uart_serial_bus.rx_fifo_size), | |
| 426 | + "RxFifoSize", NULL}, | |
| 427 | + {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(uart_serial_bus.tx_fifo_size), | |
| 428 | + "TxFifoSize", NULL}, | |
| 429 | + {ACPI_RSD_UINT32, ACPI_RSD_OFFSET(uart_serial_bus.default_baud_rate), | |
| 430 | + "ConnectionSpeed", NULL}, | |
| 431 | +}; | |
| 432 | + | |
| 312 | 433 | /* |
| 313 | 434 | * Tables used for common address descriptor flag fields |
| 314 | 435 | */ |
| @@ -413,7 +534,14 @@ acpi_rs_dump_descriptor(void *resource, struct acpi_rsdump_info *table) · 98 unmodified lines | ||
| 413 | 534 | /* Data items, 8/16/32/64 bit */ |
| 414 | 535 | |
| 415 | 536 | case ACPI_RSD_UINT8: |
| 416 | − acpi_rs_out_integer8(name, ACPI_GET8(target)); | |
| 537 | + if (table->pointer) { | |
| 538 | + acpi_rs_out_string(name, ACPI_CAST_PTR(char, | |
| 539 | + table-> | |
| 540 | + pointer | |
| 541 | + [*target])); | |
| 542 | + } else { | |
| 543 | + acpi_rs_out_integer8(name, ACPI_GET8(target)); | |
| 544 | + } | |
| 417 | 545 | break; |
| 418 | 546 | |
| 419 | 547 | case ACPI_RSD_UINT16: |
| @@ -444,6 +572,13 @@ acpi_rs_dump_descriptor(void *resource, struct acpi_rsdump_info *table) · 24 unmodified lines | ||
| 444 | 572 | 0x03])); |
| 445 | 573 | break; |
| 446 | 574 | |
| 575 | + case ACPI_RSD_3BITFLAG: | |
| 576 | + acpi_rs_out_string(name, ACPI_CAST_PTR(char, | |
| 577 | + table-> | |
| 578 | + pointer[*target & | |
| 579 | + 0x07])); | |
| 580 | + break; | |
| 581 | + | |
| 447 | 582 | case ACPI_RSD_SHORTLIST: |
| 448 | 583 | /* |
| 449 | 584 | * Short byte list (single line output) for DMA and IRQ resources |
| @@ -456,6 +591,20 @@ acpi_rs_dump_descriptor(void *resource, struct acpi_rsdump_info *table) · 6 unmodified lines | ||
| 456 | 591 | } |
| 457 | 592 | break; |
| 458 | 593 | |
| 594 | + case ACPI_RSD_SHORTLISTX: | |
| 595 | + /* | |
| 596 | + * Short byte list (single line output) for GPIO vendor data | |
| 597 | + * Note: The list length is obtained from the previous table entry | |
| 598 | + */ | |
| 599 | + if (previous_target) { | |
| 600 | + acpi_rs_out_title(name); | |
| 601 | + acpi_rs_dump_short_byte_list(*previous_target, | |
| 602 | + * | |
| 603 | + (ACPI_CAST_INDIRECT_PTR | |
| 604 | + (u8, target))); | |
| 605 | + } | |
| 606 | + break; | |
| 607 | + | |
| 459 | 608 | case ACPI_RSD_LONGLIST: |
| 460 | 609 | /* |
| 461 | 610 | * Long byte list for Vendor resource data |
| @@ -480,6 +629,18 @@ acpi_rs_dump_descriptor(void *resource, struct acpi_rsdump_info *table) · 18 unmodified lines | ||
| 480 | 629 | } |
| 481 | 630 | break; |
| 482 | 631 | |
| 632 | + case ACPI_RSD_WORDLIST: | |
| 633 | + /* | |
| 634 | + * Word list for GPIO Pin Table | |
| 635 | + * Note: The list length is obtained from the previous table entry | |
| 636 | + */ | |
| 637 | + if (previous_target) { | |
| 638 | + acpi_rs_dump_word_list(*previous_target, | |
| 639 | + *(ACPI_CAST_INDIRECT_PTR | |
| 640 | + (u16, target))); | |
| 641 | + } | |
| 642 | + break; | |
| 643 | + | |
| 483 | 644 | case ACPI_RSD_ADDRESS: |
| 484 | 645 | /* |
| 485 | 646 | * Common flags for all Address resources |
| @@ -627,14 +788,20 @@ void acpi_rs_dump_resource_list(struct acpi_resource *resource_list) · 141 unmodified lines | ||
| 627 | 788 | |
| 628 | 789 | /* Dump the resource descriptor */ |
| 629 | 790 | |
| 630 | − acpi_rs_dump_descriptor(&resource_list->data, | |
| 631 | − acpi_gbl_dump_resource_dispatch[type]); | |
| 791 | + if (type == ACPI_RESOURCE_TYPE_SERIAL_BUS) { | |
| 792 | + acpi_rs_dump_descriptor(&resource_list->data, | |
| 793 | + acpi_gbl_dump_serial_bus_dispatch | |
| 794 | + [resource_list->data. | |
| 795 | + common_serial_bus.type]); | |
| 796 | + } else { | |
| 797 | + acpi_rs_dump_descriptor(&resource_list->data, | |
| 798 | + acpi_gbl_dump_resource_dispatch | |
| 799 | + [type]); | |
| 800 | + } | |
| 632 | 801 | |
| 633 | 802 | /* Point to the next resource structure */ |
| 634 | 803 | |
| 635 | − resource_list = | |
| 636 | − ACPI_ADD_PTR(struct acpi_resource, resource_list, | |
| 637 | − resource_list->length); | |
| 804 | + resource_list = ACPI_NEXT_RESOURCE(resource_list); | |
| 638 | 805 | |
| 639 | 806 | /* Exit when END_TAG descriptor is reached */ |
| 640 | 807 | |
| @@ -768,4 +935,13 @@ static void acpi_rs_dump_dword_list(u8 length, u32 * data) · 127 unmodified lines | ||
| 768 | 935 | } |
| 769 | 936 | } |
| 770 | 937 | |
| 938 | +static void acpi_rs_dump_word_list(u16 length, u16 *data) | |
| 939 | +{ | |
| 940 | + u16 i; | |
| 941 | + | |
| 942 | + for (i = 0; i < length; i++) { | |
| 943 | + acpi_os_printf("%25s%2.2X : %4.4X\n", "Word", i, data[i]); | |
| 944 | + } | |
| 945 | +} | |
| 946 | + | |
| 771 | 947 | #endif |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -76,7 +76,10 @@ struct acpi_rsconvert_info *acpi_gbl_set_resource_dispatch[] = { · 64 unmodified lines | ||
| 76 | 76 | acpi_rs_convert_address64, /* 0x0D, ACPI_RESOURCE_TYPE_ADDRESS64 */ |
| 77 | 77 | acpi_rs_convert_ext_address64, /* 0x0E, ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64 */ |
| 78 | 78 | acpi_rs_convert_ext_irq, /* 0x0F, ACPI_RESOURCE_TYPE_EXTENDED_IRQ */ |
| 79 | − acpi_rs_convert_generic_reg /* 0x10, ACPI_RESOURCE_TYPE_GENERIC_REGISTER */ | |
| 79 | + acpi_rs_convert_generic_reg, /* 0x10, ACPI_RESOURCE_TYPE_GENERIC_REGISTER */ | |
| 80 | + acpi_rs_convert_gpio, /* 0x11, ACPI_RESOURCE_TYPE_GPIO */ | |
| 81 | + acpi_rs_convert_fixed_dma, /* 0x12, ACPI_RESOURCE_TYPE_FIXED_DMA */ | |
| 82 | + NULL, /* 0x13, ACPI_RESOURCE_TYPE_SERIAL_BUS - Use subtype table below */ | |
| 80 | 83 | }; |
| 81 | 84 | |
| 82 | 85 | /* Dispatch tables for AML-to-resource (Get Resource) conversion functions */ |
| @@ -94,7 +97,7 @@ struct acpi_rsconvert_info *acpi_gbl_get_resource_dispatch[] = { · 11 unmodified lines | ||
| 94 | 97 | acpi_rs_convert_end_dpf, /* 0x07, ACPI_RESOURCE_NAME_END_DEPENDENT */ |
| 95 | 98 | acpi_rs_convert_io, /* 0x08, ACPI_RESOURCE_NAME_IO */ |
| 96 | 99 | acpi_rs_convert_fixed_io, /* 0x09, ACPI_RESOURCE_NAME_FIXED_IO */ |
| 97 | − NULL, /* 0x0A, Reserved */ | |
| 100 | + acpi_rs_convert_fixed_dma, /* 0x0A, ACPI_RESOURCE_NAME_FIXED_DMA */ | |
| 98 | 101 | NULL, /* 0x0B, Reserved */ |
| 99 | 102 | NULL, /* 0x0C, Reserved */ |
| 100 | 103 | NULL, /* 0x0D, Reserved */ |
| @@ -114,7 +117,19 @@ struct acpi_rsconvert_info *acpi_gbl_get_resource_dispatch[] = { · 13 unmodified lines | ||
| 114 | 117 | acpi_rs_convert_address16, /* 0x08, ACPI_RESOURCE_NAME_ADDRESS16 */ |
| 115 | 118 | acpi_rs_convert_ext_irq, /* 0x09, ACPI_RESOURCE_NAME_EXTENDED_IRQ */ |
| 116 | 119 | acpi_rs_convert_address64, /* 0x0A, ACPI_RESOURCE_NAME_ADDRESS64 */ |
| 117 | − acpi_rs_convert_ext_address64 /* 0x0B, ACPI_RESOURCE_NAME_EXTENDED_ADDRESS64 */ | |
| 120 | + acpi_rs_convert_ext_address64, /* 0x0B, ACPI_RESOURCE_NAME_EXTENDED_ADDRESS64 */ | |
| 121 | + acpi_rs_convert_gpio, /* 0x0C, ACPI_RESOURCE_NAME_GPIO */ | |
| 122 | + NULL, /* 0x0D, Reserved */ | |
| 123 | + NULL, /* 0x0E, ACPI_RESOURCE_NAME_SERIAL_BUS - Use subtype table below */ | |
| 124 | +}; | |
| 125 | + | |
| 126 | +/* Subtype table for serial_bus -- I2C, SPI, and UART */ | |
| 127 | + | |
| 128 | +struct acpi_rsconvert_info *acpi_gbl_convert_resource_serial_bus_dispatch[] = { | |
| 129 | + NULL, | |
| 130 | + acpi_rs_convert_i2c_serial_bus, | |
| 131 | + acpi_rs_convert_spi_serial_bus, | |
| 132 | + acpi_rs_convert_uart_serial_bus, | |
| 118 | 133 | }; |
| 119 | 134 | |
| 120 | 135 | #ifdef ACPI_FUTURE_USAGE |
| @@ -140,6 +155,16 @@ struct acpi_rsdump_info *acpi_gbl_dump_resource_dispatch[] = { · 19 unmodified lines | ||
| 140 | 155 | acpi_rs_dump_ext_address64, /* ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64 */ |
| 141 | 156 | acpi_rs_dump_ext_irq, /* ACPI_RESOURCE_TYPE_EXTENDED_IRQ */ |
| 142 | 157 | acpi_rs_dump_generic_reg, /* ACPI_RESOURCE_TYPE_GENERIC_REGISTER */ |
| 158 | + acpi_rs_dump_gpio, /* ACPI_RESOURCE_TYPE_GPIO */ | |
| 159 | + acpi_rs_dump_fixed_dma, /* ACPI_RESOURCE_TYPE_FIXED_DMA */ | |
| 160 | + NULL, /* ACPI_RESOURCE_TYPE_SERIAL_BUS */ | |
| 161 | +}; | |
| 162 | + | |
| 163 | +struct acpi_rsdump_info *acpi_gbl_dump_serial_bus_dispatch[] = { | |
| 164 | + NULL, | |
| 165 | + acpi_rs_dump_i2c_serial_bus, /* AML_RESOURCE_I2C_BUS_TYPE */ | |
| 166 | + acpi_rs_dump_spi_serial_bus, /* AML_RESOURCE_SPI_BUS_TYPE */ | |
| 167 | + acpi_rs_dump_uart_serial_bus, /* AML_RESOURCE_UART_BUS_TYPE */ | |
| 143 | 168 | }; |
| 144 | 169 | #endif |
| 145 | 170 | |
| @@ -166,7 +191,10 @@ const u8 acpi_gbl_aml_resource_sizes[] = { · 20 unmodified lines | ||
| 166 | 191 | sizeof(struct aml_resource_address64), /* ACPI_RESOURCE_TYPE_ADDRESS64 */ |
| 167 | 192 | sizeof(struct aml_resource_extended_address64), /*ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64 */ |
| 168 | 193 | sizeof(struct aml_resource_extended_irq), /* ACPI_RESOURCE_TYPE_EXTENDED_IRQ */ |
| 169 | − sizeof(struct aml_resource_generic_register) /* ACPI_RESOURCE_TYPE_GENERIC_REGISTER */ | |
| 194 | + sizeof(struct aml_resource_generic_register), /* ACPI_RESOURCE_TYPE_GENERIC_REGISTER */ | |
| 195 | + sizeof(struct aml_resource_gpio), /* ACPI_RESOURCE_TYPE_GPIO */ | |
| 196 | + sizeof(struct aml_resource_fixed_dma), /* ACPI_RESOURCE_TYPE_FIXED_DMA */ | |
| 197 | + sizeof(struct aml_resource_common_serialbus), /* ACPI_RESOURCE_TYPE_SERIAL_BUS */ | |
| 170 | 198 | }; |
| 171 | 199 | |
| 172 | 200 | const u8 acpi_gbl_resource_struct_sizes[] = { |
| @@ -182,7 +210,7 @@ const u8 acpi_gbl_resource_struct_sizes[] = { · 9 unmodified lines | ||
| 182 | 210 | ACPI_RS_SIZE_MIN, |
| 183 | 211 | ACPI_RS_SIZE(struct acpi_resource_io), |
| 184 | 212 | ACPI_RS_SIZE(struct acpi_resource_fixed_io), |
| 185 | − 0, | |
| 213 | + ACPI_RS_SIZE(struct acpi_resource_fixed_dma), | |
| 186 | 214 | 0, |
| 187 | 215 | 0, |
| 188 | 216 | 0, |
| @@ -202,5 +230,21 @@ const u8 acpi_gbl_resource_struct_sizes[] = { · 13 unmodified lines | ||
| 202 | 230 | ACPI_RS_SIZE(struct acpi_resource_address16), |
| 203 | 231 | ACPI_RS_SIZE(struct acpi_resource_extended_irq), |
| 204 | 232 | ACPI_RS_SIZE(struct acpi_resource_address64), |
| 205 | − ACPI_RS_SIZE(struct acpi_resource_extended_address64) | |
| 233 | + ACPI_RS_SIZE(struct acpi_resource_extended_address64), | |
| 234 | + ACPI_RS_SIZE(struct acpi_resource_gpio), | |
| 235 | + ACPI_RS_SIZE(struct acpi_resource_common_serialbus) | |
| 236 | +}; | |
| 237 | + | |
| 238 | +const u8 acpi_gbl_aml_resource_serial_bus_sizes[] = { | |
| 239 | + 0, | |
| 240 | + sizeof(struct aml_resource_i2c_serialbus), | |
| 241 | + sizeof(struct aml_resource_spi_serialbus), | |
| 242 | + sizeof(struct aml_resource_uart_serialbus), | |
| 243 | +}; | |
| 244 | + | |
| 245 | +const u8 acpi_gbl_resource_struct_serial_bus_sizes[] = { | |
| 246 | + 0, | |
| 247 | + ACPI_RS_SIZE(struct acpi_resource_i2c_serialbus), | |
| 248 | + ACPI_RS_SIZE(struct acpi_resource_spi_serialbus), | |
| 249 | + ACPI_RS_SIZE(struct acpi_resource_uart_serialbus), | |
| 206 | 250 | }; |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -264,3 +264,34 @@ struct acpi_rsconvert_info acpi_rs_convert_dma[6] = { · 252 unmodified lines | ||
| 264 | 264 | AML_OFFSET(dma.dma_channel_mask), |
| 265 | 265 | ACPI_RS_OFFSET(data.dma.channel_count)} |
| 266 | 266 | }; |
| 267 | + | |
| 268 | +/******************************************************************************* | |
| 269 | + * | |
| 270 | + * acpi_rs_convert_fixed_dma | |
| 271 | + * | |
| 272 | + ******************************************************************************/ | |
| 273 | + | |
| 274 | +struct acpi_rsconvert_info acpi_rs_convert_fixed_dma[4] = { | |
| 275 | + {ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_FIXED_DMA, | |
| 276 | + ACPI_RS_SIZE(struct acpi_resource_fixed_dma), | |
| 277 | + ACPI_RSC_TABLE_SIZE(acpi_rs_convert_fixed_dma)}, | |
| 278 | + | |
| 279 | + {ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_FIXED_DMA, | |
| 280 | + sizeof(struct aml_resource_fixed_dma), | |
| 281 | + 0}, | |
| 282 | + | |
| 283 | + /* | |
| 284 | + * These fields are contiguous in both the source and destination: | |
| 285 | + * request_lines | |
| 286 | + * Channels | |
| 287 | + */ | |
| 288 | + | |
| 289 | + {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.fixed_dma.request_lines), | |
| 290 | + AML_OFFSET(fixed_dma.request_lines), | |
| 291 | + 2}, | |
| 292 | + | |
| 293 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.fixed_dma.width), | |
| 294 | + AML_OFFSET(fixed_dma.width), | |
| 295 | + 1}, | |
| 296 | + | |
| 297 | +}; | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -70,6 +70,8 @@ acpi_rs_convert_aml_to_resources(u8 * aml, · 58 unmodified lines | ||
| 70 | 70 | struct acpi_resource **resource_ptr = |
| 71 | 71 | ACPI_CAST_INDIRECT_PTR(struct acpi_resource, context); |
| 72 | 72 | struct acpi_resource *resource; |
| 73 | + union aml_resource *aml_resource; | |
| 74 | + struct acpi_rsconvert_info *conversion_table; | |
| 73 | 75 | acpi_status status; |
| 74 | 76 | |
| 75 | 77 | ACPI_FUNCTION_TRACE(rs_convert_aml_to_resources); |
| @@ -84,14 +86,37 @@ acpi_rs_convert_aml_to_resources(u8 * aml, · 8 unmodified lines | ||
| 84 | 86 | "Misaligned resource pointer %p", resource)); |
| 85 | 87 | } |
| 86 | 88 | |
| 89 | + /* Get the appropriate conversion info table */ | |
| 90 | + | |
| 91 | + aml_resource = ACPI_CAST_PTR(union aml_resource, aml); | |
| 92 | + if (acpi_ut_get_resource_type(aml) == ACPI_RESOURCE_NAME_SERIAL_BUS) { | |
| 93 | + if (aml_resource->common_serial_bus.type > | |
| 94 | + AML_RESOURCE_MAX_SERIALBUSTYPE) { | |
| 95 | + conversion_table = NULL; | |
| 96 | + } else { | |
| 97 | + /* This is an I2C, SPI, or UART serial_bus descriptor */ | |
| 98 | + | |
| 99 | + conversion_table = | |
| 100 | + acpi_gbl_convert_resource_serial_bus_dispatch | |
| 101 | + [aml_resource->common_serial_bus.type]; | |
| 102 | + } | |
| 103 | + } else { | |
| 104 | + conversion_table = | |
| 105 | + acpi_gbl_get_resource_dispatch[resource_index]; | |
| 106 | + } | |
| 107 | + | |
| 108 | + if (!conversion_table) { | |
| 109 | + ACPI_ERROR((AE_INFO, | |
| 110 | + "Invalid/unsupported resource descriptor: Type 0x%2.2X", | |
| 111 | + resource_index)); | |
| 112 | + return (AE_AML_INVALID_RESOURCE_TYPE); | |
| 113 | + } | |
| 114 | + | |
| 87 | 115 | /* Convert the AML byte stream resource to a local resource struct */ |
| 88 | 116 | |
| 89 | 117 | status = |
| 90 | − acpi_rs_convert_aml_to_resource(resource, | |
| 91 | − ACPI_CAST_PTR(union aml_resource, | |
| 92 | − aml), | |
| 93 | − acpi_gbl_get_resource_dispatch | |
| 94 | − [resource_index]); | |
| 118 | + acpi_rs_convert_aml_to_resource(resource, aml_resource, | |
| 119 | + conversion_table); | |
| 95 | 120 | if (ACPI_FAILURE(status)) { |
| 96 | 121 | ACPI_EXCEPTION((AE_INFO, status, |
| 97 | 122 | "Could not convert AML resource (Type 0x%X)", |
| @@ -106,7 +131,7 @@ acpi_rs_convert_aml_to_resources(u8 * aml, · 8 unmodified lines | ||
| 106 | 131 | |
| 107 | 132 | /* Point to the next structure in the output buffer */ |
| 108 | 133 | |
| 109 | − *resource_ptr = ACPI_ADD_PTR(void, resource, resource->length); | |
| 134 | + *resource_ptr = ACPI_NEXT_RESOURCE(resource); | |
| 110 | 135 | return_ACPI_STATUS(AE_OK); |
| 111 | 136 | } |
| 112 | 137 | |
| @@ -135,6 +160,7 @@ acpi_rs_convert_resources_to_aml(struct acpi_resource *resource, · 22 unmodified lines | ||
| 135 | 160 | { |
| 136 | 161 | u8 *aml = output_buffer; |
| 137 | 162 | u8 *end_aml = output_buffer + aml_size_needed; |
| 163 | + struct acpi_rsconvert_info *conversion_table; | |
| 138 | 164 | acpi_status status; |
| 139 | 165 | |
| 140 | 166 | ACPI_FUNCTION_TRACE(rs_convert_resources_to_aml); |
| @@ -154,11 +180,34 @@ acpi_rs_convert_resources_to_aml(struct acpi_resource *resource, · 13 unmodified lines | ||
| 154 | 180 | |
| 155 | 181 | /* Perform the conversion */ |
| 156 | 182 | |
| 157 | − status = acpi_rs_convert_resource_to_aml(resource, ACPI_CAST_PTR(union | |
| 158 | − aml_resource, | |
| 159 | − aml), | |
| 160 | − acpi_gbl_set_resource_dispatch | |
| 161 | − [resource->type]); | |
| 183 | + if (resource->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) { | |
| 184 | + if (resource->data.common_serial_bus.type > | |
| 185 | + AML_RESOURCE_MAX_SERIALBUSTYPE) { | |
| 186 | + conversion_table = NULL; | |
| 187 | + } else { | |
| 188 | + /* This is an I2C, SPI, or UART serial_bus descriptor */ | |
| 189 | + | |
| 190 | + conversion_table = | |
| 191 | + acpi_gbl_convert_resource_serial_bus_dispatch | |
| 192 | + [resource->data.common_serial_bus.type]; | |
| 193 | + } | |
| 194 | + } else { | |
| 195 | + conversion_table = | |
| 196 | + acpi_gbl_set_resource_dispatch[resource->type]; | |
| 197 | + } | |
| 198 | + | |
| 199 | + if (!conversion_table) { | |
| 200 | + ACPI_ERROR((AE_INFO, | |
| 201 | + "Invalid/unsupported resource descriptor: Type 0x%2.2X", | |
| 202 | + resource->type)); | |
| 203 | + return (AE_AML_INVALID_RESOURCE_TYPE); | |
| 204 | + } | |
| 205 | + | |
| 206 | + status = acpi_rs_convert_resource_to_aml(resource, | |
| 207 | + ACPI_CAST_PTR(union | |
| 208 | + aml_resource, | |
| 209 | + aml), | |
| 210 | + conversion_table); | |
| 162 | 211 | if (ACPI_FAILURE(status)) { |
| 163 | 212 | ACPI_EXCEPTION((AE_INFO, status, |
| 164 | 213 | "Could not convert resource (type 0x%X) to AML", |
| @@ -192,9 +241,7 @@ acpi_rs_convert_resources_to_aml(struct acpi_resource *resource, · 27 unmodified lines | ||
| 192 | 241 | |
| 193 | 242 | /* Point to the next input resource descriptor */ |
| 194 | 243 | |
| 195 | − resource = | |
| 196 | − ACPI_ADD_PTR(struct acpi_resource, resource, | |
| 197 | − resource->length); | |
| 244 | + resource = ACPI_NEXT_RESOURCE(resource); | |
| 198 | 245 | } |
| 199 | 246 | |
| 200 | 247 | /* Completed buffer, but did not find an end_tag resource descriptor */ |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -83,6 +83,10 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource, · 71 unmodified lines | ||
| 83 | 83 | |
| 84 | 84 | ACPI_FUNCTION_TRACE(rs_convert_aml_to_resource); |
| 85 | 85 | |
| 86 | + if (!info) { | |
| 87 | + return_ACPI_STATUS(AE_BAD_PARAMETER); | |
| 88 | + } | |
| 89 | + | |
| 86 | 90 | if (((acpi_size) resource) & 0x3) { |
| 87 | 91 | |
| 88 | 92 | /* Each internal resource struct is expected to be 32-bit aligned */ |
| @@ -101,7 +105,6 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource, · 12 unmodified lines | ||
| 101 | 105 | * table length (# of table entries) |
| 102 | 106 | */ |
| 103 | 107 | count = INIT_TABLE_LENGTH(info); |
| 104 | − | |
| 105 | 108 | while (count) { |
| 106 | 109 | /* |
| 107 | 110 | * Source is the external AML byte stream buffer, |
| @@ -145,6 +148,14 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource, · 37 unmodified lines | ||
| 145 | 148 | ((ACPI_GET8(source) >> info->value) & 0x03); |
| 146 | 149 | break; |
| 147 | 150 | |
| 151 | + case ACPI_RSC_3BITFLAG: | |
| 152 | + /* | |
| 153 | + * Mask and shift the flag bits | |
| 154 | + */ | |
| 155 | + ACPI_SET8(destination) = (u8) | |
| 156 | + ((ACPI_GET8(source) >> info->value) & 0x07); | |
| 157 | + break; | |
| 158 | + | |
| 148 | 159 | case ACPI_RSC_COUNT: |
| 149 | 160 | |
| 150 | 161 | item_count = ACPI_GET8(source); |
| @@ -163,6 +174,69 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource, · 12 unmodified lines | ||
| 163 | 174 | (info->value * (item_count - 1)); |
| 164 | 175 | break; |
| 165 | 176 | |
| 177 | + case ACPI_RSC_COUNT_GPIO_PIN: | |
| 178 | + | |
| 179 | + target = ACPI_ADD_PTR(void, aml, info->value); | |
| 180 | + item_count = ACPI_GET16(target) - ACPI_GET16(source); | |
| 181 | + | |
| 182 | + resource->length = resource->length + item_count; | |
| 183 | + item_count = item_count / 2; | |
| 184 | + ACPI_SET16(destination) = item_count; | |
| 185 | + break; | |
| 186 | + | |
| 187 | + case ACPI_RSC_COUNT_GPIO_VEN: | |
| 188 | + | |
| 189 | + item_count = ACPI_GET8(source); | |
| 190 | + ACPI_SET8(destination) = (u8)item_count; | |
| 191 | + | |
| 192 | + resource->length = resource->length + | |
| 193 | + (info->value * item_count); | |
| 194 | + break; | |
| 195 | + | |
| 196 | + case ACPI_RSC_COUNT_GPIO_RES: | |
| 197 | + | |
| 198 | + /* | |
| 199 | + * Vendor data is optional (length/offset may both be zero) | |
| 200 | + * Examine vendor data length field first | |
| 201 | + */ | |
| 202 | + target = ACPI_ADD_PTR(void, aml, (info->value + 2)); | |
| 203 | + if (ACPI_GET16(target)) { | |
| 204 | + | |
| 205 | + /* Use vendor offset to get resource source length */ | |
| 206 | + | |
| 207 | + target = ACPI_ADD_PTR(void, aml, info->value); | |
| 208 | + item_count = | |
| 209 | + ACPI_GET16(target) - ACPI_GET16(source); | |
| 210 | + } else { | |
| 211 | + /* No vendor data to worry about */ | |
| 212 | + | |
| 213 | + item_count = aml->large_header.resource_length + | |
| 214 | + sizeof(struct aml_resource_large_header) - | |
| 215 | + ACPI_GET16(source); | |
| 216 | + } | |
| 217 | + | |
| 218 | + resource->length = resource->length + item_count; | |
| 219 | + ACPI_SET16(destination) = item_count; | |
| 220 | + break; | |
| 221 | + | |
| 222 | + case ACPI_RSC_COUNT_SERIAL_VEN: | |
| 223 | + | |
| 224 | + item_count = ACPI_GET16(source) - info->value; | |
| 225 | + | |
| 226 | + resource->length = resource->length + item_count; | |
| 227 | + ACPI_SET16(destination) = item_count; | |
| 228 | + break; | |
| 229 | + | |
| 230 | + case ACPI_RSC_COUNT_SERIAL_RES: | |
| 231 | + | |
| 232 | + item_count = (aml_resource_length + | |
| 233 | + sizeof(struct aml_resource_large_header)) | |
| 234 | + - ACPI_GET16(source) - info->value; | |
| 235 | + | |
| 236 | + resource->length = resource->length + item_count; | |
| 237 | + ACPI_SET16(destination) = item_count; | |
| 238 | + break; | |
| 239 | + | |
| 166 | 240 | case ACPI_RSC_LENGTH: |
| 167 | 241 | |
| 168 | 242 | resource->length = resource->length + info->value; |
| @@ -183,6 +257,72 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource, · 14 unmodified lines | ||
| 183 | 257 | info->opcode); |
| 184 | 258 | break; |
| 185 | 259 | |
| 260 | + case ACPI_RSC_MOVE_GPIO_PIN: | |
| 261 | + | |
| 262 | + /* Generate and set the PIN data pointer */ | |
| 263 | + | |
| 264 | + target = (char *)ACPI_ADD_PTR(void, resource, | |
| 265 | + (resource->length - | |
| 266 | + item_count * 2)); | |
| 267 | + *(u16 **)destination = ACPI_CAST_PTR(u16, target); | |
| 268 | + | |
| 269 | + /* Copy the PIN data */ | |
| 270 | + | |
| 271 | + source = ACPI_ADD_PTR(void, aml, ACPI_GET16(source)); | |
| 272 | + acpi_rs_move_data(target, source, item_count, | |
| 273 | + info->opcode); | |
| 274 | + break; | |
| 275 | + | |
| 276 | + case ACPI_RSC_MOVE_GPIO_RES: | |
| 277 | + | |
| 278 | + /* Generate and set the resource_source string pointer */ | |
| 279 | + | |
| 280 | + target = (char *)ACPI_ADD_PTR(void, resource, | |
| 281 | + (resource->length - | |
| 282 | + item_count)); | |
| 283 | + *(u8 **)destination = ACPI_CAST_PTR(u8, target); | |
| 284 | + | |
| 285 | + /* Copy the resource_source string */ | |
| 286 | + | |
| 287 | + source = ACPI_ADD_PTR(void, aml, ACPI_GET16(source)); | |
| 288 | + acpi_rs_move_data(target, source, item_count, | |
| 289 | + info->opcode); | |
| 290 | + break; | |
| 291 | + | |
| 292 | + case ACPI_RSC_MOVE_SERIAL_VEN: | |
| 293 | + | |
| 294 | + /* Generate and set the Vendor Data pointer */ | |
| 295 | + | |
| 296 | + target = (char *)ACPI_ADD_PTR(void, resource, | |
| 297 | + (resource->length - | |
| 298 | + item_count)); | |
| 299 | + *(u8 **)destination = ACPI_CAST_PTR(u8, target); | |
| 300 | + | |
| 301 | + /* Copy the Vendor Data */ | |
| 302 | + | |
| 303 | + source = ACPI_ADD_PTR(void, aml, info->value); | |
| 304 | + acpi_rs_move_data(target, source, item_count, | |
| 305 | + info->opcode); | |
| 306 | + break; | |
| 307 | + | |
| 308 | + case ACPI_RSC_MOVE_SERIAL_RES: | |
| 309 | + | |
| 310 | + /* Generate and set the resource_source string pointer */ | |
| 311 | + | |
| 312 | + target = (char *)ACPI_ADD_PTR(void, resource, | |
| 313 | + (resource->length - | |
| 314 | + item_count)); | |
| 315 | + *(u8 **)destination = ACPI_CAST_PTR(u8, target); | |
| 316 | + | |
| 317 | + /* Copy the resource_source string */ | |
| 318 | + | |
| 319 | + source = | |
| 320 | + ACPI_ADD_PTR(void, aml, | |
| 321 | + (ACPI_GET16(source) + info->value)); | |
| 322 | + acpi_rs_move_data(target, source, item_count, | |
| 323 | + info->opcode); | |
| 324 | + break; | |
| 325 | + | |
| 186 | 326 | case ACPI_RSC_SET8: |
| 187 | 327 | |
| 188 | 328 | ACPI_MEMSET(destination, info->aml_offset, info->value); |
| @@ -219,13 +359,18 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource, · 30 unmodified lines | ||
| 219 | 359 | * Optional resource_source (Index and String). This is the more |
| 220 | 360 | * complicated case used by the Interrupt() macro |
| 221 | 361 | */ |
| 222 | − target = | |
| 223 | − ACPI_ADD_PTR(char, resource, | |
| 224 | − info->aml_offset + (item_count * 4)); | |
| 362 | + target = ACPI_ADD_PTR(char, resource, | |
| 363 | + info->aml_offset + | |
| 364 | + (item_count * 4)); | |
| 225 | 365 | |
| 226 | 366 | resource->length += |
| 227 | 367 | acpi_rs_get_resource_source(aml_resource_length, |
| 228 | − (acpi_rs_length) (((item_count - 1) * sizeof(u32)) + info->value), destination, aml, target); | |
| 368 | + (acpi_rs_length) | |
| 369 | + (((item_count - | |
| 370 | + 1) * sizeof(u32)) + | |
| 371 | + info->value), | |
| 372 | + destination, aml, | |
| 373 | + target); | |
| 229 | 374 | break; |
| 230 | 375 | |
| 231 | 376 | case ACPI_RSC_BITMASK: |
| @@ -327,6 +472,7 @@ acpi_rs_convert_resource_to_aml(struct acpi_resource *resource, · 95 unmodified lines | ||
| 327 | 472 | { |
| 328 | 473 | void *source = NULL; |
| 329 | 474 | void *destination; |
| 475 | + char *target; | |
| 330 | 476 | acpi_rsdesc_size aml_length = 0; |
| 331 | 477 | u8 count; |
| 332 | 478 | u16 temp16 = 0; |
| @@ -334,6 +480,10 @@ acpi_rs_convert_resource_to_aml(struct acpi_resource *resource, · 1 unmodified line | ||
| 334 | 480 | |
| 335 | 481 | ACPI_FUNCTION_TRACE(rs_convert_resource_to_aml); |
| 336 | 482 | |
| 483 | + if (!info) { | |
| 484 | + return_ACPI_STATUS(AE_BAD_PARAMETER); | |
| 485 | + } | |
| 486 | + | |
| 337 | 487 | /* |
| 338 | 488 | * First table entry must be ACPI_RSC_INITxxx and must contain the |
| 339 | 489 | * table length (# of table entries) |
| @@ -383,6 +533,14 @@ acpi_rs_convert_resource_to_aml(struct acpi_resource *resource, · 43 unmodified lines | ||
| 383 | 533 | ((ACPI_GET8(source) & 0x03) << info->value); |
| 384 | 534 | break; |
| 385 | 535 | |
| 536 | + case ACPI_RSC_3BITFLAG: | |
| 537 | + /* | |
| 538 | + * Mask and shift the flag bits | |
| 539 | + */ | |
| 540 | + ACPI_SET8(destination) |= (u8) | |
| 541 | + ((ACPI_GET8(source) & 0x07) << info->value); | |
| 542 | + break; | |
| 543 | + | |
| 386 | 544 | case ACPI_RSC_COUNT: |
| 387 | 545 | |
| 388 | 546 | item_count = ACPI_GET8(source); |
| @@ -400,6 +558,63 @@ acpi_rs_convert_resource_to_aml(struct acpi_resource *resource, · 11 unmodified lines | ||
| 400 | 558 | acpi_rs_set_resource_length(aml_length, aml); |
| 401 | 559 | break; |
| 402 | 560 | |
| 561 | + case ACPI_RSC_COUNT_GPIO_PIN: | |
| 562 | + | |
| 563 | + item_count = ACPI_GET16(source); | |
| 564 | + ACPI_SET16(destination) = (u16)aml_length; | |
| 565 | + | |
| 566 | + aml_length = (u16)(aml_length + item_count * 2); | |
| 567 | + target = ACPI_ADD_PTR(void, aml, info->value); | |
| 568 | + ACPI_SET16(target) = (u16)aml_length; | |
| 569 | + acpi_rs_set_resource_length(aml_length, aml); | |
| 570 | + break; | |
| 571 | + | |
| 572 | + case ACPI_RSC_COUNT_GPIO_VEN: | |
| 573 | + | |
| 574 | + item_count = ACPI_GET16(source); | |
| 575 | + ACPI_SET16(destination) = (u16)item_count; | |
| 576 | + | |
| 577 | + aml_length = | |
| 578 | + (u16)(aml_length + (info->value * item_count)); | |
| 579 | + acpi_rs_set_resource_length(aml_length, aml); | |
| 580 | + break; | |
| 581 | + | |
| 582 | + case ACPI_RSC_COUNT_GPIO_RES: | |
| 583 | + | |
| 584 | + /* Set resource source string length */ | |
| 585 | + | |
| 586 | + item_count = ACPI_GET16(source); | |
| 587 | + ACPI_SET16(destination) = (u16)aml_length; | |
| 588 | + | |
| 589 | + /* Compute offset for the Vendor Data */ | |
| 590 | + | |
| 591 | + aml_length = (u16)(aml_length + item_count); | |
| 592 | + target = ACPI_ADD_PTR(void, aml, info->value); | |
| 593 | + | |
| 594 | + /* Set vendor offset only if there is vendor data */ | |
| 595 | + | |
| 596 | + if (resource->data.gpio.vendor_length) { | |
| 597 | + ACPI_SET16(target) = (u16)aml_length; | |
| 598 | + } | |
| 599 | + | |
| 600 | + acpi_rs_set_resource_length(aml_length, aml); | |
| 601 | + break; | |
| 602 | + | |
| 603 | + case ACPI_RSC_COUNT_SERIAL_VEN: | |
| 604 | + | |
| 605 | + item_count = ACPI_GET16(source); | |
| 606 | + ACPI_SET16(destination) = item_count + info->value; | |
| 607 | + aml_length = (u16)(aml_length + item_count); | |
| 608 | + acpi_rs_set_resource_length(aml_length, aml); | |
| 609 | + break; | |
| 610 | + | |
| 611 | + case ACPI_RSC_COUNT_SERIAL_RES: | |
| 612 | + | |
| 613 | + item_count = ACPI_GET16(source); | |
| 614 | + aml_length = (u16)(aml_length + item_count); | |
| 615 | + acpi_rs_set_resource_length(aml_length, aml); | |
| 616 | + break; | |
| 617 | + | |
| 403 | 618 | case ACPI_RSC_LENGTH: |
| 404 | 619 | |
| 405 | 620 | acpi_rs_set_resource_length(info->value, aml); |
| @@ -417,6 +632,48 @@ acpi_rs_convert_resource_to_aml(struct acpi_resource *resource, · 11 unmodified lines | ||
| 417 | 632 | info->opcode); |
| 418 | 633 | break; |
| 419 | 634 | |
| 635 | + case ACPI_RSC_MOVE_GPIO_PIN: | |
| 636 | + | |
| 637 | + destination = (char *)ACPI_ADD_PTR(void, aml, | |
| 638 | + ACPI_GET16 | |
| 639 | + (destination)); | |
| 640 | + source = *(u16 **)source; | |
| 641 | + acpi_rs_move_data(destination, source, item_count, | |
| 642 | + info->opcode); | |
| 643 | + break; | |
| 644 | + | |
| 645 | + case ACPI_RSC_MOVE_GPIO_RES: | |
| 646 | + | |
| 647 | + /* Used for both resource_source string and vendor_data */ | |
| 648 | + | |
| 649 | + destination = (char *)ACPI_ADD_PTR(void, aml, | |
| 650 | + ACPI_GET16 | |
| 651 | + (destination)); | |
| 652 | + source = *(u8 **)source; | |
| 653 | + acpi_rs_move_data(destination, source, item_count, | |
| 654 | + info->opcode); | |
| 655 | + break; | |
| 656 | + | |
| 657 | + case ACPI_RSC_MOVE_SERIAL_VEN: | |
| 658 | + | |
| 659 | + destination = (char *)ACPI_ADD_PTR(void, aml, | |
| 660 | + (aml_length - | |
| 661 | + item_count)); | |
| 662 | + source = *(u8 **)source; | |
| 663 | + acpi_rs_move_data(destination, source, item_count, | |
| 664 | + info->opcode); | |
| 665 | + break; | |
| 666 | + | |
| 667 | + case ACPI_RSC_MOVE_SERIAL_RES: | |
| 668 | + | |
| 669 | + destination = (char *)ACPI_ADD_PTR(void, aml, | |
| 670 | + (aml_length - | |
| 671 | + item_count)); | |
| 672 | + source = *(u8 **)source; | |
| 673 | + acpi_rs_move_data(destination, source, item_count, | |
| 674 | + info->opcode); | |
| 675 | + break; | |
| 676 | + | |
| 420 | 677 | case ACPI_RSC_ADDRESS: |
| 421 | 678 | |
| 422 | 679 | /* Set the Resource Type, General Flags, and Type-Specific Flags */ |
| @@ -0,0 +1,441 @@ | ||
| 1 | +/******************************************************************************* | |
| 2 | + * | |
| 3 | + * Module Name: rsserial - GPIO/serial_bus resource descriptors | |
| 4 | + * | |
| 5 | + ******************************************************************************/ | |
| 6 | + | |
| 7 | +/* | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | + * All rights reserved. | |
| 10 | + * | |
| 11 | + * Redistribution and use in source and binary forms, with or without | |
| 12 | + * modification, are permitted provided that the following conditions | |
| 13 | + * are met: | |
| 14 | + * 1. Redistributions of source code must retain the above copyright | |
| 15 | + * notice, this list of conditions, and the following disclaimer, | |
| 16 | + * without modification. | |
| 17 | + * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
| 18 | + * substantially similar to the "NO WARRANTY" disclaimer below | |
| 19 | + * ("Disclaimer") and any redistribution must be conditioned upon | |
| 20 | + * including a substantially similar Disclaimer requirement for further | |
| 21 | + * binary redistribution. | |
| 22 | + * 3. Neither the names of the above-listed copyright holders nor the names | |
| 23 | + * of any contributors may be used to endorse or promote products derived | |
| 24 | + * from this software without specific prior written permission. | |
| 25 | + * | |
| 26 | + * Alternatively, this software may be distributed under the terms of the | |
| 27 | + * GNU General Public License ("GPL") version 2 as published by the Free | |
| 28 | + * Software Foundation. | |
| 29 | + * | |
| 30 | + * NO WARRANTY | |
| 31 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 32 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 33 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR | |
| 34 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 35 | + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 36 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
| 37 | + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 38 | + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
| 39 | + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | |
| 40 | + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
| 41 | + * POSSIBILITY OF SUCH DAMAGES. | |
| 42 | + */ | |
| 43 | + | |
| 44 | +#include <acpi/acpi.h> | |
| 45 | +#include "accommon.h" | |
| 46 | +#include "acresrc.h" | |
| 47 | + | |
| 48 | +#define _COMPONENT ACPI_RESOURCES | |
| 49 | +ACPI_MODULE_NAME("rsserial") | |
| 50 | + | |
| 51 | +/******************************************************************************* | |
| 52 | + * | |
| 53 | + * acpi_rs_convert_gpio | |
| 54 | + * | |
| 55 | + ******************************************************************************/ | |
| 56 | +struct acpi_rsconvert_info acpi_rs_convert_gpio[17] = { | |
| 57 | + {ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_GPIO, | |
| 58 | + ACPI_RS_SIZE(struct acpi_resource_gpio), | |
| 59 | + ACPI_RSC_TABLE_SIZE(acpi_rs_convert_gpio)}, | |
| 60 | + | |
| 61 | + {ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_GPIO, | |
| 62 | + sizeof(struct aml_resource_gpio), | |
| 63 | + 0}, | |
| 64 | + | |
| 65 | + /* | |
| 66 | + * These fields are contiguous in both the source and destination: | |
| 67 | + * revision_id | |
| 68 | + * connection_type | |
| 69 | + */ | |
| 70 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.gpio.revision_id), | |
| 71 | + AML_OFFSET(gpio.revision_id), | |
| 72 | + 2}, | |
| 73 | + | |
| 74 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.gpio.producer_consumer), | |
| 75 | + AML_OFFSET(gpio.flags), | |
| 76 | + 0}, | |
| 77 | + | |
| 78 | + {ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.gpio.sharable), | |
| 79 | + AML_OFFSET(gpio.int_flags), | |
| 80 | + 3}, | |
| 81 | + | |
| 82 | + {ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.gpio.io_restriction), | |
| 83 | + AML_OFFSET(gpio.int_flags), | |
| 84 | + 0}, | |
| 85 | + | |
| 86 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.gpio.triggering), | |
| 87 | + AML_OFFSET(gpio.int_flags), | |
| 88 | + 0}, | |
| 89 | + | |
| 90 | + {ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.gpio.polarity), | |
| 91 | + AML_OFFSET(gpio.int_flags), | |
| 92 | + 1}, | |
| 93 | + | |
| 94 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.gpio.pin_config), | |
| 95 | + AML_OFFSET(gpio.pin_config), | |
| 96 | + 1}, | |
| 97 | + | |
| 98 | + /* | |
| 99 | + * These fields are contiguous in both the source and destination: | |
| 100 | + * drive_strength | |
| 101 | + * debounce_timeout | |
| 102 | + */ | |
| 103 | + {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.gpio.drive_strength), | |
| 104 | + AML_OFFSET(gpio.drive_strength), | |
| 105 | + 2}, | |
| 106 | + | |
| 107 | + /* Pin Table */ | |
| 108 | + | |
| 109 | + {ACPI_RSC_COUNT_GPIO_PIN, ACPI_RS_OFFSET(data.gpio.pin_table_length), | |
| 110 | + AML_OFFSET(gpio.pin_table_offset), | |
| 111 | + AML_OFFSET(gpio.res_source_offset)}, | |
| 112 | + | |
| 113 | + {ACPI_RSC_MOVE_GPIO_PIN, ACPI_RS_OFFSET(data.gpio.pin_table), | |
| 114 | + AML_OFFSET(gpio.pin_table_offset), | |
| 115 | + 0}, | |
| 116 | + | |
| 117 | + /* Resource Source */ | |
| 118 | + | |
| 119 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.gpio.resource_source.index), | |
| 120 | + AML_OFFSET(gpio.res_source_index), | |
| 121 | + 1}, | |
| 122 | + | |
| 123 | + {ACPI_RSC_COUNT_GPIO_RES, | |
| 124 | + ACPI_RS_OFFSET(data.gpio.resource_source.string_length), | |
| 125 | + AML_OFFSET(gpio.res_source_offset), | |
| 126 | + AML_OFFSET(gpio.vendor_offset)}, | |
| 127 | + | |
| 128 | + {ACPI_RSC_MOVE_GPIO_RES, | |
| 129 | + ACPI_RS_OFFSET(data.gpio.resource_source.string_ptr), | |
| 130 | + AML_OFFSET(gpio.res_source_offset), | |
| 131 | + 0}, | |
| 132 | + | |
| 133 | + /* Vendor Data */ | |
| 134 | + | |
| 135 | + {ACPI_RSC_COUNT_GPIO_VEN, ACPI_RS_OFFSET(data.gpio.vendor_length), | |
| 136 | + AML_OFFSET(gpio.vendor_length), | |
| 137 | + 1}, | |
| 138 | + | |
| 139 | + {ACPI_RSC_MOVE_GPIO_RES, ACPI_RS_OFFSET(data.gpio.vendor_data), | |
| 140 | + AML_OFFSET(gpio.vendor_offset), | |
| 141 | + 0}, | |
| 142 | +}; | |
| 143 | + | |
| 144 | +/******************************************************************************* | |
| 145 | + * | |
| 146 | + * acpi_rs_convert_i2c_serial_bus | |
| 147 | + * | |
| 148 | + ******************************************************************************/ | |
| 149 | + | |
| 150 | +struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_bus[16] = { | |
| 151 | + {ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_SERIAL_BUS, | |
| 152 | + ACPI_RS_SIZE(struct acpi_resource_i2c_serialbus), | |
| 153 | + ACPI_RSC_TABLE_SIZE(acpi_rs_convert_i2c_serial_bus)}, | |
| 154 | + | |
| 155 | + {ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_SERIAL_BUS, | |
| 156 | + sizeof(struct aml_resource_i2c_serialbus), | |
| 157 | + 0}, | |
| 158 | + | |
| 159 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.common_serial_bus.revision_id), | |
| 160 | + AML_OFFSET(common_serial_bus.revision_id), | |
| 161 | + 1}, | |
| 162 | + | |
| 163 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.common_serial_bus.type), | |
| 164 | + AML_OFFSET(common_serial_bus.type), | |
| 165 | + 1}, | |
| 166 | + | |
| 167 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.common_serial_bus.slave_mode), | |
| 168 | + AML_OFFSET(common_serial_bus.flags), | |
| 169 | + 0}, | |
| 170 | + | |
| 171 | + {ACPI_RSC_1BITFLAG, | |
| 172 | + ACPI_RS_OFFSET(data.common_serial_bus.producer_consumer), | |
| 173 | + AML_OFFSET(common_serial_bus.flags), | |
| 174 | + 1}, | |
| 175 | + | |
| 176 | + {ACPI_RSC_MOVE8, | |
| 177 | + ACPI_RS_OFFSET(data.common_serial_bus.type_revision_id), | |
| 178 | + AML_OFFSET(common_serial_bus.type_revision_id), | |
| 179 | + 1}, | |
| 180 | + | |
| 181 | + {ACPI_RSC_MOVE16, | |
| 182 | + ACPI_RS_OFFSET(data.common_serial_bus.type_data_length), | |
| 183 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 184 | + 1}, | |
| 185 | + | |
| 186 | + /* Vendor data */ | |
| 187 | + | |
| 188 | + {ACPI_RSC_COUNT_SERIAL_VEN, | |
| 189 | + ACPI_RS_OFFSET(data.common_serial_bus.vendor_length), | |
| 190 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 191 | + AML_RESOURCE_I2C_MIN_DATA_LEN}, | |
| 192 | + | |
| 193 | + {ACPI_RSC_MOVE_SERIAL_VEN, | |
| 194 | + ACPI_RS_OFFSET(data.common_serial_bus.vendor_data), | |
| 195 | + 0, | |
| 196 | + sizeof(struct aml_resource_i2c_serialbus)}, | |
| 197 | + | |
| 198 | + /* Resource Source */ | |
| 199 | + | |
| 200 | + {ACPI_RSC_MOVE8, | |
| 201 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.index), | |
| 202 | + AML_OFFSET(common_serial_bus.res_source_index), | |
| 203 | + 1}, | |
| 204 | + | |
| 205 | + {ACPI_RSC_COUNT_SERIAL_RES, | |
| 206 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.string_length), | |
| 207 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 208 | + sizeof(struct aml_resource_common_serialbus)}, | |
| 209 | + | |
| 210 | + {ACPI_RSC_MOVE_SERIAL_RES, | |
| 211 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.string_ptr), | |
| 212 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 213 | + sizeof(struct aml_resource_common_serialbus)}, | |
| 214 | + | |
| 215 | + /* I2C bus type specific */ | |
| 216 | + | |
| 217 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.i2c_serial_bus.access_mode), | |
| 218 | + AML_OFFSET(i2c_serial_bus.type_specific_flags), | |
| 219 | + 0}, | |
| 220 | + | |
| 221 | + {ACPI_RSC_MOVE32, ACPI_RS_OFFSET(data.i2c_serial_bus.connection_speed), | |
| 222 | + AML_OFFSET(i2c_serial_bus.connection_speed), | |
| 223 | + 1}, | |
| 224 | + | |
| 225 | + {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.i2c_serial_bus.slave_address), | |
| 226 | + AML_OFFSET(i2c_serial_bus.slave_address), | |
| 227 | + 1}, | |
| 228 | +}; | |
| 229 | + | |
| 230 | +/******************************************************************************* | |
| 231 | + * | |
| 232 | + * acpi_rs_convert_spi_serial_bus | |
| 233 | + * | |
| 234 | + ******************************************************************************/ | |
| 235 | + | |
| 236 | +struct acpi_rsconvert_info acpi_rs_convert_spi_serial_bus[20] = { | |
| 237 | + {ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_SERIAL_BUS, | |
| 238 | + ACPI_RS_SIZE(struct acpi_resource_spi_serialbus), | |
| 239 | + ACPI_RSC_TABLE_SIZE(acpi_rs_convert_spi_serial_bus)}, | |
| 240 | + | |
| 241 | + {ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_SERIAL_BUS, | |
| 242 | + sizeof(struct aml_resource_spi_serialbus), | |
| 243 | + 0}, | |
| 244 | + | |
| 245 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.common_serial_bus.revision_id), | |
| 246 | + AML_OFFSET(common_serial_bus.revision_id), | |
| 247 | + 1}, | |
| 248 | + | |
| 249 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.common_serial_bus.type), | |
| 250 | + AML_OFFSET(common_serial_bus.type), | |
| 251 | + 1}, | |
| 252 | + | |
| 253 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.common_serial_bus.slave_mode), | |
| 254 | + AML_OFFSET(common_serial_bus.flags), | |
| 255 | + 0}, | |
| 256 | + | |
| 257 | + {ACPI_RSC_1BITFLAG, | |
| 258 | + ACPI_RS_OFFSET(data.common_serial_bus.producer_consumer), | |
| 259 | + AML_OFFSET(common_serial_bus.flags), | |
| 260 | + 1}, | |
| 261 | + | |
| 262 | + {ACPI_RSC_MOVE8, | |
| 263 | + ACPI_RS_OFFSET(data.common_serial_bus.type_revision_id), | |
| 264 | + AML_OFFSET(common_serial_bus.type_revision_id), | |
| 265 | + 1}, | |
| 266 | + | |
| 267 | + {ACPI_RSC_MOVE16, | |
| 268 | + ACPI_RS_OFFSET(data.common_serial_bus.type_data_length), | |
| 269 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 270 | + 1}, | |
| 271 | + | |
| 272 | + /* Vendor data */ | |
| 273 | + | |
| 274 | + {ACPI_RSC_COUNT_SERIAL_VEN, | |
| 275 | + ACPI_RS_OFFSET(data.common_serial_bus.vendor_length), | |
| 276 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 277 | + AML_RESOURCE_SPI_MIN_DATA_LEN}, | |
| 278 | + | |
| 279 | + {ACPI_RSC_MOVE_SERIAL_VEN, | |
| 280 | + ACPI_RS_OFFSET(data.common_serial_bus.vendor_data), | |
| 281 | + 0, | |
| 282 | + sizeof(struct aml_resource_spi_serialbus)}, | |
| 283 | + | |
| 284 | + /* Resource Source */ | |
| 285 | + | |
| 286 | + {ACPI_RSC_MOVE8, | |
| 287 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.index), | |
| 288 | + AML_OFFSET(common_serial_bus.res_source_index), | |
| 289 | + 1}, | |
| 290 | + | |
| 291 | + {ACPI_RSC_COUNT_SERIAL_RES, | |
| 292 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.string_length), | |
| 293 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 294 | + sizeof(struct aml_resource_common_serialbus)}, | |
| 295 | + | |
| 296 | + {ACPI_RSC_MOVE_SERIAL_RES, | |
| 297 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.string_ptr), | |
| 298 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 299 | + sizeof(struct aml_resource_common_serialbus)}, | |
| 300 | + | |
| 301 | + /* Spi bus type specific */ | |
| 302 | + | |
| 303 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.spi_serial_bus.wire_mode), | |
| 304 | + AML_OFFSET(spi_serial_bus.type_specific_flags), | |
| 305 | + 0}, | |
| 306 | + | |
| 307 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.spi_serial_bus.device_polarity), | |
| 308 | + AML_OFFSET(spi_serial_bus.type_specific_flags), | |
| 309 | + 1}, | |
| 310 | + | |
| 311 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.spi_serial_bus.data_bit_length), | |
| 312 | + AML_OFFSET(spi_serial_bus.data_bit_length), | |
| 313 | + 1}, | |
| 314 | + | |
| 315 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.spi_serial_bus.clock_phase), | |
| 316 | + AML_OFFSET(spi_serial_bus.clock_phase), | |
| 317 | + 1}, | |
| 318 | + | |
| 319 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.spi_serial_bus.clock_polarity), | |
| 320 | + AML_OFFSET(spi_serial_bus.clock_polarity), | |
| 321 | + 1}, | |
| 322 | + | |
| 323 | + {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.spi_serial_bus.device_selection), | |
| 324 | + AML_OFFSET(spi_serial_bus.device_selection), | |
| 325 | + 1}, | |
| 326 | + | |
| 327 | + {ACPI_RSC_MOVE32, ACPI_RS_OFFSET(data.spi_serial_bus.connection_speed), | |
| 328 | + AML_OFFSET(spi_serial_bus.connection_speed), | |
| 329 | + 1}, | |
| 330 | +}; | |
| 331 | + | |
| 332 | +/******************************************************************************* | |
| 333 | + * | |
| 334 | + * acpi_rs_convert_uart_serial_bus | |
| 335 | + * | |
| 336 | + ******************************************************************************/ | |
| 337 | + | |
| 338 | +struct acpi_rsconvert_info acpi_rs_convert_uart_serial_bus[22] = { | |
| 339 | + {ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_SERIAL_BUS, | |
| 340 | + ACPI_RS_SIZE(struct acpi_resource_uart_serialbus), | |
| 341 | + ACPI_RSC_TABLE_SIZE(acpi_rs_convert_uart_serial_bus)}, | |
| 342 | + | |
| 343 | + {ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_SERIAL_BUS, | |
| 344 | + sizeof(struct aml_resource_uart_serialbus), | |
| 345 | + 0}, | |
| 346 | + | |
| 347 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.common_serial_bus.revision_id), | |
| 348 | + AML_OFFSET(common_serial_bus.revision_id), | |
| 349 | + 1}, | |
| 350 | + | |
| 351 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.common_serial_bus.type), | |
| 352 | + AML_OFFSET(common_serial_bus.type), | |
| 353 | + 1}, | |
| 354 | + | |
| 355 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.common_serial_bus.slave_mode), | |
| 356 | + AML_OFFSET(common_serial_bus.flags), | |
| 357 | + 0}, | |
| 358 | + | |
| 359 | + {ACPI_RSC_1BITFLAG, | |
| 360 | + ACPI_RS_OFFSET(data.common_serial_bus.producer_consumer), | |
| 361 | + AML_OFFSET(common_serial_bus.flags), | |
| 362 | + 1}, | |
| 363 | + | |
| 364 | + {ACPI_RSC_MOVE8, | |
| 365 | + ACPI_RS_OFFSET(data.common_serial_bus.type_revision_id), | |
| 366 | + AML_OFFSET(common_serial_bus.type_revision_id), | |
| 367 | + 1}, | |
| 368 | + | |
| 369 | + {ACPI_RSC_MOVE16, | |
| 370 | + ACPI_RS_OFFSET(data.common_serial_bus.type_data_length), | |
| 371 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 372 | + 1}, | |
| 373 | + | |
| 374 | + /* Vendor data */ | |
| 375 | + | |
| 376 | + {ACPI_RSC_COUNT_SERIAL_VEN, | |
| 377 | + ACPI_RS_OFFSET(data.common_serial_bus.vendor_length), | |
| 378 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 379 | + AML_RESOURCE_UART_MIN_DATA_LEN}, | |
| 380 | + | |
| 381 | + {ACPI_RSC_MOVE_SERIAL_VEN, | |
| 382 | + ACPI_RS_OFFSET(data.common_serial_bus.vendor_data), | |
| 383 | + 0, | |
| 384 | + sizeof(struct aml_resource_uart_serialbus)}, | |
| 385 | + | |
| 386 | + /* Resource Source */ | |
| 387 | + | |
| 388 | + {ACPI_RSC_MOVE8, | |
| 389 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.index), | |
| 390 | + AML_OFFSET(common_serial_bus.res_source_index), | |
| 391 | + 1}, | |
| 392 | + | |
| 393 | + {ACPI_RSC_COUNT_SERIAL_RES, | |
| 394 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.string_length), | |
| 395 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 396 | + sizeof(struct aml_resource_common_serialbus)}, | |
| 397 | + | |
| 398 | + {ACPI_RSC_MOVE_SERIAL_RES, | |
| 399 | + ACPI_RS_OFFSET(data.common_serial_bus.resource_source.string_ptr), | |
| 400 | + AML_OFFSET(common_serial_bus.type_data_length), | |
| 401 | + sizeof(struct aml_resource_common_serialbus)}, | |
| 402 | + | |
| 403 | + /* Uart bus type specific */ | |
| 404 | + | |
| 405 | + {ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.uart_serial_bus.flow_control), | |
| 406 | + AML_OFFSET(uart_serial_bus.type_specific_flags), | |
| 407 | + 0}, | |
| 408 | + | |
| 409 | + {ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.uart_serial_bus.stop_bits), | |
| 410 | + AML_OFFSET(uart_serial_bus.type_specific_flags), | |
| 411 | + 2}, | |
| 412 | + | |
| 413 | + {ACPI_RSC_3BITFLAG, ACPI_RS_OFFSET(data.uart_serial_bus.data_bits), | |
| 414 | + AML_OFFSET(uart_serial_bus.type_specific_flags), | |
| 415 | + 4}, | |
| 416 | + | |
| 417 | + {ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.uart_serial_bus.endian), | |
| 418 | + AML_OFFSET(uart_serial_bus.type_specific_flags), | |
| 419 | + 7}, | |
| 420 | + | |
| 421 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.uart_serial_bus.parity), | |
| 422 | + AML_OFFSET(uart_serial_bus.parity), | |
| 423 | + 1}, | |
| 424 | + | |
| 425 | + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.uart_serial_bus.lines_enabled), | |
| 426 | + AML_OFFSET(uart_serial_bus.lines_enabled), | |
| 427 | + 1}, | |
| 428 | + | |
| 429 | + {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.uart_serial_bus.rx_fifo_size), | |
| 430 | + AML_OFFSET(uart_serial_bus.rx_fifo_size), | |
| 431 | + 1}, | |
| 432 | + | |
| 433 | + {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.uart_serial_bus.tx_fifo_size), | |
| 434 | + AML_OFFSET(uart_serial_bus.tx_fifo_size), | |
| 435 | + 1}, | |
| 436 | + | |
| 437 | + {ACPI_RSC_MOVE32, | |
| 438 | + ACPI_RS_OFFSET(data.uart_serial_bus.default_baud_rate), | |
| 439 | + AML_OFFSET(uart_serial_bus.default_baud_rate), | |
| 440 | + 1}, | |
| 441 | +}; | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -144,6 +144,9 @@ acpi_rs_move_data(void *destination, void *source, u16 item_count, u8 move_type) · 132 unmodified lines | ||
| 144 | 144 | * since there are no alignment or endian issues |
| 145 | 145 | */ |
| 146 | 146 | case ACPI_RSC_MOVE8: |
| 147 | + case ACPI_RSC_MOVE_GPIO_RES: | |
| 148 | + case ACPI_RSC_MOVE_SERIAL_VEN: | |
| 149 | + case ACPI_RSC_MOVE_SERIAL_RES: | |
| 147 | 150 | ACPI_MEMCPY(destination, source, item_count); |
| 148 | 151 | return; |
| 149 | 152 | |
| @@ -153,6 +156,7 @@ acpi_rs_move_data(void *destination, void *source, u16 item_count, u8 move_type) · 3 unmodified lines | ||
| 153 | 156 | * misaligned memory transfers |
| 154 | 157 | */ |
| 155 | 158 | case ACPI_RSC_MOVE16: |
| 159 | + case ACPI_RSC_MOVE_GPIO_PIN: | |
| 156 | 160 | ACPI_MOVE_16_TO_16(&ACPI_CAST_PTR(u16, destination)[i], |
| 157 | 161 | &ACPI_CAST_PTR(u16, source)[i]); |
| 158 | 162 | break; |
| @@ -588,6 +592,56 @@ acpi_rs_get_prs_method_data(struct acpi_namespace_node *node, · 429 unmodified lines | ||
| 588 | 592 | } |
| 589 | 593 | #endif /* ACPI_FUTURE_USAGE */ |
| 590 | 594 | |
| 595 | +/******************************************************************************* | |
| 596 | + * | |
| 597 | + * FUNCTION: acpi_rs_get_aei_method_data | |
| 598 | + * | |
| 599 | + * PARAMETERS: Node - Device node | |
| 600 | + * ret_buffer - Pointer to a buffer structure for the | |
| 601 | + * results | |
| 602 | + * | |
| 603 | + * RETURN: Status | |
| 604 | + * | |
| 605 | + * DESCRIPTION: This function is called to get the _AEI value of an object | |
| 606 | + * contained in an object specified by the handle passed in | |
| 607 | + * | |
| 608 | + * If the function fails an appropriate status will be returned | |
| 609 | + * and the contents of the callers buffer is undefined. | |
| 610 | + * | |
| 611 | + ******************************************************************************/ | |
| 612 | + | |
| 613 | +acpi_status | |
| 614 | +acpi_rs_get_aei_method_data(struct acpi_namespace_node *node, | |
| 615 | + struct acpi_buffer *ret_buffer) | |
| 616 | +{ | |
| 617 | + union acpi_operand_object *obj_desc; | |
| 618 | + acpi_status status; | |
| 619 | + | |
| 620 | + ACPI_FUNCTION_TRACE(rs_get_aei_method_data); | |
| 621 | + | |
| 622 | + /* Parameters guaranteed valid by caller */ | |
| 623 | + | |
| 624 | + /* Execute the method, no parameters */ | |
| 625 | + | |
| 626 | + status = acpi_ut_evaluate_object(node, METHOD_NAME__AEI, | |
| 627 | + ACPI_BTYPE_BUFFER, &obj_desc); | |
| 628 | + if (ACPI_FAILURE(status)) { | |
| 629 | + return_ACPI_STATUS(status); | |
| 630 | + } | |
| 631 | + | |
| 632 | + /* | |
| 633 | + * Make the call to create a resource linked list from the | |
| 634 | + * byte stream buffer that comes back from the _CRS method | |
| 635 | + * execution. | |
| 636 | + */ | |
| 637 | + status = acpi_rs_create_resource_list(obj_desc, ret_buffer); | |
| 638 | + | |
| 639 | + /* On exit, we must delete the object returned by evaluate_object */ | |
| 640 | + | |
| 641 | + acpi_ut_remove_reference(obj_desc); | |
| 642 | + return_ACPI_STATUS(status); | |
| 643 | +} | |
| 644 | + | |
| 591 | 645 | /******************************************************************************* |
| 592 | 646 | * |
| 593 | 647 | * FUNCTION: acpi_rs_get_method_data |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -307,6 +307,46 @@ acpi_set_current_resources(acpi_handle device_handle, · 295 unmodified lines | ||
| 307 | 307 | |
| 308 | 308 | ACPI_EXPORT_SYMBOL(acpi_set_current_resources) |
| 309 | 309 | |
| 310 | +/******************************************************************************* | |
| 311 | + * | |
| 312 | + * FUNCTION: acpi_get_event_resources | |
| 313 | + * | |
| 314 | + * PARAMETERS: device_handle - Handle to the device object for the | |
| 315 | + * device we are getting resources | |
| 316 | + * in_buffer - Pointer to a buffer containing the | |
| 317 | + * resources to be set for the device | |
| 318 | + * | |
| 319 | + * RETURN: Status | |
| 320 | + * | |
| 321 | + * DESCRIPTION: This function is called to get the event resources for a | |
| 322 | + * specific device. The caller must first acquire a handle for | |
| 323 | + * the desired device. The resource data is passed to the routine | |
| 324 | + * the buffer pointed to by the in_buffer variable. Uses the | |
| 325 | + * _AEI method. | |
| 326 | + * | |
| 327 | + ******************************************************************************/ | |
| 328 | +acpi_status | |
| 329 | +acpi_get_event_resources(acpi_handle device_handle, | |
| 330 | + struct acpi_buffer *ret_buffer) | |
| 331 | +{ | |
| 332 | + acpi_status status; | |
| 333 | + struct acpi_namespace_node *node; | |
| 334 | + | |
| 335 | + ACPI_FUNCTION_TRACE(acpi_get_event_resources); | |
| 336 | + | |
| 337 | + /* Validate parameters then dispatch to internal routine */ | |
| 338 | + | |
| 339 | + status = acpi_rs_validate_parameters(device_handle, ret_buffer, &node); | |
| 340 | + if (ACPI_FAILURE(status)) { | |
| 341 | + return_ACPI_STATUS(status); | |
| 342 | + } | |
| 343 | + | |
| 344 | + status = acpi_rs_get_aei_method_data(node, ret_buffer); | |
| 345 | + return_ACPI_STATUS(status); | |
| 346 | +} | |
| 347 | + | |
| 348 | +ACPI_EXPORT_SYMBOL(acpi_get_event_resources) | |
| 349 | + | |
| 310 | 350 | /****************************************************************************** |
| 311 | 351 | * |
| 312 | 352 | * FUNCTION: acpi_resource_to_address64 |
| @@ -486,8 +526,9 @@ acpi_rs_match_vendor_resource(struct acpi_resource *resource, void *context) · 173 unmodified lines | ||
| 486 | 526 | * |
| 487 | 527 | * PARAMETERS: device_handle - Handle to the device object for the |
| 488 | 528 | * device we are querying |
| 489 | − * Name - Method name of the resources we want | |
| 490 | − * (METHOD_NAME__CRS or METHOD_NAME__PRS) | |
| 529 | + * Name - Method name of the resources we want. | |
| 530 | + * (METHOD_NAME__CRS, METHOD_NAME__PRS, or | |
| 531 | + * METHOD_NAME__AEI) | |
| 491 | 532 | * user_function - Called for each resource |
| 492 | 533 | * Context - Passed to user_function |
| 493 | 534 | * |
| @@ -514,11 +555,12 @@ acpi_walk_resources(acpi_handle device_handle, · 20 unmodified lines | ||
| 514 | 555 | |
| 515 | 556 | if (!device_handle || !user_function || !name || |
| 516 | 557 | (!ACPI_COMPARE_NAME(name, METHOD_NAME__CRS) && |
| 517 | − !ACPI_COMPARE_NAME(name, METHOD_NAME__PRS))) { | |
| 558 | + !ACPI_COMPARE_NAME(name, METHOD_NAME__PRS) && | |
| 559 | + !ACPI_COMPARE_NAME(name, METHOD_NAME__AEI))) { | |
| 518 | 560 | return_ACPI_STATUS(AE_BAD_PARAMETER); |
| 519 | 561 | } |
| 520 | 562 | |
| 521 | − /* Get the _CRS or _PRS resource list */ | |
| 563 | + /* Get the _CRS/_PRS/_AEI resource list */ | |
| 522 | 564 | |
| 523 | 565 | buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER; |
| 524 | 566 | status = acpi_rs_get_method_data(device_handle, name, &buffer); |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -63,14 +63,15 @@ static void acpi_tb_setup_fadt_registers(void); · 51 unmodified lines | ||
| 63 | 63 | |
| 64 | 64 | typedef struct acpi_fadt_info { |
| 65 | 65 | char *name; |
| 66 | − u8 address64; | |
| 67 | − u8 address32; | |
| 68 | − u8 length; | |
| 66 | + u16 address64; | |
| 67 | + u16 address32; | |
| 68 | + u16 length; | |
| 69 | 69 | u8 default_length; |
| 70 | 70 | u8 type; |
| 71 | 71 | |
| 72 | 72 | } acpi_fadt_info; |
| 73 | 73 | |
| 74 | +#define ACPI_FADT_OPTIONAL 0 | |
| 74 | 75 | #define ACPI_FADT_REQUIRED 1 |
| 75 | 76 | #define ACPI_FADT_SEPARATE_LENGTH 2 |
| 76 | 77 | |
| @@ -87,7 +88,7 @@ static struct acpi_fadt_info fadt_info_table[] = { · 10 unmodified lines | ||
| 87 | 88 | ACPI_FADT_OFFSET(pm1b_event_block), |
| 88 | 89 | ACPI_FADT_OFFSET(pm1_event_length), |
| 89 | 90 | ACPI_PM1_REGISTER_WIDTH * 2, /* Enable + Status register */ |
| 90 | − 0}, | |
| 91 | + ACPI_FADT_OPTIONAL}, | |
| 91 | 92 | |
| 92 | 93 | {"Pm1aControlBlock", |
| 93 | 94 | ACPI_FADT_OFFSET(xpm1a_control_block), |
| @@ -101,7 +102,7 @@ static struct acpi_fadt_info fadt_info_table[] = { · 7 unmodified lines | ||
| 101 | 102 | ACPI_FADT_OFFSET(pm1b_control_block), |
| 102 | 103 | ACPI_FADT_OFFSET(pm1_control_length), |
| 103 | 104 | ACPI_PM1_REGISTER_WIDTH, |
| 104 | − 0}, | |
| 105 | + ACPI_FADT_OPTIONAL}, | |
| 105 | 106 | |
| 106 | 107 | {"Pm2ControlBlock", |
| 107 | 108 | ACPI_FADT_OFFSET(xpm2_control_block), |
| @@ -139,7 +140,7 @@ static struct acpi_fadt_info fadt_info_table[] = { · 31 unmodified lines | ||
| 139 | 140 | |
| 140 | 141 | typedef struct acpi_fadt_pm_info { |
| 141 | 142 | struct acpi_generic_address *target; |
| 142 | − u8 source; | |
| 143 | + u16 source; | |
| 143 | 144 | u8 register_num; |
| 144 | 145 | |
| 145 | 146 | } acpi_fadt_pm_info; |
| @@ -253,8 +254,13 @@ void acpi_tb_parse_fadt(u32 table_index) · 107 unmodified lines | ||
| 253 | 254 | acpi_tb_install_table((acpi_physical_address) acpi_gbl_FADT.Xdsdt, |
| 254 | 255 | ACPI_SIG_DSDT, ACPI_TABLE_INDEX_DSDT); |
| 255 | 256 | |
| 256 | − acpi_tb_install_table((acpi_physical_address) acpi_gbl_FADT.Xfacs, | |
| 257 | − ACPI_SIG_FACS, ACPI_TABLE_INDEX_FACS); | |
| 257 | + /* If Hardware Reduced flag is set, there is no FACS */ | |
| 258 | + | |
| 259 | + if (!acpi_gbl_reduced_hardware) { | |
| 260 | + acpi_tb_install_table((acpi_physical_address) acpi_gbl_FADT. | |
| 261 | + Xfacs, ACPI_SIG_FACS, | |
| 262 | + ACPI_TABLE_INDEX_FACS); | |
| 263 | + } | |
| 258 | 264 | } |
| 259 | 265 | |
| 260 | 266 | /******************************************************************************* |
| @@ -277,12 +283,12 @@ void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length) · 16 unmodified lines | ||
| 277 | 283 | { |
| 278 | 284 | /* |
| 279 | 285 | * Check if the FADT is larger than the largest table that we expect |
| 280 | − * (the ACPI 2.0/3.0 version). If so, truncate the table, and issue | |
| 286 | + * (the ACPI 5.0 version). If so, truncate the table, and issue | |
| 281 | 287 | * a warning. |
| 282 | 288 | */ |
| 283 | 289 | if (length > sizeof(struct acpi_table_fadt)) { |
| 284 | 290 | ACPI_WARNING((AE_INFO, |
| 285 | − "FADT (revision %u) is longer than ACPI 2.0 version, " | |
| 291 | + "FADT (revision %u) is longer than ACPI 5.0 version, " | |
| 286 | 292 | "truncating length %u to %u", |
| 287 | 293 | table->revision, length, |
| 288 | 294 | (u32)sizeof(struct acpi_table_fadt))); |
| @@ -297,6 +303,13 @@ void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length) · 8 unmodified lines | ||
| 297 | 303 | ACPI_MEMCPY(&acpi_gbl_FADT, table, |
| 298 | 304 | ACPI_MIN(length, sizeof(struct acpi_table_fadt))); |
| 299 | 305 | |
| 306 | + /* Take a copy of the Hardware Reduced flag */ | |
| 307 | + | |
| 308 | + acpi_gbl_reduced_hardware = FALSE; | |
| 309 | + if (acpi_gbl_FADT.flags & ACPI_FADT_HW_REDUCED) { | |
| 310 | + acpi_gbl_reduced_hardware = TRUE; | |
| 311 | + } | |
| 312 | + | |
| 300 | 313 | /* Convert the local copy of the FADT to the common internal format */ |
| 301 | 314 | |
| 302 | 315 | acpi_tb_convert_fadt(); |
| @@ -502,6 +515,12 @@ static void acpi_tb_validate_fadt(void) · 199 unmodified lines | ||
| 502 | 515 | acpi_gbl_FADT.Xdsdt = (u64) acpi_gbl_FADT.dsdt; |
| 503 | 516 | } |
| 504 | 517 | |
| 518 | + /* If Hardware Reduced flag is set, we are all done */ | |
| 519 | + | |
| 520 | + if (acpi_gbl_reduced_hardware) { | |
| 521 | + return; | |
| 522 | + } | |
| 523 | + | |
| 505 | 524 | /* Examine all of the 64-bit extended address fields (X fields) */ |
| 506 | 525 | |
| 507 | 526 | for (i = 0; i < ACPI_FADT_INFO_ENTRIES; i++) { |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -135,6 +135,13 @@ acpi_status acpi_tb_initialize_facs(void) · 123 unmodified lines | ||
| 135 | 135 | { |
| 136 | 136 | acpi_status status; |
| 137 | 137 | |
| 138 | + /* If Hardware Reduced flag is set, there is no FACS */ | |
| 139 | + | |
| 140 | + if (acpi_gbl_reduced_hardware) { | |
| 141 | + acpi_gbl_FACS = NULL; | |
| 142 | + return (AE_OK); | |
| 143 | + } | |
| 144 | + | |
| 138 | 145 | status = acpi_get_table_by_index(ACPI_TABLE_INDEX_FACS, |
| 139 | 146 | ACPI_CAST_INDIRECT_PTR(struct |
| 140 | 147 | acpi_table_header, |
| @@ -6,7 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | *****************************************************************************/ |
| 7 | 7 | |
| 8 | 8 | /* |
| 9 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 9 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 10 | 10 | * All rights reserved. |
| 11 | 11 | * |
| 12 | 12 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -0,0 +1,294 @@ | ||
| 1 | +/****************************************************************************** | |
| 2 | + * | |
| 3 | + * Module Name: utaddress - op_region address range check | |
| 4 | + * | |
| 5 | + *****************************************************************************/ | |
| 6 | + | |
| 7 | +/* | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | + * All rights reserved. | |
| 10 | + * | |
| 11 | + * Redistribution and use in source and binary forms, with or without | |
| 12 | + * modification, are permitted provided that the following conditions | |
| 13 | + * are met: | |
| 14 | + * 1. Redistributions of source code must retain the above copyright | |
| 15 | + * notice, this list of conditions, and the following disclaimer, | |
| 16 | + * without modification. | |
| 17 | + * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
| 18 | + * substantially similar to the "NO WARRANTY" disclaimer below | |
| 19 | + * ("Disclaimer") and any redistribution must be conditioned upon | |
| 20 | + * including a substantially similar Disclaimer requirement for further | |
| 21 | + * binary redistribution. | |
| 22 | + * 3. Neither the names of the above-listed copyright holders nor the names | |
| 23 | + * of any contributors may be used to endorse or promote products derived | |
| 24 | + * from this software without specific prior written permission. | |
| 25 | + * | |
| 26 | + * Alternatively, this software may be distributed under the terms of the | |
| 27 | + * GNU General Public License ("GPL") version 2 as published by the Free | |
| 28 | + * Software Foundation. | |
| 29 | + * | |
| 30 | + * NO WARRANTY | |
| 31 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 32 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 33 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR | |
| 34 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 35 | + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 36 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
| 37 | + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 38 | + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
| 39 | + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | |
| 40 | + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
| 41 | + * POSSIBILITY OF SUCH DAMAGES. | |
| 42 | + */ | |
| 43 | + | |
| 44 | +#include <acpi/acpi.h> | |
| 45 | +#include "accommon.h" | |
| 46 | +#include "acnamesp.h" | |
| 47 | + | |
| 48 | +#define _COMPONENT ACPI_UTILITIES | |
| 49 | +ACPI_MODULE_NAME("utaddress") | |
| 50 | + | |
| 51 | +/******************************************************************************* | |
| 52 | + * | |
| 53 | + * FUNCTION: acpi_ut_add_address_range | |
| 54 | + * | |
| 55 | + * PARAMETERS: space_id - Address space ID | |
| 56 | + * Address - op_region start address | |
| 57 | + * Length - op_region length | |
| 58 | + * region_node - op_region namespace node | |
| 59 | + * | |
| 60 | + * RETURN: Status | |
| 61 | + * | |
| 62 | + * DESCRIPTION: Add the Operation Region address range to the global list. | |
| 63 | + * The only supported Space IDs are Memory and I/O. Called when | |
| 64 | + * the op_region address/length operands are fully evaluated. | |
| 65 | + * | |
| 66 | + * MUTEX: Locks the namespace | |
| 67 | + * | |
| 68 | + * NOTE: Because this interface is only called when an op_region argument | |
| 69 | + * list is evaluated, there cannot be any duplicate region_nodes. | |
| 70 | + * Duplicate Address/Length values are allowed, however, so that multiple | |
| 71 | + * address conflicts can be detected. | |
| 72 | + * | |
| 73 | + ******************************************************************************/ | |
| 74 | +acpi_status | |
| 75 | +acpi_ut_add_address_range(acpi_adr_space_type space_id, | |
| 76 | + acpi_physical_address address, | |
| 77 | + u32 length, struct acpi_namespace_node *region_node) | |
| 78 | +{ | |
| 79 | + struct acpi_address_range *range_info; | |
| 80 | + acpi_status status; | |
| 81 | + | |
| 82 | + ACPI_FUNCTION_TRACE(ut_add_address_range); | |
| 83 | + | |
| 84 | + if ((space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) && | |
| 85 | + (space_id != ACPI_ADR_SPACE_SYSTEM_IO)) { | |
| 86 | + return_ACPI_STATUS(AE_OK); | |
| 87 | + } | |
| 88 | + | |
| 89 | + /* Allocate/init a new info block, add it to the appropriate list */ | |
| 90 | + | |
| 91 | + range_info = ACPI_ALLOCATE(sizeof(struct acpi_address_range)); | |
| 92 | + if (!range_info) { | |
| 93 | + return_ACPI_STATUS(AE_NO_MEMORY); | |
| 94 | + } | |
| 95 | + | |
| 96 | + range_info->start_address = address; | |
| 97 | + range_info->end_address = (address + length - 1); | |
| 98 | + range_info->region_node = region_node; | |
| 99 | + | |
| 100 | + status = acpi_ut_acquire_mutex(ACPI_MTX_NAMESPACE); | |
| 101 | + if (ACPI_FAILURE(status)) { | |
| 102 | + ACPI_FREE(range_info); | |
| 103 | + return_ACPI_STATUS(status); | |
| 104 | + } | |
| 105 | + | |
| 106 | + range_info->next = acpi_gbl_address_range_list[space_id]; | |
| 107 | + acpi_gbl_address_range_list[space_id] = range_info; | |
| 108 | + | |
| 109 | + ACPI_DEBUG_PRINT((ACPI_DB_NAMES, | |
| 110 | + "\nAdded [%4.4s] address range: 0x%p-0x%p\n", | |
| 111 | + acpi_ut_get_node_name(range_info->region_node), | |
| 112 | + ACPI_CAST_PTR(void, address), | |
| 113 | + ACPI_CAST_PTR(void, range_info->end_address))); | |
| 114 | + | |
| 115 | + (void)acpi_ut_release_mutex(ACPI_MTX_NAMESPACE); | |
| 116 | + return_ACPI_STATUS(AE_OK); | |
| 117 | +} | |
| 118 | + | |
| 119 | +/******************************************************************************* | |
| 120 | + * | |
| 121 | + * FUNCTION: acpi_ut_remove_address_range | |
| 122 | + * | |
| 123 | + * PARAMETERS: space_id - Address space ID | |
| 124 | + * region_node - op_region namespace node | |
| 125 | + * | |
| 126 | + * RETURN: None | |
| 127 | + * | |
| 128 | + * DESCRIPTION: Remove the Operation Region from the global list. The only | |
| 129 | + * supported Space IDs are Memory and I/O. Called when an | |
| 130 | + * op_region is deleted. | |
| 131 | + * | |
| 132 | + * MUTEX: Assumes the namespace is locked | |
| 133 | + * | |
| 134 | + ******************************************************************************/ | |
| 135 | + | |
| 136 | +void | |
| 137 | +acpi_ut_remove_address_range(acpi_adr_space_type space_id, | |
| 138 | + struct acpi_namespace_node *region_node) | |
| 139 | +{ | |
| 140 | + struct acpi_address_range *range_info; | |
| 141 | + struct acpi_address_range *prev; | |
| 142 | + | |
| 143 | + ACPI_FUNCTION_TRACE(ut_remove_address_range); | |
| 144 | + | |
| 145 | + if ((space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) && | |
| 146 | + (space_id != ACPI_ADR_SPACE_SYSTEM_IO)) { | |
| 147 | + return_VOID; | |
| 148 | + } | |
| 149 | + | |
| 150 | + /* Get the appropriate list head and check the list */ | |
| 151 | + | |
| 152 | + range_info = prev = acpi_gbl_address_range_list[space_id]; | |
| 153 | + while (range_info) { | |
| 154 | + if (range_info->region_node == region_node) { | |
| 155 | + if (range_info == prev) { /* Found at list head */ | |
| 156 | + acpi_gbl_address_range_list[space_id] = | |
| 157 | + range_info->next; | |
| 158 | + } else { | |
| 159 | + prev->next = range_info->next; | |
| 160 | + } | |
| 161 | + | |
| 162 | + ACPI_DEBUG_PRINT((ACPI_DB_NAMES, | |
| 163 | + "\nRemoved [%4.4s] address range: 0x%p-0x%p\n", | |
| 164 | + acpi_ut_get_node_name(range_info-> | |
| 165 | + region_node), | |
| 166 | + ACPI_CAST_PTR(void, | |
| 167 | + range_info-> | |
| 168 | + start_address), | |
| 169 | + ACPI_CAST_PTR(void, | |
| 170 | + range_info-> | |
| 171 | + end_address))); | |
| 172 | + | |
| 173 | + ACPI_FREE(range_info); | |
| 174 | + return_VOID; | |
| 175 | + } | |
| 176 | + | |
| 177 | + prev = range_info; | |
| 178 | + range_info = range_info->next; | |
| 179 | + } | |
| 180 | + | |
| 181 | + return_VOID; | |
| 182 | +} | |
| 183 | + | |
| 184 | +/******************************************************************************* | |
| 185 | + * | |
| 186 | + * FUNCTION: acpi_ut_check_address_range | |
| 187 | + * | |
| 188 | + * PARAMETERS: space_id - Address space ID | |
| 189 | + * Address - Start address | |
| 190 | + * Length - Length of address range | |
| 191 | + * Warn - TRUE if warning on overlap desired | |
| 192 | + * | |
| 193 | + * RETURN: Count of the number of conflicts detected. Zero is always | |
| 194 | + * returned for Space IDs other than Memory or I/O. | |
| 195 | + * | |
| 196 | + * DESCRIPTION: Check if the input address range overlaps any of the | |
| 197 | + * ASL operation region address ranges. The only supported | |
| 198 | + * Space IDs are Memory and I/O. | |
| 199 | + * | |
| 200 | + * MUTEX: Assumes the namespace is locked. | |
| 201 | + * | |
| 202 | + ******************************************************************************/ | |
| 203 | + | |
| 204 | +u32 | |
| 205 | +acpi_ut_check_address_range(acpi_adr_space_type space_id, | |
| 206 | + acpi_physical_address address, u32 length, u8 warn) | |
| 207 | +{ | |
| 208 | + struct acpi_address_range *range_info; | |
| 209 | + acpi_physical_address end_address; | |
| 210 | + char *pathname; | |
| 211 | + u32 overlap_count = 0; | |
| 212 | + | |
| 213 | + ACPI_FUNCTION_TRACE(ut_check_address_range); | |
| 214 | + | |
| 215 | + if ((space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) && | |
| 216 | + (space_id != ACPI_ADR_SPACE_SYSTEM_IO)) { | |
| 217 | + return_UINT32(0); | |
| 218 | + } | |
| 219 | + | |
| 220 | + range_info = acpi_gbl_address_range_list[space_id]; | |
| 221 | + end_address = address + length - 1; | |
| 222 | + | |
| 223 | + /* Check entire list for all possible conflicts */ | |
| 224 | + | |
| 225 | + while (range_info) { | |
| 226 | + /* | |
| 227 | + * Check if the requested Address/Length overlaps this address_range. | |
| 228 | + * Four cases to consider: | |
| 229 | + * | |
| 230 | + * 1) Input address/length is contained completely in the address range | |
| 231 | + * 2) Input address/length overlaps range at the range start | |
| 232 | + * 3) Input address/length overlaps range at the range end | |
| 233 | + * 4) Input address/length completely encompasses the range | |
| 234 | + */ | |
| 235 | + if ((address <= range_info->end_address) && | |
| 236 | + (end_address >= range_info->start_address)) { | |
| 237 | + | |
| 238 | + /* Found an address range overlap */ | |
| 239 | + | |
| 240 | + overlap_count++; | |
| 241 | + if (warn) { /* Optional warning message */ | |
| 242 | + pathname = | |
| 243 | + acpi_ns_get_external_pathname(range_info-> | |
| 244 | + region_node); | |
| 245 | + | |
| 246 | + ACPI_WARNING((AE_INFO, | |
| 247 | + "0x%p-0x%p %s conflicts with Region %s %d", | |
| 248 | + ACPI_CAST_PTR(void, address), | |
| 249 | + ACPI_CAST_PTR(void, end_address), | |
| 250 | + acpi_ut_get_region_name(space_id), | |
| 251 | + pathname, overlap_count)); | |
| 252 | + ACPI_FREE(pathname); | |
| 253 | + } | |
| 254 | + } | |
| 255 | + | |
| 256 | + range_info = range_info->next; | |
| 257 | + } | |
| 258 | + | |
| 259 | + return_UINT32(overlap_count); | |
| 260 | +} | |
| 261 | + | |
| 262 | +/******************************************************************************* | |
| 263 | + * | |
| 264 | + * FUNCTION: acpi_ut_delete_address_lists | |
| 265 | + * | |
| 266 | + * PARAMETERS: None | |
| 267 | + * | |
| 268 | + * RETURN: None | |
| 269 | + * | |
| 270 | + * DESCRIPTION: Delete all global address range lists (called during | |
| 271 | + * subsystem shutdown). | |
| 272 | + * | |
| 273 | + ******************************************************************************/ | |
| 274 | + | |
| 275 | +void acpi_ut_delete_address_lists(void) | |
| 276 | +{ | |
| 277 | + struct acpi_address_range *next; | |
| 278 | + struct acpi_address_range *range_info; | |
| 279 | + int i; | |
| 280 | + | |
| 281 | + /* Delete all elements in all address range lists */ | |
| 282 | + | |
| 283 | + for (i = 0; i < ACPI_ADDRESS_RANGE_MAX; i++) { | |
| 284 | + next = acpi_gbl_address_range_list[i]; | |
| 285 | + | |
| 286 | + while (next) { | |
| 287 | + range_info = next; | |
| 288 | + next = range_info->next; | |
| 289 | + ACPI_FREE(range_info); | |
| 290 | + } | |
| 291 | + | |
| 292 | + acpi_gbl_address_range_list[i] = NULL; | |
| 293 | + } | |
| 294 | +} | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -171,7 +171,9 @@ const char *acpi_gbl_region_types[ACPI_NUM_PREDEFINED_REGIONS] = { · 159 unmodified lines | ||
| 171 | 171 | "SMBus", |
| 172 | 172 | "SystemCMOS", |
| 173 | 173 | "PCIBARTarget", |
| 174 | − "IPMI" | |
| 174 | + "IPMI", | |
| 175 | + "GeneralPurposeIo", | |
| 176 | + "GenericSerialBus" | |
| 175 | 177 | }; |
| 176 | 178 | |
| 177 | 179 | char *acpi_ut_get_region_name(u8 space_id) |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -215,11 +215,14 @@ static void acpi_ut_delete_internal_obj(union acpi_operand_object *object) · 203 unmodified lines | ||
| 215 | 215 | ACPI_DEBUG_PRINT((ACPI_DB_ALLOCATIONS, |
| 216 | 216 | "***** Region %p\n", object)); |
| 217 | 217 | |
| 218 | − /* Invalidate the region address/length via the host OS */ | |
| 219 | − | |
| 220 | − acpi_os_invalidate_address(object->region.space_id, | |
| 221 | − object->region.address, | |
| 222 | − (acpi_size) object->region.length); | |
| 218 | + /* | |
| 219 | + * Update address_range list. However, only permanent regions | |
| 220 | + * are installed in this list. (Not created within a method) | |
| 221 | + */ | |
| 222 | + if (!(object->region.node->flags & ANOBJ_TEMPORARY)) { | |
| 223 | + acpi_ut_remove_address_range(object->region.space_id, | |
| 224 | + object->region.node); | |
| 225 | + } | |
| 223 | 226 | |
| 224 | 227 | second_desc = acpi_ns_get_secondary_object(object); |
| 225 | 228 | if (second_desc) { |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -264,6 +264,12 @@ acpi_status acpi_ut_init_globals(void) · 252 unmodified lines | ||
| 264 | 264 | return_ACPI_STATUS(status); |
| 265 | 265 | } |
| 266 | 266 | |
| 267 | + /* Address Range lists */ | |
| 268 | + | |
| 269 | + for (i = 0; i < ACPI_ADDRESS_RANGE_MAX; i++) { | |
| 270 | + acpi_gbl_address_range_list[i] = NULL; | |
| 271 | + } | |
| 272 | + | |
| 267 | 273 | /* Mutex locked flags */ |
| 268 | 274 | |
| 269 | 275 | for (i = 0; i < ACPI_NUM_MUTEX; i++) { |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -92,6 +92,7 @@ static void acpi_ut_terminate(void) · 80 unmodified lines | ||
| 92 | 92 | gpe_xrupt_info = next_gpe_xrupt_info; |
| 93 | 93 | } |
| 94 | 94 | |
| 95 | + acpi_ut_delete_address_lists(); | |
| 95 | 96 | return_VOID; |
| 96 | 97 | } |
| 97 | 98 | |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -293,14 +293,10 @@ acpi_status acpi_ut_acquire_mutex(acpi_mutex_handle mutex_id) · 281 unmodified lines | ||
| 293 | 293 | |
| 294 | 294 | acpi_status acpi_ut_release_mutex(acpi_mutex_handle mutex_id) |
| 295 | 295 | { |
| 296 | − acpi_thread_id this_thread_id; | |
| 297 | − | |
| 298 | 296 | ACPI_FUNCTION_NAME(ut_release_mutex); |
| 299 | 297 | |
| 300 | − this_thread_id = acpi_os_get_thread_id(); | |
| 301 | − | |
| 302 | 298 | ACPI_DEBUG_PRINT((ACPI_DB_MUTEX, "Thread %u releasing Mutex [%s]\n", |
| 303 | − (u32)this_thread_id, | |
| 299 | + (u32)acpi_os_get_thread_id(), | |
| 304 | 300 | acpi_ut_get_mutex_name(mutex_id))); |
| 305 | 301 | |
| 306 | 302 | if (mutex_id > ACPI_MAX_MUTEX) { |
| @@ -329,7 +325,8 @@ acpi_status acpi_ut_release_mutex(acpi_mutex_handle mutex_id) · 22 unmodified lines | ||
| 329 | 325 | * the ACPI subsystem code. |
| 330 | 326 | */ |
| 331 | 327 | for (i = mutex_id; i < ACPI_NUM_MUTEX; i++) { |
| 332 | − if (acpi_gbl_mutex_info[i].thread_id == this_thread_id) { | |
| 328 | + if (acpi_gbl_mutex_info[i].thread_id == | |
| 329 | + acpi_os_get_thread_id()) { | |
| 333 | 330 | if (i == mutex_id) { |
| 334 | 331 | continue; |
| 335 | 332 | } |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -43,7 +43,7 @@ · 31 unmodified lines | ||
| 43 | 43 | |
| 44 | 44 | #include <acpi/acpi.h> |
| 45 | 45 | #include "accommon.h" |
| 46 | −#include "amlresrc.h" | |
| 46 | +#include "acresrc.h" | |
| 47 | 47 | |
| 48 | 48 | #define _COMPONENT ACPI_UTILITIES |
| 49 | 49 | ACPI_MODULE_NAME("utresrc") |
| @@ -154,6 +154,138 @@ const char *acpi_gbl_typ_decode[] = { · 104 unmodified lines | ||
| 154 | 154 | "TypeF" |
| 155 | 155 | }; |
| 156 | 156 | |
| 157 | +const char *acpi_gbl_ppc_decode[] = { | |
| 158 | + "PullDefault", | |
| 159 | + "PullUp", | |
| 160 | + "PullDown", | |
| 161 | + "PullNone" | |
| 162 | +}; | |
| 163 | + | |
| 164 | +const char *acpi_gbl_ior_decode[] = { | |
| 165 | + "IoRestrictionNone", | |
| 166 | + "IoRestrictionInputOnly", | |
| 167 | + "IoRestrictionOutputOnly", | |
| 168 | + "IoRestrictionNoneAndPreserve" | |
| 169 | +}; | |
| 170 | + | |
| 171 | +const char *acpi_gbl_dts_decode[] = { | |
| 172 | + "Width8bit", | |
| 173 | + "Width16bit", | |
| 174 | + "Width32bit", | |
| 175 | + "Width64bit", | |
| 176 | + "Width128bit", | |
| 177 | + "Width256bit", | |
| 178 | +}; | |
| 179 | + | |
| 180 | +/* GPIO connection type */ | |
| 181 | + | |
| 182 | +const char *acpi_gbl_ct_decode[] = { | |
| 183 | + "Interrupt", | |
| 184 | + "I/O" | |
| 185 | +}; | |
| 186 | + | |
| 187 | +/* Serial bus type */ | |
| 188 | + | |
| 189 | +const char *acpi_gbl_sbt_decode[] = { | |
| 190 | + "/* UNKNOWN serial bus type */", | |
| 191 | + "I2C", | |
| 192 | + "SPI", | |
| 193 | + "UART" | |
| 194 | +}; | |
| 195 | + | |
| 196 | +/* I2C serial bus access mode */ | |
| 197 | + | |
| 198 | +const char *acpi_gbl_am_decode[] = { | |
| 199 | + "AddressingMode7Bit", | |
| 200 | + "AddressingMode10Bit" | |
| 201 | +}; | |
| 202 | + | |
| 203 | +/* I2C serial bus slave mode */ | |
| 204 | + | |
| 205 | +const char *acpi_gbl_sm_decode[] = { | |
| 206 | + "ControllerInitiated", | |
| 207 | + "DeviceInitiated" | |
| 208 | +}; | |
| 209 | + | |
| 210 | +/* SPI serial bus wire mode */ | |
| 211 | + | |
| 212 | +const char *acpi_gbl_wm_decode[] = { | |
| 213 | + "FourWireMode", | |
| 214 | + "ThreeWireMode" | |
| 215 | +}; | |
| 216 | + | |
| 217 | +/* SPI serial clock phase */ | |
| 218 | + | |
| 219 | +const char *acpi_gbl_cph_decode[] = { | |
| 220 | + "ClockPhaseFirst", | |
| 221 | + "ClockPhaseSecond" | |
| 222 | +}; | |
| 223 | + | |
| 224 | +/* SPI serial bus clock polarity */ | |
| 225 | + | |
| 226 | +const char *acpi_gbl_cpo_decode[] = { | |
| 227 | + "ClockPolarityLow", | |
| 228 | + "ClockPolarityHigh" | |
| 229 | +}; | |
| 230 | + | |
| 231 | +/* SPI serial bus device polarity */ | |
| 232 | + | |
| 233 | +const char *acpi_gbl_dp_decode[] = { | |
| 234 | + "PolarityLow", | |
| 235 | + "PolarityHigh" | |
| 236 | +}; | |
| 237 | + | |
| 238 | +/* UART serial bus endian */ | |
| 239 | + | |
| 240 | +const char *acpi_gbl_ed_decode[] = { | |
| 241 | + "LittleEndian", | |
| 242 | + "BigEndian" | |
| 243 | +}; | |
| 244 | + | |
| 245 | +/* UART serial bus bits per byte */ | |
| 246 | + | |
| 247 | +const char *acpi_gbl_bpb_decode[] = { | |
| 248 | + "DataBitsFive", | |
| 249 | + "DataBitsSix", | |
| 250 | + "DataBitsSeven", | |
| 251 | + "DataBitsEight", | |
| 252 | + "DataBitsNine", | |
| 253 | + "/* UNKNOWN Bits per byte */", | |
| 254 | + "/* UNKNOWN Bits per byte */", | |
| 255 | + "/* UNKNOWN Bits per byte */" | |
| 256 | +}; | |
| 257 | + | |
| 258 | +/* UART serial bus stop bits */ | |
| 259 | + | |
| 260 | +const char *acpi_gbl_sb_decode[] = { | |
| 261 | + "StopBitsNone", | |
| 262 | + "StopBitsOne", | |
| 263 | + "StopBitsOnePlusHalf", | |
| 264 | + "StopBitsTwo" | |
| 265 | +}; | |
| 266 | + | |
| 267 | +/* UART serial bus flow control */ | |
| 268 | + | |
| 269 | +const char *acpi_gbl_fc_decode[] = { | |
| 270 | + "FlowControlNone", | |
| 271 | + "FlowControlHardware", | |
| 272 | + "FlowControlXON", | |
| 273 | + "/* UNKNOWN flow control keyword */" | |
| 274 | +}; | |
| 275 | + | |
| 276 | +/* UART serial bus parity type */ | |
| 277 | + | |
| 278 | +const char *acpi_gbl_pt_decode[] = { | |
| 279 | + "ParityTypeNone", | |
| 280 | + "ParityTypeEven", | |
| 281 | + "ParityTypeOdd", | |
| 282 | + "ParityTypeMark", | |
| 283 | + "ParityTypeSpace", | |
| 284 | + "/* UNKNOWN parity keyword */", | |
| 285 | + "/* UNKNOWN parity keyword */", | |
| 286 | + "/* UNKNOWN parity keyword */" | |
| 287 | +}; | |
| 288 | + | |
| 157 | 289 | #endif |
| 158 | 290 | |
| 159 | 291 | /* |
| @@ -173,7 +305,7 @@ const u8 acpi_gbl_resource_aml_sizes[] = { · 13 unmodified lines | ||
| 173 | 305 | ACPI_AML_SIZE_SMALL(struct aml_resource_end_dependent), |
| 174 | 306 | ACPI_AML_SIZE_SMALL(struct aml_resource_io), |
| 175 | 307 | ACPI_AML_SIZE_SMALL(struct aml_resource_fixed_io), |
| 176 | − 0, | |
| 308 | + ACPI_AML_SIZE_SMALL(struct aml_resource_fixed_dma), | |
| 177 | 309 | 0, |
| 178 | 310 | 0, |
| 179 | 311 | 0, |
| @@ -193,7 +325,17 @@ const u8 acpi_gbl_resource_aml_sizes[] = { · 13 unmodified lines | ||
| 193 | 325 | ACPI_AML_SIZE_LARGE(struct aml_resource_address16), |
| 194 | 326 | ACPI_AML_SIZE_LARGE(struct aml_resource_extended_irq), |
| 195 | 327 | ACPI_AML_SIZE_LARGE(struct aml_resource_address64), |
| 196 | − ACPI_AML_SIZE_LARGE(struct aml_resource_extended_address64) | |
| 328 | + ACPI_AML_SIZE_LARGE(struct aml_resource_extended_address64), | |
| 329 | + ACPI_AML_SIZE_LARGE(struct aml_resource_gpio), | |
| 330 | + 0, | |
| 331 | + ACPI_AML_SIZE_LARGE(struct aml_resource_common_serialbus), | |
| 332 | +}; | |
| 333 | + | |
| 334 | +const u8 acpi_gbl_resource_aml_serial_bus_sizes[] = { | |
| 335 | + 0, | |
| 336 | + ACPI_AML_SIZE_LARGE(struct aml_resource_i2c_serialbus), | |
| 337 | + ACPI_AML_SIZE_LARGE(struct aml_resource_spi_serialbus), | |
| 338 | + ACPI_AML_SIZE_LARGE(struct aml_resource_uart_serialbus), | |
| 197 | 339 | }; |
| 198 | 340 | |
| 199 | 341 | /* |
| @@ -209,35 +351,49 @@ static const u8 acpi_gbl_resource_types[] = { · 9 unmodified lines | ||
| 209 | 351 | 0, |
| 210 | 352 | 0, |
| 211 | 353 | 0, |
| 212 | − ACPI_SMALL_VARIABLE_LENGTH, | |
| 213 | − ACPI_FIXED_LENGTH, | |
| 214 | − ACPI_SMALL_VARIABLE_LENGTH, | |
| 215 | − ACPI_FIXED_LENGTH, | |
| 216 | − ACPI_FIXED_LENGTH, | |
| 217 | − ACPI_FIXED_LENGTH, | |
| 218 | − 0, | |
| 354 | + ACPI_SMALL_VARIABLE_LENGTH, /* 04 IRQ */ | |
| 355 | + ACPI_FIXED_LENGTH, /* 05 DMA */ | |
| 356 | + ACPI_SMALL_VARIABLE_LENGTH, /* 06 start_dependent_functions */ | |
| 357 | + ACPI_FIXED_LENGTH, /* 07 end_dependent_functions */ | |
| 358 | + ACPI_FIXED_LENGTH, /* 08 IO */ | |
| 359 | + ACPI_FIXED_LENGTH, /* 09 fixed_iO */ | |
| 360 | + ACPI_FIXED_LENGTH, /* 0_a fixed_dMA */ | |
| 219 | 361 | 0, |
| 220 | 362 | 0, |
| 221 | 363 | 0, |
| 222 | − ACPI_VARIABLE_LENGTH, | |
| 223 | − ACPI_FIXED_LENGTH, | |
| 364 | + ACPI_VARIABLE_LENGTH, /* 0_e vendor_short */ | |
| 365 | + ACPI_FIXED_LENGTH, /* 0_f end_tag */ | |
| 224 | 366 | |
| 225 | 367 | /* Large descriptors */ |
| 226 | 368 | |
| 227 | 369 | 0, |
| 228 | − ACPI_FIXED_LENGTH, | |
| 229 | − ACPI_FIXED_LENGTH, | |
| 370 | + ACPI_FIXED_LENGTH, /* 01 Memory24 */ | |
| 371 | + ACPI_FIXED_LENGTH, /* 02 generic_register */ | |
| 230 | 372 | 0, |
| 231 | − ACPI_VARIABLE_LENGTH, | |
| 232 | − ACPI_FIXED_LENGTH, | |
| 233 | − ACPI_FIXED_LENGTH, | |
| 234 | − ACPI_VARIABLE_LENGTH, | |
| 235 | − ACPI_VARIABLE_LENGTH, | |
| 236 | − ACPI_VARIABLE_LENGTH, | |
| 237 | − ACPI_VARIABLE_LENGTH, | |
| 238 | − ACPI_FIXED_LENGTH | |
| 373 | + ACPI_VARIABLE_LENGTH, /* 04 vendor_long */ | |
| 374 | + ACPI_FIXED_LENGTH, /* 05 Memory32 */ | |
| 375 | + ACPI_FIXED_LENGTH, /* 06 memory32_fixed */ | |
| 376 | + ACPI_VARIABLE_LENGTH, /* 07 Dword* address */ | |
| 377 | + ACPI_VARIABLE_LENGTH, /* 08 Word* address */ | |
| 378 | + ACPI_VARIABLE_LENGTH, /* 09 extended_iRQ */ | |
| 379 | + ACPI_VARIABLE_LENGTH, /* 0_a Qword* address */ | |
| 380 | + ACPI_FIXED_LENGTH, /* 0_b Extended* address */ | |
| 381 | + ACPI_VARIABLE_LENGTH, /* 0_c Gpio* */ | |
| 382 | + 0, | |
| 383 | + ACPI_VARIABLE_LENGTH /* 0_e *serial_bus */ | |
| 239 | 384 | }; |
| 240 | 385 | |
| 386 | +/* | |
| 387 | + * For the i_aSL compiler/disassembler, we don't want any error messages | |
| 388 | + * because the disassembler uses the resource validation code to determine | |
| 389 | + * if Buffer objects are actually Resource Templates. | |
| 390 | + */ | |
| 391 | +#ifdef ACPI_ASL_COMPILER | |
| 392 | +#define ACPI_RESOURCE_ERROR(plist) | |
| 393 | +#else | |
| 394 | +#define ACPI_RESOURCE_ERROR(plist) ACPI_ERROR(plist) | |
| 395 | +#endif | |
| 396 | + | |
| 241 | 397 | /******************************************************************************* |
| 242 | 398 | * |
| 243 | 399 | * FUNCTION: acpi_ut_walk_aml_resources |
| @@ -265,6 +421,7 @@ acpi_ut_walk_aml_resources(u8 * aml, · 21 unmodified lines | ||
| 265 | 421 | u8 resource_index; |
| 266 | 422 | u32 length; |
| 267 | 423 | u32 offset = 0; |
| 424 | + u8 end_tag[2] = { 0x79, 0x00 }; | |
| 268 | 425 | |
| 269 | 426 | ACPI_FUNCTION_TRACE(ut_walk_aml_resources); |
| 270 | 427 | |
| @@ -286,6 +443,10 @@ acpi_ut_walk_aml_resources(u8 * aml, · 15 unmodified lines | ||
| 286 | 443 | |
| 287 | 444 | status = acpi_ut_validate_resource(aml, &resource_index); |
| 288 | 445 | if (ACPI_FAILURE(status)) { |
| 446 | + /* | |
| 447 | + * Exit on failure. Cannot continue because the descriptor length | |
| 448 | + * may be bogus also. | |
| 449 | + */ | |
| 289 | 450 | return_ACPI_STATUS(status); |
| 290 | 451 | } |
| 291 | 452 | |
| @@ -300,7 +461,7 @@ acpi_ut_walk_aml_resources(u8 * aml, · 8 unmodified lines | ||
| 300 | 461 | user_function(aml, length, offset, resource_index, |
| 301 | 462 | context); |
| 302 | 463 | if (ACPI_FAILURE(status)) { |
| 303 | − return (status); | |
| 464 | + return_ACPI_STATUS(status); | |
| 304 | 465 | } |
| 305 | 466 | } |
| 306 | 467 | |
| @@ -333,7 +494,19 @@ acpi_ut_walk_aml_resources(u8 * aml, · 26 unmodified lines | ||
| 333 | 494 | |
| 334 | 495 | /* Did not find an end_tag descriptor */ |
| 335 | 496 | |
| 336 | − return (AE_AML_NO_RESOURCE_END_TAG); | |
| 497 | + if (user_function) { | |
| 498 | + | |
| 499 | + /* Insert an end_tag anyway. acpi_rs_get_list_length always leaves room */ | |
| 500 | + | |
| 501 | + (void)acpi_ut_validate_resource(end_tag, &resource_index); | |
| 502 | + status = | |
| 503 | + user_function(end_tag, 2, offset, resource_index, context); | |
| 504 | + if (ACPI_FAILURE(status)) { | |
| 505 | + return_ACPI_STATUS(status); | |
| 506 | + } | |
| 507 | + } | |
| 508 | + | |
| 509 | + return_ACPI_STATUS(AE_AML_NO_RESOURCE_END_TAG); | |
| 337 | 510 | } |
| 338 | 511 | |
| 339 | 512 | /******************************************************************************* |
| @@ -354,6 +527,7 @@ acpi_ut_walk_aml_resources(u8 * aml, · 14 unmodified lines | ||
| 354 | 527 | |
| 355 | 528 | acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index) |
| 356 | 529 | { |
| 530 | + union aml_resource *aml_resource; | |
| 357 | 531 | u8 resource_type; |
| 358 | 532 | u8 resource_index; |
| 359 | 533 | acpi_rs_length resource_length; |
| @@ -375,7 +549,7 @@ acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index) · 15 unmodified lines | ||
| 375 | 549 | /* Verify the large resource type (name) against the max */ |
| 376 | 550 | |
| 377 | 551 | if (resource_type > ACPI_RESOURCE_NAME_LARGE_MAX) { |
| 378 | − return (AE_AML_INVALID_RESOURCE_TYPE); | |
| 552 | + goto invalid_resource; | |
| 379 | 553 | } |
| 380 | 554 | |
| 381 | 555 | /* |
| @@ -392,15 +566,17 @@ acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index) · 10 unmodified lines | ||
| 392 | 566 | ((resource_type & ACPI_RESOURCE_NAME_SMALL_MASK) >> 3); |
| 393 | 567 | } |
| 394 | 568 | |
| 395 | − /* Check validity of the resource type, zero indicates name is invalid */ | |
| 396 | − | |
| 569 | + /* | |
| 570 | + * Check validity of the resource type, via acpi_gbl_resource_types. Zero | |
| 571 | + * indicates an invalid resource. | |
| 572 | + */ | |
| 397 | 573 | if (!acpi_gbl_resource_types[resource_index]) { |
| 398 | − return (AE_AML_INVALID_RESOURCE_TYPE); | |
| 574 | + goto invalid_resource; | |
| 399 | 575 | } |
| 400 | 576 | |
| 401 | 577 | /* |
| 402 | − * 2) Validate the resource_length field. This ensures that the length | |
| 403 | − * is at least reasonable, and guarantees that it is non-zero. | |
| 578 | + * Validate the resource_length field. This ensures that the length | |
| 579 | + * is at least reasonable, and guarantees that it is non-zero. | |
| 404 | 580 | */ |
| 405 | 581 | resource_length = acpi_ut_get_resource_length(aml); |
| 406 | 582 | minimum_resource_length = acpi_gbl_resource_aml_sizes[resource_index]; |
| @@ -413,7 +589,7 @@ acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index) · 6 unmodified lines | ||
| 413 | 589 | /* Fixed length resource, length must match exactly */ |
| 414 | 590 | |
| 415 | 591 | if (resource_length != minimum_resource_length) { |
| 416 | − return (AE_AML_BAD_RESOURCE_LENGTH); | |
| 592 | + goto bad_resource_length; | |
| 417 | 593 | } |
| 418 | 594 | break; |
| 419 | 595 | |
| @@ -422,7 +598,7 @@ acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index) · 2 unmodified lines | ||
| 422 | 598 | /* Variable length resource, length must be at least the minimum */ |
| 423 | 599 | |
| 424 | 600 | if (resource_length < minimum_resource_length) { |
| 425 | − return (AE_AML_BAD_RESOURCE_LENGTH); | |
| 601 | + goto bad_resource_length; | |
| 426 | 602 | } |
| 427 | 603 | break; |
| 428 | 604 | |
| @@ -432,7 +608,7 @@ acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index) · 3 unmodified lines | ||
| 432 | 608 | |
| 433 | 609 | if ((resource_length > minimum_resource_length) || |
| 434 | 610 | (resource_length < (minimum_resource_length - 1))) { |
| 435 | − return (AE_AML_BAD_RESOURCE_LENGTH); | |
| 611 | + goto bad_resource_length; | |
| 436 | 612 | } |
| 437 | 613 | break; |
| 438 | 614 | |
| @@ -440,7 +616,23 @@ acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index) · 1 unmodified line | ||
| 440 | 616 | |
| 441 | 617 | /* Shouldn't happen (because of validation earlier), but be sure */ |
| 442 | 618 | |
| 443 | − return (AE_AML_INVALID_RESOURCE_TYPE); | |
| 619 | + goto invalid_resource; | |
| 620 | + } | |
| 621 | + | |
| 622 | + aml_resource = ACPI_CAST_PTR(union aml_resource, aml); | |
| 623 | + if (resource_type == ACPI_RESOURCE_NAME_SERIAL_BUS) { | |
| 624 | + | |
| 625 | + /* Validate the bus_type field */ | |
| 626 | + | |
| 627 | + if ((aml_resource->common_serial_bus.type == 0) || | |
| 628 | + (aml_resource->common_serial_bus.type > | |
| 629 | + AML_RESOURCE_MAX_SERIALBUSTYPE)) { | |
| 630 | + ACPI_RESOURCE_ERROR((AE_INFO, | |
| 631 | + "Invalid/unsupported SerialBus resource descriptor: BusType 0x%2.2X", | |
| 632 | + aml_resource->common_serial_bus. | |
| 633 | + type)); | |
| 634 | + return (AE_AML_INVALID_RESOURCE_TYPE); | |
| 635 | + } | |
| 444 | 636 | } |
| 445 | 637 | |
| 446 | 638 | /* Optionally return the resource table index */ |
| @@ -450,6 +642,22 @@ acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index) · 3 unmodified lines | ||
| 450 | 642 | } |
| 451 | 643 | |
| 452 | 644 | return (AE_OK); |
| 645 | + | |
| 646 | + invalid_resource: | |
| 647 | + | |
| 648 | + ACPI_RESOURCE_ERROR((AE_INFO, | |
| 649 | + "Invalid/unsupported resource descriptor: Type 0x%2.2X", | |
| 650 | + resource_type)); | |
| 651 | + return (AE_AML_INVALID_RESOURCE_TYPE); | |
| 652 | + | |
| 653 | + bad_resource_length: | |
| 654 | + | |
| 655 | + ACPI_RESOURCE_ERROR((AE_INFO, | |
| 656 | + "Invalid resource descriptor length: Type " | |
| 657 | + "0x%2.2X, Length 0x%4.4X, MinLength 0x%4.4X", | |
| 658 | + resource_type, resource_length, | |
| 659 | + minimum_resource_length)); | |
| 660 | + return (AE_AML_BAD_RESOURCE_LENGTH); | |
| 453 | 661 | } |
| 454 | 662 | |
| 455 | 663 | /******************************************************************************* |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | *****************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -48,6 +48,7 @@ · 36 unmodified lines | ||
| 48 | 48 | #include "acnamesp.h" |
| 49 | 49 | #include "acdebug.h" |
| 50 | 50 | #include "actables.h" |
| 51 | +#include "acinterp.h" | |
| 51 | 52 | |
| 52 | 53 | #define _COMPONENT ACPI_UTILITIES |
| 53 | 54 | ACPI_MODULE_NAME("utxface") |
| @@ -640,4 +641,41 @@ acpi_status acpi_install_interface_handler(acpi_interface_handler handler) · 586 unmodified lines | ||
| 640 | 641 | } |
| 641 | 642 | |
| 642 | 643 | ACPI_EXPORT_SYMBOL(acpi_install_interface_handler) |
| 644 | + | |
| 645 | +/***************************************************************************** | |
| 646 | + * | |
| 647 | + * FUNCTION: acpi_check_address_range | |
| 648 | + * | |
| 649 | + * PARAMETERS: space_id - Address space ID | |
| 650 | + * Address - Start address | |
| 651 | + * Length - Length | |
| 652 | + * Warn - TRUE if warning on overlap desired | |
| 653 | + * | |
| 654 | + * RETURN: Count of the number of conflicts detected. | |
| 655 | + * | |
| 656 | + * DESCRIPTION: Check if the input address range overlaps any of the | |
| 657 | + * ASL operation region address ranges. | |
| 658 | + * | |
| 659 | + ****************************************************************************/ | |
| 660 | +u32 | |
| 661 | +acpi_check_address_range(acpi_adr_space_type space_id, | |
| 662 | + acpi_physical_address address, | |
| 663 | + acpi_size length, u8 warn) | |
| 664 | +{ | |
| 665 | + u32 overlaps; | |
| 666 | + acpi_status status; | |
| 667 | + | |
| 668 | + status = acpi_ut_acquire_mutex(ACPI_MTX_NAMESPACE); | |
| 669 | + if (ACPI_FAILURE(status)) { | |
| 670 | + return (0); | |
| 671 | + } | |
| 672 | + | |
| 673 | + overlaps = acpi_ut_check_address_range(space_id, address, | |
| 674 | + (u32)length, warn); | |
| 675 | + | |
| 676 | + (void)acpi_ut_release_mutex(ACPI_MTX_NAMESPACE); | |
| 677 | + return (overlaps); | |
| 678 | +} | |
| 679 | + | |
| 680 | +ACPI_EXPORT_SYMBOL(acpi_check_address_range) | |
| 643 | 681 | #endif /* !ACPI_ASL_COMPILER */ |
| @@ -5,7 +5,7 @@ · 4 unmodified lines | ||
| 5 | 5 | ******************************************************************************/ |
| 6 | 6 | |
| 7 | 7 | /* |
| 8 | − * Copyright (C) 2000 - 2011, Intel Corp. | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | 9 | * All rights reserved. |
| 10 | 10 | * |
| 11 | 11 | * Redistribution and use in source and binary forms, with or without |
| @@ -0,0 +1,187 @@ | ||
| 1 | +/******************************************************************************* | |
| 2 | + * | |
| 3 | + * Module Name: utxfmutex - external AML mutex access functions | |
| 4 | + * | |
| 5 | + ******************************************************************************/ | |
| 6 | + | |
| 7 | +/* | |
| 8 | + * Copyright (C) 2000 - 2012, Intel Corp. | |
| 9 | + * All rights reserved. | |
| 10 | + * | |
| 11 | + * Redistribution and use in source and binary forms, with or without | |
| 12 | + * modification, are permitted provided that the following conditions | |
| 13 | + * are met: | |
| 14 | + * 1. Redistributions of source code must retain the above copyright | |
| 15 | + * notice, this list of conditions, and the following disclaimer, | |
| 16 | + * without modification. | |
| 17 | + * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
| 18 | + * substantially similar to the "NO WARRANTY" disclaimer below | |
| 19 | + * ("Disclaimer") and any redistribution must be conditioned upon | |
| 20 | + * including a substantially similar Disclaimer requirement for further | |
| 21 | + * binary redistribution. | |
| 22 | + * 3. Neither the names of the above-listed copyright holders nor the names | |
| 23 | + * of any contributors may be used to endorse or promote products derived | |
| 24 | + * from this software without specific prior written permission. | |
| 25 | + * | |
| 26 | + * Alternatively, this software may be distributed under the terms of the | |
| 27 | + * GNU General Public License ("GPL") version 2 as published by the Free | |
| 28 | + * Software Foundation. | |
| 29 | + * | |
| 30 | + * NO WARRANTY | |
| 31 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 32 | + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 33 | + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR | |
| 34 | + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 35 | + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 36 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
| 37 | + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 38 | + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
| 39 | + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | |
| 40 | + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
| 41 | + * POSSIBILITY OF SUCH DAMAGES. | |
| 42 | + */ | |
| 43 | + | |
| 44 | +#include <acpi/acpi.h> | |
| 45 | +#include "accommon.h" | |
| 46 | +#include "acnamesp.h" | |
| 47 | + | |
| 48 | +#define _COMPONENT ACPI_UTILITIES | |
| 49 | +ACPI_MODULE_NAME("utxfmutex") | |
| 50 | + | |
| 51 | +/* Local prototypes */ | |
| 52 | +static acpi_status | |
| 53 | +acpi_ut_get_mutex_object(acpi_handle handle, | |
| 54 | + acpi_string pathname, | |
| 55 | + union acpi_operand_object **ret_obj); | |
| 56 | + | |
| 57 | +/******************************************************************************* | |
| 58 | + * | |
| 59 | + * FUNCTION: acpi_ut_get_mutex_object | |
| 60 | + * | |
| 61 | + * PARAMETERS: Handle - Mutex or prefix handle (optional) | |
| 62 | + * Pathname - Mutex pathname (optional) | |
| 63 | + * ret_obj - Where the mutex object is returned | |
| 64 | + * | |
| 65 | + * RETURN: Status | |
| 66 | + * | |
| 67 | + * DESCRIPTION: Get an AML mutex object. The mutex node is pointed to by | |
| 68 | + * Handle:Pathname. Either Handle or Pathname can be NULL, but | |
| 69 | + * not both. | |
| 70 | + * | |
| 71 | + ******************************************************************************/ | |
| 72 | + | |
| 73 | +static acpi_status | |
| 74 | +acpi_ut_get_mutex_object(acpi_handle handle, | |
| 75 | + acpi_string pathname, | |
| 76 | + union acpi_operand_object **ret_obj) | |
| 77 | +{ | |
| 78 | + struct acpi_namespace_node *mutex_node; | |
| 79 | + union acpi_operand_object *mutex_obj; | |
| 80 | + acpi_status status; | |
| 81 | + | |
| 82 | + /* Parameter validation */ | |
| 83 | + | |
| 84 | + if (!ret_obj || (!handle && !pathname)) { | |
| 85 | + return (AE_BAD_PARAMETER); | |
| 86 | + } | |
| 87 | + | |
| 88 | + /* Get a the namespace node for the mutex */ | |
| 89 | + | |
| 90 | + mutex_node = handle; | |
| 91 | + if (pathname != NULL) { | |
| 92 | + status = acpi_get_handle(handle, pathname, | |
| 93 | + ACPI_CAST_PTR(acpi_handle, | |
| 94 | + &mutex_node)); | |
| 95 | + if (ACPI_FAILURE(status)) { | |
| 96 | + return (status); | |
| 97 | + } | |
| 98 | + } | |
| 99 | + | |
| 100 | + /* Ensure that we actually have a Mutex object */ | |
| 101 | + | |
| 102 | + if (!mutex_node || (mutex_node->type != ACPI_TYPE_MUTEX)) { | |
| 103 | + return (AE_TYPE); | |
| 104 | + } | |
| 105 | + | |
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File renamed without changes.
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