Merge tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann: "The SoC driver changes once more consist of many small fixes and cleanups, that are to a large part the result of automated testing. On platform specific drivers, this includes SoC specific code for xilinx, freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung, rockchip, renesas, ixp4xx. In firmware drivers, we see a similar picture for SCMI and qcomtee. Aside from these, we see actual new hardware support in a few areas: - The Apple platform gets a new driver for low power states - Updates to Qualcomm platform drivers add several new hardware specific features and additional SoCs. - Amlogic SoC support for A1 and T7 is added - The Mediatek MMSYS driver is refactored as a cleanup" * tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (157 commits) soc: qcom: make QCOM_PDR_MSG selectable soc: qcom: ubwc: Fix missing include soc: qcom: ubwc: Fix link error when QCOM_SMEM=n media: iris: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM drm/msm: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850 firmware: xilinx: Clear firmware notifiers across kexec transitions firmware: xilinx: Release all peripheral devices from firmware firmware: xilinx: Add support to clear EL3 PM state firmware: xilinx: Propagate actual error from feature check firmware: xilinx: Use TF-A feature check for TF-A-specific APIs bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data soc: fsl: qe: check platform_driver_register() in qe_ic_of_init() phy: lynx-10g: use RCW override procedure for dynamic protocol change soc: fsl: guts: implement the RCW override procedure dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region soc: fsl: guts: make fsl_soc_data available after fsl_guts_init() soc: fsl: guts: make it easier to determine on which SoC we are running soc: fsl: guts: add a central fsl_guts_read() function soc: fsl: guts: add a global structure to hold state ...

Linus Torvalds committed 2 months ago

Commit 368cf602 parents cbe8aad aed89a0121 files · +4518 −1444Browse files

Showing the changes to include (8 of 121 files). Show all

Unified · Split

8 files

include/linux/firmware/qcom/qcom_pas.h +43 −0
include/linux/firmware/xlnx-zynqmp.h +9 −1
include/linux/fsl/guts.h +15 −3
include/linux/soc/qcom/geni-se.h +4 −0
include/linux/soc/qcom/smem.h +2 −0
include/linux/soc/qcom/ubwc.h +44 −38
include/soc/fsl/dpaa2-fd.h +10 −9
include/soc/fsl/dpaa2-io.h +2 −2

include/linux/firmware/qcom/qcom_pas.h+43−0

@@ -0,0 +1,43 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
	3	+ * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
	4	+ * Copyright (C) 2015 Linaro Ltd.
	5	+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
	6	+ */
	7	+
	8	+#ifndef __QCOM_PAS_H
	9	+#define __QCOM_PAS_H
	10	+
	11	+#include <linux/err.h>
	12	+#include <linux/types.h>
	13	+
	14	+struct qcom_pas_context {
	15	+ struct device *dev;
	16	+ u32 pas_id;
	17	+ phys_addr_t mem_phys;
	18	+ size_t mem_size;
	19	+ void *ptr;
	20	+ dma_addr_t phys;
	21	+ ssize_t size;
	22	+ bool use_tzmem;
	23	+};
	24	+
	25	+bool qcom_pas_is_available(void);
	26	+struct qcom_pas_context devm_qcom_pas_context_alloc(struct device dev,
	27	+ u32 pas_id,
	28	+ phys_addr_t mem_phys,
	29	+ size_t mem_size);
	30	+int qcom_pas_init_image(u32 pas_id, const void *metadata, size_t size,
	31	+ struct qcom_pas_context *ctx);
	32	+struct resource_table qcom_pas_get_rsc_table(struct qcom_pas_context ctx,
	33	+ void *input_rt, size_t input_rt_size,
	34	+ size_t *output_rt_size);
	35	+int qcom_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size);
	36	+int qcom_pas_auth_and_reset(u32 pas_id);
	37	+int qcom_pas_prepare_and_auth_reset(struct qcom_pas_context *ctx);
	38	+int qcom_pas_set_remote_state(u32 state, u32 pas_id);
	39	+int qcom_pas_shutdown(u32 pas_id);
	40	+bool qcom_pas_supported(u32 pas_id);
	41	+void qcom_pas_metadata_release(struct qcom_pas_context *ctx);
	42	+
	43	+#endif /* __QCOM_PAS_H */

include/linux/firmware/xlnx-zynqmp.h+9−1

@@ -3,7 +3,7 @@ · 2 unmodified lines
3	3	* Xilinx Zynq MPSoC Firmware layer
4	4	*
5	5	* Copyright (C) 2014-2021 Xilinx
6		− * Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc.
	6	+ * Copyright (C) 2022 - 2026 Advanced Micro Devices, Inc.
7	7	*
8	8	* Michal Simek <michal.simek@amd.com>
9	9	* Davorin Mista <davorin.mista@aggios.com>
@@ -50,6 +50,7 @@ · 40 unmodified lines
50	50	/* PM API versions */
51	51	#define PM_API_VERSION_1 1
52	52	#define PM_API_VERSION_2 2
	53	+#define PM_API_VERSION_3 3
53	54
54	55	#define PM_PINCTRL_PARAM_SET_VERSION 2
55	56
@@ -66,6 +67,7 @@ · 10 unmodified lines
66	67	#define FIRMWARE_VERSION_MASK 0xFFFFU
67	68
68	69	/* ATF only commands */
	70	+#define TF_A_CLEAR_PM_STATE 0xa05
69	71	#define TF_A_PM_REGISTER_SGI 0xa04
70	72	#define PM_GET_TRUSTZONE_VERSION 0xa03
71	73	#define PM_SET_SUSPEND_MODE 0xa02
@@ -144,6 +146,12 @@ · 72 unmodified lines
144	146	#define XPM_EVENT_ERROR_MASK_NOC_NCR BIT(13)
145	147	#define XPM_EVENT_ERROR_MASK_NOC_CR BIT(12)
146	148
	149	+/* Node ID for all peripheral devices */
	150	+#define PM_DEV_ALL_PERIPH 0x18224FFFU
	151	+
	152	+/* Node ID for all notifier callbacks */
	153	+#define PM_ALL_NOTIFIERS 0xFFFFFFFFU
	154	+
147	155	enum pm_module_id {
148	156	PM_MODULE_ID = 0x0,
149	157	XPM_MODULE_ID = 0x2,

include/linux/fsl/guts.h+15−3

@@ -13,6 +13,7 @@ · 12 unmodified lines
13	13
14	14	#include <linux/types.h>
15	15	#include <linux/io.h>
	16	+#include <soc/fsl/phy-fsl-lynx.h>
16	17
17	18	/*
18	19	* Global Utility Registers.
@@ -91,9 +92,15 @@ struct ccsr_guts { · 72 unmodified lines
91	92	u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
92	93	Called 'elbcvselcr' on 86xx SOCs */
93	94	u8 res0c4[0x100 - 0xc4];
94		− u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
95		− There are 16 registers */
96		− u8 res140[0x224 - 0x140];
	95	+ /* 0x.0100 - read-only Reset Configuration Word Status registers in
	96	+ * CCSR, or write-only Reset Configuration Word Control registers in
	97	+ * DCSR. In both cases there are 32 registers.
	98	+ */
	99	+ union {
	100	+ u32 rcwsr[32];
	101	+ u32 rcwcr[32];
	102	+ };
	103	+ u8 res180[0x224 - 0x180];
97	104	u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
98	105	u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
99	106	u8 res22c[0x604 - 0x22c];
@@ -131,6 +138,11 @@ struct ccsr_guts { · 31 unmodified lines
131	138	u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
132	139	} __attribute__ ((packed));
133	140
	141	+int fsl_guts_lane_validate(int serdes_idx, int lane,
	142	+ enum lynx_lane_mode lane_mode);
	143	+int fsl_guts_lane_set_mode(int serdes_idx, int lane,
	144	+ enum lynx_lane_mode lane_mode);
	145	+
134	146	/* Alternate function signal multiplex control */
135	147	#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
136	148

include/linux/soc/qcom/geni-se.h+4−0

@@ -124,6 +124,7 @@ struct geni_se { · 123 unmodified lines
124	124	#define SE_DMA_RX_FSM_RST 0xd58
125	125	#define SE_HW_PARAM_0 0xe24
126	126	#define SE_HW_PARAM_1 0xe28
	127	+#define SE_HW_PARAM_2 0xe2c
127	128
128	129	/* GENI_FORCE_DEFAULT_REG fields */
129	130	#define FORCE_DEFAULT BIT(0)
@@ -291,6 +292,9 @@ struct geni_se { · 161 unmodified lines
291	292	#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
292	293	#define RX_FIFO_DEPTH_SHFT 16
293	294
	295	+/* SE_HW_PARAM_2 fields */
	296	+#define PROG_RAM_DEPTH_MSK GENMASK(10, 0)
	297	+
294	298	#define HW_VER_MAJOR_MASK GENMASK(31, 28)
295	299	#define HW_VER_MAJOR_SHFT 28
296	300	#define HW_VER_MINOR_MASK GENMASK(27, 16)

include/linux/soc/qcom/smem.h+2−0

@@ -17,4 +17,6 @@ int qcom_smem_get_feature_code(u32 *code); · 16 unmodified lines
17	17
18	18	int qcom_smem_bust_hwspin_lock_by_host(unsigned int host);
19	19
	20	+int qcom_smem_dram_get_hbb(void);
	21	+
20	22	#endif

include/linux/soc/qcom/ubwc.h+44−38

@@ -8,25 +8,12 @@ · 7 unmodified lines
8	8	#define __QCOM_UBWC_H__
9	9
10	10	#include <linux/bits.h>
	11	+#include <linux/err.h>
11	12	#include <linux/printk.h>
12	13	#include <linux/types.h>
13	14
14	15	struct qcom_ubwc_cfg_data {
15	16	u32 ubwc_enc_version;
16		− /* Can be read from MDSS_BASE + 0x58 */
17		− u32 ubwc_dec_version;
18		−
19		− /**
20		− * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
21		− *
22		− * UBWC 1.0 always enables all three levels.
23		− * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
24		− * UBWC 4.0 adds the optional ability to disable levels 2 & 3.
25		− */
26		− u32 ubwc_swizzle;
27		−#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0)
28		−#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1)
29		−#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2)
30	17
31	18	/**
32	19	* @highest_bank_bit: Highest Bank Bit
@@ -35,16 +22,10 @@ struct qcom_ubwc_cfg_data { · 2 unmodified lines
35	22	* DDR bank. This should ideally use DRAM type detection.
36	23	*/
37	24	int highest_bank_bit;
38		− bool ubwc_bank_spread;
39	25
40		− /**
41		− * @macrotile_mode: Macrotile Mode
42		− *
43		− * Whether to use 4-channel macrotiling mode or the newer
44		− * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
45		− * 4-channel and 1 is 8-channel.
46		− */
47		− bool macrotile_mode;
	26	+ unsigned int flags;
	27	+#define UBWC_FLAG_DISABLE_SWIZZLE_LVL2 BIT(0)
	28	+#define UBWC_FLAG_DISABLE_SWIZZLE_LVL3 BIT(1)
48	29	};
49	30
50	31	#define UBWC_1_0 0x10000000
@@ -67,37 +48,62 @@ static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void) · 16 unmodified lines
67	48
68	49	static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg)
69	50	{
70		− bool ret = cfg->ubwc_enc_version == UBWC_1_0;
71		−
72		− if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1))
73		− pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0\n");
74		−
75		− return ret;
	51	+ return cfg->ubwc_enc_version == UBWC_1_0;
76	52	}
77	53
78		−/*
79		− * This is the best guess, based on the MDSS driver, which worked so far.
80		− */
81	54	static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data *cfg)
82	55	{
83		− return cfg->ubwc_enc_version == UBWC_1_0 &&
84		− (cfg->ubwc_dec_version == UBWC_2_0 \|\|
85		− cfg->ubwc_dec_version == UBWC_3_0);
	56	+ return cfg->ubwc_enc_version == UBWC_1_0;
86	57	}
87	58
	59	+/*
	60	+ * @qcom_ubwc_macrotile_mode: whether to use 4-channel or 8-channel macrotiling
	61	+ *
	62	+ * The 8-channel macrotiling mode was introduced in UBWC 3.1.
	63	+ *
	64	+ * Returns: false for the 4-channel and true for 8-channel.
	65	+ */
88	66	static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg)
89	67	{
90		− return cfg->macrotile_mode;
	68	+ return cfg->ubwc_enc_version >= UBWC_3_1;
91	69	}
92	70
93	71	static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg)
94	72	{
95		− return cfg->ubwc_bank_spread;
	73	+ return true;
96	74	}
97	75
	76	+#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0)
	77	+#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1)
	78	+#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2)
	79	+
	80	+/**
	81	+ * @qcom_ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
	82	+ *
	83	+ * UBWC 1.0 always enables all three levels.
	84	+ * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
	85	+ * UBWC 4.0 adds the optional ability to disable levels 2 & 3.
	86	+ */
98	87	static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg)
99	88	{
100		− return cfg->ubwc_swizzle;
	89	+ if (cfg->ubwc_enc_version == 0)
	90	+ return 0;
	91	+
	92	+ if (cfg->ubwc_enc_version == UBWC_1_0)
	93	+ return UBWC_SWIZZLE_ENABLE_LVL1 \|
	94	+ UBWC_SWIZZLE_ENABLE_LVL2 \|
	95	+ UBWC_SWIZZLE_ENABLE_LVL3;
	96	+
	97	+ u32 ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 \|
	98	+ UBWC_SWIZZLE_ENABLE_LVL3;
	99	+
	100	+ if (cfg->flags & UBWC_FLAG_DISABLE_SWIZZLE_LVL2)
	101	+ ubwc_swizzle &= ~UBWC_SWIZZLE_ENABLE_LVL2;
	102	+
	103	+ if (cfg->flags & UBWC_FLAG_DISABLE_SWIZZLE_LVL3)
	104	+ ubwc_swizzle &= ~UBWC_SWIZZLE_ENABLE_LVL3;
	105	+
	106	+ return ubwc_swizzle;
101	107	}
102	108
103	109	static inline u32 qcom_ubwc_version_tag(const struct qcom_ubwc_cfg_data *cfg)

include/soc/fsl/dpaa2-fd.h+10−9

@@ -25,14 +25,15 @@ · 24 unmodified lines
25	25
26	26	/**
27	27	* struct dpaa2_fd - Struct describing FDs
28		− * @words: for easier/faster copying the whole FD structure
29		− * @addr: address in the FD
30		− * @len: length in the FD
31		− * @bpid: buffer pool ID
32		− * @format_offset: format, offset, and short-length fields
33		− * @frc: frame context
34		− * @ctrl: control bits...including dd, sc, va, err, etc
35		− * @flc: flow context address
	28	+ * @words: for easier/faster copying the whole FD structure
	29	+ * @simple: struct for the FD fields
	30	+ * @simple.addr: address in the FD
	31	+ * @simple.len: length in the FD
	32	+ * @simple.bpid: buffer pool ID
	33	+ * @simple.format_offset: format, offset, and short-length fields
	34	+ * @simple.frc: frame context
	35	+ * @simple.ctrl: control bits...including dd, sc, va, err, etc
	36	+ * @simple.flc: flow context address
36	37	*
37	38	* This structure represents the basic Frame Descriptor used in the system.
38	39	*/
@@ -497,7 +498,7 @@ static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle, · 458 unmodified lines
497	498	* dpaa2_fl_get_frc() - Get the frame context in the FLE
498	499	* @fle: the given frame list entry
499	500	*
500		− * Return the frame context field in the frame lsit entry.
	501	+ * Return the frame context field in the frame list entry.
501	502	*/
502	503	static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
503	504	{

include/soc/fsl/dpaa2-io.h+2−2

@@ -22,7 +22,7 @@ struct device; · 21 unmodified lines
22	22	* DOC: DPIO Service
23	23	*
24	24	* The DPIO service provides APIs for users to interact with the datapath
25		− * by enqueueing and dequeing frame descriptors.
	25	+ * by enqueueing and dequeueing frame descriptors.
26	26	*
27	27	* The following set of APIs can be used to enqueue and dequeue frames
28	28	* as well as producing notification callbacks when data is available
@@ -33,7 +33,7 @@ struct device; · 4 unmodified lines
33	33
34	34	/**
35	35	* struct dpaa2_io_desc - The DPIO descriptor
36		− * @receives_notifications: Use notificaton mode. Non-zero if the DPIO
	36	+ * @receives_notifications: Use notification mode. Non-zero if the DPIO
37	37	* has a channel.
38	38	* @has_8prio: Set to non-zero for channel with 8 priority WQs. Ignored
39	39	* unless receives_notification is TRUE.