MRP frames are configured to be trapped to the CPU queue 7, and this number is reflected in the extraction header. However, the information isn't used anywhere, so just leave MRP frames to go to CPU queue 0 unless needed otherwise.
Unified · Split
| @@ -102,7 +102,6 @@ static int ocelot_mrp_copy_add_vcap(struct ocelot *ocelot, int port, int prio) · 101 unmodified lines | |||
| 102 | filter->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; | 102 | filter->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; |
| 103 | filter->action.port_mask = 0x0; | 103 | filter->action.port_mask = 0x0; |
| 104 | filter->action.cpu_copy_ena = true; | 104 | filter->action.cpu_copy_ena = true; |
| 105 | filter->action.cpu_qu_num = OCELOT_MRP_CPUQ; | ||
| 106 | 105 | ||
| 107 | err = ocelot_vcap_filter_add(ocelot, filter, NULL); | 106 | err = ocelot_vcap_filter_add(ocelot, filter, NULL); |
| 108 | if (err) | 107 | if (err) |
| @@ -105,8 +105,6 @@ · 104 unmodified lines | |||
| 105 | #define REG_RESERVED_ADDR 0xffffffff | 105 | #define REG_RESERVED_ADDR 0xffffffff |
| 106 | #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) | 106 | #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) |
| 107 | 107 | ||
| 108 | #define OCELOT_MRP_CPUQ 7 | ||
| 109 | |||
| 110 | enum ocelot_target { | 108 | enum ocelot_target { |
| 111 | ANA = 1, | 109 | ANA = 1, |
| 112 | QS, | 110 | QS, |