Merge tag 'drm-fixes-2023-03-24' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Daniel Vetter: - usual pile of fixes for amdgpu & i915 - probe error handling fixes for meson, lt8912b bridge - the host1x patch from Arnd - panel-orientation fix for Lenovo Book X90F * tag 'drm-fixes-2023-03-24' of git://anongit.freedesktop.org/drm/drm: (23 commits) gpu: host1x: fix uninitialized variable use drm/amd/display: Set dcn32 caps.seamless_odm drm/amd/display: fix wrong index used in dccg32_set_dpstreamclk drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi drm/amd/display: remove outdated 8bpc comments drm/amdgpu/gfx: set cg flags to enter/exit safe mode drm/amdgpu: Force signal hw_fences that are embedded in non-sched jobs drm/amdgpu: add mes resume when do gfx post soft reset drm/amdgpu: skip ASIC reset for APUs when go to S4 drm/amdgpu: reposition the gpu reset checking for reuse drm/bridge: lt8912b: return EPROBE_DEFER if bridge is not found drm/meson: fix missing component unbind on bind errors drm: panel-orientation-quirks: Add quirk for Lenovo Yoga Book X90F Revert "drm/i915/hwmon: Enable PL1 power limit" drm/i915: Update vblank timestamping stuff on seamless M/N change drm/i915: Fix format for perf_limit_reasons drm/i915/gt: perform uc late init after probe error injection drm/i915/active: Fix missing debug object activation drm/i915/guc: Fix missing ecodes drm/i915/mtl: Disable MC6 for MTL A step ...

Linus Torvalds committed 3 years ago

Commit 37154c12 parents 5ad4fe9 08570b727 files · +180 −123Browse files

Unified · Split

27 files

drivers/gpu/drm/amd/amdgpu/amdgpu.h +3 −2
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +23 −18
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +15 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +4 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +9 −0
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +14 −0
drivers/gpu/drm/amd/amdgpu/nv.c +1 −1
drivers/gpu/drm/amd/amdgpu/vi.c +1 −16
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +0 −1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +1 −2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +1 −0
drivers/gpu/drm/bridge/lontium-lt8912b.c +2 −2
drivers/gpu/drm/drm_panel_orientation_quirks.c +10 −3
drivers/gpu/drm/i915/display/intel_crtc.c +8 −0
drivers/gpu/drm/i915/display/intel_display.c +1 −0
drivers/gpu/drm/i915/display/intel_dmc.c +21 −5
drivers/gpu/drm/i915/display/intel_fbdev.c +18 −6
drivers/gpu/drm/i915/gt/intel_gt.c +2 −2
drivers/gpu/drm/i915/gt/intel_gt_pm.c +0 −27
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +1 −1
drivers/gpu/drm/i915/gt/intel_rc6.c +8 −0
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c +22 −0
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c +1 −12
drivers/gpu/drm/i915/i915_active.c +1 −2
drivers/gpu/drm/i915/i915_hwmon.c +0 −5
drivers/gpu/drm/i915/i915_reg.h +5 −12
drivers/gpu/drm/meson/meson_drv.c +8 −5

drivers/gpu/drm/amd/amdgpu/amdgpu.h+3−2

@@ -1272,6 +1272,7 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); · 1271 unmodified lines
1272	1272	int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1273	1273	bool amdgpu_device_need_post(struct amdgpu_device *adev);
1274	1274	bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
	1275	+bool amdgpu_device_aspm_support_quirk(void);
1275	1276
1276	1277	void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1277	1278	u64 num_vis_bytes);
@@ -1391,10 +1392,12 @@ int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_sta · 113 unmodified lines
1391	1392	int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1392	1393
1393	1394	void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
	1395	+bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1394	1396	void amdgpu_acpi_detect(void);
1395	1397	#else
1396	1398	static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1397	1399	static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
	1400	+static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1398	1401	static inline void amdgpu_acpi_detect(void) { }
1399	1402	static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1400	1403	static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
@@ -1405,11 +1408,9 @@ static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, · 4 unmodified lines
1405	1408
1406	1409	#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1407	1410	bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1408		−bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1409	1411	bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1410	1412	#else
1411	1413	static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1412		−static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1413	1414	static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1414	1415	#endif
1415	1416

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c+23−18

@@ -971,6 +971,29 @@ static bool amdgpu_atcs_pci_probe_handle(struct pci_dev *pdev) · 970 unmodified lines
971	971	return true;
972	972	}
973	973
	974	+
	975	+/**
	976	+ * amdgpu_acpi_should_gpu_reset
	977	+ *
	978	+ * @adev: amdgpu_device_pointer
	979	+ *
	980	+ * returns true if should reset GPU, false if not
	981	+ */
	982	+bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev)
	983	+{
	984	+ if (adev->flags & AMD_IS_APU)
	985	+ return false;
	986	+
	987	+ if (amdgpu_sriov_vf(adev))
	988	+ return false;
	989	+
	990	+#if IS_ENABLED(CONFIG_SUSPEND)
	991	+ return pm_suspend_target_state != PM_SUSPEND_TO_IDLE;
	992	+#else
	993	+ return true;
	994	+#endif
	995	+}
	996	+
974	997	/*
975	998	* amdgpu_acpi_detect - detect ACPI ATIF/ATCS methods
976	999	*
@@ -1042,24 +1065,6 @@ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) · 65 unmodified lines
1042	1065	(pm_suspend_target_state == PM_SUSPEND_MEM);
1043	1066	}
1044	1067
1045		−/**
1046		− * amdgpu_acpi_should_gpu_reset
1047		− *
1048		− * @adev: amdgpu_device_pointer
1049		− *
1050		− * returns true if should reset GPU, false if not
1051		− */
1052		−bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev)
1053		−{
1054		− if (adev->flags & AMD_IS_APU)
1055		− return false;
1056		−
1057		− if (amdgpu_sriov_vf(adev))
1058		− return false;
1059		−
1060		− return pm_suspend_target_state != PM_SUSPEND_TO_IDLE;
1061		−}
1062		−
1063	1068	/**
1064	1069	* amdgpu_acpi_is_s0ix_active
1065	1070	*

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+15−0

@@ -80,6 +80,10 @@ · 79 unmodified lines
80	80
81	81	#include <drm/drm_drv.h>
82	82
	83	+#if IS_ENABLED(CONFIG_X86)
	84	+#include <asm/intel-family.h>
	85	+#endif
	86	+
83	87	MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
84	88	MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
85	89	MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
@@ -1356,6 +1360,17 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) · 1270 unmodified lines
1356	1360	return pcie_aspm_enabled(adev->pdev);
1357	1361	}
1358	1362
	1363	+bool amdgpu_device_aspm_support_quirk(void)
	1364	+{
	1365	+#if IS_ENABLED(CONFIG_X86)
	1366	+ struct cpuinfo_x86 *c = &cpu_data(0);
	1367	+
	1368	+ return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
	1369	+#else
	1370	+ return true;
	1371	+#endif
	1372	+}
	1373	+
1359	1374	/* if we get transitioned to only one device, take VGA back */
1360	1375	/**
1361	1376	* amdgpu_device_vga_set_decode - enable/disable vga decode

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+4−1

@@ -2467,7 +2467,10 @@ static int amdgpu_pmops_freeze(struct device *dev) · 2466 unmodified lines
2467	2467	adev->in_s4 = false;
2468	2468	if (r)
2469	2469	return r;
2470		− return amdgpu_asic_reset(adev);
	2470	+
	2471	+ if (amdgpu_acpi_should_gpu_reset(adev))
	2472	+ return amdgpu_asic_reset(adev);
	2473	+ return 0;
2471	2474	}
2472	2475
2473	2476	static int amdgpu_pmops_thaw(struct device *dev)

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+9−0

@@ -678,6 +678,15 @@ void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring) · 677 unmodified lines
678	678	ptr = &ring->fence_drv.fences[i];
679	679	old = rcu_dereference_protected(*ptr, 1);
680	680	if (old && old->ops == &amdgpu_job_fence_ops) {
	681	+ struct amdgpu_job *job;
	682	+
	683	+ /* For non-scheduler bad job, i.e. failed ib test, we need to signal
	684	+ * it right here or we won't be able to track them in fence_drv
	685	+ * and they will remain unsignaled during sa_bo free.
	686	+ */
	687	+ job = container_of(old, struct amdgpu_job, hw_fence);
	688	+ if (!job->base.s_fence && !dma_fence_is_signaled(old))
	689	+ dma_fence_signal(old);
681	690	RCU_INIT_POINTER(*ptr, NULL);
682	691	dma_fence_put(old);
683	692	}

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+14−0

@@ -1287,6 +1287,11 @@ static int gfx_v11_0_sw_init(void *handle) · 1286 unmodified lines
1287	1287	break;
1288	1288	}
1289	1289
	1290	+ /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */
	1291	+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3) &&
	1292	+ amdgpu_sriov_is_pp_one_vf(adev))
	1293	+ adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG;
	1294	+
1290	1295	/* EOP Event */
1291	1296	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1292	1297	GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
@@ -4655,6 +4660,14 @@ static bool gfx_v11_0_check_soft_reset(void *handle) · 3362 unmodified lines
4655	4660	return false;
4656	4661	}
4657	4662
	4663	+static int gfx_v11_0_post_soft_reset(void *handle)
	4664	+{
	4665	+ /**
	4666	+ * GFX soft reset will impact MES, need resume MES when do GFX soft reset
	4667	+ */
	4668	+ return amdgpu_mes_resume((struct amdgpu_device *)handle);
	4669	+}
	4670	+
4658	4671	static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4659	4672	{
4660	4673	uint64_t clock;
@@ -6166,6 +6179,7 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { · 1505 unmodified lines
6166	6179	.wait_for_idle = gfx_v11_0_wait_for_idle,
6167	6180	.soft_reset = gfx_v11_0_soft_reset,
6168	6181	.check_soft_reset = gfx_v11_0_check_soft_reset,
	6182	+ .post_soft_reset = gfx_v11_0_post_soft_reset,
6169	6183	.set_clockgating_state = gfx_v11_0_set_clockgating_state,
6170	6184	.set_powergating_state = gfx_v11_0_set_powergating_state,
6171	6185	.get_clockgating_state = gfx_v11_0_get_clockgating_state,

drivers/gpu/drm/amd/amdgpu/nv.c+1−1

@@ -578,7 +578,7 @@ static void nv_pcie_gen3_enable(struct amdgpu_device *adev) · 577 unmodified lines
578	578
579	579	static void nv_program_aspm(struct amdgpu_device *adev)
580	580	{
581		− if (!amdgpu_device_should_use_aspm(adev))
	581	+ if (!amdgpu_device_should_use_aspm(adev) \|\| !amdgpu_device_aspm_support_quirk())
582	582	return;
583	583
584	584	if (!(adev->flags & AMD_IS_APU) &&

drivers/gpu/drm/amd/amdgpu/vi.c+1−16

@@ -81,10 +81,6 @@ · 80 unmodified lines
81	81	#include "mxgpu_vi.h"
82	82	#include "amdgpu_dm.h"
83	83
84		−#if IS_ENABLED(CONFIG_X86)
85		−#include <asm/intel-family.h>
86		−#endif
87		−
88	84	#define ixPCIE_LC_L1_PM_SUBSTATE 0x100100C6
89	85	#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
90	86	#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
@@ -1138,24 +1134,13 @@ static void vi_enable_aspm(struct amdgpu_device *adev) · 1047 unmodified lines
1138	1134	WREG32_PCIE(ixPCIE_LC_CNTL, data);
1139	1135	}
1140	1136
1141		−static bool aspm_support_quirk_check(void)
1142		−{
1143		−#if IS_ENABLED(CONFIG_X86)
1144		− struct cpuinfo_x86 *c = &cpu_data(0);
1145		−
1146		− return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
1147		−#else
1148		− return true;
1149		−#endif
1150		−}
1151		−
1152	1137	static void vi_program_aspm(struct amdgpu_device *adev)
1153	1138	{
1154	1139	u32 data, data1, orig;
1155	1140	bool bL1SS = false;
1156	1141	bool bClkReqSupport = true;
1157	1142
1158		− if (!amdgpu_device_should_use_aspm(adev) \|\| !aspm_support_quirk_check())
	1143	+ if (!amdgpu_device_should_use_aspm(adev) \|\| !amdgpu_device_aspm_support_quirk())
1159	1144	return;
1160	1145
1161	1146	if (adev->flags & AMD_IS_APU \|\|

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+0−1

@@ -7244,7 +7244,6 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, · 7243 unmodified lines
7244	7244	if (!aconnector->mst_root)
7245	7245	drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7246	7246
7247		− /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7248	7247	aconnector->base.state->max_bpc = 16;
7249	7248	aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7250	7249

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c+1−2

@@ -271,8 +271,7 @@ static void dccg32_set_dpstreamclk( · 270 unmodified lines
271	271	dccg32_set_dtbclk_p_src(dccg, src, otg_inst);
272	272
273	273	/* enabled to select one of the DTBCLKs for pipe */
274		− switch (otg_inst)
275		− {
	274	+ switch (dp_hpo_inst) {
276	275	case 0:
277	276	REG_UPDATE_2(DPSTREAMCLK_CNTL,
278	277	DPSTREAMCLK0_EN,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c+1−0

@@ -2186,6 +2186,7 @@ static bool dcn32_resource_construct( · 2185 unmodified lines
2186	2186	dc->caps.edp_dsc_support = true;
2187	2187	dc->caps.extended_aux_timeout_support = true;
2188	2188	dc->caps.dmcub_support = true;
	2189	+ dc->caps.seamless_odm = true;
2189	2190
2190	2191	/* Color pipeline capabilities */
2191	2192	dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/bridge/lontium-lt8912b.c+2−2

@@ -676,8 +676,8 @@ static int lt8912_parse_dt(struct lt8912 *lt) · 675 unmodified lines
676	676
677	677	lt->hdmi_port = of_drm_find_bridge(port_node);
678	678	if (!lt->hdmi_port) {
679		− dev_err(lt->dev, "%s: Failed to get hdmi port\n", __func__);
680		− ret = -ENODEV;
	679	+ ret = -EPROBE_DEFER;
	680	+ dev_err_probe(lt->dev, ret, "%s: Failed to get hdmi port\n", __func__);
681	681	goto err_free_host_node;
682	682	}
683	683

drivers/gpu/drm/drm_panel_orientation_quirks.c+10−3

@@ -328,10 +328,17 @@ static const struct dmi_system_id orientation_data[] = { · 327 unmodified lines
328	328	DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "IdeaPad Duet 3 10IGL5"),
329	329	},
330	330	.driver_data = (void *)&lcd1200x1920_rightside_up,
331		− }, { /* Lenovo Yoga Book X90F / X91F / X91L */
	331	+ }, { /* Lenovo Yoga Book X90F / X90L */
332	332	.matches = {
333		− /* Non exact match to match all versions */
334		− DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X9"),
	333	+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
	334	+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
	335	+ DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "YETI-11"),
	336	+ },
	337	+ .driver_data = (void *)&lcd1200x1920_rightside_up,
	338	+ }, { /* Lenovo Yoga Book X91F / X91L */
	339	+ .matches = {
	340	+ /* Non exact match to match F + L versions */
	341	+ DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X91"),
335	342	},
336	343	.driver_data = (void *)&lcd1200x1920_rightside_up,
337	344	}, { /* Lenovo Yoga Tablet 2 830F / 830L */

drivers/gpu/drm/i915/display/intel_crtc.c+8−0

@@ -683,6 +683,14 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) · 682 unmodified lines
683	683	*/
684	684	intel_vrr_send_push(new_crtc_state);
685	685
	686	+ /*
	687	+ * Seamless M/N update may need to update frame timings.
	688	+ *
	689	+ * FIXME Should be synchronized with the start of vblank somehow...
	690	+ */
	691	+ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
	692	+ intel_crtc_update_active_timings(new_crtc_state);
	693	+
686	694	local_irq_enable();
687	695
688	696	if (intel_vgpu_active(dev_priv))

drivers/gpu/drm/i915/display/intel_display.c+1−0

@@ -5145,6 +5145,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, · 5144 unmodified lines
5145	5145	* only fields that are know to not cause problems are preserved. */
5146	5146
5147	5147	saved_state->uapi = crtc_state->uapi;
	5148	+ saved_state->inherited = crtc_state->inherited;
5148	5149	saved_state->scaler_state = crtc_state->scaler_state;
5149	5150	saved_state->shared_dpll = crtc_state->shared_dpll;
5150	5151	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;

drivers/gpu/drm/i915/display/intel_dmc.c+21−5

@@ -384,15 +384,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915) · 383 unmodified lines
384	384	}
385	385	}
386	386
387		−static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
	387	+static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
388	388	{
389	389	enum pipe pipe;
390	390
391		− if (DISPLAY_VER(i915) < 13)
392		− return;
393		−
394	391	/*
395		− * Wa_16015201720:adl-p,dg2, mtl
	392	+ * Wa_16015201720:adl-p,dg2
396	393	* The WA requires clock gating to be disabled all the time
397	394	* for pipe A and B.
398	395	* For pipe C and D clock gating needs to be disabled only
@@ -408,6 +405,25 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) · 9 unmodified lines
408	405	PIPEDMC_GATING_DIS, 0);
409	406	}
410	407
	408	+static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
	409	+{
	410	+ /*
	411	+ * Wa_16015201720
	412	+ * The WA requires clock gating to be disabled all the time
	413	+ * for pipe A and B.
	414	+ */
	415	+ intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
	416	+ MTL_PIPEDMC_GATING_DIS_A \| MTL_PIPEDMC_GATING_DIS_B);
	417	+}
	418	+
	419	+static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
	420	+{
	421	+ if (DISPLAY_VER(i915) >= 14 && enable)
	422	+ mtl_pipedmc_clock_gating_wa(i915);
	423	+ else if (DISPLAY_VER(i915) == 13)
	424	+ adlp_pipedmc_clock_gating_wa(i915, enable);
	425	+}
	426	+
411	427	void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
412	428	{
413	429	if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))

drivers/gpu/drm/i915/display/intel_fbdev.c+18−6

@@ -210,6 +210,7 @@ static int intelfb_create(struct drm_fb_helper *helper, · 209 unmodified lines
210	210	bool prealloc = false;
211	211	void __iomem *vaddr;
212	212	struct drm_i915_gem_object *obj;
	213	+ struct i915_gem_ww_ctx ww;
213	214	int ret;
214	215
215	216	mutex_lock(&ifbdev->hpd_lock);
@@ -283,13 +284,24 @@ static int intelfb_create(struct drm_fb_helper *helper, · 67 unmodified lines
283	284	info->fix.smem_len = vma->size;
284	285	}
285	286
286		− vaddr = i915_vma_pin_iomap(vma);
287		− if (IS_ERR(vaddr)) {
288		− drm_err(&dev_priv->drm,
289		− "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
290		− ret = PTR_ERR(vaddr);
291		− goto out_unpin;
	287	+ for_i915_gem_ww(&ww, ret, false) {
	288	+ ret = i915_gem_object_lock(vma->obj, &ww);
	289	+
	290	+ if (ret)
	291	+ continue;
	292	+
	293	+ vaddr = i915_vma_pin_iomap(vma);
	294	+ if (IS_ERR(vaddr)) {
	295	+ drm_err(&dev_priv->drm,
	296	+ "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
	297	+ ret = PTR_ERR(vaddr);
	298	+ continue;
	299	+ }
292	300	}
	301	+
	302	+ if (ret)
	303	+ goto out_unpin;
	304	+
293	305	info->screen_base = vaddr;
294	306	info->screen_size = vma->size;
295	307

drivers/gpu/drm/i915/gt/intel_gt.c+2−2

@@ -737,12 +737,12 @@ int intel_gt_init(struct intel_gt *gt) · 736 unmodified lines
737	737	if (err)
738	738	goto err_gt;
739	739
740		− intel_uc_init_late(&gt->uc);
741		−
742	740	err = i915_inject_probe_error(gt->i915, -EIO);
743	741	if (err)
744	742	goto err_gt;
745	743
	744	+ intel_uc_init_late(&gt->uc);
	745	+
746	746	intel_migrate_init(&gt->migrate, gt);
747	747
748	748	goto out_fw;

drivers/gpu/drm/i915/gt/intel_gt_pm.c+0−27

@@ -21,31 +21,10 @@ · 20 unmodified lines
21	21	#include "intel_rc6.h"
22	22	#include "intel_rps.h"
23	23	#include "intel_wakeref.h"
24		−#include "intel_pcode.h"
25	24	#include "pxp/intel_pxp_pm.h"
26	25
27	26	#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
28	27
29		−static void mtl_media_busy(struct intel_gt *gt)
30		−{
31		− /* Wa_14017073508: mtl */
32		− if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
33		− gt->type == GT_MEDIA)
34		− snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
35		− PCODE_MBOX_GT_STATE_MEDIA_BUSY,
36		− PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
37		−}
38		−
39		−static void mtl_media_idle(struct intel_gt *gt)
40		−{
41		− /* Wa_14017073508: mtl */
42		− if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
43		− gt->type == GT_MEDIA)
44		− snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
45		− PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY,
46		− PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
47		−}
48		−
49	28	static void user_forcewake(struct intel_gt *gt, bool suspend)
50	29	{
51	30	int count = atomic_read(&gt->user_wakeref);
@@ -93,9 +72,6 @@ static int __gt_unpark(struct intel_wakeref *wf) · 41 unmodified lines
93	72
94	73	GT_TRACE(gt, "\n");
95	74
96		− /* Wa_14017073508: mtl */
97		− mtl_media_busy(gt);
98		−
99	75	/*
100	76	* It seems that the DMC likes to transition between the DC states a lot
101	77	* when there are no connected displays (no active power domains) during
@@ -145,9 +121,6 @@ static int __gt_park(struct intel_wakeref *wf) · 43 unmodified lines
145	121	GEM_BUG_ON(!wakeref);
146	122	intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref);
147	123
148		− /* Wa_14017073508: mtl */
149		− mtl_media_idle(gt);
150		−
151	124	return 0;
152	125	}
153	126

drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c+1−1

@@ -580,7 +580,7 @@ static bool perf_limit_reasons_eval(void *data) · 579 unmodified lines
580	580	}
581	581
582	582	DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
583		− perf_limit_reasons_clear, "%llu\n");
	583	+ perf_limit_reasons_clear, "0x%llx\n");
584	584
585	585	void intel_gt_pm_debugfs_register(struct intel_gt gt, struct dentry root)
586	586	{

drivers/gpu/drm/i915/gt/intel_rc6.c+8−0

@@ -486,6 +486,7 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) · 485 unmodified lines
486	486	static bool rc6_supported(struct intel_rc6 *rc6)
487	487	{
488	488	struct drm_i915_private *i915 = rc6_to_i915(rc6);
	489	+ struct intel_gt *gt = rc6_to_gt(rc6);
489	490
490	491	if (!HAS_RC6(i915))
491	492	return false;
@@ -502,6 +503,13 @@ static bool rc6_supported(struct intel_rc6 *rc6) · 10 unmodified lines
502	503	return false;
503	504	}
504	505
	506	+ if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
	507	+ gt->type == GT_MEDIA) {
	508	+ drm_notice(&i915->drm,
	509	+ "Media RC6 disabled on A step\n");
	510	+ return false;
	511	+ }
	512	+
505	513	return true;
506	514	}
507	515

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c+22−0

@@ -1571,6 +1571,27 @@ int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf, · 1570 unmodified lines
1571	1571
1572	1572	#endif //CONFIG_DRM_I915_CAPTURE_ERROR
1573	1573
	1574	+static void guc_capture_find_ecode(struct intel_engine_coredump *ee)
	1575	+{
	1576	+ struct gcap_reg_list_info *reginfo;
	1577	+ struct guc_mmio_reg *regs;
	1578	+ i915_reg_t reg_ipehr = RING_IPEHR(0);
	1579	+ i915_reg_t reg_instdone = RING_INSTDONE(0);
	1580	+ int i;
	1581	+
	1582	+ if (!ee->guc_capture_node)
	1583	+ return;
	1584	+
	1585	+ reginfo = ee->guc_capture_node->reginfo + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE;
	1586	+ regs = reginfo->regs;
	1587	+ for (i = 0; i < reginfo->num_regs; i++) {
	1588	+ if (regs[i].offset == reg_ipehr.reg)
	1589	+ ee->ipehr = regs[i].value;
	1590	+ else if (regs[i].offset == reg_instdone.reg)
	1591	+ ee->instdone.instdone = regs[i].value;
	1592	+ }
	1593	+}
	1594	+
1574	1595	void intel_guc_capture_free_node(struct intel_engine_coredump *ee)
1575	1596	{
1576	1597	if (!ee \|\| !ee->guc_capture_node)
@@ -1612,6 +1633,7 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt, · 35 unmodified lines
1612	1633	list_del(&n->link);
1613	1634	ee->guc_capture_node = n;
1614	1635	ee->guc_capture = guc->capture;
	1636	+ guc_capture_find_ecode(ee);
1615	1637	return;
1616	1638	}
1617	1639	}

drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c+1−12

@@ -11,20 +11,9 @@ · 10 unmodified lines
11	11
12	12	static bool __guc_rc_supported(struct intel_guc *guc)
13	13	{
14		− struct intel_gt *gt = guc_to_gt(guc);
15		−
16		− /*
17		− * Wa_14017073508: mtl
18		− * Do not enable gucrc to avoid additional interrupts which
19		− * may disrupt pcode wa.
20		− */
21		− if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
22		− gt->type == GT_MEDIA)
23		− return false;
24		−
25	14	/* GuC RC is unavailable for pre-Gen12 */
26	15	return guc->submission_supported &&
27		− GRAPHICS_VER(gt->i915) >= 12;
	16	+ GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
28	17	}
29	18
30	19	static bool __guc_rc_selected(struct intel_guc *guc)

drivers/gpu/drm/i915/i915_active.c+1−2

@@ -92,8 +92,7 @@ static void debug_active_init(struct i915_active *ref) · 91 unmodified lines
92	92	static void debug_active_activate(struct i915_active *ref)
93	93	{
94	94	lockdep_assert_held(&ref->tree_lock);
95		− if (!atomic_read(&ref->count)) /* before the first inc */
96		− debug_object_activate(ref, &active_debug_desc);
	95	+ debug_object_activate(ref, &active_debug_desc);
97	96	}
98	97
99	98	static void debug_active_deactivate(struct i915_active *ref)

drivers/gpu/drm/i915/i915_hwmon.c+0−5

@@ -687,11 +687,6 @@ hwm_get_preregistration_info(struct drm_i915_private *i915) · 686 unmodified lines
687	687	for_each_gt(gt, i915, i)
688	688	hwm_energy(&hwmon->ddat_gt[i], &energy);
689	689	}
690		−
691		− /* Enable PL1 power limit */
692		− if (i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit))
693		− hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,
694		− PKG_PWR_LIM_1_EN, PKG_PWR_LIM_1_EN);
695	690	}
696	691
697	692	void i915_hwmon_register(struct drm_i915_private *i915)

drivers/gpu/drm/i915/i915_reg.h+5−12

@@ -1786,9 +1786,11 @@ · 1785 unmodified lines
1786	1786	* GEN9 clock gating regs
1787	1787	*/
1788	1788	#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1789		−#define DARBF_GATING_DIS (1 << 27)
1790		−#define PWM2_GATING_DIS (1 << 14)
1791		−#define PWM1_GATING_DIS (1 << 13)
	1789	+#define DARBF_GATING_DIS REG_BIT(27)
	1790	+#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
	1791	+#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
	1792	+#define PWM2_GATING_DIS REG_BIT(14)
	1793	+#define PWM1_GATING_DIS REG_BIT(13)
1792	1794
1793	1795	#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1794	1796	#define TGL_VRH_GATING_DIS REG_BIT(31)
@@ -6596,15 +6598,6 @@ · 4801 unmodified lines
6596	6598	/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
6597	6599	#define PCODE_MBOX_DOMAIN_NONE 0x0
6598	6600	#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
6599		−
6600		−/* Wa_14017210380: mtl */
6601		−#define PCODE_MBOX_GT_STATE 0x50
6602		−/* sub-commands (param1) */
6603		−#define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1
6604		−#define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2
6605		−/* param2 */
6606		−#define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1
6607		−
6608	6601	#define GEN6_PCODE_DATA _MMIO(0x138128)
6609	6602	#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
6610	6603	#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16

drivers/gpu/drm/meson/meson_drv.c+8−5

@@ -325,23 +325,23 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) · 324 unmodified lines
325	325
326	326	ret = meson_encoder_hdmi_init(priv);
327	327	if (ret)
328		− goto exit_afbcd;
	328	+ goto unbind_all;
329	329
330	330	ret = meson_plane_create(priv);
331	331	if (ret)
332		− goto exit_afbcd;
	332	+ goto unbind_all;
333	333
334	334	ret = meson_overlay_create(priv);
335	335	if (ret)
336		− goto exit_afbcd;
	336	+ goto unbind_all;
337	337
338	338	ret = meson_crtc_create(priv);
339	339	if (ret)
340		− goto exit_afbcd;
	340	+ goto unbind_all;
341	341
342	342	ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm);
343	343	if (ret)
344		− goto exit_afbcd;
	344	+ goto unbind_all;
345	345
346	346	drm_mode_config_reset(drm);
347	347
@@ -359,6 +359,9 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) · 11 unmodified lines
359	359
360	360	uninstall_irq:
361	361	free_irq(priv->vsync_irq, drm);
	362	+unbind_all:
	363	+ if (has_components)
	364	+ component_unbind_all(drm->dev, drm);
362	365	exit_afbcd:
363	366	if (priv->afbcd.ops)
364	367	priv->afbcd.ops->exit(priv);