lael-labs/linux

Documentation/networking/msg_zerocopy.rst+1−1

@@ -7,7 +7,7 @@ Intro · 6 unmodified lines
7	=====	7	=====
8		8
9	The MSG_ZEROCOPY flag enables copy avoidance for socket send calls.	9	The MSG_ZEROCOPY flag enables copy avoidance for socket send calls.
10	The feature is currently implemented for TCP sockets.	10	The feature is currently implemented for TCP and UDP sockets.
11		11
12		12
13	Opportunity and Caveats	13	Opportunity and Caveats

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	VERSION = 5	2	VERSION = 5
3	PATCHLEVEL = 0	3	PATCHLEVEL = 0
4	SUBLEVEL = 0	4	SUBLEVEL = 0
5	EXTRAVERSION = -rc6	5	EXTRAVERSION = -rc7
6	NAME = Shy Crocodile	6	NAME = Shy Crocodile
7		7
8	# DOCUMENTATION	8	# DOCUMENTATION

arch/arm/Kconfig+1−0

@@ -1400,6 +1400,7 @@ config NR_CPUS · 1399 unmodified lines
1400	config HOTPLUG_CPU	1400	config HOTPLUG_CPU
1401	bool "Support for hot-pluggable CPUs"	1401	bool "Support for hot-pluggable CPUs"
1402	depends on SMP	1402	depends on SMP
		1403	select GENERIC_IRQ_MIGRATION
1403	help	1404	help
1404	Say Y here to experiment with turning CPUs off and on. CPUs	1405	Say Y here to experiment with turning CPUs off and on. CPUs
1405	can be controlled through /sys/devices/system/cpu.	1406	can be controlled through /sys/devices/system/cpu.

arch/arm/boot/dts/omap4-droid4-xt894.dts+11−0

@@ -644,6 +644,17 @@ · 643 unmodified lines
644	};	644	};
645	};	645	};
646		646
		647	/* Configure pwm clock source for timers 8 & 9 */
		648	&timer8 {
		649	assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
		650	assigned-clock-parents = <&sys_clkin_ck>;
		651	};
		652
		653	&timer9 {
		654	assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
		655	assigned-clock-parents = <&sys_clkin_ck>;
		656	};
		657
647	/*	658	/*
648	* As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for	659	* As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
649	* uart1 wakeirq.	660	* uart1 wakeirq.

arch/arm/boot/dts/omap5-board-common.dtsi+6−3

 	palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
 		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */
+			/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
+			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
 		>;
 	};
 	palmas: palmas@48 {
 		compatible = "ti,palmas";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
 		reg = <0x48>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&twl6040_pins>;
-		interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
+		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
 		/* audpwron gpio defined in the board specific dts */

arch/arm/boot/dts/omap5-cm-t54.dts+11−1

 			OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6)  /* llib_wakereqin.gpio1_wk15 */
 		>;
 	};
+	palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
+		pinctrl-single,pins = <
+			/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
+			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
+		>;
+	};
 };
 &omap5_pmx_core {
 	palmas: palmas@48 {
 		compatible = "ti,palmas";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
 		reg = <0x48>;
+		pinctrl-0 = <&palmas_sys_nirq_pins>;
+		pinctrl-names = "default";
+		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		ti,system-power-controller;

arch/arm/boot/dts/rk3188.dtsi+0−1

@@ -719,7 +719,6 @@ · 718 unmodified lines
719	pm_qos = <&qos_lcdc0>,	719	pm_qos = <&qos_lcdc0>,
720	<&qos_lcdc1>,	720	<&qos_lcdc1>,
721	<&qos_cif0>,	721	<&qos_cif0>,
722	<&qos_cif1>,
723	<&qos_ipp>,	722	<&qos_ipp>,
724	<&qos_rga>;	723	<&qos_rga>;
725	};	724	};

arch/arm/include/asm/irq.h+0−1

@@ -25,7 +25,6 @@ · 24 unmodified lines
25	#ifndef __ASSEMBLY__	25	#ifndef __ASSEMBLY__
26	struct irqaction;	26	struct irqaction;
27	struct pt_regs;	27	struct pt_regs;
28	extern void migrate_irqs(void);
29		28
30	extern void asm_do_IRQ(unsigned int, struct pt_regs *);	29	extern void asm_do_IRQ(unsigned int, struct pt_regs *);
31	void handle_IRQ(unsigned int, struct pt_regs *);	30	void handle_IRQ(unsigned int, struct pt_regs *);

arch/arm/include/asm/kvm_host.h+10−0

 #define KVM_REQ_SLEEP \
 	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
 #define KVM_REQ_IRQ_PENDING	KVM_ARCH_REQ(1)
+#define KVM_REQ_VCPU_RESET	KVM_ARCH_REQ(2)
 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
 typedef struct kvm_cpu_context kvm_cpu_context_t;
+struct vcpu_reset_state {
+	unsigned long	pc;
+	unsigned long	r0;
+	bool		be;
+	bool		reset;
+};
 struct kvm_vcpu_arch {
 	struct kvm_cpu_context ctxt;
 	/* Cache some mmu pages needed inside spinlock regions */
 	struct kvm_mmu_memory_cache mmu_page_cache;
+	struct vcpu_reset_state reset_state;
 	/* Detect first run of a vcpu */
 	bool has_run_once;
 };

arch/arm/include/asm/stage2_pgtable.h+5−0

@@ -76,4 +76,9 @@ static inline bool kvm_stage2_has_pud(struct kvm *kvm) · 75 unmodified lines
76	#define S2_PMD_MASK PMD_MASK	76	#define S2_PMD_MASK PMD_MASK
77	#define S2_PMD_SIZE PMD_SIZE	77	#define S2_PMD_SIZE PMD_SIZE
78		78
		79	static inline bool kvm_stage2_has_pmd(struct kvm *kvm)
		80	{
		81	return true;
		82	}
		83
79	#endif /* __ARM_S2_PGTABLE_H_ */	84	#endif /* __ARM_S2_PGTABLE_H_ */

arch/arm/kernel/irq.c+0−62

@@ -31,7 +31,6 @@ · 30 unmodified lines
31	#include <linux/smp.h>	31	#include <linux/smp.h>
32	#include <linux/init.h>	32	#include <linux/init.h>
33	#include <linux/seq_file.h>	33	#include <linux/seq_file.h>
34	#include <linux/ratelimit.h>
35	#include <linux/errno.h>	34	#include <linux/errno.h>
36	#include <linux/list.h>	35	#include <linux/list.h>
37	#include <linux/kallsyms.h>	36	#include <linux/kallsyms.h>
@@ -109,64 +108,3 @@ int __init arch_probe_nr_irqs(void) · 71 unmodified lines
109	return nr_irqs;	108	return nr_irqs;
110	}	109	}
111	#endif	110	#endif
112
113	#ifdef CONFIG_HOTPLUG_CPU
114	static bool migrate_one_irq(struct irq_desc *desc)
115	{
116	struct irq_data *d = irq_desc_get_irq_data(desc);
117	const struct cpumask *affinity = irq_data_get_affinity_mask(d);
118	struct irq_chip *c;
119	bool ret = false;
120
121	/*
122	* If this is a per-CPU interrupt, or the affinity does not
123	* include this CPU, then we have nothing to do.
124	*/
125	if (irqd_is_per_cpu(d) \|\| !cpumask_test_cpu(smp_processor_id(), affinity))
126	return false;
127
128	if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
129	affinity = cpu_online_mask;
130	ret = true;
131	}
132
133	c = irq_data_get_irq_chip(d);
134	if (!c->irq_set_affinity)
135	pr_debug("IRQ%u: unable to set affinity\n", d->irq);
136	else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
137	cpumask_copy(irq_data_get_affinity_mask(d), affinity);
138
139	return ret;
140	}
141
142	/*
143	* The current CPU has been marked offline. Migrate IRQs off this CPU.
144	* If the affinity settings do not allow other CPUs, force them onto any
145	* available CPU.
146	*
147	* Note: we must iterate over all IRQs, whether they have an attached
148	* action structure or not, as we need to get chained interrupts too.
149	*/
150	void migrate_irqs(void)
151	{
152	unsigned int i;
153	struct irq_desc *desc;
154	unsigned long flags;
155
156	local_irq_save(flags);
157
158	for_each_irq_desc(i, desc) {
159	bool affinity_broken;
160
161	raw_spin_lock(&desc->lock);
162	affinity_broken = migrate_one_irq(desc);
163	raw_spin_unlock(&desc->lock);
164
165	if (affinity_broken)
166	pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n",
167	i, smp_processor_id());
168	}
169
170	local_irq_restore(flags);
171	}
172	#endif /* CONFIG_HOTPLUG_CPU */

arch/arm/kernel/smp.c+1−1

@@ -254,7 +254,7 @@ int __cpu_disable(void) · 253 unmodified lines
254	/*	254	/*
255	* OK - migrate IRQs away from this CPU	255	* OK - migrate IRQs away from this CPU
256	*/	256	*/
257	migrate_irqs();	257	irq_migrate_all_off_this_cpu();
258		258
259	/*	259	/*
260	* Flush user cache and TLB mappings, and then remove this CPU	260	* Flush user cache and TLB mappings, and then remove this CPU

arch/arm/kvm/coproc.c+2−2

@@ -1450,6 +1450,6 @@ void kvm_reset_coprocs(struct kvm_vcpu *vcpu) · 1449 unmodified lines
1450	reset_coproc_regs(vcpu, table, num);	1450	reset_coproc_regs(vcpu, table, num);
1451		1451
1452	for (num = 1; num < NR_CP15_REGS; num++)	1452	for (num = 1; num < NR_CP15_REGS; num++)
1453	if (vcpu_cp15(vcpu, num) == 0x42424242)	1453	WARN(vcpu_cp15(vcpu, num) == 0x42424242,
1454	panic("Didn't reset vcpu_cp15(vcpu, %zi)", num);	1454	"Didn't reset vcpu_cp15(vcpu, %zi)", num);
1455	}	1455	}

arch/arm/kvm/reset.c+24−0

@@ -26,6 +26,7 @@ · 25 unmodified lines
26	#include <asm/cputype.h>	26	#include <asm/cputype.h>
27	#include <asm/kvm_arm.h>	27	#include <asm/kvm_arm.h>
28	#include <asm/kvm_coproc.h>	28	#include <asm/kvm_coproc.h>
		29	#include <asm/kvm_emulate.h>
29		30
30	#include <kvm/arm_arch_timer.h>	31	#include <kvm/arm_arch_timer.h>
31		32
@@ -69,6 +70,29 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) · 37 unmodified lines
69	/* Reset CP15 registers */	70	/* Reset CP15 registers */
70	kvm_reset_coprocs(vcpu);	71	kvm_reset_coprocs(vcpu);
71		72
		73	/*
		74	* Additional reset state handling that PSCI may have imposed on us.
		75	* Must be done after all the sys_reg reset.
		76	*/
		77	if (READ_ONCE(vcpu->arch.reset_state.reset)) {
		78	unsigned long target_pc = vcpu->arch.reset_state.pc;
		79
		80	/* Gracefully handle Thumb2 entry point */
		81	if (target_pc & 1) {
		82	target_pc &= ~1UL;
		83	vcpu_set_thumb(vcpu);
		84	}
		85
		86	/* Propagate caller endianness */
		87	if (vcpu->arch.reset_state.be)
		88	kvm_vcpu_set_be(vcpu);
		89
		90	*vcpu_pc(vcpu) = target_pc;
		91	vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
		92
		93	vcpu->arch.reset_state.reset = false;
		94	}
		95
72	/* Reset arch_timer context */	96	/* Reset arch_timer context */
73	return kvm_timer_vcpu_reset(vcpu);	97	return kvm_timer_vcpu_reset(vcpu);
74	}	98	}

arch/arm/mach-omap2/cpuidle44xx.c+4−12

 	mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
 				 (cx->mpu_logic_state == PWRDM_POWER_OFF);
+	/* Enter broadcast mode for periodic timers */
+	tick_broadcast_enable();
+	/* Enter broadcast mode for one-shot timers */
 	tick_broadcast_enter();
 	/*
 	return index;
 }
-/*
- * For each cpu, setup the broadcast timer because local timers
- * stops for the states above C1.
- */
-static void omap_setup_broadcast_timer(void *arg)
-{
-	tick_broadcast_enable();
-}
 static struct cpuidle_driver omap4_idle_driver = {
 	.name				= "omap4_idle",
 	.owner				= THIS_MODULE,
 	if (!cpu_clkdm[0] || !cpu_clkdm[1])
 		return -ENODEV;
-	/* Configure the broadcast timer on each cpu */
-	on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
 	return cpuidle_register(idle_driver, cpu_online_mask);
 }

arch/arm/mach-omap2/display.c+6−1

 	u32 enable_mask, enable_shift;
 	u32 pipd_mask, pipd_shift;
 	u32 reg;
+	int ret;
 	if (dsi_id == 0) {
 		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
 		return -ENODEV;
 	}
-	regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
+	ret = regmap_read(omap4_dsi_mux_syscon,
+					  OMAP4_DSIPHY_SYSCON_OFFSET,
+					  &reg);
+	if (ret)
+		return ret;
 	reg &= ~enable_mask;
 	reg &= ~pipd_mask;

arch/arm/mach-omap2/omap-wakeupgen.c+35−1

@@ -50,6 +50,9 @@ · 49 unmodified lines
50	#define OMAP4_NR_BANKS 4	50	#define OMAP4_NR_BANKS 4
51	#define OMAP4_NR_IRQS 128	51	#define OMAP4_NR_IRQS 128
52		52
		53	#define SYS_NIRQ1_EXT_SYS_IRQ_1 7
		54	#define SYS_NIRQ2_EXT_SYS_IRQ_2 119
		55
53	static void __iomem *wakeupgen_base;	56	static void __iomem *wakeupgen_base;
54	static void __iomem *sar_base;	57	static void __iomem *sar_base;
55	static DEFINE_RAW_SPINLOCK(wakeupgen_lock);	58	static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
@@ -153,6 +156,37 @@ static void wakeupgen_unmask(struct irq_data *d) · 97 unmodified lines
153	irq_chip_unmask_parent(d);	156	irq_chip_unmask_parent(d);
154	}	157	}
155		158
		159	/*
		160	* The sys_nirq pins bypass peripheral modules and are wired directly
		161	* to MPUSS wakeupgen. They get automatically inverted for GIC.
		162	*/
		163	static int wakeupgen_irq_set_type(struct irq_data *d, unsigned int type)
		164	{
		165	bool inverted = false;
		166
		167	switch (type) {
		168	case IRQ_TYPE_LEVEL_LOW:
		169	type &= ~IRQ_TYPE_LEVEL_MASK;
		170	type \|= IRQ_TYPE_LEVEL_HIGH;
		171	inverted = true;
		172	break;
		173	case IRQ_TYPE_EDGE_FALLING:
		174	type &= ~IRQ_TYPE_EDGE_BOTH;
		175	type \|= IRQ_TYPE_EDGE_RISING;
		176	inverted = true;
		177	break;
		178	default:
		179	break;
		180	}
		181
		182	if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&
		183	d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)
		184	pr_warn("wakeupgen: irq%li polarity inverted in dts\n",
		185	d->hwirq);
		186
		187	return irq_chip_set_type_parent(d, type);
		188	}
		189
156	#ifdef CONFIG_HOTPLUG_CPU	190	#ifdef CONFIG_HOTPLUG_CPU
157	static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);	191	static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
158		192
@@ -446,7 +480,7 @@ static struct irq_chip wakeupgen_chip = { · 287 unmodified lines
446	.irq_mask = wakeupgen_mask,	480	.irq_mask = wakeupgen_mask,
447	.irq_unmask = wakeupgen_unmask,	481	.irq_unmask = wakeupgen_unmask,
448	.irq_retrigger = irq_chip_retrigger_hierarchy,	482	.irq_retrigger = irq_chip_retrigger_hierarchy,
449	.irq_set_type = irq_chip_set_type_parent,	483	.irq_set_type = wakeupgen_irq_set_type,
450	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND,	484	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND,
451	#ifdef CONFIG_SMP	485	#ifdef CONFIG_SMP
452	.irq_set_affinity = irq_chip_set_affinity_parent,	486	.irq_set_affinity = irq_chip_set_affinity_parent,

arch/arm/mm/dma-mapping.c+2−0

@@ -2390,4 +2390,6 @@ void arch_teardown_dma_ops(struct device *dev) · 2389 unmodified lines
2390	return;	2390	return;
2391		2391
2392	arm_teardown_iommu_dma_ops(dev);	2392	arm_teardown_iommu_dma_ops(dev);
		2393	/* Let arch_setup_dma_ops() start again from scratch upon re-probe */
		2394	set_dma_ops(dev, NULL);
2393	}	2395	}

arch/arm/probes/kprobes/opt-arm.c+1−1

@@ -247,7 +247,7 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe op, struct kprobe or · 246 unmodified lines
247	}	247	}
248		248
249	/* Copy arch-dep-instance from template. */	249	/* Copy arch-dep-instance from template. */
250	memcpy(code, (unsigned char *)optprobe_template_entry,	250	memcpy(code, (unsigned long *)&optprobe_template_entry,
251	TMPL_END_IDX * sizeof(kprobe_opcode_t));	251	TMPL_END_IDX * sizeof(kprobe_opcode_t));
252		252
253	/* Adjust buffer according to instruction. */	253	/* Adjust buffer according to instruction. */

arch/arm64/boot/dts/freescale/imx8mq-evk.dts+22−22

@@ -227,34 +227,34 @@ · 226 unmodified lines
227		227
228	pinctrl_usdhc1_100mhz: usdhc1-100grp {	228	pinctrl_usdhc1_100mhz: usdhc1-100grp {
229	fsl,pins = <	229	fsl,pins = <
230	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85	230	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
231	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5	231	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
232	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5	232	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
233	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5	233	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
234	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5	234	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
235	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5	235	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
236	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5	236	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
237	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5	237	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
238	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5	238	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
239	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5	239	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
240	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85	240	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
241	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1	241	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
242	>;	242	>;
243	};	243	};
244		244
245	pinctrl_usdhc1_200mhz: usdhc1-200grp {	245	pinctrl_usdhc1_200mhz: usdhc1-200grp {
246	fsl,pins = <	246	fsl,pins = <
247	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87	247	MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
248	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7	248	MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
249	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7	249	MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
250	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7	250	MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
251	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7	251	MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
252	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7	252	MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
253	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7	253	MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
254	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7	254	MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
255	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7	255	MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
256	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7	256	MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
257	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87	257	MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
258	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1	258	MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
259	>;	259	>;
260	};	260	};

arch/arm64/boot/dts/freescale/imx8mq.dtsi+2−0

 				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 				clock-names = "ipg", "ahb", "per";
+				assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+				assigned-clock-rates = <400000000>;
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step = <2>;
 				bus-width = <4>;

arch/arm64/boot/dts/rockchip/rk3328-rock64.dts+2−0

 		pinctrl-0 = <&usb30_host_drv>;
 		regulator-name = "vcc_host_5v";
 		regulator-always-on;
+		regulator-boot-on;
 		vin-supply = <&vcc_sys>;
 	};
 		pinctrl-0 = <&usb20_host_drv>;
 		regulator-name = "vcc_host1_5v";
 		regulator-always-on;
+		regulator-boot-on;
 		vin-supply = <&vcc_sys>;
 	};

arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts+1−1

@@ -22,7 +22,7 @@ · 21 unmodified lines
22	backlight = <&backlight>;	22	backlight = <&backlight>;
23	power-supply = <&pp3300_disp>;	23	power-supply = <&pp3300_disp>;
24		24
25	ports {	25	port {
26	panel_in_edp: endpoint {	26	panel_in_edp: endpoint {
27	remote-endpoint = <&edp_out_panel>;	27	remote-endpoint = <&edp_out_panel>;
28	};	28	};

arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts+1−1

@@ -43,7 +43,7 @@ · 42 unmodified lines
43	backlight = <&backlight>;	43	backlight = <&backlight>;
44	power-supply = <&pp3300_disp>;	44	power-supply = <&pp3300_disp>;
45		45
46	ports {	46	port {
47	panel_in_edp: endpoint {	47	panel_in_edp: endpoint {
48	remote-endpoint = <&edp_out_panel>;	48	remote-endpoint = <&edp_out_panel>;
49	};	49	};

arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts+1−1

@@ -91,7 +91,7 @@ · 90 unmodified lines
91	pinctrl-0 = <&lcd_panel_reset>;	91	pinctrl-0 = <&lcd_panel_reset>;
92	power-supply = <&vcc3v3_s0>;	92	power-supply = <&vcc3v3_s0>;
93		93
94	ports {	94	port {
95	panel_in_edp: endpoint {	95	panel_in_edp: endpoint {
96	remote-endpoint = <&edp_out_panel>;	96	remote-endpoint = <&edp_out_panel>;
97	};	97	};

arch/arm64/include/asm/kvm_host.h+11−0

 #define KVM_REQ_SLEEP \
 	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
 #define KVM_REQ_IRQ_PENDING	KVM_ARCH_REQ(1)
+#define KVM_REQ_VCPU_RESET	KVM_ARCH_REQ(2)
 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
 typedef struct kvm_cpu_context kvm_cpu_context_t;
+struct vcpu_reset_state {
+	unsigned long	pc;
+	unsigned long	r0;
+	bool		be;
+	bool		reset;
+};
 struct kvm_vcpu_arch {
 	struct kvm_cpu_context ctxt;
 	/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
 	u64 vsesr_el2;
+	/* Additional reset state */
+	struct vcpu_reset_state	reset_state;
 	/* True when deferrable sysregs are loaded on the physical CPU,
 	 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
 	bool sysregs_loaded_on_cpu;

arch/arm64/include/asm/memory.h+11−0

@@ -332,6 +332,17 @@ static inline void *phys_to_virt(phys_addr_t x) · 331 unmodified lines
332	#define virt_addr_valid(kaddr) \	332	#define virt_addr_valid(kaddr) \
333	(_virt_addr_is_linear(kaddr) && _virt_addr_valid(kaddr))	333	(_virt_addr_is_linear(kaddr) && _virt_addr_valid(kaddr))
334		334
		335	/*
		336	* Given that the GIC architecture permits ITS implementations that can only be
		337	* configured with a LPI table address once, GICv3 systems with many CPUs may
		338	* end up reserving a lot of different regions after a kexec for their LPI
		339	* tables (one per CPU), as we are forced to reuse the same memory after kexec
		340	* (and thus reserve it persistently with EFI beforehand)
		341	*/
		342	#if defined(CONFIG_EFI) && defined(CONFIG_ARM_GIC_V3_ITS)
		343	# define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + NR_CPUS + 1)
		344	#endif
		345
335	#include <asm-generic/memory_model.h>	346	#include <asm-generic/memory_model.h>
336		347
337	#endif	348	#endif

arch/arm64/kernel/setup.c+0−1

@@ -313,7 +313,6 @@ void __init setup_arch(char **cmdline_p) · 312 unmodified lines
313	arm64_memblock_init();	313	arm64_memblock_init();
314		314
315	paging_init();	315	paging_init();
316	efi_apply_persistent_mem_reservations();
317		316
318	acpi_table_upgrade();	317	acpi_table_upgrade();
319		318

arch/arm64/kvm/hyp/switch.c+5−0

 #include <kvm/arm_psci.h>
 #include <asm/cpufeature.h>
+#include <asm/kprobes.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_host.h>
 	write_sysreg(kvm_get_hyp_vector(), vbar_el1);
 }
+NOKPROBE_SYMBOL(activate_traps_vhe);
 static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
 {
 	write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
 	write_sysreg(vectors, vbar_el1);
 }
+NOKPROBE_SYMBOL(deactivate_traps_vhe);
 static void __hyp_text __deactivate_traps_nvhe(void)
 {
 	return exit_code;
 }
+NOKPROBE_SYMBOL(kvm_vcpu_run_vhe);
 /* Switch to the guest for legacy non-VHE systems */
 int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
 	      read_sysreg_el2(esr),   read_sysreg_el2(far),
 	      read_sysreg(hpfar_el2), par, vcpu);
 }
+NOKPROBE_SYMBOL(__hyp_call_panic_vhe);
 void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
 {

arch/arm64/kvm/hyp/sysreg-sr.c+5−0

 #include <linux/compiler.h>
 #include <linux/kvm_host.h>
+#include <asm/kprobes.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_hyp.h>
 {
 	__sysreg_save_common_state(ctxt);
 }
+NOKPROBE_SYMBOL(sysreg_save_host_state_vhe);
 void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt)
 {
 	__sysreg_save_common_state(ctxt);
 	__sysreg_save_el2_return_state(ctxt);
 }
+NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe);
 static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
 {
 {
 	__sysreg_restore_common_state(ctxt);
 }
+NOKPROBE_SYMBOL(sysreg_restore_host_state_vhe);
 void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt)
 {
 	__sysreg_restore_common_state(ctxt);
 	__sysreg_restore_el2_return_state(ctxt);
 }
+NOKPROBE_SYMBOL(sysreg_restore_guest_state_vhe);
 void __hyp_text __sysreg32_save_state(struct kvm_vcpu *vcpu)
 {

arch/arm64/kvm/reset.c+48−2

@@ -32,6 +32,7 @@ · 31 unmodified lines
32	#include <asm/kvm_arm.h>	32	#include <asm/kvm_arm.h>
33	#include <asm/kvm_asm.h>	33	#include <asm/kvm_asm.h>
34	#include <asm/kvm_coproc.h>	34	#include <asm/kvm_coproc.h>
		35	#include <asm/kvm_emulate.h>
35	#include <asm/kvm_mmu.h>	36	#include <asm/kvm_mmu.h>
36		37
37	/* Maximum phys_shift supported for any VM on this host */	38	/* Maximum phys_shift supported for any VM on this host */
@@ -105,16 +106,33 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) · 67 unmodified lines
105	* This function finds the right table above and sets the registers on	106	* This function finds the right table above and sets the registers on
106	* the virtual CPU struct to their architecturally defined reset	107	* the virtual CPU struct to their architecturally defined reset
107	* values.	108	* values.
		109	*
		110	* Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT
		111	* ioctl or as part of handling a request issued by another VCPU in the PSCI
		112	* handling code. In the first case, the VCPU will not be loaded, and in the
		113	* second case the VCPU will be loaded. Because this function operates purely
		114	* on the memory-backed valus of system registers, we want to do a full put if
		115	* we were loaded (handling a request) and load the values back at the end of
		116	* the function. Otherwise we leave the state alone. In both cases, we
		117	* disable preemption around the vcpu reset as we would otherwise race with
		118	* preempt notifiers which also call put/load.
108	*/	119	*/
109	int kvm_reset_vcpu(struct kvm_vcpu *vcpu)	120	int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
110	{	121	{
111	const struct kvm_regs *cpu_reset;	122	const struct kvm_regs *cpu_reset;
		123	int ret = -EINVAL;
		124	bool loaded;
		125
		126	preempt_disable();
		127	loaded = (vcpu->cpu != -1);
		128	if (loaded)
		129	kvm_arch_vcpu_put(vcpu);
112		130
113	switch (vcpu->arch.target) {	131	switch (vcpu->arch.target) {
114	default:	132	default:
115	if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {	133	if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
116	if (!cpu_has_32bit_el1())	134	if (!cpu_has_32bit_el1())
117	return -EINVAL;	135	goto out;
118	cpu_reset = &default_regs_reset32;	136	cpu_reset = &default_regs_reset32;
119	} else {	137	} else {
120	cpu_reset = &default_regs_reset;	138	cpu_reset = &default_regs_reset;
@@ -129,6 +147,29 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) · 8 unmodified lines
129	/* Reset system registers */	147	/* Reset system registers */
130	kvm_reset_sys_regs(vcpu);	148	kvm_reset_sys_regs(vcpu);
131		149
		150	/*
		151	* Additional reset state handling that PSCI may have imposed on us.
		152	* Must be done after all the sys_reg reset.
		153	*/
		154	if (vcpu->arch.reset_state.reset) {
		155	unsigned long target_pc = vcpu->arch.reset_state.pc;
		156
		157	/* Gracefully handle Thumb2 entry point */
		158	if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
		159	target_pc &= ~1UL;
		160	vcpu_set_thumb(vcpu);
		161	}
		162
		163	/* Propagate caller endianness */
		164	if (vcpu->arch.reset_state.be)
		165	kvm_vcpu_set_be(vcpu);
		166
		167	*vcpu_pc(vcpu) = target_pc;
		168	vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
		169
		170	vcpu->arch.reset_state.reset = false;
		171	}
		172
132	/* Reset PMU */	173	/* Reset PMU */
133	kvm_pmu_vcpu_reset(vcpu);	174	kvm_pmu_vcpu_reset(vcpu);
134		175
@@ -137,7 +178,12 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) · 2 unmodified lines
137	vcpu->arch.workaround_flags \|= VCPU_WORKAROUND_2_FLAG;	178	vcpu->arch.workaround_flags \|= VCPU_WORKAROUND_2_FLAG;
138		179
139	/* Reset timer */	180	/* Reset timer */
140	return kvm_timer_vcpu_reset(vcpu);	181	ret = kvm_timer_vcpu_reset(vcpu);
		182	out:
		183	if (loaded)
		184	kvm_arch_vcpu_load(vcpu, smp_processor_id());
		185	preempt_enable();
		186	return ret;
141	}	187	}
142		188
143	void kvm_set_ipa_limit(void)	189	void kvm_set_ipa_limit(void)

arch/arm64/kvm/sys_regs.c+32−18

 		return read_zero(vcpu, p);
 }
-static bool trap_undef(struct kvm_vcpu *vcpu,
+/*
-		       struct sys_reg_params *p,
+ * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
-		       const struct sys_reg_desc *r)
+ * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
+ * system, these registers should UNDEF. LORID_EL1 being a RO register, we
+ * treat it separately.
+ */
+static bool trap_loregion(struct kvm_vcpu *vcpu,
+			  struct sys_reg_params *p,
+			  const struct sys_reg_desc *r)
 {
-	kvm_inject_undefined(vcpu);
+	u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
-	return false;
+	u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
+			 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
+	if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
+		kvm_inject_undefined(vcpu);
+		return false;
+	}
+	if (p->is_write && sr == SYS_LORID_EL1)
+		return write_to_read_only(vcpu, p, r);
+	return trap_raz_wi(vcpu, p, r);
 }
 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 		if (val & ptrauth_mask)
 			kvm_debug("ptrauth unsupported for guests, suppressing\n");
 		val &= ~ptrauth_mask;
-	} else if (id == SYS_ID_AA64MMFR1_EL1) {
-		if (val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))
-			kvm_debug("LORegions unsupported for guests, suppressing\n");
-		val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);
 	}
 	return val;
 	{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
 	{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
-	{ SYS_DESC(SYS_LORSA_EL1), trap_undef },
+	{ SYS_DESC(SYS_LORSA_EL1), trap_loregion },
-	{ SYS_DESC(SYS_LOREA_EL1), trap_undef },
+	{ SYS_DESC(SYS_LOREA_EL1), trap_loregion },
-	{ SYS_DESC(SYS_LORN_EL1), trap_undef },
+	{ SYS_DESC(SYS_LORN_EL1), trap_loregion },
-	{ SYS_DESC(SYS_LORC_EL1), trap_undef },
+	{ SYS_DESC(SYS_LORC_EL1), trap_loregion },
-	{ SYS_DESC(SYS_LORID_EL1), trap_undef },
+	{ SYS_DESC(SYS_LORID_EL1), trap_loregion },
 	{ SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
 	{ SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
 	table = get_target_table(vcpu->arch.target, true, &num);
 	reset_sys_reg_descs(vcpu, table, num);
-	for (num = 1; num < NR_SYS_REGS; num++)
+	for (num = 1; num < NR_SYS_REGS; num++) {
-		if (__vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
+		if (WARN(__vcpu_sys_reg(vcpu, num) == 0x4242424242424242,
-			panic("Didn't reset __vcpu_sys_reg(%zi)", num);
+			 "Didn't reset __vcpu_sys_reg(%zi)\n", num))
+			break;
+	}
 }

arch/csky/include/asm/pgtable.h+7−2

 	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset_t(address))
 #define pmd_page(pmd)	(pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
 #define pte_clear(mm, addr, ptep)	set_pte((ptep), \
-			(((unsigned int)addr&0x80000000)?__pte(1):__pte(0)))
+	(((unsigned int) addr & PAGE_OFFSET) ? __pte(_PAGE_GLOBAL) : __pte(0)))
-#define pte_none(pte)	(!(pte_val(pte)&0xfffffffe))
+#define pte_none(pte)		(!(pte_val(pte) & ~_PAGE_GLOBAL))
 #define pte_present(pte)	(pte_val(pte) & _PAGE_PRESENT)
 #define pte_pfn(x)	((unsigned long)((x).pte_low >> PAGE_SHIFT))
 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) \
 #define pgd_index(address)	((address) >> PGDIR_SHIFT)
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+				     unsigned long size, pgprot_t vma_prot);
 /*
  * Macro to make mark a page protection value as "uncacheable".  Note
  * that "protection" is really a misnomer here as the protection value

arch/csky/include/asm/processor.h+2−2

@@ -49,7 +49,7 @@ struct thread_struct { · 48 unmodified lines
49	};	49	};
50		50
51	#define INIT_THREAD { \	51	#define INIT_THREAD { \
52	.ksp = (unsigned long) init_thread_union.stack + THREAD_SIZE, \	52	.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
53	.sr = DEFAULT_PSR_VALUE, \	53	.sr = DEFAULT_PSR_VALUE, \
54	}	54	}
55		55
@@ -95,7 +95,7 @@ unsigned long get_wchan(struct task_struct *p); · 39 unmodified lines
95	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->usp)	95	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->usp)
96		96
97	#define task_pt_regs(p) \	97	#define task_pt_regs(p) \
98	((struct pt_regs *)(THREAD_SIZE + p->stack) - 1)	98	((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
99		99
100	#define cpu_relax() barrier()	100	#define cpu_relax() barrier()
101		101

arch/csky/kernel/dumpstack.c+4−0

 		if (task)
 			stack = (unsigned long *)thread_saved_fp(task);
 		else
+#ifdef CONFIG_STACKTRACE
+			asm volatile("mov %0, r8\n":"=r"(stack)::"memory");
+#else
 			stack = (unsigned long *)&stack;
+#endif
 	}
 	show_trace(stack);

arch/csky/kernel/ptrace.c+2−1

 #include <linux/ptrace.h>
 #include <linux/regset.h>
 #include <linux/sched.h>
+#include <linux/sched/task_stack.h>
 #include <linux/signal.h>
 #include <linux/smp.h>
 #include <linux/uaccess.h>
 static const struct user_regset csky_regsets[] = {
 	[REGSET_GPR] = {
 		.core_note_type = NT_PRSTATUS,
-		.n = ELF_NGREG,
+		.n = sizeof(struct pt_regs) / sizeof(u32),
 		.size = sizeof(u32),
 		.align = sizeof(u32),
 		.get = &gpr_get,

arch/csky/kernel/smp.c+2−1

@@ -160,7 +160,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle) · 159 unmodified lines
160	{	160	{
161	unsigned long mask = 1 << cpu;	161	unsigned long mask = 1 << cpu;
162		162
163	secondary_stack = (unsigned int)tidle->stack + THREAD_SIZE - 8;	163	secondary_stack =
		164	(unsigned int) task_stack_page(tidle) + THREAD_SIZE - 8;
164	secondary_hint = mfcr("cr31");	165	secondary_hint = mfcr("cr31");
165	secondary_ccr = mfcr("cr18");	166	secondary_ccr = mfcr("cr18");
166		167

arch/csky/mm/ioremap.c+14−0

@@ -46,3 +46,17 @@ void iounmap(void __iomem *addr) · 45 unmodified lines
46	vunmap((void *)((unsigned long)addr & PAGE_MASK));	46	vunmap((void *)((unsigned long)addr & PAGE_MASK));
47	}	47	}
48	EXPORT_SYMBOL(iounmap);	48	EXPORT_SYMBOL(iounmap);
		49
		50	pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
		51	unsigned long size, pgprot_t vma_prot)
		52	{
		53	if (!pfn_valid(pfn)) {
		54	vma_prot.pgprot \|= _PAGE_SO;
		55	return pgprot_noncached(vma_prot);
		56	} else if (file->f_flags & O_SYNC) {
		57	return pgprot_noncached(vma_prot);
		58	}
		59
		60	return vma_prot;
		61	}
		62	EXPORT_SYMBOL(phys_mem_access_prot);

arch/mips/net/ebpf_jit.c+12−12

 	REG_64BIT_32BIT,
 	/* 32-bit compatible, need truncation for 64-bit ops. */
 	REG_32BIT,
-	/* 32-bit zero extended. */
-	REG_32BIT_ZERO_EX,
 	/* 32-bit no sign/zero extension needed. */
 	REG_32BIT_POS
 };
 	const struct bpf_prog *prog = ctx->skf;
 	int stack_adjust = ctx->stack_size;
 	int store_offset = stack_adjust - 8;
+	enum reg_val_type td;
 	int r0 = MIPS_R_V0;
-	if (dest_reg == MIPS_R_RA &&
+	if (dest_reg == MIPS_R_RA) {
-	    get_reg_val_type(ctx, prog->len, BPF_REG_0) == REG_32BIT_ZERO_EX)
 		/* Don't let zero extended value escape. */
-		emit_instr(ctx, sll, r0, r0, 0);
+		td = get_reg_val_type(ctx, prog->len, BPF_REG_0);
+		if (td == REG_64BIT)
+			emit_instr(ctx, sll, r0, r0, 0);
+	}
 	if (ctx->flags & EBPF_SAVE_RA) {
 		emit_instr(ctx, ld, MIPS_R_RA, store_offset, MIPS_R_SP);
 		if (dst < 0)
 			return dst;
 		td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
-		if (td == REG_64BIT || td == REG_32BIT_ZERO_EX) {
+		if (td == REG_64BIT) {
 			/* sign extend */
 			emit_instr(ctx, sll, dst, dst, 0);
 		}
 		if (dst < 0)
 			return dst;
 		td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
-		if (td == REG_64BIT || td == REG_32BIT_ZERO_EX) {
+		if (td == REG_64BIT) {
 			/* sign extend */
 			emit_instr(ctx, sll, dst, dst, 0);
 		}
 		if (dst < 0)
 			return dst;
 		td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
-		if (td == REG_64BIT || td == REG_32BIT_ZERO_EX)
+		if (td == REG_64BIT)
 			/* sign extend */
 			emit_instr(ctx, sll, dst, dst, 0);
 		if (insn->imm == 1) {
 		if (src < 0 || dst < 0)
 			return -EINVAL;
 		td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
-		if (td == REG_64BIT || td == REG_32BIT_ZERO_EX) {
+		if (td == REG_64BIT) {
 			/* sign extend */
 			emit_instr(ctx, sll, dst, dst, 0);
 		}
 		did_move = false;
 		ts = get_reg_val_type(ctx, this_idx, insn->src_reg);
-		if (ts == REG_64BIT || ts == REG_32BIT_ZERO_EX) {
+		if (ts == REG_64BIT) {
 			int tmp_reg = MIPS_R_AT;
 			if (bpf_op == BPF_MOV) {
 		if (insn->imm == 64 && td == REG_32BIT)
 			emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
-		if (insn->imm != 64 &&
+		if (insn->imm != 64 && td == REG_64BIT) {
-		    (td == REG_64BIT || td == REG_32BIT_ZERO_EX)) {
 			/* sign extend */
 			emit_instr(ctx, sll, dst, dst, 0);
 		}

arch/powerpc/include/asm/book3s/64/pgtable.h+2−2

@@ -904,7 +904,7 @@ static inline int pud_none(pud_t pud) · 903 unmodified lines
904		904
905	static inline int pud_present(pud_t pud)	905	static inline int pud_present(pud_t pud)
906	{	906	{
907	return (pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));	907	return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
908	}	908	}
909		909
910	extern struct page *pud_page(pud_t pud);	910	extern struct page *pud_page(pud_t pud);
@@ -951,7 +951,7 @@ static inline int pgd_none(pgd_t pgd) · 40 unmodified lines
951		951
952	static inline int pgd_present(pgd_t pgd)	952	static inline int pgd_present(pgd_t pgd)
953	{	953	{
954	return (pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));	954	return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));
955	}	955	}
956		956
957	static inline pte_t pgd_pte(pgd_t pgd)	957	static inline pte_t pgd_pte(pgd_t pgd)

arch/x86/events/core.c+14−0

@@ -2278,6 +2278,19 @@ void perf_check_microcode(void) · 2277 unmodified lines
2278	x86_pmu.check_microcode();	2278	x86_pmu.check_microcode();
2279	}	2279	}
2280		2280
		2281	static int x86_pmu_check_period(struct perf_event *event, u64 value)
		2282	{
		2283	if (x86_pmu.check_period && x86_pmu.check_period(event, value))
		2284	return -EINVAL;
		2285
		2286	if (value && x86_pmu.limit_period) {
		2287	if (x86_pmu.limit_period(event, value) > value)
		2288	return -EINVAL;
		2289	}
		2290
		2291	return 0;
		2292	}
		2293
2281	static struct pmu pmu = {	2294	static struct pmu pmu = {
2282	.pmu_enable = x86_pmu_enable,	2295	.pmu_enable = x86_pmu_enable,
2283	.pmu_disable = x86_pmu_disable,	2296	.pmu_disable = x86_pmu_disable,
@@ -2302,6 +2315,7 @@ static struct pmu pmu = { · 18 unmodified lines
2302	.event_idx = x86_pmu_event_idx,	2315	.event_idx = x86_pmu_event_idx,
2303	.sched_task = x86_pmu_sched_task,	2316	.sched_task = x86_pmu_sched_task,
2304	.task_ctx_size = sizeof(struct x86_perf_task_context),	2317	.task_ctx_size = sizeof(struct x86_perf_task_context),
		2318	.check_period = x86_pmu_check_period,
2305	};	2319	};
2306		2320
2307	void arch_perf_update_userpage(struct perf_event *event,	2321	void arch_perf_update_userpage(struct perf_event *event,

arch/x86/events/intel/core.c+9−0

 	intel_pmu_lbr_sched_task(ctx, sched_in);
 }
+static int intel_pmu_check_period(struct perf_event *event, u64 value)
+{
+	return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
+}
 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
 	.cpu_starting		= intel_pmu_cpu_starting,
 	.cpu_dying		= intel_pmu_cpu_dying,
 	.cpu_dead		= intel_pmu_cpu_dead,
+	.check_period		= intel_pmu_check_period,
 };
 static struct attribute *intel_pmu_attrs[];
 	.guest_get_msrs		= intel_guest_get_msrs,
 	.sched_task		= intel_pmu_sched_task,
+	.check_period		= intel_pmu_check_period,
 };
 static __init void intel_clovertown_quirk(void)

arch/x86/events/perf_event.h+14−2

 	 * Intel host/guest support (KVM)
 	 */
 	struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
+	/*
+	 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
+	 */
+	int (*check_period) (struct perf_event *event, u64 period);
 };
 struct x86_perf_task_context {
 #ifdef CONFIG_CPU_SUP_INTEL
-static inline bool intel_pmu_has_bts(struct perf_event *event)
+static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
 {
 	struct hw_perf_event *hwc = &event->hw;
 	unsigned int hw_event, bts_event;
 	hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
 	bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
-	return hw_event == bts_event && hwc->sample_period == 1;
+	return hw_event == bts_event && period == 1;
+}
+static inline bool intel_pmu_has_bts(struct perf_event *event)
+{
+	struct hw_perf_event *hwc = &event->hw;
+	return intel_pmu_has_bts_period(event, hwc->sample_period);
 }
 int intel_pmu_save_and_restart(struct perf_event *event);

arch/x86/ia32/ia32_aout.c+4−2

 /*
  * fill in the user structure for a core dump..
  */
-static void dump_thread32(struct pt_regs *regs, struct user32 *dump)
+static void fill_dump(struct pt_regs *regs, struct user32 *dump)
 {
 	u32 fs, gs;
 	memset(dump, 0, sizeof(*dump));
 	fs = get_fs();
 	set_fs(KERNEL_DS);
 	has_dumped = 1;
+	fill_dump(cprm->regs, &dump);
 	strncpy(dump.u_comm, current->comm, sizeof(current->comm));
 	dump.u_ar0 = offsetof(struct user32, regs);
 	dump.signal = cprm->siginfo->si_signo;
-	dump_thread32(cprm->regs, &dump);
 	/*
 	 * If the size of the dump file exceeds the rlimit, then see

arch/x86/include/asm/intel-family.h+2−0

@@ -52,6 +52,8 @@ · 51 unmodified lines
52		52
53	#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66	53	#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
54		54
		55	#define INTEL_FAM6_ICELAKE_MOBILE 0x7E
		56
55	/* "Small Core" Processors (Atom) */	57	/* "Small Core" Processors (Atom) */
56		58
57	#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */	59	#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */

arch/x86/include/asm/uv/bios.h+7−1

 	BIOS_STATUS_SUCCESS		=  0,
 	BIOS_STATUS_UNIMPLEMENTED	= -ENOSYS,
 	BIOS_STATUS_EINVAL		= -EINVAL,
-	BIOS_STATUS_UNAVAIL		= -EBUSY
+	BIOS_STATUS_UNAVAIL		= -EBUSY,
+	BIOS_STATUS_ABORT		= -EINTR,
 };
 /* Address map parameters */
 extern struct kobject *sgi_uv_kobj;	/* /sys/firmware/sgi_uv */
+/*
+ * EFI runtime lock; cf. firmware/efi/runtime-wrappers.c for details
+ */
+extern struct semaphore __efi_uv_runtime_lock;
 #endif /* _ASM_X86_UV_BIOS_H */

arch/x86/kvm/vmx/nested.c+9−3

 	    (nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id))
 		return -EINVAL;
+	if (!nested_cpu_has_preemption_timer(vmcs12) &&
+	    nested_cpu_has_save_preemption_timer(vmcs12))
+		return -EINVAL;
 	if (nested_cpu_has_ept(vmcs12) &&
 	    !valid_ept_address(vcpu, vmcs12->ept_pointer))
 		return -EINVAL;
 	 * secondary cpu-based controls.  Do not include those that
 	 * depend on CPUID bits, they are added later by vmx_cpuid_update.
 	 */
-	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
+	if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
-		msrs->secondary_ctls_low,
+		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
-		msrs->secondary_ctls_high);
+		      msrs->secondary_ctls_low,
+		      msrs->secondary_ctls_high);
 	msrs->secondary_ctls_low = 0;
 	msrs->secondary_ctls_high &=
 		SECONDARY_EXEC_DESC |

arch/x86/kvm/vmx/vmx.c+13−16

 	if (!entry_only)
 		j = find_msr(&m->host, msr);
-	if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
+	if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
+		(j < 0 &&  m->host.nr == NR_AUTOLOAD_MSRS)) {
 		printk_once(KERN_WARNING "Not enough msr switch entries. "
 				"Can't add msr %x\n", msr);
 		return;
 	if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
 		return;
-	/*
-	 * First handle the simple case where no cmpxchg is necessary; just
-	 * allow posting non-urgent interrupts.
-	 *
-	 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
-	 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
-	 * expects the VCPU to be on the blocked_vcpu_list that matches
-	 * PI.NDST.
-	 */
-	if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
-	    vcpu->cpu == cpu) {
-		pi_clear_sn(pi_desc);
-		return;
-	}
 	/* The full case.  */
 	do {
 		old.control = new.control = pi_desc->control;
 		new.sn = 0;
 	} while (cmpxchg64(&pi_desc->control, old.control,
 			   new.control) != old.control);
+	/*
+	 * Clear SN before reading the bitmap.  The VT-d firmware
+	 * writes the bitmap and reads SN atomically (5.2.3 in the
+	 * spec), so it doesn't really have a memory barrier that
+	 * pairs with this, but we cannot do that and we need one.
+	 */
+	smp_mb__after_atomic();
+	if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
+		pi_set_on(pi_desc);
 }
 /*

arch/x86/kvm/vmx/vmx.h+5−5

@@ -337,16 +337,16 @@ static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) · 336 unmodified lines
337	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);	337	return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
338	}	338	}
339		339
340	static inline void pi_clear_sn(struct pi_desc *pi_desc)	340	static inline void pi_set_sn(struct pi_desc *pi_desc)
341	{	341	{
342	return clear_bit(POSTED_INTR_SN,	342	return set_bit(POSTED_INTR_SN,
343	(unsigned long *)&pi_desc->control);	343	(unsigned long *)&pi_desc->control);
344	}	344	}
345		345
346	static inline void pi_set_sn(struct pi_desc *pi_desc)	346	static inline void pi_set_on(struct pi_desc *pi_desc)
347	{	347	{
348	return set_bit(POSTED_INTR_SN,	348	set_bit(POSTED_INTR_ON,
349	(unsigned long *)&pi_desc->control);	349	(unsigned long *)&pi_desc->control);
350	}	350	}
351		351
352	static inline void pi_clear_on(struct pi_desc *pi_desc)	352	static inline void pi_clear_on(struct pi_desc *pi_desc)

arch/x86/kvm/x86.c+1−1

@@ -7801,7 +7801,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) · 7800 unmodified lines
7801	* 1) We should set ->mode before checking ->requests. Please see	7801	* 1) We should set ->mode before checking ->requests. Please see
7802	* the comment in kvm_vcpu_exiting_guest_mode().	7802	* the comment in kvm_vcpu_exiting_guest_mode().
7803	*	7803	*
7804	* 2) For APICv, we should set ->mode before checking PIR.ON. This	7804	* 2) For APICv, we should set ->mode before checking PID.ON. This
7805	* pairs with the memory barrier implicit in pi_test_and_set_on	7805	* pairs with the memory barrier implicit in pi_test_and_set_on
7806	* (see vmx_deliver_posted_interrupt).	7806	* (see vmx_deliver_posted_interrupt).
7807	*	7807	*

arch/x86/platform/uv/bios_uv.c+21−2

 struct uv_systab *uv_systab;
-s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
+static s64 __uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3,
+			u64 a4, u64 a5)
 {
 	struct uv_systab *tab = uv_systab;
 	s64 ret;
 	return ret;
 }
+s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
+{
+	s64 ret;
+	if (down_interruptible(&__efi_uv_runtime_lock))
+		return BIOS_STATUS_ABORT;
+	ret = __uv_bios_call(which, a1, a2, a3, a4, a5);
+	up(&__efi_uv_runtime_lock);
+	return ret;
+}
 EXPORT_SYMBOL_GPL(uv_bios_call);
 s64 uv_bios_call_irqsave(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3,
 	unsigned long bios_flags;
 	s64 ret;
+	if (down_interruptible(&__efi_uv_runtime_lock))
+		return BIOS_STATUS_ABORT;
 	local_irq_save(bios_flags);
-	ret = uv_bios_call(which, a1, a2, a3, a4, a5);
+	ret = __uv_bios_call(which, a1, a2, a3, a4, a5);
 	local_irq_restore(bios_flags);
+	up(&__efi_uv_runtime_lock);
 	return ret;
 }

crypto/af_alg.c+3−1

 int af_alg_release(struct socket *sock)
 {
-	if (sock->sk)
+	if (sock->sk) {
 		sock_put(sock->sk);
+		sock->sk = NULL;
+	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(af_alg_release);

drivers/auxdisplay/ht16k33.c+1−1

@@ -509,7 +509,7 @@ static int ht16k33_remove(struct i2c_client *client) · 508 unmodified lines
509	struct ht16k33_priv *priv = i2c_get_clientdata(client);	509	struct ht16k33_priv *priv = i2c_get_clientdata(client);
510	struct ht16k33_fbdev *fbdev = &priv->fbdev;	510	struct ht16k33_fbdev *fbdev = &priv->fbdev;
511		511
512	cancel_delayed_work(&fbdev->work);	512	cancel_delayed_work_sync(&fbdev->work);
513	unregister_framebuffer(fbdev->info);	513	unregister_framebuffer(fbdev->info);
514	framebuffer_release(fbdev->info);	514	framebuffer_release(fbdev->info);
515	free_page((unsigned long) fbdev->buffer);	515	free_page((unsigned long) fbdev->buffer);

drivers/bus/ti-sysc.c+3−3

@@ -781,12 +781,12 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { · 780 unmodified lines
781	SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,	781	SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
782	SYSC_QUIRK_LEGACY_IDLE),	782	SYSC_QUIRK_LEGACY_IDLE),
783	SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,	783	SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
784	SYSC_QUIRK_LEGACY_IDLE),	784	0),
785	/* Some timers on omap4 and later */	785	/* Some timers on omap4 and later */
786	SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,	786	SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
787	SYSC_QUIRK_LEGACY_IDLE),	787	0),
788	SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,	788	SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
789	SYSC_QUIRK_LEGACY_IDLE),	789	0),
790	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,	790	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
791	SYSC_QUIRK_LEGACY_IDLE),	791	SYSC_QUIRK_LEGACY_IDLE),
792	/* Uarts on omap4 and later */	792	/* Uarts on omap4 and later */

drivers/clocksource/timer-ti-dm.c+4−1

 	if (IS_ERR(parent))
 		return -ENODEV;
+	/* Bail out if both clocks point to fck */
+	if (clk_is_match(parent, timer->fclk))
+		return 0;
 	ret = clk_set_parent(timer->fclk, parent);
 	if (ret < 0)
 		pr_err("%s: failed to set parent\n", __func__);
 	timer->pdev = pdev;
 	pm_runtime_enable(dev);
-	pm_runtime_irq_safe(dev);
 	if (!timer->reserved) {
 		ret = pm_runtime_get_sync(dev);

drivers/firmware/efi/efi.c+0−4

 		early_memunmap(tbl, sizeof(*tbl));
 	}
-	return 0;
-}
-int __init efi_apply_persistent_mem_reservations(void)
-{
 	if (efi.mem_reserve != EFI_INVALID_TABLE_ADDR) {
 		unsigned long prsv = efi.mem_reserve;

drivers/firmware/efi/libstub/arm-stub.c+0−3

@@ -75,9 +75,6 @@ void install_memreserve_table(efi_system_table_t *sys_table_arg) · 74 unmodified lines
75	efi_guid_t memreserve_table_guid = LINUX_EFI_MEMRESERVE_TABLE_GUID;	75	efi_guid_t memreserve_table_guid = LINUX_EFI_MEMRESERVE_TABLE_GUID;
76	efi_status_t status;	76	efi_status_t status;
77		77
78	if (IS_ENABLED(CONFIG_ARM))
79	return;
80
81	status = efi_call_early(allocate_pool, EFI_LOADER_DATA, sizeof(*rsv),	78	status = efi_call_early(allocate_pool, EFI_LOADER_DATA, sizeof(*rsv),
82	(void **)&rsv);	79	(void **)&rsv);
83	if (status != EFI_SUCCESS) {	80	if (status != EFI_SUCCESS) {

drivers/firmware/efi/runtime-wrappers.c+7−0

@@ -146,6 +146,13 @@ void efi_call_virt_check_flags(unsigned long flags, const char *call) · 145 unmodified lines
146	*/	146	*/
147	static DEFINE_SEMAPHORE(efi_runtime_lock);	147	static DEFINE_SEMAPHORE(efi_runtime_lock);
148		148
		149	/*
		150	* Expose the EFI runtime lock to the UV platform
		151	*/
		152	#ifdef CONFIG_X86_UV
		153	extern struct semaphore __efi_uv_runtime_lock __alias(efi_runtime_lock);
		154	#endif
		155
149	/*	156	/*
150	* Calls the appropriate efi_runtime_service() with the appropriate	157	* Calls the appropriate efi_runtime_service() with the appropriate
151	* arguments.	158	* arguments.

drivers/i2c/busses/i2c-bcm2835.c+12−0

 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
 }
+static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)
+{
+	i2c_dev->curr_msg = NULL;
+	i2c_dev->num_msgs = 0;
+	i2c_dev->msg_buf = NULL;
+	i2c_dev->msg_buf_remaining = 0;
+}
 /*
  * Note about I2C_C_CLEAR on error:
  * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
 	time_left = wait_for_completion_timeout(&i2c_dev->completion,
 						adap->timeout);
+	bcm2835_i2c_finish_transfer(i2c_dev);
 	if (!time_left) {
 		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
 				   BCM2835_I2C_C_CLEAR);

drivers/i2c/busses/i2c-cadence.c+7−2

 	 * Check for the message size against FIFO depth and set the
 	 * 'hold bus' bit if it is greater than FIFO depth.
 	 */
-	if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
+	if ((id->recv_count > CDNS_I2C_FIFO_DEPTH)  || id->bus_hold_flag)
 		ctrl_reg |= CDNS_I2C_CR_HOLD;
+	else
+		ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD;
 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 	 * Check for the message size against FIFO depth and set the
 	 * 'hold bus' bit if it is greater than FIFO depth.
 	 */
-	if (id->send_count > CDNS_I2C_FIFO_DEPTH)
+	if ((id->send_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag)
 		ctrl_reg |= CDNS_I2C_CR_HOLD;
+	else
+		ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD;
 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 	/* Clear the interrupts in interrupt status register. */

drivers/input/keyboard/Kconfig+1−1

@@ -420,7 +420,7 @@ config KEYBOARD_MPR121 · 419 unmodified lines
420		420
421	config KEYBOARD_SNVS_PWRKEY	421	config KEYBOARD_SNVS_PWRKEY
422	tristate "IMX SNVS Power Key Driver"	422	tristate "IMX SNVS Power Key Driver"
423	depends on SOC_IMX6SX	423	depends on SOC_IMX6SX \|\| SOC_IMX7D
424	depends on OF	424	depends on OF
425	help	425	help
426	This is the snvs powerkey driver for the Freescale i.MX application	426	This is the snvs powerkey driver for the Freescale i.MX application

drivers/input/keyboard/cap11xx.c+11−24

@@ -75,9 +75,7 @@ · 74 unmodified lines
75	struct cap11xx_led {	75	struct cap11xx_led {
76	struct cap11xx_priv *priv;	76	struct cap11xx_priv *priv;
77	struct led_classdev cdev;	77	struct led_classdev cdev;
78	struct work_struct work;
79	u32 reg;	78	u32 reg;
80	enum led_brightness new_brightness;
81	};	79	};
82	#endif	80	#endif
83		81
@@ -233,30 +231,21 @@ static void cap11xx_input_close(struct input_dev *idev) · 149 unmodified lines
233	}	231	}
234		232
235	#ifdef CONFIG_LEDS_CLASS	233	#ifdef CONFIG_LEDS_CLASS
236	static void cap11xx_led_work(struct work_struct *work)	234	static int cap11xx_led_set(struct led_classdev *cdev,
		235	enum led_brightness value)
237	{	236	{
238	struct cap11xx_led *led = container_of(work, struct cap11xx_led, work);	237	struct cap11xx_led *led = container_of(cdev, struct cap11xx_led, cdev);
239	struct cap11xx_priv *priv = led->priv;	238	struct cap11xx_priv *priv = led->priv;
240	int value = led->new_brightness;
241		239
242	/*	240	/*
243	* All LEDs share the same duty cycle as this is a HW limitation.	241	* All LEDs share the same duty cycle as this is a HW
244	* Brightness levels per LED are either 0 (OFF) and 1 (ON).	242	* limitation. Brightness levels per LED are either
		243	* 0 (OFF) and 1 (ON).
245	*/	244	*/
246	regmap_update_bits(priv->regmap, CAP11XX_REG_LED_OUTPUT_CONTROL,	245	return regmap_update_bits(priv->regmap,
247	BIT(led->reg), value ? BIT(led->reg) : 0);	246	CAP11XX_REG_LED_OUTPUT_CONTROL,
248	}	247	BIT(led->reg),
249		248	value ? BIT(led->reg) : 0);
250	static void cap11xx_led_set(struct led_classdev *cdev,
251	enum led_brightness value)
252	{
253	struct cap11xx_led *led = container_of(cdev, struct cap11xx_led, cdev);
254
255	if (led->new_brightness == value)
256	return;
257
258	led->new_brightness = value;
259	schedule_work(&led->work);
260	}	249	}
261		250
262	static int cap11xx_init_leds(struct device *dev,	251	static int cap11xx_init_leds(struct device *dev,
@@ -299,7 +288,7 @@ static int cap11xx_init_leds(struct device *dev, · 36 unmodified lines
299	led->cdev.default_trigger =	288	led->cdev.default_trigger =
300	of_get_property(child, "linux,default-trigger", NULL);	289	of_get_property(child, "linux,default-trigger", NULL);
301	led->cdev.flags = 0;	290	led->cdev.flags = 0;
302	led->cdev.brightness_set = cap11xx_led_set;	291	led->cdev.brightness_set_blocking = cap11xx_led_set;
303	led->cdev.max_brightness = 1;	292	led->cdev.max_brightness = 1;
304	led->cdev.brightness = LED_OFF;	293	led->cdev.brightness = LED_OFF;
305		294
@@ -312,8 +301,6 @@ static int cap11xx_init_leds(struct device *dev, · 6 unmodified lines
312	led->reg = reg;	301	led->reg = reg;
313	led->priv = priv;	302	led->priv = priv;
314		303
315	INIT_WORK(&led->work, cap11xx_led_work);
316
317	error = devm_led_classdev_register(dev, &led->cdev);	304	error = devm_led_classdev_register(dev, &led->cdev);
318	if (error) {	305	if (error) {
319	of_node_put(child);	306	of_node_put(child);

drivers/input/keyboard/matrix_keypad.c+1−1

@@ -222,7 +222,7 @@ static void matrix_keypad_stop(struct input_dev *dev) · 221 unmodified lines
222	keypad->stopped = true;	222	keypad->stopped = true;
223	spin_unlock_irq(&keypad->lock);	223	spin_unlock_irq(&keypad->lock);
224		224
225	flush_work(&keypad->work.work);	225	flush_delayed_work(&keypad->work);
226	/*	226	/*
227	* matrix_keypad_scan() will leave IRQs enabled;	227	* matrix_keypad_scan() will leave IRQs enabled;
228	* we should disable them now.	228	* we should disable them now.

drivers/input/keyboard/qt2160.c+27−42

@@ -58,10 +58,9 @@ static unsigned char qt2160_key2code[] = { · 57 unmodified lines
58	struct qt2160_led {	58	struct qt2160_led {
59	struct qt2160_data *qt2160;	59	struct qt2160_data *qt2160;
60	struct led_classdev cdev;	60	struct led_classdev cdev;
61	struct work_struct work;
62	char name[32];	61	char name[32];
63	int id;	62	int id;
64	enum led_brightness new_brightness;	63	enum led_brightness brightness;
65	};	64	};
66	#endif	65	#endif
67		66
@@ -74,7 +73,6 @@ struct qt2160_data { · 6 unmodified lines
74	u16 key_matrix;	73	u16 key_matrix;
75	#ifdef CONFIG_LEDS_CLASS	74	#ifdef CONFIG_LEDS_CLASS
76	struct qt2160_led leds[QT2160_NUM_LEDS_X];	75	struct qt2160_led leds[QT2160_NUM_LEDS_X];
77	struct mutex led_lock;
78	#endif	76	#endif
79	};	77	};
80		78
@@ -83,46 +81,39 @@ static int qt2160_write(struct i2c_client *client, u8 reg, u8 data); · 2 unmodified lines
83		81
84	#ifdef CONFIG_LEDS_CLASS	82	#ifdef CONFIG_LEDS_CLASS
85		83
86	static void qt2160_led_work(struct work_struct *work)	84	static int qt2160_led_set(struct led_classdev *cdev,
		85	enum led_brightness value)
87	{	86	{
88	struct qt2160_led *led = container_of(work, struct qt2160_led, work);	87	struct qt2160_led *led = container_of(cdev, struct qt2160_led, cdev);
89	struct qt2160_data *qt2160 = led->qt2160;	88	struct qt2160_data *qt2160 = led->qt2160;
90	struct i2c_client *client = qt2160->client;	89	struct i2c_client *client = qt2160->client;
91	int value = led->new_brightness;
92	u32 drive, pwmen;	90	u32 drive, pwmen;
93		91
94	mutex_lock(&qt2160->led_lock);	92	if (value != led->brightness) {
95		93	drive = qt2160_read(client, QT2160_CMD_DRIVE_X);
96	drive = qt2160_read(client, QT2160_CMD_DRIVE_X);	94	pwmen = qt2160_read(client, QT2160_CMD_PWMEN_X);
97	pwmen = qt2160_read(client, QT2160_CMD_PWMEN_X);	95	if (value != LED_OFF) {
98	if (value != LED_OFF) {	96	drive \|= BIT(led->id);
99	drive \|= (1 << led->id);	97	pwmen \|= BIT(led->id);
100	pwmen \|= (1 << led->id);
101
102	} else {
103	drive &= ~(1 << led->id);
104	pwmen &= ~(1 << led->id);
105	}
106	qt2160_write(client, QT2160_CMD_DRIVE_X, drive);
107	qt2160_write(client, QT2160_CMD_PWMEN_X, pwmen);
108		98
109	/*	99	} else {
110	* Changing this register will change the brightness	100	drive &= ~BIT(led->id);
111	* of every LED in the qt2160. It's a HW limitation.	101	pwmen &= ~BIT(led->id);
112	*/	102	}
113	if (value != LED_OFF)	103	qt2160_write(client, QT2160_CMD_DRIVE_X, drive);
114	qt2160_write(client, QT2160_CMD_PWM_DUTY, value);	104	qt2160_write(client, QT2160_CMD_PWMEN_X, pwmen);
115		105
116	mutex_unlock(&qt2160->led_lock);	106	/*
117	}	107	* Changing this register will change the brightness
		108	* of every LED in the qt2160. It's a HW limitation.
		109	*/
		110	if (value != LED_OFF)
		111	qt2160_write(client, QT2160_CMD_PWM_DUTY, value);
118		112
119	static void qt2160_led_set(struct led_classdev *cdev,	113	led->brightness = value;
120	enum led_brightness value)	114	}
121	{
122	struct qt2160_led *led = container_of(cdev, struct qt2160_led, cdev);
123		115
124	led->new_brightness = value;	116	return 0;
125	schedule_work(&led->work);
126	}	117	}
127		118
128	#endif /* CONFIG_LEDS_CLASS */	119	#endif /* CONFIG_LEDS_CLASS */
@@ -293,20 +284,16 @@ static int qt2160_register_leds(struct qt2160_data *qt2160) · 164 unmodified lines
293	int ret;	284	int ret;
294	int i;	285	int i;
295		286
296	mutex_init(&qt2160->led_lock);
297
298	for (i = 0; i < QT2160_NUM_LEDS_X; i++) {	287	for (i = 0; i < QT2160_NUM_LEDS_X; i++) {
299	struct qt2160_led *led = &qt2160->leds[i];	288	struct qt2160_led *led = &qt2160->leds[i];
300		289
301	snprintf(led->name, sizeof(led->name), "qt2160:x%d", i);	290	snprintf(led->name, sizeof(led->name), "qt2160:x%d", i);
302	led->cdev.name = led->name;	291	led->cdev.name = led->name;
303	led->cdev.brightness_set = qt2160_led_set;	292	led->cdev.brightness_set_blocking = qt2160_led_set;
304	led->cdev.brightness = LED_OFF;	293	led->cdev.brightness = LED_OFF;
305	led->id = i;	294	led->id = i;
306	led->qt2160 = qt2160;	295	led->qt2160 = qt2160;
307		296
308	INIT_WORK(&led->work, qt2160_led_work);
309
310	ret = led_classdev_register(&client->dev, &led->cdev);	297	ret = led_classdev_register(&client->dev, &led->cdev);
311	if (ret < 0)	298	if (ret < 0)
312	return ret;	299	return ret;
@@ -324,10 +311,8 @@ static void qt2160_unregister_leds(struct qt2160_data *qt2160) · 11 unmodified lines
324	{	311	{
325	int i;	312	int i;
326		313
327	for (i = 0; i < QT2160_NUM_LEDS_X; i++) {	314	for (i = 0; i < QT2160_NUM_LEDS_X; i++)
328	led_classdev_unregister(&qt2160->leds[i].cdev);	315	led_classdev_unregister(&qt2160->leds[i].cdev);
329	cancel_work_sync(&qt2160->leds[i].work);
330	}
331	}	316	}
332		317
333	#else	318	#else

drivers/input/keyboard/st-keyscan.c+2−2

 	input_dev->id.bustype = BUS_HOST;
+	keypad_data->input_dev = input_dev;
 	error = keypad_matrix_key_parse_dt(keypad_data);
 	if (error)
 		return error;
 	input_set_drvdata(input_dev, keypad_data);
-	keypad_data->input_dev = input_dev;
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	keypad_data->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(keypad_data->base))

drivers/input/misc/apanel.c+4−20

 #include <linux/io.h>
 #include <linux/input-polldev.h>
 #include <linux/i2c.h>
-#include <linux/workqueue.h>
 #include <linux/leds.h>
 #define APANEL_NAME	"Fujitsu Application Panel"
 	struct i2c_client *client;
 	unsigned short keymap[MAX_PANEL_KEYS];
 	u16    nkeys;
-	u16    led_bits;
-	struct work_struct led_work;
 	struct led_classdev mail_led;
 };
 			report_key(idev, ap->keymap[i]);
 }
-/* Track state changes of LED */
+static int mail_led_set(struct led_classdev *led,
-static void led_update(struct work_struct *work)
-{
-	struct apanel *ap = container_of(work, struct apanel, led_work);
-	i2c_smbus_write_word_data(ap->client, 0x10, ap->led_bits);
-}
-static void mail_led_set(struct led_classdev *led,
 			 enum led_brightness value)
 {
 	struct apanel *ap = container_of(led, struct apanel, mail_led);
+	u16 led_bits = value != LED_OFF ? 0x8000 : 0x0000;
-	if (value != LED_OFF)
+	return i2c_smbus_write_word_data(ap->client, 0x10, led_bits);
-		ap->led_bits |= 0x8000;
-	else
-		ap->led_bits &= ~0x8000;
-	schedule_work(&ap->led_work);
 }
 static int apanel_remove(struct i2c_client *client)
 	},
 	.mail_led = {
 		.name = "mail:blue",
-		.brightness_set = mail_led_set,
+		.brightness_set_blocking = mail_led_set,
 	},
 };
 	if (err)
 		goto out3;
-	INIT_WORK(&ap->led_work, led_update);
 	if (device_chip[APANEL_DEV_LED] != CHIP_NONE) {
 		err = led_classdev_register(&client->dev, &ap->mail_led);
 		if (err)

drivers/input/misc/bma150.c+5−4

 	idev->close = bma150_irq_close;
 	input_set_drvdata(idev, bma150);
+	bma150->input = idev;
 	error = input_register_device(idev);
 	if (error) {
 		input_free_device(idev);
 		return error;
 	}
-	bma150->input = idev;
 	return 0;
 }
 	bma150_init_input_device(bma150, ipoll_dev->input);
+	bma150->input_polled = ipoll_dev;
+	bma150->input = ipoll_dev->input;
 	error = input_register_polled_device(ipoll_dev);
 	if (error) {
 		input_free_polled_device(ipoll_dev);
 		return error;
 	}
-	bma150->input_polled = ipoll_dev;
-	bma150->input = ipoll_dev->input;
 	return 0;
 }

drivers/input/misc/pwm-vibra.c+13−6

 	struct work_struct play_work;
 	u16 level;
 	u32 direction_duty_cycle;
+	bool vcc_on;
 };
 static int pwm_vibrator_start(struct pwm_vibrator *vibrator)
 	struct pwm_state state;
 	int err;
-	err = regulator_enable(vibrator->vcc);
+	if (!vibrator->vcc_on) {
-	if (err) {
+		err = regulator_enable(vibrator->vcc);
-		dev_err(pdev, "failed to enable regulator: %d", err);
+		if (err) {
-		return err;
+			dev_err(pdev, "failed to enable regulator: %d", err);
+			return err;
+		}
+		vibrator->vcc_on = true;
 	}
 	pwm_get_state(vibrator->pwm, &state);
 static void pwm_vibrator_stop(struct pwm_vibrator *vibrator)
 {
-	regulator_disable(vibrator->vcc);
 	if (vibrator->pwm_dir)
 		pwm_disable(vibrator->pwm_dir);
 	pwm_disable(vibrator->pwm);
+	if (vibrator->vcc_on) {
+		regulator_disable(vibrator->vcc);
+		vibrator->vcc_on = false;
+	}
 }
 static void pwm_vibrator_play_work(struct work_struct *work)

drivers/input/mouse/elan_i2c_core.c+1−1

 static const struct acpi_device_id elan_acpi_id[] = {
 	{ "ELAN0000", 0 },
 	{ "ELAN0100", 0 },
-	{ "ELAN0501", 0 },
 	{ "ELAN0600", 0 },
 	{ "ELAN0602", 0 },
 	{ "ELAN0605", 0 },
 	{ "ELAN060C", 0 },
 	{ "ELAN0611", 0 },
 	{ "ELAN0612", 0 },
+	{ "ELAN0617", 0 },
 	{ "ELAN0618", 0 },
 	{ "ELAN061C", 0 },
 	{ "ELAN061D", 0 },

drivers/input/mouse/elantech.c+9−0

  * Asus UX31               0x361f00        20, 15, 0e      clickpad
  * Asus UX32VD             0x361f02        00, 15, 0e      clickpad
  * Avatar AVIU-145A2       0x361f00        ?               clickpad
+ * Fujitsu CELSIUS H760    0x570f02        40, 14, 0c      3 hw buttons (**)
+ * Fujitsu CELSIUS H780    0x5d0f02        41, 16, 0d      3 hw buttons (**)
  * Fujitsu LIFEBOOK E544   0x470f00        d0, 12, 09      2 hw buttons
  * Fujitsu LIFEBOOK E546   0x470f00        50, 12, 09      2 hw buttons
  * Fujitsu LIFEBOOK E547   0x470f00        50, 12, 09      2 hw buttons
 			DMI_MATCH(DMI_PRODUCT_NAME, "CELSIUS H760"),
 		},
 	},
+	{
+		/* Fujitsu H780 also has a middle button */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "CELSIUS H780"),
+		},
+	},
 #endif
 	{ }
 };

drivers/input/serio/ps2-gpio.c+1−0

@@ -76,6 +76,7 @@ static void ps2_gpio_close(struct serio *serio) · 75 unmodified lines
76	{	76	{
77	struct ps2_gpio_data *drvdata = serio->port_data;	77	struct ps2_gpio_data *drvdata = serio->port_data;
78		78
		79	flush_delayed_work(&drvdata->tx_work);
79	disable_irq(drvdata->irq);	80	disable_irq(drvdata->irq);
80	}	81	}
81		82

drivers/mailbox/bcm-flexrm-mailbox.c+2−2

@@ -1396,9 +1396,9 @@ static void flexrm_shutdown(struct mbox_chan *chan) · 1395 unmodified lines
1396		1396
1397	/* Clear ring flush state */	1397	/* Clear ring flush state */
1398	timeout = 1000; /* timeout of 1s */	1398	timeout = 1000; /* timeout of 1s */
1399	writel_relaxed(0x0, ring + RING_CONTROL);	1399	writel_relaxed(0x0, ring->regs + RING_CONTROL);
1400	do {	1400	do {
1401	if (!(readl_relaxed(ring + RING_FLUSH_DONE) &	1401	if (!(readl_relaxed(ring->regs + RING_FLUSH_DONE) &
1402	FLUSH_DONE_MASK))	1402	FLUSH_DONE_MASK))
1403	break;	1403	break;
1404	mdelay(1);	1404	mdelay(1);

drivers/mailbox/mailbox.c+1−0

@@ -310,6 +310,7 @@ int mbox_flush(struct mbox_chan *chan, unsigned long timeout) · 309 unmodified lines
310		310
311	return ret;	311	return ret;
312	}	312	}
		313	EXPORT_SYMBOL_GPL(mbox_flush);
313		314
314	/**	315	/**
315	* mbox_request_channel - Request a mailbox channel.	316	* mbox_request_channel - Request a mailbox channel.

drivers/net/dsa/b53/b53_common.c+71−19

 	b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 }
-static void b53_enable_vlan(struct b53_device *dev, bool enable)
+static void b53_enable_vlan(struct b53_device *dev, bool enable,
+			    bool enable_filtering)
 {
 	u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 		vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 		vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 		vc4 &= ~VC4_ING_VID_CHECK_MASK;
-		vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
+		if (enable_filtering) {
-		vc5 |= VC5_DROP_VTABLE_MISS;
+			vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
+			vc5 |= VC5_DROP_VTABLE_MISS;
+		} else {
+			vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
+			vc5 &= ~VC5_DROP_VTABLE_MISS;
+		}
 		if (is5325(dev))
 			vc0 &= ~VC0_RESERVED_1;
 	}
 	b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
+	dev->vlan_enabled = enable;
+	dev->vlan_filtering_enabled = enable_filtering;
 }
 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 	b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 }
+static u16 b53_default_pvid(struct b53_device *dev)
+{
+	if (is5325(dev) || is5365(dev))
+		return 1;
+	else
+		return 0;
+}
 int b53_configure_vlan(struct dsa_switch *ds)
 {
 	struct b53_device *dev = ds->priv;
 	struct b53_vlan vl = { 0 };
-	int i;
+	int i, def_vid;
+	def_vid = b53_default_pvid(dev);
 	/* clear all vlan entries */
 	if (is5325(dev) || is5365(dev)) {
-		for (i = 1; i < dev->num_vlans; i++)
+		for (i = def_vid; i < dev->num_vlans; i++)
 			b53_set_vlan_entry(dev, i, &vl);
 	} else {
 		b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 	}
-	b53_enable_vlan(dev, false);
+	b53_enable_vlan(dev, false, dev->vlan_filtering_enabled);
 	b53_for_each_port(dev, i)
 		b53_write16(dev, B53_VLAN_PAGE,
-			    B53_VLAN_PORT_DEF_TAG(i), 1);
+			    B53_VLAN_PORT_DEF_TAG(i), def_vid);
 	if (!is5325(dev) && !is5365(dev))
 		b53_set_jumbo(dev, dev->enable_jumbo, false);
 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
 {
+	struct b53_device *dev = ds->priv;
+	struct net_device *bridge_dev;
+	unsigned int i;
+	u16 pvid, new_pvid;
+	/* Handle the case were multiple bridges span the same switch device
+	 * and one of them has a different setting than what is being requested
+	 * which would be breaking filtering semantics for any of the other
+	 * bridge devices.
+	 */
+	b53_for_each_port(dev, i) {
+		bridge_dev = dsa_to_port(ds, i)->bridge_dev;
+		if (bridge_dev &&
+		    bridge_dev != dsa_to_port(ds, port)->bridge_dev &&
+		    br_vlan_enabled(bridge_dev) != vlan_filtering) {
+			netdev_err(bridge_dev,
+				   "VLAN filtering is global to the switch!\n");
+			return -EINVAL;
+		}
+	}
+	b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
+	new_pvid = pvid;
+	if (dev->vlan_filtering_enabled && !vlan_filtering) {
+		/* Filtering is currently enabled, use the default PVID since
+		 * the bridge does not expect tagging anymore
+		 */
+		dev->ports[port].pvid = pvid;
+		new_pvid = b53_default_pvid(dev);
+	} else if (!dev->vlan_filtering_enabled && vlan_filtering) {
+		/* Filtering is currently disabled, restore the previous PVID */
+		new_pvid = dev->ports[port].pvid;
+	}
+	if (pvid != new_pvid)
+		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
+			    new_pvid);
+	b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
 	return 0;
 }
 EXPORT_SYMBOL(b53_vlan_filtering);
 	if (vlan->vid_end > dev->num_vlans)
 		return -ERANGE;
-	b53_enable_vlan(dev, true);
+	b53_enable_vlan(dev, true, dev->vlan_filtering_enabled);
 	return 0;
 }
 		b53_fast_age_vlan(dev, vid);
 	}
-	if (pvid) {
+	if (pvid && !dsa_is_cpu_port(ds, port)) {
 		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
 			    vlan->vid_end);
 		b53_fast_age_vlan(dev, vid);
 		vl->members &= ~BIT(port);
-		if (pvid == vid) {
+		if (pvid == vid)
-			if (is5325(dev) || is5365(dev))
+			pvid = b53_default_pvid(dev);
-				pvid = 1;
-			else
-				pvid = 0;
-		}
 		if (untagged && !dsa_is_cpu_port(ds, port))
 			vl->untag &= ~(BIT(port));
 	b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 	dev->ports[port].vlan_ctl_mask = pvlan;
-	if (is5325(dev) || is5365(dev))
+	pvid = b53_default_pvid(dev);
-		pvid = 1;
-	else
-		pvid = 0;
 	/* Make this port join all VLANs without VLAN entries */
 	if (is58xx(dev)) {

drivers/net/dsa/b53/b53_priv.h+3−0

 struct b53_port {
 	u16		vlan_ctl_mask;
 	struct ethtool_eee eee;
+	u16		pvid;
 };
 struct b53_vlan {
 	unsigned int num_vlans;
 	struct b53_vlan *vlans;
+	bool vlan_enabled;
+	bool vlan_filtering_enabled;
 	unsigned int num_ports;
 	struct b53_port *ports;
 };

drivers/net/dsa/bcm_sf2.c+6−4

 {
 	struct net_device *p = ds->ports[port].cpu_dp->master;
 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
-	struct ethtool_wolinfo pwol;
+	struct ethtool_wolinfo pwol = { };
 	/* Get the parent device WoL settings */
-	p->ethtool_ops->get_wol(p, &pwol);
+	if (p->ethtool_ops->get_wol)
+		p->ethtool_ops->get_wol(p, &pwol);
 	/* Advertise the parent device supported settings */
 	wol->supported = pwol.supported;
 	struct net_device *p = ds->ports[port].cpu_dp->master;
 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 	s8 cpu_port = ds->ports[port].cpu_dp->index;
-	struct ethtool_wolinfo pwol;
+	struct ethtool_wolinfo pwol =  { };
-	p->ethtool_ops->get_wol(p, &pwol);
+	if (p->ethtool_ops->get_wol)
+		p->ethtool_ops->get_wol(p, &pwol);
 	if (wol->wolopts & ~pwol.supported)
 		return -EINVAL;

drivers/net/ethernet/broadcom/bcmsysport.c+4−0

 	priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
 	reg = rxchk_readl(priv, RXCHK_CONTROL);
+	/* Clear L2 header checks, which would prevent BPDUs
+	 * from being received.
+	 */
+	reg &= ~RXCHK_L2_HDR_DIS;
 	if (priv->rx_chk_en)
 		reg |= RXCHK_EN;
 	else

drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c+3−0

@@ -3128,6 +3128,9 @@ int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset) · 3127 unmodified lines
3128	dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);	3128	dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
3129	dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);	3129	dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3130	}	3130	}
		3131
		3132	put_device(&pdev->dev);
		3133
3131	return 0;	3134	return 0;
3132	}	3135	}
3133	EXPORT_SYMBOL(hns_dsaf_roce_reset);	3136	EXPORT_SYMBOL(hns_dsaf_roce_reset);

drivers/net/ethernet/marvell/mv643xx_eth.c+6−1

 	ret = mv643xx_eth_shared_of_probe(pdev);
 	if (ret)
-		return ret;
+		goto err_put_clk;
 	pd = dev_get_platdata(&pdev->dev);
 	msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
 	infer_hw_params(msp);
 	return 0;
+err_put_clk:
+	if (!IS_ERR(msp->clk))
+		clk_disable_unprepare(msp->clk);
+	return ret;
 }
 static int mv643xx_eth_shared_remove(struct platform_device *pdev)

drivers/net/ethernet/marvell/sky2.c+1−1

@@ -5073,7 +5073,7 @@ static int sky2_probe(struct pci_dev pdev, const struct pci_device_id ent) · 5072 unmodified lines
5073	INIT_WORK(&hw->restart_work, sky2_restart);	5073	INIT_WORK(&hw->restart_work, sky2_restart);
5074		5074
5075	pci_set_drvdata(pdev, hw);	5075	pci_set_drvdata(pdev, hw);
5076	pdev->d3_delay = 200;	5076	pdev->d3_delay = 300;
5077		5077
5078	return 0;	5078	return 0;
5079		5079

drivers/net/ethernet/mellanox/mlx4/en_netdev.c+1−1

@@ -3360,7 +3360,7 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, · 3359 unmodified lines
3360	dev->addr_len = ETH_ALEN;	3360	dev->addr_len = ETH_ALEN;
3361	mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);	3361	mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
3362	if (!is_valid_ether_addr(dev->dev_addr)) {	3362	if (!is_valid_ether_addr(dev->dev_addr)) {
3363	en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",	3363	en_err(priv, "Port: %d, invalid mac burned: %pM, quitting\n",
3364	priv->port, dev->dev_addr);	3364	priv->port, dev->dev_addr);
3365	err = -EINVAL;	3365	err = -EINVAL;
3366	goto out;	3366	goto out;

drivers/net/ethernet/mellanox/mlxsw/spectrum.c+7−5

 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 		bool configure = false;
 		bool pfc = false;
+		u16 thres_cells;
+		u16 delay_cells;
 		bool lossy;
-		u16 thres;
 		for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
 			if (prio_tc[j] == i) {
 			continue;
 		lossy = !(pfc || pause_en);
-		thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
+		thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
-		delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
+		delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
-						  pause_en);
+							pfc, pause_en);
-		mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
+		mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres_cells + delay_cells,
+				     thres_cells, lossy);
 	}
 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);

drivers/net/ethernet/qlogic/qed/qed_iwarp.c+15−6

 	eth_hlen = ETH_HLEN + (vlan_valid ? sizeof(u32) : 0);
+	if (!ether_addr_equal(ethh->h_dest,
+			      p_hwfn->p_rdma_info->iwarp.mac_addr)) {
+		DP_VERBOSE(p_hwfn,
+			   QED_MSG_RDMA,
+			   "Got unexpected mac %pM instead of %pM\n",
+			   ethh->h_dest, p_hwfn->p_rdma_info->iwarp.mac_addr);
+		return -EINVAL;
+	}
 	ether_addr_copy(remote_mac_addr, ethh->h_source);
 	ether_addr_copy(local_mac_addr, ethh->h_dest);
 	struct qed_iwarp_info *iwarp_info;
 	struct qed_ll2_acquire_data data;
 	struct qed_ll2_cbs cbs;
-	u32 mpa_buff_size;
+	u32 buff_size;
 	u16 n_ooo_bufs;
 	int rc = 0;
 	int i;
 	memset(&data, 0, sizeof(data));
 	data.input.conn_type = QED_LL2_TYPE_IWARP;
-	data.input.mtu = QED_IWARP_MAX_SYN_PKT_SIZE;
+	data.input.mtu = params->max_mtu;
 	data.input.rx_num_desc = QED_IWARP_LL2_SYN_RX_SIZE;
 	data.input.tx_num_desc = QED_IWARP_LL2_SYN_TX_SIZE;
 	data.input.tx_max_bds_per_packet = 1;	/* will never be fragmented */
 		goto err;
 	}
+	buff_size = QED_IWARP_MAX_BUF_SIZE(params->max_mtu);
 	rc = qed_iwarp_ll2_alloc_buffers(p_hwfn,
 					 QED_IWARP_LL2_SYN_RX_SIZE,
-					 QED_IWARP_MAX_SYN_PKT_SIZE,
+					 buff_size,
 					 iwarp_info->ll2_syn_handle);
 	if (rc)
 		goto err;
 	if (rc)
 		goto err;
-	mpa_buff_size = QED_IWARP_MAX_BUF_SIZE(params->max_mtu);
 	rc = qed_iwarp_ll2_alloc_buffers(p_hwfn,
 					 data.input.rx_num_desc,
-					 mpa_buff_size,
+					 buff_size,
 					 iwarp_info->ll2_mpa_handle);
 	if (rc)
 		goto err;
 	iwarp_info->max_num_partial_fpdus = (u16)p_hwfn->p_rdma_info->num_qps;
-	iwarp_info->mpa_intermediate_buf = kzalloc(mpa_buff_size, GFP_KERNEL);
+	iwarp_info->mpa_intermediate_buf = kzalloc(buff_size, GFP_KERNEL);
 	if (!iwarp_info->mpa_intermediate_buf)
 		goto err;

drivers/net/ethernet/qlogic/qed/qed_iwarp.h+0−1

@@ -46,7 +46,6 @@ enum qed_iwarp_qp_state qed_roce2iwarp_state(enum qed_roce_qp_state state); · 45 unmodified lines
46		46
47	#define QED_IWARP_LL2_SYN_TX_SIZE (128)	47	#define QED_IWARP_LL2_SYN_TX_SIZE (128)
48	#define QED_IWARP_LL2_SYN_RX_SIZE (256)	48	#define QED_IWARP_LL2_SYN_RX_SIZE (256)
49	#define QED_IWARP_MAX_SYN_PKT_SIZE (128)
50		49
51	#define QED_IWARP_LL2_OOO_DEF_TX_SIZE (256)	50	#define QED_IWARP_LL2_OOO_DEF_TX_SIZE (256)
52	#define QED_IWARP_MAX_OOO (16)	51	#define QED_IWARP_MAX_OOO (16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c+6−3

 static int dwmac4_rx_check_timestamp(void *desc)
 {
 	struct dma_desc *p = (struct dma_desc *)desc;
+	unsigned int rdes0 = le32_to_cpu(p->des0);
+	unsigned int rdes1 = le32_to_cpu(p->des1);
+	unsigned int rdes3 = le32_to_cpu(p->des3);
 	u32 own, ctxt;
 	int ret = 1;
-	own = p->des3 & RDES3_OWN;
+	own = rdes3 & RDES3_OWN;
-	ctxt = ((p->des3 & RDES3_CONTEXT_DESCRIPTOR)
+	ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
 		>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
 	if (likely(!own && ctxt)) {
-		if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
+		if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
 			/* Corrupted value */
 			ret = -EINVAL;
 		else

drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c+12−10

 				     struct ethtool_eee *edata)
 {
 	struct stmmac_priv *priv = netdev_priv(dev);
+	int ret;
-	priv->eee_enabled = edata->eee_enabled;
+	if (!edata->eee_enabled) {
-	if (!priv->eee_enabled)
 		stmmac_disable_eee_mode(priv);
-	else {
+	} else {
 		/* We are asking for enabling the EEE but it is safe
 		 * to verify all by invoking the eee_init function.
 		 * In case of failure it will return an error.
 		 */
-		priv->eee_enabled = stmmac_eee_init(priv);
+		edata->eee_enabled = stmmac_eee_init(priv);
-		if (!priv->eee_enabled)
+		if (!edata->eee_enabled)
 			return -EOPNOTSUPP;
-		/* Do not change tx_lpi_timer in case of failure */
-		priv->tx_lpi_timer = edata->tx_lpi_timer;
 	}
-	return phy_ethtool_set_eee(dev->phydev, edata);
+	ret = phy_ethtool_set_eee(dev->phydev, edata);
+	if (ret)
+		return ret;
+	priv->eee_enabled = edata->eee_enabled;
+	priv->tx_lpi_timer = edata->tx_lpi_timer;
+	return 0;
 }
 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)

drivers/net/ethernet/ti/netcp_core.c+1−1

@@ -259,7 +259,7 @@ static int netcp_module_probe(struct netcp_device *netcp_device, · 258 unmodified lines
259	const char *name;	259	const char *name;
260	char node_name[32];	260	char node_name[32];
261		261
262	if (of_property_read_string(node, "label", &name) < 0) {	262	if (of_property_read_string(child, "label", &name) < 0) {
263	snprintf(node_name, sizeof(node_name), "%pOFn", child);	263	snprintf(node_name, sizeof(node_name), "%pOFn", child);
264	name = node_name;	264	name = node_name;
265	}	265	}

drivers/net/phy/xilinx_gmii2rgmii.c+4−1

 	u16 val = 0;
 	int err;
-	err = priv->phy_drv->read_status(phydev);
+	if (priv->phy_drv->read_status)
+		err = priv->phy_drv->read_status(phydev);
+	else
+		err = genphy_read_status(phydev);
 	if (err < 0)
 		return err;

drivers/net/usb/qmi_wwan.c+2−2

@@ -1201,8 +1201,8 @@ static const struct usb_device_id products[] = { · 1200 unmodified lines
1201	{QMI_FIXED_INTF(0x114f, 0x68a2, 8)}, /* Sierra Wireless MC7750 */	1201	{QMI_FIXED_INTF(0x114f, 0x68a2, 8)}, /* Sierra Wireless MC7750 */
1202	{QMI_FIXED_INTF(0x1199, 0x68a2, 8)}, /* Sierra Wireless MC7710 in QMI mode */	1202	{QMI_FIXED_INTF(0x1199, 0x68a2, 8)}, /* Sierra Wireless MC7710 in QMI mode */
1203	{QMI_FIXED_INTF(0x1199, 0x68a2, 19)}, /* Sierra Wireless MC7710 in QMI mode */	1203	{QMI_FIXED_INTF(0x1199, 0x68a2, 19)}, /* Sierra Wireless MC7710 in QMI mode */
1204	{QMI_FIXED_INTF(0x1199, 0x68c0, 8)}, /* Sierra Wireless MC7304/MC7354 */	1204	{QMI_QUIRK_SET_DTR(0x1199, 0x68c0, 8)}, /* Sierra Wireless MC7304/MC7354, WP76xx */
1205	{QMI_FIXED_INTF(0x1199, 0x68c0, 10)}, /* Sierra Wireless MC7304/MC7354 */	1205	{QMI_QUIRK_SET_DTR(0x1199, 0x68c0, 10)},/* Sierra Wireless MC7304/MC7354 */
1206	{QMI_FIXED_INTF(0x1199, 0x901c, 8)}, /* Sierra Wireless EM7700 */	1206	{QMI_FIXED_INTF(0x1199, 0x901c, 8)}, /* Sierra Wireless EM7700 */
1207	{QMI_FIXED_INTF(0x1199, 0x901f, 8)}, /* Sierra Wireless EM7355 */	1207	{QMI_FIXED_INTF(0x1199, 0x901f, 8)}, /* Sierra Wireless EM7355 */
1208	{QMI_FIXED_INTF(0x1199, 0x9041, 8)}, /* Sierra Wireless MC7305/MC7355 */	1208	{QMI_FIXED_INTF(0x1199, 0x9041, 8)}, /* Sierra Wireless MC7305/MC7355 */

drivers/net/usb/r8152.c+3−2

 /* MAC PASSTHRU */
 #define AD_MASK			0xfee0
 #define BND_MASK		0x0004
+#define BD_MASK			0x0001
 #define EFUSE			0xcfdb
 #define PASS_THRU_MASK		0x1
 			return -ENODEV;
 		}
 	} else {
-		/* test for RTL8153-BND */
+		/* test for RTL8153-BND and RTL8153-BD */
 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
-		if ((ocp_data & BND_MASK) == 0) {
+		if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK)) {
 			netif_dbg(tp, probe, tp->netdev,
 				  "Invalid variant for MAC pass through\n");
 			return -ENODEV;

drivers/net/wireless/mediatek/mt76/mt76x0/usb.c+29−17

@@ -158,39 +158,49 @@ static const struct ieee80211_ops mt76x0u_ops = { · 157 unmodified lines
158	.get_txpower = mt76_get_txpower,	158	.get_txpower = mt76_get_txpower,
159	};	159	};
160		160
161	static int mt76x0u_register_device(struct mt76x02_dev *dev)	161	static int mt76x0u_init_hardware(struct mt76x02_dev *dev)
162	{	162	{
163	struct ieee80211_hw *hw = dev->mt76.hw;
164	int err;	163	int err;
165		164
166	err = mt76u_alloc_queues(&dev->mt76);
167	if (err < 0)
168	goto out_err;
169
170	err = mt76u_mcu_init_rx(&dev->mt76);
171	if (err < 0)
172	goto out_err;
173
174	mt76x0_chip_onoff(dev, true, true);	165	mt76x0_chip_onoff(dev, true, true);
175	if (!mt76x02_wait_for_mac(&dev->mt76)) {	166
176	err = -ETIMEDOUT;	167	if (!mt76x02_wait_for_mac(&dev->mt76))
177	goto out_err;	168	return -ETIMEDOUT;
178	}
179		169
180	err = mt76x0u_mcu_init(dev);	170	err = mt76x0u_mcu_init(dev);
181	if (err < 0)	171	if (err < 0)
182	goto out_err;	172	return err;
183		173
184	mt76x0_init_usb_dma(dev);	174	mt76x0_init_usb_dma(dev);
185	err = mt76x0_init_hardware(dev);	175	err = mt76x0_init_hardware(dev);
186	if (err < 0)	176	if (err < 0)
187	goto out_err;	177	return err;
188		178
189	mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);	179	mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
190	mt76_wr(dev, MT_TXOP_CTRL_CFG,	180	mt76_wr(dev, MT_TXOP_CTRL_CFG,
191	FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) \|	181	FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) \|
192	FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58));	182	FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58));
193		183
		184	return 0;
		185	}
		186
		187	static int mt76x0u_register_device(struct mt76x02_dev *dev)
		188	{
		189	struct ieee80211_hw *hw = dev->mt76.hw;
		190	int err;
		191
		192	err = mt76u_alloc_queues(&dev->mt76);
		193	if (err < 0)
		194	goto out_err;
		195
		196	err = mt76u_mcu_init_rx(&dev->mt76);
		197	if (err < 0)
		198	goto out_err;
		199
		200	err = mt76x0u_init_hardware(dev);
		201	if (err < 0)
		202	goto out_err;
		203
194	err = mt76x0_register_device(dev);	204	err = mt76x0_register_device(dev);
195	if (err < 0)	205	if (err < 0)
196	goto out_err;	206	goto out_err;
@@ -301,6 +311,8 @@ static int __maybe_unused mt76x0_suspend(struct usb_interface *usb_intf, · 104 unmodified lines
301		311
302	mt76u_stop_queues(&dev->mt76);	312	mt76u_stop_queues(&dev->mt76);
303	mt76x0u_mac_stop(dev);	313	mt76x0u_mac_stop(dev);
		314	clear_bit(MT76_STATE_MCU_RUNNING, &dev->mt76.state);
		315	mt76x0_chip_onoff(dev, false, false);
304	usb_kill_urb(usb->mcu.res.urb);	316	usb_kill_urb(usb->mcu.res.urb);
305		317
306	return 0;	318	return 0;
@@ -328,7 +340,7 @@ static int __maybe_unused mt76x0_resume(struct usb_interface *usb_intf) · 21 unmodified lines
328	tasklet_enable(&usb->rx_tasklet);	340	tasklet_enable(&usb->rx_tasklet);
329	tasklet_enable(&usb->tx_tasklet);	341	tasklet_enable(&usb->tx_tasklet);
330		342
331	ret = mt76x0_init_hardware(dev);	343	ret = mt76x0u_init_hardware(dev);
332	if (ret)	344	if (ret)
333	goto err;	345	goto err;
334		346

drivers/scsi/qla2xxx/qla_init.c+2−2

@@ -1785,13 +1785,13 @@ qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, · 1784 unmodified lines
1785		1785
1786	/* Issue Marker IOCB */	1786	/* Issue Marker IOCB */
1787	qla2x00_marker(vha, vha->hw->req_q_map[0],	1787	qla2x00_marker(vha, vha->hw->req_q_map[0],
1788	vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,	1788	vha->hw->rsp_q_map[0], fcport->loop_id, lun,
1789	flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);	1789	flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1790	}	1790	}
1791		1791
1792	done_free_sp:	1792	done_free_sp:
1793	sp->free(sp);	1793	sp->free(sp);
1794	sp->fcport->flags &= ~FCF_ASYNC_SENT;	1794	fcport->flags &= ~FCF_ASYNC_SENT;
1795	done:	1795	done:
1796	return rval;	1796	return rval;
1797	}	1797	}

drivers/scsi/sd.c+9−3

 	if (rot == 1) {
 		blk_queue_flag_set(QUEUE_FLAG_NONROT, q);
 		blk_queue_flag_clear(QUEUE_FLAG_ADD_RANDOM, q);
-	} else {
-		blk_queue_flag_clear(QUEUE_FLAG_NONROT, q);
-		blk_queue_flag_set(QUEUE_FLAG_ADD_RANDOM, q);
 	}
 	if (sdkp->device->type == TYPE_ZBC) {
 	if (sdkp->media_present) {
 		sd_read_capacity(sdkp, buffer);
+		/*
+		 * set the default to rotational.  All non-rotational devices
+		 * support the block characteristics VPD page, which will
+		 * cause this to be updated correctly and any device which
+		 * doesn't support it should be treated as rotational.
+		 */
+		blk_queue_flag_clear(QUEUE_FLAG_NONROT, q);
+		blk_queue_flag_set(QUEUE_FLAG_ADD_RANDOM, q);
 		if (scsi_device_supports_vpd(sdp)) {
 			sd_read_block_provisioning(sdkp);
 			sd_read_block_limits(sdkp);

drivers/vhost/vhost.c+1−1

@@ -1788,7 +1788,7 @@ static int log_used(struct vhost_virtqueue *vq, u64 used_offset, u64 len) · 1787 unmodified lines
1788		1788
1789	ret = translate_desc(vq, (uintptr_t)vq->used + used_offset,	1789	ret = translate_desc(vq, (uintptr_t)vq->used + used_offset,
1790	len, iov, 64, VHOST_ACCESS_WO);	1790	len, iov, 64, VHOST_ACCESS_WO);
1791	if (ret)	1791	if (ret < 0)
1792	return ret;	1792	return ret;
1793		1793
1794	for (i = 0; i < ret; i++) {	1794	for (i = 0; i < ret; i++) {

fs/binfmt_script.c+48−9

@@ -14,13 +14,30 @@ · 13 unmodified lines
14	#include <linux/err.h>	14	#include <linux/err.h>
15	#include <linux/fs.h>	15	#include <linux/fs.h>
16		16
		17	static inline bool spacetab(char c) { return c == ' ' \|\| c == '\t'; }
		18	static inline char next_non_spacetab(char first, const char *last)
		19	{
		20	for (; first <= last; first++)
		21	if (!spacetab(*first))
		22	return first;
		23	return NULL;
		24	}
		25	static inline char next_terminator(char first, const char *last)
		26	{
		27	for (; first <= last; first++)
		28	if (spacetab(first) \|\| !first)
		29	return first;
		30	return NULL;
		31	}
		32
17	static int load_script(struct linux_binprm *bprm)	33	static int load_script(struct linux_binprm *bprm)
18	{	34	{
19	const char i_arg, i_name;	35	const char i_arg, i_name;
20	char *cp;	36	char cp, buf_end;
21	struct file *file;	37	struct file *file;
22	int retval;	38	int retval;
23		39
		40	/* Not ours to exec if we don't start with "#!". */
24	if ((bprm->buf[0] != '#') \|\| (bprm->buf[1] != '!'))	41	if ((bprm->buf[0] != '#') \|\| (bprm->buf[1] != '!'))
25	return -ENOEXEC;	42	return -ENOEXEC;
26		43
@@ -33,18 +50,40 @@ static int load_script(struct linux_binprm *bprm) · 6 unmodified lines
33	if (bprm->interp_flags & BINPRM_FLAGS_PATH_INACCESSIBLE)	50	if (bprm->interp_flags & BINPRM_FLAGS_PATH_INACCESSIBLE)
34	return -ENOENT;	51	return -ENOENT;
35		52
36	/*	53	/* Release since we are not mapping a binary into memory. */
37	* This section does the #! interpretation.
38	* Sorta complicated, but hopefully it will work. -TYT
39	*/
40
41	allow_write_access(bprm->file);	54	allow_write_access(bprm->file);
42	fput(bprm->file);	55	fput(bprm->file);
43	bprm->file = NULL;	56	bprm->file = NULL;
44		57
45	bprm->buf[BINPRM_BUF_SIZE - 1] = '\0';	58	/*
46	if ((cp = strchr(bprm->buf, '\n')) == NULL)	59	* This section handles parsing the #! line into separate
47	cp = bprm->buf+BINPRM_BUF_SIZE-1;	60	* interpreter path and argument strings. We must be careful
		61	* because bprm->buf is not yet guaranteed to be NUL-terminated
		62	* (though the buffer will have trailing NUL padding when the
		63	* file size was smaller than the buffer size).
		64	*
		65	* We do not want to exec a truncated interpreter path, so either
		66	* we find a newline (which indicates nothing is truncated), or
		67	* we find a space/tab/NUL after the interpreter path (which
		68	* itself may be preceded by spaces/tabs). Truncating the
		69	* arguments is fine: the interpreter can re-read the script to
		70	* parse them on its own.
		71	*/
		72	buf_end = bprm->buf + sizeof(bprm->buf) - 1;
		73	cp = strnchr(bprm->buf, sizeof(bprm->buf), '\n');
		74	if (!cp) {
		75	cp = next_non_spacetab(bprm->buf + 2, buf_end);
		76	if (!cp)
		77	return -ENOEXEC; /* Entire buf is spaces/tabs */
		78	/*
		79	* If there is no later space/tab/NUL we must assume the
		80	* interpreter path is truncated.
		81	*/
		82	if (!next_terminator(cp, buf_end))
		83	return -ENOEXEC;
		84	cp = buf_end;
		85	}
		86	/* NUL-terminate the buffer and any trailing spaces/tabs. */
48	*cp = '\0';	87	*cp = '\0';
49	while (cp > bprm->buf) {	88	while (cp > bprm->buf) {
50	cp--;	89	cp--;

fs/nfs/write.c+6−5

 }
 /* A writeback failed: mark the page as bad, and invalidate the page cache */
-static void nfs_set_pageerror(struct page *page)
+static void nfs_set_pageerror(struct address_space *mapping)
 {
-	nfs_zap_mapping(page_file_mapping(page)->host, page_file_mapping(page));
+	nfs_zap_mapping(mapping->host, mapping);
 }
 /*
 		nfs_list_remove_request(req);
 		if (test_bit(NFS_IOHDR_ERROR, &hdr->flags) &&
 		    (hdr->good_bytes < bytes)) {
-			nfs_set_pageerror(req->wb_page);
+			nfs_set_pageerror(page_file_mapping(req->wb_page));
 			nfs_context_set_write_error(req->wb_context, hdr->error);
 			goto remove_req;
 		}
 		unsigned int offset, unsigned int count)
 {
 	struct nfs_open_context *ctx = nfs_file_open_context(file);
-	struct inode	*inode = page_file_mapping(page)->host;
+	struct address_space *mapping = page_file_mapping(page);
+	struct inode	*inode = mapping->host;
 	int		status = 0;
 	nfs_inc_stats(inode, NFSIOS_VFSUPDATEPAGE);
 	status = nfs_writepage_setup(ctx, page, offset, count);
 	if (status < 0)
-		nfs_set_pageerror(page);
+		nfs_set_pageerror(mapping);
 	else
 		__set_page_dirty_nobuffers(page);
 out:

fs/nfsd/nfsctl.c+2−2

@@ -1239,8 +1239,8 @@ static __net_init int nfsd_init_net(struct net *net) · 1238 unmodified lines
1239	retval = nfsd_idmap_init(net);	1239	retval = nfsd_idmap_init(net);
1240	if (retval)	1240	if (retval)
1241	goto out_idmap_error;	1241	goto out_idmap_error;
1242	nn->nfsd4_lease = 45; /* default lease time */	1242	nn->nfsd4_lease = 90; /* default lease time */
1243	nn->nfsd4_grace = 45;	1243	nn->nfsd4_grace = 90;
1244	nn->somebody_reclaimed = false;	1244	nn->somebody_reclaimed = false;
1245	nn->clverifier_counter = prandom_u32();	1245	nn->clverifier_counter = prandom_u32();
1246	nn->clientid_counter = prandom_u32();	1246	nn->clientid_counter = prandom_u32();

include/kvm/arm_vgic.h+3−3

@@ -100,7 +100,7 @@ enum vgic_irq_config { · 99 unmodified lines
100	};	100	};
101		101
102	struct vgic_irq {	102	struct vgic_irq {
103	spinlock_t irq_lock; /* Protects the content of the struct */	103	raw_spinlock_t irq_lock; /* Protects the content of the struct */
104	struct list_head lpi_list; /* Used to link all LPIs together */	104	struct list_head lpi_list; /* Used to link all LPIs together */
105	struct list_head ap_list;	105	struct list_head ap_list;
106		106
@@ -256,7 +256,7 @@ struct vgic_dist { · 149 unmodified lines
256	u64 propbaser;	256	u64 propbaser;
257		257
258	/* Protects the lpi_list and the count value below. */	258	/* Protects the lpi_list and the count value below. */
259	spinlock_t lpi_list_lock;	259	raw_spinlock_t lpi_list_lock;
260	struct list_head lpi_list_head;	260	struct list_head lpi_list_head;
261	int lpi_list_count;	261	int lpi_list_count;
262		262
@@ -307,7 +307,7 @@ struct vgic_cpu { · 44 unmodified lines
307	unsigned int used_lrs;	307	unsigned int used_lrs;
308	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];	308	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
309		309
310	spinlock_t ap_list_lock; /* Protects the ap_list */	310	raw_spinlock_t ap_list_lock; /* Protects the ap_list */
311		311
312	/*	312	/*
313	* List of IRQs that this VCPU should consider because they are either	313	* List of IRQs that this VCPU should consider because they are either

include/linux/compiler_attributes.h+14−0

@@ -34,6 +34,7 @@ · 33 unmodified lines
34	#ifndef __has_attribute	34	#ifndef __has_attribute
35	# define __has_attribute(x) __GCC4_has_attribute_##x	35	# define __has_attribute(x) __GCC4_has_attribute_##x
36	# define __GCC4_has_attribute___assume_aligned__ (__GNUC_MINOR__ >= 9)	36	# define __GCC4_has_attribute___assume_aligned__ (__GNUC_MINOR__ >= 9)
		37	# define __GCC4_has_attribute___copy__ 0
37	# define __GCC4_has_attribute___designated_init__ 0	38	# define __GCC4_has_attribute___designated_init__ 0
38	# define __GCC4_has_attribute___externally_visible__ 1	39	# define __GCC4_has_attribute___externally_visible__ 1
39	# define __GCC4_has_attribute___noclone__ 1	40	# define __GCC4_has_attribute___noclone__ 1
@@ -100,6 +101,19 @@ · 60 unmodified lines
100	*/	101	*/
101	#define __attribute_const__ __attribute__((__const__))	102	#define __attribute_const__ __attribute__((__const__))
102		103
		104	/*
		105	* Optional: only supported since gcc >= 9
		106	* Optional: not supported by clang
		107	* Optional: not supported by icc
		108	*
		109	* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-copy-function-attribute
		110	*/
		111	#if __has_attribute(__copy__)
		112	# define __copy(symbol) __attribute__((__copy__(symbol)))
		113	#else
		114	# define __copy(symbol)
		115	#endif
		116
103	/*	117	/*
104	* Don't. Just don't. See commit 771c035372a0 ("deprecate the '__deprecated'	118	* Don't. Just don't. See commit 771c035372a0 ("deprecate the '__deprecated'
105	* attribute warnings entirely and for good") for more information.	119	* attribute warnings entirely and for good") for more information.

include/linux/efi.h+0−7

 extern void efi_reboot(enum reboot_mode reboot_mode, const char *__unused);
 extern bool efi_is_table_address(unsigned long phys_addr);
-extern int efi_apply_persistent_mem_reservations(void);
 #else
 static inline bool efi_enabled(int feature)
 {
 {
 	return false;
 }
-static inline int efi_apply_persistent_mem_reservations(void)
-{
-	return 0;
-}
 #endif
 extern int efi_status_to_err(efi_status_t status);

include/linux/memblock.h+0−3

@@ -29,9 +29,6 @@ extern unsigned long max_pfn; · 28 unmodified lines
29	*/	29	*/
30	extern unsigned long long max_possible_pfn;	30	extern unsigned long long max_possible_pfn;
31		31
32	#define INIT_MEMBLOCK_REGIONS 128
33	#define INIT_PHYSMEM_REGIONS 4
34
35	/**	32	/**
36	* enum memblock_flags - definition of memory region attributes	33	* enum memblock_flags - definition of memory region attributes
37	* @MEMBLOCK_NONE: no special request	34	* @MEMBLOCK_NONE: no special request

include/linux/module.h+2−2

@@ -129,13 +129,13 @@ extern void cleanup_module(void); · 128 unmodified lines
129	#define module_init(initfn) \	129	#define module_init(initfn) \
130	static inline initcall_t __maybe_unused __inittest(void) \	130	static inline initcall_t __maybe_unused __inittest(void) \
131	{ return initfn; } \	131	{ return initfn; } \
132	int init_module(void) __attribute__((alias(#initfn)));	132	int init_module(void) __copy(initfn) __attribute__((alias(#initfn)));
133		133
134	/* This is only required if you want to be unloadable. */	134	/* This is only required if you want to be unloadable. */
135	#define module_exit(exitfn) \	135	#define module_exit(exitfn) \
136	static inline exitcall_t __maybe_unused __exittest(void) \	136	static inline exitcall_t __maybe_unused __exittest(void) \
137	{ return exitfn; } \	137	{ return exitfn; } \
138	void cleanup_module(void) __attribute__((alias(#exitfn)));	138	void cleanup_module(void) __copy(exitfn) __attribute__((alias(#exitfn)));
139		139
140	#endif	140	#endif
141		141

include/linux/netdev_features.h+22−2

@@ -11,6 +11,8 @@ · 10 unmodified lines
11	#define _LINUX_NETDEV_FEATURES_H	11	#define _LINUX_NETDEV_FEATURES_H
12		12
13	#include <linux/types.h>	13	#include <linux/types.h>
		14	#include <linux/bitops.h>
		15	#include <asm/byteorder.h>
14		16
15	typedef u64 netdev_features_t;	17	typedef u64 netdev_features_t;
16		18
@@ -154,8 +156,26 @@ enum { · 137 unmodified lines
154	#define NETIF_F_HW_TLS_TX __NETIF_F(HW_TLS_TX)	156	#define NETIF_F_HW_TLS_TX __NETIF_F(HW_TLS_TX)
155	#define NETIF_F_HW_TLS_RX __NETIF_F(HW_TLS_RX)	157	#define NETIF_F_HW_TLS_RX __NETIF_F(HW_TLS_RX)
156		158
157	#define for_each_netdev_feature(mask_addr, bit) \	159	/* Finds the next feature with the highest number of the range of start till 0.
158	for_each_set_bit(bit, (unsigned long *)mask_addr, NETDEV_FEATURE_COUNT)	160	*/
		161	static inline int find_next_netdev_feature(u64 feature, unsigned long start)
		162	{
		163	/* like BITMAP_LAST_WORD_MASK() for u64
		164	* this sets the most significant 64 - start to 0.
		165	*/
		166	feature &= ~0ULL >> (-start & ((sizeof(feature) * 8) - 1));
		167
		168	return fls64(feature) - 1;
		169	}
		170
		171	/* This goes for the MSB to the LSB through the set feature bits,
		172	* mask_addr should be a u64 and bit an int
		173	*/
		174	#define for_each_netdev_feature(mask_addr, bit) \
		175	for ((bit) = find_next_netdev_feature((mask_addr), \
		176	NETDEV_FEATURE_COUNT); \
		177	(bit) >= 0; \
		178	(bit) = find_next_netdev_feature((mask_addr), (bit) - 1))
159		179
160	/* Features valid for ethtool to change */	180	/* Features valid for ethtool to change */
161	/* = all defined minus driver/device-class-related */	181	/* = all defined minus driver/device-class-related */

include/linux/perf_event.h+5−0

 	 * Filter events for PMU-specific reasons.
 	 */
 	int (*filter_match)		(struct perf_event *event); /* optional */
+	/*
+	 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
+	 */
+	int (*check_period)		(struct perf_event *event, u64 value); /* optional */
 };
 enum perf_addr_filter_action_t {

include/linux/skbuff.h+7−1

 	if (skb_flow_dissect_flow_keys_basic(skb, &keys, NULL, 0, 0, 0, 0))
 		skb_set_transport_header(skb, keys.control.thoff);
-	else
+	else if (offset_hint >= 0)
 		skb_set_transport_header(skb, offset_hint);
 }
 	return skb_shinfo(skb)->gso_type & SKB_GSO_SCTP;
 }
+static inline bool skb_is_gso_tcp(const struct sk_buff *skb)
+{
+	return skb_is_gso(skb) &&
+	       skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6);
+}
 static inline void skb_gso_reset(struct sk_buff *skb)
 {
 	skb_shinfo(skb)->gso_size = 0;

include/linux/virtio_net.h+9−0

@@ -57,6 +57,15 @@ static inline int virtio_net_hdr_to_skb(struct sk_buff *skb, · 56 unmodified lines
57		57
58	if (!skb_partial_csum_set(skb, start, off))	58	if (!skb_partial_csum_set(skb, start, off))
59	return -EINVAL;	59	return -EINVAL;
		60	} else {
		61	/* gso packets without NEEDS_CSUM do not set transport_offset.
		62	* probe and drop if does not match one of the above types.
		63	*/
		64	if (gso_type) {
		65	skb_probe_transport_header(skb, -1);
		66	if (!skb_transport_header_was_set(skb))
		67	return -EINVAL;
		68	}
60	}	69	}
61		70
62	if (hdr->gso_type != VIRTIO_NET_HDR_GSO_NONE) {	71	if (hdr->gso_type != VIRTIO_NET_HDR_GSO_NONE) {

kernel/bpf/stackmap.c+7−1

 	struct stack_map_irq_work *work;
 	work = container_of(entry, struct stack_map_irq_work, irq_work);
-	up_read(work->sem);
+	up_read_non_owner(work->sem);
 	work->sem = NULL;
 }
 	} else {
 		work->sem = &current->mm->mmap_sem;
 		irq_work_queue(&work->irq_work);
+		/*
+		 * The irq_work will release the mmap_sem with
+		 * up_read_non_owner(). The rwsem_release() is called
+		 * here to release the lock from lockdep's perspective.
+		 */
+		rwsem_release(&current->mm->mmap_sem.dep_map, 1, _RET_IP_);
 	}
 }

kernel/events/core.c+16−0

 	}
 }
+static int perf_event_check_period(struct perf_event *event, u64 value)
+{
+	return event->pmu->check_period(event, value);
+}
 static int perf_event_period(struct perf_event *event, u64 __user *arg)
 {
 	u64 value;
 	if (event->attr.freq && value > sysctl_perf_event_sample_rate)
 		return -EINVAL;
+	if (perf_event_check_period(event, value))
+		return -EINVAL;
 	event_function_call(event, __perf_event_period, &value);
 	return 0;
 	return 0;
 }
+static int perf_event_nop_int(struct perf_event *event, u64 value)
+{
+	return 0;
+}
 static DEFINE_PER_CPU(unsigned int, nop_txn_flags);
 static void perf_pmu_start_txn(struct pmu *pmu, unsigned int flags)
 		pmu->pmu_disable = perf_pmu_nop_void;
 	}
+	if (!pmu->check_period)
+		pmu->check_period = perf_event_nop_int;
 	if (!pmu->event_idx)
 		pmu->event_idx = perf_event_idx_default;

kernel/events/ring_buffer.c+1−1

@@ -734,7 +734,7 @@ struct ring_buffer *rb_alloc(int nr_pages, long watermark, int cpu, int flags) · 733 unmodified lines
734	size = sizeof(struct ring_buffer);	734	size = sizeof(struct ring_buffer);
735	size += nr_pages * sizeof(void *);	735	size += nr_pages * sizeof(void *);
736		736
737	if (order_base_2(size) >= MAX_ORDER)	737	if (order_base_2(size) >= PAGE_SHIFT+MAX_ORDER)
738	goto fail;	738	goto fail;
739		739
740	rb = kzalloc(size, GFP_KERNEL);	740	rb = kzalloc(size, GFP_KERNEL);

kernel/trace/trace.c+2−0

@@ -3384,6 +3384,8 @@ static void print_func_help_header_irq(struct trace_buffer *buf, struct seq_file · 3383 unmodified lines
3384	const char tgid_space[] = " ";	3384	const char tgid_space[] = " ";
3385	const char space[] = " ";	3385	const char space[] = " ";
3386		3386
		3387	print_event_info(buf, m);
		3388
3387	seq_printf(m, "# %s _-----=> irqs-off\n",	3389	seq_printf(m, "# %s _-----=> irqs-off\n",
3388	tgid ? tgid_space : space);	3390	tgid ? tgid_space : space);
3389	seq_printf(m, "# %s / _----=> need-resched\n",	3391	seq_printf(m, "# %s / _----=> need-resched\n",

kernel/trace/trace_kprobe.c+1−9

 static nokprobe_inline int
 fetch_store_strlen(unsigned long addr)
 {
-	mm_segment_t old_fs;
 	int ret, len = 0;
 	u8 c;
-	old_fs = get_fs();
-	set_fs(KERNEL_DS);
-	pagefault_disable();
 	do {
-		ret = __copy_from_user_inatomic(&c, (u8 *)addr + len, 1);
+		ret = probe_mem_read(&c, (u8 *)addr + len, 1);
 		len++;
 	} while (c && ret == 0 && len < MAX_STRING_SIZE);
-	pagefault_enable();
-	set_fs(old_fs);
 	return (ret < 0) ? ret : len;
 }

lib/crc32.c+2−2

@@ -206,8 +206,8 @@ u32 __pure __weak __crc32c_le(u32 crc, unsigned char const *p, size_t len) · 205 unmodified lines
206	EXPORT_SYMBOL(crc32_le);	206	EXPORT_SYMBOL(crc32_le);
207	EXPORT_SYMBOL(__crc32c_le);	207	EXPORT_SYMBOL(__crc32c_le);
208		208
209	u32 crc32_le_base(u32, unsigned char const *, size_t) __alias(crc32_le);	209	u32 __pure crc32_le_base(u32, unsigned char const *, size_t) __alias(crc32_le);
210	u32 __crc32c_le_base(u32, unsigned char const *, size_t) __alias(__crc32c_le);	210	u32 __pure __crc32c_le_base(u32, unsigned char const *, size_t) __alias(__crc32c_le);
211		211
212	/*	212	/*
213	* This multiplies the polynomials x and y modulo the given modulus.	213	* This multiplies the polynomials x and y modulo the given modulus.

mm/memblock.c+9−2

 #include "internal.h"
+#define INIT_MEMBLOCK_REGIONS			128
+#define INIT_PHYSMEM_REGIONS			4
+#ifndef INIT_MEMBLOCK_RESERVED_REGIONS
+# define INIT_MEMBLOCK_RESERVED_REGIONS		INIT_MEMBLOCK_REGIONS
+#endif
 /**
  * DOC: memblock overview
  *
 unsigned long long max_possible_pfn;
 static struct memblock_region memblock_memory_init_regions[INIT_MEMBLOCK_REGIONS] __initdata_memblock;
-static struct memblock_region memblock_reserved_init_regions[INIT_MEMBLOCK_REGIONS] __initdata_memblock;
+static struct memblock_region memblock_reserved_init_regions[INIT_MEMBLOCK_RESERVED_REGIONS] __initdata_memblock;
 #ifdef CONFIG_HAVE_MEMBLOCK_PHYS_MAP
 static struct memblock_region memblock_physmem_init_regions[INIT_PHYSMEM_REGIONS] __initdata_memblock;
 #endif
 	.reserved.regions	= memblock_reserved_init_regions,
 	.reserved.cnt		= 1,	/* empty dummy entry */
-	.reserved.max		= INIT_MEMBLOCK_REGIONS,
+	.reserved.max		= INIT_MEMBLOCK_RESERVED_REGIONS,
 	.reserved.name		= "reserved",
 #ifdef CONFIG_HAVE_MEMBLOCK_PHYS_MAP

mm/page_alloc.c+4−4

@@ -4675,11 +4675,11 @@ refill: · 4674 unmodified lines
4675	/* Even if we own the page, we do not use atomic_set().	4675	/* Even if we own the page, we do not use atomic_set().
4676	* This would break get_page_unless_zero() users.	4676	* This would break get_page_unless_zero() users.
4677	*/	4677	*/
4678	page_ref_add(page, size);	4678	page_ref_add(page, PAGE_FRAG_CACHE_MAX_SIZE);
4679		4679
4680	/* reset page count bias and offset to start of new frag */	4680	/* reset page count bias and offset to start of new frag */
4681	nc->pfmemalloc = page_is_pfmemalloc(page);	4681	nc->pfmemalloc = page_is_pfmemalloc(page);
4682	nc->pagecnt_bias = size + 1;	4682	nc->pagecnt_bias = PAGE_FRAG_CACHE_MAX_SIZE + 1;
4683	nc->offset = size;	4683	nc->offset = size;
4684	}	4684	}
4685		4685
@@ -4695,10 +4695,10 @@ refill: · 9 unmodified lines
4695	size = nc->size;	4695	size = nc->size;
4696	#endif	4696	#endif
4697	/* OK, page count is 0, we can safely set it */	4697	/* OK, page count is 0, we can safely set it */
4698	set_page_count(page, size + 1);	4698	set_page_count(page, PAGE_FRAG_CACHE_MAX_SIZE + 1);
4699		4699
4700	/* reset page count bias and offset to start of new frag */	4700	/* reset page count bias and offset to start of new frag */
4701	nc->pagecnt_bias = size + 1;	4701	nc->pagecnt_bias = PAGE_FRAG_CACHE_MAX_SIZE + 1;
4702	offset = size - fragsz;	4702	offset = size - fragsz;
4703	}	4703	}
4704		4704

net/core/dev.c+2−2

@@ -8215,7 +8215,7 @@ static netdev_features_t netdev_sync_upper_features(struct net_device *lower, · 8214 unmodified lines
8215	netdev_features_t feature;	8215	netdev_features_t feature;
8216	int feature_bit;	8216	int feature_bit;
8217		8217
8218	for_each_netdev_feature(&upper_disables, feature_bit) {	8218	for_each_netdev_feature(upper_disables, feature_bit) {
8219	feature = __NETIF_F_BIT(feature_bit);	8219	feature = __NETIF_F_BIT(feature_bit);
8220	if (!(upper->wanted_features & feature)	8220	if (!(upper->wanted_features & feature)
8221	&& (features & feature)) {	8221	&& (features & feature)) {
@@ -8235,7 +8235,7 @@ static void netdev_sync_lower_features(struct net_device *upper, · 13 unmodified lines
8235	netdev_features_t feature;	8235	netdev_features_t feature;
8236	int feature_bit;	8236	int feature_bit;
8237		8237
8238	for_each_netdev_feature(&upper_disables, feature_bit) {	8238	for_each_netdev_feature(upper_disables, feature_bit) {
8239	feature = __NETIF_F_BIT(feature_bit);	8239	feature = __NETIF_F_BIT(feature_bit);
8240	if (!(features & feature) && (lower->features & feature)) {	8240	if (!(features & feature) && (lower->features & feature)) {
8241	netdev_dbg(upper, "Disabling feature %pNF on lower dev %s.\n",	8241	netdev_dbg(upper, "Disabling feature %pNF on lower dev %s.\n",

net/core/filter.c+4−8

 	u32 off = skb_mac_header_len(skb);
 	int ret;
-	/* SCTP uses GSO_BY_FRAGS, thus cannot adjust it. */
+	if (!skb_is_gso_tcp(skb))
-	if (skb_is_gso(skb) && unlikely(skb_is_gso_sctp(skb)))
 		return -ENOTSUPP;
 	ret = skb_cow(skb, len_diff);
 	u32 off = skb_mac_header_len(skb);
 	int ret;
-	/* SCTP uses GSO_BY_FRAGS, thus cannot adjust it. */
+	if (!skb_is_gso_tcp(skb))
-	if (skb_is_gso(skb) && unlikely(skb_is_gso_sctp(skb)))
 		return -ENOTSUPP;
 	ret = skb_unclone(skb, GFP_ATOMIC);
 	u32 off = skb_mac_header_len(skb) + bpf_skb_net_base_len(skb);
 	int ret;
-	/* SCTP uses GSO_BY_FRAGS, thus cannot adjust it. */
+	if (!skb_is_gso_tcp(skb))
-	if (skb_is_gso(skb) && unlikely(skb_is_gso_sctp(skb)))
 		return -ENOTSUPP;
 	ret = skb_cow(skb, len_diff);
 	u32 off = skb_mac_header_len(skb) + bpf_skb_net_base_len(skb);
 	int ret;
-	/* SCTP uses GSO_BY_FRAGS, thus cannot adjust it. */
+	if (!skb_is_gso_tcp(skb))
-	if (skb_is_gso(skb) && unlikely(skb_is_gso_sctp(skb)))
 		return -ENOTSUPP;
 	ret = skb_unclone(skb, GFP_ATOMIC);

net/core/skbuff.c+4−0

  */
 void *netdev_alloc_frag(unsigned int fragsz)
 {
+	fragsz = SKB_DATA_ALIGN(fragsz);
 	return __netdev_alloc_frag(fragsz, GFP_ATOMIC);
 }
 EXPORT_SYMBOL(netdev_alloc_frag);
 void *napi_alloc_frag(unsigned int fragsz)
 {
+	fragsz = SKB_DATA_ALIGN(fragsz);
 	return __napi_alloc_frag(fragsz, GFP_ATOMIC);
 }
 EXPORT_SYMBOL(napi_alloc_frag);

net/ipv4/tcp.c+2−0

 	sk_mem_reclaim(sk);
 	tcp_clear_all_retrans_hints(tcp_sk(sk));
 	tcp_sk(sk)->packets_out = 0;
+	inet_csk(sk)->icsk_backoff = 0;
 }
 int tcp_disconnect(struct sock *sk, int flags)
 	if (tp->write_seq == 0)
 		tp->write_seq = 1;
 	icsk->icsk_backoff = 0;
+	tp->snd_cwnd = 2;
 	icsk->icsk_probes_out = 0;
 	icsk->icsk_rto = TCP_TIMEOUT_INIT;
 	tp->snd_ssthresh = TCP_INFINITE_SSTHRESH;

net/ipv4/tcp_ipv4.c+4−1

 		if (sock_owned_by_user(sk))
 			break;
+		skb = tcp_rtx_queue_head(sk);
+		if (WARN_ON_ONCE(!skb))
+			break;
 		icsk->icsk_backoff--;
 		icsk->icsk_rto = tp->srtt_us ? __tcp_set_rto(tp) :
 					       TCP_TIMEOUT_INIT;
 		icsk->icsk_rto = inet_csk_rto_backoff(icsk, TCP_RTO_MAX);
-		skb = tcp_rtx_queue_head(sk);
 		tcp_mstamp_refresh(tp);
 		delta_us = (u32)(tp->tcp_mstamp - tcp_skb_timestamp_us(skb));

net/ipv6/ip6_gre.c+20−14

 	return 0;
 }
+static void ip6erspan_set_version(struct nlattr *data[],
+				  struct __ip6_tnl_parm *parms)
+{
+	parms->erspan_ver = 1;
+	if (data[IFLA_GRE_ERSPAN_VER])
+		parms->erspan_ver = nla_get_u8(data[IFLA_GRE_ERSPAN_VER]);
+	if (parms->erspan_ver == 1) {
+		if (data[IFLA_GRE_ERSPAN_INDEX])
+			parms->index = nla_get_u32(data[IFLA_GRE_ERSPAN_INDEX]);
+	} else if (parms->erspan_ver == 2) {
+		if (data[IFLA_GRE_ERSPAN_DIR])
+			parms->dir = nla_get_u8(data[IFLA_GRE_ERSPAN_DIR]);
+		if (data[IFLA_GRE_ERSPAN_HWID])
+			parms->hwid = nla_get_u16(data[IFLA_GRE_ERSPAN_HWID]);
+	}
+}
 static void ip6gre_netlink_parms(struct nlattr *data[],
 				struct __ip6_tnl_parm *parms)
 {
 	if (data[IFLA_GRE_COLLECT_METADATA])
 		parms->collect_md = true;
-	parms->erspan_ver = 1;
-	if (data[IFLA_GRE_ERSPAN_VER])
-		parms->erspan_ver = nla_get_u8(data[IFLA_GRE_ERSPAN_VER]);
-	if (parms->erspan_ver == 1) {
-		if (data[IFLA_GRE_ERSPAN_INDEX])
-			parms->index = nla_get_u32(data[IFLA_GRE_ERSPAN_INDEX]);
-	} else if (parms->erspan_ver == 2) {
-		if (data[IFLA_GRE_ERSPAN_DIR])
-			parms->dir = nla_get_u8(data[IFLA_GRE_ERSPAN_DIR]);
-		if (data[IFLA_GRE_ERSPAN_HWID])
-			parms->hwid = nla_get_u16(data[IFLA_GRE_ERSPAN_HWID]);
-	}
 }
 static int ip6gre_tap_init(struct net_device *dev)
 	int err;
 	ip6gre_netlink_parms(data, &nt->parms);
+	ip6erspan_set_version(data, &nt->parms);
 	ign = net_generic(net, ip6gre_net_id);
 	if (nt->parms.collect_md) {
 	if (IS_ERR(t))
 		return PTR_ERR(t);
+	ip6erspan_set_version(data, &p);
 	ip6gre_tunnel_unlink_md(ign, t);
 	ip6gre_tunnel_unlink(ign, t);
 	ip6erspan_tnl_change(t, &p, !tb[IFLA_MTU]);

net/mac80211/cfg.c+5−1

 		      BSS_CHANGED_P2P_PS |
 		      BSS_CHANGED_TXPOWER;
 	int err;
+	int prev_beacon_int;
 	old = sdata_dereference(sdata->u.ap.beacon, sdata);
 	if (old)
 	sdata->needed_rx_chains = sdata->local->rx_chains;
+	prev_beacon_int = sdata->vif.bss_conf.beacon_int;
 	sdata->vif.bss_conf.beacon_int = params->beacon_interval;
 	if (params->he_cap)
 	if (!err)
 		ieee80211_vif_copy_chanctx_to_vlans(sdata, false);
 	mutex_unlock(&local->mtx);
-	if (err)
+	if (err) {
+		sdata->vif.bss_conf.beacon_int = prev_beacon_int;
 		return err;
+	}
 	/*
 	 * Apply control port protocol, this allows us to

net/mac80211/mesh.h+6−0

  * @dst: mesh path destination mac address
  * @mpp: mesh proxy mac address
  * @rhash: rhashtable list pointer
+ * @walk_list: linked list containing all mesh_path objects.
  * @gate_list: list pointer for known gates list
  * @sdata: mesh subif
  * @next_hop: mesh neighbor to which frames for this destination will be
 	u8 dst[ETH_ALEN];
 	u8 mpp[ETH_ALEN];	/* used for MPP or MAP */
 	struct rhash_head rhash;
+	struct hlist_node walk_list;
 	struct hlist_node gate_list;
 	struct ieee80211_sub_if_data *sdata;
 	struct sta_info __rcu *next_hop;
  * gate's mpath may or may not be resolved and active.
  * @gates_lock: protects updates to known_gates
  * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr
+ * @walk_head: linked list containging all mesh_path objects
+ * @walk_lock: lock protecting walk_head
  * @entries: number of entries in the table
  */
 struct mesh_table {
 	struct hlist_head known_gates;
 	spinlock_t gates_lock;
 	struct rhashtable rhead;
+	struct hlist_head walk_head;
+	spinlock_t walk_lock;
 	atomic_t entries;		/* Up to MAX_MESH_NEIGHBOURS */
 };

net/mac80211/mesh_pathtbl.c+47−110

@@ -59,8 +59,10 @@ static struct mesh_table *mesh_table_alloc(void) · 58 unmodified lines
59	return NULL;	59	return NULL;
60		60
61	INIT_HLIST_HEAD(&newtbl->known_gates);	61	INIT_HLIST_HEAD(&newtbl->known_gates);
		62	INIT_HLIST_HEAD(&newtbl->walk_head);
62	atomic_set(&newtbl->entries, 0);	63	atomic_set(&newtbl->entries, 0);
63	spin_lock_init(&newtbl->gates_lock);	64	spin_lock_init(&newtbl->gates_lock);
		65	spin_lock_init(&newtbl->walk_lock);
64		66
65	return newtbl;	67	return newtbl;
66	}	68	}
@@ -249,28 +251,15 @@ mpp_path_lookup(struct ieee80211_sub_if_data sdata, const u8 dst) · 182 unmodified lines
249	static struct mesh_path *	251	static struct mesh_path *
250	__mesh_path_lookup_by_idx(struct mesh_table *tbl, int idx)	252	__mesh_path_lookup_by_idx(struct mesh_table *tbl, int idx)
251	{	253	{
252	int i = 0, ret;	254	int i = 0;
253	struct mesh_path *mpath = NULL;	255	struct mesh_path *mpath;
254	struct rhashtable_iter iter;
255
256	ret = rhashtable_walk_init(&tbl->rhead, &iter, GFP_ATOMIC);
257	if (ret)
258	return NULL;
259
260	rhashtable_walk_start(&iter);
261		256
262	while ((mpath = rhashtable_walk_next(&iter))) {	257	hlist_for_each_entry_rcu(mpath, &tbl->walk_head, walk_list) {
263	if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
264	continue;
265	if (IS_ERR(mpath))
266	break;
267	if (i++ == idx)	258	if (i++ == idx)
268	break;	259	break;
269	}	260	}
270	rhashtable_walk_stop(&iter);
271	rhashtable_walk_exit(&iter);
272		261
273	if (IS_ERR(mpath) \|\| !mpath)	262	if (!mpath)
274	return NULL;	263	return NULL;
275		264
276	if (mpath_expired(mpath)) {	265	if (mpath_expired(mpath)) {
@@ -432,6 +421,7 @@ struct mesh_path mesh_path_add(struct ieee80211_sub_if_data sdata, · 155 unmodified lines
432	return ERR_PTR(-ENOMEM);	421	return ERR_PTR(-ENOMEM);
433		422
434	tbl = sdata->u.mesh.mesh_paths;	423	tbl = sdata->u.mesh.mesh_paths;
		424	spin_lock_bh(&tbl->walk_lock);
435	do {	425	do {
436	ret = rhashtable_lookup_insert_fast(&tbl->rhead,	426	ret = rhashtable_lookup_insert_fast(&tbl->rhead,
437	&new_mpath->rhash,	427	&new_mpath->rhash,
@@ -441,20 +431,20 @@ struct mesh_path mesh_path_add(struct ieee80211_sub_if_data sdata, · 3 unmodified lines
441	mpath = rhashtable_lookup_fast(&tbl->rhead,	431	mpath = rhashtable_lookup_fast(&tbl->rhead,
442	dst,	432	dst,
443	mesh_rht_params);	433	mesh_rht_params);
444		434	else if (!ret)
		435	hlist_add_head(&new_mpath->walk_list, &tbl->walk_head);
445	} while (unlikely(ret == -EEXIST && !mpath));	436	} while (unlikely(ret == -EEXIST && !mpath));
		437	spin_unlock_bh(&tbl->walk_lock);
446		438
447	if (ret && ret != -EEXIST)	439	if (ret) {
448	return ERR_PTR(ret);
449
450	/* At this point either new_mpath was added, or we found a
451	* matching entry already in the table; in the latter case
452	* free the unnecessary new entry.
453	*/
454	if (ret == -EEXIST) {
455	kfree(new_mpath);	440	kfree(new_mpath);
		441
		442	if (ret != -EEXIST)
		443	return ERR_PTR(ret);
		444
456	new_mpath = mpath;	445	new_mpath = mpath;
457	}	446	}
		447
458	sdata->u.mesh.mesh_paths_generation++;	448	sdata->u.mesh.mesh_paths_generation++;
459	return new_mpath;	449	return new_mpath;
460	}	450	}
@@ -480,9 +470,17 @@ int mpp_path_add(struct ieee80211_sub_if_data *sdata, · 19 unmodified lines
480		470
481	memcpy(new_mpath->mpp, mpp, ETH_ALEN);	471	memcpy(new_mpath->mpp, mpp, ETH_ALEN);
482	tbl = sdata->u.mesh.mpp_paths;	472	tbl = sdata->u.mesh.mpp_paths;
		473
		474	spin_lock_bh(&tbl->walk_lock);
483	ret = rhashtable_lookup_insert_fast(&tbl->rhead,	475	ret = rhashtable_lookup_insert_fast(&tbl->rhead,
484	&new_mpath->rhash,	476	&new_mpath->rhash,
485	mesh_rht_params);	477	mesh_rht_params);
		478	if (!ret)
		479	hlist_add_head_rcu(&new_mpath->walk_list, &tbl->walk_head);
		480	spin_unlock_bh(&tbl->walk_lock);
		481
		482	if (ret)
		483	kfree(new_mpath);
486		484
487	sdata->u.mesh.mpp_paths_generation++;	485	sdata->u.mesh.mpp_paths_generation++;
488	return ret;	486	return ret;
@@ -503,20 +501,9 @@ void mesh_plink_broken(struct sta_info *sta) · 14 unmodified lines
503	struct mesh_table *tbl = sdata->u.mesh.mesh_paths;	501	struct mesh_table *tbl = sdata->u.mesh.mesh_paths;
504	static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};	502	static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
505	struct mesh_path *mpath;	503	struct mesh_path *mpath;
506	struct rhashtable_iter iter;
507	int ret;
508
509	ret = rhashtable_walk_init(&tbl->rhead, &iter, GFP_ATOMIC);
510	if (ret)
511	return;
512		504
513	rhashtable_walk_start(&iter);	505	rcu_read_lock();
514		506	hlist_for_each_entry_rcu(mpath, &tbl->walk_head, walk_list) {
515	while ((mpath = rhashtable_walk_next(&iter))) {
516	if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
517	continue;
518	if (IS_ERR(mpath))
519	break;
520	if (rcu_access_pointer(mpath->next_hop) == sta &&	507	if (rcu_access_pointer(mpath->next_hop) == sta &&
521	mpath->flags & MESH_PATH_ACTIVE &&	508	mpath->flags & MESH_PATH_ACTIVE &&
522	!(mpath->flags & MESH_PATH_FIXED)) {	509	!(mpath->flags & MESH_PATH_FIXED)) {
@@ -530,8 +517,7 @@ void mesh_plink_broken(struct sta_info *sta) · 7 unmodified lines
530	WLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast);	517	WLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast);
531	}	518	}
532	}	519	}
533	rhashtable_walk_stop(&iter);	520	rcu_read_unlock();
534	rhashtable_walk_exit(&iter);
535	}	521	}
536		522
537	static void mesh_path_free_rcu(struct mesh_table *tbl,	523	static void mesh_path_free_rcu(struct mesh_table *tbl,
@@ -551,6 +537,7 @@ static void mesh_path_free_rcu(struct mesh_table *tbl, · 13 unmodified lines
551		537
552	static void __mesh_path_del(struct mesh_table tbl, struct mesh_path mpath)	538	static void __mesh_path_del(struct mesh_table tbl, struct mesh_path mpath)
553	{	539	{
		540	hlist_del_rcu(&mpath->walk_list);
554	rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, mesh_rht_params);	541	rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, mesh_rht_params);
555	mesh_path_free_rcu(tbl, mpath);	542	mesh_path_free_rcu(tbl, mpath);
556	}	543	}
@@ -571,27 +558,14 @@ void mesh_path_flush_by_nexthop(struct sta_info *sta) · 14 unmodified lines
571	struct ieee80211_sub_if_data *sdata = sta->sdata;	558	struct ieee80211_sub_if_data *sdata = sta->sdata;
572	struct mesh_table *tbl = sdata->u.mesh.mesh_paths;	559	struct mesh_table *tbl = sdata->u.mesh.mesh_paths;
573	struct mesh_path *mpath;	560	struct mesh_path *mpath;
574	struct rhashtable_iter iter;	561	struct hlist_node *n;
575	int ret;
576
577	ret = rhashtable_walk_init(&tbl->rhead, &iter, GFP_ATOMIC);
578	if (ret)
579	return;
580
581	rhashtable_walk_start(&iter);
582
583	while ((mpath = rhashtable_walk_next(&iter))) {
584	if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
585	continue;
586	if (IS_ERR(mpath))
587	break;
588		562
		563	spin_lock_bh(&tbl->walk_lock);
		564	hlist_for_each_entry_safe(mpath, n, &tbl->walk_head, walk_list) {
589	if (rcu_access_pointer(mpath->next_hop) == sta)	565	if (rcu_access_pointer(mpath->next_hop) == sta)
590	__mesh_path_del(tbl, mpath);	566	__mesh_path_del(tbl, mpath);
591	}	567	}
592		568	spin_unlock_bh(&tbl->walk_lock);
593	rhashtable_walk_stop(&iter);
594	rhashtable_walk_exit(&iter);
595	}	569	}
596		570
597	static void mpp_flush_by_proxy(struct ieee80211_sub_if_data *sdata,	571	static void mpp_flush_by_proxy(struct ieee80211_sub_if_data *sdata,
@@ -599,51 +573,26 @@ static void mpp_flush_by_proxy(struct ieee80211_sub_if_data *sdata, · 1 unmodified line
599	{	573	{
600	struct mesh_table *tbl = sdata->u.mesh.mpp_paths;	574	struct mesh_table *tbl = sdata->u.mesh.mpp_paths;
601	struct mesh_path *mpath;	575	struct mesh_path *mpath;
602	struct rhashtable_iter iter;	576	struct hlist_node *n;
603	int ret;
604
605	ret = rhashtable_walk_init(&tbl->rhead, &iter, GFP_ATOMIC);
606	if (ret)
607	return;
608
609	rhashtable_walk_start(&iter);
610
611	while ((mpath = rhashtable_walk_next(&iter))) {
612	if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
613	continue;
614	if (IS_ERR(mpath))
615	break;
616		577
		578	spin_lock_bh(&tbl->walk_lock);
		579	hlist_for_each_entry_safe(mpath, n, &tbl->walk_head, walk_list) {
617	if (ether_addr_equal(mpath->mpp, proxy))	580	if (ether_addr_equal(mpath->mpp, proxy))
618	__mesh_path_del(tbl, mpath);	581	__mesh_path_del(tbl, mpath);
619	}	582	}
620		583	spin_unlock_bh(&tbl->walk_lock);
621	rhashtable_walk_stop(&iter);
622	rhashtable_walk_exit(&iter);
623	}	584	}
624		585
625	static void table_flush_by_iface(struct mesh_table *tbl)	586	static void table_flush_by_iface(struct mesh_table *tbl)
626	{	587	{
627	struct mesh_path *mpath;	588	struct mesh_path *mpath;
628	struct rhashtable_iter iter;	589	struct hlist_node *n;
629	int ret;
630
631	ret = rhashtable_walk_init(&tbl->rhead, &iter, GFP_ATOMIC);
632	if (ret)
633	return;
634
635	rhashtable_walk_start(&iter);
636		590
637	while ((mpath = rhashtable_walk_next(&iter))) {	591	spin_lock_bh(&tbl->walk_lock);
638	if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)	592	hlist_for_each_entry_safe(mpath, n, &tbl->walk_head, walk_list) {
639	continue;
640	if (IS_ERR(mpath))
641	break;
642	__mesh_path_del(tbl, mpath);	593	__mesh_path_del(tbl, mpath);
643	}	594	}
644		595	spin_unlock_bh(&tbl->walk_lock);
645	rhashtable_walk_stop(&iter);
646	rhashtable_walk_exit(&iter);
647	}	596	}
648		597
649	/**	598	/**
@@ -675,15 +624,15 @@ static int table_path_del(struct mesh_table *tbl, · 25 unmodified lines
675	{	624	{
676	struct mesh_path *mpath;	625	struct mesh_path *mpath;
677		626
678	rcu_read_lock();	627	spin_lock_bh(&tbl->walk_lock);
679	mpath = rhashtable_lookup_fast(&tbl->rhead, addr, mesh_rht_params);	628	mpath = rhashtable_lookup_fast(&tbl->rhead, addr, mesh_rht_params);
680	if (!mpath) {	629	if (!mpath) {
681	rcu_read_unlock();	630	spin_unlock_bh(&tbl->walk_lock);
682	return -ENXIO;	631	return -ENXIO;
683	}	632	}
684		633
685	__mesh_path_del(tbl, mpath);	634	__mesh_path_del(tbl, mpath);
686	rcu_read_unlock();	635	spin_unlock_bh(&tbl->walk_lock);
687	return 0;	636	return 0;
688	}	637	}
689		638
@@ -854,28 +803,16 @@ void mesh_path_tbl_expire(struct ieee80211_sub_if_data *sdata, · 164 unmodified lines
854	struct mesh_table *tbl)	803	struct mesh_table *tbl)
855	{	804	{
856	struct mesh_path *mpath;	805	struct mesh_path *mpath;
857	struct rhashtable_iter iter;	806	struct hlist_node *n;
858	int ret;
859		807
860	ret = rhashtable_walk_init(&tbl->rhead, &iter, GFP_KERNEL);	808	spin_lock_bh(&tbl->walk_lock);
861	if (ret)	809	hlist_for_each_entry_safe(mpath, n, &tbl->walk_head, walk_list) {
862	return;
863
864	rhashtable_walk_start(&iter);
865
866	while ((mpath = rhashtable_walk_next(&iter))) {
867	if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
868	continue;
869	if (IS_ERR(mpath))
870	break;
871	if ((!(mpath->flags & MESH_PATH_RESOLVING)) &&	810	if ((!(mpath->flags & MESH_PATH_RESOLVING)) &&
872	(!(mpath->flags & MESH_PATH_FIXED)) &&	811	(!(mpath->flags & MESH_PATH_FIXED)) &&
873	time_after(jiffies, mpath->exp_time + MESH_PATH_EXPIRE))	812	time_after(jiffies, mpath->exp_time + MESH_PATH_EXPIRE))
874	__mesh_path_del(tbl, mpath);	813	__mesh_path_del(tbl, mpath);
875	}	814	}
876		815	spin_unlock_bh(&tbl->walk_lock);
877	rhashtable_walk_stop(&iter);
878	rhashtable_walk_exit(&iter);
879	}	816	}
880		817
881	void mesh_path_expire(struct ieee80211_sub_if_data *sdata)	818	void mesh_path_expire(struct ieee80211_sub_if_data *sdata)

net/netfilter/ipvs/ip_vs_ctl.c+2−1

 {
 	struct ip_vs_dest *dest;
 	unsigned int atype, i;
-	int ret = 0;
 	EnterFunction(2);
 #ifdef CONFIG_IP_VS_IPV6
 	if (udest->af == AF_INET6) {
+		int ret;
 		atype = ipv6_addr_type(&udest->addr.in6);
 		if ((!(atype & IPV6_ADDR_UNICAST) ||
 			atype & IPV6_ADDR_LINKLOCAL) &&

net/netfilter/nf_tables_api.c+3−0

@@ -328,6 +328,9 @@ static int nft_delrule_by_chain(struct nft_ctx *ctx) · 327 unmodified lines
328	int err;	328	int err;
329		329
330	list_for_each_entry(rule, &ctx->chain->rules, list) {	330	list_for_each_entry(rule, &ctx->chain->rules, list) {
		331	if (!nft_is_active_next(ctx->net, rule))
		332	continue;
		333
331	err = nft_delrule(ctx, rule);	334	err = nft_delrule(ctx, rule);
332	if (err < 0)	335	if (err < 0)
333	return err;	336	return err;

net/sunrpc/auth_gss/gss_krb5_seqnum.c+38−11

 		      unsigned char *cksum, unsigned char *buf)
 {
 	struct crypto_sync_skcipher *cipher;
-	unsigned char plain[8];
+	unsigned char *plain;
 	s32 code;
 	dprintk("RPC:       %s:\n", __func__);
 	if (IS_ERR(cipher))
 		return PTR_ERR(cipher);
+	plain = kmalloc(8, GFP_NOFS);
+	if (!plain)
+		return -ENOMEM;
 	plain[0] = (unsigned char) ((seqnum >> 24) & 0xff);
 	plain[1] = (unsigned char) ((seqnum >> 16) & 0xff);
 	plain[2] = (unsigned char) ((seqnum >> 8) & 0xff);
 	code = krb5_encrypt(cipher, cksum, plain, buf, 8);
 out:
+	kfree(plain);
 	crypto_free_sync_skcipher(cipher);
 	return code;
 }
 		u32 seqnum,
 		unsigned char *cksum, unsigned char *buf)
 {
-	unsigned char plain[8];
+	unsigned char *plain;
+	s32 code;
 	if (kctx->enctype == ENCTYPE_ARCFOUR_HMAC)
 		return krb5_make_rc4_seq_num(kctx, direction, seqnum,
 					     cksum, buf);
+	plain = kmalloc(8, GFP_NOFS);
+	if (!plain)
+		return -ENOMEM;
 	plain[0] = (unsigned char) (seqnum & 0xff);
 	plain[1] = (unsigned char) ((seqnum >> 8) & 0xff);
 	plain[2] = (unsigned char) ((seqnum >> 16) & 0xff);
 	plain[6] = direction;
 	plain[7] = direction;
-	return krb5_encrypt(key, cksum, plain, buf, 8);
+	code = krb5_encrypt(key, cksum, plain, buf, 8);
+	kfree(plain);
+	return code;
 }
 static s32
 		     unsigned char *buf, int *direction, s32 *seqnum)
 {
 	struct crypto_sync_skcipher *cipher;
-	unsigned char plain[8];
+	unsigned char *plain;
 	s32 code;
 	dprintk("RPC:       %s:\n", __func__);
 	if (code)
 		goto out;
+	plain = kmalloc(8, GFP_NOFS);
+	if (!plain) {
+		code = -ENOMEM;
+		goto out;
+	}
 	code = krb5_decrypt(cipher, cksum, buf, plain, 8);
 	if (code)
-		goto out;
+		goto out_plain;
 	if ((plain[4] != plain[5]) || (plain[4] != plain[6])
 				   || (plain[4] != plain[7])) {
 		code = (s32)KG_BAD_SEQ;
-		goto out;
+		goto out_plain;
 	}
 	*direction = plain[4];
 	*seqnum = ((plain[0] << 24) | (plain[1] << 16) |
 					(plain[2] << 8) | (plain[3]));
+out_plain:
+	kfree(plain);
 out:
 	crypto_free_sync_skcipher(cipher);
 	return code;
 	       int *direction, u32 *seqnum)
 {
 	s32 code;
-	unsigned char plain[8];
+	unsigned char *plain;
 	struct crypto_sync_skcipher *key = kctx->seq;
 	dprintk("RPC:       krb5_get_seq_num:\n");
 	if (kctx->enctype == ENCTYPE_ARCFOUR_HMAC)
 		return krb5_get_rc4_seq_num(kctx, cksum, buf,
 					    direction, seqnum);
+	plain = kmalloc(8, GFP_NOFS);
+	if (!plain)
+		return -ENOMEM;
 	if ((code = krb5_decrypt(key, cksum, buf, plain, 8)))
-		return code;
+		goto out;
 	if ((plain[4] != plain[5]) || (plain[4] != plain[6]) ||
-	    (plain[4] != plain[7]))
+	    (plain[4] != plain[7])) {
-		return (s32)KG_BAD_SEQ;
+		code = (s32)KG_BAD_SEQ;
+		goto out;
+	}
 	*direction = plain[4];
 	*seqnum = ((plain[0]) |
 		   (plain[1] << 8) | (plain[2] << 16) | (plain[3] << 24));
-	return 0;
+out:
+	kfree(plain);
+	return code;
 }

net/sunrpc/debugfs.c+1−1

@@ -146,7 +146,7 @@ rpc_clnt_debugfs_register(struct rpc_clnt *clnt) · 145 unmodified lines
146	rcu_read_lock();	146	rcu_read_lock();
147	xprt = rcu_dereference(clnt->cl_xprt);	147	xprt = rcu_dereference(clnt->cl_xprt);
148	/* no "debugfs" dentry? Don't bother with the symlink. */	148	/* no "debugfs" dentry? Don't bother with the symlink. */
149	if (!xprt->debugfs) {	149	if (IS_ERR_OR_NULL(xprt->debugfs)) {
150	rcu_read_unlock();	150	rcu_read_unlock();
151	return;	151	return;
152	}	152	}

net/sunrpc/xprtrdma/verbs.c+2−1

@@ -527,7 +527,8 @@ rpcrdma_ep_create(struct rpcrdma_ep ep, struct rpcrdma_ia ia, · 526 unmodified lines
527		527
528	sendcq = ib_alloc_cq(ia->ri_device, NULL,	528	sendcq = ib_alloc_cq(ia->ri_device, NULL,
529	ep->rep_attr.cap.max_send_wr + 1,	529	ep->rep_attr.cap.max_send_wr + 1,
530	1, IB_POLL_WORKQUEUE);	530	ia->ri_device->num_comp_vectors > 1 ? 1 : 0,
		531	IB_POLL_WORKQUEUE);
531	if (IS_ERR(sendcq)) {	532	if (IS_ERR(sendcq)) {
532	rc = PTR_ERR(sendcq);	533	rc = PTR_ERR(sendcq);
533	goto out1;	534	goto out1;

net/xdp/xdp_umem.c+6−5

 	return 0;
 err_unreg_umem:
-	xdp_clear_umem_at_qid(dev, queue_id);
 	if (!force_zc)
 		err = 0; /* fallback to copy mode */
+	if (err)
+		xdp_clear_umem_at_qid(dev, queue_id);
 out_rtnl_unlock:
 	rtnl_unlock();
 	return err;
 	if (!umem->pgs)
 		return -ENOMEM;
-	down_write(&current->mm->mmap_sem);
+	down_read(&current->mm->mmap_sem);
-	npgs = get_user_pages(umem->address, umem->npgs,
+	npgs = get_user_pages_longterm(umem->address, umem->npgs,
-			      gup_flags, &umem->pgs[0], NULL);
+				       gup_flags, &umem->pgs[0], NULL);
-	up_write(&current->mm->mmap_sem);
+	up_read(&current->mm->mmap_sem);
 	if (npgs != umem->npgs) {
 		if (npgs >= 0) {

net/xdp/xsk.c+4−0

 		if (!umem)
 			return -EINVAL;
+		/* Matches the smp_wmb() in XDP_UMEM_REG */
+		smp_rmb();
 		if (offset == XDP_UMEM_PGOFF_FILL_RING)
 			q = READ_ONCE(umem->fq);
 		else if (offset == XDP_UMEM_PGOFF_COMPLETION_RING)
 	if (!q)
 		return -EINVAL;
+	/* Matches the smp_wmb() in xsk_init_queue */
+	smp_rmb();
 	qpg = virt_to_head_page(q->ring);
 	if (size > (PAGE_SIZE << compound_order(qpg)))
 		return -EINVAL;

virt/kvm/arm/arm.c+10−0

 		/* Awaken to handle a signal, request we sleep again later. */
 		kvm_make_request(KVM_REQ_SLEEP, vcpu);
 	}
+	/*
+	 * Make sure we will observe a potential reset request if we've
+	 * observed a change to the power state. Pairs with the smp_wmb() in
+	 * kvm_psci_vcpu_on().
+	 */
+	smp_rmb();
 }
 static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu)
 		if (kvm_check_request(KVM_REQ_SLEEP, vcpu))
 			vcpu_req_sleep(vcpu);
+		if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu))
+			kvm_reset_vcpu(vcpu);
 		/*
 		 * Clear IRQ_PENDING requests that were made to guarantee
 		 * that a VCPU sees new virtual interrupts.

virt/kvm/arm/mmu.c+6−3

 	vma_pagesize = vma_kernel_pagesize(vma);
 	/*
-	 * PUD level may not exist for a VM but PMD is guaranteed to
+	 * The stage2 has a minimum of 2 level table (For arm64 see
-	 * exist.
+	 * kvm_arm_setup_stage2()). Hence, we are guaranteed that we can
+	 * use PMD_SIZE huge mappings (even when the PMD is folded into PGD).
+	 * As for PUD huge maps, we must make sure that we have at least
+	 * 3 levels, i.e, PMD is not folded.
 	 */
 	if ((vma_pagesize == PMD_SIZE ||
-	     (vma_pagesize == PUD_SIZE && kvm_stage2_has_pud(kvm))) &&
+	     (vma_pagesize == PUD_SIZE && kvm_stage2_has_pmd(kvm))) &&
 	    !force_pte) {
 		gfn = (fault_ipa & huge_page_mask(hstate_vma(vma))) >> PAGE_SHIFT;
 	}

virt/kvm/arm/psci.c+16−20

@@ -104,12 +104,10 @@ static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu) · 103 unmodified lines
104		104
105	static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)	105	static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
106	{	106	{
		107	struct vcpu_reset_state *reset_state;
107	struct kvm *kvm = source_vcpu->kvm;	108	struct kvm *kvm = source_vcpu->kvm;
108	struct kvm_vcpu *vcpu = NULL;	109	struct kvm_vcpu *vcpu = NULL;
109	struct swait_queue_head *wq;
110	unsigned long cpu_id;	110	unsigned long cpu_id;
111	unsigned long context_id;
112	phys_addr_t target_pc;
113		111
114	cpu_id = smccc_get_arg1(source_vcpu) & MPIDR_HWID_BITMASK;	112	cpu_id = smccc_get_arg1(source_vcpu) & MPIDR_HWID_BITMASK;
115	if (vcpu_mode_is_32bit(source_vcpu))	113	if (vcpu_mode_is_32bit(source_vcpu))
@@ -130,32 +128,30 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) · 14 unmodified lines
130	return PSCI_RET_INVALID_PARAMS;	128	return PSCI_RET_INVALID_PARAMS;
131	}	129	}
132		130
133	target_pc = smccc_get_arg2(source_vcpu);	131	reset_state = &vcpu->arch.reset_state;
134	context_id = smccc_get_arg3(source_vcpu);
135		132
136	kvm_reset_vcpu(vcpu);	133	reset_state->pc = smccc_get_arg2(source_vcpu);
137
138	/* Gracefully handle Thumb2 entry point */
139	if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
140	target_pc &= ~((phys_addr_t) 1);
141	vcpu_set_thumb(vcpu);
142	}
143		134
144	/* Propagate caller endianness */	135	/* Propagate caller endianness */
145	if (kvm_vcpu_is_be(source_vcpu))	136	reset_state->be = kvm_vcpu_is_be(source_vcpu);
146	kvm_vcpu_set_be(vcpu);
147		137
148	*vcpu_pc(vcpu) = target_pc;
149	/*	138	/*
150	* NOTE: We always update r0 (or x0) because for PSCI v0.1	139	* NOTE: We always update r0 (or x0) because for PSCI v0.1
151	* the general puspose registers are undefined upon CPU_ON.	140	* the general puspose registers are undefined upon CPU_ON.
152	*/	141	*/
153	smccc_set_retval(vcpu, context_id, 0, 0, 0);	142	reset_state->r0 = smccc_get_arg3(source_vcpu);
154	vcpu->arch.power_off = false;	143
155	smp_mb(); /* Make sure the above is visible */	144	WRITE_ONCE(reset_state->reset, true);
		145	kvm_make_request(KVM_REQ_VCPU_RESET, vcpu);
156		146
157	wq = kvm_arch_vcpu_wq(vcpu);	147	/*
158	swake_up_one(wq);	148	* Make sure the reset request is observed if the change to
		149	* power_state is observed.
		150	*/
		151	smp_wmb();
		152
		153	vcpu->arch.power_off = false;
		154	kvm_vcpu_wake_up(vcpu);
159		155
160	return PSCI_RET_SUCCESS;	156	return PSCI_RET_SUCCESS;
161	}	157	}

virt/kvm/arm/vgic/vgic-debug.c+2−2

@@ -251,9 +251,9 @@ static int vgic_debug_show(struct seq_file s, void v) · 250 unmodified lines
251	return 0;	251	return 0;
252	}	252	}
253		253
254	spin_lock_irqsave(&irq->irq_lock, flags);	254	raw_spin_lock_irqsave(&irq->irq_lock, flags);
255	print_irq_state(s, irq, vcpu);	255	print_irq_state(s, irq, vcpu);
256	spin_unlock_irqrestore(&irq->irq_lock, flags);	256	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
257		257
258	vgic_put_irq(kvm, irq);	258	vgic_put_irq(kvm, irq);
259	return 0;	259	return 0;

virt/kvm/arm/vgic/vgic-init.c+18−12

 	struct vgic_dist *dist = &kvm->arch.vgic;
 	INIT_LIST_HEAD(&dist->lpi_list_head);
-	spin_lock_init(&dist->lpi_list_lock);
+	raw_spin_lock_init(&dist->lpi_list_lock);
 }
 /* CREATION */
 		irq->intid = i + VGIC_NR_PRIVATE_IRQS;
 		INIT_LIST_HEAD(&irq->ap_list);
-		spin_lock_init(&irq->irq_lock);
+		raw_spin_lock_init(&irq->irq_lock);
 		irq->vcpu = NULL;
 		irq->target_vcpu = vcpu0;
 		kref_init(&irq->refcount);
 	vgic_cpu->sgi_iodev.base_addr = VGIC_ADDR_UNDEF;
 	INIT_LIST_HEAD(&vgic_cpu->ap_list_head);
-	spin_lock_init(&vgic_cpu->ap_list_lock);
+	raw_spin_lock_init(&vgic_cpu->ap_list_lock);
 	/*
 	 * Enable and configure all SGIs to be edge-triggered and
 		struct vgic_irq *irq = &vgic_cpu->private_irqs[i];
 		INIT_LIST_HEAD(&irq->ap_list);
-		spin_lock_init(&irq->irq_lock);
+		raw_spin_lock_init(&irq->irq_lock);
 		irq->intid = i;
 		irq->vcpu = NULL;
 		irq->target_vcpu = vcpu;
 			irq->config = VGIC_CONFIG_LEVEL;
 		}
-		/*
-		 * GICv3 can only be created via the KVM_DEVICE_CREATE API and
-		 * so we always know the emulation type at this point as it's
-		 * either explicitly configured as GICv3, or explicitly
-		 * configured as GICv2, or not configured yet which also
-		 * implies GICv2.
-		 */
 		if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
 			irq->group = 1;
 		else
 {
 	struct vgic_dist *dist = &kvm->arch.vgic;
 	struct kvm_vcpu *vcpu;
-	int ret = 0, i;
+	int ret = 0, i, idx;
 	if (vgic_initialized(kvm))
 		return 0;
 	if (ret)
 		goto out;
+	/* Initialize groups on CPUs created before the VGIC type was known */
+	kvm_for_each_vcpu(idx, vcpu, kvm) {
+		struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+		for (i = 0; i < VGIC_NR_PRIVATE_IRQS; i++) {
+			struct vgic_irq *irq = &vgic_cpu->private_irqs[i];
+			if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
+				irq->group = 1;
+			else
+				irq->group = 0;
+		}
+	}
 	if (vgic_has_its(kvm)) {
 		ret = vgic_v4_init(kvm);
 		if (ret)

virt/kvm/arm/vgic/vgic-its.c+11−11

@@ -65,7 +65,7 @@ static struct vgic_irq vgic_add_lpi(struct kvm kvm, u32 intid, · 64 unmodified lines
65		65
66	INIT_LIST_HEAD(&irq->lpi_list);	66	INIT_LIST_HEAD(&irq->lpi_list);
67	INIT_LIST_HEAD(&irq->ap_list);	67	INIT_LIST_HEAD(&irq->ap_list);
68	spin_lock_init(&irq->irq_lock);	68	raw_spin_lock_init(&irq->irq_lock);
69		69
70	irq->config = VGIC_CONFIG_EDGE;	70	irq->config = VGIC_CONFIG_EDGE;
71	kref_init(&irq->refcount);	71	kref_init(&irq->refcount);
@@ -73,7 +73,7 @@ static struct vgic_irq vgic_add_lpi(struct kvm kvm, u32 intid, · 1 unmodified line
73	irq->target_vcpu = vcpu;	73	irq->target_vcpu = vcpu;
74	irq->group = 1;	74	irq->group = 1;
75		75
76	spin_lock_irqsave(&dist->lpi_list_lock, flags);	76	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
77		77
78	/*	78	/*
79	* There could be a race with another vgic_add_lpi(), so we need to	79	* There could be a race with another vgic_add_lpi(), so we need to
@@ -101,7 +101,7 @@ static struct vgic_irq vgic_add_lpi(struct kvm kvm, u32 intid, · 21 unmodified lines
101	dist->lpi_list_count++;	101	dist->lpi_list_count++;
102		102
103	out_unlock:	103	out_unlock:
104	spin_unlock_irqrestore(&dist->lpi_list_lock, flags);	104	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
105		105
106	/*	106	/*
107	* We "cache" the configuration table entries in our struct vgic_irq's.	107	* We "cache" the configuration table entries in our struct vgic_irq's.
@@ -287,7 +287,7 @@ static int update_lpi_config(struct kvm kvm, struct vgic_irq irq, · 179 unmodified lines
287	if (ret)	287	if (ret)
288	return ret;	288	return ret;
289		289
290	spin_lock_irqsave(&irq->irq_lock, flags);	290	raw_spin_lock_irqsave(&irq->irq_lock, flags);
291		291
292	if (!filter_vcpu \|\| filter_vcpu == irq->target_vcpu) {	292	if (!filter_vcpu \|\| filter_vcpu == irq->target_vcpu) {
293	irq->priority = LPI_PROP_PRIORITY(prop);	293	irq->priority = LPI_PROP_PRIORITY(prop);
@@ -299,7 +299,7 @@ static int update_lpi_config(struct kvm kvm, struct vgic_irq irq, · 5 unmodified lines
299	}	299	}
300	}	300	}
301		301
302	spin_unlock_irqrestore(&irq->irq_lock, flags);	302	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
303		303
304	if (irq->hw)	304	if (irq->hw)
305	return its_prop_update_vlpi(irq->host_irq, prop, needs_inv);	305	return its_prop_update_vlpi(irq->host_irq, prop, needs_inv);
@@ -332,7 +332,7 @@ int vgic_copy_lpi_list(struct kvm kvm, struct kvm_vcpu vcpu, u32 **intid_ptr) · 26 unmodified lines
332	if (!intids)	332	if (!intids)
333	return -ENOMEM;	333	return -ENOMEM;
334		334
335	spin_lock_irqsave(&dist->lpi_list_lock, flags);	335	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
336	list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {	336	list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
337	if (i == irq_count)	337	if (i == irq_count)
338	break;	338	break;
@@ -341,7 +341,7 @@ int vgic_copy_lpi_list(struct kvm kvm, struct kvm_vcpu vcpu, u32 **intid_ptr) · 2 unmodified lines
341	continue;	341	continue;
342	intids[i++] = irq->intid;	342	intids[i++] = irq->intid;
343	}	343	}
344	spin_unlock_irqrestore(&dist->lpi_list_lock, flags);	344	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
345		345
346	*intid_ptr = intids;	346	*intid_ptr = intids;
347	return i;	347	return i;
@@ -352,9 +352,9 @@ static int update_affinity(struct vgic_irq irq, struct kvm_vcpu vcpu) · 4 unmodified lines
352	int ret = 0;	352	int ret = 0;
353	unsigned long flags;	353	unsigned long flags;
354		354
355	spin_lock_irqsave(&irq->irq_lock, flags);	355	raw_spin_lock_irqsave(&irq->irq_lock, flags);
356	irq->target_vcpu = vcpu;	356	irq->target_vcpu = vcpu;
357	spin_unlock_irqrestore(&irq->irq_lock, flags);	357	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
358		358
359	if (irq->hw) {	359	if (irq->hw) {
360	struct its_vlpi_map map;	360	struct its_vlpi_map map;
@@ -455,7 +455,7 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu) · 94 unmodified lines
455	}	455	}
456		456
457	irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);	457	irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
458	spin_lock_irqsave(&irq->irq_lock, flags);	458	raw_spin_lock_irqsave(&irq->irq_lock, flags);
459	irq->pending_latch = pendmask & (1U << bit_nr);	459	irq->pending_latch = pendmask & (1U << bit_nr);
460	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);	460	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
461	vgic_put_irq(vcpu->kvm, irq);	461	vgic_put_irq(vcpu->kvm, irq);
@@ -612,7 +612,7 @@ static int vgic_its_trigger_msi(struct kvm kvm, struct vgic_its its, · 150 unmodified lines
612	return irq_set_irqchip_state(irq->host_irq,	612	return irq_set_irqchip_state(irq->host_irq,
613	IRQCHIP_STATE_PENDING, true);	613	IRQCHIP_STATE_PENDING, true);
614		614
615	spin_lock_irqsave(&irq->irq_lock, flags);	615	raw_spin_lock_irqsave(&irq->irq_lock, flags);
616	irq->pending_latch = true;	616	irq->pending_latch = true;
617	vgic_queue_irq_unlock(kvm, irq, flags);	617	vgic_queue_irq_unlock(kvm, irq, flags);
618		618

virt/kvm/arm/vgic/vgic-mmio-v2.c+7−7

@@ -147,7 +147,7 @@ static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu, · 146 unmodified lines
147		147
148	irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);	148	irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
149		149
150	spin_lock_irqsave(&irq->irq_lock, flags);	150	raw_spin_lock_irqsave(&irq->irq_lock, flags);
151	irq->pending_latch = true;	151	irq->pending_latch = true;
152	irq->source \|= 1U << source_vcpu->vcpu_id;	152	irq->source \|= 1U << source_vcpu->vcpu_id;
153		153
@@ -191,13 +191,13 @@ static void vgic_mmio_write_target(struct kvm_vcpu *vcpu, · 37 unmodified lines
191	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);	191	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
192	int target;	192	int target;
193		193
194	spin_lock_irqsave(&irq->irq_lock, flags);	194	raw_spin_lock_irqsave(&irq->irq_lock, flags);
195		195
196	irq->targets = (val >> (i * 8)) & cpu_mask;	196	irq->targets = (val >> (i * 8)) & cpu_mask;
197	target = irq->targets ? __ffs(irq->targets) : 0;	197	target = irq->targets ? __ffs(irq->targets) : 0;
198	irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);	198	irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
199		199
200	spin_unlock_irqrestore(&irq->irq_lock, flags);	200	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
201	vgic_put_irq(vcpu->kvm, irq);	201	vgic_put_irq(vcpu->kvm, irq);
202	}	202	}
203	}	203	}
@@ -230,13 +230,13 @@ static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu, · 26 unmodified lines
230	for (i = 0; i < len; i++) {	230	for (i = 0; i < len; i++) {
231	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	231	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
232		232
233	spin_lock_irqsave(&irq->irq_lock, flags);	233	raw_spin_lock_irqsave(&irq->irq_lock, flags);
234		234
235	irq->source &= ~((val >> (i * 8)) & 0xff);	235	irq->source &= ~((val >> (i * 8)) & 0xff);
236	if (!irq->source)	236	if (!irq->source)
237	irq->pending_latch = false;	237	irq->pending_latch = false;
238		238
239	spin_unlock_irqrestore(&irq->irq_lock, flags);	239	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
240	vgic_put_irq(vcpu->kvm, irq);	240	vgic_put_irq(vcpu->kvm, irq);
241	}	241	}
242	}	242	}
@@ -252,7 +252,7 @@ static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu, · 9 unmodified lines
252	for (i = 0; i < len; i++) {	252	for (i = 0; i < len; i++) {
253	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	253	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
254		254
255	spin_lock_irqsave(&irq->irq_lock, flags);	255	raw_spin_lock_irqsave(&irq->irq_lock, flags);
256		256
257	irq->source \|= (val >> (i * 8)) & 0xff;	257	irq->source \|= (val >> (i * 8)) & 0xff;
258		258
@@ -260,7 +260,7 @@ static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu, · 1 unmodified line
260	irq->pending_latch = true;	260	irq->pending_latch = true;
261	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);	261	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
262	} else {	262	} else {
263	spin_unlock_irqrestore(&irq->irq_lock, flags);	263	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
264	}	264	}
265	vgic_put_irq(vcpu->kvm, irq);	265	vgic_put_irq(vcpu->kvm, irq);
266	}	266	}

virt/kvm/arm/vgic/vgic-mmio-v3.c+6−6

@@ -169,13 +169,13 @@ static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, · 168 unmodified lines
169	if (!irq)	169	if (!irq)
170	return;	170	return;
171		171
172	spin_lock_irqsave(&irq->irq_lock, flags);	172	raw_spin_lock_irqsave(&irq->irq_lock, flags);
173		173
174	/* We only care about and preserve Aff0, Aff1 and Aff2. */	174	/* We only care about and preserve Aff0, Aff1 and Aff2. */
175	irq->mpidr = val & GENMASK(23, 0);	175	irq->mpidr = val & GENMASK(23, 0);
176	irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);	176	irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
177		177
178	spin_unlock_irqrestore(&irq->irq_lock, flags);	178	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
179	vgic_put_irq(vcpu->kvm, irq);	179	vgic_put_irq(vcpu->kvm, irq);
180	}	180	}
181		181
@@ -281,7 +281,7 @@ static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, · 99 unmodified lines
281	for (i = 0; i < len * 8; i++) {	281	for (i = 0; i < len * 8; i++) {
282	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	282	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
283		283
284	spin_lock_irqsave(&irq->irq_lock, flags);	284	raw_spin_lock_irqsave(&irq->irq_lock, flags);
285	if (test_bit(i, &val)) {	285	if (test_bit(i, &val)) {
286	/*	286	/*
287	* pending_latch is set irrespective of irq type	287	* pending_latch is set irrespective of irq type
@@ -292,7 +292,7 @@ static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, · 4 unmodified lines
292	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);	292	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
293	} else {	293	} else {
294	irq->pending_latch = false;	294	irq->pending_latch = false;
295	spin_unlock_irqrestore(&irq->irq_lock, flags);	295	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
296	}	296	}
297		297
298	vgic_put_irq(vcpu->kvm, irq);	298	vgic_put_irq(vcpu->kvm, irq);
@@ -957,7 +957,7 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) · 658 unmodified lines
957		957
958	irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);	958	irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
959		959
960	spin_lock_irqsave(&irq->irq_lock, flags);	960	raw_spin_lock_irqsave(&irq->irq_lock, flags);
961		961
962	/*	962	/*
963	* An access targetting Group0 SGIs can only generate	963	* An access targetting Group0 SGIs can only generate
@@ -968,7 +968,7 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) · 4 unmodified lines
968	irq->pending_latch = true;	968	irq->pending_latch = true;
969	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);	969	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
970	} else {	970	} else {
971	spin_unlock_irqrestore(&irq->irq_lock, flags);	971	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
972	}	972	}
973		973
974	vgic_put_irq(vcpu->kvm, irq);	974	vgic_put_irq(vcpu->kvm, irq);

virt/kvm/arm/vgic/vgic-mmio.c+17−17

@@ -77,7 +77,7 @@ void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr, · 76 unmodified lines
77	for (i = 0; i < len * 8; i++) {	77	for (i = 0; i < len * 8; i++) {
78	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	78	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
79		79
80	spin_lock_irqsave(&irq->irq_lock, flags);	80	raw_spin_lock_irqsave(&irq->irq_lock, flags);
81	irq->group = !!(val & BIT(i));	81	irq->group = !!(val & BIT(i));
82	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);	82	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
83		83
@@ -120,7 +120,7 @@ void vgic_mmio_write_senable(struct kvm_vcpu *vcpu, · 36 unmodified lines
120	for_each_set_bit(i, &val, len * 8) {	120	for_each_set_bit(i, &val, len * 8) {
121	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	121	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
122		122
123	spin_lock_irqsave(&irq->irq_lock, flags);	123	raw_spin_lock_irqsave(&irq->irq_lock, flags);
124	irq->enabled = true;	124	irq->enabled = true;
125	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);	125	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
126		126
@@ -139,11 +139,11 @@ void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu, · 12 unmodified lines
139	for_each_set_bit(i, &val, len * 8) {	139	for_each_set_bit(i, &val, len * 8) {
140	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	140	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
141		141
142	spin_lock_irqsave(&irq->irq_lock, flags);	142	raw_spin_lock_irqsave(&irq->irq_lock, flags);
143		143
144	irq->enabled = false;	144	irq->enabled = false;
145		145
146	spin_unlock_irqrestore(&irq->irq_lock, flags);	146	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
147	vgic_put_irq(vcpu->kvm, irq);	147	vgic_put_irq(vcpu->kvm, irq);
148	}	148	}
149	}	149	}
@@ -160,10 +160,10 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, · 10 unmodified lines
160	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	160	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
161	unsigned long flags;	161	unsigned long flags;
162		162
163	spin_lock_irqsave(&irq->irq_lock, flags);	163	raw_spin_lock_irqsave(&irq->irq_lock, flags);
164	if (irq_is_pending(irq))	164	if (irq_is_pending(irq))
165	value \|= (1U << i);	165	value \|= (1U << i);
166	spin_unlock_irqrestore(&irq->irq_lock, flags);	166	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
167		167
168	vgic_put_irq(vcpu->kvm, irq);	168	vgic_put_irq(vcpu->kvm, irq);
169	}	169	}
@@ -215,7 +215,7 @@ void vgic_mmio_write_spending(struct kvm_vcpu *vcpu, · 45 unmodified lines
215	for_each_set_bit(i, &val, len * 8) {	215	for_each_set_bit(i, &val, len * 8) {
216	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	216	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
217		217
218	spin_lock_irqsave(&irq->irq_lock, flags);	218	raw_spin_lock_irqsave(&irq->irq_lock, flags);
219	if (irq->hw)	219	if (irq->hw)
220	vgic_hw_irq_spending(vcpu, irq, is_uaccess);	220	vgic_hw_irq_spending(vcpu, irq, is_uaccess);
221	else	221	else
@@ -262,14 +262,14 @@ void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu, · 40 unmodified lines
262	for_each_set_bit(i, &val, len * 8) {	262	for_each_set_bit(i, &val, len * 8) {
263	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	263	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
264		264
265	spin_lock_irqsave(&irq->irq_lock, flags);	265	raw_spin_lock_irqsave(&irq->irq_lock, flags);
266		266
267	if (irq->hw)	267	if (irq->hw)
268	vgic_hw_irq_cpending(vcpu, irq, is_uaccess);	268	vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
269	else	269	else
270	irq->pending_latch = false;	270	irq->pending_latch = false;
271		271
272	spin_unlock_irqrestore(&irq->irq_lock, flags);	272	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
273	vgic_put_irq(vcpu->kvm, irq);	273	vgic_put_irq(vcpu->kvm, irq);
274	}	274	}
275	}	275	}
@@ -311,7 +311,7 @@ static void vgic_mmio_change_active(struct kvm_vcpu vcpu, struct vgic_irq irq, · 35 unmodified lines
311	unsigned long flags;	311	unsigned long flags;
312	struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();	312	struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();
313		313
314	spin_lock_irqsave(&irq->irq_lock, flags);	314	raw_spin_lock_irqsave(&irq->irq_lock, flags);
315		315
316	if (irq->hw) {	316	if (irq->hw) {
317	vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);	317	vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
@@ -342,7 +342,7 @@ static void vgic_mmio_change_active(struct kvm_vcpu vcpu, struct vgic_irq irq, · 24 unmodified lines
342	if (irq->active)	342	if (irq->active)
343	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);	343	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
344	else	344	else
345	spin_unlock_irqrestore(&irq->irq_lock, flags);	345	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
346	}	346	}
347		347
348	/*	348	/*
@@ -485,10 +485,10 @@ void vgic_mmio_write_priority(struct kvm_vcpu *vcpu, · 136 unmodified lines
485	for (i = 0; i < len; i++) {	485	for (i = 0; i < len; i++) {
486	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	486	struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
487		487
488	spin_lock_irqsave(&irq->irq_lock, flags);	488	raw_spin_lock_irqsave(&irq->irq_lock, flags);
489	/* Narrow the priority range to what we actually support */	489	/* Narrow the priority range to what we actually support */
490	irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);	490	irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
491	spin_unlock_irqrestore(&irq->irq_lock, flags);	491	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
492		492
493	vgic_put_irq(vcpu->kvm, irq);	493	vgic_put_irq(vcpu->kvm, irq);
494	}	494	}
@@ -534,14 +534,14 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu, · 39 unmodified lines
534	continue;	534	continue;
535		535
536	irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);	536	irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
537	spin_lock_irqsave(&irq->irq_lock, flags);	537	raw_spin_lock_irqsave(&irq->irq_lock, flags);
538		538
539	if (test_bit(i * 2 + 1, &val))	539	if (test_bit(i * 2 + 1, &val))
540	irq->config = VGIC_CONFIG_EDGE;	540	irq->config = VGIC_CONFIG_EDGE;
541	else	541	else
542	irq->config = VGIC_CONFIG_LEVEL;	542	irq->config = VGIC_CONFIG_LEVEL;
543		543
544	spin_unlock_irqrestore(&irq->irq_lock, flags);	544	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
545	vgic_put_irq(vcpu->kvm, irq);	545	vgic_put_irq(vcpu->kvm, irq);
546	}	546	}
547	}	547	}
@@ -590,12 +590,12 @@ void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid, · 42 unmodified lines
590	* restore irq config before line level.	590	* restore irq config before line level.
591	*/	591	*/
592	new_level = !!(val & (1U << i));	592	new_level = !!(val & (1U << i));
593	spin_lock_irqsave(&irq->irq_lock, flags);	593	raw_spin_lock_irqsave(&irq->irq_lock, flags);
594	irq->line_level = new_level;	594	irq->line_level = new_level;
595	if (new_level)	595	if (new_level)
596	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);	596	vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
597	else	597	else
598	spin_unlock_irqrestore(&irq->irq_lock, flags);	598	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
599		599
600	vgic_put_irq(vcpu->kvm, irq);	600	vgic_put_irq(vcpu->kvm, irq);
601	}	601	}

virt/kvm/arm/vgic/vgic-v2.c+2−2

@@ -84,7 +84,7 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) · 83 unmodified lines
84		84
85	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);	85	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
86		86
87	spin_lock(&irq->irq_lock);	87	raw_spin_lock(&irq->irq_lock);
88		88
89	/* Always preserve the active bit */	89	/* Always preserve the active bit */
90	irq->active = !!(val & GICH_LR_ACTIVE_BIT);	90	irq->active = !!(val & GICH_LR_ACTIVE_BIT);
@@ -127,7 +127,7 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) · 36 unmodified lines
127	vgic_irq_set_phys_active(irq, false);	127	vgic_irq_set_phys_active(irq, false);
128	}	128	}
129		129
130	spin_unlock(&irq->irq_lock);	130	raw_spin_unlock(&irq->irq_lock);
131	vgic_put_irq(vcpu->kvm, irq);	131	vgic_put_irq(vcpu->kvm, irq);
132	}	132	}
133		133

virt/kvm/arm/vgic/vgic-v3.c+4−4

@@ -76,7 +76,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) · 75 unmodified lines
76	if (!irq) /* An LPI could have been unmapped. */	76	if (!irq) /* An LPI could have been unmapped. */
77	continue;	77	continue;
78		78
79	spin_lock(&irq->irq_lock);	79	raw_spin_lock(&irq->irq_lock);
80		80
81	/* Always preserve the active bit */	81	/* Always preserve the active bit */
82	irq->active = !!(val & ICH_LR_ACTIVE_BIT);	82	irq->active = !!(val & ICH_LR_ACTIVE_BIT);
@@ -119,7 +119,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) · 36 unmodified lines
119	vgic_irq_set_phys_active(irq, false);	119	vgic_irq_set_phys_active(irq, false);
120	}	120	}
121		121
122	spin_unlock(&irq->irq_lock);	122	raw_spin_unlock(&irq->irq_lock);
123	vgic_put_irq(vcpu->kvm, irq);	123	vgic_put_irq(vcpu->kvm, irq);
124	}	124	}
125		125
@@ -347,9 +347,9 @@ retry: · 221 unmodified lines
347		347
348	status = val & (1 << bit_nr);	348	status = val & (1 << bit_nr);
349		349
350	spin_lock_irqsave(&irq->irq_lock, flags);	350	raw_spin_lock_irqsave(&irq->irq_lock, flags);
351	if (irq->target_vcpu != vcpu) {	351	if (irq->target_vcpu != vcpu) {
352	spin_unlock_irqrestore(&irq->irq_lock, flags);	352	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
353	goto retry;	353	goto retry;
354	}	354	}
355	irq->pending_latch = status;	355	irq->pending_latch = status;

virt/kvm/arm/vgic/vgic.c+59−59

  * When taking more than one ap_list_lock at the same time, always take the
  * lowest numbered VCPU's ap_list_lock first, so:
  *   vcpuX->vcpu_id < vcpuY->vcpu_id:
- *     spin_lock(vcpuX->arch.vgic_cpu.ap_list_lock);
+ *     raw_spin_lock(vcpuX->arch.vgic_cpu.ap_list_lock);
- *     spin_lock(vcpuY->arch.vgic_cpu.ap_list_lock);
+ *     raw_spin_lock(vcpuY->arch.vgic_cpu.ap_list_lock);
  *
  * Since the VGIC must support injecting virtual interrupts from ISRs, we have
- * to use the spin_lock_irqsave/spin_unlock_irqrestore versions of outer
+ * to use the raw_spin_lock_irqsave/raw_spin_unlock_irqrestore versions of outer
  * spinlocks for any lock that may be taken while injecting an interrupt.
  */
 	struct vgic_irq *irq = NULL;
 	unsigned long flags;
-	spin_lock_irqsave(&dist->lpi_list_lock, flags);
+	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
 	list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
 		if (irq->intid != intid)
 	irq = NULL;
 out_unlock:
-	spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
+	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
 	return irq;
 }
 	if (irq->intid < VGIC_MIN_LPI)
 		return;
-	spin_lock_irqsave(&dist->lpi_list_lock, flags);
+	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
 	if (!kref_put(&irq->refcount, vgic_irq_release)) {
-		spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
+		raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
 		return;
 	};
 	list_del(&irq->lpi_list);
 	dist->lpi_list_count--;
-	spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
+	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
 	kfree(irq);
 }
 	bool penda, pendb;
 	int ret;
-	spin_lock(&irqa->irq_lock);
+	raw_spin_lock(&irqa->irq_lock);
-	spin_lock_nested(&irqb->irq_lock, SINGLE_DEPTH_NESTING);
+	raw_spin_lock_nested(&irqb->irq_lock, SINGLE_DEPTH_NESTING);
 	if (irqa->active || irqb->active) {
 		ret = (int)irqb->active - (int)irqa->active;
 	/* Both pending and enabled, sort by priority */
 	ret = irqa->priority - irqb->priority;
 out:
-	spin_unlock(&irqb->irq_lock);
+	raw_spin_unlock(&irqb->irq_lock);
-	spin_unlock(&irqa->irq_lock);
+	raw_spin_unlock(&irqa->irq_lock);
 	return ret;
 }
 		 * not need to be inserted into an ap_list and there is also
 		 * no more work for us to do.
 		 */
-		spin_unlock_irqrestore(&irq->irq_lock, flags);
+		raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 		/*
 		 * We have to kick the VCPU here, because we could be
 	 * We must unlock the irq lock to take the ap_list_lock where
 	 * we are going to insert this new pending interrupt.
 	 */
-	spin_unlock_irqrestore(&irq->irq_lock, flags);
+	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 	/* someone can do stuff here, which we re-check below */
-	spin_lock_irqsave(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
+	raw_spin_lock_irqsave(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
-	spin_lock(&irq->irq_lock);
+	raw_spin_lock(&irq->irq_lock);
 	/*
 	 * Did something change behind our backs?
 	 */
 	if (unlikely(irq->vcpu || vcpu != vgic_target_oracle(irq))) {
-		spin_unlock(&irq->irq_lock);
+		raw_spin_unlock(&irq->irq_lock);
-		spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
+		raw_spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock,
+					   flags);
-		spin_lock_irqsave(&irq->irq_lock, flags);
+		raw_spin_lock_irqsave(&irq->irq_lock, flags);
 		goto retry;
 	}
 	list_add_tail(&irq->ap_list, &vcpu->arch.vgic_cpu.ap_list_head);
 	irq->vcpu = vcpu;
-	spin_unlock(&irq->irq_lock);
+	raw_spin_unlock(&irq->irq_lock);
-	spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
+	raw_spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
 	kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
 	kvm_vcpu_kick(vcpu);
 	if (!irq)
 		return -EINVAL;
-	spin_lock_irqsave(&irq->irq_lock, flags);
+	raw_spin_lock_irqsave(&irq->irq_lock, flags);
 	if (!vgic_validate_injection(irq, level, owner)) {
 		/* Nothing to see here, move along... */
-		spin_unlock_irqrestore(&irq->irq_lock, flags);
+		raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 		vgic_put_irq(kvm, irq);
 		return 0;
 	}
 	BUG_ON(!irq);
-	spin_lock_irqsave(&irq->irq_lock, flags);
+	raw_spin_lock_irqsave(&irq->irq_lock, flags);
 	ret = kvm_vgic_map_irq(vcpu, irq, host_irq, get_input_level);
-	spin_unlock_irqrestore(&irq->irq_lock, flags);
+	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 	vgic_put_irq(vcpu->kvm, irq);
 	return ret;
 	if (!irq->hw)
 		goto out;
-	spin_lock_irqsave(&irq->irq_lock, flags);
+	raw_spin_lock_irqsave(&irq->irq_lock, flags);
 	irq->active = false;
 	irq->pending_latch = false;
 	irq->line_level = false;
-	spin_unlock_irqrestore(&irq->irq_lock, flags);
+	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 out:
 	vgic_put_irq(vcpu->kvm, irq);
 }
 	irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
 	BUG_ON(!irq);
-	spin_lock_irqsave(&irq->irq_lock, flags);
+	raw_spin_lock_irqsave(&irq->irq_lock, flags);
 	kvm_vgic_unmap_irq(irq);
-	spin_unlock_irqrestore(&irq->irq_lock, flags);
+	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 	vgic_put_irq(vcpu->kvm, irq);
 	return 0;
 		return -EINVAL;
 	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
-	spin_lock_irqsave(&irq->irq_lock, flags);
+	raw_spin_lock_irqsave(&irq->irq_lock, flags);
 	if (irq->owner && irq->owner != owner)
 		ret = -EEXIST;
 	else
 		irq->owner = owner;
-	spin_unlock_irqrestore(&irq->irq_lock, flags);
+	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 	return ret;
 }
 	DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
 retry:
-	spin_lock(&vgic_cpu->ap_list_lock);
+	raw_spin_lock(&vgic_cpu->ap_list_lock);
 	list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
 		struct kvm_vcpu *target_vcpu, *vcpuA, *vcpuB;
 		bool target_vcpu_needs_kick = false;
-		spin_lock(&irq->irq_lock);
+		raw_spin_lock(&irq->irq_lock);
 		BUG_ON(vcpu != irq->vcpu);
 			 */
 			list_del(&irq->ap_list);
 			irq->vcpu = NULL;
-			spin_unlock(&irq->irq_lock);
+			raw_spin_unlock(&irq->irq_lock);
 			/*
 			 * This vgic_put_irq call matches the
 		if (target_vcpu == vcpu) {
 			/* We're on the right CPU */
-			spin_unlock(&irq->irq_lock);
+			raw_spin_unlock(&irq->irq_lock);
 			continue;
 		}
 		/* This interrupt looks like it has to be migrated. */
-		spin_unlock(&irq->irq_lock);
+		raw_spin_unlock(&irq->irq_lock);
-		spin_unlock(&vgic_cpu->ap_list_lock);
+		raw_spin_unlock(&vgic_cpu->ap_list_lock);
 		/*
 		 * Ensure locking order by always locking the smallest
 			vcpuB = vcpu;
 		}
-		spin_lock(&vcpuA->arch.vgic_cpu.ap_list_lock);
+		raw_spin_lock(&vcpuA->arch.vgic_cpu.ap_list_lock);
-		spin_lock_nested(&vcpuB->arch.vgic_cpu.ap_list_lock,
+		raw_spin_lock_nested(&vcpuB->arch.vgic_cpu.ap_list_lock,
-				 SINGLE_DEPTH_NESTING);
+				      SINGLE_DEPTH_NESTING);
-		spin_lock(&irq->irq_lock);
+		raw_spin_lock(&irq->irq_lock);
 		/*
 		 * If the affinity has been preserved, move the
 			target_vcpu_needs_kick = true;
 		}
-		spin_unlock(&irq->irq_lock);
+		raw_spin_unlock(&irq->irq_lock);
-		spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
+		raw_spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
-		spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
+		raw_spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
 		if (target_vcpu_needs_kick) {
 			kvm_make_request(KVM_REQ_IRQ_PENDING, target_vcpu);
 		goto retry;
 	}
-	spin_unlock(&vgic_cpu->ap_list_lock);
+	raw_spin_unlock(&vgic_cpu->ap_list_lock);
 }
 static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu)
 	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
 		int w;
-		spin_lock(&irq->irq_lock);
+		raw_spin_lock(&irq->irq_lock);
 		/* GICv2 SGIs can count for more than one... */
 		w = vgic_irq_get_lr_count(irq);
-		spin_unlock(&irq->irq_lock);
+		raw_spin_unlock(&irq->irq_lock);
 		count += w;
 		*multi_sgi |= (w > 1);
 	count = 0;
 	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
-		spin_lock(&irq->irq_lock);
+		raw_spin_lock(&irq->irq_lock);
 		/*
 		 * If we have multi-SGIs in the pipeline, we need to
 		 * the AP list has been sorted already.
 		 */
 		if (multi_sgi && irq->priority > prio) {
-			spin_unlock(&irq->irq_lock);
+			_raw_spin_unlock(&irq->irq_lock);
 			break;
 		}
 				prio = irq->priority;
 		}
-		spin_unlock(&irq->irq_lock);
+		raw_spin_unlock(&irq->irq_lock);
 		if (count == kvm_vgic_global_state.nr_lr) {
 			if (!list_is_last(&irq->ap_list,
 	DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
-	spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
+	raw_spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
 	vgic_flush_lr_state(vcpu);
-	spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
+	raw_spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
 	if (can_access_vgic_from_kernel())
 		vgic_restore_state(vcpu);
 	vgic_get_vmcr(vcpu, &vmcr);
-	spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags);
+	raw_spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags);
 	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
-		spin_lock(&irq->irq_lock);
+		raw_spin_lock(&irq->irq_lock);
 		pending = irq_is_pending(irq) && irq->enabled &&
 			  !irq->active &&
 			  irq->priority < vmcr.pmr;
-		spin_unlock(&irq->irq_lock);
+		raw_spin_unlock(&irq->irq_lock);
 		if (pending)
 			break;
 	}
-	spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags);
+	raw_spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags);
 	return pending;
 }
 		return false;
 	irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
-	spin_lock_irqsave(&irq->irq_lock, flags);
+	raw_spin_lock_irqsave(&irq->irq_lock, flags);
 	map_is_active = irq->hw && irq->active;
-	spin_unlock_irqrestore(&irq->irq_lock, flags);
+	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 	vgic_put_irq(vcpu->kvm, irq);
 	return map_is_active;
 }