lael-labs/linux

CREDITS+1−2

@@ -2808,8 +2808,7 @@ S: Ottawa, Ontario · 2807 unmodified lines
2808	S: Canada K2P 0X8	2808	S: Canada K2P 0X8
2809		2809
2810	N: Mikael Pettersson	2810	N: Mikael Pettersson
2811	E: mikpe@it.uu.se	2811	E: mikpelinux@gmail.com
2812	W: http://user.it.uu.se/~mikpe/linux/
2813	D: Miscellaneous fixes	2812	D: Miscellaneous fixes
2814		2813
2815	N: Reed H. Petty	2814	N: Reed H. Petty

Documentation/arm64/tagged-pointers.txt+7−7

Documentation/block/00-INDEX+2−0

 	- Generic Block Device Capability (/sys/block/<device>/capability)
 cfq-iosched.txt
 	- CFQ IO scheduler tunables
+cmdline-partition.txt
+	- how to specify block device partitions on kernel command line
 data-integrity.txt
 	- Block data integrity
 deadline-iosched.txt

Documentation/block/cmdline-partition.txt+4−4

@@ -1,9 +1,9 @@
1	Embedded device command line partition	1	Embedded device command line partition parsing
2	=====================================================================	2	=====================================================================
3		3
4	Read block device partition table from command line.	4	Support for reading the block device partition table from the command line.
5	The partition used for fixed block device (eMMC) embedded device.	5	It is typically used for fixed block (eMMC) embedded devices.
6	It is no MBR, save storage space. Bootloader can be easily accessed	6	It has no MBR, so saves storage space. Bootloader can be easily accessed
7	by absolute address of data on the block device.	7	by absolute address of data on the block device.
8	Users can easily change the partition.	8	Users can easily change the partition.
9		9

Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt+5−5

@@ -1,11 +1,11 @@
1	* Samsung Exynos specific extensions to the Synopsis Designware Mobile	1	* Samsung Exynos specific extensions to the Synopsys Designware Mobile
2	Storage Host Controller	2	Storage Host Controller
3		3
4	The Synopsis designware mobile storage host controller is used to interface	4	The Synopsys designware mobile storage host controller is used to interface
5	a SoC with storage medium such as eMMC or SD/MMC cards. This file documents	5	a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
6	differences between the core Synopsis dw mshc controller properties described	6	differences between the core Synopsys dw mshc controller properties described
7	by synopsis-dw-mshc.txt and the properties used by the Samsung Exynos specific	7	by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
8	extensions to the Synopsis Designware Mobile Storage Host Controller.	8	extensions to the Synopsys Designware Mobile Storage Host Controller.
9		9
10	Required Properties:	10	Required Properties:
11		11

Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt+5−5

@@ -1,11 +1,11 @@
1	* Rockchip specific extensions to the Synopsis Designware Mobile	1	* Rockchip specific extensions to the Synopsys Designware Mobile
2	Storage Host Controller	2	Storage Host Controller
3		3
4	The Synopsis designware mobile storage host controller is used to interface	4	The Synopsys designware mobile storage host controller is used to interface
5	a SoC with storage medium such as eMMC or SD/MMC cards. This file documents	5	a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
6	differences between the core Synopsis dw mshc controller properties described	6	differences between the core Synopsys dw mshc controller properties described
7	by synopsis-dw-mshc.txt and the properties used by the Rockchip specific	7	by synopsys-dw-mshc.txt and the properties used by the Rockchip specific
8	extensions to the Synopsis Designware Mobile Storage Host Controller.	8	extensions to the Synopsys Designware Mobile Storage Host Controller.
9		9
10	Required Properties:	10	Required Properties:
11		11

Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txtrenamed from Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt+4−4

@@ -1,14 +1,14 @@
1	* Synopsis Designware Mobile Storage Host Controller	1	* Synopsys Designware Mobile Storage Host Controller
2		2
3	The Synopsis designware mobile storage host controller is used to interface	3	The Synopsys designware mobile storage host controller is used to interface
4	a SoC with storage medium such as eMMC or SD/MMC cards. This file documents	4	a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
5	differences between the core mmc properties described by mmc.txt and the	5	differences between the core mmc properties described by mmc.txt and the
6	properties used by the Synopsis Designware Mobile Storage Host Controller.	6	properties used by the Synopsys Designware Mobile Storage Host Controller.
7		7
8	Required Properties:	8	Required Properties:
9		9
10	* compatible: should be	10	* compatible: should be
11	- snps,dw-mshc: for controllers compliant with synopsis dw-mshc.	11	- snps,dw-mshc: for controllers compliant with synopsys dw-mshc.
12	* #address-cells: should be 1.	12	* #address-cells: should be 1.
13	* #size-cells: should be 0.	13	* #size-cells: should be 0.
14		14

Documentation/devicetree/bindings/mmc/tmio_mmc.txt+10−7

 described in mmc.txt, can be used. Additionally the following tmio_mmc-specific
 optional bindings can be used.
+Required properties:
+- compatible:	"renesas,sdhi-shmobile" - a generic sh-mobile SDHI unit
+		"renesas,sdhi-sh7372" - SDHI IP on SH7372 SoC
+		"renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
+		"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
+		"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
+		"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
+		"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
+		"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
 Optional properties:
 - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
-When used with Renesas SDHI hardware, the following compatibility strings
-configure various model-specific properties:
-"renesas,sh7372-sdhi":	(default) compatible with SH7372
-"renesas,r8a7740-sdhi":	compatible with R8A7740: certain MMC/SD commands have to
-			wait for the interface to become idle.

Documentation/devicetree/bindings/net/fsl-tsec-phy.txt+17−1

 Clock Properties:
+  - fsl,cksel        Timer reference clock source.
   - fsl,tclk-period  Timer reference clock period in nanoseconds.
   - fsl,tmr-prsc     Prescaler, divides the output clock.
   - fsl,tmr-add      Frequency compensation value.
   clock. You must choose these carefully for the clock to work right.
   Here is how to figure good values:
-  TimerOsc     = system clock               MHz
+  TimerOsc     = selected reference clock   MHz
   tclk_period  = desired clock period       nanoseconds
   NominalFreq  = 1000 / tclk_period         MHz
   FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
   Pulse Per Second (PPS) signal, since this will be offered to the PPS
   subsystem to synchronize the Linux clock.
+  Reference clock source is determined by the value, which is holded
+  in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
+  value, which will be directly written in those bits, that is why,
+  according to reference manual, the next clock sources can be used:
+  <0> - external high precision timer reference clock (TSEC_TMR_CLK
+        input is used for this purpose);
+  <1> - eTSEC system clock;
+  <2> - eTSEC1 transmit clock;
+  <3> - RTC clock input.
+  When this attribute is not used, eTSEC system clock will serve as
+  IEEE 1588 timer reference clock.
 Example:
 	ptp_clock@24E00 {
 		reg = <0x24E00 0xB0>;
 		interrupts = <12 0x8 13 0x8>;
 		interrupt-parent = < &ipic >;
+		fsl,cksel       = <1>;
 		fsl,tclk-period = <10>;
 		fsl,tmr-prsc    = <100>;
 		fsl,tmr-add     = <0x999999A4>;

Documentation/devicetree/bindings/pci/designware-pcie.txt+1−1

@@ -1,4 +1,4 @@
1	* Synopsis Designware PCIe interface	1	* Synopsys Designware PCIe interface
2		2
3	Required properties:	3	Required properties:
4	- compatible: should contain "snps,dw-pcie" to identify the	4	- compatible: should contain "snps,dw-pcie" to identify the

Documentation/devicetree/bindings/serial/qca,ar9330-uart.txtrenamed from Documentation/devicetree/bindings/tty/serial/qca,ar9330-uart.txt+0−0

File renamed without changes.

Documentation/filesystems/vfs.txt+7−7

 	ssize_t (*listxattr) (struct dentry *, char *, size_t);
 	int (*removexattr) (struct dentry *, const char *);
 	void (*update_time)(struct inode *, struct timespec *, int);
-	int (*atomic_open)(struct inode *, struct dentry *,
+	int (*atomic_open)(struct inode *, struct dentry *, struct file *,
+			unsigned open_flag, umode_t create_mode, int *opened);
 	int (*tmpfile) (struct inode *, struct dentry *, umode_t);
-} ____cacheline_aligned;
-				struct file *, unsigned open_flag,
-				umode_t create_mode, int *opened);
 };
 Again, all methods are called without any locks being held, unless
   	method the filesystem can look up, possibly create and open the file in
   	one atomic operation.  If it cannot perform this (e.g. the file type
   	turned out to be wrong) it may signal this by returning 1 instead of
-  	usual 0 or -ve .  This method is only called if the last
+	usual 0 or -ve .  This method is only called if the last component is
-  	component is negative or needs lookup.  Cached positive dentries are
+	negative or needs lookup.  Cached positive dentries are still handled by
-  	still handled by f_op->open().
+	f_op->open().  If the file was created, the FILE_CREATED flag should be
+	set in "opened".  In case of O_EXCL the method must only succeed if the
+	file didn't exist and hence FILE_CREATED shall always be set on success.
   tmpfile: called in the end of O_TMPFILE open().  Optional, equivalent to
 	atomically creating, opening and unlinking a file in given directory.

Documentation/kernel-parameters.txt+9−1

 			Format: <io>,<irq>,<mode>
 			See header of drivers/net/hamradio/baycom_ser_hdx.c.
+	blkdevparts=	Manual partition parsing of block device(s) for
+			embedded devices based on command line input.
+			See Documentation/block/cmdline-partition.txt
 	boot_delay=	Milliseconds to delay each printk during boot.
 			Values larger than 10 seconds (10000) are changed to
 			no delay (0).
 			pages. In the event, a node is too small to have both
 			kernelcore and Movable pages, kernelcore pages will
 			take priority and other nodes will have a larger number
-			of kernelcore pages.  The Movable zone is used for the
+			of Movable pages.  The Movable zone is used for the
 			allocation of pages that may be reclaimed or moved
 			by the page migration subsystem.  This means that
 			HugeTLB pages may not be allocated from this zone.
 				the unplug protocol
 			never -- do not unplug even if version check succeeds
+	xen_nopvspin	[X86,XEN]
+			Disables the ticketlock slowpath using Xen PV
+			optimizations.
 	xirc2ps_cs=	[NET,PCMCIA]
 			Format:
 			<irq>,<irq_mask>,<io>,<full_duplex>,<do_sound>,<lockup_hack>[,<irq2>[,<irq3>[,<irq4>]]]

Documentation/networking/bonding.txt+6−0

 To remove an ARP target:
 # echo -192.168.0.100 > /sys/class/net/bond0/bonding/arp_ip_target
+To configure the interval between learning packet transmits:
+# echo 12 > /sys/class/net/bond0/bonding/lp_interval
+	NOTE: the lp_inteval is the number of seconds between instances where
+the bonding driver sends learning packets to each slaves peer switch.  The
+default interval is 1 second.
 Example Configuration
 ---------------------
 	We begin with the same example that is shown in section 3.3,

Documentation/sound/alsa/HD-Audio-Models.txt+6−0

   imac27	IMac 27 Inch
   auto		BIOS setup (default)
+Cirrus Logic CS4208
+===================
+  mba6		MacBook Air 6,1 and 6,2
+  gpio0		Enable GPIO 0 amp
+  auto		BIOS setup (default)
 VIA VT17xx/VT18xx/VT20xx
 ========================
   auto		BIOS setup (default)

MAINTAINERS+33−7

@@ -824,15 +824,21 @@ S: Maintained · 823 unmodified lines
824	F: arch/arm/mach-gemini/	824	F: arch/arm/mach-gemini/
825		825
826	ARM/CSR SIRFPRIMA2 MACHINE SUPPORT	826	ARM/CSR SIRFPRIMA2 MACHINE SUPPORT
827	M: Barry Song <baohua.song@csr.com>	827	M: Barry Song <baohua@kernel.org>
828	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)	828	L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
829	T: git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git	829	T: git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git
830	S: Maintained	830	S: Maintained
831	F: arch/arm/mach-prima2/	831	F: arch/arm/mach-prima2/
		832	F: drivers/clk/clk-prima2.c
		833	F: drivers/clocksource/timer-prima2.c
		834	F: drivers/clocksource/timer-marco.c
832	F: drivers/dma/sirf-dma.c	835	F: drivers/dma/sirf-dma.c
833	F: drivers/i2c/busses/i2c-sirf.c	836	F: drivers/i2c/busses/i2c-sirf.c
		837	F: drivers/input/misc/sirfsoc-onkey.c
		838	F: drivers/irqchip/irq-sirfsoc.c
834	F: drivers/mmc/host/sdhci-sirf.c	839	F: drivers/mmc/host/sdhci-sirf.c
835	F: drivers/pinctrl/sirf/	840	F: drivers/pinctrl/sirf/
		841	F: drivers/rtc/rtc-sirfsoc.c
836	F: drivers/spi/spi-sirf.c	842	F: drivers/spi/spi-sirf.c
837		843
838	ARM/EBSA110 MACHINE SUPPORT	844	ARM/EBSA110 MACHINE SUPPORT
@@ -1812,7 +1818,8 @@ S: Supported · 973 unmodified lines
1812	F: drivers/net/ethernet/broadcom/bnx2x/	1818	F: drivers/net/ethernet/broadcom/bnx2x/
1813		1819
1814	BROADCOM BCM281XX/BCM11XXX ARM ARCHITECTURE	1820	BROADCOM BCM281XX/BCM11XXX ARM ARCHITECTURE
1815	M: Christian Daudt <csd@broadcom.com>	1821	M: Christian Daudt <bcm@fixthebug.org>
		1822	L: bcm-kernel-feedback-list@broadcom.com
1816	T: git git://git.github.com/broadcom/bcm11351	1823	T: git git://git.github.com/broadcom/bcm11351
1817	S: Maintained	1824	S: Maintained
1818	F: arch/arm/mach-bcm/	1825	F: arch/arm/mach-bcm/
@@ -2639,6 +2646,18 @@ F: include/linux/device-mapper.h · 820 unmodified lines
2639	F: include/linux/dm-*.h	2646	F: include/linux/dm-*.h
2640	F: include/uapi/linux/dm-*.h	2647	F: include/uapi/linux/dm-*.h
2641		2648
		2649	DIGI NEO AND CLASSIC PCI PRODUCTS
		2650	M: Lidza Louina <lidza.louina@gmail.com>
		2651	L: driverdev-devel@linuxdriverproject.org
		2652	S: Maintained
		2653	F: drivers/staging/dgnc/
		2654
		2655	DIGI EPCA PCI PRODUCTS
		2656	M: Lidza Louina <lidza.louina@gmail.com>
		2657	L: driverdev-devel@linuxdriverproject.org
		2658	S: Maintained
		2659	F: drivers/staging/dgap/
		2660
2642	DIOLAN U2C-12 I2C DRIVER	2661	DIOLAN U2C-12 I2C DRIVER
2643	M: Guenter Roeck <linux@roeck-us.net>	2662	M: Guenter Roeck <linux@roeck-us.net>
2644	L: linux-i2c@vger.kernel.org	2663	L: linux-i2c@vger.kernel.org
@@ -4457,6 +4476,13 @@ L: linux-serial@vger.kernel.org · 1812 unmodified lines
4457	S: Maintained	4476	S: Maintained
4458	F: drivers/tty/serial/ioc3_serial.c	4477	F: drivers/tty/serial/ioc3_serial.c
4459		4478
		4479	IOMMU DRIVERS
		4480	M: Joerg Roedel <joro@8bytes.org>
		4481	L: iommu@lists.linux-foundation.org
		4482	T: git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
		4483	S: Maintained
		4484	F: drivers/iommu/
		4485
4460	IP MASQUERADING	4486	IP MASQUERADING
4461	M: Juanjo Ciarlante <jjciarla@raiz.uncu.edu.ar>	4487	M: Juanjo Ciarlante <jjciarla@raiz.uncu.edu.ar>
4462	S: Maintained	4488	S: Maintained
@@ -6595,7 +6621,7 @@ S: Obsolete · 2132 unmodified lines
6595	F: drivers/net/wireless/prism54/	6621	F: drivers/net/wireless/prism54/
6596		6622
6597	PROMISE SATA TX2/TX4 CONTROLLER LIBATA DRIVER	6623	PROMISE SATA TX2/TX4 CONTROLLER LIBATA DRIVER
6598	M: Mikael Pettersson <mikpe@it.uu.se>	6624	M: Mikael Pettersson <mikpelinux@gmail.com>
6599	L: linux-ide@vger.kernel.org	6625	L: linux-ide@vger.kernel.org
6600	S: Maintained	6626	S: Maintained
6601	F: drivers/ata/sata_promise.*	6627	F: drivers/ata/sata_promise.*
@@ -7260,9 +7286,9 @@ F: kernel/wait.c · 658 unmodified lines
7260	F: include/linux/wait.h	7286	F: include/linux/wait.h
7261		7287
7262	SCORE ARCHITECTURE	7288	SCORE ARCHITECTURE
7263	M: Chen Liqin <liqin.chen@sunplusct.com>	7289	M: Chen Liqin <liqin.linux@gmail.com>
7264	M: Lennox Wu <lennox.wu@gmail.com>	7290	M: Lennox Wu <lennox.wu@gmail.com>
7265	W: http://www.sunplusct.com	7291	W: http://www.sunplus.com
7266	S: Supported	7292	S: Supported
7267	F: arch/score/	7293	F: arch/score/
7268		7294
@@ -8726,9 +8752,8 @@ F: Documentation/hid/hiddev.txt · 1457 unmodified lines
8726	F: drivers/hid/usbhid/	8752	F: drivers/hid/usbhid/
8727		8753
8728	USB/IP DRIVERS	8754	USB/IP DRIVERS
8729	M: Matt Mooney <mfm@muteddisk.com>
8730	L: linux-usb@vger.kernel.org	8755	L: linux-usb@vger.kernel.org
8731	S: Maintained	8756	S: Orphan
8732	F: drivers/staging/usbip/	8757	F: drivers/staging/usbip/
8733		8758
8734	USB ISP116X DRIVER	8759	USB ISP116X DRIVER
@@ -9368,6 +9393,7 @@ F: arch/arm64/include/asm/xen/ · 633 unmodified lines
9368		9393
9369	XEN NETWORK BACKEND DRIVER	9394	XEN NETWORK BACKEND DRIVER
9370	M: Ian Campbell <ian.campbell@citrix.com>	9395	M: Ian Campbell <ian.campbell@citrix.com>
		9396	M: Wei Liu <wei.liu2@citrix.com>
9371	L: xen-devel@lists.xenproject.org (moderated for non-subscribers)	9397	L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
9372	L: netdev@vger.kernel.org	9398	L: netdev@vger.kernel.org
9373	S: Supported	9399	S: Supported

Makefile+1−1

@@ -1,7 +1,7 @@
1	VERSION = 3	1	VERSION = 3
2	PATCHLEVEL = 12	2	PATCHLEVEL = 12
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc1	4	EXTRAVERSION = -rc4
5	NAME = One Giant Leap for Frogkind	5	NAME = One Giant Leap for Frogkind
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION

arch/Kconfig+0−3

@@ -286,9 +286,6 @@ config HAVE_PERF_USER_STACK_DUMP · 285 unmodified lines
286	config HAVE_ARCH_JUMP_LABEL	286	config HAVE_ARCH_JUMP_LABEL
287	bool	287	bool
288		288
289	config HAVE_ARCH_MUTEX_CPU_RELAX
290	bool
291
292	config HAVE_RCU_TABLE_FREE	289	config HAVE_RCU_TABLE_FREE
293	bool	290	bool
294		291

arch/arc/include/asm/spinlock.h+8−1

 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
-	lock->slock = __ARCH_SPIN_LOCK_UNLOCKED__;
+	unsigned int tmp = __ARCH_SPIN_LOCK_UNLOCKED__;
+	__asm__ __volatile__(
+	"	ex  %0, [%1]		\n"
+	: "+r" (tmp)
+	: "r"(&(lock->slock))
+	: "memory");
 	smp_mb();
 }

arch/arc/include/asm/uaccess.h+2−2

@@ -43,7 +43,7 @@ · 42 unmodified lines
43	* Because it essentially checks if buffer end is within limit and @len is	43	* Because it essentially checks if buffer end is within limit and @len is
44	* non-ngeative, which implies that buffer start will be within limit too.	44	* non-ngeative, which implies that buffer start will be within limit too.
45	*	45	*
46	* The reason for rewriting being, for majorit yof cases, @len is generally	46	* The reason for rewriting being, for majority of cases, @len is generally
47	* compile time constant, causing first sub-expression to be compile time	47	* compile time constant, causing first sub-expression to be compile time
48	* subsumed.	48	* subsumed.
49	*	49	*
@@ -53,7 +53,7 @@ · 3 unmodified lines
53	*	53	*
54	*/	54	*/
55	#define __user_ok(addr, sz) (((sz) <= TASK_SIZE) && \	55	#define __user_ok(addr, sz) (((sz) <= TASK_SIZE) && \
56	(((addr)+(sz)) <= get_fs()))	56	((addr) <= (get_fs() - (sz))))
57	#define __access_ok(addr, sz) (unlikely(__kernel_ok) \|\| \	57	#define __access_ok(addr, sz) (unlikely(__kernel_ok) \|\| \
58	likely(__user_ok((addr), (sz))))	58	likely(__user_ok((addr), (sz))))
59		59

arch/arc/kernel/signal.c+13−12

 {
 	struct rt_sigframe __user *sf;
 	unsigned int magic;
-	int err;
 	struct pt_regs *regs = current_pt_regs();
 	/* Always make any pending restarted system calls return -EINTR */
 	if (!access_ok(VERIFY_READ, sf, sizeof(*sf)))
 		goto badframe;
-	err = restore_usr_regs(regs, sf);
+	if (__get_user(magic, &sf->sigret_magic))
-	err |= __get_user(magic, &sf->sigret_magic);
-	if (err)
 		goto badframe;
 	if (unlikely(is_do_ss_needed(magic)))
 		if (restore_altstack(&sf->uc.uc_stack))
 			goto badframe;
+	if (restore_usr_regs(regs, sf))
+		goto badframe;
 	/* Don't restart from sigreturn */
 	syscall_wont_restart(regs);
 	if (!sf)
 		return 1;
+	/*
+	 * w/o SA_SIGINFO, struct ucontext is partially populated (only
+	 * uc_mcontext/uc_sigmask) for kernel's normal user state preservation
+	 * during signal handler execution. This works for SA_SIGINFO as well
+	 * although the semantics are now overloaded (the same reg state can be
+	 * inspected by userland: but are they allowed to fiddle with it ?
+	 */
+	err |= stash_usr_regs(sf, regs, set);
 	/*
 	 * SA_SIGINFO requires 3 args to signal handler:
 	 *  #1: sig-no (common to any handler)
 		magic = MAGIC_SIGALTSTK;
 	}
-	/*
-	 * w/o SA_SIGINFO, struct ucontext is partially populated (only
-	 * uc_mcontext/uc_sigmask) for kernel's normal user state preservation
-	 * during signal handler execution. This works for SA_SIGINFO as well
-	 * although the semantics are now overloaded (the same reg state can be
-	 * inspected by userland: but are they allowed to fiddle with it ?
-	 */
-	err |= stash_usr_regs(sf, regs, set);
 	err |= __put_user(magic, &sf->sigret_magic);
 	if (err)
 		return err;

arch/arc/kernel/time.c+2−5

@@ -227,12 +227,9 @@ void __attribute__((weak)) arc_local_timer_setup(unsigned int cpu) · 226 unmodified lines
227	{	227	{
228	struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);	228	struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
229		229
230	clockevents_calc_mult_shift(clk, arc_get_core_freq(), 5);
231
232	clk->max_delta_ns = clockevent_delta2ns(ARC_TIMER_MAX, clk);
233	clk->cpumask = cpumask_of(cpu);	230	clk->cpumask = cpumask_of(cpu);
234		231	clockevents_config_and_register(clk, arc_get_core_freq(),
235	clockevents_register_device(clk);	232	0, ARC_TIMER_MAX);
236		233
237	/*	234	/*
238	* setup the per-cpu timer IRQ handler - for all cpus	235	* setup the per-cpu timer IRQ handler - for all cpus

arch/arc/kernel/unaligned.c+6−0

 		regs->status32 &= ~STATUS_DE_MASK;
 	} else {
 		regs->ret += state.instr_len;
+		/* handle zero-overhead-loop */
+		if ((regs->ret == regs->lp_end) && (regs->lp_count)) {
+			regs->ret = regs->lp_start;
+			regs->lp_count--;
+		}
 	}
 	return 0;

arch/arm/Kconfig+1−2

@@ -2217,8 +2217,7 @@ config NEON · 2216 unmodified lines
2217		2217
2218	config KERNEL_MODE_NEON	2218	config KERNEL_MODE_NEON
2219	bool "Support for NEON in kernel mode"	2219	bool "Support for NEON in kernel mode"
2220	default n	2220	depends on NEON && AEABI
2221	depends on NEON
2222	help	2221	help
2223	Say Y to include support for NEON in kernel mode.	2222	Say Y to include support for NEON in kernel mode.
2224		2223

arch/arm/boot/dts/Makefile+3−0

 dtb-$(CONFIG_ARCH_AT91)	+= sama5d34ek.dtb
 dtb-$(CONFIG_ARCH_AT91)	+= sama5d35ek.dtb
+dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
 	am335x-evm.dtb \
 	am335x-evmsk.dtb \
 	am335x-bone.dtb \
+	am335x-boneblack.dtb \
 	am3517-evm.dtb \
 	am3517_mt_ventoux.dtb \
 	am43x-epos-evm.dtb

arch/arm/boot/dts/am335x-bone-common.dtsi+262−0

@@ -0,0 +1,262 @@
	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	/ {
	10	model = "TI AM335x BeagleBone";
	11	compatible = "ti,am335x-bone", "ti,am33xx";
	12
	13	cpus {
	14	cpu@0 {
	15	cpu0-supply = <&dcdc2_reg>;
	16	};
	17	};
	18
	19	memory {
	20	device_type = "memory";
	21	reg = <0x80000000 0x10000000>; /* 256 MB */
	22	};
	23
	24	am33xx_pinmux: pinmux@44e10800 {
	25	pinctrl-names = "default";
	26	pinctrl-0 = <&clkout2_pin>;
	27
	28	user_leds_s0: user_leds_s0 {
	29	pinctrl-single,pins = <
	30	0x54 (PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a5.gpio1_21 */
	31	0x58 (PIN_OUTPUT_PULLUP \| MUX_MODE7) /* gpmc_a6.gpio1_22 */
	32	0x5c (PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a7.gpio1_23 */
	33	0x60 (PIN_OUTPUT_PULLUP \| MUX_MODE7) /* gpmc_a8.gpio1_24 */
	34	>;
	35	};
	36
	37	i2c0_pins: pinmux_i2c0_pins {
	38	pinctrl-single,pins = <
	39	0x188 (PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c0_sda.i2c0_sda */
	40	0x18c (PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c0_scl.i2c0_scl */
	41	>;
	42	};
	43
	44	uart0_pins: pinmux_uart0_pins {
	45	pinctrl-single,pins = <
	46	0x170 (PIN_INPUT_PULLUP \| MUX_MODE0) /* uart0_rxd.uart0_rxd */
	47	0x174 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* uart0_txd.uart0_txd */
	48	>;
	49	};
	50
	51	clkout2_pin: pinmux_clkout2_pin {
	52	pinctrl-single,pins = <
	53	0x1b4 (PIN_OUTPUT_PULLDOWN \| MUX_MODE3) /* xdma_event_intr1.clkout2 */
	54	>;
	55	};
	56
	57	cpsw_default: cpsw_default {
	58	pinctrl-single,pins = <
	59	/* Slave 1 */
	60	0x110 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
	61	0x114 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txen.mii1_txen */
	62	0x118 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
	63	0x11c (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txd3.mii1_txd3 */
	64	0x120 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txd2.mii1_txd2 */
	65	0x124 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txd1.mii1_txd1 */
	66	0x128 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txd0.mii1_txd0 */
	67	0x12c (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_txclk.mii1_txclk */
	68	0x130 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
	69	0x134 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
	70	0x138 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
	71	0x13c (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
	72	0x140 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
	73	>;
	74	};
	75
	76	cpsw_sleep: cpsw_sleep {
	77	pinctrl-single,pins = <
	78	/* Slave 1 reset value */
	79	0x110 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	80	0x114 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	81	0x118 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	82	0x11c (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	83	0x120 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	84	0x124 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	85	0x128 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	86	0x12c (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	87	0x130 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	88	0x134 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	89	0x138 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	90	0x13c (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	91	0x140 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	92	>;
	93	};
	94
	95	davinci_mdio_default: davinci_mdio_default {
	96	pinctrl-single,pins = <
	97	/* MDIO */
	98	0x148 (PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE0) /* mdio_data.mdio_data */
	99	0x14c (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* mdio_clk.mdio_clk */
	100	>;
	101	};
	102
	103	davinci_mdio_sleep: davinci_mdio_sleep {
	104	pinctrl-single,pins = <
	105	/* MDIO reset value */
	106	0x148 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	107	0x14c (PIN_INPUT_PULLDOWN \| MUX_MODE7)
	108	>;
	109	};
	110	};
	111
	112	ocp {
	113	uart0: serial@44e09000 {
	114	pinctrl-names = "default";
	115	pinctrl-0 = <&uart0_pins>;
	116
	117	status = "okay";
	118	};
	119
	120	musb: usb@47400000 {
	121	status = "okay";
	122
	123	control@44e10000 {
	124	status = "okay";
	125	};
	126
	127	usb-phy@47401300 {
	128	status = "okay";
	129	};
	130
	131	usb-phy@47401b00 {
	132	status = "okay";
	133	};
	134
	135	usb@47401000 {
	136	status = "okay";
	137	};
	138
	139	usb@47401800 {
	140	status = "okay";
	141	dr_mode = "host";
	142	};
	143
	144	dma-controller@07402000 {
	145	status = "okay";
	146	};
	147	};
	148
	149	i2c0: i2c@44e0b000 {
	150	pinctrl-names = "default";
	151	pinctrl-0 = <&i2c0_pins>;
	152
	153	status = "okay";
	154	clock-frequency = <400000>;
	155
	156	tps: tps@24 {
	157	reg = <0x24>;
	158	};
	159
	160	};
	161	};
	162
	163	leds {
	164	pinctrl-names = "default";
	165	pinctrl-0 = <&user_leds_s0>;
	166
	167	compatible = "gpio-leds";
	168
	169	led@2 {
	170	label = "beaglebone:green:heartbeat";
	171	gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
	172	linux,default-trigger = "heartbeat";
	173	default-state = "off";
	174	};
	175
	176	led@3 {
	177	label = "beaglebone:green:mmc0";
	178	gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
	179	linux,default-trigger = "mmc0";
	180	default-state = "off";
	181	};
	182
	183	led@4 {
	184	label = "beaglebone:green:usr2";
	185	gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
	186	default-state = "off";
	187	};
	188
	189	led@5 {
	190	label = "beaglebone:green:usr3";
	191	gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
	192	default-state = "off";
	193	};
	194	};
	195	};
	196
	197	/include/ "tps65217.dtsi"
	198
	199	&tps {
	200	regulators {
	201	dcdc1_reg: regulator@0 {
	202	regulator-always-on;
	203	};
	204
	205	dcdc2_reg: regulator@1 {
	206	/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
	207	regulator-name = "vdd_mpu";
	208	regulator-min-microvolt = <925000>;
	209	regulator-max-microvolt = <1325000>;
	210	regulator-boot-on;
	211	regulator-always-on;
	212	};
	213
	214	dcdc3_reg: regulator@2 {
	215	/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
	216	regulator-name = "vdd_core";
	217	regulator-min-microvolt = <925000>;
	218	regulator-max-microvolt = <1150000>;
	219	regulator-boot-on;
	220	regulator-always-on;
	221	};
	222
	223	ldo1_reg: regulator@3 {
	224	regulator-always-on;
	225	};
	226
	227	ldo2_reg: regulator@4 {
	228	regulator-always-on;
	229	};
	230
	231	ldo3_reg: regulator@5 {
	232	regulator-always-on;
	233	};
	234
	235	ldo4_reg: regulator@6 {
	236	regulator-always-on;
	237	};
	238	};
	239	};
	240
	241	&cpsw_emac0 {
	242	phy_id = <&davinci_mdio>, <0>;
	243	phy-mode = "mii";
	244	};
	245
	246	&cpsw_emac1 {
	247	phy_id = <&davinci_mdio>, <1>;
	248	phy-mode = "mii";
	249	};
	250
	251	&mac {
	252	pinctrl-names = "default", "sleep";
	253	pinctrl-0 = <&cpsw_default>;
	254	pinctrl-1 = <&cpsw_sleep>;
	255
	256	};
	257
	258	&davinci_mdio {
	259	pinctrl-names = "default", "sleep";
	260	pinctrl-0 = <&davinci_mdio_default>;
	261	pinctrl-1 = <&davinci_mdio_sleep>;
	262	};

arch/arm/boot/dts/am335x-bone.dts+1−255

@@ -8,258 +8,4 @@ · 7 unmodified lines
8	/dts-v1/;	8	/dts-v1/;
9		9
10	#include "am33xx.dtsi"	10	#include "am33xx.dtsi"
11		11	#include "am335x-bone-common.dtsi"
12	/ {
13	model = "TI AM335x BeagleBone";
14	compatible = "ti,am335x-bone", "ti,am33xx";
15
16	cpus {
17	cpu@0 {
18	cpu0-supply = <&dcdc2_reg>;
19	};
20	};
21
22	memory {
23	device_type = "memory";
24	reg = <0x80000000 0x10000000>; /* 256 MB */
25	};
26
27	am33xx_pinmux: pinmux@44e10800 {
28	pinctrl-names = "default";
29	pinctrl-0 = <&clkout2_pin>;
30
31	user_leds_s0: user_leds_s0 {
32	pinctrl-single,pins = <
33	0x54 (PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a5.gpio1_21 */
34	0x58 (PIN_OUTPUT_PULLUP \| MUX_MODE7) /* gpmc_a6.gpio1_22 */
35	0x5c (PIN_OUTPUT_PULLDOWN \| MUX_MODE7) /* gpmc_a7.gpio1_23 */
36	0x60 (PIN_OUTPUT_PULLUP \| MUX_MODE7) /* gpmc_a8.gpio1_24 */
37	>;
38	};
39
40	i2c0_pins: pinmux_i2c0_pins {
41	pinctrl-single,pins = <
42	0x188 (PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c0_sda.i2c0_sda */
43	0x18c (PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c0_scl.i2c0_scl */
44	>;
45	};
46
47	uart0_pins: pinmux_uart0_pins {
48	pinctrl-single,pins = <
49	0x170 (PIN_INPUT_PULLUP \| MUX_MODE0) /* uart0_rxd.uart0_rxd */
50	0x174 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* uart0_txd.uart0_txd */
51	>;
52	};
53
54	clkout2_pin: pinmux_clkout2_pin {
55	pinctrl-single,pins = <
56	0x1b4 (PIN_OUTPUT_PULLDOWN \| MUX_MODE3) /* xdma_event_intr1.clkout2 */
57	>;
58	};
59
60	cpsw_default: cpsw_default {
61	pinctrl-single,pins = <
62	/* Slave 1 */
63	0x110 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
64	0x114 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txen.mii1_txen */
65	0x118 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
66	0x11c (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txd3.mii1_txd3 */
67	0x120 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txd2.mii1_txd2 */
68	0x124 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txd1.mii1_txd1 */
69	0x128 (PIN_OUTPUT_PULLDOWN \| MUX_MODE0) /* mii1_txd0.mii1_txd0 */
70	0x12c (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_txclk.mii1_txclk */
71	0x130 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
72	0x134 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
73	0x138 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
74	0x13c (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
75	0x140 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
76	>;
77	};
78
79	cpsw_sleep: cpsw_sleep {
80	pinctrl-single,pins = <
81	/* Slave 1 reset value */
82	0x110 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
83	0x114 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
84	0x118 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
85	0x11c (PIN_INPUT_PULLDOWN \| MUX_MODE7)
86	0x120 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
87	0x124 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
88	0x128 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
89	0x12c (PIN_INPUT_PULLDOWN \| MUX_MODE7)
90	0x130 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
91	0x134 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
92	0x138 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
93	0x13c (PIN_INPUT_PULLDOWN \| MUX_MODE7)
94	0x140 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
95	>;
96	};
97
98	davinci_mdio_default: davinci_mdio_default {
99	pinctrl-single,pins = <
100	/* MDIO */
101	0x148 (PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE0) /* mdio_data.mdio_data */
102	0x14c (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* mdio_clk.mdio_clk */
103	>;
104	};
105
106	davinci_mdio_sleep: davinci_mdio_sleep {
107	pinctrl-single,pins = <
108	/* MDIO reset value */
109	0x148 (PIN_INPUT_PULLDOWN \| MUX_MODE7)
110	0x14c (PIN_INPUT_PULLDOWN \| MUX_MODE7)
111	>;
112	};
113	};
114
115	ocp {
116	uart0: serial@44e09000 {
117	pinctrl-names = "default";
118	pinctrl-0 = <&uart0_pins>;
119
120	status = "okay";
121	};
122
123	musb: usb@47400000 {
124	status = "okay";
125
126	control@44e10000 {
127	status = "okay";
128	};
129
130	usb-phy@47401300 {
131	status = "okay";
132	};
133
134	usb-phy@47401b00 {
135	status = "okay";
136	};
137
138	usb@47401000 {
139	status = "okay";
140	};
141
142	usb@47401800 {
143	status = "okay";
144	dr_mode = "host";
145	};
146
147	dma-controller@07402000 {
148	status = "okay";
149	};
150	};
151
152	i2c0: i2c@44e0b000 {
153	pinctrl-names = "default";
154	pinctrl-0 = <&i2c0_pins>;
155
156	status = "okay";
157	clock-frequency = <400000>;
158
159	tps: tps@24 {
160	reg = <0x24>;
161	};
162
163	};
164	};
165
166	leds {
167	pinctrl-names = "default";
168	pinctrl-0 = <&user_leds_s0>;
169
170	compatible = "gpio-leds";
171
172	led@2 {
173	label = "beaglebone:green:heartbeat";
174	gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
175	linux,default-trigger = "heartbeat";
176	default-state = "off";
177	};
178
179	led@3 {
180	label = "beaglebone:green:mmc0";
181	gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
182	linux,default-trigger = "mmc0";
183	default-state = "off";
184	};
185
186	led@4 {
187	label = "beaglebone:green:usr2";
188	gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
189	default-state = "off";
190	};
191
192	led@5 {
193	label = "beaglebone:green:usr3";
194	gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
195	default-state = "off";
196	};
197	};
198	};
199
200	/include/ "tps65217.dtsi"
201
202	&tps {
203	regulators {
204	dcdc1_reg: regulator@0 {
205	regulator-always-on;
206	};
207
208	dcdc2_reg: regulator@1 {
209	/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
210	regulator-name = "vdd_mpu";
211	regulator-min-microvolt = <925000>;
212	regulator-max-microvolt = <1325000>;
213	regulator-boot-on;
214	regulator-always-on;
215	};
216
217	dcdc3_reg: regulator@2 {
218	/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
219	regulator-name = "vdd_core";
220	regulator-min-microvolt = <925000>;
221	regulator-max-microvolt = <1150000>;
222	regulator-boot-on;
223	regulator-always-on;
224	};
225
226	ldo1_reg: regulator@3 {
227	regulator-always-on;
228	};
229
230	ldo2_reg: regulator@4 {
231	regulator-always-on;
232	};
233
234	ldo3_reg: regulator@5 {
235	regulator-always-on;
236	};
237
238	ldo4_reg: regulator@6 {
239	regulator-always-on;
240	};
241	};
242	};
243
244	&cpsw_emac0 {
245	phy_id = <&davinci_mdio>, <0>;
246	phy-mode = "mii";
247	};
248
249	&cpsw_emac1 {
250	phy_id = <&davinci_mdio>, <1>;
251	phy-mode = "mii";
252	};
253
254	&mac {
255	pinctrl-names = "default", "sleep";
256	pinctrl-0 = <&cpsw_default>;
257	pinctrl-1 = <&cpsw_sleep>;
258
259	};
260
261	&davinci_mdio {
262	pinctrl-names = "default", "sleep";
263	pinctrl-0 = <&davinci_mdio_default>;
264	pinctrl-1 = <&davinci_mdio_sleep>;
265	};

arch/arm/boot/dts/am335x-boneblack.dts+17−0

@@ -0,0 +1,17 @@
	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	/dts-v1/;
	9
	10	#include "am33xx.dtsi"
	11	#include "am335x-bone-common.dtsi"
	12
	13	&ldo3_reg {
	14	regulator-min-microvolt = <1800000>;
	15	regulator-max-microvolt = <1800000>;
	16	regulator-always-on;
	17	};

arch/arm/boot/dts/armada-370-netgear-rn102.dts+32−17

 	};
 	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+		pcie-controller {
+			status = "okay";
+			/* Connected to Marvell SATA controller */
+			pcie@1,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+			/* Connected to FL1009 USB 3.0 controller */
+			pcie@2,0 {
+				/* Port 1, Lane 0 */
+				status = "okay";
+			};
+		};
 		internal-regs {
 			serial@12000 {
 				clock-frequency = <200000000>;
 					marvell,pins = "mpp56";
 					marvell,function = "gpio";
 				};
+				poweroff: poweroff {
+					marvell,pins = "mpp8";
+					marvell,function = "gpio";
+				};
 			};
 			mdio {
 					pwm_polarity = <0>;
 				};
 			};
-			pcie-controller {
-				status = "okay";
-				/* Connected to Marvell SATA controller */
-				pcie@1,0 {
-					/* Port 0, Lane 0 */
-					status = "okay";
-				};
-				/* Connected to FL1009 USB 3.0 controller */
-				pcie@2,0 {
-					/* Port 1, Lane 0 */
-					status = "okay";
-				};
-			};
 		};
 	};
 		button@1 {
 			label = "Power Button";
 			linux,code = <116>;     /* KEY_POWER */
-			gpios = <&gpio1 30 1>;
+			gpios = <&gpio1 30 0>;
 		};
 		button@2 {
 		};
 	};
+	gpio_poweroff {
+		compatible = "gpio-poweroff";
+		pinctrl-0 = <&poweroff>;
+		pinctrl-names = "default";
+		gpios = <&gpio0 8 1>;
+	};
 };

arch/arm/boot/dts/armada-xp.dtsi+11−0

@@ -70,6 +70,8 @@ · 69 unmodified lines
70		70
71	timer@20300 {	71	timer@20300 {
72	compatible = "marvell,armada-xp-timer";	72	compatible = "marvell,armada-xp-timer";
		73	clocks = <&coreclk 2>, <&refclk>;
		74	clock-names = "nbclk", "fixed";
73	};	75	};
74		76
75	coreclk: mvebu-sar@18230 {	77	coreclk: mvebu-sar@18230 {
@@ -169,4 +171,13 @@ · 93 unmodified lines
169	};	171	};
170	};	172	};
171	};	173	};
		174
		175	clocks {
		176	/* 25 MHz reference crystal */
		177	refclk: oscillator {
		178	compatible = "fixed-clock";
		179	#clock-cells = <0>;
		180	clock-frequency = <25000000>;
		181	};
		182	};
172	};	183	};

arch/arm/boot/dts/at91sam9x5.dtsi+4−2

 							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA8 periph A */
 					};
-					pinctrl_uart2_rts: uart2_rts-0 {
+					pinctrl_usart2_rts: usart2_rts-0 {
 						atmel,pins =
 							<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB0 periph B */
 					};
-					pinctrl_uart2_cts: uart2_cts-0 {
+					pinctrl_usart2_cts: usart2_cts-0 {
 						atmel,pins =
 							<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB1 periph B */
 					};
 				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
 				dma-names = "rxtx";
+				pinctrl-names = "default";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
 				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
 				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
 				dma-names = "rxtx";
+				pinctrl-names = "default";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";

arch/arm/boot/dts/atlas6.dtsi+12−0

 				interrupts = <17>;
 				fifosize = <128>;
 				clocks = <&clks 13>;
+				sirf,uart-dma-rx-channel = <21>;
+				sirf,uart-dma-tx-channel = <2>;
 			};
 			uart1: uart@b0060000 {
 				interrupts = <19>;
 				fifosize = <128>;
 				clocks = <&clks 15>;
+				sirf,uart-dma-rx-channel = <6>;
+				sirf,uart-dma-tx-channel = <7>;
 			};
 			usp0: usp@b0080000 {
 				compatible = "sirf,prima2-usp";
 				reg = <0xb0080000 0x10000>;
 				interrupts = <20>;
+				fifosize = <128>;
 				clocks = <&clks 28>;
+				sirf,usp-dma-rx-channel = <17>;
+				sirf,usp-dma-tx-channel = <18>;
 			};
 			usp1: usp@b0090000 {
 				compatible = "sirf,prima2-usp";
 				reg = <0xb0090000 0x10000>;
 				interrupts = <21>;
+				fifosize = <128>;
 				clocks = <&clks 29>;
+				sirf,usp-dma-rx-channel = <14>;
+				sirf,usp-dma-tx-channel = <15>;
 			};
 			dmac0: dma-controller@b00b0000 {
 				compatible = "sirf,prima2-vip";
 				reg = <0xb00C0000 0x10000>;
 				clocks = <&clks 31>;
+				interrupts = <14>;
+				sirf,vip-dma-rx-channel = <16>;
 			};
 			spi0: spi@b00d0000 {

arch/arm/boot/dts/imx27.dtsi+3−3

@@ -187,7 +187,7 @@ · 186 unmodified lines
187	compatible = "fsl,imx27-cspi";	187	compatible = "fsl,imx27-cspi";
188	reg = <0x1000e000 0x1000>;	188	reg = <0x1000e000 0x1000>;
189	interrupts = <16>;	189	interrupts = <16>;
190	clocks = <&clks 53>, <&clks 53>;	190	clocks = <&clks 53>, <&clks 60>;
191	clock-names = "ipg", "per";	191	clock-names = "ipg", "per";
192	status = "disabled";	192	status = "disabled";
193	};	193	};
@@ -198,7 +198,7 @@ · 4 unmodified lines
198	compatible = "fsl,imx27-cspi";	198	compatible = "fsl,imx27-cspi";
199	reg = <0x1000f000 0x1000>;	199	reg = <0x1000f000 0x1000>;
200	interrupts = <15>;	200	interrupts = <15>;
201	clocks = <&clks 52>, <&clks 52>;	201	clocks = <&clks 52>, <&clks 60>;
202	clock-names = "ipg", "per";	202	clock-names = "ipg", "per";
203	status = "disabled";	203	status = "disabled";
204	};	204	};
@@ -309,7 +309,7 @@ · 104 unmodified lines
309	compatible = "fsl,imx27-cspi";	309	compatible = "fsl,imx27-cspi";
310	reg = <0x10017000 0x1000>;	310	reg = <0x10017000 0x1000>;
311	interrupts = <6>;	311	interrupts = <6>;
312	clocks = <&clks 51>, <&clks 51>;	312	clocks = <&clks 51>, <&clks 60>;
313	clock-names = "ipg", "per";	313	clock-names = "ipg", "per";
314	status = "disabled";	314	status = "disabled";
315	};	315	};

arch/arm/boot/dts/imx51.dtsi+1−1

@@ -474,7 +474,7 @@ · 473 unmodified lines
474	compatible = "fsl,imx51-pata", "fsl,imx27-pata";	474	compatible = "fsl,imx51-pata", "fsl,imx27-pata";
475	reg = <0x83fe0000 0x4000>;	475	reg = <0x83fe0000 0x4000>;
476	interrupts = <70>;	476	interrupts = <70>;
477	clocks = <&clks 161>;	477	clocks = <&clks 172>;
478	status = "disabled";	478	status = "disabled";
479	};	479	};
480		480

arch/arm/boot/dts/imx6q-pinfunc.h+2−2

@@ -207,8 +207,8 @@ · 206 unmodified lines
207	#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1	207	#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
208	#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1	208	#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
209	#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0	209	#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
210	#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0	210	#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0
211	#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1	211	#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1
212	#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0	212	#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
213	#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0	213	#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
214	#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0	214	#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0

arch/arm/boot/dts/kirkwood.dtsi+2−1

 		cpu@0 {
 			device_type = "cpu";
 			compatible = "marvell,feroceon";
+			reg = <0>;
 			clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
 			clock-names = "cpu_clk", "ddrclk", "powersave";
 		};
 		xor@60900 {
 			compatible = "marvell,orion-xor";
 			reg = <0x60900 0x100
-			       0xd0B00 0x100>;
+			       0x60B00 0x100>;
 			status = "okay";
 			clocks = <&gate_clk 16>;

arch/arm/boot/dts/omap3-beagle-xm.dts+1−1

@@ -11,7 +11,7 @@ · 10 unmodified lines
11		11
12	/ {	12	/ {
13	model = "TI OMAP3 BeagleBoard xM";	13	model = "TI OMAP3 BeagleBoard xM";
14	compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";	14	compatible = "ti,omap3-beagle-xm", "ti,omap3-beagle", "ti,omap3";
15		15
16	cpus {	16	cpus {
17	cpu@0 {	17	cpu@0 {

arch/arm/boot/dts/omap3-igep.dtsi+14−0

@@ -48,6 +48,15 @@ · 47 unmodified lines
48	>;	48	>;
49	};	49	};
50		50
		51	mcbsp2_pins: pinmux_mcbsp2_pins {
		52	pinctrl-single,pins = <
		53	0x10c (PIN_INPUT \| MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
		54	0x10e (PIN_INPUT \| MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
		55	0x110 (PIN_INPUT \| MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
		56	0x112 (PIN_OUTPUT \| MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
		57	>;
		58	};
		59
51	mmc1_pins: pinmux_mmc1_pins {	60	mmc1_pins: pinmux_mmc1_pins {
52	pinctrl-single,pins = <	61	pinctrl-single,pins = <
53	0x114 (PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */	62	0x114 (PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
@@ -93,6 +102,11 @@ · 39 unmodified lines
93	clock-frequency = <400000>;	102	clock-frequency = <400000>;
94	};	103	};
95		104
		105	&mcbsp2 {
		106	pinctrl-names = "default";
		107	pinctrl-0 = <&mcbsp2_pins>;
		108	};
		109
96	&mmc1 {	110	&mmc1 {
97	pinctrl-names = "default";	111	pinctrl-names = "default";
98	pinctrl-0 = <&mmc1_pins>;	112	pinctrl-0 = <&mmc1_pins>;

arch/arm/boot/dts/omap4-panda-common.dtsi+45−1

@@ -107,6 +107,19 @@ · 106 unmodified lines
107	*/	107	*/
108	clock-frequency = <19200000>;	108	clock-frequency = <19200000>;
109	};	109	};
		110
		111	/* regulator for wl12xx on sdio5 */
		112	wl12xx_vmmc: wl12xx_vmmc {
		113	pinctrl-names = "default";
		114	pinctrl-0 = <&wl12xx_gpio>;
		115	compatible = "regulator-fixed";
		116	regulator-name = "vwl1271";
		117	regulator-min-microvolt = <1800000>;
		118	regulator-max-microvolt = <1800000>;
		119	gpio = <&gpio2 11 0>;
		120	startup-delay-us = <70000>;
		121	enable-active-high;
		122	};
110	};	123	};
111		124
112	&omap4_pmx_wkup {	125	&omap4_pmx_wkup {
@@ -235,6 +248,33 @@ · 122 unmodified lines
235	0x1c (PIN_OUTPUT \| MUX_MODE3) /* gpio_wk8 */	248	0x1c (PIN_OUTPUT \| MUX_MODE3) /* gpio_wk8 */
236	>;	249	>;
237	};	250	};
		251
		252	/*
		253	* wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
		254	* REVISIT: Are the pull-ups needed for GPIO 48 and 49?
		255	*/
		256	wl12xx_gpio: pinmux_wl12xx_gpio {
		257	pinctrl-single,pins = <
		258	0x26 (PIN_OUTPUT \| MUX_MODE3) /* gpmc_a19.gpio_43 */
		259	0x2c (PIN_OUTPUT \| MUX_MODE3) /* gpmc_a22.gpio_46 */
		260	0x30 (PIN_OUTPUT_PULLUP \| MUX_MODE3) /* gpmc_a24.gpio_48 */
		261	0x32 (PIN_OUTPUT_PULLUP \| MUX_MODE3) /* gpmc_a25.gpio_49 */
		262	>;
		263	};
		264
		265	/* wl12xx GPIO inputs and SDIO pins */
		266	wl12xx_pins: pinmux_wl12xx_pins {
		267	pinctrl-single,pins = <
		268	0x38 (PIN_INPUT \| MUX_MODE3) /* gpmc_ncs2.gpio_52 */
		269	0x3a (PIN_INPUT \| MUX_MODE3) /* gpmc_ncs3.gpio_53 */
		270	0x108 (PIN_OUTPUT \| MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
		271	0x10a (PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
		272	0x10c (PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
		273	0x10e (PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
		274	0x110 (PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
		275	0x112 (PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
		276	>;
		277	};
238	};	278	};
239		279
240	&i2c1 {	280	&i2c1 {
@@ -314,8 +354,12 @@ · 73 unmodified lines
314	};	354	};
315		355
316	&mmc5 {	356	&mmc5 {
317	ti,non-removable;	357	pinctrl-names = "default";
		358	pinctrl-0 = <&wl12xx_pins>;
		359	vmmc-supply = <&wl12xx_vmmc>;
		360	non-removable;
318	bus-width = <4>;	361	bus-width = <4>;
		362	cap-power-off-card;
319	};	363	};
320		364
321	&emif1 {	365	&emif1 {

arch/arm/boot/dts/omap4-sdp.dts+38−1

@@ -140,6 +140,19 @@ · 139 unmodified lines
140	"DMic", "Digital Mic",	140	"DMic", "Digital Mic",
141	"Digital Mic", "Digital Mic1 Bias";	141	"Digital Mic", "Digital Mic1 Bias";
142	};	142	};
		143
		144	/* regulator for wl12xx on sdio5 */
		145	wl12xx_vmmc: wl12xx_vmmc {
		146	pinctrl-names = "default";
		147	pinctrl-0 = <&wl12xx_gpio>;
		148	compatible = "regulator-fixed";
		149	regulator-name = "vwl1271";
		150	regulator-min-microvolt = <1800000>;
		151	regulator-max-microvolt = <1800000>;
		152	gpio = <&gpio2 22 0>;
		153	startup-delay-us = <70000>;
		154	enable-active-high;
		155	};
143	};	156	};
144		157
145	&omap4_pmx_wkup {	158	&omap4_pmx_wkup {
@@ -295,6 +308,26 @@ · 149 unmodified lines
295	0xf0 (PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c4_sda */	308	0xf0 (PIN_INPUT_PULLUP \| MUX_MODE0) /* i2c4_sda */
296	>;	309	>;
297	};	310	};
		311
		312	/* wl12xx GPIO output for WLAN_EN */
		313	wl12xx_gpio: pinmux_wl12xx_gpio {
		314	pinctrl-single,pins = <
		315	0x3c (PIN_OUTPUT \| MUX_MODE3) /* gpmc_nwp.gpio_54 */
		316	>;
		317	};
		318
		319	/* wl12xx GPIO inputs and SDIO pins */
		320	wl12xx_pins: pinmux_wl12xx_pins {
		321	pinctrl-single,pins = <
		322	0x3a (PIN_INPUT \| MUX_MODE3) /* gpmc_ncs3.gpio_53 */
		323	0x108 (PIN_OUTPUT \| MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */
		324	0x10a (PIN_INPUT_PULLUP \| MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */
		325	0x10c (PIN_INPUT_PULLUP \| MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */
		326	0x10e (PIN_INPUT_PULLUP \| MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */
		327	0x110 (PIN_INPUT_PULLUP \| MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */
		328	0x112 (PIN_INPUT_PULLUP \| MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */
		329	>;
		330	};
298	};	331	};
299		332
300	&i2c1 {	333	&i2c1 {
@@ -420,8 +453,12 @@ · 119 unmodified lines
420	};	453	};
421		454
422	&mmc5 {	455	&mmc5 {
		456	pinctrl-names = "default";
		457	pinctrl-0 = <&wl12xx_pins>;
		458	vmmc-supply = <&wl12xx_vmmc>;
		459	non-removable;
423	bus-width = <4>;	460	bus-width = <4>;
424	ti,non-removable;	461	cap-power-off-card;
425	};	462	};
426		463
427	&emif1 {	464	&emif1 {

arch/arm/boot/dts/omap5.dtsi+4−3

 		omap_dwc3@4a020000 {
 			compatible = "ti,dwc3";
 			ti,hwmods = "usb_otg_ss";
-			reg = <0x4a020000 0x1000>;
+			reg = <0x4a020000 0x10000>;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
 			dwc3@4a030000 {
 				compatible = "snps,dwc3";
-				reg = <0x4a030000 0x1000>;
+				reg = <0x4a030000 0x10000>;
 				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 				usb-phy = <&usb2_phy>, <&usb3_phy>;
 				tx-fifo-resize;
 			};
 		};
-		ocp2scp {
+		ocp2scp@4a080000 {
 			compatible = "ti,omap-ocp2scp";
 			#address-cells = <1>;
 			#size-cells = <1>;
+			reg = <0x4a080000 0x20>;
 			ranges;
 			ti,hwmods = "ocp2scp1";
 			usb2_phy: usb2phy@4a084000 {

arch/arm/boot/dts/prima2.dtsi+23−4

 			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0xb0000000 0xb0000000 0x180000>;
+			ranges = <0xb0000000 0xb0000000 0x180000>,
+			       <0x56000000 0x56000000 0x1b00000>;
 			timer@b0020000 {
 				compatible = "sirf,prima2-tick";
 			uart0: uart@b0050000 {
 				cell-index = <0>;
 				compatible = "sirf,prima2-uart";
-				reg = <0xb0050000 0x10000>;
+				reg = <0xb0050000 0x1000>;
 				interrupts = <17>;
+				fifosize = <128>;
 				clocks = <&clks 13>;
+				sirf,uart-dma-rx-channel = <21>;
+				sirf,uart-dma-tx-channel = <2>;
 			};
 			uart1: uart@b0060000 {
 				cell-index = <1>;
 				compatible = "sirf,prima2-uart";
-				reg = <0xb0060000 0x10000>;
+				reg = <0xb0060000 0x1000>;
 				interrupts = <18>;
+				fifosize = <32>;
 				clocks = <&clks 14>;
 			};
 			uart2: uart@b0070000 {
 				cell-index = <2>;
 				compatible = "sirf,prima2-uart";
-				reg = <0xb0070000 0x10000>;
+				reg = <0xb0070000 0x1000>;
 				interrupts = <19>;
+				fifosize = <128>;
 				clocks = <&clks 15>;
+				sirf,uart-dma-rx-channel = <6>;
+				sirf,uart-dma-tx-channel = <7>;
 			};
 			usp0: usp@b0080000 {
 				compatible = "sirf,prima2-usp";
 				reg = <0xb0080000 0x10000>;
 				interrupts = <20>;
+				fifosize = <128>;
 				clocks = <&clks 28>;
+				sirf,usp-dma-rx-channel = <17>;
+				sirf,usp-dma-tx-channel = <18>;
 			};
 			usp1: usp@b0090000 {
 				compatible = "sirf,prima2-usp";
 				reg = <0xb0090000 0x10000>;
 				interrupts = <21>;
+				fifosize = <128>;
 				clocks = <&clks 29>;
+				sirf,usp-dma-rx-channel = <14>;
+				sirf,usp-dma-tx-channel = <15>;
 			};
 			usp2: usp@b00a0000 {
 				compatible = "sirf,prima2-usp";
 				reg = <0xb00a0000 0x10000>;
 				interrupts = <22>;
+				fifosize = <128>;
 				clocks = <&clks 30>;
+				sirf,usp-dma-rx-channel = <10>;
+				sirf,usp-dma-tx-channel = <11>;
 			};
 			dmac0: dma-controller@b00b0000 {
 				compatible = "sirf,prima2-vip";
 				reg = <0xb00C0000 0x10000>;
 				clocks = <&clks 31>;
+				interrupts = <14>;
+				sirf,vip-dma-rx-channel = <16>;
 			};
 			spi0: spi@b00d0000 {

arch/arm/boot/dts/r8a73a4.dtsi+3−3

@@ -193,7 +193,7 @@ · 192 unmodified lines
193	};	193	};
194		194
195	sdhi0: sdhi@ee100000 {	195	sdhi0: sdhi@ee100000 {
196	compatible = "renesas,r8a73a4-sdhi";	196	compatible = "renesas,sdhi-r8a73a4";
197	reg = <0 0xee100000 0 0x100>;	197	reg = <0 0xee100000 0 0x100>;
198	interrupt-parent = <&gic>;	198	interrupt-parent = <&gic>;
199	interrupts = <0 165 4>;	199	interrupts = <0 165 4>;
@@ -202,7 +202,7 @@ · 2 unmodified lines
202	};	202	};
203		203
204	sdhi1: sdhi@ee120000 {	204	sdhi1: sdhi@ee120000 {
205	compatible = "renesas,r8a73a4-sdhi";	205	compatible = "renesas,sdhi-r8a73a4";
206	reg = <0 0xee120000 0 0x100>;	206	reg = <0 0xee120000 0 0x100>;
207	interrupt-parent = <&gic>;	207	interrupt-parent = <&gic>;
208	interrupts = <0 166 4>;	208	interrupts = <0 166 4>;
@@ -211,7 +211,7 @@ · 2 unmodified lines
211	};	211	};
212		212
213	sdhi2: sdhi@ee140000 {	213	sdhi2: sdhi@ee140000 {
214	compatible = "renesas,r8a73a4-sdhi";	214	compatible = "renesas,sdhi-r8a73a4";
215	reg = <0 0xee140000 0 0x100>;	215	reg = <0 0xee140000 0 0x100>;
216	interrupt-parent = <&gic>;	216	interrupt-parent = <&gic>;
217	interrupts = <0 167 4>;	217	interrupts = <0 167 4>;

arch/arm/boot/dts/r8a7778.dtsi+0−1

@@ -96,6 +96,5 @@ · 95 unmodified lines
96	pfc: pfc@fffc0000 {	96	pfc: pfc@fffc0000 {
97	compatible = "renesas,pfc-r8a7778";	97	compatible = "renesas,pfc-r8a7778";
98	reg = <0xfffc000 0x118>;	98	reg = <0xfffc000 0x118>;
99	#gpio-range-cells = <3>;
100	};	99	};
101	};	100	};

arch/arm/boot/dts/r8a7779.dtsi+0−1

@@ -188,7 +188,6 @@ · 187 unmodified lines
188	pfc: pfc@fffc0000 {	188	pfc: pfc@fffc0000 {
189	compatible = "renesas,pfc-r8a7779";	189	compatible = "renesas,pfc-r8a7779";
190	reg = <0xfffc0000 0x23c>;	190	reg = <0xfffc0000 0x23c>;
191	#gpio-range-cells = <3>;
192	};	191	};
193		192
194	thermal@ffc48000 {	193	thermal@ffc48000 {

arch/arm/boot/dts/r8a7790.dtsi+4−5

 	pfc: pfc@e6060000 {
 		compatible = "renesas,pfc-r8a7790";
 		reg = <0 0xe6060000 0 0x250>;
-		#gpio-range-cells = <3>;
 	};
 	sdhi0: sdhi@ee100000 {
-		compatible = "renesas,r8a7790-sdhi";
+		compatible = "renesas,sdhi-r8a7790";
 		reg = <0 0xee100000 0 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 165 4>;
 	};
 	sdhi1: sdhi@ee120000 {
-		compatible = "renesas,r8a7790-sdhi";
+		compatible = "renesas,sdhi-r8a7790";
 		reg = <0 0xee120000 0 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 166 4>;
 	};
 	sdhi2: sdhi@ee140000 {
-		compatible = "renesas,r8a7790-sdhi";
+		compatible = "renesas,sdhi-r8a7790";
 		reg = <0 0xee140000 0 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 167 4>;
 	};
 	sdhi3: sdhi@ee160000 {
-		compatible = "renesas,r8a7790-sdhi";
+		compatible = "renesas,sdhi-r8a7790";
 		reg = <0 0xee160000 0 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 168 4>;

arch/arm/boot/dts/sh73a0.dtsi+3−3

@@ -196,7 +196,7 @@ · 195 unmodified lines
196	};	196	};
197		197
198	sdhi0: sdhi@ee100000 {	198	sdhi0: sdhi@ee100000 {
199	compatible = "renesas,r8a7740-sdhi";	199	compatible = "renesas,sdhi-r8a7740";
200	reg = <0xee100000 0x100>;	200	reg = <0xee100000 0x100>;
201	interrupt-parent = <&gic>;	201	interrupt-parent = <&gic>;
202	interrupts = <0 83 4	202	interrupts = <0 83 4
@@ -208,7 +208,7 @@ · 5 unmodified lines
208		208
209	/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */	209	/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
210	sdhi1: sdhi@ee120000 {	210	sdhi1: sdhi@ee120000 {
211	compatible = "renesas,r8a7740-sdhi";	211	compatible = "renesas,sdhi-r8a7740";
212	reg = <0xee120000 0x100>;	212	reg = <0xee120000 0x100>;
213	interrupt-parent = <&gic>;	213	interrupt-parent = <&gic>;
214	interrupts = <0 88 4	214	interrupts = <0 88 4
@@ -219,7 +219,7 @@ · 4 unmodified lines
219	};	219	};
220		220
221	sdhi2: sdhi@ee140000 {	221	sdhi2: sdhi@ee140000 {
222	compatible = "renesas,r8a7740-sdhi";	222	compatible = "renesas,sdhi-r8a7740";
223	reg = <0xee140000 0x100>;	223	reg = <0xee140000 0x100>;
224	interrupt-parent = <&gic>;	224	interrupt-parent = <&gic>;
225	interrupts = <0 104 4	225	interrupts = <0 104 4

arch/arm/common/edma.c+31−7

 	.ccnt = 1,
 };
+static const struct of_device_id edma_of_ids[] = {
+	{ .compatible = "ti,edma3", },
+	{}
+};
 /*****************************************************************************/
 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
 static int prepare_unused_channel_list(struct device *dev, void *data)
 {
 	struct platform_device *pdev = to_platform_device(dev);
-	int i, ctlr;
+	int i, count, ctlr;
+	struct of_phandle_args  dma_spec;
+	if (dev->of_node) {
+		count = of_property_count_strings(dev->of_node, "dma-names");
+		if (count < 0)
+			return 0;
+		for (i = 0; i < count; i++) {
+			if (of_parse_phandle_with_args(dev->of_node, "dmas",
+						       "#dma-cells", i,
+						       &dma_spec))
+				continue;
+			if (!of_match_node(edma_of_ids, dma_spec.np)) {
+				of_node_put(dma_spec.np);
+				continue;
+			}
+			clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
+				  edma_cc[0]->edma_unused);
+			of_node_put(dma_spec.np);
+		}
+		return 0;
+	}
+	/* For non-OF case */
 	for (i = 0; i < pdev->num_resources; i++) {
 		if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
 				(int)pdev->resource[i].start >= 0) {
 			ctlr = EDMA_CTLR(pdev->resource[i].start);
 			clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
-					edma_cc[ctlr]->edma_unused);
+				  edma_cc[ctlr]->edma_unused);
 		}
 	}
 	return 0;
 }
-static const struct of_device_id edma_of_ids[] = {
-	{ .compatible = "ti,edma3", },
-	{}
-};
 static struct platform_driver edma_driver = {
 	.driver = {
 		.name	= "edma",

arch/arm/configs/multi_v7_defconfig+3−0

 CONFIG_TEGRA_PCI=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_ARCH_U8500=y
+CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_UX500_DT=y
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_SMP=y
 CONFIG_HIGHPTE=y
 CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_NET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_MMC_SDHCI_SPEAR=y
 CONFIG_MMC_OMAP=y

arch/arm/crypto/aes-armv4.S+3−3

@@ -148,7 +148,7 @@ AES_Te: · 147 unmodified lines
148	@ const AES_KEY *key) {	148	@ const AES_KEY *key) {
149	.align 5	149	.align 5
150	ENTRY(AES_encrypt)	150	ENTRY(AES_encrypt)
151	sub r3,pc,#8 @ AES_encrypt	151	adr r3,AES_encrypt
152	stmdb sp!,{r1,r4-r12,lr}	152	stmdb sp!,{r1,r4-r12,lr}
153	mov r12,r0 @ inp	153	mov r12,r0 @ inp
154	mov r11,r2	154	mov r11,r2
@@ -381,7 +381,7 @@ _armv4_AES_encrypt: · 226 unmodified lines
381	.align 5	381	.align 5
382	ENTRY(private_AES_set_encrypt_key)	382	ENTRY(private_AES_set_encrypt_key)
383	_armv4_AES_set_encrypt_key:	383	_armv4_AES_set_encrypt_key:
384	sub r3,pc,#8 @ AES_set_encrypt_key	384	adr r3,_armv4_AES_set_encrypt_key
385	teq r0,#0	385	teq r0,#0
386	moveq r0,#-1	386	moveq r0,#-1
387	beq .Labrt	387	beq .Labrt
@@ -843,7 +843,7 @@ AES_Td: · 455 unmodified lines
843	@ const AES_KEY *key) {	843	@ const AES_KEY *key) {
844	.align 5	844	.align 5
845	ENTRY(AES_decrypt)	845	ENTRY(AES_decrypt)
846	sub r3,pc,#8 @ AES_decrypt	846	adr r3,AES_decrypt
847	stmdb sp!,{r1,r4-r12,lr}	847	stmdb sp!,{r1,r4-r12,lr}
848	mov r12,r0 @ inp	848	mov r12,r0 @ inp
849	mov r11,r2	849	mov r11,r2

arch/arm/include/asm/uaccess.h+7−0

@@ -19,6 +19,13 @@ · 18 unmodified lines
19	#include <asm/unified.h>	19	#include <asm/unified.h>
20	#include <asm/compiler.h>	20	#include <asm/compiler.h>
21		21
		22	#if __LINUX_ARM_ARCH__ < 6
		23	#include <asm-generic/uaccess-unaligned.h>
		24	#else
		25	#define __get_user_unaligned __get_user
		26	#define __put_user_unaligned __put_user
		27	#endif
		28
22	#define VERIFY_READ 0	29	#define VERIFY_READ 0
23	#define VERIFY_WRITE 1	30	#define VERIFY_WRITE 1
24		31

arch/arm/kernel/entry-common.S+2−2

@@ -442,10 +442,10 @@ local_restart: · 441 unmodified lines
442	ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine	442	ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine
443		443
444	add r1, sp, #S_OFF	444	add r1, sp, #S_OFF
445	cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE)	445	2: cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE)
446	eor r0, scno, #__NR_SYSCALL_BASE @ put OS number back	446	eor r0, scno, #__NR_SYSCALL_BASE @ put OS number back
447	bcs arm_syscall	447	bcs arm_syscall
448	2: mov why, #0 @ no longer a real syscall	448	mov why, #0 @ no longer a real syscall
449	b sys_ni_syscall @ not private func	449	b sys_ni_syscall @ not private func
450		450
451	#if defined(CONFIG_OABI_COMPAT) \|\| !defined(CONFIG_AEABI)	451	#if defined(CONFIG_OABI_COMPAT) \|\| !defined(CONFIG_AEABI)

arch/arm/kernel/entry-header.S+4−4

@@ -329,10 +329,10 @@ · 328 unmodified lines
329	#ifdef CONFIG_CONTEXT_TRACKING	329	#ifdef CONFIG_CONTEXT_TRACKING
330	.if \save	330	.if \save
331	stmdb sp!, {r0-r3, ip, lr}	331	stmdb sp!, {r0-r3, ip, lr}
332	bl user_exit	332	bl context_tracking_user_exit
333	ldmia sp!, {r0-r3, ip, lr}	333	ldmia sp!, {r0-r3, ip, lr}
334	.else	334	.else
335	bl user_exit	335	bl context_tracking_user_exit
336	.endif	336	.endif
337	#endif	337	#endif
338	.endm	338	.endm
@@ -341,10 +341,10 @@ · 2 unmodified lines
341	#ifdef CONFIG_CONTEXT_TRACKING	341	#ifdef CONFIG_CONTEXT_TRACKING
342	.if \save	342	.if \save
343	stmdb sp!, {r0-r3, ip, lr}	343	stmdb sp!, {r0-r3, ip, lr}
344	bl user_enter	344	bl context_tracking_user_enter
345	ldmia sp!, {r0-r3, ip, lr}	345	ldmia sp!, {r0-r3, ip, lr}
346	.else	346	.else
347	bl user_enter	347	bl context_tracking_user_enter
348	.endif	348	.endif
349	#endif	349	#endif
350	.endm	350	.endm

arch/arm/kvm/reset.c+3−3

@@ -58,14 +58,14 @@ static const struct kvm_irq_level a15_vtimer_irq = { · 57 unmodified lines
58	*/	58	*/
59	int kvm_reset_vcpu(struct kvm_vcpu *vcpu)	59	int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
60	{	60	{
61	struct kvm_regs *cpu_reset;	61	struct kvm_regs *reset_regs;
62	const struct kvm_irq_level *cpu_vtimer_irq;	62	const struct kvm_irq_level *cpu_vtimer_irq;
63		63
64	switch (vcpu->arch.target) {	64	switch (vcpu->arch.target) {
65	case KVM_ARM_TARGET_CORTEX_A15:	65	case KVM_ARM_TARGET_CORTEX_A15:
66	if (vcpu->vcpu_id > a15_max_cpu_idx)	66	if (vcpu->vcpu_id > a15_max_cpu_idx)
67	return -EINVAL;	67	return -EINVAL;
68	cpu_reset = &a15_regs_reset;	68	reset_regs = &a15_regs_reset;
69	vcpu->arch.midr = read_cpuid_id();	69	vcpu->arch.midr = read_cpuid_id();
70	cpu_vtimer_irq = &a15_vtimer_irq;	70	cpu_vtimer_irq = &a15_vtimer_irq;
71	break;	71	break;
@@ -74,7 +74,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) · 2 unmodified lines
74	}	74	}
75		75
76	/* Reset core registers */	76	/* Reset core registers */
77	memcpy(&vcpu->arch.regs, cpu_reset, sizeof(vcpu->arch.regs));	77	memcpy(&vcpu->arch.regs, reset_regs, sizeof(vcpu->arch.regs));
78		78
79	/* Reset CP15 registers */	79	/* Reset CP15 registers */
80	kvm_reset_coprocs(vcpu);	80	kvm_reset_coprocs(vcpu);

arch/arm/mach-at91/at91rm9200_time.c+1−1

@@ -93,7 +93,7 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) · 92 unmodified lines
93		93
94	static struct irqaction at91rm9200_timer_irq = {	94	static struct irqaction at91rm9200_timer_irq = {
95	.name = "at91_tick",	95	.name = "at91_tick",
96	.flags = IRQF_SHARED \| IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,	96	.flags = IRQF_SHARED \| IRQF_TIMER \| IRQF_IRQPOLL,
97	.handler = at91rm9200_timer_interrupt,	97	.handler = at91rm9200_timer_interrupt,
98	.irq = NR_IRQS_LEGACY + AT91_ID_SYS,	98	.irq = NR_IRQS_LEGACY + AT91_ID_SYS,
99	};	99	};

arch/arm/mach-at91/at91sam926x_time.c+1−1

@@ -171,7 +171,7 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) · 170 unmodified lines
171		171
172	static struct irqaction at91sam926x_pit_irq = {	172	static struct irqaction at91sam926x_pit_irq = {
173	.name = "at91_tick",	173	.name = "at91_tick",
174	.flags = IRQF_SHARED \| IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,	174	.flags = IRQF_SHARED \| IRQF_TIMER \| IRQF_IRQPOLL,
175	.handler = at91sam926x_pit_interrupt,	175	.handler = at91sam926x_pit_interrupt,
176	.irq = NR_IRQS_LEGACY + AT91_ID_SYS,	176	.irq = NR_IRQS_LEGACY + AT91_ID_SYS,
177	};	177	};

arch/arm/mach-at91/at91sam9g45_reset.S+8−0

 #include "at91_rstc.h"
 			.arm
+/*
+ * at91_ramc_base is an array void*
+ * init at NULL if only one DDR controler is present in or DT
+ */
 			.globl	at91sam9g45_restart
 at91sam9g45_restart:
 			ldr	r5, =at91_ramc_base		@ preload constants
 			ldr	r0, [r5]
+			ldr	r5, [r5, #4]			@ ddr1
+			cmp	r5, #0
 			ldr	r4, =at91_rstc_base
 			ldr	r1, [r4]
 			.balign	32				@ align to cache line
+			strne	r2, [r5, #AT91_DDRSDRC_RTR]	@ disable DDR1 access
+			strne	r3, [r5, #AT91_DDRSDRC_LPR]	@ power down DDR1
 			str	r2, [r0, #AT91_DDRSDRC_RTR]	@ disable DDR0 access
 			str	r3, [r0, #AT91_DDRSDRC_LPR]	@ power down DDR0
 			str	r4, [r1, #AT91_RSTC_CR]		@ reset processor

arch/arm/mach-at91/at91x40_time.c+1−1

@@ -57,7 +57,7 @@ static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id) · 56 unmodified lines
57		57
58	static struct irqaction at91x40_timer_irq = {	58	static struct irqaction at91x40_timer_irq = {
59	.name = "at91_tick",	59	.name = "at91_tick",
60	.flags = IRQF_DISABLED \| IRQF_TIMER,	60	.flags = IRQF_TIMER,
61	.handler = at91x40_timer_interrupt	61	.handler = at91x40_timer_interrupt
62	};	62	};
63		63

arch/arm/mach-davinci/board-dm365-evm.c+1−1

@@ -176,7 +176,7 @@ static struct at24_platform_data eeprom_info = { · 175 unmodified lines
176	.context = (void *)0x7f00,	176	.context = (void *)0x7f00,
177	};	177	};
178		178
179	static struct snd_platform_data dm365_evm_snd_data = {	179	static struct snd_platform_data dm365_evm_snd_data __maybe_unused = {
180	.asp_chan_q = EVENTQ_3,	180	.asp_chan_q = EVENTQ_3,
181	};	181	};
182		182

arch/arm/mach-davinci/include/mach/serial.h+2−2

 #include <mach/hardware.h>
-#include <linux/platform_device.h>
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
 #define UART_DM646X_SCR_TX_WATERMARK	0x08
 #ifndef __ASSEMBLY__
+#include <linux/platform_device.h>
 extern int davinci_serial_init(struct platform_device *);
 #endif

arch/arm/mach-imx/clk-fixup-mux.c+1−0

@@ -90,6 +90,7 @@ struct clk imx_clk_fixup_mux(const char name, void __iomem *reg, · 89 unmodified lines
90	init.ops = &clk_fixup_mux_ops;	90	init.ops = &clk_fixup_mux_ops;
91	init.parent_names = parents;	91	init.parent_names = parents;
92	init.num_parents = num_parents;	92	init.num_parents = num_parents;
		93	init.flags = 0;
93		94
94	fixup_mux->mux.reg = reg;	95	fixup_mux->mux.reg = reg;
95	fixup_mux->mux.shift = shift;	96	fixup_mux->mux.shift = shift;

arch/arm/mach-imx/clk-imx27.c+1−1

@@ -285,7 +285,7 @@ int __init mx27_clocks_init(unsigned long fref) · 284 unmodified lines
285	clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);	285	clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
286	clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");	286	clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
287	clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);	287	clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
288	clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0");	288	clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
289	clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);	289	clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
290		290
291	mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);	291	mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);

arch/arm/mach-imx/clk-imx51-imx53.c+2−2

arch/arm/mach-imx/mach-imx6q.c+7−2

 	of_node_put(np);
 }
-static void __init imx6q_opp_init(struct device *cpu_dev)
+static void __init imx6q_opp_init(void)
 {
 	struct device_node *np;
+	struct device *cpu_dev = get_cpu_device(0);
+	if (!cpu_dev) {
+		pr_warn("failed to get cpu0 device\n");
+		return;
+	}
 	np = of_node_get(cpu_dev->of_node);
 	if (!np) {
 		pr_warn("failed to find cpu0 node\n");
 		imx6q_cpuidle_init();
 	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
-		imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
+		imx6q_opp_init();
 		platform_device_register(&imx6q_cpufreq_pdev);
 	}
 }

arch/arm/mach-imx/system.c+11−0

@@ -117,6 +117,17 @@ void __init imx_init_l2cache(void) · 116 unmodified lines
117	/* Configure the L2 PREFETCH and POWER registers */	117	/* Configure the L2 PREFETCH and POWER registers */
118	val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);	118	val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
119	val \|= 0x70800000;	119	val \|= 0x70800000;
		120	/*
		121	* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
		122	* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
		123	* But according to ARM PL310 errata: 752271
		124	* ID: 752271: Double linefill feature can cause data corruption
		125	* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
		126	* Workaround: The only workaround to this erratum is to disable the
		127	* double linefill feature. This is the default behavior.
		128	*/
		129	if (cpu_is_imx6q())
		130	val &= ~(1 << 30 \| 1 << 23);
120	writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);	131	writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
121	val = L2X0_DYNAMIC_CLK_GATING_EN \| L2X0_STNDBY_MODE_EN;	132	val = L2X0_DYNAMIC_CLK_GATING_EN \| L2X0_STNDBY_MODE_EN;
122	writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);	133	writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);

arch/arm/mach-integrator/pci_v3.h+7−0

@@ -1,2 +1,9 @@
1	/* Simple oneliner include to the PCIv3 early init */	1	/* Simple oneliner include to the PCIv3 early init */
		2	#ifdef CONFIG_PCI
2	extern int pci_v3_early_init(void);	3	extern int pci_v3_early_init(void);
		4	#else
		5	static inline int pci_v3_early_init(void)
		6	{
		7	return 0;
		8	}
		9	#endif

arch/arm/mach-mvebu/coherency.c+7−1

 		coherency_base = of_iomap(np, 0);
 		coherency_cpu_base = of_iomap(np, 1);
 		set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+		of_node_put(np);
 	}
 	return 0;
 static int __init coherency_late_init(void)
 {
-	if (of_find_matching_node(NULL, of_coherency_table))
+	struct device_node *np;
+	np = of_find_matching_node(NULL, of_coherency_table);
+	if (np) {
 		bus_register_notifier(&platform_bus_type,
 				      &mvebu_hwcc_platform_nb);
+		of_node_put(np);
+	}
 	return 0;
 }

arch/arm/mach-mvebu/pmsu.c+1−0

@@ -67,6 +67,7 @@ int __init armada_370_xp_pmsu_init(void) · 66 unmodified lines
67	pr_info("Initializing Power Management Service Unit\n");	67	pr_info("Initializing Power Management Service Unit\n");
68	pmsu_mp_base = of_iomap(np, 0);	68	pmsu_mp_base = of_iomap(np, 0);
69	pmsu_reset_base = of_iomap(np, 1);	69	pmsu_reset_base = of_iomap(np, 1);
		70	of_node_put(np);
70	}	71	}
71		72
72	return 0;	73	return 0;

arch/arm/mach-mvebu/system-controller.c+1−0

@@ -98,6 +98,7 @@ static int __init mvebu_system_controller_init(void) · 97 unmodified lines
98	BUG_ON(!match);	98	BUG_ON(!match);
99	system_controller_base = of_iomap(np, 0);	99	system_controller_base = of_iomap(np, 0);
100	mvebu_sc = (struct mvebu_system_controller *)match->data;	100	mvebu_sc = (struct mvebu_system_controller *)match->data;
		101	of_node_put(np);
101	}	102	}
102		103
103	return 0;	104	return 0;

arch/arm/mach-omap2/cclock44xx_data.c+1−1

@@ -1632,7 +1632,7 @@ static struct omap_clk omap44xx_clks[] = { · 1631 unmodified lines
1632	CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),	1632	CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
1633	CLK(NULL, "auxclk5_ck", &auxclk5_ck),	1633	CLK(NULL, "auxclk5_ck", &auxclk5_ck),
1634	CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),	1634	CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
1635	CLK("omap-gpmc", "fck", &dummy_ck),	1635	CLK("50000000.gpmc", "fck", &dummy_ck),
1636	CLK("omap_i2c.1", "ick", &dummy_ck),	1636	CLK("omap_i2c.1", "ick", &dummy_ck),
1637	CLK("omap_i2c.2", "ick", &dummy_ck),	1637	CLK("omap_i2c.2", "ick", &dummy_ck),
1638	CLK("omap_i2c.3", "ick", &dummy_ck),	1638	CLK("omap_i2c.3", "ick", &dummy_ck),

arch/arm/mach-omap2/cpuidle44xx.c+1−1

@@ -143,7 +143,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, · 142 unmodified lines
143	* Call idle CPU cluster PM exit notifier chain	143	* Call idle CPU cluster PM exit notifier chain
144	* to restore GIC and wakeupgen context.	144	* to restore GIC and wakeupgen context.
145	*/	145	*/
146	if ((cx->mpu_state == PWRDM_POWER_RET) &&	146	if (dev->cpu == 0 && (cx->mpu_state == PWRDM_POWER_RET) &&
147	(cx->mpu_logic_state == PWRDM_POWER_OFF))	147	(cx->mpu_logic_state == PWRDM_POWER_OFF))
148	cpu_cluster_pm_exit();	148	cpu_cluster_pm_exit();
149		149

arch/arm/mach-omap2/gpmc.c+2−2

@@ -1491,8 +1491,8 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, · 1490 unmodified lines
1491	*/	1491	*/
1492	ret = gpmc_cs_remap(cs, res.start);	1492	ret = gpmc_cs_remap(cs, res.start);
1493	if (ret < 0) {	1493	if (ret < 0) {
1494	dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",	1494	dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1495	cs, res.start);	1495	cs, &res.start);
1496	goto err;	1496	goto err;
1497	}	1497	}
1498		1498

arch/arm/mach-omap2/mux34xx.c+1−1

@@ -620,7 +620,7 @@ static struct omap_mux __initdata omap3_muxmodes[] = { · 619 unmodified lines
620	"uart1_rts", "ssi1_flag_tx", NULL, NULL,	620	"uart1_rts", "ssi1_flag_tx", NULL, NULL,
621	"gpio_149", NULL, NULL, "safe_mode"),	621	"gpio_149", NULL, NULL, "safe_mode"),
622	_OMAP3_MUXENTRY(UART1_RX, 151,	622	_OMAP3_MUXENTRY(UART1_RX, 151,
623	"uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",	623	"uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
624	"gpio_151", NULL, NULL, "safe_mode"),	624	"gpio_151", NULL, NULL, "safe_mode"),
625	_OMAP3_MUXENTRY(UART1_TX, 148,	625	_OMAP3_MUXENTRY(UART1_TX, 148,
626	"uart1_tx", "ssi1_dat_tx", NULL, NULL,	626	"uart1_tx", "ssi1_dat_tx", NULL, NULL,

arch/arm/mach-omap2/omap-smp.c+1−1

@@ -1,5 +1,5 @@
1	/*	1	/*
2	* OMAP4 SMP source file. It contains platform specific fucntions	2	* OMAP4 SMP source file. It contains platform specific functions
3	* needed for the linux smp kernel.	3	* needed for the linux smp kernel.
4	*	4	*
5	* Copyright (C) 2009 Texas Instruments, Inc.	5	* Copyright (C) 2009 Texas Instruments, Inc.

arch/arm/mach-omap2/omap_device.c+1−1

@@ -158,7 +158,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev) · 157 unmodified lines
158	}	158	}
159		159
160	od = omap_device_alloc(pdev, hwmods, oh_cnt);	160	od = omap_device_alloc(pdev, hwmods, oh_cnt);
161	if (!od) {	161	if (IS_ERR(od)) {
162	dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",	162	dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
163	oh_name);	163	oh_name);
164	ret = PTR_ERR(od);	164	ret = PTR_ERR(od);

arch/arm/mach-sa1100/collie.c+1−1

@@ -289,7 +289,7 @@ static void collie_flash_exit(void) · 288 unmodified lines
289	}	289	}
290		290
291	static struct flash_platform_data collie_flash_data = {	291	static struct flash_platform_data collie_flash_data = {
292	.map_name = "cfi_probe",	292	.map_name = "jedec_probe",
293	.init = collie_flash_init,	293	.init = collie_flash_init,
294	.set_vpp = collie_set_vpp,	294	.set_vpp = collie_set_vpp,
295	.exit = collie_flash_exit,	295	.exit = collie_flash_exit,

arch/arm/mach-shmobile/board-armadillo800eva.c+2−2

@@ -1108,9 +1108,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = { · 1107 unmodified lines
1108	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",	1108	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
1109	"fsib_mclk_in", "fsib"),	1109	"fsib_mclk_in", "fsib"),
1110	/* GETHER */	1110	/* GETHER */
1111	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",	1111	PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740",
1112	"gether_mii", "gether"),	1112	"gether_mii", "gether"),
1113	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",	1113	PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740",
1114	"gether_int", "gether"),	1114	"gether_int", "gether"),
1115	/* HDMI */	1115	/* HDMI */
1116	PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",	1116	PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",

arch/arm/mach-shmobile/board-lager.c+26−1

@@ -29,6 +29,7 @@ · 28 unmodified lines
29	#include <linux/pinctrl/machine.h>	29	#include <linux/pinctrl/machine.h>
30	#include <linux/platform_data/gpio-rcar.h>	30	#include <linux/platform_data/gpio-rcar.h>
31	#include <linux/platform_device.h>	31	#include <linux/platform_device.h>
		32	#include <linux/phy.h>
32	#include <linux/regulator/fixed.h>	33	#include <linux/regulator/fixed.h>
33	#include <linux/regulator/machine.h>	34	#include <linux/regulator/machine.h>
34	#include <linux/sh_eth.h>	35	#include <linux/sh_eth.h>
@@ -155,6 +156,30 @@ static void __init lager_add_standard_devices(void) · 120 unmodified lines
155	&ether_pdata, sizeof(ether_pdata));	156	&ether_pdata, sizeof(ether_pdata));
156	}	157	}
157		158
		159	/*
		160	* Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
		161	* to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
		162	* 14-15. We have to set them back to 01 from the default 00 value each time
		163	* the PHY is reset. It's also important because the PHY's LED0 signal is
		164	* connected to SoC's ETH_LINK signal and in the PHY's default mode it will
		165	* bounce on and off after each packet, which we apparently want to avoid.
		166	*/
		167	static int lager_ksz8041_fixup(struct phy_device *phydev)
		168	{
		169	u16 phyctrl1 = phy_read(phydev, 0x1e);
		170
		171	phyctrl1 &= ~0xc000;
		172	phyctrl1 \|= 0x4000;
		173	return phy_write(phydev, 0x1e, phyctrl1);
		174	}
		175
		176	static void __init lager_init(void)
		177	{
		178	lager_add_standard_devices();
		179
		180	phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
		181	}
		182
158	static const char *lager_boards_compat_dt[] __initdata = {	183	static const char *lager_boards_compat_dt[] __initdata = {
159	"renesas,lager",	184	"renesas,lager",
160	NULL,	185	NULL,
@@ -163,6 +188,6 @@ static const char *lager_boards_compat_dt[] __initdata = { · 2 unmodified lines
163	DT_MACHINE_START(LAGER_DT, "lager")	188	DT_MACHINE_START(LAGER_DT, "lager")
164	.init_early = r8a7790_init_delay,	189	.init_early = r8a7790_init_delay,
165	.init_time = r8a7790_timer_init,	190	.init_time = r8a7790_timer_init,
166	.init_machine = lager_add_standard_devices,	191	.init_machine = lager_init,
167	.dt_compat = lager_boards_compat_dt,	192	.dt_compat = lager_boards_compat_dt,
168	MACHINE_END	193	MACHINE_END

arch/arm/mach-shmobile/clock-r8a73a4.c+1−1

@@ -555,7 +555,7 @@ static struct clk_lookup lookups[] = { · 554 unmodified lines
555	CLKDEV_CON_ID("pll2h", &pll2h_clk),	555	CLKDEV_CON_ID("pll2h", &pll2h_clk),
556		556
557	/* CPU clock */	557	/* CPU clock */
558	CLKDEV_DEV_ID("cpufreq-cpu0", &z_clk),	558	CLKDEV_DEV_ID("cpu0", &z_clk),
559		559
560	/* DIV6 */	560	/* DIV6 */
561	CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),	561	CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),

arch/arm/mach-shmobile/clock-sh73a0.c+1−1

@@ -616,7 +616,7 @@ static struct clk_lookup lookups[] = { · 615 unmodified lines
616	CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */	616	CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
617		617
618	/* DIV4 clocks */	618	/* DIV4 clocks */
619	CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),	619	CLKDEV_DEV_ID("cpu0", &div4_clks[DIV4_Z]),
620		620
621	/* DIV6 clocks */	621	/* DIV6 clocks */
622	CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),	622	CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),

arch/arm/mach-u300/Kconfig+5−5

-menu "ST-Ericsson AB U300/U335 Platform"
-comment "ST-Ericsson Mobile Platform Products"
 config ARCH_U300
 	bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5
 	depends on MMU
 	help
 	  Support for ST-Ericsson U300 series mobile platforms.
-comment "ST-Ericsson U300/U335 Feature Selections"
+if ARCH_U300
+menu "ST-Ericsson AB U300/U335 Platform"
 config MACH_U300
 	depends on ARCH_U300
 		SPI framework and ARM PL022 support.
 endmenu
+endif

arch/arm/mach-ux500/cache-l2x0.c+1−0

@@ -69,6 +69,7 @@ static int __init ux500_l2x0_init(void) · 68 unmodified lines
69	* some SMI service available.	69	* some SMI service available.
70	*/	70	*/
71	outer_cache.disable = NULL;	71	outer_cache.disable = NULL;
		72	outer_cache.set_debug = NULL;
72		73
73	return 0;	74	return 0;
74	}	75	}

arch/arm/mach-vexpress/tc2_pm.c+10−1

 	} else
 		BUG();
+	/*
+	 * If the CPU is committed to power down, make sure
+	 * the power controller will be in charge of waking it
+	 * up upon IRQ, ie IRQ lines are cut from GIC CPU IF
+	 * to the CPU by disabling the GIC CPU IF to prevent wfi
+	 * from completing execution behind power controller back
+	 */
+	if (!skip_wfi)
+		gic_cpu_if_down();
 	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
 		arch_spin_unlock(&tc2_pm_lock);
 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 	ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
-	gic_cpu_if_down();
 	tc2_pm_down(residency);
 }

arch/arm64/Kconfig.debug+0−7

@@ -6,13 +6,6 @@ config FRAME_POINTER · 5 unmodified lines
6	bool	6	bool
7	default y	7	default y
8		8
9	config DEBUG_STACK_USAGE
10	bool "Enable stack utilization instrumentation"
11	depends on DEBUG_KERNEL
12	help
13	Enables the display of the minimum amount of free stack which each
14	task has ever had available in the sysrq-T output.
15
16	config EARLY_PRINTK	9	config EARLY_PRINTK
17	bool "Early printk support"	10	bool "Early printk support"
18	default y	11	default y

arch/arm64/configs/defconfig+4−1

 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
-# CONFIG_BLK_DEV is not set
+CONFIG_BLK_DEV=y
 CONFIG_SCSI=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
 CONFIG_FUSE_FS=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_FTRACE is not set
 CONFIG_ATOMIC64_SELFTEST=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_BLK=y

arch/arm64/include/asm/hwcap.h+1−1

@@ -43,6 +43,6 @@ · 42 unmodified lines
43	COMPAT_HWCAP_VFPv3\|COMPAT_HWCAP_VFPv4\|\	43	COMPAT_HWCAP_VFPv3\|COMPAT_HWCAP_VFPv4\|\
44	COMPAT_HWCAP_NEON\|COMPAT_HWCAP_IDIV)	44	COMPAT_HWCAP_NEON\|COMPAT_HWCAP_IDIV)
45		45
46	extern unsigned int elf_hwcap;	46	extern unsigned long elf_hwcap;
47	#endif	47	#endif
48	#endif	48	#endif

arch/arm64/include/asm/uaccess.h+6−4

 #define get_user(x, ptr)						\
 ({									\
+	__typeof__(*(ptr)) __user *__p = (ptr);				\
 	might_fault();							\
-	access_ok(VERIFY_READ, (ptr), sizeof(*(ptr))) ?			\
+	access_ok(VERIFY_READ, __p, sizeof(*__p)) ?			\
-		__get_user((x), (ptr)) :				\
+		__get_user((x), __p) :					\
 		((x) = 0, -EFAULT);					\
 })
 #define put_user(x, ptr)						\
 ({									\
+	__typeof__(*(ptr)) __user *__p = (ptr);				\
 	might_fault();							\
-	access_ok(VERIFY_WRITE, (ptr), sizeof(*(ptr))) ?		\
+	access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ?			\
-		__put_user((x), (ptr)) :				\
+		__put_user((x), __p) :					\
 		-EFAULT;						\
 })

arch/arm64/kernel/fpsimd.c+2−0

 void fpsimd_flush_thread(void)
 {
+	preempt_disable();
 	memset(&current->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));
 	fpsimd_load_state(&current->thread.fpsimd_state);
+	preempt_enable();
 }
 #ifdef CONFIG_KERNEL_MODE_NEON

arch/arm64/kernel/process.c+16−5

 void __show_regs(struct pt_regs *regs)
 {
-	int i;
+	int i, top_reg;
+	u64 lr, sp;
+	if (compat_user_mode(regs)) {
+		lr = regs->compat_lr;
+		sp = regs->compat_sp;
+		top_reg = 12;
+	} else {
+		lr = regs->regs[30];
+		sp = regs->sp;
+		top_reg = 29;
+	}
 	show_regs_print_info(KERN_DEFAULT);
 	print_symbol("PC is at %s\n", instruction_pointer(regs));
-	print_symbol("LR is at %s\n", regs->regs[30]);
+	print_symbol("LR is at %s\n", lr);
 	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
-	       regs->pc, regs->regs[30], regs->pstate);
+	       regs->pc, lr, regs->pstate);
-	printk("sp : %016llx\n", regs->sp);
+	printk("sp : %016llx\n", sp);
-	for (i = 29; i >= 0; i--) {
+	for (i = top_reg; i >= 0; i--) {
 		printk("x%-2d: %016llx ", i, regs->regs[i]);
 		if (i % 2 == 0)
 			printk("\n");

arch/arm64/kernel/setup.c+1−1

@@ -57,7 +57,7 @@ · 56 unmodified lines
57	unsigned int processor_id;	57	unsigned int processor_id;
58	EXPORT_SYMBOL(processor_id);	58	EXPORT_SYMBOL(processor_id);
59		59
60	unsigned int elf_hwcap __read_mostly;	60	unsigned long elf_hwcap __read_mostly;
61	EXPORT_SYMBOL_GPL(elf_hwcap);	61	EXPORT_SYMBOL_GPL(elf_hwcap);
62		62
63	static const char *cpu_name;	63	static const char *cpu_name;

arch/arm64/mm/fault.c+1−1

@@ -130,7 +130,7 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr, · 129 unmodified lines
130	force_sig_info(sig, &si, tsk);	130	force_sig_info(sig, &si, tsk);
131	}	131	}
132		132
133	void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)	133	static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
134	{	134	{
135	struct task_struct *tsk = current;	135	struct task_struct *tsk = current;
136	struct mm_struct *mm = tsk->active_mm;	136	struct mm_struct *mm = tsk->active_mm;

arch/arm64/mm/tlb.S+1−1

@@ -35,7 +35,7 @@ · 34 unmodified lines
35	*/	35	*/
36	ENTRY(__cpu_flush_user_tlb_range)	36	ENTRY(__cpu_flush_user_tlb_range)
37	vma_vm_mm x3, x2 // get vma->vm_mm	37	vma_vm_mm x3, x2 // get vma->vm_mm
38	mmid x3, x3 // get vm_mm->context.id	38	mmid w3, x3 // get vm_mm->context.id
39	dsb sy	39	dsb sy
40	lsr x0, x0, #12 // align address	40	lsr x0, x0, #12 // align address
41	lsr x1, x1, #12	41	lsr x1, x1, #12

arch/avr32/include/asm/Kbuild+16−2

@@ -1,6 +1,20 @@
1		1
2	generic-y += clkdev.h	2	generic-y += clkdev.h
		3	generic-y += cputime.h
		4	generic-y += delay.h
		5	generic-y += device.h
		6	generic-y += div64.h
		7	generic-y += emergency-restart.h
3	generic-y += exec.h	8	generic-y += exec.h
4	generic-y += trace_clock.h	9	generic-y += futex.h
		10	generic-y += preempt.h
		11	generic-y += irq_regs.h
5	generic-y += param.h	12	generic-y += param.h
6	generic-y += preempt.h	13	generic-y += local.h
		14	generic-y += local64.h
		15	generic-y += percpu.h
		16	generic-y += scatterlist.h
		17	generic-y += sections.h
		18	generic-y += topology.h
		19	generic-y += trace_clock.h
		20	generic-y += xor.h

arch/avr32/include/asm/cputime.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_CPUTIME_H
2	#define __ASM_AVR32_CPUTIME_H
3
4	#include <asm-generic/cputime.h>
5
6	#endif /* __ASM_AVR32_CPUTIME_H */

arch/avr32/include/asm/delay.h+0−1

@@ -1 +0,0 @@
1	#include <asm-generic/delay.h>

arch/avr32/include/asm/device.h+0−7

@@ -1,7 +0,0 @@
1	/*
2	* Arch specific extensions to struct device
3	*
4	* This file is released under the GPLv2
5	*/
6	#include <asm-generic/device.h>
7

arch/avr32/include/asm/div64.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_DIV64_H
2	#define __ASM_AVR32_DIV64_H
3
4	#include <asm-generic/div64.h>
5
6	#endif /* __ASM_AVR32_DIV64_H */

arch/avr32/include/asm/emergency-restart.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_EMERGENCY_RESTART_H
2	#define __ASM_AVR32_EMERGENCY_RESTART_H
3
4	#include <asm-generic/emergency-restart.h>
5
6	#endif /* __ASM_AVR32_EMERGENCY_RESTART_H */

arch/avr32/include/asm/futex.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_FUTEX_H
2	#define __ASM_AVR32_FUTEX_H
3
4	#include <asm-generic/futex.h>
5
6	#endif /* __ASM_AVR32_FUTEX_H */

arch/avr32/include/asm/irq_regs.h+0−1

@@ -1 +0,0 @@
1	#include <asm-generic/irq_regs.h>

arch/avr32/include/asm/local.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_LOCAL_H
2	#define __ASM_AVR32_LOCAL_H
3
4	#include <asm-generic/local.h>
5
6	#endif /* __ASM_AVR32_LOCAL_H */

arch/avr32/include/asm/local64.h+0−1

@@ -1 +0,0 @@
1	#include <asm-generic/local64.h>

arch/avr32/include/asm/percpu.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_PERCPU_H
2	#define __ASM_AVR32_PERCPU_H
3
4	#include <asm-generic/percpu.h>
5
6	#endif /* __ASM_AVR32_PERCPU_H */

arch/avr32/include/asm/scatterlist.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_SCATTERLIST_H
2	#define __ASM_AVR32_SCATTERLIST_H
3
4	#include <asm-generic/scatterlist.h>
5
6	#endif /* __ASM_AVR32_SCATTERLIST_H */

arch/avr32/include/asm/sections.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_SECTIONS_H
2	#define __ASM_AVR32_SECTIONS_H
3
4	#include <asm-generic/sections.h>
5
6	#endif /* __ASM_AVR32_SECTIONS_H */

arch/avr32/include/asm/topology.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef __ASM_AVR32_TOPOLOGY_H
2	#define __ASM_AVR32_TOPOLOGY_H
3
4	#include <asm-generic/topology.h>
5
6	#endif /* __ASM_AVR32_TOPOLOGY_H */

arch/avr32/include/asm/xor.h+0−6

@@ -1,6 +0,0 @@
1	#ifndef _ASM_XOR_H
2	#define _ASM_XOR_H
3
4	#include <asm-generic/xor.h>
5
6	#endif

arch/avr32/kernel/process.c+1−1

@@ -289,7 +289,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, · 288 unmodified lines
289	memset(childregs, 0, sizeof(struct pt_regs));	289	memset(childregs, 0, sizeof(struct pt_regs));
290	p->thread.cpu_context.r0 = arg;	290	p->thread.cpu_context.r0 = arg;
291	p->thread.cpu_context.r1 = usp; /* fn */	291	p->thread.cpu_context.r1 = usp; /* fn */
292	p->thread.cpu_context.r2 = syscall_return;	292	p->thread.cpu_context.r2 = (unsigned long)syscall_return;
293	p->thread.cpu_context.pc = (unsigned long)ret_from_kernel_thread;	293	p->thread.cpu_context.pc = (unsigned long)ret_from_kernel_thread;
294	childregs->sr = MODE_SUPERVISOR;	294	childregs->sr = MODE_SUPERVISOR;
295	} else {	295	} else {

arch/avr32/kernel/time.c+8−1

 	case CLOCK_EVT_MODE_SHUTDOWN:
 		sysreg_write(COMPARE, 0);
 		pr_debug("%s: stop\n", evdev->name);
-		cpu_idle_poll_ctrl(false);
+		if (evdev->mode == CLOCK_EVT_MODE_ONESHOT ||
+		    evdev->mode == CLOCK_EVT_MODE_RESUME) {
+			/*
+			 * Only disable idle poll if we have forced that
+			 * in a previous call.
+			 */
+			cpu_idle_poll_ctrl(false);
+		}
 		break;
 	default:
 		BUG();

arch/mips/Makefile+0−3

@@ -288,9 +288,6 @@ endif · 287 unmodified lines
288	vmlinux.32: vmlinux	288	vmlinux.32: vmlinux
289	$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@	289	$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
290		290
291
292	#obj-$(CONFIG_KPROBES) += kprobes.o
293
294	#	291	#
295	# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit	292	# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
296	# ELF files from 32-bit files by conversion.	293	# ELF files from 32-bit files by conversion.

arch/mips/alchemy/board-mtx1.c+1−1

@@ -276,7 +276,7 @@ static struct platform_device mtx1_pci_host = { · 275 unmodified lines
276	.resource = alchemy_pci_host_res,	276	.resource = alchemy_pci_host_res,
277	};	277	};
278		278
279	static struct __initdata platform_device * mtx1_devs[] = {	279	static struct platform_device *mtx1_devs[] __initdata = {
280	&mtx1_pci_host,	280	&mtx1_pci_host,
281	&mtx1_gpio_leds,	281	&mtx1_gpio_leds,
282	&mtx1_wdt,	282	&mtx1_wdt,

arch/mips/alchemy/common/usb.c+2−1

 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/syscore_ops.h>
+#include <asm/cpu.h>
 #include <asm/mach-au1x00/au1000.h>
 /* control register offsets */
 {
 #if defined(CONFIG_DMA_COHERENT)
 	/* Au1200 AB USB does not support coherent memory */
-	if (!(read_c0_prid() & 0xff)) {
+	if (!(read_c0_prid() & PRID_REV_MASK)) {
 		printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
 		printk(KERN_INFO "Au1200 USB: update your board or re-configure"
 				 " the kernel\n");

arch/mips/bcm63xx/cpu.c+2−2

@@ -306,14 +306,14 @@ void __init bcm63xx_cpu_init(void) · 305 unmodified lines
306		306
307	switch (c->cputype) {	307	switch (c->cputype) {
308	case CPU_BMIPS3300:	308	case CPU_BMIPS3300:
309	if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)	309	if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
310	__cpu_name[cpu] = "Broadcom BCM6338";	310	__cpu_name[cpu] = "Broadcom BCM6338";
311	/* fall-through */	311	/* fall-through */
312	case CPU_BMIPS32:	312	case CPU_BMIPS32:
313	chipid_reg = BCM_6345_PERF_BASE;	313	chipid_reg = BCM_6345_PERF_BASE;
314	break;	314	break;
315	case CPU_BMIPS4350:	315	case CPU_BMIPS4350:
316	switch ((read_c0_prid() & 0xff)) {	316	switch ((read_c0_prid() & PRID_REV_MASK)) {
317	case 0x04:	317	case 0x04:
318	chipid_reg = BCM_3368_PERF_BASE;	318	chipid_reg = BCM_3368_PERF_BASE;
319	break;	319	break;

arch/mips/boot/dts/include/dt-bindings+1−1

@@ -1 +1 @@
1	../../../../../include/dt-bindings	1	../../../../../include/dt-bindings

arch/mips/cavium-octeon/csrc-octeon.c+1−0

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	#include <linux/smp.h>	12	#include <linux/smp.h>
13		13
14	#include <asm/cpu-info.h>	14	#include <asm/cpu-info.h>
		15	#include <asm/cpu-type.h>
15	#include <asm/time.h>	16	#include <asm/time.h>
16		17
17	#include <asm/octeon/octeon.h>	18	#include <asm/octeon/octeon.h>

arch/mips/dec/prom/init.c+1−0

@@ -13,6 +13,7 @@ · 12 unmodified lines
13		13
14	#include <asm/bootinfo.h>	14	#include <asm/bootinfo.h>
15	#include <asm/cpu.h>	15	#include <asm/cpu.h>
		16	#include <asm/cpu-type.h>
16	#include <asm/processor.h>	17	#include <asm/processor.h>
17		18
18	#include <asm/dec/prom.h>	19	#include <asm/dec/prom.h>

arch/mips/include/asm/cpu-features.h+1−7

 #include <asm/cpu-info.h>
 #include <cpu-feature-overrides.h>
-#ifndef current_cpu_type
-#define current_cpu_type()	current_cpu_data.cputype
-#endif
-#define boot_cpu_type()		cpu_data[0].cputype
 /*
  * SMP assumption: Options of CPU 0 are a superset of all processors.
  * This is true for all known MIPS systems.
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
- * pre-MIPS32/MIPS53 processors have CLO, CLZ.	The IDT RC64574 is 64-bit and
+ * pre-MIPS32/MIPS64 processors have CLO, CLZ.	The IDT RC64574 is 64-bit and
  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */

arch/mips/include/asm/cpu-info.h+1−0

@@ -84,6 +84,7 @@ struct cpuinfo_mips { · 83 unmodified lines
84	extern struct cpuinfo_mips cpu_data[];	84	extern struct cpuinfo_mips cpu_data[];
85	#define current_cpu_data cpu_data[smp_processor_id()]	85	#define current_cpu_data cpu_data[smp_processor_id()]
86	#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]	86	#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
		87	#define boot_cpu_data cpu_data[0]
87		88
88	extern void cpu_probe(void);	89	extern void cpu_probe(void);
89	extern void cpu_report(void);	90	extern void cpu_report(void);

arch/mips/include/asm/cpu-type.h+203−0

@@ -0,0 +1,203 @@
	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003, 2004 Ralf Baechle
	7	* Copyright (C) 2004 Maciej W. Rozycki
	8	*/
	9	#ifndef __ASM_CPU_TYPE_H
	10	#define __ASM_CPU_TYPE_H
	11
	12	#include <linux/smp.h>
	13	#include <linux/compiler.h>
	14
	15	static inline int __pure __get_cpu_type(const int cpu_type)
	16	{
	17	switch (cpu_type) {
	18	#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) \|\| \
	19	defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
	20	case CPU_LOONGSON2:
	21	#endif
	22
	23	#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
	24	case CPU_LOONGSON1:
	25	#endif
	26
	27	#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
	28	case CPU_4KC:
	29	case CPU_ALCHEMY:
	30	case CPU_BMIPS3300:
	31	case CPU_BMIPS4350:
	32	case CPU_PR4450:
	33	case CPU_BMIPS32:
	34	case CPU_JZRISC:
	35	#endif
	36
	37	#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) \|\| \
	38	defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
	39	case CPU_4KEC:
	40	#endif
	41
	42	#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
	43	case CPU_4KSC:
	44	case CPU_24K:
	45	case CPU_34K:
	46	case CPU_1004K:
	47	case CPU_74K:
	48	case CPU_M14KC:
	49	case CPU_M14KEC:
	50	#endif
	51
	52	#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
	53	case CPU_5KC:
	54	case CPU_5KE:
	55	case CPU_20KC:
	56	case CPU_25KF:
	57	case CPU_SB1:
	58	case CPU_SB1A:
	59	#endif
	60
	61	#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
	62	/*
	63	* All MIPS64 R2 processors have their own special symbols. That is,
	64	* there currently is no pure R2 core
	65	*/
	66	#endif
	67
	68	#ifdef CONFIG_SYS_HAS_CPU_R3000
	69	case CPU_R2000:
	70	case CPU_R3000:
	71	case CPU_R3000A:
	72	case CPU_R3041:
	73	case CPU_R3051:
	74	case CPU_R3052:
	75	case CPU_R3081:
	76	case CPU_R3081E:
	77	#endif
	78
	79	#ifdef CONFIG_SYS_HAS_CPU_TX39XX
	80	case CPU_TX3912:
	81	case CPU_TX3922:
	82	case CPU_TX3927:
	83	#endif
	84
	85	#ifdef CONFIG_SYS_HAS_CPU_VR41XX
	86	case CPU_VR41XX:
	87	case CPU_VR4111:
	88	case CPU_VR4121:
	89	case CPU_VR4122:
	90	case CPU_VR4131:
	91	case CPU_VR4133:
	92	case CPU_VR4181:
	93	case CPU_VR4181A:
	94	#endif
	95
	96	#ifdef CONFIG_SYS_HAS_CPU_R4300
	97	case CPU_R4300:
	98	case CPU_R4310:
	99	#endif
	100
	101	#ifdef CONFIG_SYS_HAS_CPU_R4X00
	102	case CPU_R4000PC:
	103	case CPU_R4000SC:
	104	case CPU_R4000MC:
	105	case CPU_R4200:
	106	case CPU_R4400PC:
	107	case CPU_R4400SC:
	108	case CPU_R4400MC:
	109	case CPU_R4600:
	110	case CPU_R4700:
	111	case CPU_R4640:
	112	case CPU_R4650:
	113	#endif
	114
	115	#ifdef CONFIG_SYS_HAS_CPU_TX49XX
	116	case CPU_TX49XX:
	117	#endif
	118
	119	#ifdef CONFIG_SYS_HAS_CPU_R5000
	120	case CPU_R5000:
	121	#endif
	122
	123	#ifdef CONFIG_SYS_HAS_CPU_R5432
	124	case CPU_R5432:
	125	#endif
	126
	127	#ifdef CONFIG_SYS_HAS_CPU_R5500
	128	case CPU_R5500:
	129	#endif
	130
	131	#ifdef CONFIG_SYS_HAS_CPU_R6000
	132	case CPU_R6000:
	133	case CPU_R6000A:
	134	#endif
	135
	136	#ifdef CONFIG_SYS_HAS_CPU_NEVADA
	137	case CPU_NEVADA:
	138	#endif
	139
	140	#ifdef CONFIG_SYS_HAS_CPU_R8000
	141	case CPU_R8000:
	142	#endif
	143
	144	#ifdef CONFIG_SYS_HAS_CPU_R10000
	145	case CPU_R10000:
	146	case CPU_R12000:
	147	case CPU_R14000:
	148	#endif
	149	#ifdef CONFIG_SYS_HAS_CPU_RM7000
	150	case CPU_RM7000:
	151	case CPU_SR71000:
	152	#endif
	153	#ifdef CONFIG_SYS_HAS_CPU_RM9000
	154	case CPU_RM9000:
	155	#endif
	156	#ifdef CONFIG_SYS_HAS_CPU_SB1
	157	case CPU_SB1:
	158	case CPU_SB1A:
	159	#endif
	160	#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
	161	case CPU_CAVIUM_OCTEON:
	162	case CPU_CAVIUM_OCTEON_PLUS:
	163	case CPU_CAVIUM_OCTEON2:
	164	#endif
	165
	166	#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
	167	case CPU_BMIPS4380:
	168	#endif
	169
	170	#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
	171	case CPU_BMIPS5000:
	172	#endif
	173
	174	#ifdef CONFIG_SYS_HAS_CPU_XLP
	175	case CPU_XLP:
	176	#endif
	177
	178	#ifdef CONFIG_SYS_HAS_CPU_XLR
	179	case CPU_XLR:
	180	#endif
	181	break;
	182	default:
	183	unreachable();
	184	}
	185
	186	return cpu_type;
	187	}
	188
	189	static inline int __pure current_cpu_type(void)
	190	{
	191	const int cpu_type = current_cpu_data.cputype;
	192
	193	return __get_cpu_type(cpu_type);
	194	}
	195
	196	static inline int __pure boot_cpu_type(void)
	197	{
	198	const int cpu_type = cpu_data[0].cputype;
	199
	200	return __get_cpu_type(cpu_type);
	201	}
	202
	203	#endif /* __ASM_CPU_TYPE_H */

arch/mips/include/asm/cpu.h+29−9

  *	  various MIPS cpu types.
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
- * Copyright (C) 2004  Maciej W. Rozycki
+ * Copyright (C) 2004, 2013  Maciej W. Rozycki
  */
 #ifndef _ASM_CPU_H
 #define _ASM_CPU_H
-/* Assigned Company values for bits 23:16 of the PRId Register
+/*
-   (CP0 register 15, select 0).	 As of the MIPS32 and MIPS64 specs from
+   As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
-   MTI, the PRId register is defined in this (backwards compatible)
+   register 15, select 0) is defined in this (backwards compatible) way:
-   way:
   +----------------+----------------+----------------+----------------+
   | Company Options| Company ID	    | Processor ID   | Revision	      |
    spec.
 */
+#define PRID_OPT_MASK		0xff000000
+/*
+ * Assigned Company values for bits 23:16 of the PRId register.
+ */
+#define PRID_COMP_MASK		0xff0000
 #define PRID_COMP_LEGACY	0x000000
 #define PRID_COMP_MIPS		0x010000
 #define PRID_COMP_BROADCOM	0x020000
 #define PRID_COMP_INGENIC	0xd00000
 /*
- * Assigned values for the product ID register.	 In order to detect a
+ * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
- * certain CPU type exactly eventually additional registers may need to
+ * register.  In order to detect a certain CPU type exactly eventually
- * be examined.	 These are valid when 23:16 == PRID_COMP_LEGACY
+ * additional registers may need to be examined.
  */
+#define PRID_IMP_MASK		0xff00
+/*
+ * These are valid when 23:16 == PRID_COMP_LEGACY
+ */
 #define PRID_IMP_R2000		0x0100
 #define PRID_IMP_AU1_REV1	0x0100
 #define PRID_IMP_AU1_REV2	0x0200
 #define PRID_IMP_NETLOGIC_XLP2XX	0x1200
 /*
- * Definitions for 7:0 on legacy processors
+ * Particular Revision values for bits 7:0 of the PRId register.
  */
 #define PRID_REV_MASK		0x00ff
+/*
+ * Definitions for 7:0 on legacy processors
+ */
 #define PRID_REV_TX4927		0x0022
 #define PRID_REV_TX4937		0x0030
 #define PRID_REV_R4400		0x0040
  *  31				   16 15	     8 7	      0
  */
+#define FPIR_IMP_MASK		0xff00
 #define FPIR_IMP_NONE		0x0000
 enum cpu_type_enum {

arch/mips/include/asm/mach-au1x00/au1000.h+3−1

 #include <linux/io.h>
 #include <linux/irq.h>
+#include <asm/cpu.h>
 /* cpu pipeline flush */
 void static inline au_sync(void)
 {
 static inline int alchemy_get_cputype(void)
 {
-	switch (read_c0_prid() & 0xffff0000) {
+	switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
 	case 0x00030000:
 		return ALCHEMY_CPU_AU1000;
 		break;

arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h+2−0

@@ -8,6 +8,8 @@ · 7 unmodified lines
8	#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H	8	#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
9	#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H	9	#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
10		10
		11	#include <asm/cpu.h>
		12
11	/*	13	/*
12	* IP22 with a variety of processors so we can't use defaults for everything.	14	* IP22 with a variety of processors so we can't use defaults for everything.
13	*/	15	*/

arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h+2−0

@@ -8,6 +8,8 @@ · 7 unmodified lines
8	#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H	8	#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
9	#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H	9	#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
10		10
		11	#include <asm/cpu.h>
		12
11	/*	13	/*
12	* IP27 only comes with R10000 family processors all using the same config	14	* IP27 only comes with R10000 family processors all using the same config
13	*/	15	*/

arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h+2−0

@@ -9,6 +9,8 @@ · 8 unmodified lines
9	#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H	9	#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
10	#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H	10	#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
11		11
		12	#include <asm/cpu.h>
		13
12	/*	14	/*
13	* IP28 only comes with R10000 family processors all using the same config	15	* IP28 only comes with R10000 family processors all using the same config
14	*/	16	*/

arch/mips/include/asm/mipsregs.h+7−0

@@ -603,6 +603,13 @@ · 602 unmodified lines
603	#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)	603	#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
604	#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)	604	#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
605		605
		606	#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
		607	#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
		608	#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
		609	#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
		610	#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
		611	#define MIPS_CONF5_K (_ULCAST_(1) << 30)
		612
606	#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)	613	#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
607		614
608	#define MIPS_CONF7_WII (_ULCAST_(1) << 31)	615	#define MIPS_CONF7_WII (_ULCAST_(1) << 31)

arch/mips/include/asm/pci.h+12−0

@@ -83,6 +83,18 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) · 82 unmodified lines
83	extern int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,	83	extern int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
84	enum pci_mmap_state mmap_state, int write_combine);	84	enum pci_mmap_state mmap_state, int write_combine);
85		85
		86	#define HAVE_ARCH_PCI_RESOURCE_TO_USER
		87
		88	static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
		89	const struct resource rsrc, resource_size_t start,
		90	resource_size_t *end)
		91	{
		92	phys_t size = resource_size(rsrc);
		93
		94	*start = fixup_bigphys_addr(rsrc->start, size);
		95	*end = rsrc->start + size;
		96	}
		97
86	/*	98	/*
87	* Dynamic DMA mapping stuff.	99	* Dynamic DMA mapping stuff.
88	* MIPS has everything mapped statically.	100	* MIPS has everything mapped statically.

arch/mips/include/asm/timex.h+32−1

@@ -10,7 +10,9 @@ · 9 unmodified lines
10		10
11	#ifdef __KERNEL__	11	#ifdef __KERNEL__
12		12
		13	#include <asm/cpu-features.h>
13	#include <asm/mipsregs.h>	14	#include <asm/mipsregs.h>
		15	#include <asm/cpu-type.h>
14		16
15	/*	17	/*
16	* This is the clock rate of the i8253 PIT. A MIPS system may not have	18	* This is the clock rate of the i8253 PIT. A MIPS system may not have
@@ -33,9 +35,38 @@ · 16 unmodified lines
33		35
34	typedef unsigned int cycles_t;	36	typedef unsigned int cycles_t;
35		37
		38	/*
		39	* On R4000/R4400 before version 5.0 an erratum exists such that if the
		40	* cycle counter is read in the exact moment that it is matching the
		41	* compare register, no interrupt will be generated.
		42	*
		43	* There is a suggested workaround and also the erratum can't strike if
		44	* the compare interrupt isn't being used as the clock source device.
		45	* However for now the implementaton of this function doesn't get these
		46	* fine details right.
		47	*/
36	static inline cycles_t get_cycles(void)	48	static inline cycles_t get_cycles(void)
37	{	49	{
38	return 0;	50	switch (boot_cpu_type()) {
		51	case CPU_R4400PC:
		52	case CPU_R4400SC:
		53	case CPU_R4400MC:
		54	if ((read_c0_prid() & 0xff) >= 0x0050)
		55	return read_c0_count();
		56	break;
		57
		58	case CPU_R4000PC:
		59	case CPU_R4000SC:
		60	case CPU_R4000MC:
		61	break;
		62
		63	default:
		64	if (cpu_has_counter)
		65	return read_c0_count();
		66	break;
		67	}
		68
		69	return 0; /* no usable counter */
39	}	70	}
40		71
41	#endif /* __KERNEL__ */	72	#endif /* __KERNEL__ */

arch/mips/include/asm/vga.h+2−1

 #ifndef _ASM_VGA_H
 #define _ASM_VGA_H
+#include <asm/addrspace.h>
 #include <asm/byteorder.h>
 /*
  *	access the videoram directly without any black magic.
  */
-#define VGA_MAP_MEM(x, s)	(0xb0000000L + (unsigned long)(x))
+#define VGA_MAP_MEM(x, s)	CKSEG1ADDR(0x10000000L + (unsigned long)(x))
 #define vga_readb(x)	(*(x))
 #define vga_writeb(x, y)	(*(y) = (x))

arch/mips/kernel/cpu-probe.c+37−21

 #include <asm/bugs.h>
 #include <asm/cpu.h>
+#include <asm/cpu-type.h>
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
 #include <asm/watch.h>
 {
 	struct cpuinfo_mips *c = &current_cpu_data;
-	switch (c->cputype) {
+	switch (current_cpu_type()) {
 	case CPU_34K:
 		/*
 		 * Erratum "RPS May Cause Incorrect Instruction Execution"
  */
 static inline int __cpu_has_fpu(void)
 {
-	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
+	return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
 }
 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 	return config4 & MIPS_CONF_M;
 }
+static inline unsigned int decode_config5(struct cpuinfo_mips *c)
+{
+	unsigned int config5;
+	config5 = read_c0_config5();
+	config5 &= ~MIPS_CONF5_UFR;
+	write_c0_config5(config5);
+	return config5 & MIPS_CONF_M;
+}
 static void decode_configs(struct cpuinfo_mips *c)
 {
 	int ok;
 		ok = decode_config3(c);
 	if (ok)
 		ok = decode_config4(c);
+	if (ok)
+		ok = decode_config5(c);
 	mips_probe_watch_registers(c);
 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 {
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_R2000:
 		c->cputype = CPU_R2000;
 		__cpu_name[cpu] = "R2000";
 		c->tlbsize = 64;
 		break;
 	case PRID_IMP_R3000:
-		if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
+		if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 			if (cpu_has_confreg()) {
 				c->cputype = CPU_R3081E;
 				__cpu_name[cpu] = "R3081";
 		break;
 	case PRID_IMP_R4000:
 		if (read_c0_config() & CONF_SC) {
-			if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
+			if ((c->processor_id & PRID_REV_MASK) >=
+			    PRID_REV_R4400) {
 				c->cputype = CPU_R4400PC;
 				__cpu_name[cpu] = "R4400PC";
 			} else {
 				__cpu_name[cpu] = "R4000PC";
 			}
 		} else {
-			if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
+			if ((c->processor_id & PRID_REV_MASK) >=
+			    PRID_REV_R4400) {
 				c->cputype = CPU_R4400SC;
 				__cpu_name[cpu] = "R4400SC";
 			} else {
 			__cpu_name[cpu] = "TX3927";
 			c->tlbsize = 64;
 		} else {
-			switch (c->processor_id & 0xff) {
+			switch (c->processor_id & PRID_REV_MASK) {
 			case PRID_REV_TX3912:
 				c->cputype = CPU_TX3912;
 				__cpu_name[cpu] = "TX3912";
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_4KC:
 		c->cputype = CPU_4KC;
 		__cpu_name[cpu] = "MIPS 4Kc";
 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_AU1_REV1:
 	case PRID_IMP_AU1_REV2:
 		c->cputype = CPU_ALCHEMY;
 			break;
 		case 4:
 			__cpu_name[cpu] = "Au1200";
-			if ((c->processor_id & 0xff) == 2)
+			if ((c->processor_id & PRID_REV_MASK) == 2)
 				__cpu_name[cpu] = "Au1250";
 			break;
 		case 5:
 {
 	decode_configs(c);
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_SB1:
 		c->cputype = CPU_SB1;
 		__cpu_name[cpu] = "SiByte SB1";
 		/* FPU in pass1 is known to have issues. */
-		if ((c->processor_id & 0xff) < 0x02)
+		if ((c->processor_id & PRID_REV_MASK) < 0x02)
 			c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 		break;
 	case PRID_IMP_SB1A:
 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_SR71000:
 		c->cputype = CPU_SR71000;
 		__cpu_name[cpu] = "Sandcraft SR71000";
 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_PR4450:
 		c->cputype = CPU_PR4450;
 		__cpu_name[cpu] = "Philips PR4450";
 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_BMIPS32_REV4:
 	case PRID_IMP_BMIPS32_REV8:
 		c->cputype = CPU_BMIPS32;
 		set_elf_platform(cpu, "bmips3300");
 		break;
 	case PRID_IMP_BMIPS43XX: {
-		int rev = c->processor_id & 0xff;
+		int rev = c->processor_id & PRID_REV_MASK;
 		if (rev >= PRID_REV_BMIPS4380_LO &&
 				rev <= PRID_REV_BMIPS4380_HI) {
 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_CAVIUM_CN38XX:
 	case PRID_IMP_CAVIUM_CN31XX:
 	case PRID_IMP_CAVIUM_CN30XX:
 	decode_configs(c);
 	/* JZRISC does not implement the CP0 counter. */
 	c->options &= ~MIPS_CPU_COUNTER;
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_JZRISC:
 		c->cputype = CPU_JZRISC;
 		__cpu_name[cpu] = "Ingenic JZRISC";
 {
 	decode_configs(c);
-	if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
+	if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
 		c->cputype = CPU_ALCHEMY;
 		__cpu_name[cpu] = "Au1300";
 		/* following stuff is not for Alchemy */
 			MIPS_CPU_EJTAG	 |
 			MIPS_CPU_LLSC);
-	switch (c->processor_id & 0xff00) {
+	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_NETLOGIC_XLP2XX:
 		c->cputype = CPU_XLP;
 		__cpu_name[cpu] = "Broadcom XLPII";
 	c->cputype	= CPU_UNKNOWN;
 	c->processor_id = read_c0_prid();
-	switch (c->processor_id & 0xff0000) {
+	switch (c->processor_id & PRID_COMP_MASK) {
 	case PRID_COMP_LEGACY:
 		cpu_probe_legacy(c, cpu);
 		break;

arch/mips/kernel/idle.c+2−1

 #include <linux/sched.h>
 #include <asm/cpu.h>
 #include <asm/cpu-info.h>
+#include <asm/cpu-type.h>
 #include <asm/idle.h>
 #include <asm/mipsregs.h>
 		return;
 	}
-	switch (c->cputype) {
+	switch (current_cpu_type()) {
 	case CPU_R3081:
 	case CPU_R3081E:
 		cpu_wait = r3081_wait;

arch/mips/kernel/time.c+1−0

@@ -24,6 +24,7 @@ · 23 unmodified lines
24	#include <linux/export.h>	24	#include <linux/export.h>
25		25
26	#include <asm/cpu-features.h>	26	#include <asm/cpu-features.h>
		27	#include <asm/cpu-type.h>
27	#include <asm/div64.h>	28	#include <asm/div64.h>
28	#include <asm/smtc_ipi.h>	29	#include <asm/smtc_ipi.h>
29	#include <asm/time.h>	30	#include <asm/time.h>

arch/mips/kernel/traps.c+2−1

 #include <asm/break.h>
 #include <asm/cop2.h>
 #include <asm/cpu.h>
+#include <asm/cpu-type.h>
 #include <asm/dsp.h>
 #include <asm/fpu.h>
 #include <asm/fpu_emulator.h>
 		regs->regs[rt] = read_c0_count();
 		return 0;
 	case 3:		/* Count register resolution */
-		switch (current_cpu_data.cputype) {
+		switch (current_cpu_type()) {
 		case CPU_20KC:
 		case CPU_25KF:
 			regs->regs[rt] = 1;

arch/mips/mm/c-octeon.c+4−2

 #include <asm/bootinfo.h>
 #include <asm/cacheops.h>
 #include <asm/cpu-features.h>
+#include <asm/cpu-type.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/r4kcache.h>
 	unsigned long dcache_size;
 	unsigned int config1;
 	struct cpuinfo_mips *c = &current_cpu_data;
+	int cputype = current_cpu_type();
 	config1 = read_c0_config1();
-	switch (c->cputype) {
+	switch (cputype) {
 	case CPU_CAVIUM_OCTEON:
 	case CPU_CAVIUM_OCTEON_PLUS:
 		c->icache.linesz = 2 << ((config1 >> 19) & 7);
 			c->icache.sets * c->icache.ways * c->icache.linesz;
 		c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
 		c->dcache.linesz = 128;
-		if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
+		if (cputype == CPU_CAVIUM_OCTEON_PLUS)
 			c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
 		else
 			c->dcache.sets = 1; /* CN3XXX has one Dcache set */

arch/mips/mm/c-r4k.c+34−16

 #include <linux/highmem.h>
 #include <linux/kernel.h>
 #include <linux/linkage.h>
+#include <linux/preempt.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/mm.h>
 #include <asm/cacheops.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
+#include <asm/cpu-type.h>
 #include <asm/io.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 	/* Catch bad driver code */
 	BUG_ON(size == 0);
+	preempt_disable();
 	if (cpu_has_inclusive_pcaches) {
 		if (size >= scache_size)
 			r4k_blast_scache();
 		else
 			blast_scache_range(addr, addr + size);
+		preempt_enable();
 		__sync();
 		return;
 	}
 		R4600_HIT_CACHEOP_WAR_IMPL;
 		blast_dcache_range(addr, addr + size);
 	}
+	preempt_enable();
 	bc_wback_inv(addr, size);
 	__sync();
 	/* Catch bad driver code */
 	BUG_ON(size == 0);
+	preempt_disable();
 	if (cpu_has_inclusive_pcaches) {
 		if (size >= scache_size)
 			r4k_blast_scache();
 			 */
 			blast_inv_scache_range(addr, addr + size);
 		}
+		preempt_enable();
 		__sync();
 		return;
 	}
 		R4600_HIT_CACHEOP_WAR_IMPL;
 		blast_inv_dcache_range(addr, addr + size);
 	}
+	preempt_enable();
 	bc_inv(addr, size);
 	__sync();
 static inline void alias_74k_erratum(struct cpuinfo_mips *c)
 {
+	unsigned int imp = c->processor_id & PRID_IMP_MASK;
+	unsigned int rev = c->processor_id & PRID_REV_MASK;
 	/*
 	 * Early versions of the 74K do not update the cache tags on a
 	 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
 	 * aliases. In this case it is better to treat the cache as always
 	 * having aliases.
 	 */
-	if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
+	switch (imp) {
-		c->dcache.flags |= MIPS_CACHE_VTAG;
+	case PRID_IMP_74K:
-	if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
+		if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
-		write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+			c->dcache.flags |= MIPS_CACHE_VTAG;
-	if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
+		if (rev == PRID_REV_ENCODE_332(2, 4, 0))
-	    ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
+			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
-		c->dcache.flags |= MIPS_CACHE_VTAG;
+		break;
-		write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+	case PRID_IMP_1074K:
+		if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
+			c->dcache.flags |= MIPS_CACHE_VTAG;
+			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+		}
+		break;
+	default:
+		BUG();
 	}
 }
 	unsigned long config1;
 	unsigned int lsize;
-	switch (c->cputype) {
+	switch (current_cpu_type()) {
 	case CPU_R4600:			/* QED style two way caches? */
 	case CPU_R4700:
 	case CPU_R5000:
 	 * presumably no vendor is shipping his hardware in the "bad"
 	 * configuration.
 	 */
-	if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
+	if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
+	    (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
 	    !(config & CONF_SC) && c->icache.linesz != 16 &&
 	    PAGE_SIZE <= 0x8000)
 		panic("Improper R4000SC processor configuration detected");
 	 * normally they'd suffer from aliases but magic in the hardware deals
 	 * with that for us so we don't need to take care ourselves.
 	 */
-	switch (c->cputype) {
+	switch (current_cpu_type()) {
 	case CPU_20KC:
 	case CPU_25KF:
 	case CPU_SB1:
 	case CPU_34K:
 	case CPU_74K:
 	case CPU_1004K:
-		if (c->cputype == CPU_74K)
+		if (current_cpu_type() == CPU_74K)
 			alias_74k_erratum(c);
 		if ((read_c0_config7() & (1 << 16))) {
 			/* effectively physically indexed dcache,
 			c->dcache.flags |= MIPS_CACHE_ALIASES;
 	}
-	switch (c->cputype) {
+	switch (current_cpu_type()) {
 	case CPU_20KC:
 		/*
 		 * Some older 20Kc chips doesn't have the 'VI' bit in
 	 * processors don't have a S-cache that would be relevant to the
 	 * Linux memory management.
 	 */
-	switch (c->cputype) {
+	switch (current_cpu_type()) {
 	case CPU_R4000SC:
 	case CPU_R4000MC:
 	case CPU_R4400SC:
 {
 	extern char __weak except_vec2_generic;
 	extern char __weak except_vec2_sb1;
-	struct cpuinfo_mips *c = &current_cpu_data;
-	switch (c->cputype) {
+	switch (current_cpu_type()) {
 	case CPU_SB1:
 	case CPU_SB1A:
 		set_uncached_handler(0x100, &except_vec2_sb1, 0x80);

arch/mips/mm/dma-default.c+5−8

 #include <linux/highmem.h>
 #include <asm/cache.h>
+#include <asm/cpu-type.h>
 #include <asm/io.h>
 #include <dma-coherence.h>
 {
 	int i;
-	/* Make sure that gcc doesn't leave the empty loop body.  */
+	if (cpu_needs_post_dma_flush(dev))
-	for (i = 0; i < nelems; i++, sg++) {
+		for (i = 0; i < nelems; i++, sg++)
-		if (cpu_needs_post_dma_flush(dev))
 			__dma_sync(sg_page(sg), sg->offset, sg->length,
 				   direction);
-	}
 }
 static void mips_dma_sync_sg_for_device(struct device *dev,
 {
 	int i;
-	/* Make sure that gcc doesn't leave the empty loop body.  */
+	if (!plat_device_is_coherent(dev))
-	for (i = 0; i < nelems; i++, sg++) {
+		for (i = 0; i < nelems; i++, sg++)
-		if (!plat_device_is_coherent(dev))
 			__dma_sync(sg_page(sg), sg->offset, sg->length,
 				   direction);
-	}
 }
 int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)

arch/mips/mm/page.c+1−0

@@ -18,6 +18,7 @@ · 17 unmodified lines
18		18
19	#include <asm/bugs.h>	19	#include <asm/bugs.h>
20	#include <asm/cacheops.h>	20	#include <asm/cacheops.h>
		21	#include <asm/cpu-type.h>
21	#include <asm/inst.h>	22	#include <asm/inst.h>
22	#include <asm/io.h>	23	#include <asm/io.h>
23	#include <asm/page.h>	24	#include <asm/page.h>

arch/mips/mm/sc-mips.c+2−1

 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <asm/cpu-type.h>
 #include <asm/mipsregs.h>
 #include <asm/bcache.h>
 #include <asm/cacheops.h>
 	unsigned int tmp;
 	/* Check the bypass bit (L2B) */
-	switch (c->cputype) {
+	switch (current_cpu_type()) {
 	case CPU_34K:
 	case CPU_74K:
 	case CPU_1004K:

arch/mips/mm/tlb-r4k.c+1−0

@@ -16,6 +16,7 @@ · 15 unmodified lines
16	#include <linux/module.h>	16	#include <linux/module.h>
17		17
18	#include <asm/cpu.h>	18	#include <asm/cpu.h>
		19	#include <asm/cpu-type.h>
19	#include <asm/bootinfo.h>	20	#include <asm/bootinfo.h>
20	#include <asm/mmu_context.h>	21	#include <asm/mmu_context.h>
21	#include <asm/pgtable.h>	22	#include <asm/pgtable.h>

arch/mips/mm/tlbex.c+1−0

@@ -30,6 +30,7 @@ · 29 unmodified lines
30	#include <linux/cache.h>	30	#include <linux/cache.h>
31		31
32	#include <asm/cacheflush.h>	32	#include <asm/cacheflush.h>
		33	#include <asm/cpu-type.h>
33	#include <asm/pgtable.h>	34	#include <asm/pgtable.h>
34	#include <asm/war.h>	35	#include <asm/war.h>
35	#include <asm/uasm.h>	36	#include <asm/uasm.h>

arch/mips/mti-malta/malta-time.c+3−2

 #include <linux/timex.h>
 #include <linux/mc146818rtc.h>
+#include <asm/cpu.h>
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/hardirq.h>
 #endif
 #if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ)
-	unsigned int prid = read_c0_prid() & 0xffff00;
+	unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
 	/*
 	 * XXXKYMA: hardwire the CPU frequency to Host Freq/4
 void __init plat_time_init(void)
 {
-	unsigned int prid = read_c0_prid() & 0xffff00;
+	unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
 	unsigned int freq;
 	estimate_frequencies();

arch/mips/mti-sead3/sead3-time.c+2−1

  */
 #include <linux/init.h>
+#include <asm/cpu.h>
 #include <asm/setup.h>
 #include <asm/time.h>
 #include <asm/irq.h>
  */
 static unsigned int __init estimate_cpu_frequency(void)
 {
-	unsigned int prid = read_c0_prid() & 0xffff00;
+	unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
 	unsigned int tick = 0;
 	unsigned int freq;
 	unsigned int orig;

arch/mips/netlogic/xlr/fmn-config.c+2−1

 #include <linux/irq.h>
 #include <linux/interrupt.h>
+#include <asm/cpu.h>
 #include <asm/mipsregs.h>
 #include <asm/netlogic/xlr/fmn.h>
 #include <asm/netlogic/xlr/xlr.h>
 	int processor_id, num_core;
 	num_core = hweight32(nlm_current_node()->coremask);
-	processor_id = read_c0_prid() & 0xff00;
+	processor_id = read_c0_prid() & PRID_IMP_MASK;
 	setup_cpu_fmninfo(cpu, num_core);
 	switch (processor_id) {

arch/mips/oprofile/common.c+1−0

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	#include <linux/oprofile.h>	12	#include <linux/oprofile.h>
13	#include <linux/smp.h>	13	#include <linux/smp.h>
14	#include <asm/cpu-info.h>	14	#include <asm/cpu-info.h>
		15	#include <asm/cpu-type.h>
15		16
16	#include "op_impl.h"	17	#include "op_impl.h"
17		18

arch/mips/pci/pci-bcm1480.c+1−0

@@ -39,6 +39,7 @@ · 38 unmodified lines
39	#include <linux/mm.h>	39	#include <linux/mm.h>
40	#include <linux/console.h>	40	#include <linux/console.h>
41	#include <linux/tty.h>	41	#include <linux/tty.h>
		42	#include <linux/vt.h>
42		43
43	#include <asm/sibyte/bcm1480_regs.h>	44	#include <asm/sibyte/bcm1480_regs.h>
44	#include <asm/sibyte/bcm1480_scd.h>	45	#include <asm/sibyte/bcm1480_scd.h>

arch/mips/sibyte/bcm1480/setup.c+2−1

 #include <linux/string.h>
 #include <asm/bootinfo.h>
+#include <asm/cpu.h>
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 #include <asm/sibyte/sb1250.h>
 	uint64_t sys_rev;
 	int plldiv;
-	sb1_pass = read_c0_prid() & 0xff;
+	sb1_pass = read_c0_prid() & PRID_REV_MASK;
 	sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
 	soc_type = SYS_SOC_TYPE(sys_rev);
 	part_type = G_SYS_PART(sys_rev);

arch/mips/sibyte/sb1250/setup.c+2−1

 #include <linux/string.h>
 #include <asm/bootinfo.h>
+#include <asm/cpu.h>
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 #include <asm/sibyte/sb1250.h>
 	int plldiv;
 	int bad_config = 0;
-	sb1_pass = read_c0_prid() & 0xff;
+	sb1_pass = read_c0_prid() & PRID_REV_MASK;
 	sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
 	soc_type = SYS_SOC_TYPE(sys_rev);
 	soc_pass = G_SYS_REVISION(sys_rev);

arch/mips/sni/setup.c+2−1

 #endif
 #include <asm/bootinfo.h>
+#include <asm/cpu.h>
 #include <asm/io.h>
 #include <asm/reboot.h>
 #include <asm/sni.h>
 		system_type = "RM300-Cxx";
 		break;
 	case SNI_BRD_PCI_DESKTOP:
-		switch (read_c0_prid() & 0xff00) {
+		switch (read_c0_prid() & PRID_IMP_MASK) {
 		case PRID_IMP_R4600:
 		case PRID_IMP_R4700:
 			system_type = "RM200-C20";

arch/openrisc/include/asm/prom.h+0−44

@@ -14,53 +14,9 @@ · 13 unmodified lines
14	* the Free Software Foundation; either version 2 of the License, or	14	* the Free Software Foundation; either version 2 of the License, or
15	* (at your option) any later version.	15	* (at your option) any later version.
16	*/	16	*/
17
18	#include <linux/of.h> /* linux/of.h gets to determine #include ordering */
19
20	#ifndef _ASM_OPENRISC_PROM_H	17	#ifndef _ASM_OPENRISC_PROM_H
21	#define _ASM_OPENRISC_PROM_H	18	#define _ASM_OPENRISC_PROM_H
22	#ifdef __KERNEL__
23	#ifndef __ASSEMBLY__
24		19
25	#include <linux/types.h>
26	#include <asm/irq.h>
27	#include <linux/irqdomain.h>
28	#include <linux/atomic.h>
29	#include <linux/of_irq.h>
30	#include <linux/of_fdt.h>
31	#include <linux/of_address.h>
32	#include <linux/proc_fs.h>
33	#include <linux/platform_device.h>
34	#define HAVE_ARCH_DEVTREE_FIXUPS	20	#define HAVE_ARCH_DEVTREE_FIXUPS
35		21
36	/* Other Prototypes */
37	extern int early_uartlite_console(void);
38
39	/* Parse the ibm,dma-window property of an OF node into the busno, phys and
40	* size parameters.
41	*/
42	void of_parse_dma_window(struct device_node dn, const void dma_window_prop,
43	unsigned long busno, unsigned long phys, unsigned long *size);
44
45	extern void kdump_move_device_tree(void);
46
47	/* Get the MAC address */
48	extern const void of_get_mac_address(struct device_node np);
49
50	/**
51	* of_irq_map_pci - Resolve the interrupt for a PCI device
52	* @pdev: the device whose interrupt is to be resolved
53	* @out_irq: structure of_irq filled by this function
54	*
55	* This function resolves the PCI interrupt for a given PCI device. If a
56	* device-node exists for a given pci_dev, it will use normal OF tree
57	* walking. If not, it will implement standard swizzling and walk up the
58	* PCI tree until an device-node is found, at which point it will finish
59	* resolving using the OF tree walking.
60	*/
61	struct pci_dev;
62	extern int of_irq_map_pci(struct pci_dev pdev, struct of_irq out_irq);
63
64	#endif /* __ASSEMBLY__ */
65	#endif /* __KERNEL__ */
66	#endif /* _ASM_OPENRISC_PROM_H */	22	#endif /* _ASM_OPENRISC_PROM_H */

arch/parisc/mm/fault.c+3−2

 	if (user_mode(regs))
 		flags |= FAULT_FLAG_USER;
+	acc_type = parisc_acctyp(code, regs->iir);
 	if (acc_type & VM_WRITE)
 		flags |= FAULT_FLAG_WRITE;
 retry:
 good_area:
-	acc_type = parisc_acctyp(code,regs->iir);
 	if ((vma->vm_flags & acc_type) != acc_type)
 		goto bad_area;

arch/powerpc/boot/Makefile+2−2

@@ -74,7 +74,7 @@ src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c · 73 unmodified lines
74	src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c	74	src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
75	src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c	75	src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c
76		76
77	src-plat-y := of.c	77	src-plat-y := of.c epapr.c
78	src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \	78	src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
79	treeboot-walnut.c cuboot-acadia.c \	79	treeboot-walnut.c cuboot-acadia.c \
80	cuboot-kilauea.c simpleboot.c \	80	cuboot-kilauea.c simpleboot.c \
@@ -97,7 +97,7 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \ · 16 unmodified lines
97	prpmc2800.c	97	prpmc2800.c
98	src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c	98	src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
99	src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c	99	src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
100	src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c	100	src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
101		101
102	src-wlib := $(sort $(src-wlib-y))	102	src-wlib := $(sort $(src-wlib-y))
103	src-plat := $(sort $(src-plat-y))	103	src-plat := $(sort $(src-plat-y))

arch/powerpc/boot/epapr-wrapper.c+9−0

@@ -0,0 +1,9 @@
	1	extern void epapr_platform_init(unsigned long r3, unsigned long r4,
	2	unsigned long r5, unsigned long r6,
	3	unsigned long r7);
	4
	5	void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
	6	unsigned long r6, unsigned long r7)
	7	{
	8	epapr_platform_init(r3, r4, r5, r6, r7);
	9	}

arch/powerpc/boot/epapr.c+2−2

@@ -48,8 +48,8 @@ static void platform_fixups(void) · 47 unmodified lines
48	fdt_addr, fdt_totalsize((void *)fdt_addr), ima_size);	48	fdt_addr, fdt_totalsize((void *)fdt_addr), ima_size);
49	}	49	}
50		50
51	void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,	51	void epapr_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
52	unsigned long r6, unsigned long r7)	52	unsigned long r6, unsigned long r7)
53	{	53	{
54	epapr_magic = r6;	54	epapr_magic = r6;
55	ima_size = r7;	55	ima_size = r7;

arch/powerpc/boot/of.c+15−1

 static unsigned long claim_base;
+void epapr_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+			 unsigned long r6, unsigned long r7);
 static void *of_try_claim(unsigned long size)
 {
 	unsigned long addr = 0;
 	}
 }
-void platform_init(unsigned long a1, unsigned long a2, void *promptr)
+static void of_platform_init(unsigned long a1, unsigned long a2, void *promptr)
 {
 	platform_ops.image_hdr = of_image_hdr;
 	platform_ops.malloc = of_try_claim;
 		loader_info.initrd_size = a2;
 	}
 }
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+		   unsigned long r6, unsigned long r7)
+{
+	/* Detect OF vs. ePAPR boot */
+	if (r5)
+		of_platform_init(r3, r4, (void *)r5);
+	else
+		epapr_platform_init(r3, r4, r5, r6, r7);
+}

arch/powerpc/boot/wrapper+5−4

 case "$platform" in
 pseries)
-    platformo=$object/of.o
+    platformo="$object/of.o $object/epapr.o"
     link_address='0x4000000'
     ;;
 maple)
-    platformo=$object/of.o
+    platformo="$object/of.o $object/epapr.o"
     link_address='0x400000'
     ;;
 pmac|chrp)
-    platformo=$object/of.o
+    platformo="$object/of.o $object/epapr.o"
     ;;
 coff)
-    platformo="$object/crt0.o $object/of.o"
+    platformo="$object/crt0.o $object/of.o $object/epapr.o"
     lds=$object/zImage.coff.lds
     link_address='0x500000'
     pie=
     platformo="$object/treeboot-iss4xx.o"
     ;;
 epapr)
+    platformo="$object/epapr.o $object/epapr-wrapper.o"
     link_address='0x20000000'
     pie=-pie
     ;;

arch/powerpc/include/asm/irq.h+2−2

@@ -69,9 +69,9 @@ extern struct thread_info *softirq_ctx[NR_CPUS]; · 68 unmodified lines
69		69
70	extern void irq_ctx_init(void);	70	extern void irq_ctx_init(void);
71	extern void call_do_softirq(struct thread_info *tp);	71	extern void call_do_softirq(struct thread_info *tp);
72	extern int call_handle_irq(int irq, void *p1,	72	extern void call_do_irq(struct pt_regs regs, struct thread_info tp);
73	struct thread_info tp, void func);
74	extern void do_IRQ(struct pt_regs *regs);	73	extern void do_IRQ(struct pt_regs *regs);
		74	extern void __do_irq(struct pt_regs *regs);
75		75
76	int irq_choose_cpu(const struct cpumask *mask);	76	int irq_choose_cpu(const struct cpumask *mask);
77		77

arch/powerpc/include/asm/processor.h+1−3

 struct thread_struct {
 	unsigned long	ksp;		/* Kernel stack pointer */
-	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */
 #ifdef CONFIG_PPC64
 	unsigned long	ksp_vsid;
 #endif
 #endif
 #ifdef CONFIG_PPC32
 	void		*pgdir;		/* root of page-table tree */
+	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */
 #endif
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 	/*
 #else
 #define INIT_THREAD  { \
 	.ksp = INIT_SP, \
-	.ksp_limit = INIT_SP_LIMIT, \
 	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
 	.fs = KERNEL_DS, \
 	.fpr = {{0}}, \

arch/powerpc/kernel/asm-offsets.c+2−1

 	DEFINE(TASKTHREADPPR, offsetof(struct task_struct, thread.ppr));
 #else
 	DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
+	DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
+	DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
 #endif /* CONFIG_PPC64 */
 	DEFINE(KSP, offsetof(struct thread_struct, ksp));
-	DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
 	DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
 #ifdef CONFIG_BOOKE
 	DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0]));

arch/powerpc/kernel/iommu.c+1−1

@@ -661,7 +661,7 @@ struct iommu_table iommu_init_table(struct iommu_table tbl, int nid) · 660 unmodified lines
661	/* number of bytes needed for the bitmap */	661	/* number of bytes needed for the bitmap */
662	sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);	662	sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
663		663
664	page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz));	664	page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
665	if (!page)	665	if (!page)
666	panic("iommu_init_table: Can't allocate %ld bytes\n", sz);	666	panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
667	tbl->it_map = page_address(page);	667	tbl->it_map = page_address(page);

arch/powerpc/kernel/irq.c+44−56

 }
 #endif
-static inline void handle_one_irq(unsigned int irq)
-{
-	struct thread_info *curtp, *irqtp;
-	unsigned long saved_sp_limit;
-	struct irq_desc *desc;
-	desc = irq_to_desc(irq);
-	if (!desc)
-		return;
-	/* Switch to the irq stack to handle this */
-	curtp = current_thread_info();
-	irqtp = hardirq_ctx[smp_processor_id()];
-	if (curtp == irqtp) {
-		/* We're already on the irq stack, just handle it */
-		desc->handle_irq(irq, desc);
-		return;
-	}
-	saved_sp_limit = current->thread.ksp_limit;
-	irqtp->task = curtp->task;
-	irqtp->flags = 0;
-	/* Copy the softirq bits in preempt_count so that the
-	 * softirq checks work in the hardirq context. */
-	irqtp->preempt_count = (irqtp->preempt_count & ~SOFTIRQ_MASK) |
-			       (curtp->preempt_count & SOFTIRQ_MASK);
-	current->thread.ksp_limit = (unsigned long)irqtp +
-		_ALIGN_UP(sizeof(struct thread_info), 16);
-	call_handle_irq(irq, desc, irqtp, desc->handle_irq);
-	current->thread.ksp_limit = saved_sp_limit;
-	irqtp->task = NULL;
-	/* Set any flag that may have been set on the
-	 * alternate stack
-	 */
-	if (irqtp->flags)
-		set_bits(irqtp->flags, &curtp->flags);
-}
 static inline void check_stack_overflow(void)
 {
 #ifdef CONFIG_DEBUG_STACKOVERFLOW
 #endif
 }
-void do_IRQ(struct pt_regs *regs)
+void __do_irq(struct pt_regs *regs)
 {
-	struct pt_regs *old_regs = set_irq_regs(regs);
+	struct irq_desc *desc;
 	unsigned int irq;
 	irq_enter();
 	 */
 	irq = ppc_md.get_irq();
-	/* We can hard enable interrupts now */
+	/* We can hard enable interrupts now to allow perf interrupts */
 	may_hard_irq_enable();
 	/* And finally process it */
-	if (irq != NO_IRQ)
+	if (unlikely(irq == NO_IRQ))
-		handle_one_irq(irq);
-	else
 		__get_cpu_var(irq_stat).spurious_irqs++;
+	else {
+		desc = irq_to_desc(irq);
+		if (likely(desc))
+			desc->handle_irq(irq, desc);
+	}
 	trace_irq_exit(regs);
 	irq_exit();
+}
+void do_IRQ(struct pt_regs *regs)
+{
+	struct pt_regs *old_regs = set_irq_regs(regs);
+	struct thread_info *curtp, *irqtp;
+	/* Switch to the irq stack to handle this */
+	curtp = current_thread_info();
+	irqtp = hardirq_ctx[raw_smp_processor_id()];
+	/* Already there ? */
+	if (unlikely(curtp == irqtp)) {
+		__do_irq(regs);
+		set_irq_regs(old_regs);
+		return;
+	}
+	/* Prepare the thread_info in the irq stack */
+	irqtp->task = curtp->task;
+	irqtp->flags = 0;
+	/* Copy the preempt_count so that the [soft]irq checks work. */
+	irqtp->preempt_count = curtp->preempt_count;
+	/* Switch stack and call */
+	call_do_irq(regs, irqtp);
+	/* Restore stack limit */
+	irqtp->task = NULL;
+	/* Copy back updates to the thread_info */
+	if (irqtp->flags)
+		set_bits(irqtp->flags, &curtp->flags);
 	set_irq_regs(old_regs);
 }
 		memset((void *)softirq_ctx[i], 0, THREAD_SIZE);
 		tp = softirq_ctx[i];
 		tp->cpu = i;
-		tp->preempt_count = 0;
 		memset((void *)hardirq_ctx[i], 0, THREAD_SIZE);
 		tp = hardirq_ctx[i];
 		tp->cpu = i;
-		tp->preempt_count = HARDIRQ_OFFSET;
 	}
 }
 static inline void do_softirq_onstack(void)
 {
 	struct thread_info *curtp, *irqtp;
-	unsigned long saved_sp_limit = current->thread.ksp_limit;
 	curtp = current_thread_info();
 	irqtp = softirq_ctx[smp_processor_id()];
 	irqtp->task = curtp->task;
 	irqtp->flags = 0;
-	current->thread.ksp_limit = (unsigned long)irqtp +
-				    _ALIGN_UP(sizeof(struct thread_info), 16);
 	call_do_softirq(irqtp);
-	current->thread.ksp_limit = saved_sp_limit;
 	irqtp->task = NULL;
 	/* Set any flag that may have been set on the

arch/powerpc/kernel/misc_32.S+20−5

 	.text
+/*
+ * We store the saved ksp_limit in the unused part
+ * of the STACK_FRAME_OVERHEAD
+ */
 _GLOBAL(call_do_softirq)
 	mflr	r0
 	stw	r0,4(r1)
+	lwz	r10,THREAD+KSP_LIMIT(r2)
+	addi	r11,r3,THREAD_INFO_GAP
 	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
 	mr	r1,r3
+	stw	r10,8(r1)
+	stw	r11,THREAD+KSP_LIMIT(r2)
 	bl	__do_softirq
+	lwz	r10,8(r1)
 	lwz	r1,0(r1)
 	lwz	r0,4(r1)
+	stw	r10,THREAD+KSP_LIMIT(r2)
 	mtlr	r0
 	blr
-_GLOBAL(call_handle_irq)
+_GLOBAL(call_do_irq)
 	mflr	r0
 	stw	r0,4(r1)
-	mtctr	r6
+	lwz	r10,THREAD+KSP_LIMIT(r2)
-	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
+	addi	r11,r3,THREAD_INFO_GAP
-	mr	r1,r5
+	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
-	bctrl
+	mr	r1,r4
+	stw	r10,8(r1)
+	stw	r11,THREAD+KSP_LIMIT(r2)
+	bl	__do_irq
+	lwz	r10,8(r1)
 	lwz	r1,0(r1)
 	lwz	r0,4(r1)
+	stw	r10,THREAD+KSP_LIMIT(r2)
 	mtlr	r0
 	blr

arch/powerpc/kernel/misc_64.S+4−6

 	mtlr	r0
 	blr
-_GLOBAL(call_handle_irq)
+_GLOBAL(call_do_irq)
-	ld	r8,0(r6)
 	mflr	r0
 	std	r0,16(r1)
-	mtctr	r8
+	stdu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
-	stdu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
+	mr	r1,r4
-	mr	r1,r5
+	bl	.__do_irq
-	bctrl
 	ld	r1,0(r1)
 	ld	r0,16(r1)
 	mtlr	r0

arch/powerpc/kernel/process.c+2−1

@@ -1000,9 +1000,10 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, · 999 unmodified lines
1000	kregs = (struct pt_regs *) sp;	1000	kregs = (struct pt_regs *) sp;
1001	sp -= STACK_FRAME_OVERHEAD;	1001	sp -= STACK_FRAME_OVERHEAD;
1002	p->thread.ksp = sp;	1002	p->thread.ksp = sp;
		1003	#ifdef CONFIG_PPC32
1003	p->thread.ksp_limit = (unsigned long)task_stack_page(p) +	1004	p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1004	_ALIGN_UP(sizeof(struct thread_info), 16);	1005	_ALIGN_UP(sizeof(struct thread_info), 16);
1005		1006	#endif
1006	#ifdef CONFIG_HAVE_HW_BREAKPOINT	1007	#ifdef CONFIG_HAVE_HW_BREAKPOINT
1007	p->thread.ptrace_bps[0] = NULL;	1008	p->thread.ptrace_bps[0] = NULL;
1008	#endif	1009	#endif

arch/powerpc/kernel/prom_init.c+21−0

 static cell_t __initdata regbuf[1024];
+static bool rtas_has_query_cpu_stopped;
 /*
  * Error results ... some OF calls will return "-1" on error, some
 	prom_setprop(rtas_node, "/rtas", "linux,rtas-entry",
 		     &val, sizeof(val));
+	/* Check if it supports "query-cpu-stopped-state" */
+	if (prom_getprop(rtas_node, "query-cpu-stopped-state",
+			 &val, sizeof(val)) != PROM_ERROR)
+		rtas_has_query_cpu_stopped = true;
 #if defined(CONFIG_PPC_POWERNV) && defined(__BIG_ENDIAN__)
 	/* PowerVN takeover hack */
 	prom_rtas_data = base;
 		= (void *) LOW_ADDR(__secondary_hold_acknowledge);
 	unsigned long secondary_hold = LOW_ADDR(__secondary_hold);
+	/*
+	 * On pseries, if RTAS supports "query-cpu-stopped-state",
+	 * we skip this stage, the CPUs will be started by the
+	 * kernel using RTAS.
+	 */
+	if ((of_platform == PLATFORM_PSERIES ||
+	     of_platform == PLATFORM_PSERIES_LPAR) &&
+	    rtas_has_query_cpu_stopped) {
+		prom_printf("prom_hold_cpus: skipped\n");
+		return;
+	}
 	prom_debug("prom_hold_cpus: start...\n");
 	prom_debug("    1) spinloop       = 0x%x\n", (unsigned long)spinloop);
 	prom_debug("    1) *spinloop      = 0x%x\n", *spinloop);
 	 * On non-powermacs, put all CPUs in spin-loops.
 	 *
 	 * PowerMacs use a different mechanism to spin CPUs
+	 *
+	 * (This must be done after instanciating RTAS)
 	 */
 	if (of_platform != PLATFORM_POWERMAC &&
 	    of_platform != PLATFORM_OPAL)

arch/powerpc/kernel/sysfs.c+16−2

 #include <asm/machdep.h>
 #include <asm/smp.h>
 #include <asm/pmc.h>
+#include <asm/firmware.h>
 #include "cacheinfo.h"
 SYSFS_PMCSETUP(dscr, SPRN_DSCR);
 SYSFS_PMCSETUP(pir, SPRN_PIR);
+/*
+  Lets only enable read for phyp resources and
+  enable write when needed with a separate function.
+  Lets be conservative and default to pseries.
+*/
 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
-static DEVICE_ATTR(purr, 0600, show_purr, store_purr);
+static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
 unsigned long dscr_default = 0;
 EXPORT_SYMBOL(dscr_default);
+static void add_write_permission_dev_attr(struct device_attribute *attr)
+{
+	attr->attr.mode |= 0200;
+}
 static ssize_t show_dscr_default(struct device *dev,
 		struct device_attribute *attr, char *buf)
 {
 	if (cpu_has_feature(CPU_FTR_MMCRA))
 		device_create_file(s, &dev_attr_mmcra);
-	if (cpu_has_feature(CPU_FTR_PURR))
+	if (cpu_has_feature(CPU_FTR_PURR)) {
+		if (!firmware_has_feature(FW_FEATURE_LPAR))
+			add_write_permission_dev_attr(&dev_attr_purr);
 		device_create_file(s, &dev_attr_purr);
+	}
 	if (cpu_has_feature(CPU_FTR_SPURR))
 		device_create_file(s, &dev_attr_spurr);

arch/powerpc/kernel/tm.S+64−31

 	TABORT(R3)
 	blr
+	.section	".toc","aw"
+DSCR_DEFAULT:
+	.tc dscr_default[TC],dscr_default
+	.section	".text"
 /* void tm_reclaim(struct thread_struct *thread,
  *                 unsigned long orig_msr,
 	mr	r15, r14
 	ori	r15, r15, MSR_FP
 	li	r16, MSR_RI
+	ori	r16, r16, MSR_EE /* IRQs hard off */
 	andc	r15, r15, r16
 	oris	r15, r15, MSR_VEC@h
 #ifdef CONFIG_VSX
 	std	r1, PACATMSCRATCH(r13)
 	ld	r1, PACAR1(r13)
+	/* Store the PPR in r11 and reset to decent value */
+	std	r11, GPR11(r1)			/* Temporary stash */
+	mfspr	r11, SPRN_PPR
+	HMT_MEDIUM
 	/* Now get some more GPRS free */
 	std	r7, GPR7(r1)			/* Temporary stash */
 	std	r12, GPR12(r1)			/* ''   ''    ''   */
 	ld	r12, STACK_PARAM(0)(r1)		/* Param 0, thread_struct * */
+	std	r11, THREAD_TM_PPR(r12)		/* Store PPR and free r11 */
 	addi	r7, r12, PT_CKPT_REGS		/* Thread's ckpt_regs */
 	/* Make r7 look like an exception frame so that we
 	SAVE_GPR(0, r7)				/* user r0 */
 	SAVE_GPR(2, r7)			/* user r2 */
 	SAVE_4GPRS(3, r7)			/* user r3-r6 */
-	SAVE_4GPRS(8, r7)			/* user r8-r11 */
+	SAVE_GPR(8, r7)				/* user r8 */
+	SAVE_GPR(9, r7)				/* user r9 */
+	SAVE_GPR(10, r7)			/* user r10 */
 	ld	r3, PACATMSCRATCH(r13)		/* user r1 */
 	ld	r4, GPR7(r1)			/* user r7 */
-	ld	r5, GPR12(r1)			/* user r12 */
+	ld	r5, GPR11(r1)			/* user r11 */
-	GET_SCRATCH0(6)				/* user r13 */
+	ld	r6, GPR12(r1)			/* user r12 */
+	GET_SCRATCH0(8)				/* user r13 */
 	std	r3, GPR1(r7)
 	std	r4, GPR7(r7)
-	std	r5, GPR12(r7)
+	std	r5, GPR11(r7)
-	std	r6, GPR13(r7)
+	std	r6, GPR12(r7)
+	std	r8, GPR13(r7)
 	SAVE_NVGPRS(r7)				/* user r14-r31 */
 	std	r6, _XER(r7)
-	/* ******************** TAR, PPR, DSCR ********** */
+	/* ******************** TAR, DSCR ********** */
 	mfspr	r3, SPRN_TAR
-	mfspr	r4, SPRN_PPR
+	mfspr	r4, SPRN_DSCR
-	mfspr	r5, SPRN_DSCR
 	std	r3, THREAD_TM_TAR(r12)
-	std	r4, THREAD_TM_PPR(r12)
+	std	r4, THREAD_TM_DSCR(r12)
-	std	r5, THREAD_TM_DSCR(r12)
 	/* MSR and flags:  We don't change CRs, and we don't need to alter
 	 * MSR.
 	std	r3, THREAD_TM_TFHAR(r12)
 	std	r4, THREAD_TM_TFIAR(r12)
-	/* AMR and PPR are checkpointed too, but are unsupported by Linux. */
+	/* AMR is checkpointed too, but is unsupported by Linux. */
 	/* Restore original MSR/IRQ state & clear TM mode */
 	ld	r14, TM_FRAME_L0(r1)		/* Orig MSR */
 	mtcr	r4
 	mtlr	r0
 	ld	r2, 40(r1)
+	/* Load system default DSCR */
+	ld	r4, DSCR_DEFAULT@toc(r2)
+	ld	r0, 0(r4)
+	mtspr	SPRN_DSCR, r0
 	blr
 restore_gprs:
-	/* ******************** TAR, PPR, DSCR ********** */
+	/* ******************** CR,LR,CCR,MSR ********** */
-	ld	r4, THREAD_TM_TAR(r3)
+	ld	r4, _CTR(r7)
-	ld	r5, THREAD_TM_PPR(r3)
+	ld	r5, _LINK(r7)
-	ld	r6, THREAD_TM_DSCR(r3)
+	ld	r6, _CCR(r7)
+	ld	r8, _XER(r7)
-	mtspr	SPRN_TAR,	r4
+	mtctr	r4
-	mtspr	SPRN_PPR,	r5
+	mtlr	r5
-	mtspr	SPRN_DSCR,	r6
+	mtcr	r6
+	mtxer	r8
-	/* ******************** CR,LR,CCR,MSR ********** */
+	/* ******************** TAR ******************** */
-	ld	r3, _CTR(r7)
+	ld	r4, THREAD_TM_TAR(r3)
-	ld	r4, _LINK(r7)
+	mtspr	SPRN_TAR,	r4
-	ld	r5, _CCR(r7)
-	ld	r6, _XER(r7)
-	mtctr	r3
+	/* Load up the PPR and DSCR in GPRs only at this stage */
-	mtlr	r4
+	ld	r5, THREAD_TM_DSCR(r3)
-	mtcr	r5
+	ld	r6, THREAD_TM_PPR(r3)
-	mtxer	r6
 	/* Clear the MSR RI since we are about to change R1.  EE is already off
 	 */
 	mtmsrd	r4, 1
 	REST_4GPRS(0, r7)			/* GPR0-3 */
-	REST_GPR(4, r7)				/* GPR4-6 */
+	REST_GPR(4, r7)				/* GPR4 */
-	REST_GPR(5, r7)
-	REST_GPR(6, r7)
 	REST_4GPRS(8, r7)			/* GPR8-11 */
 	REST_2GPRS(12, r7)			/* GPR12-13 */
 	REST_NVGPRS(r7)				/* GPR14-31 */
-	ld	r7, GPR7(r7)			/* GPR7 */
+	/* Load up PPR and DSCR here so we don't run with user values for long
+	 */
+	mtspr	SPRN_DSCR, r5
+	mtspr	SPRN_PPR, r6
+	REST_GPR(5, r7)				/* GPR5-7 */
+	REST_GPR(6, r7)
+	ld	r7, GPR7(r7)
 	/* Commit register state as checkpointed state: */
 	TRECHKPT
+	HMT_MEDIUM
 	/* Our transactional state has now changed.
 	 *
 	 * Now just get out of here.  Transactional (current) state will be
 	mtcr	r4
 	mtlr	r0
 	ld	r2, 40(r1)
+	/* Load system default DSCR */
+	ld	r4, DSCR_DEFAULT@toc(r2)
+	ld	r0, 0(r4)
+	mtspr	SPRN_DSCR, r0
 	blr
 	/* ****************************************************************** */

arch/powerpc/kernel/vio.c+8−4

 	const char *cp;
 	dn = dev->of_node;
-	if (!dn)
+	if (!dn) {
-		return -ENODEV;
+		strcat(buf, "\n");
+		return strlen(buf);
+	}
 	cp = of_get_property(dn, "compatible", NULL);
-	if (!cp)
+	if (!cp) {
-		return -ENODEV;
+		strcat(buf, "\n");
+		return strlen(buf);
+	}
 	return sprintf(buf, "vio:T%sS%s\n", vio_dev->type, cp);
 }

arch/powerpc/lib/checksum_64.S+42−16

 	blr
-	.macro source
+	.macro srcnr
 100:
 	.section __ex_table,"a"
 	.align 3
-	.llong 100b,.Lsrc_error
+	.llong 100b,.Lsrc_error_nr
 	.previous
 	.endm
-	.macro dest
+	.macro source
+150:
+	.section __ex_table,"a"
+	.align 3
+	.llong 150b,.Lsrc_error
+	.previous
+	.endm
+	.macro dstnr
 200:
 	.section __ex_table,"a"
 	.align 3
-	.llong 200b,.Ldest_error
+	.llong 200b,.Ldest_error_nr
+	.previous
+	.endm
+	.macro dest
+250:
+	.section __ex_table,"a"
+	.align 3
+	.llong 250b,.Ldest_error
 	.previous
 	.endm
 	rldicl. r6,r3,64-1,64-2		/* r6 = (r3 & 0x3) >> 1 */
 	beq	.Lcopy_aligned
-	li	r7,4
+	li	r9,4
-	sub	r6,r7,r6
+	sub	r6,r9,r6
 	mtctr	r6
 1:
-source;	lhz	r6,0(r3)		/* align to doubleword */
+srcnr;	lhz	r6,0(r3)		/* align to doubleword */
 	subi	r5,r5,2
 	addi	r3,r3,2
 	adde	r0,r0,r6
-dest;	sth	r6,0(r4)
+dstnr;	sth	r6,0(r4)
 	addi	r4,r4,2
 	bdnz	1b
 	mtctr	r6
 3:
-source;	ld	r6,0(r3)
+srcnr;	ld	r6,0(r3)
 	addi	r3,r3,8
 	adde	r0,r0,r6
-dest;	std	r6,0(r4)
+dstnr;	std	r6,0(r4)
 	addi	r4,r4,8
 	bdnz	3b
 	srdi.	r6,r5,2
 	beq	.Lcopy_tail_halfword
-source;	lwz	r6,0(r3)
+srcnr;	lwz	r6,0(r3)
 	addi	r3,r3,4
 	adde	r0,r0,r6
-dest;	stw	r6,0(r4)
+dstnr;	stw	r6,0(r4)
 	addi	r4,r4,4
 	subi	r5,r5,4
 	srdi.	r6,r5,1
 	beq	.Lcopy_tail_byte
-source;	lhz	r6,0(r3)
+srcnr;	lhz	r6,0(r3)
 	addi	r3,r3,2
 	adde	r0,r0,r6
-dest;	sth	r6,0(r4)
+dstnr;	sth	r6,0(r4)
 	addi	r4,r4,2
 	subi	r5,r5,2
 	andi.	r6,r5,1
 	beq	.Lcopy_finish
-source;	lbz	r6,0(r3)
+srcnr;	lbz	r6,0(r3)
 	sldi	r9,r6,8			/* Pad the byte out to 16 bits */
 	adde	r0,r0,r9
-dest;	stb	r6,0(r4)
+dstnr;	stb	r6,0(r4)
 .Lcopy_finish:
 	addze	r0,r0			/* add in final carry */
 	blr
 .Lsrc_error:
+	ld	r14,STK_REG(R14)(r1)
+	ld	r15,STK_REG(R15)(r1)
+	ld	r16,STK_REG(R16)(r1)
+	addi	r1,r1,STACKFRAMESIZE
+.Lsrc_error_nr:
 	cmpdi	0,r7,0
 	beqlr
 	li	r6,-EFAULT
 	blr
 .Ldest_error:
+	ld	r14,STK_REG(R14)(r1)
+	ld	r15,STK_REG(R15)(r1)
+	ld	r16,STK_REG(R16)(r1)
+	addi	r1,r1,STACKFRAMESIZE
+.Ldest_error_nr:
 	cmpdi	0,r8,0
 	beqlr
 	li	r6,-EFAULT

arch/powerpc/lib/sstep.c+2−1

@@ -1505,6 +1505,7 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr) · 1504 unmodified lines
1505	*/	1505	*/
1506	if ((ra == 1) && !(regs->msr & MSR_PR) \	1506	if ((ra == 1) && !(regs->msr & MSR_PR) \
1507	&& (val3 >= (regs->gpr[1] - STACK_INT_FRAME_SIZE))) {	1507	&& (val3 >= (regs->gpr[1] - STACK_INT_FRAME_SIZE))) {
		1508	#ifdef CONFIG_PPC32
1508	/*	1509	/*
1509	* Check if we will touch kernel sack overflow	1510	* Check if we will touch kernel sack overflow
1510	*/	1511	*/
@@ -1513,7 +1514,7 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr) · 2 unmodified lines
1513	err = -EINVAL;	1514	err = -EINVAL;
1514	break;	1515	break;
1515	}	1516	}
1516		1517	#endif /* CONFIG_PPC32 */
1517	/*	1518	/*
1518	* Check if we already set since that means we'll	1519	* Check if we already set since that means we'll
1519	* lose the previous value.	1520	* lose the previous value.

arch/powerpc/mm/init_64.c+4−0

@@ -300,5 +300,9 @@ void vmemmap_free(unsigned long start, unsigned long end) · 299 unmodified lines
300	{	300	{
301	}	301	}
302		302
		303	void register_page_bootmem_memmap(unsigned long section_nr,
		304	struct page *start_page, unsigned long size)
		305	{
		306	}
303	#endif /* CONFIG_SPARSEMEM_VMEMMAP */	307	#endif /* CONFIG_SPARSEMEM_VMEMMAP */
304		308

arch/powerpc/mm/mem.c+9−0

 }
 #endif /* ! CONFIG_NEED_MULTIPLE_NODES */
+static void __init register_page_bootmem_info(void)
+{
+	int i;
+	for_each_online_node(i)
+		register_page_bootmem_info_node(NODE_DATA(i));
+}
 void __init mem_init(void)
 {
 #ifdef CONFIG_SWIOTLB
 	swiotlb_init(0);
 #endif
+	register_page_bootmem_info();
 	high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
 	set_max_mapnr(max_pfn);
 	free_all_bootmem();

arch/powerpc/perf/power8-pmu.c+3−2

 #define MMCR1_UNIT_SHIFT(pmc)		(60 - (4 * ((pmc) - 1)))
 #define MMCR1_COMBINE_SHIFT(pmc)	(35 - ((pmc) - 1))
 #define MMCR1_PMCSEL_SHIFT(pmc)		(24 - (((pmc) - 1)) * 8)
+#define MMCR1_FAB_SHIFT			36
 #define MMCR1_DC_QUAL_SHIFT		47
 #define MMCR1_IC_QUAL_SHIFT		46
 		 * the threshold bits are used for the match value.
 		 */
 		if (event_is_fab_match(event[i])) {
-			mmcr1 |= (event[i] >> EVENT_THR_CTL_SHIFT) &
+			mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
-				  EVENT_THR_CTL_MASK;
+				  EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
 		} else {
 			val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
 			mmcra |= val << MMCRA_THR_CTL_SHIFT;

arch/powerpc/platforms/pseries/smp.c+16−10

 	alloc_bootmem_cpumask_var(&of_spin_mask);
-	/* Mark threads which are still spinning in hold loops. */
+	/*
-	if (cpu_has_feature(CPU_FTR_SMT)) {
+	 * Mark threads which are still spinning in hold loops
-		for_each_present_cpu(i) {
+	 *
-			if (cpu_thread_in_core(i) == 0)
+	 * We know prom_init will not have started them if RTAS supports
-				cpumask_set_cpu(i, of_spin_mask);
+	 * query-cpu-stopped-state.
-		}
+	 */
-	} else {
+	if (rtas_token("query-cpu-stopped-state") == RTAS_UNKNOWN_SERVICE) {
-		cpumask_copy(of_spin_mask, cpu_present_mask);
+		if (cpu_has_feature(CPU_FTR_SMT)) {
+			for_each_present_cpu(i) {
+				if (cpu_thread_in_core(i) == 0)
+					cpumask_set_cpu(i, of_spin_mask);
+			}
+		} else
+			cpumask_copy(of_spin_mask, cpu_present_mask);
+		cpumask_clear_cpu(boot_cpuid, of_spin_mask);
 	}
-	cpumask_clear_cpu(boot_cpuid, of_spin_mask);
 	/* Non-lpar has additional take/give timebase */
 	if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
 		smp_ops->give_timebase = rtas_give_timebase;

arch/s390/Kconfig+1−1

 	select ARCH_INLINE_WRITE_UNLOCK_IRQ
 	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE
 	select ARCH_SAVE_PAGE_KEYS if HIBERNATION
+	select ARCH_USE_CMPXCHG_LOCKREF
 	select ARCH_WANT_IPC_PARSE_VERSION
 	select BUILDTIME_EXTABLE_SORT
 	select CLONE_BACKWARDS2
 	select GENERIC_TIME_VSYSCALL_OLD
 	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 	select HAVE_ARCH_JUMP_LABEL if !MARCH_G5
-	select HAVE_ARCH_MUTEX_CPU_RELAX
 	select HAVE_ARCH_SECCOMP_FILTER
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT

arch/s390/include/asm/mutex.h+0−2

@@ -7,5 +7,3 @@ · 6 unmodified lines
7	*/	7	*/
8		8
9	#include <asm-generic/mutex-dec.h>	9	#include <asm-generic/mutex-dec.h>
10
11	#define arch_mutex_cpu_relax() barrier()

arch/s390/include/asm/processor.h+2−0

@@ -198,6 +198,8 @@ static inline void cpu_relax(void) · 197 unmodified lines
198	barrier();	198	barrier();
199	}	199	}
200		200
		201	#define arch_mutex_cpu_relax() barrier()
		202
201	static inline void psw_set_key(unsigned int key)	203	static inline void psw_set_key(unsigned int key)
202	{	204	{
203	asm volatile("spka 0(%0)" : : "d" (key));	205	asm volatile("spka 0(%0)" : : "d" (key));

arch/s390/include/asm/spinlock.h+5−0

 extern int arch_spin_trylock_retry(arch_spinlock_t *);
 extern void arch_spin_relax(arch_spinlock_t *lock);
+static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
+{
+	return lock.owner_cpu == 0;
+}
 static inline void arch_spin_lock(arch_spinlock_t *lp)
 {
 	int old;

arch/score/Kconfig+4−0

 config SCORE
        def_bool y
+       select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_SHOW
        select GENERIC_IOMAP
        select GENERIC_ATOMIC64
 source "crypto/Kconfig"
 source "lib/Kconfig"
+config NO_IOMEM
+       def_bool y

arch/score/Makefile+2−2

@@ -20,8 +20,8 @@ cflags-y += -G0 -pipe -mel -mnhwloop -D__SCOREEL__ \ · 19 unmodified lines
20	#	20	#
21	KBUILD_AFLAGS += $(cflags-y)	21	KBUILD_AFLAGS += $(cflags-y)
22	KBUILD_CFLAGS += $(cflags-y)	22	KBUILD_CFLAGS += $(cflags-y)
23	KBUILD_AFLAGS_MODULE += -mlong-calls	23	KBUILD_AFLAGS_MODULE +=
24	KBUILD_CFLAGS_MODULE += -mlong-calls	24	KBUILD_CFLAGS_MODULE +=
25	LDFLAGS += --oformat elf32-littlescore	25	LDFLAGS += --oformat elf32-littlescore
26	LDFLAGS_vmlinux += -G0 -static -nostdlib	26	LDFLAGS_vmlinux += -G0 -static -nostdlib
27		27

arch/score/include/asm/checksum.h+51−42

@@ -184,48 +184,57 @@ static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr, · 183 unmodified lines
184	__wsum sum)	184	__wsum sum)
185	{	185	{
186	__asm__ __volatile__(	186	__asm__ __volatile__(
187	".set\tnoreorder\t\t\t# csum_ipv6_magic\n\t"	187	".set\tvolatile\t\t\t# csum_ipv6_magic\n\t"
188	".set\tnoat\n\t"	188	"add\t%0, %0, %5\t\t\t# proto (long in network byte order)\n\t"
189	"addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t"	189	"cmp.c\t%5, %0\n\t"
190	"sltu\t$1, %0, %5\n\t"	190	"bleu 1f\n\t"
191	"addu\t%0, $1\n\t"	191	"addi\t%0, 0x1\n\t"
192	"addu\t%0, %6\t\t\t# csum\n\t"	192	"1:add\t%0, %0, %6\t\t\t# csum\n\t"
193	"sltu\t$1, %0, %6\n\t"	193	"cmp.c\t%6, %0\n\t"
194	"lw\t%1, 0(%2)\t\t\t# four words source address\n\t"	194	"lw\t%1, [%2, 0]\t\t\t# four words source address\n\t"
195	"addu\t%0, $1\n\t"	195	"bleu 1f\n\t"
196	"addu\t%0, %1\n\t"	196	"addi\t%0, 0x1\n\t"
197	"sltu\t$1, %0, %1\n\t"	197	"1:add\t%0, %0, %1\n\t"
198	"lw\t%1, 4(%2)\n\t"	198	"cmp.c\t%1, %0\n\t"
199	"addu\t%0, $1\n\t"	199	"1:lw\t%1, [%2, 4]\n\t"
200	"addu\t%0, %1\n\t"	200	"bleu 1f\n\t"
201	"sltu\t$1, %0, %1\n\t"	201	"addi\t%0, 0x1\n\t"
202	"lw\t%1, 8(%2)\n\t"	202	"1:add\t%0, %0, %1\n\t"
203	"addu\t%0, $1\n\t"	203	"cmp.c\t%1, %0\n\t"
204	"addu\t%0, %1\n\t"	204	"lw\t%1, [%2,8]\n\t"
205	"sltu\t$1, %0, %1\n\t"	205	"bleu 1f\n\t"
206	"lw\t%1, 12(%2)\n\t"	206	"addi\t%0, 0x1\n\t"
207	"addu\t%0, $1\n\t"	207	"1:add\t%0, %0, %1\n\t"
208	"addu\t%0, %1\n\t"	208	"cmp.c\t%1, %0\n\t"
209	"sltu\t$1, %0, %1\n\t"	209	"lw\t%1, [%2, 12]\n\t"
210	"lw\t%1, 0(%3)\n\t"	210	"bleu 1f\n\t"
211	"addu\t%0, $1\n\t"	211	"addi\t%0, 0x1\n\t"
212	"addu\t%0, %1\n\t"	212	"1:add\t%0, %0,%1\n\t"
213	"sltu\t$1, %0, %1\n\t"	213	"cmp.c\t%1, %0\n\t"
214	"lw\t%1, 4(%3)\n\t"	214	"lw\t%1, [%3, 0]\n\t"
215	"addu\t%0, $1\n\t"	215	"bleu 1f\n\t"
216	"addu\t%0, %1\n\t"	216	"addi\t%0, 0x1\n\t"
217	"sltu\t$1, %0, %1\n\t"	217	"1:add\t%0, %0, %1\n\t"
218	"lw\t%1, 8(%3)\n\t"	218	"cmp.c\t%1, %0\n\t"
219	"addu\t%0, $1\n\t"	219	"lw\t%1, [%3, 4]\n\t"
220	"addu\t%0, %1\n\t"	220	"bleu 1f\n\t"
221	"sltu\t$1, %0, %1\n\t"	221	"addi\t%0, 0x1\n\t"
222	"lw\t%1, 12(%3)\n\t"	222	"1:add\t%0, %0, %1\n\t"
223	"addu\t%0, $1\n\t"	223	"cmp.c\t%1, %0\n\t"
224	"addu\t%0, %1\n\t"	224	"lw\t%1, [%3, 8]\n\t"
225	"sltu\t$1, %0, %1\n\t"	225	"bleu 1f\n\t"
226	"addu\t%0, $1\t\t\t# Add final carry\n\t"	226	"addi\t%0, 0x1\n\t"
227	".set\tnoat\n\t"	227	"1:add\t%0, %0, %1\n\t"
228	".set\tnoreorder"	228	"cmp.c\t%1, %0\n\t"
		229	"lw\t%1, [%3, 12]\n\t"
		230	"bleu 1f\n\t"
		231	"addi\t%0, 0x1\n\t"
		232	"1:add\t%0, %0, %1\n\t"
		233	"cmp.c\t%1, %0\n\t"
		234	"bleu 1f\n\t"
		235	"addi\t%0, 0x1\n\t"
		236	"1:\n\t"
		237	".set\toptimize"
229	: "=r" (sum), "=r" (proto)	238	: "=r" (sum), "=r" (proto)
230	: "r" (saddr), "r" (daddr),	239	: "r" (saddr), "r" (daddr),
231	"0" (htonl(len)), "1" (htonl(proto)), "r" (sum));	240	"0" (htonl(len)), "1" (htonl(proto)), "r" (sum));

arch/score/include/asm/io.h+0−1

@@ -5,5 +5,4 @@ · 4 unmodified lines
5		5
6	#define virt_to_bus virt_to_phys	6	#define virt_to_bus virt_to_phys
7	#define bus_to_virt phys_to_virt	7	#define bus_to_virt phys_to_virt
8
9	#endif /* _ASM_SCORE_IO_H */	8	#endif /* _ASM_SCORE_IO_H */

arch/score/include/asm/pgalloc.h+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	#define _ASM_SCORE_PGALLOC_H	2	#define _ASM_SCORE_PGALLOC_H
3		3
4	#include <linux/mm.h>	4	#include <linux/mm.h>
5		5	#include <linux/highmem.h>
6	static inline void pmd_populate_kernel(struct mm_struct mm, pmd_t pmd,	6	static inline void pmd_populate_kernel(struct mm_struct mm, pmd_t pmd,
7	pte_t *pte)	7	pte_t *pte)
8	{	8	{

arch/score/kernel/entry.S+2−2

@@ -264,7 +264,7 @@ resume_kernel: · 263 unmodified lines
264	disable_irq	264	disable_irq
265	lw r8, [r28, TI_PRE_COUNT]	265	lw r8, [r28, TI_PRE_COUNT]
266	cmpz.c r8	266	cmpz.c r8
267	bne r8, restore_all	267	bne restore_all
268	need_resched:	268	need_resched:
269	lw r8, [r28, TI_FLAGS]	269	lw r8, [r28, TI_FLAGS]
270	andri.c r9, r8, _TIF_NEED_RESCHED	270	andri.c r9, r8, _TIF_NEED_RESCHED
@@ -415,7 +415,7 @@ ENTRY(handle_sys) · 144 unmodified lines
415	sw r9, [r0, PT_EPC]	415	sw r9, [r0, PT_EPC]
416		416
417	cmpi.c r27, __NR_syscalls # check syscall number	417	cmpi.c r27, __NR_syscalls # check syscall number
418	bgeu illegal_syscall	418	bcs illegal_syscall
419		419
420	slli r8, r27, 2 # get syscall routine	420	slli r8, r27, 2 # get syscall routine
421	la r11, sys_call_table	421	la r11, sys_call_table

arch/score/kernel/process.c+2−2

@@ -78,8 +78,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, · 77 unmodified lines
78	p->thread.reg0 = (unsigned long) childregs;	78	p->thread.reg0 = (unsigned long) childregs;
79	if (unlikely(p->flags & PF_KTHREAD)) {	79	if (unlikely(p->flags & PF_KTHREAD)) {
80	memset(childregs, 0, sizeof(struct pt_regs));	80	memset(childregs, 0, sizeof(struct pt_regs));
81	p->thread->reg12 = usp;	81	p->thread.reg12 = usp;
82	p->thread->reg13 = arg;	82	p->thread.reg13 = arg;
83	p->thread.reg3 = (unsigned long) ret_from_kernel_thread;	83	p->thread.reg3 = (unsigned long) ret_from_kernel_thread;
84	} else {	84	} else {
85	childregs = current_pt_regs();	85	childregs = current_pt_regs();

arch/sparc/Kconfig+6−1

 	  Only choose N if you know in advance that you will not need to modify
 	  OpenPROM settings on the running system.
-# Makefile helper
+# Makefile helpers
 config SPARC64_PCI
 	bool
 	default y
 	depends on SPARC64 && PCI
+config SPARC64_PCI_MSI
+	bool
+	default y
+	depends on SPARC64_PCI && PCI_MSI
 endmenu
 menu "Executable file formats"

arch/sparc/include/asm/floppy_64.h+1−1

@@ -254,7 +254,7 @@ static int sun_fd_request_irq(void) · 253 unmodified lines
254	once = 1;	254	once = 1;
255		255
256	error = request_irq(FLOPPY_IRQ, sparc_floppy_irq,	256	error = request_irq(FLOPPY_IRQ, sparc_floppy_irq,
257	IRQF_DISABLED, "floppy", NULL);	257	0, "floppy", NULL);
258		258
259	return ((error == 0) ? 0 : -1);	259	return ((error == 0) ? 0 : -1);
260	}	260	}

arch/sparc/kernel/Makefile+2−1

@@ -1,3 +1,4 @@
		1
1	#	2	#
2	# Makefile for the linux kernel.	3	# Makefile for the linux kernel.
3	#	4	#
@@ -99,7 +100,7 @@ obj-$(CONFIG_STACKTRACE) += stacktrace.o · 95 unmodified lines
99	obj-$(CONFIG_SPARC64_PCI) += pci.o pci_common.o psycho_common.o	100	obj-$(CONFIG_SPARC64_PCI) += pci.o pci_common.o psycho_common.o
100	obj-$(CONFIG_SPARC64_PCI) += pci_psycho.o pci_sabre.o pci_schizo.o	101	obj-$(CONFIG_SPARC64_PCI) += pci_psycho.o pci_sabre.o pci_schizo.o
101	obj-$(CONFIG_SPARC64_PCI) += pci_sun4v.o pci_sun4v_asm.o pci_fire.o	102	obj-$(CONFIG_SPARC64_PCI) += pci_sun4v.o pci_sun4v_asm.o pci_fire.o
102	obj-$(CONFIG_PCI_MSI) += pci_msi.o	103	obj-$(CONFIG_SPARC64_PCI_MSI) += pci_msi.o
103		104
104	obj-$(CONFIG_COMPAT) += sys32.o sys_sparc32.o signal32.o	105	obj-$(CONFIG_COMPAT) += sys32.o sys_sparc32.o signal32.o
105		106

arch/sparc/kernel/ds.c+2−3

@@ -849,9 +849,8 @@ void ldom_reboot(const char *boot_command) · 848 unmodified lines
849	if (boot_command && strlen(boot_command)) {	849	if (boot_command && strlen(boot_command)) {
850	unsigned long len;	850	unsigned long len;
851		851
852	strcpy(full_boot_str, "boot ");	852	snprintf(full_boot_str, sizeof(full_boot_str), "boot %s",
853	strlcpy(full_boot_str + strlen("boot "), boot_command,	853	boot_command);
854	sizeof(full_boot_str + strlen("boot ")));
855	len = strlen(full_boot_str);	854	len = strlen(full_boot_str);
856		855
857	if (reboot_data_supported) {	856	if (reboot_data_supported) {

arch/sparc/kernel/ldc.c+2−2

@@ -1249,12 +1249,12 @@ int ldc_bind(struct ldc_channel lp, const char name) · 1248 unmodified lines
1249	snprintf(lp->rx_irq_name, LDC_IRQ_NAME_MAX, "%s RX", name);	1249	snprintf(lp->rx_irq_name, LDC_IRQ_NAME_MAX, "%s RX", name);
1250	snprintf(lp->tx_irq_name, LDC_IRQ_NAME_MAX, "%s TX", name);	1250	snprintf(lp->tx_irq_name, LDC_IRQ_NAME_MAX, "%s TX", name);
1251		1251
1252	err = request_irq(lp->cfg.rx_irq, ldc_rx, IRQF_DISABLED,	1252	err = request_irq(lp->cfg.rx_irq, ldc_rx, 0,
1253	lp->rx_irq_name, lp);	1253	lp->rx_irq_name, lp);
1254	if (err)	1254	if (err)
1255	return err;	1255	return err;
1256		1256
1257	err = request_irq(lp->cfg.tx_irq, ldc_tx, IRQF_DISABLED,	1257	err = request_irq(lp->cfg.tx_irq, ldc_tx, 0,
1258	lp->tx_irq_name, lp);	1258	lp->tx_irq_name, lp);
1259	if (err) {	1259	if (err) {
1260	free_irq(lp->cfg.rx_irq, lp);	1260	free_irq(lp->cfg.rx_irq, lp);

arch/x86/Kconfig+3−2

 	bool "Intel Low Power Subsystem Support"
 	depends on ACPI
 	select COMMON_CLK
+	select PINCTRL
 	---help---
 	  Select to build support for Intel Low Power Subsystem such as
 	  found on Intel Lynxpoint PCH. Selecting this option enables
-	  things like clock tree (common clock framework) which are needed
+	  things like clock tree (common clock framework) and pincontrol
-	  by the LPSS peripheral drivers.
+	  which are needed by the LPSS peripheral drivers.
 config X86_RDC321X
 	bool "RDC R-321x SoC"

arch/x86/include/asm/xen/page.h+20−11

@@ -79,30 +79,38 @@ static inline int phys_to_machine_mapping_valid(unsigned long pfn) · 78 unmodified lines
79	return get_phys_to_machine(pfn) != INVALID_P2M_ENTRY;	79	return get_phys_to_machine(pfn) != INVALID_P2M_ENTRY;
80	}	80	}
81		81
82	static inline unsigned long mfn_to_pfn(unsigned long mfn)	82	static inline unsigned long mfn_to_pfn_no_overrides(unsigned long mfn)
83	{	83	{
84	unsigned long pfn;	84	unsigned long pfn;
85	int ret = 0;	85	int ret;
86		86
87	if (xen_feature(XENFEAT_auto_translated_physmap))	87	if (xen_feature(XENFEAT_auto_translated_physmap))
88	return mfn;	88	return mfn;
89		89
90	if (unlikely(mfn >= machine_to_phys_nr)) {	90	if (unlikely(mfn >= machine_to_phys_nr))
91	pfn = ~0;	91	return ~0;
92	goto try_override;	92
93	}
94	pfn = 0;
95	/*	93	/*
96	* The array access can fail (e.g., device space beyond end of RAM).	94	* The array access can fail (e.g., device space beyond end of RAM).
97	* In such cases it doesn't matter what we return (we return garbage),	95	* In such cases it doesn't matter what we return (we return garbage),
98	* but we must handle the fault without crashing!	96	* but we must handle the fault without crashing!
99	*/	97	*/
100	ret = __get_user(pfn, &machine_to_phys_mapping[mfn]);	98	ret = __get_user(pfn, &machine_to_phys_mapping[mfn]);
101	try_override:
102	/* ret might be < 0 if there are no entries in the m2p for mfn */
103	if (ret < 0)	99	if (ret < 0)
104	pfn = ~0;	100	return ~0;
105	else if (get_phys_to_machine(pfn) != mfn)	101
		102	return pfn;
		103	}
		104
		105	static inline unsigned long mfn_to_pfn(unsigned long mfn)
		106	{
		107	unsigned long pfn;
		108
		109	if (xen_feature(XENFEAT_auto_translated_physmap))
		110	return mfn;
		111
		112	pfn = mfn_to_pfn_no_overrides(mfn);
		113	if (get_phys_to_machine(pfn) != mfn) {
106	/*	114	/*
107	* If this appears to be a foreign mfn (because the pfn	115	* If this appears to be a foreign mfn (because the pfn
108	* doesn't map back to the mfn), then check the local override	116	* doesn't map back to the mfn), then check the local override
@@ -111,6 +119,7 @@ try_override: · 2 unmodified lines
111	* m2p_find_override_pfn returns ~0 if it doesn't find anything.	119	* m2p_find_override_pfn returns ~0 if it doesn't find anything.
112	*/	120	*/
113	pfn = m2p_find_override_pfn(mfn, ~0);	121	pfn = m2p_find_override_pfn(mfn, ~0);
		122	}
114		123
115	/*	124	/*
116	* pfn is ~0 if there are no entries in the m2p for mfn or if the	125	* pfn is ~0 if there are no entries in the m2p for mfn or if the

arch/x86/kernel/cpu/perf_event.c+6−6

@@ -1506,7 +1506,7 @@ static int __init init_hw_perf_events(void) · 1505 unmodified lines
1506	err = amd_pmu_init();	1506	err = amd_pmu_init();
1507	break;	1507	break;
1508	default:	1508	default:
1509	return 0;	1509	err = -ENOTSUPP;
1510	}	1510	}
1511	if (err != 0) {	1511	if (err != 0) {
1512	pr_cont("no PMU driver, software events only.\n");	1512	pr_cont("no PMU driver, software events only.\n");
@@ -1883,9 +1883,9 @@ static struct pmu pmu = { · 370 unmodified lines
1883		1883
1884	void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)	1884	void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1885	{	1885	{
1886	userpg->cap_usr_time = 0;	1886	userpg->cap_user_time = 0;
1887	userpg->cap_usr_time_zero = 0;	1887	userpg->cap_user_time_zero = 0;
1888	userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc;	1888	userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
1889	userpg->pmc_width = x86_pmu.cntval_bits;	1889	userpg->pmc_width = x86_pmu.cntval_bits;
1890		1890
1891	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))	1891	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
@@ -1894,13 +1894,13 @@ void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) · 2 unmodified lines
1894	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))	1894	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1895	return;	1895	return;
1896		1896
1897	userpg->cap_usr_time = 1;	1897	userpg->cap_user_time = 1;
1898	userpg->time_mult = this_cpu_read(cyc2ns);	1898	userpg->time_mult = this_cpu_read(cyc2ns);
1899	userpg->time_shift = CYC2NS_SCALE_FACTOR;	1899	userpg->time_shift = CYC2NS_SCALE_FACTOR;
1900	userpg->time_offset = this_cpu_read(cyc2ns_offset) - now;	1900	userpg->time_offset = this_cpu_read(cyc2ns_offset) - now;
1901		1901
1902	if (sched_clock_stable && !check_tsc_disabled()) {	1902	if (sched_clock_stable && !check_tsc_disabled()) {
1903	userpg->cap_usr_time_zero = 1;	1903	userpg->cap_user_time_zero = 1;
1904	userpg->time_zero = this_cpu_read(cyc2ns_offset);	1904	userpg->time_zero = this_cpu_read(cyc2ns_offset);
1905	}	1905	}
1906	}	1906	}

arch/x86/kernel/cpu/perf_event_intel.c+1−0

@@ -2325,6 +2325,7 @@ __init int intel_pmu_init(void) · 2324 unmodified lines
2325	break;	2325	break;
2326		2326
2327	case 55: /* Atom 22nm "Silvermont" */	2327	case 55: /* Atom 22nm "Silvermont" */
		2328	case 77: /* Avoton "Silvermont" */
2328	memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,	2329	memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
2329	sizeof(hw_cache_event_ids));	2330	sizeof(hw_cache_event_ids));
2330	memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,	2331	memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,

arch/x86/kernel/cpu/perf_event_intel_ds.c+1−0

@@ -584,6 +584,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = { · 583 unmodified lines
584	INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */	584	INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
585	INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */	585	INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
586	INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */	586	INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
		587	INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
587	INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */	588	INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
588	EVENT_CONSTRAINT_END	589	EVENT_CONSTRAINT_END
589	};	590	};

arch/x86/kernel/cpu/perf_event_intel_uncore.c+5−5

@@ -2706,14 +2706,14 @@ static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box) · 2705 unmodified lines
2706	box->hrtimer.function = uncore_pmu_hrtimer;	2706	box->hrtimer.function = uncore_pmu_hrtimer;
2707	}	2707	}
2708		2708
2709	struct intel_uncore_box uncore_alloc_box(struct intel_uncore_type type, int cpu)	2709	static struct intel_uncore_box uncore_alloc_box(struct intel_uncore_type type, int node)
2710	{	2710	{
2711	struct intel_uncore_box *box;	2711	struct intel_uncore_box *box;
2712	int i, size;	2712	int i, size;
2713		2713
2714	size = sizeof(box) + type->num_shared_regs sizeof(struct intel_uncore_extra_reg);	2714	size = sizeof(box) + type->num_shared_regs sizeof(struct intel_uncore_extra_reg);
2715		2715
2716	box = kzalloc_node(size, GFP_KERNEL, cpu_to_node(cpu));	2716	box = kzalloc_node(size, GFP_KERNEL, node);
2717	if (!box)	2717	if (!box)
2718	return NULL;	2718	return NULL;
2719		2719
@@ -3031,7 +3031,7 @@ static int uncore_validate_group(struct intel_uncore_pmu *pmu, · 311 unmodified lines
3031	struct intel_uncore_box *fake_box;	3031	struct intel_uncore_box *fake_box;
3032	int ret = -EINVAL, n;	3032	int ret = -EINVAL, n;
3033		3033
3034	fake_box = uncore_alloc_box(pmu->type, smp_processor_id());	3034	fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
3035	if (!fake_box)	3035	if (!fake_box)
3036	return -ENOMEM;	3036	return -ENOMEM;
3037		3037
@@ -3294,7 +3294,7 @@ static int uncore_pci_probe(struct pci_dev pdev, const struct pci_device_id id · 256 unmodified lines
3294	}	3294	}
3295		3295
3296	type = pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];	3296	type = pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
3297	box = uncore_alloc_box(type, 0);	3297	box = uncore_alloc_box(type, NUMA_NO_NODE);
3298	if (!box)	3298	if (!box)
3299	return -ENOMEM;	3299	return -ENOMEM;
3300		3300
@@ -3499,7 +3499,7 @@ static int uncore_cpu_prepare(int cpu, int phys_id) · 198 unmodified lines
3499	if (pmu->func_id < 0)	3499	if (pmu->func_id < 0)
3500	pmu->func_id = j;	3500	pmu->func_id = j;
3501		3501
3502	box = uncore_alloc_box(type, cpu);	3502	box = uncore_alloc_box(type, cpu_to_node(cpu));
3503	if (!box)	3503	if (!box)
3504	return -ENOMEM;	3504	return -ENOMEM;
3505		3505

arch/x86/kernel/entry_64.S+0−15

@@ -487,21 +487,6 @@ ENDPROC(native_usergs_sysret64) · 486 unmodified lines
487	TRACE_IRQS_OFF	487	TRACE_IRQS_OFF
488	.endm	488	.endm
489		489
490	ENTRY(save_rest)
491	PARTIAL_FRAME 1 (REST_SKIP+8)
492	movq 58+16(%rsp), %r11 / save return address */
493	movq_cfi rbx, RBX+16
494	movq_cfi rbp, RBP+16
495	movq_cfi r12, R12+16
496	movq_cfi r13, R13+16
497	movq_cfi r14, R14+16
498	movq_cfi r15, R15+16
499	movq %r11, 8(%rsp) /* return address */
500	FIXUP_TOP_OF_STACK %r11, 16
501	ret
502	CFI_ENDPROC
503	END(save_rest)
504
505	/* save complete stack frame */	490	/* save complete stack frame */
506	.pushsection .kprobes.text, "ax"	491	.pushsection .kprobes.text, "ax"
507	ENTRY(save_paranoid)	492	ENTRY(save_paranoid)

arch/x86/kernel/microcode_amd.c+1−0

@@ -216,6 +216,7 @@ int apply_microcode_amd(int cpu) · 215 unmodified lines
216	/* need to apply patch? */	216	/* need to apply patch? */
217	if (rev >= mc_amd->hdr.patch_id) {	217	if (rev >= mc_amd->hdr.patch_id) {
218	c->microcode = rev;	218	c->microcode = rev;
		219	uci->cpu_sig.rev = rev;
219	return 0;	220	return 0;
220	}	221	}
221		222

arch/x86/kernel/reboot.c+17−1

@@ -352,12 +352,28 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { · 351 unmodified lines
352	},	352	},
353	{ /* Handle problems with rebooting on the Precision M6600. */	353	{ /* Handle problems with rebooting on the Precision M6600. */
354	.callback = set_pci_reboot,	354	.callback = set_pci_reboot,
355	.ident = "Dell OptiPlex 990",	355	.ident = "Dell Precision M6600",
356	.matches = {	356	.matches = {
357	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),	357	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
358	DMI_MATCH(DMI_PRODUCT_NAME, "Precision M6600"),	358	DMI_MATCH(DMI_PRODUCT_NAME, "Precision M6600"),
359	},	359	},
360	},	360	},
		361	{ /* Handle problems with rebooting on the Dell PowerEdge C6100. */
		362	.callback = set_pci_reboot,
		363	.ident = "Dell PowerEdge C6100",
		364	.matches = {
		365	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
		366	DMI_MATCH(DMI_PRODUCT_NAME, "C6100"),
		367	},
		368	},
		369	{ /* Some C6100 machines were shipped with vendor being 'Dell'. */
		370	.callback = set_pci_reboot,
		371	.ident = "Dell PowerEdge C6100",
		372	.matches = {
		373	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
		374	DMI_MATCH(DMI_PRODUCT_NAME, "C6100"),
		375	},
		376	},
361	{ }	377	{ }
362	};	378	};
363		379

arch/x86/kernel/smpboot.c+2−1

 {
 	static int current_node = -1;
 	int node = early_cpu_to_node(cpu);
+	int max_cpu_present = find_last_bit(cpumask_bits(cpu_present_mask), NR_CPUS);
 	if (system_state == SYSTEM_BOOTING) {
 		if (node != current_node) {
 			current_node = node;
 			pr_info("Booting Node %3d, Processors ", node);
 		}
-		pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : "");
+		pr_cont(" #%4d%s", cpu, cpu == max_cpu_present ? " OK\n" : "");
 		return;
 	} else
 		pr_info("Booting Node %d Processor %d APIC 0x%x\n",

arch/x86/kernel/sysfb_simplefb.c+2−2

@@ -72,14 +72,14 @@ __init int create_simplefb(const struct screen_info *si, · 71 unmodified lines
72	* the part that is occupied by the framebuffer */	72	* the part that is occupied by the framebuffer */
73	len = mode->height * mode->stride;	73	len = mode->height * mode->stride;
74	len = PAGE_ALIGN(len);	74	len = PAGE_ALIGN(len);
75	if (len > si->lfb_size << 16) {	75	if (len > (u64)si->lfb_size << 16) {
76	printk(KERN_WARNING "sysfb: VRAM smaller than advertised\n");	76	printk(KERN_WARNING "sysfb: VRAM smaller than advertised\n");
77	return -EINVAL;	77	return -EINVAL;
78	}	78	}
79		79
80	/* setup IORESOURCE_MEM as framebuffer memory */	80	/* setup IORESOURCE_MEM as framebuffer memory */
81	memset(&res, 0, sizeof(res));	81	memset(&res, 0, sizeof(res));
82	res.flags = IORESOURCE_MEM;	82	res.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
83	res.name = simplefb_resname;	83	res.name = simplefb_resname;
84	res.start = si->lfb_base;	84	res.start = si->lfb_base;
85	res.end = si->lfb_base + len - 1;	85	res.end = si->lfb_base + len - 1;

arch/x86/kvm/vmx.c+3−1

 	 * There are errata that may cause this bit to not be set:
 	 * AAK134, BY25.
 	 */
-	if (exit_qualification & INTR_INFO_UNBLOCK_NMI)
+	if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
+			cpu_has_virtual_nmis() &&
+			(exit_qualification & INTR_INFO_UNBLOCK_NMI))
 		vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
 	gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);

arch/x86/pci/mmconfig-shared.c+6−1

 	if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
 		return -ENODEV;
-	if (start > end || !addr)
+	if (start > end)
 		return -EINVAL;
 	mutex_lock(&pci_mmcfg_lock);
 		return -EEXIST;
 	}
+	if (!addr) {
+		mutex_unlock(&pci_mmcfg_lock);
+		return -EINVAL;
+	}
 	rc = -EBUSY;
 	cfg = pci_mmconfig_alloc(seg, start, end, addr);
 	if (cfg == NULL) {

arch/x86/platform/efi/efi.c+7−4

 	for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
 		md = p;
-		if (!(md->attribute & EFI_MEMORY_RUNTIME) &&
+		if (!(md->attribute & EFI_MEMORY_RUNTIME)) {
-		    md->type != EFI_BOOT_SERVICES_CODE &&
+#ifdef CONFIG_X86_64
-		    md->type != EFI_BOOT_SERVICES_DATA)
+			if (md->type != EFI_BOOT_SERVICES_CODE &&
-			continue;
+			    md->type != EFI_BOOT_SERVICES_DATA)
+#endif
+				continue;
+		}
 		size = md->num_pages << EFI_PAGE_SHIFT;
 		end = md->phys_addr + size;

arch/x86/xen/p2m.c+4−6

 	unsigned long uninitialized_var(address);
 	unsigned level;
 	pte_t *ptep = NULL;
-	int ret = 0;
 	pfn = page_to_pfn(page);
 	if (!PageHighMem(page)) {
 	 * frontend pages while they are being shared with the backend,
 	 * because mfn_to_pfn (that ends up being called by GUPF) will
 	 * return the backend pfn rather than the frontend pfn. */
-	ret = __get_user(pfn, &machine_to_phys_mapping[mfn]);
+	pfn = mfn_to_pfn_no_overrides(mfn);
-	if (ret == 0 && get_phys_to_machine(pfn) == mfn)
+	if (get_phys_to_machine(pfn) == mfn)
 		set_phys_to_machine(pfn, FOREIGN_FRAME(mfn));
 	return 0;
 	unsigned long uninitialized_var(address);
 	unsigned level;
 	pte_t *ptep = NULL;
-	int ret = 0;
 	pfn = page_to_pfn(page);
 	mfn = get_phys_to_machine(pfn);
 	 * the original pfn causes mfn_to_pfn(mfn) to return the frontend
 	 * pfn again. */
 	mfn &= ~FOREIGN_FRAME_BIT;
-	ret = __get_user(pfn, &machine_to_phys_mapping[mfn]);
+	pfn = mfn_to_pfn_no_overrides(mfn);
-	if (ret == 0 && get_phys_to_machine(pfn) == FOREIGN_FRAME(mfn) &&
+	if (get_phys_to_machine(pfn) == FOREIGN_FRAME(mfn) &&
 			m2p_find_override(mfn) == NULL)
 		set_phys_to_machine(pfn, mfn);

arch/x86/xen/spinlock.c+24−2

@@ -259,6 +259,14 @@ void xen_uninit_lock_cpu(int cpu) · 258 unmodified lines
259	}	259	}
260		260
261		261
		262	/*
		263	* Our init of PV spinlocks is split in two init functions due to us
		264	* using paravirt patching and jump labels patching and having to do
		265	* all of this before SMP code is invoked.
		266	*
		267	* The paravirt patching needs to be done _before_ the alternative asm code
		268	* is started, otherwise we would not patch the core kernel code.
		269	*/
262	void __init xen_init_spinlocks(void)	270	void __init xen_init_spinlocks(void)
263	{	271	{
264		272
@@ -267,12 +275,26 @@ void __init xen_init_spinlocks(void) · 2 unmodified lines
267	return;	275	return;
268	}	276	}
269		277
270	static_key_slow_inc(&paravirt_ticketlocks_enabled);
271
272	pv_lock_ops.lock_spinning = PV_CALLEE_SAVE(xen_lock_spinning);	278	pv_lock_ops.lock_spinning = PV_CALLEE_SAVE(xen_lock_spinning);
273	pv_lock_ops.unlock_kick = xen_unlock_kick;	279	pv_lock_ops.unlock_kick = xen_unlock_kick;
274	}	280	}
275		281
		282	/*
		283	* While the jump_label init code needs to happend _after_ the jump labels are
		284	* enabled and before SMP is started. Hence we use pre-SMP initcall level
		285	* init. We cannot do it in xen_init_spinlocks as that is done before
		286	* jump labels are activated.
		287	*/
		288	static __init int xen_init_spinlocks_jump(void)
		289	{
		290	if (!xen_pvspin)
		291	return 0;
		292
		293	static_key_slow_inc(&paravirt_ticketlocks_enabled);
		294	return 0;
		295	}
		296	early_initcall(xen_init_spinlocks_jump);
		297
276	static __init int xen_parse_nopvspin(char *arg)	298	static __init int xen_parse_nopvspin(char *arg)
277	{	299	{
278	xen_pvspin = false;	300	xen_pvspin = false;

block/Kconfig+7−2

 	See Documentation/cgroups/blkio-controller.txt for more information.
-config CMDLINE_PARSER
+config BLK_CMDLINE_PARSER
 	bool "Block device command line partition parser"
 	default n
 	---help---
-	Parsing command line, get the partitions information.
+	Enabling this option allows you to specify the partition layout from
+	the kernel boot args.  This is typically of use for embedded devices
+	which don't otherwise have any standardized method for listing the
+	partitions on a block device.
+	See Documentation/block/cmdline-partition.txt for more information.
 menu "Partition Types"

block/Makefile+1−1

@@ -18,4 +18,4 @@ obj-$(CONFIG_IOSCHED_CFQ) += cfq-iosched.o · 17 unmodified lines
18		18
19	obj-$(CONFIG_BLOCK_COMPAT) += compat_ioctl.o	19	obj-$(CONFIG_BLOCK_COMPAT) += compat_ioctl.o
20	obj-$(CONFIG_BLK_DEV_INTEGRITY) += blk-integrity.o	20	obj-$(CONFIG_BLK_DEV_INTEGRITY) += blk-integrity.o
21	obj-$(CONFIG_CMDLINE_PARSER) += cmdline-parser.o	21	obj-$(CONFIG_BLK_CMDLINE_PARSER) += cmdline-parser.o

block/blk-cgroup.c+15−10

 	blkg->online = true;
 	spin_unlock(&blkcg->lock);
-	if (!ret)
+	if (!ret) {
+		if (blkcg == &blkcg_root) {
+			q->root_blkg = blkg;
+			q->root_rl.blkg = blkg;
+		}
 		return blkg;
+	}
 	/* @blkg failed fully initialized, use the usual release path */
 	blkg_put(blkg);
 	if (rcu_dereference_raw(blkcg->blkg_hint) == blkg)
 		rcu_assign_pointer(blkcg->blkg_hint, NULL);
+	/*
+	 * If root blkg is destroyed.  Just clear the pointer since root_rl
+	 * does not take reference on root blkg.
+	 */
+	if (blkcg == &blkcg_root) {
+		blkg->q->root_blkg = NULL;
+		blkg->q->root_rl.blkg = NULL;
+	}
 	/*
 	 * Put the reference taken at the time of creation so that when all
 	 * queues are gone, group can be destroyed.
 		blkg_destroy(blkg);
 		spin_unlock(&blkcg->lock);
 	}
-	/*
-	 * root blkg is destroyed.  Just clear the pointer since
-	 * root_rl does not take reference on root blkg.
-	 */
-	q->root_blkg = NULL;
-	q->root_rl.blkg = NULL;
 }
 /*
 		ret = PTR_ERR(blkg);
 		goto out_unlock;
 	}
-	q->root_blkg = blkg;
-	q->root_rl.blkg = blkg;
 	list_for_each_entry(blkg, &q->blkg_list, q_node)
 		cnt++;

block/blk-core.c+2−4

 	if (plug) {
 		/*
 		 * If this is the first request added after a plug, fire
-		 * of a plug trace. If others have been added before, check
+		 * of a plug trace.
-		 * if we have multiple devices in this plug. If so, make a
-		 * note to sort the list before dispatch.
 		 */
-		if (list_empty(&plug->list))
+		if (!request_count)
 			trace_block_plug(q);
 		else {
 			if (request_count >= BLK_MAX_REQUEST_COUNT) {

block/blk-exec.c+2−2

 	spin_lock_irq(q->queue_lock);
 	if (unlikely(blk_queue_dying(q))) {
+		rq->cmd_flags |= REQ_QUIET;
 		rq->errors = -ENXIO;
-		if (rq->end_io)
+		__blk_end_request_all(rq, rq->errors);
-			rq->end_io(rq, rq->errors);
 		spin_unlock_irq(q->queue_lock);
 		return;
 	}

block/cfq-iosched.c+2−2

@@ -1803,7 +1803,7 @@ static u64 cfqg_prfill_avg_queue_size(struct seq_file *sf, · 1802 unmodified lines
1803		1803
1804	if (samples) {	1804	if (samples) {
1805	v = blkg_stat_read(&cfqg->stats.avg_queue_size_sum);	1805	v = blkg_stat_read(&cfqg->stats.avg_queue_size_sum);
1806	do_div(v, samples);	1806	v = div64_u64(v, samples);
1807	}	1807	}
1808	__blkg_prfill_u64(sf, pd, v);	1808	__blkg_prfill_u64(sf, pd, v);
1809	return 0;	1809	return 0;
@@ -4358,7 +4358,7 @@ static int cfq_init_queue(struct request_queue q, struct elevator_type e) · 2548 unmodified lines
4358	if (!eq)	4358	if (!eq)
4359	return -ENOMEM;	4359	return -ENOMEM;
4360		4360
4361	cfqd = kmalloc_node(sizeof(*cfqd), GFP_KERNEL \| __GFP_ZERO, q->node);	4361	cfqd = kzalloc_node(sizeof(*cfqd), GFP_KERNEL, q->node);
4362	if (!cfqd) {	4362	if (!cfqd) {
4363	kobject_put(&eq->kobj);	4363	kobject_put(&eq->kobj);
4364	return -ENOMEM;	4364	return -ENOMEM;

block/deadline-iosched.c+1−1

@@ -346,7 +346,7 @@ static int deadline_init_queue(struct request_queue q, struct elevator_type e) · 345 unmodified lines
346	if (!eq)	346	if (!eq)
347	return -ENOMEM;	347	return -ENOMEM;
348		348
349	dd = kmalloc_node(sizeof(*dd), GFP_KERNEL \| __GFP_ZERO, q->node);	349	dd = kzalloc_node(sizeof(*dd), GFP_KERNEL, q->node);
350	if (!dd) {	350	if (!dd) {
351	kobject_put(&eq->kobj);	351	kobject_put(&eq->kobj);
352	return -ENOMEM;	352	return -ENOMEM;

block/elevator.c+1−1

@@ -155,7 +155,7 @@ struct elevator_queue elevator_alloc(struct request_queue q, · 154 unmodified lines
155	{	155	{
156	struct elevator_queue *eq;	156	struct elevator_queue *eq;
157		157
158	eq = kmalloc_node(sizeof(*eq), GFP_KERNEL \| __GFP_ZERO, q->node);	158	eq = kzalloc_node(sizeof(*eq), GFP_KERNEL, q->node);
159	if (unlikely(!eq))	159	if (unlikely(!eq))
160	goto err;	160	goto err;
161		161

block/genhd.c+1−2

@@ -1252,8 +1252,7 @@ struct gendisk *alloc_disk_node(int minors, int node_id) · 1251 unmodified lines
1252	{	1252	{
1253	struct gendisk *disk;	1253	struct gendisk *disk;
1254		1254
1255	disk = kmalloc_node(sizeof(struct gendisk),	1255	disk = kzalloc_node(sizeof(struct gendisk), GFP_KERNEL, node_id);
1256	GFP_KERNEL \| __GFP_ZERO, node_id);
1257	if (disk) {	1256	if (disk) {
1258	if (!init_part_stats(&disk->part0)) {	1257	if (!init_part_stats(&disk->part0)) {
1259	kfree(disk);	1258	kfree(disk);

block/partitions/Kconfig+2−2

@@ -263,7 +263,7 @@ config SYSV68_PARTITION · 262 unmodified lines
263		263
264	config CMDLINE_PARTITION	264	config CMDLINE_PARTITION
265	bool "Command line partition support" if PARTITION_ADVANCED	265	bool "Command line partition support" if PARTITION_ADVANCED
266	select CMDLINE_PARSER	266	select BLK_CMDLINE_PARSER
267	help	267	help
268	Say Y here if you would read the partitions table from bootargs.	268	Say Y here if you want to read the partition table from bootargs.
269	The format for the command line is just like mtdparts.	269	The format for the command line is just like mtdparts.

block/partitions/cmdline.c+4−4

@@ -2,15 +2,15 @@ · 1 unmodified line
2	* Copyright (C) 2013 HUAWEI	2	* Copyright (C) 2013 HUAWEI
3	* Author: Cai Zhiyong <caizhiyong@huawei.com>	3	* Author: Cai Zhiyong <caizhiyong@huawei.com>
4	*	4	*
5	* Read block device partition table from command line.	5	* Read block device partition table from the command line.
6	* The partition used for fixed block device (eMMC) embedded device.	6	* Typically used for fixed block (eMMC) embedded devices.
7	* It is no MBR, save storage space. Bootloader can be easily accessed	7	* It has no MBR, so saves storage space. Bootloader can be easily accessed
8	* by absolute address of data on the block device.	8	* by absolute address of data on the block device.
9	* Users can easily change the partition.	9	* Users can easily change the partition.
10	*	10	*
11	* The format for the command line is just like mtdparts.	11	* The format for the command line is just like mtdparts.
12	*	12	*
13	* Verbose config please reference "Documentation/block/cmdline-partition.txt"	13	* For further information, see "Documentation/block/cmdline-partition.txt"
14	*	14	*
15	*/	15	*/
16		16

drivers/acpi/acpi_ipmi.c+14−10

 #include <linux/ipmi.h>
 #include <linux/device.h>
 #include <linux/pnp.h>
+#include <linux/spinlock.h>
 MODULE_AUTHOR("Zhao Yakui");
 MODULE_DESCRIPTION("ACPI IPMI Opregion driver");
 	struct list_head head;
 	/* the IPMI request message list */
 	struct list_head tx_msg_list;
-	struct mutex	tx_msg_lock;
+	spinlock_t	tx_msg_lock;
 	acpi_handle handle;
 	struct pnp_dev *pnp_dev;
 	ipmi_user_t	user_interface;
 	struct kernel_ipmi_msg *msg;
 	struct acpi_ipmi_buffer *buffer;
 	struct acpi_ipmi_device *device;
+	unsigned long flags;
 	msg = &tx_msg->tx_message;
 	/*
 	/* Get the msgid */
 	device = tx_msg->device;
-	mutex_lock(&device->tx_msg_lock);
+	spin_lock_irqsave(&device->tx_msg_lock, flags);
 	device->curr_msgid++;
 	tx_msg->tx_msgid = device->curr_msgid;
-	mutex_unlock(&device->tx_msg_lock);
+	spin_unlock_irqrestore(&device->tx_msg_lock, flags);
 }
 static void acpi_format_ipmi_response(struct acpi_ipmi_msg *msg,
 	int msg_found = 0;
 	struct acpi_ipmi_msg *tx_msg;
 	struct pnp_dev *pnp_dev = ipmi_device->pnp_dev;
+	unsigned long flags;
 	if (msg->user != ipmi_device->user_interface) {
 		dev_warn(&pnp_dev->dev, "Unexpected response is returned. "
 		ipmi_free_recv_msg(msg);
 		return;
 	}
-	mutex_lock(&ipmi_device->tx_msg_lock);
+	spin_lock_irqsave(&ipmi_device->tx_msg_lock, flags);
 	list_for_each_entry(tx_msg, &ipmi_device->tx_msg_list, head) {
 		if (msg->msgid == tx_msg->tx_msgid) {
 			msg_found = 1;
 		}
 	}
-	mutex_unlock(&ipmi_device->tx_msg_lock);
+	spin_unlock_irqrestore(&ipmi_device->tx_msg_lock, flags);
 	if (!msg_found) {
 		dev_warn(&pnp_dev->dev, "Unexpected response (msg id %ld) is "
 			"returned.\n", msg->msgid);
 	struct acpi_ipmi_device *ipmi_device = handler_context;
 	int err, rem_time;
 	acpi_status status;
+	unsigned long flags;
 	/*
 	 * IPMI opregion message.
 	 * IPMI message is firstly written to the BMC and system software
 		return AE_NO_MEMORY;
 	acpi_format_ipmi_msg(tx_msg, address, value);
-	mutex_lock(&ipmi_device->tx_msg_lock);
+	spin_lock_irqsave(&ipmi_device->tx_msg_lock, flags);
 	list_add_tail(&tx_msg->head, &ipmi_device->tx_msg_list);
-	mutex_unlock(&ipmi_device->tx_msg_lock);
+	spin_unlock_irqrestore(&ipmi_device->tx_msg_lock, flags);
 	err = ipmi_request_settime(ipmi_device->user_interface,
 					&tx_msg->addr,
 					tx_msg->tx_msgid,
 	status = AE_OK;
 end_label:
-	mutex_lock(&ipmi_device->tx_msg_lock);
+	spin_lock_irqsave(&ipmi_device->tx_msg_lock, flags);
 	list_del(&tx_msg->head);
-	mutex_unlock(&ipmi_device->tx_msg_lock);
+	spin_unlock_irqrestore(&ipmi_device->tx_msg_lock, flags);
 	kfree(tx_msg);
 	return status;
 }
 	INIT_LIST_HEAD(&ipmi_device->head);
-	mutex_init(&ipmi_device->tx_msg_lock);
+	spin_lock_init(&ipmi_device->tx_msg_lock);
 	INIT_LIST_HEAD(&ipmi_device->tx_msg_list);
 	ipmi_install_space_handler(ipmi_device);

drivers/acpi/scan.c+2−2

@@ -968,7 +968,7 @@ int acpi_bus_get_device(acpi_handle handle, struct acpi_device **device) · 967 unmodified lines
968	}	968	}
969	return 0;	969	return 0;
970	}	970	}
971	EXPORT_SYMBOL_GPL(acpi_bus_get_device);	971	EXPORT_SYMBOL(acpi_bus_get_device);
972		972
973	int acpi_device_add(struct acpi_device *device,	973	int acpi_device_add(struct acpi_device *device,
974	void (release)(struct device ))	974	void (release)(struct device ))
@@ -1121,7 +1121,7 @@ int acpi_bus_register_driver(struct acpi_driver *driver) · 146 unmodified lines
1121	EXPORT_SYMBOL(acpi_bus_register_driver);	1121	EXPORT_SYMBOL(acpi_bus_register_driver);
1122		1122
1123	/**	1123	/**
1124	* acpi_bus_unregister_driver - unregisters a driver with the APIC bus	1124	* acpi_bus_unregister_driver - unregisters a driver with the ACPI bus
1125	* @driver: driver to unregister	1125	* @driver: driver to unregister
1126	*	1126	*
1127	* Unregisters a driver with the ACPI bus. Searches the namespace for all	1127	* Unregisters a driver with the ACPI bus. Searches the namespace for all

drivers/ata/sata_promise.c+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	* sata_promise.c - Promise SATA	2	* sata_promise.c - Promise SATA
3	*	3	*
4	* Maintained by: Tejun Heo <tj@kernel.org>	4	* Maintained by: Tejun Heo <tj@kernel.org>
5	* Mikael Pettersson <mikpe@it.uu.se>	5	* Mikael Pettersson
6	* Please ALWAYS copy linux-ide@vger.kernel.org	6	* Please ALWAYS copy linux-ide@vger.kernel.org
7	* on emails.	7	* on emails.
8	*	8	*

drivers/atm/he.c+1−12

@@ -2865,15 +2865,4 @@ static struct pci_driver he_driver = { · 2864 unmodified lines
2865	.id_table = he_pci_tbl,	2865	.id_table = he_pci_tbl,
2866	};	2866	};
2867		2867
2868	static int __init he_init(void)	2868	module_pci_driver(he_driver);
2869	{
2870	return pci_register_driver(&he_driver);
2871	}
2872
2873	static void __exit he_cleanup(void)
2874	{
2875	pci_unregister_driver(&he_driver);
2876	}
2877
2878	module_init(he_init);
2879	module_exit(he_cleanup);

drivers/atm/nicstar.c+1−1

@@ -778,7 +778,7 @@ static int ns_init_card(int i, struct pci_dev *pcidev) · 777 unmodified lines
778	return error;	778	return error;
779	}	779	}
780		780
781	if (mac[i] == NULL \|\| mac_pton(mac[i], card->atmdev->esi)) {	781	if (mac[i] == NULL \|\| !mac_pton(mac[i], card->atmdev->esi)) {
782	nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,	782	nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
783	card->atmdev->esi, 6);	783	card->atmdev->esi, 6);
784	if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) ==	784	if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) ==

drivers/base/core.c+7−7

@@ -2017,7 +2017,7 @@ EXPORT_SYMBOL_GPL(device_move); · 2016 unmodified lines
2017	*/	2017	*/
2018	void device_shutdown(void)	2018	void device_shutdown(void)
2019	{	2019	{
2020	struct device *dev;	2020	struct device dev, parent;
2021		2021
2022	spin_lock(&devices_kset->list_lock);	2022	spin_lock(&devices_kset->list_lock);
2023	/*	2023	/*
@@ -2034,7 +2034,7 @@ void device_shutdown(void) · 10 unmodified lines
2034	* prevent it from being freed because parent's	2034	* prevent it from being freed because parent's
2035	* lock is to be held	2035	* lock is to be held
2036	*/	2036	*/
2037	get_device(dev->parent);	2037	parent = get_device(dev->parent);
2038	get_device(dev);	2038	get_device(dev);
2039	/*	2039	/*
2040	* Make sure the device is off the kset list, in the	2040	* Make sure the device is off the kset list, in the
@@ -2044,8 +2044,8 @@ void device_shutdown(void) · 3 unmodified lines
2044	spin_unlock(&devices_kset->list_lock);	2044	spin_unlock(&devices_kset->list_lock);
2045		2045
2046	/* hold lock to avoid race with probe/release */	2046	/* hold lock to avoid race with probe/release */
2047	if (dev->parent)	2047	if (parent)
2048	device_lock(dev->parent);	2048	device_lock(parent);
2049	device_lock(dev);	2049	device_lock(dev);
2050		2050
2051	/* Don't allow any more runtime suspends */	2051	/* Don't allow any more runtime suspends */
@@ -2063,11 +2063,11 @@ void device_shutdown(void) · 11 unmodified lines
2063	}	2063	}
2064		2064
2065	device_unlock(dev);	2065	device_unlock(dev);
2066	if (dev->parent)	2066	if (parent)
2067	device_unlock(dev->parent);	2067	device_unlock(parent);
2068		2068
2069	put_device(dev);	2069	put_device(dev);
2070	put_device(dev->parent);	2070	put_device(parent);
2071		2071
2072	spin_lock(&devices_kset->list_lock);	2072	spin_lock(&devices_kset->list_lock);
2073	}	2073	}

drivers/bcma/driver_pci.c+26−23

 	}
 }
-static void bcma_core_pci_power_save(struct bcma_drv_pci *pc, bool up)
-{
-	u16 data;
-	if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
-		data = up ? 0x74 : 0x7C;
-		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
-					 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
-		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
-					 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
-	} else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
-		data = up ? 0x75 : 0x7D;
-		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
-					 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
-		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
-					 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
-	}
-}
 /**************************************************
  * Init.
  **************************************************/
 		bcma_core_pci_clientmode_init(pc);
 }
+void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
+{
+	struct bcma_drv_pci *pc;
+	u16 data;
+	if (bus->hosttype != BCMA_HOSTTYPE_PCI)
+		return;
+	pc = &bus->drv_pci[0];
+	if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
+		data = up ? 0x74 : 0x7C;
+		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
+					 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
+		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
+					 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
+	} else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
+		data = up ? 0x75 : 0x7D;
+		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
+					 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
+		bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
+					 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
+	}
+}
+EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
 			  bool enable)
 {
 	pc = &bus->drv_pci[0];
-	bcma_core_pci_power_save(pc, true);
 	bcma_core_pci_extend_L1timer(pc, true);
 }
 EXPORT_SYMBOL_GPL(bcma_core_pci_up);
 	pc = &bus->drv_pci[0];
 	bcma_core_pci_extend_L1timer(pc, false);
-	bcma_core_pci_power_save(pc, false);
 }
 EXPORT_SYMBOL_GPL(bcma_core_pci_down);

drivers/bcma/scan.c+7−5

 	return NULL;
 }
+#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
 			      struct bcma_device_id *match, int core_num,
 			      struct bcma_device *core)
 	 * the main register space for the core
 	 */
 	tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
-	if (tmp == 0 || IS_ERR_VALUE(tmp)) {
+	if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
 		/* Try again to see if it is a bridge */
 		tmp = bcma_erom_get_addr_desc(bus, eromptr,
 					      SCAN_ADDR_TYPE_BRIDGE, 0);
-		if (tmp == 0 || IS_ERR_VALUE(tmp)) {
+		if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
 			return -EILSEQ;
 		} else {
 			bcma_info(bus, "Bridge found\n");
 		for (j = 0; ; j++) {
 			tmp = bcma_erom_get_addr_desc(bus, eromptr,
 				SCAN_ADDR_TYPE_SLAVE, i);
-			if (IS_ERR_VALUE(tmp)) {
+			if (IS_ERR_VALUE_U32(tmp)) {
 				/* no more entries for port _i_ */
 				/* pr_debug("erom: slave port %d "
 				 * "has %d descriptors\n", i, j); */
 		for (j = 0; ; j++) {
 			tmp = bcma_erom_get_addr_desc(bus, eromptr,
 				SCAN_ADDR_TYPE_MWRAP, i);
-			if (IS_ERR_VALUE(tmp)) {
+			if (IS_ERR_VALUE_U32(tmp)) {
 				/* no more entries for port _i_ */
 				/* pr_debug("erom: master wrapper %d "
 				 * "has %d descriptors\n", i, j); */
 		for (j = 0; ; j++) {
 			tmp = bcma_erom_get_addr_desc(bus, eromptr,
 				SCAN_ADDR_TYPE_SWRAP, i + hack);
-			if (IS_ERR_VALUE(tmp)) {
+			if (IS_ERR_VALUE_U32(tmp)) {
 				/* no more entries for port _i_ */
 				/* pr_debug("erom: master wrapper %d "
 				 * has %d descriptors\n", i, j); */

drivers/block/cciss.c+1−0

@@ -1189,6 +1189,7 @@ static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode, · 1188 unmodified lines
1189	int err;	1189	int err;
1190	u32 cp;	1190	u32 cp;
1191		1191
		1192	memset(&arg64, 0, sizeof(arg64));
1192	err = 0;	1193	err = 0;
1193	err \|=	1194	err \|=
1194	copy_from_user(&arg64.LUN_info, &arg32->LUN_info,	1195	copy_from_user(&arg64.LUN_info, &arg32->LUN_info,

drivers/block/cpqarray.c+1−0

@@ -1193,6 +1193,7 @@ out_passthru: · 1192 unmodified lines
1193	ida_pci_info_struct pciinfo;	1193	ida_pci_info_struct pciinfo;
1194		1194
1195	if (!arg) return -EINVAL;	1195	if (!arg) return -EINVAL;
		1196	memset(&pciinfo, 0, sizeof(pciinfo));
1196	pciinfo.bus = host->pci_dev->bus->number;	1197	pciinfo.bus = host->pci_dev->bus->number;
1197	pciinfo.dev_fn = host->pci_dev->devfn;	1198	pciinfo.dev_fn = host->pci_dev->devfn;
1198	pciinfo.board_id = host->board_id;	1199	pciinfo.board_id = host->board_id;

drivers/block/rbd.c+59−18

 					u64 snap_id)
 {
 	u32 which;
+	const char *snap_name;
 	which = rbd_dev_snap_index(rbd_dev, snap_id);
 	if (which == BAD_SNAP_INDEX)
-		return NULL;
+		return ERR_PTR(-ENOENT);
-	return _rbd_dev_v1_snap_name(rbd_dev, which);
+	snap_name = _rbd_dev_v1_snap_name(rbd_dev, which);
+	return snap_name ? snap_name : ERR_PTR(-ENOMEM);
 }
 static const char *rbd_snap_name(struct rbd_device *rbd_dev, u64 snap_id)
 	obj_request_done_set(obj_request);
 }
-static int rbd_obj_notify_ack(struct rbd_device *rbd_dev, u64 notify_id)
+static int rbd_obj_notify_ack_sync(struct rbd_device *rbd_dev, u64 notify_id)
 {
 	struct rbd_obj_request *obj_request;
 	struct ceph_osd_client *osdc = &rbd_dev->rbd_client->client->osdc;
 	obj_request->osd_req = rbd_osd_req_create(rbd_dev, false, obj_request);
 	if (!obj_request->osd_req)
 		goto out;
-	obj_request->callback = rbd_obj_request_put;
 	osd_req_op_watch_init(obj_request->osd_req, 0, CEPH_OSD_OP_NOTIFY_ACK,
 					notify_id, 0, 0);
 	rbd_osd_req_format_read(obj_request);
 	ret = rbd_obj_request_submit(osdc, obj_request);
-out:
 	if (ret)
-		rbd_obj_request_put(obj_request);
+		goto out;
+	ret = rbd_obj_request_wait(obj_request);
+out:
+	rbd_obj_request_put(obj_request);
 	return ret;
 }
 	if (ret)
 		rbd_warn(rbd_dev, "header refresh error (%d)\n", ret);
-	rbd_obj_notify_ack(rbd_dev, notify_id);
+	rbd_obj_notify_ack_sync(rbd_dev, notify_id);
 }
 /*
 		clear_bit(RBD_DEV_FLAG_EXISTS, &rbd_dev->flags);
 }
+static void rbd_dev_update_size(struct rbd_device *rbd_dev)
+{
+	sector_t size;
+	bool removing;
+	/*
+	 * Don't hold the lock while doing disk operations,
+	 * or lock ordering will conflict with the bdev mutex via:
+	 * rbd_add() -> blkdev_get() -> rbd_open()
+	 */
+	spin_lock_irq(&rbd_dev->lock);
+	removing = test_bit(RBD_DEV_FLAG_REMOVING, &rbd_dev->flags);
+	spin_unlock_irq(&rbd_dev->lock);
+	/*
+	 * If the device is being removed, rbd_dev->disk has
+	 * been destroyed, so don't try to update its size
+	 */
+	if (!removing) {
+		size = (sector_t)rbd_dev->mapping.size / SECTOR_SIZE;
+		dout("setting size to %llu sectors", (unsigned long long)size);
+		set_capacity(rbd_dev->disk, size);
+		revalidate_disk(rbd_dev->disk);
+	}
+}
 static int rbd_dev_refresh(struct rbd_device *rbd_dev)
 {
 	u64 mapping_size;
 	up_write(&rbd_dev->header_rwsem);
 	if (mapping_size != rbd_dev->mapping.size) {
-		sector_t size;
+		rbd_dev_update_size(rbd_dev);
-		size = (sector_t)rbd_dev->mapping.size / SECTOR_SIZE;
-		dout("setting size to %llu sectors", (unsigned long long)size);
-		set_capacity(rbd_dev->disk, size);
-		revalidate_disk(rbd_dev->disk);
 	}
 	return ret;
 		snap_id = snapc->snaps[which];
 		snap_name = rbd_dev_v2_snap_name(rbd_dev, snap_id);
-		if (IS_ERR(snap_name))
+		if (IS_ERR(snap_name)) {
-			break;
+			/* ignore no-longer existing snapshots */
+			if (PTR_ERR(snap_name) == -ENOENT)
+				continue;
+			else
+				break;
+		}
 		found = !strcmp(name, snap_name);
 		kfree(snap_name);
 	}
 	/* Look up the snapshot name, and make a copy */
 	snap_name = rbd_snap_name(rbd_dev, spec->snap_id);
-	if (!snap_name) {
+	if (IS_ERR(snap_name)) {
-		ret = -ENOMEM;
+		ret = PTR_ERR(snap_name);
 		goto out_err;
 	}
 	if (ret < 0 || already)
 		return ret;
-	rbd_bus_del_dev(rbd_dev);
 	ret = rbd_dev_header_watch_sync(rbd_dev, false);
 	if (ret)
 		rbd_warn(rbd_dev, "failed to cancel watch event (%d)\n", ret);
+	/*
+	 * flush remaining watch callbacks - these must be complete
+	 * before the osd_client is shutdown
+	 */
+	dout("%s: flushing notifies", __func__);
+	ceph_osdc_flush_notifies(&rbd_dev->rbd_client->client->osdc);
+	/*
+	 * Don't free anything from rbd_dev->disk until after all
+	 * notifies are completely processed. Otherwise
+	 * rbd_bus_del_dev() will race with rbd_watch_cb(), resulting
+	 * in a potential use after free of rbd_dev->disk or rbd_dev.
+	 */
+	rbd_bus_del_dev(rbd_dev);
 	rbd_dev_image_release(rbd_dev);
 	module_put(THIS_MODULE);

drivers/bluetooth/ath3k.c+2−0

 	{ USB_DEVICE(0x04CA, 0x3008) },
 	{ USB_DEVICE(0x13d3, 0x3362) },
 	{ USB_DEVICE(0x0CF3, 0xE004) },
+	{ USB_DEVICE(0x0CF3, 0xE005) },
 	{ USB_DEVICE(0x0930, 0x0219) },
 	{ USB_DEVICE(0x0489, 0xe057) },
 	{ USB_DEVICE(0x13d3, 0x3393) },
 	{ USB_DEVICE(0x04ca, 0x3008), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x13d3, 0x3362), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x0cf3, 0xe004), .driver_info = BTUSB_ATH3012 },
+	{ USB_DEVICE(0x0cf3, 0xe005), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x0930, 0x0219), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x0489, 0xe057), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x13d3, 0x3393), .driver_info = BTUSB_ATH3012 },

drivers/bluetooth/btusb.c+5−0

 	/* Broadcom BCM20702A0 */
 	{ USB_DEVICE(0x0b05, 0x17b5) },
+	{ USB_DEVICE(0x0b05, 0x17cb) },
 	{ USB_DEVICE(0x04ca, 0x2003) },
 	{ USB_DEVICE(0x0489, 0xe042) },
 	{ USB_DEVICE(0x413c, 0x8197) },
 	/*Broadcom devices with vendor specific id */
 	{ USB_VENDOR_AND_INTERFACE_INFO(0x0a5c, 0xff, 0x01, 0x01) },
+	/* Belkin F8065bf - Broadcom based */
+	{ USB_VENDOR_AND_INTERFACE_INFO(0x050d, 0xff, 0x01, 0x01) },
 	{ }	/* Terminating entry */
 };
 	{ USB_DEVICE(0x04ca, 0x3008), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x13d3, 0x3362), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x0cf3, 0xe004), .driver_info = BTUSB_ATH3012 },
+	{ USB_DEVICE(0x0cf3, 0xe005), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x0930, 0x0219), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x0489, 0xe057), .driver_info = BTUSB_ATH3012 },
 	{ USB_DEVICE(0x13d3, 0x3393), .driver_info = BTUSB_ATH3012 },

drivers/bus/mvebu-mbus.c+9−3

 					 phys_addr_t sdramwins_phys_base,
 					 size_t sdramwins_size)
 {
+	struct device_node *np;
 	int win;
 	mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
 		return -ENOMEM;
 	}
-	if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
+	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
+	if (np) {
 		mbus->hw_io_coherency = 1;
+		of_node_put(np);
+	}
 	for (win = 0; win < mbus->soc->num_wins; win++)
 		mvebu_mbus_disable_window(mbus, win);
 	int ret;
 	/*
-	 * These are optional, so we clear them and they'll
+	 * These are optional, so we make sure that resource_size(x) will
-	 * be zero if they are missing from the DT.
+	 * return 0.
 	 */
 	memset(mem, 0, sizeof(struct resource));
+	mem->end = -1;
 	memset(io, 0, sizeof(struct resource));
+	io->end = -1;
 	ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
 	if (!ret) {

drivers/char/tpm/xen-tpmfront.c+0−36

@@ -142,32 +142,6 @@ static int vtpm_recv(struct tpm_chip chip, u8 buf, size_t count) · 141 unmodified lines
142	return length;	142	return length;
143	}	143	}
144		144
145	ssize_t tpm_show_locality(struct device dev, struct device_attribute attr,
146	char *buf)
147	{
148	struct tpm_chip *chip = dev_get_drvdata(dev);
149	struct tpm_private *priv = TPM_VPRIV(chip);
150	u8 locality = priv->shr->locality;
151
152	return sprintf(buf, "%d\n", locality);
153	}
154
155	ssize_t tpm_store_locality(struct device dev, struct device_attribute attr,
156	const char *buf, size_t len)
157	{
158	struct tpm_chip *chip = dev_get_drvdata(dev);
159	struct tpm_private *priv = TPM_VPRIV(chip);
160	u8 val;
161
162	int rv = kstrtou8(buf, 0, &val);
163	if (rv)
164	return rv;
165
166	priv->shr->locality = val;
167
168	return len;
169	}
170
171	static const struct file_operations vtpm_ops = {	145	static const struct file_operations vtpm_ops = {
172	.owner = THIS_MODULE,	146	.owner = THIS_MODULE,
173	.llseek = no_llseek,	147	.llseek = no_llseek,
@@ -188,8 +162,6 @@ static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL); · 14 unmodified lines
188	static DEVICE_ATTR(cancel, S_IWUSR \| S_IWGRP, NULL, tpm_store_cancel);	162	static DEVICE_ATTR(cancel, S_IWUSR \| S_IWGRP, NULL, tpm_store_cancel);
189	static DEVICE_ATTR(durations, S_IRUGO, tpm_show_durations, NULL);	163	static DEVICE_ATTR(durations, S_IRUGO, tpm_show_durations, NULL);
190	static DEVICE_ATTR(timeouts, S_IRUGO, tpm_show_timeouts, NULL);	164	static DEVICE_ATTR(timeouts, S_IRUGO, tpm_show_timeouts, NULL);
191	static DEVICE_ATTR(locality, S_IRUGO \| S_IWUSR, tpm_show_locality,
192	tpm_store_locality);
193		165
194	static struct attribute *vtpm_attrs[] = {	166	static struct attribute *vtpm_attrs[] = {
195	&dev_attr_pubek.attr,	167	&dev_attr_pubek.attr,
@@ -202,7 +174,6 @@ static struct attribute *vtpm_attrs[] = { · 6 unmodified lines
202	&dev_attr_cancel.attr,	174	&dev_attr_cancel.attr,
203	&dev_attr_durations.attr,	175	&dev_attr_durations.attr,
204	&dev_attr_timeouts.attr,	176	&dev_attr_timeouts.attr,
205	&dev_attr_locality.attr,
206	NULL,	177	NULL,
207	};	178	};
208		179
@@ -210,8 +181,6 @@ static struct attribute_group vtpm_attr_grp = { · 1 unmodified line
210	.attrs = vtpm_attrs,	181	.attrs = vtpm_attrs,
211	};	182	};
212		183
213	#define TPM_LONG_TIMEOUT (10 * 60 * HZ)
214
215	static const struct tpm_vendor_specific tpm_vtpm = {	184	static const struct tpm_vendor_specific tpm_vtpm = {
216	.status = vtpm_status,	185	.status = vtpm_status,
217	.recv = vtpm_recv,	186	.recv = vtpm_recv,
@@ -224,11 +193,6 @@ static const struct tpm_vendor_specific tpm_vtpm = { · 6 unmodified lines
224	.miscdev = {	193	.miscdev = {
225	.fops = &vtpm_ops,	194	.fops = &vtpm_ops,
226	},	195	},
227	.duration = {
228	TPM_LONG_TIMEOUT,
229	TPM_LONG_TIMEOUT,
230	TPM_LONG_TIMEOUT,
231	},
232	};	196	};
233		197
234	static irqreturn_t tpmif_interrupt(int dummy, void *dev_id)	198	static irqreturn_t tpmif_interrupt(int dummy, void *dev_id)

drivers/clocksource/Kconfig+1−0

@@ -26,6 +26,7 @@ config DW_APB_TIMER_OF · 25 unmodified lines
26		26
27	config ARMADA_370_XP_TIMER	27	config ARMADA_370_XP_TIMER
28	bool	28	bool
		29	select CLKSRC_OF
29		30
30	config ORION_TIMER	31	config ORION_TIMER
31	select CLKSRC_OF	32	select CLKSRC_OF

drivers/clocksource/clksrc-of.c+3−0

@@ -30,6 +30,9 @@ void __init clocksource_of_init(void) · 29 unmodified lines
30	clocksource_of_init_fn init_func;	30	clocksource_of_init_fn init_func;
31		31
32	for_each_matching_node_and_match(np, __clksrc_of_table, &match) {	32	for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
		33	if (!of_device_is_available(np))
		34	continue;
		35
33	init_func = match->data;	36	init_func = match->data;
34	init_func(np);	37	init_func(np);
35	}	38	}

drivers/clocksource/em_sti.c+1−1

@@ -301,7 +301,7 @@ static void em_sti_register_clockevent(struct em_sti_priv *p) · 300 unmodified lines
301	ced->name = dev_name(&p->pdev->dev);	301	ced->name = dev_name(&p->pdev->dev);
302	ced->features = CLOCK_EVT_FEAT_ONESHOT;	302	ced->features = CLOCK_EVT_FEAT_ONESHOT;
303	ced->rating = 200;	303	ced->rating = 200;
304	ced->cpumask = cpumask_of(0);	304	ced->cpumask = cpu_possible_mask;
305	ced->set_next_event = em_sti_clock_event_next;	305	ced->set_next_event = em_sti_clock_event_next;
306	ced->set_mode = em_sti_clock_event_mode;	306	ced->set_mode = em_sti_clock_event_mode;
307		307

drivers/clocksource/exynos_mct.c+9−1

 				evt->irq);
 			return -EIO;
 		}
-		irq_set_affinity(evt->irq, cpumask_of(cpu));
 	} else {
 		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
 	}
 					   unsigned long action, void *hcpu)
 {
 	struct mct_clock_event_device *mevt;
+	unsigned int cpu;
 	/*
 	 * Grab cpu pointer in each case to avoid spurious
 		mevt = this_cpu_ptr(&percpu_mct_tick);
 		exynos4_local_timer_setup(&mevt->evt);
 		break;
+	case CPU_ONLINE:
+		cpu = (unsigned long)hcpu;
+		if (mct_int_type == MCT_INT_SPI)
+			irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
+						cpumask_of(cpu));
+		break;
 	case CPU_DYING:
 		mevt = this_cpu_ptr(&percpu_mct_tick);
 		exynos4_local_timer_stop(&mevt->evt);
 					 &percpu_mct_tick);
 		WARN(err, "MCT: can't request IRQ %d (%d)\n",
 		     mct_irqs[MCT_L0_IRQ], err);
+	} else {
+		irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
 	}
 	err = register_cpu_notifier(&exynos4_mct_cpu_nb);

drivers/cpufreq/acpi-cpufreq.c+4−0

@@ -986,6 +986,10 @@ static int __init acpi_cpufreq_init(void) · 985 unmodified lines
986	{	986	{
987	int ret;	987	int ret;
988		988
		989	/* don't keep reloading if cpufreq_driver exists */
		990	if (cpufreq_get_current_driver())
		991	return 0;
		992
989	if (acpi_disabled)	993	if (acpi_disabled)
990	return 0;	994	return 0;
991		995

drivers/cpufreq/cpufreq-cpu0.c+7−2

 #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
 #include <linux/clk.h>
+#include <linux/cpu.h>
 #include <linux/cpufreq.h>
 #include <linux/err.h>
 #include <linux/module.h>
 	struct device_node *np;
 	int ret;
-	cpu_dev = &pdev->dev;
+	cpu_dev = get_cpu_device(0);
+	if (!cpu_dev) {
+		pr_err("failed to get cpu0 device\n");
+		return -ENODEV;
+	}
 	np = of_node_get(cpu_dev->of_node);
 	if (!np) {
 	if (of_property_read_u32(np, "clock-latency", &transition_latency))
 		transition_latency = CPUFREQ_ETERNAL;
-	if (cpu_reg) {
+	if (!IS_ERR(cpu_reg)) {
 		struct opp *opp;
 		unsigned long min_uV, max_uV;
 		int i;

drivers/cpufreq/cpufreq.c+23−11

@@ -952,9 +952,20 @@ static void update_policy_cpu(struct cpufreq_policy *policy, unsigned int cpu) · 951 unmodified lines
952	if (cpu == policy->cpu)	952	if (cpu == policy->cpu)
953	return;	953	return;
954		954
		955	/*
		956	* Take direct locks as lock_policy_rwsem_write wouldn't work here.
		957	* Also lock for last cpu is enough here as contention will happen only
		958	* after policy->cpu is changed and after it is changed, other threads
		959	* will try to acquire lock for new cpu. And policy is already updated
		960	* by then.
		961	*/
		962	down_write(&per_cpu(cpu_policy_rwsem, policy->cpu));
		963
955	policy->last_cpu = policy->cpu;	964	policy->last_cpu = policy->cpu;
956	policy->cpu = cpu;	965	policy->cpu = cpu;
957		966
		967	up_write(&per_cpu(cpu_policy_rwsem, policy->last_cpu));
		968
958	#ifdef CONFIG_CPU_FREQ_TABLE	969	#ifdef CONFIG_CPU_FREQ_TABLE
959	cpufreq_frequency_table_update_policy_cpu(policy);	970	cpufreq_frequency_table_update_policy_cpu(policy);
960	#endif	971	#endif
@@ -1125,7 +1136,7 @@ static int cpufreq_nominate_new_policy_cpu(struct cpufreq_policy *policy, · 164 unmodified lines
1125	int ret;	1136	int ret;
1126		1137
1127	/* first sibling now owns the new sysfs dir */	1138	/* first sibling now owns the new sysfs dir */
1128	cpu_dev = get_cpu_device(cpumask_first(policy->cpus));	1139	cpu_dev = get_cpu_device(cpumask_any_but(policy->cpus, old_cpu));
1129		1140
1130	/* Don't touch sysfs files during light-weight tear-down */	1141	/* Don't touch sysfs files during light-weight tear-down */
1131	if (frozen)	1142	if (frozen)
@@ -1189,12 +1200,9 @@ static int __cpufreq_remove_dev_prepare(struct device *dev, · 57 unmodified lines
1189	policy->governor->name, CPUFREQ_NAME_LEN);	1200	policy->governor->name, CPUFREQ_NAME_LEN);
1190	#endif	1201	#endif
1191		1202
1192	WARN_ON(lock_policy_rwsem_write(cpu));	1203	lock_policy_rwsem_read(cpu);
1193	cpus = cpumask_weight(policy->cpus);	1204	cpus = cpumask_weight(policy->cpus);
1194		1205	unlock_policy_rwsem_read(cpu);
1195	if (cpus > 1)
1196	cpumask_clear_cpu(cpu, policy->cpus);
1197	unlock_policy_rwsem_write(cpu);
1198		1206
1199	if (cpu != policy->cpu) {	1207	if (cpu != policy->cpu) {
1200	if (!frozen)	1208	if (!frozen)
@@ -1203,9 +1211,7 @@ static int __cpufreq_remove_dev_prepare(struct device *dev, · 2 unmodified lines
1203		1211
1204	new_cpu = cpufreq_nominate_new_policy_cpu(policy, cpu, frozen);	1212	new_cpu = cpufreq_nominate_new_policy_cpu(policy, cpu, frozen);
1205	if (new_cpu >= 0) {	1213	if (new_cpu >= 0) {
1206	WARN_ON(lock_policy_rwsem_write(cpu));
1207	update_policy_cpu(policy, new_cpu);	1214	update_policy_cpu(policy, new_cpu);
1208	unlock_policy_rwsem_write(cpu);
1209		1215
1210	if (!frozen) {	1216	if (!frozen) {
1211	pr_debug("%s: policy Kobject moved to cpu: %d "	1217	pr_debug("%s: policy Kobject moved to cpu: %d "
@@ -1237,9 +1243,12 @@ static int __cpufreq_remove_dev_finish(struct device *dev, · 25 unmodified lines
1237	return -EINVAL;	1243	return -EINVAL;
1238	}	1244	}
1239		1245
1240	lock_policy_rwsem_read(cpu);	1246	WARN_ON(lock_policy_rwsem_write(cpu));
1241	cpus = cpumask_weight(policy->cpus);	1247	cpus = cpumask_weight(policy->cpus);
1242	unlock_policy_rwsem_read(cpu);	1248
		1249	if (cpus > 1)
		1250	cpumask_clear_cpu(cpu, policy->cpus);
		1251	unlock_policy_rwsem_write(cpu);
1243		1252
1244	/* If cpu is last user of policy, free policy */	1253	/* If cpu is last user of policy, free policy */
1245	if (cpus == 1) {	1254	if (cpus == 1) {
@@ -1451,6 +1460,9 @@ unsigned int cpufreq_get(unsigned int cpu) · 205 unmodified lines
1451	{	1460	{
1452	unsigned int ret_freq = 0;	1461	unsigned int ret_freq = 0;
1453		1462
		1463	if (cpufreq_disabled() \|\| !cpufreq_driver)
		1464	return -ENOENT;
		1465
1454	if (!down_read_trylock(&cpufreq_rwsem))	1466	if (!down_read_trylock(&cpufreq_rwsem))
1455	return 0;	1467	return 0;
1456		1468
@@ -2095,7 +2107,7 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data) · 638 unmodified lines
2095	write_lock_irqsave(&cpufreq_driver_lock, flags);	2107	write_lock_irqsave(&cpufreq_driver_lock, flags);
2096	if (cpufreq_driver) {	2108	if (cpufreq_driver) {
2097	write_unlock_irqrestore(&cpufreq_driver_lock, flags);	2109	write_unlock_irqrestore(&cpufreq_driver_lock, flags);
2098	return -EBUSY;	2110	return -EEXIST;
2099	}	2111	}
2100	cpufreq_driver = driver_data;	2112	cpufreq_driver = driver_data;
2101	write_unlock_irqrestore(&cpufreq_driver_lock, flags);	2113	write_unlock_irqrestore(&cpufreq_driver_lock, flags);

drivers/cpufreq/exynos5440-cpufreq.c+1−1

@@ -457,7 +457,7 @@ err_free_table: · 456 unmodified lines
457	opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);	457	opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
458	err_put_node:	458	err_put_node:
459	of_node_put(np);	459	of_node_put(np);
460	dev_err(dvfs_info->dev, "%s: failed initialization\n", __func__);	460	dev_err(&pdev->dev, "%s: failed initialization\n", __func__);
461	return ret;	461	return ret;
462	}	462	}
463		463

drivers/cpufreq/imx6q-cpufreq.c+6−1

  */
 #include <linux/clk.h>
+#include <linux/cpu.h>
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 	unsigned long min_volt, max_volt;
 	int num, ret;
-	cpu_dev = &pdev->dev;
+	cpu_dev = get_cpu_device(0);
+	if (!cpu_dev) {
+		pr_err("failed to get cpu0 device\n");
+		return -ENODEV;
+	}
 	np = of_node_get(cpu_dev->of_node);
 	if (!np) {

drivers/cpufreq/intel_pstate.c+4−1

@@ -394,7 +394,10 @@ static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) · 393 unmodified lines
394	trace_cpu_frequency(pstate * 100000, cpu->cpu);	394	trace_cpu_frequency(pstate * 100000, cpu->cpu);
395		395
396	cpu->pstate.current_pstate = pstate;	396	cpu->pstate.current_pstate = pstate;
397	wrmsrl(MSR_IA32_PERF_CTL, pstate << 8);	397	if (limits.no_turbo)
		398	wrmsrl(MSR_IA32_PERF_CTL, BIT(32) \| (pstate << 8));
		399	else
		400	wrmsrl(MSR_IA32_PERF_CTL, pstate << 8);
398		401
399	}	402	}
400		403

drivers/cpufreq/spear-cpufreq.c+1−1

@@ -113,7 +113,7 @@ static int spear_cpufreq_target(struct cpufreq_policy *policy, · 112 unmodified lines
113	unsigned int target_freq, unsigned int relation)	113	unsigned int target_freq, unsigned int relation)
114	{	114	{
115	struct cpufreq_freqs freqs;	115	struct cpufreq_freqs freqs;
116	unsigned long newfreq;	116	long newfreq;
117	struct clk *srcclk;	117	struct clk *srcclk;
118	int index, ret, mult = 1;	118	int index, ret, mult = 1;
119		119

drivers/dma/Kconfig+1−0

@@ -198,6 +198,7 @@ config TI_EDMA · 197 unmodified lines
198	depends on ARCH_DAVINCI \|\| ARCH_OMAP	198	depends on ARCH_DAVINCI \|\| ARCH_OMAP
199	select DMA_ENGINE	199	select DMA_ENGINE
200	select DMA_VIRTUAL_CHANNELS	200	select DMA_VIRTUAL_CHANNELS
		201	select TI_PRIV_EDMA
201	default n	202	default n
202	help	203	help
203	Enable support for the TI EDMA controller. This DMA	204	Enable support for the TI EDMA controller. This DMA

drivers/dma/edma.c+1−1

@@ -749,6 +749,6 @@ static void __exit edma_exit(void) · 748 unmodified lines
749	}	749	}
750	module_exit(edma_exit);	750	module_exit(edma_exit);
751		751
752	MODULE_AUTHOR("Matt Porter <mporter@ti.com>");	752	MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
753	MODULE_DESCRIPTION("TI EDMA DMA engine driver");	753	MODULE_DESCRIPTION("TI EDMA DMA engine driver");
754	MODULE_LICENSE("GPL v2");	754	MODULE_LICENSE("GPL v2");

drivers/dma/imx-dma.c+15−16

 	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
+	unsigned long flags;
-	spin_lock(&imxdma->lock);
+	spin_lock_irqsave(&imxdma->lock, flags);
 	if (list_empty(&imxdmac->ld_active)) {
-		spin_unlock(&imxdma->lock);
+		spin_unlock_irqrestore(&imxdma->lock, flags);
 		goto out;
 	}
 	desc = list_first_entry(&imxdmac->ld_active,
 				struct imxdma_desc,
 				node);
-	spin_unlock(&imxdma->lock);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
 	if (desc->sg) {
 		u32 tmp;
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
-	unsigned long flags;
 	int slot = -1;
 	int i;
 	switch (d->type) {
 	case IMXDMA_DESC_INTERLEAVED:
 		/* Try to get a free 2D slot */
-		spin_lock_irqsave(&imxdma->lock, flags);
 		for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
 			if ((imxdma->slots_2d[i].count > 0) &&
 			((imxdma->slots_2d[i].xsr != d->x) ||
 			slot = i;
 			break;
 		}
-		if (slot < 0) {
+		if (slot < 0)
-			spin_unlock_irqrestore(&imxdma->lock, flags);
 			return -EBUSY;
-		}
 		imxdma->slots_2d[slot].xsr = d->x;
 		imxdma->slots_2d[slot].ysr = d->y;
 		imxdmac->slot_2d = slot;
 		imxdmac->enabled_2d = true;
-		spin_unlock_irqrestore(&imxdma->lock, flags);
 		if (slot == IMX_DMA_2D_SLOT_A) {
 			d->config_mem &= ~CCR_MSEL_B;
 	struct imxdma_channel *imxdmac = (void *)data;
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct imxdma_desc *desc;
+	unsigned long flags;
-	spin_lock(&imxdma->lock);
+	spin_lock_irqsave(&imxdma->lock, flags);
 	if (list_empty(&imxdmac->ld_active)) {
 		/* Someone might have called terminate all */
-		goto out;
+		spin_unlock_irqrestore(&imxdma->lock, flags);
+		return;
 	}
 	desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
-	if (desc->desc.callback)
-		desc->desc.callback(desc->desc.callback_param);
 	/* If we are dealing with a cyclic descriptor, keep it on ld_active
 	 * and dont mark the descriptor as complete.
 	 * Only in non-cyclic cases it would be marked as complete
 				 __func__, imxdmac->channel);
 	}
 out:
-	spin_unlock(&imxdma->lock);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
+	if (desc->desc.callback)
+		desc->desc.callback(desc->desc.callback_param);
 }
 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 	kfree(imxdmac->sg_list);
 	imxdmac->sg_list = kcalloc(periods + 1,
-			sizeof(struct scatterlist), GFP_KERNEL);
+			sizeof(struct scatterlist), GFP_ATOMIC);
 	if (!imxdmac->sg_list)
 		return NULL;

drivers/gpio/gpio-omap.c+101−57

@@ -63,6 +63,7 @@ struct gpio_bank { · 62 unmodified lines
63	struct gpio_chip chip;	63	struct gpio_chip chip;
64	struct clk *dbck;	64	struct clk *dbck;
65	u32 mod_usage;	65	u32 mod_usage;
		66	u32 irq_usage;
66	u32 dbck_enable_mask;	67	u32 dbck_enable_mask;
67	bool dbck_enabled;	68	bool dbck_enabled;
68	struct device *dev;	69	struct device *dev;
@@ -86,6 +87,9 @@ struct gpio_bank { · 17 unmodified lines
86	#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))	87	#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
87	#define GPIO_MOD_CTRL_BIT BIT(0)	88	#define GPIO_MOD_CTRL_BIT BIT(0)
88		89
		90	#define BANK_USED(bank) (bank->mod_usage \|\| bank->irq_usage)
		91	#define LINE_USED(line, offset) (line & (1 << offset))
		92
89	static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)	93	static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
90	{	94	{
91	return bank->chip.base + gpio_irq;	95	return bank->chip.base + gpio_irq;
@@ -420,15 +424,69 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, · 328 unmodified lines
420	return 0;	424	return 0;
421	}	425	}
422		426
		427	static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset)
		428	{
		429	if (bank->regs->pinctrl) {
		430	void __iomem *reg = bank->base + bank->regs->pinctrl;
		431
		432	/* Claim the pin for MPU */
		433	__raw_writel(__raw_readl(reg) \| (1 << offset), reg);
		434	}
		435
		436	if (bank->regs->ctrl && !BANK_USED(bank)) {
		437	void __iomem *reg = bank->base + bank->regs->ctrl;
		438	u32 ctrl;
		439
		440	ctrl = __raw_readl(reg);
		441	/* Module is enabled, clocks are not gated */
		442	ctrl &= ~GPIO_MOD_CTRL_BIT;
		443	__raw_writel(ctrl, reg);
		444	bank->context.ctrl = ctrl;
		445	}
		446	}
		447
		448	static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset)
		449	{
		450	void __iomem *base = bank->base;
		451
		452	if (bank->regs->wkup_en &&
		453	!LINE_USED(bank->mod_usage, offset) &&
		454	!LINE_USED(bank->irq_usage, offset)) {
		455	/* Disable wake-up during idle for dynamic tick */
		456	_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
		457	bank->context.wake_en =
		458	__raw_readl(bank->base + bank->regs->wkup_en);
		459	}
		460
		461	if (bank->regs->ctrl && !BANK_USED(bank)) {
		462	void __iomem *reg = bank->base + bank->regs->ctrl;
		463	u32 ctrl;
		464
		465	ctrl = __raw_readl(reg);
		466	/* Module is disabled, clocks are gated */
		467	ctrl \|= GPIO_MOD_CTRL_BIT;
		468	__raw_writel(ctrl, reg);
		469	bank->context.ctrl = ctrl;
		470	}
		471	}
		472
		473	static int gpio_is_input(struct gpio_bank *bank, int mask)
		474	{
		475	void __iomem *reg = bank->base + bank->regs->direction;
		476
		477	return __raw_readl(reg) & mask;
		478	}
		479
423	static int gpio_irq_type(struct irq_data *d, unsigned type)	480	static int gpio_irq_type(struct irq_data *d, unsigned type)
424	{	481	{
425	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);	482	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
426	unsigned gpio = 0;	483	unsigned gpio = 0;
427	int retval;	484	int retval;
428	unsigned long flags;	485	unsigned long flags;
		486	unsigned offset;
429		487
430	if (WARN_ON(!bank->mod_usage))	488	if (!BANK_USED(bank))
431	return -EINVAL;	489	pm_runtime_get_sync(bank->dev);
432		490
433	#ifdef CONFIG_ARCH_OMAP1	491	#ifdef CONFIG_ARCH_OMAP1
434	if (d->irq > IH_MPUIO_BASE)	492	if (d->irq > IH_MPUIO_BASE)
@@ -446,7 +504,17 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) · 11 unmodified lines
446	return -EINVAL;	504	return -EINVAL;
447		505
448	spin_lock_irqsave(&bank->lock, flags);	506	spin_lock_irqsave(&bank->lock, flags);
449	retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);	507	offset = GPIO_INDEX(bank, gpio);
		508	retval = _set_gpio_triggering(bank, offset, type);
		509	if (!LINE_USED(bank->mod_usage, offset)) {
		510	_enable_gpio_module(bank, offset);
		511	_set_gpio_direction(bank, offset, 1);
		512	} else if (!gpio_is_input(bank, 1 << offset)) {
		513	spin_unlock_irqrestore(&bank->lock, flags);
		514	return -EINVAL;
		515	}
		516
		517	bank->irq_usage \|= 1 << GPIO_INDEX(bank, gpio);
450	spin_unlock_irqrestore(&bank->lock, flags);	518	spin_unlock_irqrestore(&bank->lock, flags);
451		519
452	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))	520	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
@@ -603,35 +671,19 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) · 150 unmodified lines
603	* If this is the first gpio_request for the bank,	671	* If this is the first gpio_request for the bank,
604	* enable the bank module.	672	* enable the bank module.
605	*/	673	*/
606	if (!bank->mod_usage)	674	if (!BANK_USED(bank))
607	pm_runtime_get_sync(bank->dev);	675	pm_runtime_get_sync(bank->dev);
608		676
609	spin_lock_irqsave(&bank->lock, flags);	677	spin_lock_irqsave(&bank->lock, flags);
610	/* Set trigger to none. You need to enable the desired trigger with	678	/* Set trigger to none. You need to enable the desired trigger with
611	* request_irq() or set_irq_type().	679	* request_irq() or set_irq_type(). Only do this if the IRQ line has
		680	* not already been requested.
612	*/	681	*/
613	_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);	682	if (!LINE_USED(bank->irq_usage, offset)) {
614		683	_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
615	if (bank->regs->pinctrl) {	684	_enable_gpio_module(bank, offset);
616	void __iomem *reg = bank->base + bank->regs->pinctrl;
617
618	/* Claim the pin for MPU */
619	__raw_writel(__raw_readl(reg) \| (1 << offset), reg);
620	}
621
622	if (bank->regs->ctrl && !bank->mod_usage) {
623	void __iomem *reg = bank->base + bank->regs->ctrl;
624	u32 ctrl;
625
626	ctrl = __raw_readl(reg);
627	/* Module is enabled, clocks are not gated */
628	ctrl &= ~GPIO_MOD_CTRL_BIT;
629	__raw_writel(ctrl, reg);
630	bank->context.ctrl = ctrl;
631	}	685	}
632
633	bank->mod_usage \|= 1 << offset;	686	bank->mod_usage \|= 1 << offset;
634
635	spin_unlock_irqrestore(&bank->lock, flags);	687	spin_unlock_irqrestore(&bank->lock, flags);
636		688
637	return 0;	689	return 0;
@@ -640,31 +692,11 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) · 2 unmodified lines
640	static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)	692	static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
641	{	693	{
642	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);	694	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
643	void __iomem *base = bank->base;
644	unsigned long flags;	695	unsigned long flags;
645		696
646	spin_lock_irqsave(&bank->lock, flags);	697	spin_lock_irqsave(&bank->lock, flags);
647
648	if (bank->regs->wkup_en) {
649	/* Disable wake-up during idle for dynamic tick */
650	_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
651	bank->context.wake_en =
652	__raw_readl(bank->base + bank->regs->wkup_en);
653	}
654
655	bank->mod_usage &= ~(1 << offset);	698	bank->mod_usage &= ~(1 << offset);
656		699	_disable_gpio_module(bank, offset);
657	if (bank->regs->ctrl && !bank->mod_usage) {
658	void __iomem *reg = bank->base + bank->regs->ctrl;
659	u32 ctrl;
660
661	ctrl = __raw_readl(reg);
662	/* Module is disabled, clocks are gated */
663	ctrl \|= GPIO_MOD_CTRL_BIT;
664	__raw_writel(ctrl, reg);
665	bank->context.ctrl = ctrl;
666	}
667
668	_reset_gpio(bank, bank->chip.base + offset);	700	_reset_gpio(bank, bank->chip.base + offset);
669	spin_unlock_irqrestore(&bank->lock, flags);	701	spin_unlock_irqrestore(&bank->lock, flags);
670		702
@@ -672,7 +704,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) · 1 unmodified line
672	* If this is the last gpio to be freed in the bank,	704	* If this is the last gpio to be freed in the bank,
673	* disable the bank module.	705	* disable the bank module.
674	*/	706	*/
675	if (!bank->mod_usage)	707	if (!BANK_USED(bank))
676	pm_runtime_put(bank->dev);	708	pm_runtime_put(bank->dev);
677	}	709	}
678		710
@@ -762,10 +794,20 @@ static void gpio_irq_shutdown(struct irq_data *d) · 83 unmodified lines
762	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);	794	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
763	unsigned int gpio = irq_to_gpio(bank, d->hwirq);	795	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
764	unsigned long flags;	796	unsigned long flags;
		797	unsigned offset = GPIO_INDEX(bank, gpio);
765		798
766	spin_lock_irqsave(&bank->lock, flags);	799	spin_lock_irqsave(&bank->lock, flags);
		800	bank->irq_usage &= ~(1 << offset);
		801	_disable_gpio_module(bank, offset);
767	_reset_gpio(bank, gpio);	802	_reset_gpio(bank, gpio);
768	spin_unlock_irqrestore(&bank->lock, flags);	803	spin_unlock_irqrestore(&bank->lock, flags);
		804
		805	/*
		806	* If this is the last IRQ to be freed in the bank,
		807	* disable the bank module.
		808	*/
		809	if (!BANK_USED(bank))
		810	pm_runtime_put(bank->dev);
769	}	811	}
770		812
771	static void gpio_ack_irq(struct irq_data *d)	813	static void gpio_ack_irq(struct irq_data *d)
@@ -897,13 +939,6 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset) · 125 unmodified lines
897	return 0;	939	return 0;
898	}	940	}
899		941
900	static int gpio_is_input(struct gpio_bank *bank, int mask)
901	{
902	void __iomem *reg = bank->base + bank->regs->direction;
903
904	return __raw_readl(reg) & mask;
905	}
906
907	static int gpio_get(struct gpio_chip *chip, unsigned offset)	942	static int gpio_get(struct gpio_chip *chip, unsigned offset)
908	{	943	{
909	struct gpio_bank *bank;	944	struct gpio_bank *bank;
@@ -922,13 +957,22 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) · 12 unmodified lines
922	{	957	{
923	struct gpio_bank *bank;	958	struct gpio_bank *bank;
924	unsigned long flags;	959	unsigned long flags;
		960	int retval = 0;
925		961
926	bank = container_of(chip, struct gpio_bank, chip);	962	bank = container_of(chip, struct gpio_bank, chip);
927	spin_lock_irqsave(&bank->lock, flags);	963	spin_lock_irqsave(&bank->lock, flags);
		964
		965	if (LINE_USED(bank->irq_usage, offset)) {
		966	retval = -EINVAL;
		967	goto exit;
		968	}
		969
928	bank->set_dataout(bank, offset, value);	970	bank->set_dataout(bank, offset, value);
929	_set_gpio_direction(bank, offset, 0);	971	_set_gpio_direction(bank, offset, 0);
		972
		973	exit:
930	spin_unlock_irqrestore(&bank->lock, flags);	974	spin_unlock_irqrestore(&bank->lock, flags);
931	return 0;	975	return retval;
932	}	976	}
933		977
934	static int gpio_debounce(struct gpio_chip *chip, unsigned offset,	978	static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
@@ -1400,7 +1444,7 @@ void omap2_gpio_prepare_for_idle(int pwr_mode) · 465 unmodified lines
1400	struct gpio_bank *bank;	1444	struct gpio_bank *bank;
1401		1445
1402	list_for_each_entry(bank, &omap_gpio_list, node) {	1446	list_for_each_entry(bank, &omap_gpio_list, node) {
1403	if (!bank->mod_usage \|\| !bank->loses_context)	1447	if (!BANK_USED(bank) \|\| !bank->loses_context)
1404	continue;	1448	continue;
1405		1449
1406	bank->power_mode = pwr_mode;	1450	bank->power_mode = pwr_mode;
@@ -1414,7 +1458,7 @@ void omap2_gpio_resume_after_idle(void) · 7 unmodified lines
1414	struct gpio_bank *bank;	1458	struct gpio_bank *bank;
1415		1459
1416	list_for_each_entry(bank, &omap_gpio_list, node) {	1460	list_for_each_entry(bank, &omap_gpio_list, node) {
1417	if (!bank->mod_usage \|\| !bank->loses_context)	1461	if (!BANK_USED(bank) \|\| !bank->loses_context)
1418	continue;	1462	continue;
1419		1463
1420	pm_runtime_get_sync(bank->dev);	1464	pm_runtime_get_sync(bank->dev);

drivers/gpio/gpio-rcar.c+3−4

 	if (pdata) {
 		p->config = *pdata;
 	} else if (IS_ENABLED(CONFIG_OF) && np) {
-		ret = of_parse_phandle_with_args(np, "gpio-ranges",
+		ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
-				"#gpio-range-cells", 0, &args);
+						       &args);
-		p->config.number_of_pins = ret == 0 && args.args_count == 3
+		p->config.number_of_pins = ret == 0 ? args.args[2]
-					 ? args.args[2]
 					 : RCAR_MAX_GPIO_PER_BANK;
 		p->config.gpio_base = -1;
 	}

drivers/gpu/drm/ast/ast_drv.h+1−1

@@ -177,7 +177,7 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast, · 176 unmodified lines
177		177
178	static inline void ast_open_key(struct ast_private *ast)	178	static inline void ast_open_key(struct ast_private *ast)
179	{	179	{
180	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xA1, 0xFF, 0x04);	180	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
181	}	181	}
182		182
183	#define AST_VIDMEM_SIZE_8M 0x00800000	183	#define AST_VIDMEM_SIZE_8M 0x00800000

drivers/gpu/drm/drm_context.c+8−65

 #include <drm/drmP.h>
+/******************************************************************/
+/** \name Context bitmap support */
+/*@{*/
 /**
  * Free a handle from the context bitmap.
  *
  * in drm_device::ctx_idr, while holding the drm_device::struct_mutex
  * lock.
  */
-static void drm_ctxbitmap_free(struct drm_device * dev, int ctx_handle)
+void drm_ctxbitmap_free(struct drm_device * dev, int ctx_handle)
 {
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return;
 	mutex_lock(&dev->struct_mutex);
 	idr_remove(&dev->ctx_idr, ctx_handle);
 	mutex_unlock(&dev->struct_mutex);
 }
-/******************************************************************/
-/** \name Context bitmap support */
-/*@{*/
-void drm_legacy_ctxbitmap_release(struct drm_device *dev,
-				  struct drm_file *file_priv)
-{
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return;
-	mutex_lock(&dev->ctxlist_mutex);
-	if (!list_empty(&dev->ctxlist)) {
-		struct drm_ctx_list *pos, *n;
-		list_for_each_entry_safe(pos, n, &dev->ctxlist, head) {
-			if (pos->tag == file_priv &&
-			    pos->handle != DRM_KERNEL_CONTEXT) {
-				if (dev->driver->context_dtor)
-					dev->driver->context_dtor(dev,
-								  pos->handle);
-				drm_ctxbitmap_free(dev, pos->handle);
-				list_del(&pos->head);
-				kfree(pos);
-				--dev->ctx_count;
-			}
-		}
-	}
-	mutex_unlock(&dev->ctxlist_mutex);
-}
 /**
  * Context bitmap allocation.
  *
  *
  * Initialise the drm_device::ctx_idr
  */
-void drm_legacy_ctxbitmap_init(struct drm_device * dev)
+int drm_ctxbitmap_init(struct drm_device * dev)
 {
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return;
 	idr_init(&dev->ctx_idr);
+	return 0;
 }
 /**
  * Free all idr members using drm_ctx_sarea_free helper function
  * while holding the drm_device::struct_mutex lock.
  */
-void drm_legacy_ctxbitmap_cleanup(struct drm_device * dev)
+void drm_ctxbitmap_cleanup(struct drm_device * dev)
 {
 	mutex_lock(&dev->struct_mutex);
 	idr_destroy(&dev->ctx_idr);
 	struct drm_local_map *map;
 	struct drm_map_list *_entry;
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return -EINVAL;
 	mutex_lock(&dev->struct_mutex);
 	map = idr_find(&dev->ctx_idr, request->ctx_id);
 	struct drm_local_map *map = NULL;
 	struct drm_map_list *r_list = NULL;
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return -EINVAL;
 	mutex_lock(&dev->struct_mutex);
 	list_for_each_entry(r_list, &dev->maplist, head) {
 		if (r_list->map
 	struct drm_ctx ctx;
 	int i;
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return -EINVAL;
 	if (res->count >= DRM_RESERVED_CONTEXTS) {
 		memset(&ctx, 0, sizeof(ctx));
 		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
 	struct drm_ctx_list *ctx_entry;
 	struct drm_ctx *ctx = data;
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return -EINVAL;
 	ctx->handle = drm_ctxbitmap_next(dev);
 	if (ctx->handle == DRM_KERNEL_CONTEXT) {
 		/* Skip kernel's context and get a new one. */
 {
 	struct drm_ctx *ctx = data;
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return -EINVAL;
 	/* This is 0, because we don't handle any context flags */
 	ctx->flags = 0;
 {
 	struct drm_ctx *ctx = data;
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return -EINVAL;
 	DRM_DEBUG("%d\n", ctx->handle);
 	return drm_context_switch(dev, dev->last_context, ctx->handle);
 }
 {
 	struct drm_ctx *ctx = data;
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return -EINVAL;
 	DRM_DEBUG("%d\n", ctx->handle);
 	drm_context_switch_complete(dev, file_priv, ctx->handle);
 {
 	struct drm_ctx *ctx = data;
-	if (drm_core_check_feature(dev, DRIVER_MODESET))
-		return -EINVAL;
 	DRM_DEBUG("%d\n", ctx->handle);
 	if (ctx->handle != DRM_KERNEL_CONTEXT) {
 		if (dev->driver->context_dtor)

drivers/gpu/drm/drm_fb_helper.c+8−0

@@ -407,6 +407,14 @@ static void drm_fb_helper_dpms(struct fb_info *info, int dpms_mode) · 406 unmodified lines
407	struct drm_connector *connector;	407	struct drm_connector *connector;
408	int i, j;	408	int i, j;
409		409
		410	/*
		411	* fbdev->blank can be called from irq context in case of a panic.
		412	* Since we already have our own special panic handler which will
		413	* restore the fbdev console mode completely, just bail out early.
		414	*/
		415	if (oops_in_progress)
		416	return;
		417
410	/*	418	/*
411	* fbdev->blank can be called from irq context in case of a panic.	419	* fbdev->blank can be called from irq context in case of a panic.
412	* Since we already have our own special panic handler which will	420	* Since we already have our own special panic handler which will

drivers/gpu/drm/drm_fops.c+20−1

@@ -439,7 +439,26 @@ int drm_release(struct inode inode, struct file filp) · 438 unmodified lines
439	if (dev->driver->driver_features & DRIVER_GEM)	439	if (dev->driver->driver_features & DRIVER_GEM)
440	drm_gem_release(dev, file_priv);	440	drm_gem_release(dev, file_priv);
441		441
442	drm_legacy_ctxbitmap_release(dev, file_priv);	442	mutex_lock(&dev->ctxlist_mutex);
		443	if (!list_empty(&dev->ctxlist)) {
		444	struct drm_ctx_list pos, n;
		445
		446	list_for_each_entry_safe(pos, n, &dev->ctxlist, head) {
		447	if (pos->tag == file_priv &&
		448	pos->handle != DRM_KERNEL_CONTEXT) {
		449	if (dev->driver->context_dtor)
		450	dev->driver->context_dtor(dev,
		451	pos->handle);
		452
		453	drm_ctxbitmap_free(dev, pos->handle);
		454
		455	list_del(&pos->head);
		456	kfree(pos);
		457	--dev->ctx_count;
		458	}
		459	}
		460	}
		461	mutex_unlock(&dev->ctxlist_mutex);
443		462
444	mutex_lock(&dev->struct_mutex);	463	mutex_lock(&dev->struct_mutex);
445		464

drivers/gpu/drm/drm_stub.c+8−2

@@ -292,7 +292,13 @@ int drm_fill_in_dev(struct drm_device *dev, · 291 unmodified lines
292	goto error_out_unreg;	292	goto error_out_unreg;
293	}	293	}
294		294
295	drm_legacy_ctxbitmap_init(dev);	295
		296
		297	retcode = drm_ctxbitmap_init(dev);
		298	if (retcode) {
		299	DRM_ERROR("Cannot allocate memory for context bitmap.\n");
		300	goto error_out_unreg;
		301	}
296		302
297	if (driver->driver_features & DRIVER_GEM) {	303	if (driver->driver_features & DRIVER_GEM) {
298	retcode = drm_gem_init(dev);	304	retcode = drm_gem_init(dev);
@@ -446,7 +452,7 @@ void drm_put_dev(struct drm_device *dev) · 147 unmodified lines
446	drm_rmmap(dev, r_list->map);	452	drm_rmmap(dev, r_list->map);
447	drm_ht_remove(&dev->map_hash);	453	drm_ht_remove(&dev->map_hash);
448		454
449	drm_legacy_ctxbitmap_cleanup(dev);	455	drm_ctxbitmap_cleanup(dev);
450		456
451	if (drm_core_check_feature(dev, DRIVER_MODESET))	457	if (drm_core_check_feature(dev, DRIVER_MODESET))
452	drm_put_minor(&dev->control);	458	drm_put_minor(&dev->control);

drivers/gpu/drm/exynos/Kconfig+1−1

@@ -56,7 +56,7 @@ config DRM_EXYNOS_IPP · 55 unmodified lines
56		56
57	config DRM_EXYNOS_FIMC	57	config DRM_EXYNOS_FIMC
58	bool "Exynos DRM FIMC"	58	bool "Exynos DRM FIMC"
59	depends on DRM_EXYNOS_IPP && MFD_SYSCON && OF	59	depends on DRM_EXYNOS_IPP && MFD_SYSCON
60	help	60	help
61	Choose this option if you want to use Exynos FIMC for DRM.	61	Choose this option if you want to use Exynos FIMC for DRM.
62		62

drivers/gpu/drm/exynos/exynos_drm_buf.c+4−3

 			return -ENOMEM;
 		}
-		buf->kvaddr = dma_alloc_attrs(dev->dev, buf->size,
+		buf->kvaddr = (void __iomem *)dma_alloc_attrs(dev->dev,
+					buf->size,
 					&buf->dma_addr, GFP_KERNEL,
 					&buf->dma_attrs);
 		if (!buf->kvaddr) {
 	}
 	buf->sgt = drm_prime_pages_to_sg(buf->pages, nr_pages);
-	if (!buf->sgt) {
+	if (IS_ERR(buf->sgt)) {
 		DRM_ERROR("failed to get sg table.\n");
-		ret = -ENOMEM;
+		ret = PTR_ERR(buf->sgt);
 		goto err_free_attrs;
 	}

drivers/gpu/drm/exynos/exynos_drm_fbdev.c+3−2

 		if (is_drm_iommu_supported(dev)) {
 			unsigned int nr_pages = buffer->size >> PAGE_SHIFT;
-			buffer->kvaddr = vmap(buffer->pages, nr_pages, VM_MAP,
+			buffer->kvaddr = (void __iomem *) vmap(buffer->pages,
+					nr_pages, VM_MAP,
 					pgprot_writecombine(PAGE_KERNEL));
 		} else {
 			phys_addr_t dma_addr = buffer->dma_addr;
 			if (dma_addr)
-				buffer->kvaddr = phys_to_virt(dma_addr);
+				buffer->kvaddr = (void __iomem *)phys_to_virt(dma_addr);
 			else
 				buffer->kvaddr = (void __iomem *)NULL;
 		}

drivers/gpu/drm/i2c/tda998x_drv.c+1−2

 		reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
 		break;
 	case DRM_MODE_DPMS_OFF:
-		/* disable audio and video ports */
+		/* disable video ports */
-		reg_write(encoder, REG_ENA_AP, 0x00);
 		reg_write(encoder, REG_ENA_VP_0, 0x00);
 		reg_write(encoder, REG_ENA_VP_1, 0x00);
 		reg_write(encoder, REG_ENA_VP_2, 0x00);

drivers/gpu/drm/i915/i915_gem.c+8−11

 		if (i915_terminally_wedged(&dev_priv->gpu_error))
 			return VM_FAULT_SIGBUS;
 	case -EAGAIN:
-		/* Give the error handler a chance to run and move the
+		/*
-		 * objects off the GPU active list. Next time we service the
+		 * EAGAIN means the gpu is hung and we'll wait for the error
-		 * fault, we should be able to transition the page into the
+		 * handler to reset everything when re-faulting in
-		 * GTT without touching the GPU (and so avoid further
+		 * i915_mutex_lock_interruptible.
-		 * EIO/EGAIN). If the GPU is wedged, then there is no issue
-		 * with coherency, just lost writes.
 		 */
-		set_need_resched();
 	case 0:
 	case -ERESTARTSYS:
 	case -EINTR:
 	if (!mutex_trylock(&dev->struct_mutex)) {
 		if (!mutex_is_locked_by(&dev->struct_mutex, current))
-			return SHRINK_STOP;
+			return 0;
 		if (dev_priv->mm.shrinker_no_lock_stealing)
-			return SHRINK_STOP;
+			return 0;
 		unlock = false;
 	}
 	if (!mutex_trylock(&dev->struct_mutex)) {
 		if (!mutex_is_locked_by(&dev->struct_mutex, current))
-			return 0;
+			return SHRINK_STOP;
 		if (dev_priv->mm.shrinker_no_lock_stealing)
-			return 0;
+			return SHRINK_STOP;
 		unlock = false;
 	}

drivers/gpu/drm/i915/i915_gpu_error.c+4−2

@@ -143,8 +143,10 @@ static void i915_error_vprintf(struct drm_i915_error_state_buf *e, · 142 unmodified lines
143		143
144	/* Seek the first printf which is hits start position */	144	/* Seek the first printf which is hits start position */
145	if (e->pos < e->start) {	145	if (e->pos < e->start) {
146	len = vsnprintf(NULL, 0, f, args);	146	va_list tmp;
147	if (!__i915_error_seek(e, len))	147
		148	va_copy(tmp, args);
		149	if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
148	return;	150	return;
149	}	151	}
150		152

drivers/gpu/drm/i915/i915_irq.c+54−14

@@ -1469,6 +1469,34 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) · 1468 unmodified lines
1469	return ret;	1469	return ret;
1470	}	1470	}
1471		1471
		1472	static void i915_error_wake_up(struct drm_i915_private *dev_priv,
		1473	bool reset_completed)
		1474	{
		1475	struct intel_ring_buffer *ring;
		1476	int i;
		1477
		1478	/*
		1479	* Notify all waiters for GPU completion events that reset state has
		1480	* been changed, and that they need to restart their wait after
		1481	* checking for potential errors (and bail out to drop locks if there is
		1482	* a gpu reset pending so that i915_error_work_func can acquire them).
		1483	*/
		1484
		1485	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
		1486	for_each_ring(ring, dev_priv, i)
		1487	wake_up_all(&ring->irq_queue);
		1488
		1489	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
		1490	wake_up_all(&dev_priv->pending_flip_queue);
		1491
		1492	/*
		1493	* Signal tasks blocked in i915_gem_wait_for_error that the pending
		1494	* reset state is cleared.
		1495	*/
		1496	if (reset_completed)
		1497	wake_up_all(&dev_priv->gpu_error.reset_queue);
		1498	}
		1499
1472	/**	1500	/**
1473	* i915_error_work_func - do process context error handling work	1501	* i915_error_work_func - do process context error handling work
1474	* @work: work struct	1502	* @work: work struct
@@ -1483,11 +1511,10 @@ static void i915_error_work_func(struct work_struct *work) · 8 unmodified lines
1483	drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,	1511	drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1484	gpu_error);	1512	gpu_error);
1485	struct drm_device *dev = dev_priv->dev;	1513	struct drm_device *dev = dev_priv->dev;
1486	struct intel_ring_buffer *ring;
1487	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };	1514	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1488	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };	1515	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1489	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };	1516	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1490	int i, ret;	1517	int ret;
1491		1518
1492	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);	1519	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1493		1520
@@ -1506,8 +1533,16 @@ static void i915_error_work_func(struct work_struct *work) · 12 unmodified lines
1506	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,	1533	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1507	reset_event);	1534	reset_event);
1508		1535
		1536	/*
		1537	* All state reset _must_ be completed before we update the
		1538	* reset counter, for otherwise waiters might miss the reset
		1539	* pending state and not properly drop locks, resulting in
		1540	* deadlocks with the reset work.
		1541	*/
1509	ret = i915_reset(dev);	1542	ret = i915_reset(dev);
1510		1543
		1544	intel_display_handle_reset(dev);
		1545
1511	if (ret == 0) {	1546	if (ret == 0) {
1512	/*	1547	/*
1513	* After all the gem state is reset, increment the reset	1548	* After all the gem state is reset, increment the reset
@@ -1528,12 +1563,11 @@ static void i915_error_work_func(struct work_struct *work) · 14 unmodified lines
1528	atomic_set(&error->reset_counter, I915_WEDGED);	1563	atomic_set(&error->reset_counter, I915_WEDGED);
1529	}	1564	}
1530		1565
1531	for_each_ring(ring, dev_priv, i)	1566	/*
1532	wake_up_all(&ring->irq_queue);	1567	* Note: The wake_up also serves as a memory barrier so that
1533		1568	* waiters see the update value of the reset counter atomic_t.
1534	intel_display_handle_reset(dev);	1569	*/
1535		1570	i915_error_wake_up(dev_priv, true);
1536	wake_up_all(&dev_priv->gpu_error.reset_queue);
1537	}	1571	}
1538	}	1572	}
1539		1573
@@ -1642,8 +1676,6 @@ static void i915_report_and_clear_eir(struct drm_device *dev) · 102 unmodified lines
1642	void i915_handle_error(struct drm_device *dev, bool wedged)	1676	void i915_handle_error(struct drm_device *dev, bool wedged)
1643	{	1677	{
1644	struct drm_i915_private *dev_priv = dev->dev_private;	1678	struct drm_i915_private *dev_priv = dev->dev_private;
1645	struct intel_ring_buffer *ring;
1646	int i;
1647		1679
1648	i915_capture_error_state(dev);	1680	i915_capture_error_state(dev);
1649	i915_report_and_clear_eir(dev);	1681	i915_report_and_clear_eir(dev);
@@ -1653,11 +1685,19 @@ void i915_handle_error(struct drm_device *dev, bool wedged) · 3 unmodified lines
1653	&dev_priv->gpu_error.reset_counter);	1685	&dev_priv->gpu_error.reset_counter);
1654		1686
1655	/*	1687	/*
1656	* Wakeup waiting processes so that the reset work item	1688	* Wakeup waiting processes so that the reset work function
1657	* doesn't deadlock trying to grab various locks.	1689	* i915_error_work_func doesn't deadlock trying to grab various
		1690	* locks. By bumping the reset counter first, the woken
		1691	* processes will see a reset in progress and back off,
		1692	* releasing their locks and then wait for the reset completion.
		1693	* We must do this for _all_ gpu waiters that might hold locks
		1694	* that the reset work needs to acquire.
		1695	*
		1696	* Note: The wake_up serves as the required memory barrier to
		1697	* ensure that the waiters see the updated value of the reset
		1698	* counter atomic_t.
1658	*/	1699	*/
1659	for_each_ring(ring, dev_priv, i)	1700	i915_error_wake_up(dev_priv, false);
1660	wake_up_all(&ring->irq_queue);
1661	}	1701	}
1662		1702
1663	/*	1703	/*

drivers/gpu/drm/i915/intel_ddi.c+1−1

@@ -778,7 +778,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) · 777 unmodified lines
778	/* Can only use the always-on power well for eDP when	778	/* Can only use the always-on power well for eDP when
779	* not using the panel fitter, and when not using motion	779	* not using the panel fitter, and when not using motion
780	* blur mitigation (which we don't support). */	780	* blur mitigation (which we don't support). */
781	if (intel_crtc->config.pch_pfit.size)	781	if (intel_crtc->config.pch_pfit.enabled)
782	temp \|= TRANS_DDI_EDP_INPUT_A_ONOFF;	782	temp \|= TRANS_DDI_EDP_INPUT_A_ONOFF;
783	else	783	else
784	temp \|= TRANS_DDI_EDP_INPUT_A_ON;	784	temp \|= TRANS_DDI_EDP_INPUT_A_ON;

drivers/gpu/drm/i915/intel_display.c+24−22

 		I915_WRITE(PIPESRC(intel_crtc->pipe),
 			   ((crtc->mode.hdisplay - 1) << 16) |
 			   (crtc->mode.vdisplay - 1));
-		if (!intel_crtc->config.pch_pfit.size &&
+		if (!intel_crtc->config.pch_pfit.enabled &&
 		    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
 		     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
 			I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = crtc->pipe;
-	if (crtc->config.pch_pfit.size) {
+	if (crtc->config.pch_pfit.enabled) {
 		/* Force use of hard-coded filter coefficients
 		 * as some pre-programmed values are broken,
 		 * e.g. x201.
 	/* To avoid upsetting the power well on haswell only disable the pfit if
 	 * it's in use. The hw state code will make sure we get this right. */
-	if (crtc->config.pch_pfit.size) {
+	if (crtc->config.pch_pfit.enabled) {
 		I915_WRITE(PF_CTL(pipe), 0);
 		I915_WRITE(PF_WIN_POS(pipe), 0);
 		I915_WRITE(PF_WIN_SZ(pipe), 0);
 	pipeconf = 0;
+	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
+	    I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
+		pipeconf |= PIPECONF_ENABLE;
 	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
 		/* Enable pixel doubling when the dot clock is > 90% of the (display)
 		 * core speed.
 		return -EINVAL;
 	}
-	/* Ensure that the cursor is valid for the new mode before changing... */
-	intel_crtc_update_cursor(crtc, true);
 	if (is_lvds && dev_priv->lvds_downclock_avail) {
 		/*
 		 * Ensure we match the reduced clock's P to the target clock.
 		intel_crtc->config.dpll.p2 = clock.p2;
 	}
-	/* Ensure that the cursor is valid for the new mode before changing... */
-	intel_crtc_update_cursor(crtc, true);
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
 	if (intel_crtc->config.has_pch_encoder) {
 		fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
 	tmp = I915_READ(PF_CTL(crtc->pipe));
 	if (tmp & PF_ENABLE) {
+		pipe_config->pch_pfit.enabled = true;
 		pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
 		pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
 		if (!crtc->base.enabled)
 			continue;
-		if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
+		if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
 		    crtc->config.cpu_transcoder != TRANSCODER_EDP)
 			enable = true;
 	}
 	if (!intel_ddi_pll_mode_set(crtc))
 		return -EINVAL;
-	/* Ensure that the cursor is valid for the new mode before changing... */
-	intel_crtc_update_cursor(crtc, true);
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 	/* Set ELD valid state */
 	tmp = I915_READ(aud_cntrl_st2);
-	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
+	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
 	tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
 	I915_WRITE(aud_cntrl_st2, tmp);
 	tmp = I915_READ(aud_cntrl_st2);
-	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
+	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
 	/* Enable HDMI mode */
 	tmp = I915_READ(aud_config);
-	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
+	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
 	/* clear N_programing_enable and N_value_index */
 	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
 	I915_WRITE(aud_config, tmp);
 	intel_crtc->cursor_width = width;
 	intel_crtc->cursor_height = height;
-	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
+	if (intel_crtc->active)
+		intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
 	return 0;
 fail_unpin:
 	intel_crtc->cursor_x = x;
 	intel_crtc->cursor_y = y;
-	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
+	if (intel_crtc->active)
+		intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
 	return 0;
 }
 		      pipe_config->gmch_pfit.control,
 		      pipe_config->gmch_pfit.pgm_ratios,
 		      pipe_config->gmch_pfit.lvds_border_bits);
-	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
+	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
 		      pipe_config->pch_pfit.pos,
-		      pipe_config->pch_pfit.size);
+		      pipe_config->pch_pfit.size,
+		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
 	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
 }
 	if (INTEL_INFO(dev)->gen < 4)
 		PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
 	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
-	PIPE_CONF_CHECK_I(pch_pfit.pos);
+	PIPE_CONF_CHECK_I(pch_pfit.enabled);
-	PIPE_CONF_CHECK_I(pch_pfit.size);
+	if (current_config->pch_pfit.enabled) {
+		PIPE_CONF_CHECK_I(pch_pfit.pos);
+		PIPE_CONF_CHECK_I(pch_pfit.size);
+	}
 	PIPE_CONF_CHECK_I(ips_enabled);

drivers/gpu/drm/i915/intel_dp.c+12−1

@@ -588,7 +588,18 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, · 587 unmodified lines
588	DRM_DEBUG_KMS("aux_ch native nack\n");	588	DRM_DEBUG_KMS("aux_ch native nack\n");
589	return -EREMOTEIO;	589	return -EREMOTEIO;
590	case AUX_NATIVE_REPLY_DEFER:	590	case AUX_NATIVE_REPLY_DEFER:
591	udelay(100);	591	/*
		592	* For now, just give more slack to branch devices. We
		593	* could check the DPCD for I2C bit rate capabilities,
		594	* and if available, adjust the interval. We could also
		595	* be more careful with DP-to-Legacy adapters where a
		596	* long legacy cable may force very low I2C bit rates.
		597	*/
		598	if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
		599	DP_DWN_STRM_PORT_PRESENT)
		600	usleep_range(500, 600);
		601	else
		602	usleep_range(300, 400);
592	continue;	603	continue;
593	default:	604	default:
594	DRM_ERROR("aux_ch invalid native reply 0x%02x\n",	605	DRM_ERROR("aux_ch invalid native reply 0x%02x\n",

drivers/gpu/drm/i915/intel_drv.h+1−0

@@ -280,6 +280,7 @@ struct intel_crtc_config { · 279 unmodified lines
280	struct {	280	struct {
281	u32 pos;	281	u32 pos;
282	u32 size;	282	u32 size;
		283	bool enabled;
283	} pch_pfit;	284	} pch_pfit;
284		285
285	/* FDI configuration, only valid if has_pch_encoder is set. */	286	/* FDI configuration, only valid if has_pch_encoder is set. */

drivers/gpu/drm/i915/intel_dvo.c+2−0

@@ -263,6 +263,8 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder, · 262 unmodified lines
263	C(vtotal);	263	C(vtotal);
264	C(clock);	264	C(clock);
265	#undef C	265	#undef C
		266
		267	drm_mode_set_crtcinfo(adjusted_mode, 0);
266	}	268	}
267		269
268	if (intel_dvo->dev.dev_ops->mode_fixup)	270	if (intel_dvo->dev.dev_ops->mode_fixup)

drivers/gpu/drm/i915/intel_panel.c+1−0

@@ -112,6 +112,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc, · 111 unmodified lines
112	done:	112	done:
113	pipe_config->pch_pfit.pos = (x << 16) \| y;	113	pipe_config->pch_pfit.pos = (x << 16) \| y;
114	pipe_config->pch_pfit.size = (width << 16) \| height;	114	pipe_config->pch_pfit.size = (width << 16) \| height;
		115	pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
115	}	116	}
116		117
117	static void	118	static void

drivers/gpu/drm/i915/intel_pm.c+3−3

 				    struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	uint32_t pixel_rate, pfit_size;
+	uint32_t pixel_rate;
 	pixel_rate = intel_crtc->config.adjusted_mode.clock;
 	/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
 	 * adjust the pixel_rate here. */
-	pfit_size = intel_crtc->config.pch_pfit.size;
+	if (intel_crtc->config.pch_pfit.enabled) {
-	if (pfit_size) {
 		uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
+		uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
 		pipe_w = intel_crtc->config.requested_mode.hdisplay;
 		pipe_h = intel_crtc->config.requested_mode.vdisplay;

drivers/gpu/drm/i915/intel_sdvo.c+36−27

@@ -788,6 +788,8 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, · 787 unmodified lines
788	uint16_t h_sync_offset, v_sync_offset;	788	uint16_t h_sync_offset, v_sync_offset;
789	int mode_clock;	789	int mode_clock;
790		790
		791	memset(dtd, 0, sizeof(*dtd));
		792
791	width = mode->hdisplay;	793	width = mode->hdisplay;
792	height = mode->vdisplay;	794	height = mode->vdisplay;
793		795
@@ -830,44 +832,51 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, · 36 unmodified lines
830	if (mode->flags & DRM_MODE_FLAG_PVSYNC)	832	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
831	dtd->part2.dtd_flags \|= DTD_FLAG_VSYNC_POSITIVE;	833	dtd->part2.dtd_flags \|= DTD_FLAG_VSYNC_POSITIVE;
832		834
833	dtd->part2.sdvo_flags = 0;
834	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;	835	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
835	dtd->part2.reserved = 0;
836	}	836	}
837		837
838	static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,	838	static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
839	const struct intel_sdvo_dtd *dtd)	839	const struct intel_sdvo_dtd *dtd)
840	{	840	{
841	mode->hdisplay = dtd->part1.h_active;	841	struct drm_display_mode mode = {};
842	mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;	842
843	mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;	843	mode.hdisplay = dtd->part1.h_active;
844	mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;	844	mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
845	mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;	845	mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
846	mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;	846	mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
847	mode->htotal = mode->hdisplay + dtd->part1.h_blank;	847	mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
848	mode->htotal += (dtd->part1.h_high & 0xf) << 8;	848	mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
849		849	mode.htotal = mode.hdisplay + dtd->part1.h_blank;
850	mode->vdisplay = dtd->part1.v_active;	850	mode.htotal += (dtd->part1.h_high & 0xf) << 8;
851	mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;	851
852	mode->vsync_start = mode->vdisplay;	852	mode.vdisplay = dtd->part1.v_active;
853	mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;	853	mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
854	mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;	854	mode.vsync_start = mode.vdisplay;
855	mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;	855	mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
856	mode->vsync_end = mode->vsync_start +	856	mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
		857	mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
		858	mode.vsync_end = mode.vsync_start +
857	(dtd->part2.v_sync_off_width & 0xf);	859	(dtd->part2.v_sync_off_width & 0xf);
858	mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;	860	mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
859	mode->vtotal = mode->vdisplay + dtd->part1.v_blank;	861	mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
860	mode->vtotal += (dtd->part1.v_high & 0xf) << 8;	862	mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
861		863
862	mode->clock = dtd->part1.clock * 10;	864	mode.clock = dtd->part1.clock * 10;
863		865
864	mode->flags &= ~(DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC);
865	if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)	866	if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
866	mode->flags \|= DRM_MODE_FLAG_INTERLACE;	867	mode.flags \|= DRM_MODE_FLAG_INTERLACE;
867	if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)	868	if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
868	mode->flags \|= DRM_MODE_FLAG_PHSYNC;	869	mode.flags \|= DRM_MODE_FLAG_PHSYNC;
		870	else
		871	mode.flags \|= DRM_MODE_FLAG_NHSYNC;
869	if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)	872	if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
870	mode->flags \|= DRM_MODE_FLAG_PVSYNC;	873	mode.flags \|= DRM_MODE_FLAG_PVSYNC;
		874	else
		875	mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		876
		877	drm_mode_set_crtcinfo(&mode, 0);
		878
		879	drm_mode_copy(pmode, &mode);
871	}	880	}
872		881
873	static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)	882	static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)

drivers/gpu/drm/i915/intel_tv.c+8−0

@@ -916,6 +916,14 @@ intel_tv_compute_config(struct intel_encoder *encoder, · 915 unmodified lines
916	DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");	916	DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
917	pipe_config->pipe_bpp = 8*3;	917	pipe_config->pipe_bpp = 8*3;
918		918
		919	/* TV has it's own notion of sync and other mode flags, so clear them. */
		920	pipe_config->adjusted_mode.flags = 0;
		921
		922	/*
		923	* FIXME: We don't check whether the input mode is actually what we want
		924	* or whether userspace is doing something stupid.
		925	*/
		926
919	return true;	927	return true;
920	}	928	}
921		929

drivers/gpu/drm/msm/adreno/adreno_gpu.c+9−1

 	/* reset completed fence seqno, just discard anything pending: */
 	adreno_gpu->memptrs->fence = gpu->submitted_fence;
+	adreno_gpu->memptrs->rptr  = 0;
+	adreno_gpu->memptrs->wptr  = 0;
 	gpu->funcs->pm_resume(gpu);
 	ret = gpu->funcs->hw_init(gpu);
 			return;
 	} while(time_before(jiffies, t));
-	DRM_ERROR("timeout waiting for %s to drain ringbuffer!\n", gpu->name);
+	DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
 	/* TODO maybe we need to reset GPU here to recover from hang? */
 }
 {
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 	uint32_t freedwords;
+	unsigned long t = jiffies + ADRENO_IDLE_TIMEOUT;
 	do {
 		uint32_t size = gpu->rb->size / 4;
 		uint32_t wptr = get_wptr(gpu->rb);
 		uint32_t rptr = adreno_gpu->memptrs->rptr;
 		freedwords = (rptr + (size - 1) - wptr) % size;
+		if (time_after(jiffies, t)) {
+			DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
+			break;
+		}
 	} while(freedwords < ndwords);
 }

drivers/gpu/drm/msm/mdp4/mdp4_kms.c+0−2

@@ -19,8 +19,6 @@ · 18 unmodified lines
19	#include "msm_drv.h"	19	#include "msm_drv.h"
20	#include "mdp4_kms.h"	20	#include "mdp4_kms.h"
21		21
22	#include <mach/iommu.h>
23
24	static struct mdp4_platform_config mdp4_get_config(struct platform_device dev);	22	static struct mdp4_platform_config mdp4_get_config(struct platform_device dev);
25		23
26	static int mdp4_hw_init(struct msm_kms *kms)	24	static int mdp4_hw_init(struct msm_kms *kms)

drivers/gpu/drm/msm/msm_drv.c+37−21

@@ -18,8 +18,6 @@ · 17 unmodified lines
18	#include "msm_drv.h"	18	#include "msm_drv.h"
19	#include "msm_gpu.h"	19	#include "msm_gpu.h"
20		20
21	#include <mach/iommu.h>
22
23	static void msm_fb_output_poll_changed(struct drm_device *dev)	21	static void msm_fb_output_poll_changed(struct drm_device *dev)
24	{	22	{
25	struct msm_drm_private *priv = dev->dev_private;	23	struct msm_drm_private *priv = dev->dev_private;
@@ -62,6 +60,8 @@ int msm_iommu_attach(struct drm_device dev, struct iommu_domain iommu, · 36 unmodified lines
62	int i, ret;	60	int i, ret;
63		61
64	for (i = 0; i < cnt; i++) {	62	for (i = 0; i < cnt; i++) {
		63	/* TODO maybe some day msm iommu won't require this hack: */
		64	struct device msm_iommu_get_ctx(const char ctx_name);
65	struct device *ctx = msm_iommu_get_ctx(names[i]);	65	struct device *ctx = msm_iommu_get_ctx(names[i]);
66	if (!ctx)	66	if (!ctx)
67	continue;	67	continue;
@@ -199,7 +199,7 @@ static int msm_load(struct drm_device *dev, unsigned long flags) · 131 unmodified lines
199	* imx drm driver on iMX5	199	* imx drm driver on iMX5
200	*/	200	*/
201	dev_err(dev->dev, "failed to load kms\n");	201	dev_err(dev->dev, "failed to load kms\n");
202	ret = PTR_ERR(priv->kms);	202	ret = PTR_ERR(kms);
203	goto fail;	203	goto fail;
204	}	204	}
205		205
@@ -499,25 +499,41 @@ int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, · 293 unmodified lines
499	struct timespec *timeout)	499	struct timespec *timeout)
500	{	500	{
501	struct msm_drm_private *priv = dev->dev_private;	501	struct msm_drm_private *priv = dev->dev_private;
502	unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
503	unsigned long start_jiffies = jiffies;
504	unsigned long remaining_jiffies;
505	int ret;	502	int ret;
506		503
507	if (time_after(start_jiffies, timeout_jiffies))	504	if (!priv->gpu)
508	remaining_jiffies = 0;	505	return 0;
509	else	506
510	remaining_jiffies = timeout_jiffies - start_jiffies;	507	if (fence > priv->gpu->submitted_fence) {
511		508	DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
512	ret = wait_event_interruptible_timeout(priv->fence_event,	509	fence, priv->gpu->submitted_fence);
513	priv->completed_fence >= fence,	510	return -EINVAL;
514	remaining_jiffies);	511	}
515	if (ret == 0) {	512
516	DBG("timeout waiting for fence: %u (completed: %u)",	513	if (!timeout) {
517	fence, priv->completed_fence);	514	/* no-wait: */
518	ret = -ETIMEDOUT;	515	ret = fence_completed(dev, fence) ? 0 : -EBUSY;
519	} else if (ret != -ERESTARTSYS) {	516	} else {
520	ret = 0;	517	unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
		518	unsigned long start_jiffies = jiffies;
		519	unsigned long remaining_jiffies;
		520
		521	if (time_after(start_jiffies, timeout_jiffies))
		522	remaining_jiffies = 0;
		523	else
		524	remaining_jiffies = timeout_jiffies - start_jiffies;
		525
		526	ret = wait_event_interruptible_timeout(priv->fence_event,
		527	fence_completed(dev, fence),
		528	remaining_jiffies);
		529
		530	if (ret == 0) {
		531	DBG("timeout waiting for fence: %u (completed: %u)",
		532	fence, priv->completed_fence);
		533	ret = -ETIMEDOUT;
		534	} else if (ret != -ERESTARTSYS) {
		535	ret = 0;
		536	}
521	}	537	}
522		538
523	return ret;	539	return ret;
@@ -681,7 +697,7 @@ static struct drm_driver msm_driver = { · 157 unmodified lines
681	.gem_vm_ops = &vm_ops,	697	.gem_vm_ops = &vm_ops,
682	.dumb_create = msm_gem_dumb_create,	698	.dumb_create = msm_gem_dumb_create,
683	.dumb_map_offset = msm_gem_dumb_map_offset,	699	.dumb_map_offset = msm_gem_dumb_map_offset,
684	.dumb_destroy = msm_gem_dumb_destroy,	700	.dumb_destroy = drm_gem_dumb_destroy,
685	#ifdef CONFIG_DEBUG_FS	701	#ifdef CONFIG_DEBUG_FS
686	.debugfs_init = msm_debugfs_init,	702	.debugfs_init = msm_debugfs_init,
687	.debugfs_cleanup = msm_debugfs_cleanup,	703	.debugfs_cleanup = msm_debugfs_cleanup,

drivers/gpu/drm/msm/msm_drv.h+7−1

 int msm_gem_queue_inactive_work(struct drm_gem_object *obj,
 		struct work_struct *work);
 void msm_gem_move_to_active(struct drm_gem_object *obj,
-		struct msm_gpu *gpu, uint32_t fence);
+		struct msm_gpu *gpu, bool write, uint32_t fence);
 void msm_gem_move_to_inactive(struct drm_gem_object *obj);
 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
 		struct timespec *timeout);
 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
+static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
+{
+	struct msm_drm_private *priv = dev->dev_private;
+	return priv->completed_fence >= fence;
+}
 static inline int align_pitch(int width, int bpp)
 {
 	int bytespp = (bpp + 7) / 8;

drivers/gpu/drm/msm/msm_gem.c+24−17

 		}
 		msm_obj->sgt = drm_prime_pages_to_sg(p, npages);
-		if (!msm_obj->sgt) {
+		if (IS_ERR(msm_obj->sgt)) {
 			dev_err(dev->dev, "failed to allocate sgt\n");
-			return ERR_PTR(-ENOMEM);
+			return ERR_CAST(msm_obj->sgt);
 		}
 		msm_obj->pages = p;
 out:
 	switch (ret) {
 	case -EAGAIN:
-		set_need_resched();
 	case 0:
 	case -ERESTARTSYS:
 	case -EINTR:
 			MSM_BO_SCANOUT | MSM_BO_WC, &args->handle);
 }
-int msm_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
-		uint32_t handle)
-{
-	/* No special work needed, drop the reference and see what falls out */
-	return drm_gem_handle_delete(file, handle);
-}
 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
 		uint32_t handle, uint64_t *offset)
 {
 }
 void msm_gem_move_to_active(struct drm_gem_object *obj,
-		struct msm_gpu *gpu, uint32_t fence)
+		struct msm_gpu *gpu, bool write, uint32_t fence)
 {
 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
 	msm_obj->gpu = gpu;
-	msm_obj->fence = fence;
+	if (write)
+		msm_obj->write_fence = fence;
+	else
+		msm_obj->read_fence = fence;
 	list_del_init(&msm_obj->mm_list);
 	list_add_tail(&msm_obj->mm_list, &gpu->active_list);
 }
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 	msm_obj->gpu = NULL;
-	msm_obj->fence = 0;
+	msm_obj->read_fence = 0;
+	msm_obj->write_fence = 0;
 	list_del_init(&msm_obj->mm_list);
 	list_add_tail(&msm_obj->mm_list, &priv->inactive_list);
 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
 	int ret = 0;
-	if (is_active(msm_obj) && !(op & MSM_PREP_NOSYNC))
+	if (is_active(msm_obj)) {
-		ret = msm_wait_fence_interruptable(dev, msm_obj->fence, timeout);
+		uint32_t fence = 0;
+		if (op & MSM_PREP_READ)
+			fence = msm_obj->write_fence;
+		if (op & MSM_PREP_WRITE)
+			fence = max(fence, msm_obj->read_fence);
+		if (op & MSM_PREP_NOSYNC)
+			timeout = NULL;
+		ret = msm_wait_fence_interruptable(dev, fence, timeout);
+	}
 	/* TODO cache maintenance */
 	uint64_t off = drm_vma_node_start(&obj->vma_node);
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
-	seq_printf(m, "%08x: %c(%d) %2d (%2d) %08llx %p %d\n",
+	seq_printf(m, "%08x: %c(r=%u,w=%u) %2d (%2d) %08llx %p %d\n",
 			msm_obj->flags, is_active(msm_obj) ? 'A' : 'I',
-			msm_obj->fence, obj->name, obj->refcount.refcount.counter,
+			msm_obj->read_fence, msm_obj->write_fence,
+			obj->name, obj->refcount.refcount.counter,
 			off, msm_obj->vaddr, obj->size);
 }

drivers/gpu/drm/msm/msm_gem.h+1−1

@@ -36,7 +36,7 @@ struct msm_gem_object { · 35 unmodified lines
36	*/	36	*/
37	struct list_head mm_list;	37	struct list_head mm_list;
38	struct msm_gpu gpu; / non-null if active */	38	struct msm_gpu gpu; / non-null if active */
39	uint32_t fence;	39	uint32_t read_fence, write_fence;
40		40
41	/* Transiently in the process of submit ioctl, objects associated	41	/* Transiently in the process of submit ioctl, objects associated
42	* with the submit are on submit->bo_list.. this only lasts for	42	* with the submit are on submit->bo_list.. this only lasts for

drivers/gpu/drm/msm/msm_gem_submit.c+13−11

 		}
 		if (submit_bo.flags & BO_INVALID_FLAGS) {
-			DBG("invalid flags: %x", submit_bo.flags);
+			DRM_ERROR("invalid flags: %x\n", submit_bo.flags);
 			ret = -EINVAL;
 			goto out_unlock;
 		}
 		 */
 		obj = idr_find(&file->object_idr, submit_bo.handle);
 		if (!obj) {
-			DBG("invalid handle %u at index %u", submit_bo.handle, i);
+			DRM_ERROR("invalid handle %u at index %u\n", submit_bo.handle, i);
 			ret = -EINVAL;
 			goto out_unlock;
 		}
 		msm_obj = to_msm_bo(obj);
 		if (!list_empty(&msm_obj->submit_entry)) {
-			DBG("handle %u at index %u already on submit list",
+			DRM_ERROR("handle %u at index %u already on submit list\n",
 					submit_bo.handle, i);
 			ret = -EINVAL;
 			goto out_unlock;
 		struct msm_gem_object **obj, uint32_t *iova, bool *valid)
 {
 	if (idx >= submit->nr_bos) {
-		DBG("invalid buffer index: %u (out of %u)", idx, submit->nr_bos);
+		DRM_ERROR("invalid buffer index: %u (out of %u)\n",
-		return EINVAL;
+				idx, submit->nr_bos);
+		return -EINVAL;
 	}
 	if (obj)
 	int ret;
 	if (offset % 4) {
-		DBG("non-aligned cmdstream buffer: %u", offset);
+		DRM_ERROR("non-aligned cmdstream buffer: %u\n", offset);
 		return -EINVAL;
 	}
 			return -EFAULT;
 		if (submit_reloc.submit_offset % 4) {
-			DBG("non-aligned reloc offset: %u",
+			DRM_ERROR("non-aligned reloc offset: %u\n",
 					submit_reloc.submit_offset);
 			return -EINVAL;
 		}
 		if ((off >= (obj->base.size / 4)) ||
 				(off < last_offset)) {
-			DBG("invalid offset %u at reloc %u", off, i);
+			DRM_ERROR("invalid offset %u at reloc %u\n", off, i);
 			return -EINVAL;
 		}
 			goto out;
 		if (submit_cmd.size % 4) {
-			DBG("non-aligned cmdstream buffer size: %u",
+			DRM_ERROR("non-aligned cmdstream buffer size: %u\n",
 					submit_cmd.size);
 			ret = -EINVAL;
 			goto out;
 		}
-		if (submit_cmd.size >= msm_obj->base.size) {
+		if ((submit_cmd.size + submit_cmd.submit_offset) >=
-			DBG("invalid cmdstream size: %u", submit_cmd.size);
+				msm_obj->base.size) {
+			DRM_ERROR("invalid cmdstream size: %u\n", submit_cmd.size);
 			ret = -EINVAL;
 			goto out;
 		}

drivers/gpu/drm/msm/msm_gpu.c+20−4

 static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev)
 {
 	struct drm_device *dev = gpu->dev;
-	struct kgsl_device_platform_data *pdata = pdev->dev.platform_data;
+	struct kgsl_device_platform_data *pdata;
 	if (!pdev) {
 		dev_err(dev->dev, "could not find dtv pdata\n");
 		return;
 	}
+	pdata = pdev->dev.platform_data;
 	if (pdata->bus_scale_table) {
 		gpu->bsc = msm_bus_scale_register_client(pdata->bus_scale_table);
 		DBG("bus scale client: %08x", gpu->bsc);
 static void hangcheck_handler(unsigned long data)
 {
 	struct msm_gpu *gpu = (struct msm_gpu *)data;
+	struct drm_device *dev = gpu->dev;
+	struct msm_drm_private *priv = dev->dev_private;
 	uint32_t fence = gpu->funcs->last_fence(gpu);
 	if (fence != gpu->hangcheck_fence) {
 		gpu->hangcheck_fence = fence;
 	} else if (fence < gpu->submitted_fence) {
 		/* no progress and not done.. hung! */
-		struct msm_drm_private *priv = gpu->dev->dev_private;
 		gpu->hangcheck_fence = fence;
+		dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
+				gpu->name);
+		dev_err(dev->dev, "%s:     completed fence: %u\n",
+				gpu->name, fence);
+		dev_err(dev->dev, "%s:     submitted fence: %u\n",
+				gpu->name, gpu->submitted_fence);
 		queue_work(priv->wq, &gpu->recover_work);
 	}
 	/* if still more pending work, reset the hangcheck timer: */
 	if (gpu->submitted_fence > gpu->hangcheck_fence)
 		hangcheck_timer_reset(gpu);
+	/* workaround for missing irq: */
+	queue_work(priv->wq, &gpu->retire_work);
 }
 /*
 		obj = list_first_entry(&gpu->active_list,
 				struct msm_gem_object, mm_list);
-		if (obj->fence <= fence) {
+		if ((obj->read_fence <= fence) &&
+				(obj->write_fence <= fence)) {
 			/* move to inactive: */
 			msm_gem_move_to_inactive(&obj->base);
 			msm_gem_put_iova(&obj->base, gpu->id);
 					submit->gpu->id, &iova);
 		}
-		msm_gem_move_to_active(&msm_obj->base, gpu, submit->fence);
+		if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
+			msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
+		if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
+			msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
 	}
 	hangcheck_timer_reset(gpu);
 	mutex_unlock(&dev->struct_mutex);

drivers/gpu/drm/nouveau/core/subdev/bios/init.c+18−3

@@ -579,8 +579,22 @@ static void · 578 unmodified lines
579	init_reserved(struct nvbios_init *init)	579	init_reserved(struct nvbios_init *init)
580	{	580	{
581	u8 opcode = nv_ro08(init->bios, init->offset);	581	u8 opcode = nv_ro08(init->bios, init->offset);
582	trace("RESERVED\t0x%02x\n", opcode);	582	u8 length, i;
583	init->offset += 1;	583
		584	switch (opcode) {
		585	case 0xaa:
		586	length = 4;
		587	break;
		588	default:
		589	length = 1;
		590	break;
		591	}
		592
		593	trace("RESERVED 0x%02x\t", opcode);
		594	for (i = 1; i < length; i++)
		595	cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
		596	cont("\n");
		597	init->offset += length;
584	}	598	}
585		599
586	/**	600	/**
@@ -1437,7 +1451,7 @@ init_configure_mem(struct nvbios_init *init) · 850 unmodified lines
1437	data = init_rdvgai(init, 0x03c4, 0x01);	1451	data = init_rdvgai(init, 0x03c4, 0x01);
1438	init_wrvgai(init, 0x03c4, 0x01, data \| 0x20);	1452	init_wrvgai(init, 0x03c4, 0x01, data \| 0x20);
1439		1453
1440	while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {	1454	for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1441	switch (addr) {	1455	switch (addr) {
1442	case 0x10021c: /* CKE_NORMAL */	1456	case 0x10021c: /* CKE_NORMAL */
1443	case 0x1002d0: /* CMD_REFRESH */	1457	case 0x1002d0: /* CMD_REFRESH */
@@ -2135,6 +2149,7 @@ static struct nvbios_init_opcode { · 691 unmodified lines
2135	[0x99] = { init_zm_auxch },	2149	[0x99] = { init_zm_auxch },
2136	[0x9a] = { init_i2c_long_if },	2150	[0x9a] = { init_i2c_long_if },
2137	[0xa9] = { init_gpio_ne },	2151	[0xa9] = { init_gpio_ne },
		2152	[0xaa] = { init_reserved },
2138	};	2153	};
2139		2154
2140	#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))	2155	#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))

drivers/gpu/drm/nouveau/nouveau_display.c+15−20

 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_display *disp;
-	u32 pclass = dev->pdev->class >> 8;
 	int ret, gen;
 	disp = drm->display = kzalloc(sizeof(*disp), GFP_KERNEL);
 	drm_kms_helper_poll_init(dev);
 	drm_kms_helper_poll_disable(dev);
-	if (nouveau_modeset == 1 ||
+	if (drm->vbios.dcb.entries) {
-	    (nouveau_modeset < 0 && pclass == PCI_CLASS_DISPLAY_VGA)) {
+		if (nv_device(drm->device)->card_type < NV_50)
-		if (drm->vbios.dcb.entries) {
+			ret = nv04_display_create(dev);
-			if (nv_device(drm->device)->card_type < NV_50)
+		else
-				ret = nv04_display_create(dev);
+			ret = nv50_display_create(dev);
-			else
+	} else {
-				ret = nv50_display_create(dev);
+		ret = 0;
-		} else {
+	}
-			ret = 0;
-		}
-		if (ret)
-			goto disp_create_err;
-		if (dev->mode_config.num_crtc) {
+	if (ret)
-			ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
+		goto disp_create_err;
-			if (ret)
-				goto vblank_err;
-		}
-		nouveau_backlight_init(dev);
+	if (dev->mode_config.num_crtc) {
+		ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
+		if (ret)
+			goto vblank_err;
 	}
+	nouveau_backlight_init(dev);
 	return 0;
 vblank_err:

drivers/gpu/drm/nouveau/nouveau_fbcon.c+2−1

@@ -454,7 +454,8 @@ nouveau_fbcon_init(struct drm_device *dev) · 453 unmodified lines
454	int preferred_bpp;	454	int preferred_bpp;
455	int ret;	455	int ret;
456		456
457	if (!dev->mode_config.num_crtc)	457	if (!dev->mode_config.num_crtc \|\|
		458	(dev->pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
458	return 0;	459	return 0;
459		460
460	fbcon = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL);	461	fbcon = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL);

drivers/gpu/drm/nouveau/nouveau_sgdma.c+1−3

 	else
 		nvbe->ttm.ttm.func = &nv50_sgdma_backend;
-	if (ttm_dma_tt_init(&nvbe->ttm, bdev, size, page_flags, dummy_read_page)) {
+	if (ttm_dma_tt_init(&nvbe->ttm, bdev, size, page_flags, dummy_read_page))
-		kfree(nvbe);
 		return NULL;
-	}
 	return &nvbe->ttm.ttm;
 }

drivers/gpu/drm/radeon/atombios_encoders.c+15−8

 	switch (connector->connector_type) {
 	case DRM_MODE_CONNECTOR_DVII:
 	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
-		if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+		if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
-		    radeon_audio)
+		    (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+		     (radeon_connector->audio == RADEON_AUDIO_AUTO)))
 			return ATOM_ENCODER_MODE_HDMI;
 		else if (radeon_connector->use_digital)
 			return ATOM_ENCODER_MODE_DVI;
 	case DRM_MODE_CONNECTOR_DVID:
 	case DRM_MODE_CONNECTOR_HDMIA:
 	default:
-		if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+		if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
-		    radeon_audio)
+		    (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+		     (radeon_connector->audio == RADEON_AUDIO_AUTO)))
 			return ATOM_ENCODER_MODE_HDMI;
 		else
 			return ATOM_ENCODER_MODE_DVI;
 		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 			return ATOM_ENCODER_MODE_DP;
-		else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+		else if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
-			 radeon_audio)
+			 (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+			  (radeon_connector->audio == RADEON_AUDIO_AUTO)))
 			return ATOM_ENCODER_MODE_HDMI;
 		else
 			return ATOM_ENCODER_MODE_DVI;
 			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
-			/* some early dce3.2 boards have a bug in their transmitter control table */
+			/* some dce3.x boards have a bug in their transmitter control table.
-			if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
+			 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
+			 * does the same thing and more.
+			 */
+			if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
+			    (rdev->family != CHIP_RS880))
 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
 		}
 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {

drivers/gpu/drm/radeon/btc_dpm.c+51−6

@@ -1168,6 +1168,23 @@ static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = · 1167 unmodified lines
1168	{ 25000, 30000, RADEON_SCLK_UP }	1168	{ 25000, 30000, RADEON_SCLK_UP }
1169	};	1169	};
1170		1170
		1171	void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
		1172	u32 *max_clock)
		1173	{
		1174	u32 i, clock = 0;
		1175
		1176	if ((table == NULL) \|\| (table->count == 0)) {
		1177	*max_clock = clock;
		1178	return;
		1179	}
		1180
		1181	for (i = 0; i < table->count; i++) {
		1182	if (clock < table->entries[i].clk)
		1183	clock = table->entries[i].clk;
		1184	}
		1185	*max_clock = clock;
		1186	}
		1187
1171	void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,	1188	void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
1172	u32 clock, u16 max_voltage, u16 *voltage)	1189	u32 clock, u16 max_voltage, u16 *voltage)
1173	{	1190	{
@@ -2080,6 +2097,7 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, · 906 unmodified lines
2080	bool disable_mclk_switching;	2097	bool disable_mclk_switching;
2081	u32 mclk, sclk;	2098	u32 mclk, sclk;
2082	u16 vddc, vddci;	2099	u16 vddc, vddci;
		2100	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2083		2101
2084	if ((rdev->pm.dpm.new_active_crtc_count > 1) \|\|	2102	if ((rdev->pm.dpm.new_active_crtc_count > 1) \|\|
2085	btc_dpm_vblank_too_short(rdev))	2103	btc_dpm_vblank_too_short(rdev))
@@ -2121,6 +2139,39 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, · 35 unmodified lines
2121	ps->low.vddci = max_limits->vddci;	2139	ps->low.vddci = max_limits->vddci;
2122	}	2140	}
2123		2141
		2142	/* limit clocks to max supported clocks based on voltage dependency tables */
		2143	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
		2144	&max_sclk_vddc);
		2145	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
		2146	&max_mclk_vddci);
		2147	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
		2148	&max_mclk_vddc);
		2149
		2150	if (max_sclk_vddc) {
		2151	if (ps->low.sclk > max_sclk_vddc)
		2152	ps->low.sclk = max_sclk_vddc;
		2153	if (ps->medium.sclk > max_sclk_vddc)
		2154	ps->medium.sclk = max_sclk_vddc;
		2155	if (ps->high.sclk > max_sclk_vddc)
		2156	ps->high.sclk = max_sclk_vddc;
		2157	}
		2158	if (max_mclk_vddci) {
		2159	if (ps->low.mclk > max_mclk_vddci)
		2160	ps->low.mclk = max_mclk_vddci;
		2161	if (ps->medium.mclk > max_mclk_vddci)
		2162	ps->medium.mclk = max_mclk_vddci;
		2163	if (ps->high.mclk > max_mclk_vddci)
		2164	ps->high.mclk = max_mclk_vddci;
		2165	}
		2166	if (max_mclk_vddc) {
		2167	if (ps->low.mclk > max_mclk_vddc)
		2168	ps->low.mclk = max_mclk_vddc;
		2169	if (ps->medium.mclk > max_mclk_vddc)
		2170	ps->medium.mclk = max_mclk_vddc;
		2171	if (ps->high.mclk > max_mclk_vddc)
		2172	ps->high.mclk = max_mclk_vddc;
		2173	}
		2174
2124	/* XXX validate the min clocks required for display */	2175	/* XXX validate the min clocks required for display */
2125		2176
2126	if (disable_mclk_switching) {	2177	if (disable_mclk_switching) {
@@ -2340,12 +2391,6 @@ int btc_dpm_set_power_state(struct radeon_device *rdev) · 213 unmodified lines
2340	return ret;	2391	return ret;
2341	}	2392	}
2342		2393
2343	ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
2344	if (ret) {
2345	DRM_ERROR("rv770_dpm_force_performance_level failed\n");
2346	return ret;
2347	}
2348
2349	return 0;	2394	return 0;
2350	}	2395	}
2351		2396

drivers/gpu/drm/radeon/btc_dpm.h+2−0

 				   struct rv7xx_pl *pl);
 void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
 					u32 clock, u16 max_voltage, u16 *voltage);
+void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
+						     u32 *max_clock);
 void btc_apply_voltage_delta_rules(struct radeon_device *rdev,
 				   u16 max_vddc, u16 max_vddci,
 				   u16 *vddc, u16 *vddci);

drivers/gpu/drm/radeon/ci_dpm.c+26−6

 };
 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
+extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
+							    u32 *max_clock);
 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 				       u32 arb_freq_src, u32 arb_freq_dest);
 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
 	struct radeon_clock_and_voltage_limits *max_limits;
 	bool disable_mclk_switching;
 	u32 sclk, mclk;
+	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
 	int i;
 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 		}
 	}
+	/* limit clocks to max supported clocks based on voltage dependency tables */
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
+							&max_sclk_vddc);
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
+							&max_mclk_vddci);
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
+							&max_mclk_vddc);
+	for (i = 0; i < ps->performance_level_count; i++) {
+		if (max_sclk_vddc) {
+			if (ps->performance_levels[i].sclk > max_sclk_vddc)
+				ps->performance_levels[i].sclk = max_sclk_vddc;
+		}
+		if (max_mclk_vddci) {
+			if (ps->performance_levels[i].mclk > max_mclk_vddci)
+				ps->performance_levels[i].mclk = max_mclk_vddci;
+		}
+		if (max_mclk_vddc) {
+			if (ps->performance_levels[i].mclk > max_mclk_vddc)
+				ps->performance_levels[i].mclk = max_mclk_vddc;
+		}
+	}
 	/* XXX validate the min clocks required for display */
 	if (disable_mclk_switching) {
 	if (pi->pcie_performance_request)
 		ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
-	ret = ci_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
-	if (ret) {
-		DRM_ERROR("ci_dpm_force_performance_level failed\n");
-		return ret;
-	}
 	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
 			     RADEON_CG_BLOCK_MC |
 			     RADEON_CG_BLOCK_SDMA |

drivers/gpu/drm/radeon/ci_smc.c+26−13

@@ -47,10 +47,11 @@ int ci_copy_bytes_to_smc(struct radeon_device *rdev, · 46 unmodified lines
47	u32 smc_start_address,	47	u32 smc_start_address,
48	const u8 *src, u32 byte_count, u32 limit)	48	const u8 *src, u32 byte_count, u32 limit)
49	{	49	{
		50	unsigned long flags;
50	u32 data, original_data;	51	u32 data, original_data;
51	u32 addr;	52	u32 addr;
52	u32 extra_shift;	53	u32 extra_shift;
53	int ret;	54	int ret = 0;
54		55
55	if (smc_start_address & 3)	56	if (smc_start_address & 3)
56	return -EINVAL;	57	return -EINVAL;
@@ -59,13 +60,14 @@ int ci_copy_bytes_to_smc(struct radeon_device *rdev, · 2 unmodified lines
59		60
60	addr = smc_start_address;	61	addr = smc_start_address;
61		62
		63	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
62	while (byte_count >= 4) {	64	while (byte_count >= 4) {
63	/* SMC address space is BE */	65	/* SMC address space is BE */
64	data = (src[0] << 24) \| (src[1] << 16) \| (src[2] << 8) \| src[3];	66	data = (src[0] << 24) \| (src[1] << 16) \| (src[2] << 8) \| src[3];
65		67
66	ret = ci_set_smc_sram_address(rdev, addr, limit);	68	ret = ci_set_smc_sram_address(rdev, addr, limit);
67	if (ret)	69	if (ret)
68	return ret;	70	goto done;
69		71
70	WREG32(SMC_IND_DATA_0, data);	72	WREG32(SMC_IND_DATA_0, data);
71		73
@@ -80,7 +82,7 @@ int ci_copy_bytes_to_smc(struct radeon_device *rdev, · 8 unmodified lines
80		82
81	ret = ci_set_smc_sram_address(rdev, addr, limit);	83	ret = ci_set_smc_sram_address(rdev, addr, limit);
82	if (ret)	84	if (ret)
83	return ret;	85	goto done;
84		86
85	original_data = RREG32(SMC_IND_DATA_0);	87	original_data = RREG32(SMC_IND_DATA_0);
86		88
@@ -97,11 +99,15 @@ int ci_copy_bytes_to_smc(struct radeon_device *rdev, · 10 unmodified lines
97		99
98	ret = ci_set_smc_sram_address(rdev, addr, limit);	100	ret = ci_set_smc_sram_address(rdev, addr, limit);
99	if (ret)	101	if (ret)
100	return ret;	102	goto done;
101		103
102	WREG32(SMC_IND_DATA_0, data);	104	WREG32(SMC_IND_DATA_0, data);
103	}	105	}
104	return 0;	106
		107	done:
		108	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
		109
		110	return ret;
105	}	111	}
106		112
107	void ci_start_smc(struct radeon_device *rdev)	113	void ci_start_smc(struct radeon_device *rdev)
@@ -197,6 +203,7 @@ PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev) · 89 unmodified lines
197		203
198	int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)	204	int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)
199	{	205	{
		206	unsigned long flags;
200	u32 ucode_start_address;	207	u32 ucode_start_address;
201	u32 ucode_size;	208	u32 ucode_size;
202	const u8 *src;	209	const u8 *src;
@@ -219,6 +226,7 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) · 16 unmodified lines
219	return -EINVAL;	226	return -EINVAL;
220		227
221	src = (const u8 *)rdev->smc_fw->data;	228	src = (const u8 *)rdev->smc_fw->data;
		229	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
222	WREG32(SMC_IND_INDEX_0, ucode_start_address);	230	WREG32(SMC_IND_INDEX_0, ucode_start_address);
223	WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);	231	WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
224	while (ucode_size >= 4) {	232	while (ucode_size >= 4) {
@@ -231,6 +239,7 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) · 6 unmodified lines
231	ucode_size -= 4;	239	ucode_size -= 4;
232	}	240	}
233	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);	241	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
		242	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
234		243
235	return 0;	244	return 0;
236	}	245	}
@@ -238,25 +247,29 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) · 1 unmodified line
238	int ci_read_smc_sram_dword(struct radeon_device *rdev,	247	int ci_read_smc_sram_dword(struct radeon_device *rdev,
239	u32 smc_address, u32 *value, u32 limit)	248	u32 smc_address, u32 *value, u32 limit)
240	{	249	{
		250	unsigned long flags;
241	int ret;	251	int ret;
242		252
		253	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
243	ret = ci_set_smc_sram_address(rdev, smc_address, limit);	254	ret = ci_set_smc_sram_address(rdev, smc_address, limit);
244	if (ret)	255	if (ret == 0)
245	return ret;	256	*value = RREG32(SMC_IND_DATA_0);
		257	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
246		258
247	*value = RREG32(SMC_IND_DATA_0);	259	return ret;
248	return 0;
249	}	260	}
250		261
251	int ci_write_smc_sram_dword(struct radeon_device *rdev,	262	int ci_write_smc_sram_dword(struct radeon_device *rdev,
252	u32 smc_address, u32 value, u32 limit)	263	u32 smc_address, u32 value, u32 limit)
253	{	264	{
		265	unsigned long flags;
254	int ret;	266	int ret;
255		267
		268	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
256	ret = ci_set_smc_sram_address(rdev, smc_address, limit);	269	ret = ci_set_smc_sram_address(rdev, smc_address, limit);
257	if (ret)	270	if (ret == 0)
258	return ret;	271	WREG32(SMC_IND_DATA_0, value);
		272	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
259		273
260	WREG32(SMC_IND_DATA_0, value);	274	return ret;
261	return 0;
262	}	275	}

drivers/gpu/drm/radeon/cik.c+37−16

 static void cik_program_aspm(struct radeon_device *rdev);
 static void cik_init_pg(struct radeon_device *rdev);
 static void cik_init_cg(struct radeon_device *rdev);
+static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
+					  bool enable);
 /* get temperature in millidegrees */
 int ci_get_temp(struct radeon_device *rdev)
  */
 u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
 	WREG32(PCIE_INDEX, reg);
 	(void)RREG32(PCIE_INDEX);
 	r = RREG32(PCIE_DATA);
+	spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
 	return r;
 }
 void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
 	WREG32(PCIE_INDEX, reg);
 	(void)RREG32(PCIE_INDEX);
 	WREG32(PCIE_DATA, v);
 	(void)RREG32(PCIE_DATA);
+	spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
 }
 static const u32 spectre_rlc_save_restore_register_list[] =
 		} else if ((rdev->pdev->device == 0x1309) ||
 			   (rdev->pdev->device == 0x130A) ||
 			   (rdev->pdev->device == 0x130D) ||
-			   (rdev->pdev->device == 0x1313)) {
+			   (rdev->pdev->device == 0x1313) ||
+			   (rdev->pdev->device == 0x131D)) {
 			rdev->config.cik.max_cu_per_sh = 6;
 			rdev->config.cik.max_backends_per_se = 2;
 		} else if ((rdev->pdev->device == 0x1306) ||
 		rdev->config.cik.tile_config |= (3 << 0);
 		break;
 	}
-	if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
+	rdev->config.cik.tile_config |=
-		rdev->config.cik.tile_config |= 1 << 4;
+		((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
-	else
-		rdev->config.cik.tile_config |= 0 << 4;
 	rdev->config.cik.tile_config |=
 		((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 	rdev->config.cik.tile_config |=
 {
 	int r;
+	cik_enable_gui_idle_interrupt(rdev, false);
 	r = cik_cp_load_microcode(rdev);
 	if (r)
 		return r;
 	if (r)
 		return r;
+	cik_enable_gui_idle_interrupt(rdev, true);
 	return 0;
 }
 	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 	/* size in MB on si */
-	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
+	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
-	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
+	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 	rdev->mc.visible_vram_size = rdev->mc.aper_size;
 	si_vram_gtt_location(rdev, &rdev->mc);
 	radeon_update_bandwidth_info(rdev);
 	u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
 	u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
 	u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
-	char *block = (char *)&mc_client;
+	char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
+		(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
-	printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
+	printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 	       protections, vmid, addr,
 	       (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
-	       block, mc_id);
+	       block, mc_client, mc_id);
 }
 /**
 void cik_update_cg(struct radeon_device *rdev,
 		   u32 block, bool enable)
 {
 	if (block & RADEON_CG_BLOCK_GFX) {
+		cik_enable_gui_idle_interrupt(rdev, false);
 		/* order matters! */
 		if (enable) {
 			cik_enable_mgcg(rdev, true);
 			cik_enable_cgcg(rdev, false);
 			cik_enable_mgcg(rdev, false);
 		}
+		cik_enable_gui_idle_interrupt(rdev, true);
 	}
 	if (block & RADEON_CG_BLOCK_MC) {
 {
 	u32 data, orig;
-	if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
+	if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
 		orig = data = RREG32(RLC_PG_CNTL);
 		data |= GFX_PG_ENABLE;
 		if (orig != data)
 	if (rdev->pg_flags) {
 		cik_enable_sck_slowdown_on_pu(rdev, true);
 		cik_enable_sck_slowdown_on_pd(rdev, true);
-		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
+		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
 			cik_init_gfx_cgpg(rdev);
 			cik_enable_cp_pg(rdev, true);
 			cik_enable_gds_pg(rdev, true);
 {
 	if (rdev->pg_flags) {
 		cik_update_gfx_pg(rdev, false);
-		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
+		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
 			cik_enable_cp_pg(rdev, false);
 			cik_enable_gds_pg(rdev, false);
 		}
 	u32 tmp;
 	/* gfx ring */
-	WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+	tmp = RREG32(CP_INT_CNTL_RING0) &
+		(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+	WREG32(CP_INT_CNTL_RING0, tmp);
 	/* sdma */
 	tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
  */
 int cik_irq_set(struct radeon_device *rdev)
 {
-	u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE |
+	u32 cp_int_cntl;
-		PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
 	u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
 	u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
 	u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
 		return 0;
 	}
+	cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
+		(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+	cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
 	hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
 	hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
 	hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/cypress_dpm.c+0−6

 	if (eg_pi->pcie_performance_request)
 		cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
-	ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
-	if (ret) {
-		DRM_ERROR("rv770_dpm_force_performance_level failed\n");
-		return ret;
-	}
 	return 0;
 }

drivers/gpu/drm/radeon/dce6_afmt.c+10−2

 static u32 dce6_endpoint_rreg(struct radeon_device *rdev,
 			      u32 block_offset, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->end_idx_lock, flags);
 	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
+	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
 	return r;
 }
 static void dce6_endpoint_wreg(struct radeon_device *rdev,
 			       u32 block_offset, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->end_idx_lock, flags);
 	if (ASIC_IS_DCE8(rdev))
 		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 	else
 		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
 		       AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
 	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
+	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
 }
 #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg))
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 	u32 offset = dig->afmt->offset;
-	u32 id = dig->afmt->pin->id;
 	if (!dig->afmt->pin)
 		return;
-	WREG32(AFMT_AUDIO_SRC_CONTROL + offset, AFMT_AUDIO_SRC_SELECT(id));
+	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
+	       AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
 }
 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)

drivers/gpu/drm/radeon/kv_dpm.c+129−35

@@ -40,6 +40,7 @@ static int kv_calculate_dpm_settings(struct radeon_device *rdev); · 39 unmodified lines
40	static void kv_enable_new_levels(struct radeon_device *rdev);	40	static void kv_enable_new_levels(struct radeon_device *rdev);
41	static void kv_program_nbps_index_settings(struct radeon_device *rdev,	41	static void kv_program_nbps_index_settings(struct radeon_device *rdev,
42	struct radeon_ps *new_rps);	42	struct radeon_ps *new_rps);
		43	static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
43	static int kv_set_enabled_levels(struct radeon_device *rdev);	44	static int kv_set_enabled_levels(struct radeon_device *rdev);
44	static int kv_force_dpm_highest(struct radeon_device *rdev);	45	static int kv_force_dpm_highest(struct radeon_device *rdev);
45	static int kv_force_dpm_lowest(struct radeon_device *rdev);	46	static int kv_force_dpm_lowest(struct radeon_device *rdev);
@@ -519,7 +520,7 @@ static int kv_set_dpm_boot_state(struct radeon_device *rdev) · 473 unmodified lines
519		520
520	static void kv_program_vc(struct radeon_device *rdev)	521	static void kv_program_vc(struct radeon_device *rdev)
521	{	522	{
522	WREG32_SMC(CG_FTV_0, 0x3FFFC000);	523	WREG32_SMC(CG_FTV_0, 0x3FFFC100);
523	}	524	}
524		525
525	static void kv_clear_vc(struct radeon_device *rdev)	526	static void kv_clear_vc(struct radeon_device *rdev)
@@ -638,7 +639,10 @@ static int kv_force_lowest_valid(struct radeon_device *rdev) · 112 unmodified lines
638		639
639	static int kv_unforce_levels(struct radeon_device *rdev)	640	static int kv_unforce_levels(struct radeon_device *rdev)
640	{	641	{
641	return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);	642	if (rdev->family == CHIP_KABINI)
		643	return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
		644	else
		645	return kv_set_enabled_levels(rdev);
642	}	646	}
643		647
644	static int kv_update_sclk_t(struct radeon_device *rdev)	648	static int kv_update_sclk_t(struct radeon_device *rdev)
@@ -667,9 +671,8 @@ static int kv_program_bootup_state(struct radeon_device *rdev) · 22 unmodified lines
667	&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;	671	&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
668		672
669	if (table && table->count) {	673	if (table && table->count) {
670	for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {	674	for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
671	if ((table->entries[i].clk == pi->boot_pl.sclk) \|\|	675	if (table->entries[i].clk == pi->boot_pl.sclk)
672	(i == 0))
673	break;	676	break;
674	}	677	}
675		678
@@ -682,9 +685,8 @@ static int kv_program_bootup_state(struct radeon_device *rdev) · 6 unmodified lines
682	if (table->num_max_dpm_entries == 0)	685	if (table->num_max_dpm_entries == 0)
683	return -EINVAL;	686	return -EINVAL;
684		687
685	for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {	688	for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
686	if ((table->entries[i].sclk_frequency == pi->boot_pl.sclk) \|\|	689	if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
687	(i == 0))
688	break;	690	break;
689	}	691	}
690		692
@@ -1078,6 +1080,13 @@ static int kv_enable_ulv(struct radeon_device *rdev, bool enable) · 387 unmodified lines
1078	PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);	1080	PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1079	}	1081	}
1080		1082
		1083	static void kv_reset_acp_boot_level(struct radeon_device *rdev)
		1084	{
		1085	struct kv_power_info *pi = kv_get_pi(rdev);
		1086
		1087	pi->acp_boot_level = 0xff;
		1088	}
		1089
1081	static void kv_update_current_ps(struct radeon_device *rdev,	1090	static void kv_update_current_ps(struct radeon_device *rdev,
1082	struct radeon_ps *rps)	1091	struct radeon_ps *rps)
1083	{	1092	{
@@ -1100,6 +1109,18 @@ static void kv_update_requested_ps(struct radeon_device *rdev, · 16 unmodified lines
1100	pi->requested_rps.ps_priv = &pi->requested_ps;	1109	pi->requested_rps.ps_priv = &pi->requested_ps;
1101	}	1110	}
1102		1111
		1112	void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
		1113	{
		1114	struct kv_power_info *pi = kv_get_pi(rdev);
		1115	int ret;
		1116
		1117	if (pi->bapm_enable) {
		1118	ret = kv_smc_bapm_enable(rdev, enable);
		1119	if (ret)
		1120	DRM_ERROR("kv_smc_bapm_enable failed\n");
		1121	}
		1122	}
		1123
1103	int kv_dpm_enable(struct radeon_device *rdev)	1124	int kv_dpm_enable(struct radeon_device *rdev)
1104	{	1125	{
1105	struct kv_power_info *pi = kv_get_pi(rdev);	1126	struct kv_power_info *pi = kv_get_pi(rdev);
@@ -1192,6 +1213,8 @@ int kv_dpm_enable(struct radeon_device *rdev) · 86 unmodified lines
1192	return ret;	1213	return ret;
1193	}	1214	}
1194		1215
		1216	kv_reset_acp_boot_level(rdev);
		1217
1195	if (rdev->irq.installed &&	1218	if (rdev->irq.installed &&
1196	r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {	1219	r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1197	ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);	1220	ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
@@ -1203,6 +1226,12 @@ int kv_dpm_enable(struct radeon_device *rdev) · 5 unmodified lines
1203	radeon_irq_set(rdev);	1226	radeon_irq_set(rdev);
1204	}	1227	}
1205		1228
		1229	ret = kv_smc_bapm_enable(rdev, false);
		1230	if (ret) {
		1231	DRM_ERROR("kv_smc_bapm_enable failed\n");
		1232	return ret;
		1233	}
		1234
1206	/* powerdown unused blocks for now */	1235	/* powerdown unused blocks for now */
1207	kv_dpm_powergate_acp(rdev, true);	1236	kv_dpm_powergate_acp(rdev, true);
1208	kv_dpm_powergate_samu(rdev, true);	1237	kv_dpm_powergate_samu(rdev, true);
@@ -1226,6 +1255,8 @@ void kv_dpm_disable(struct radeon_device *rdev) · 17 unmodified lines
1226	RADEON_CG_BLOCK_BIF \|	1255	RADEON_CG_BLOCK_BIF \|
1227	RADEON_CG_BLOCK_HDP), false);	1256	RADEON_CG_BLOCK_HDP), false);
1228		1257
		1258	kv_smc_bapm_enable(rdev, false);
		1259
1229	/* powerup blocks */	1260	/* powerup blocks */
1230	kv_dpm_powergate_acp(rdev, false);	1261	kv_dpm_powergate_acp(rdev, false);
1231	kv_dpm_powergate_samu(rdev, false);	1262	kv_dpm_powergate_samu(rdev, false);
@@ -1450,6 +1481,39 @@ static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate) · 218 unmodified lines
1450	return kv_enable_samu_dpm(rdev, !gate);	1481	return kv_enable_samu_dpm(rdev, !gate);
1451	}	1482	}
1452		1483
		1484	static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
		1485	{
		1486	u8 i;
		1487	struct radeon_clock_voltage_dependency_table *table =
		1488	&rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
		1489
		1490	for (i = 0; i < table->count; i++) {
		1491	if (table->entries[i].clk >= 0) /* XXX */
		1492	break;
		1493	}
		1494
		1495	if (i >= table->count)
		1496	i = table->count - 1;
		1497
		1498	return i;
		1499	}
		1500
		1501	static void kv_update_acp_boot_level(struct radeon_device *rdev)
		1502	{
		1503	struct kv_power_info *pi = kv_get_pi(rdev);
		1504	u8 acp_boot_level;
		1505
		1506	if (!pi->caps_stable_p_state) {
		1507	acp_boot_level = kv_get_acp_boot_level(rdev);
		1508	if (acp_boot_level != pi->acp_boot_level) {
		1509	pi->acp_boot_level = acp_boot_level;
		1510	kv_send_msg_to_smc_with_parameter(rdev,
		1511	PPSMC_MSG_ACPDPM_SetEnabledMask,
		1512	(1 << pi->acp_boot_level));
		1513	}
		1514	}
		1515	}
		1516
1453	static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)	1517	static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1454	{	1518	{
1455	struct kv_power_info *pi = kv_get_pi(rdev);	1519	struct kv_power_info *pi = kv_get_pi(rdev);
@@ -1461,7 +1525,7 @@ static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate) · 5 unmodified lines
1461	if (pi->caps_stable_p_state)	1525	if (pi->caps_stable_p_state)
1462	pi->acp_boot_level = table->count - 1;	1526	pi->acp_boot_level = table->count - 1;
1463	else	1527	else
1464	pi->acp_boot_level = 0;	1528	pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1465		1529
1466	ret = kv_copy_bytes_to_smc(rdev,	1530	ret = kv_copy_bytes_to_smc(rdev,
1467	pi->dpm_table_start +	1531	pi->dpm_table_start +
@@ -1588,13 +1652,11 @@ static void kv_set_valid_clock_range(struct radeon_device *rdev, · 120 unmodified lines
1588	}	1652	}
1589	}	1653	}
1590		1654
1591	for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {	1655	for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1592	if ((table->entries[i].clk <= new_ps->levels[new_ps->num_levels -1].sclk) \|\|	1656	if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1593	(i == 0)) {
1594	pi->highest_valid = i;
1595	break;	1657	break;
1596	}
1597	}	1658	}
		1659	pi->highest_valid = i;
1598		1660
1599	if (pi->lowest_valid > pi->highest_valid) {	1661	if (pi->lowest_valid > pi->highest_valid) {
1600	if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >	1662	if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
@@ -1615,14 +1677,12 @@ static void kv_set_valid_clock_range(struct radeon_device *rdev, · 14 unmodified lines
1615	}	1677	}
1616	}	1678	}
1617		1679
1618	for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {	1680	for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1619	if (table->entries[i].sclk_frequency <=	1681	if (table->entries[i].sclk_frequency <=
1620	new_ps->levels[new_ps->num_levels - 1].sclk \|\|	1682	new_ps->levels[new_ps->num_levels - 1].sclk)
1621	i == 0) {
1622	pi->highest_valid = i;
1623	break;	1683	break;
1624	}
1625	}	1684	}
		1685	pi->highest_valid = i;
1626		1686
1627	if (pi->lowest_valid > pi->highest_valid) {	1687	if (pi->lowest_valid > pi->highest_valid) {
1628	if ((new_ps->levels[0].sclk -	1688	if ((new_ps->levels[0].sclk -
@@ -1724,6 +1784,14 @@ int kv_dpm_set_power_state(struct radeon_device *rdev) · 95 unmodified lines
1724	RADEON_CG_BLOCK_BIF \|	1784	RADEON_CG_BLOCK_BIF \|
1725	RADEON_CG_BLOCK_HDP), false);	1785	RADEON_CG_BLOCK_HDP), false);
1726		1786
		1787	if (pi->bapm_enable) {
		1788	ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
		1789	if (ret) {
		1790	DRM_ERROR("kv_smc_bapm_enable failed\n");
		1791	return ret;
		1792	}
		1793	}
		1794
1727	if (rdev->family == CHIP_KABINI) {	1795	if (rdev->family == CHIP_KABINI) {
1728	if (pi->enable_dpm) {	1796	if (pi->enable_dpm) {
1729	kv_set_valid_clock_range(rdev, new_ps);	1797	kv_set_valid_clock_range(rdev, new_ps);
@@ -1775,6 +1843,7 @@ int kv_dpm_set_power_state(struct radeon_device *rdev) · 45 unmodified lines
1775	return ret;	1843	return ret;
1776	}	1844	}
1777	#endif	1845	#endif
		1846	kv_update_acp_boot_level(rdev);
1778	kv_update_sclk_t(rdev);	1847	kv_update_sclk_t(rdev);
1779	kv_enable_nb_dpm(rdev);	1848	kv_enable_nb_dpm(rdev);
1780	}	1849	}
@@ -1785,7 +1854,6 @@ int kv_dpm_set_power_state(struct radeon_device *rdev) · 4 unmodified lines
1785	RADEON_CG_BLOCK_BIF \|	1854	RADEON_CG_BLOCK_BIF \|
1786	RADEON_CG_BLOCK_HDP), true);	1855	RADEON_CG_BLOCK_HDP), true);
1787		1856
1788	rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1789	return 0;	1857	return 0;
1790	}	1858	}
1791		1859
@@ -1806,12 +1874,23 @@ void kv_dpm_setup_asic(struct radeon_device *rdev) · 14 unmodified lines
1806		1874
1807	void kv_dpm_reset_asic(struct radeon_device *rdev)	1875	void kv_dpm_reset_asic(struct radeon_device *rdev)
1808	{	1876	{
1809	kv_force_lowest_valid(rdev);	1877	struct kv_power_info *pi = kv_get_pi(rdev);
1810	kv_init_graphics_levels(rdev);	1878
1811	kv_program_bootup_state(rdev);	1879	if (rdev->family == CHIP_KABINI) {
1812	kv_upload_dpm_settings(rdev);	1880	kv_force_lowest_valid(rdev);
1813	kv_force_lowest_valid(rdev);	1881	kv_init_graphics_levels(rdev);
1814	kv_unforce_levels(rdev);	1882	kv_program_bootup_state(rdev);
		1883	kv_upload_dpm_settings(rdev);
		1884	kv_force_lowest_valid(rdev);
		1885	kv_unforce_levels(rdev);
		1886	} else {
		1887	kv_init_graphics_levels(rdev);
		1888	kv_program_bootup_state(rdev);
		1889	kv_freeze_sclk_dpm(rdev, true);
		1890	kv_upload_dpm_settings(rdev);
		1891	kv_freeze_sclk_dpm(rdev, false);
		1892	kv_set_enabled_level(rdev, pi->graphics_boot_level);
		1893	}
1815	}	1894	}
1816		1895
1817	//XXX use sumo_dpm_display_configuration_changed	1896	//XXX use sumo_dpm_display_configuration_changed
@@ -1871,12 +1950,15 @@ static int kv_force_dpm_highest(struct radeon_device *rdev) · 53 unmodified lines
1871	if (ret)	1950	if (ret)
1872	return ret;	1951	return ret;
1873		1952
1874	for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i >= 0; i--) {	1953	for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
1875	if (enable_mask & (1 << i))	1954	if (enable_mask & (1 << i))
1876	break;	1955	break;
1877	}	1956	}
1878		1957
1879	return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);	1958	if (rdev->family == CHIP_KABINI)
		1959	return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
		1960	else
		1961	return kv_set_enabled_level(rdev, i);
1880	}	1962	}
1881		1963
1882	static int kv_force_dpm_lowest(struct radeon_device *rdev)	1964	static int kv_force_dpm_lowest(struct radeon_device *rdev)
@@ -1893,7 +1975,10 @@ static int kv_force_dpm_lowest(struct radeon_device *rdev) · 10 unmodified lines
1893	break;	1975	break;
1894	}	1976	}
1895		1977
1896	return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);	1978	if (rdev->family == CHIP_KABINI)
		1979	return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
		1980	else
		1981	return kv_set_enabled_level(rdev, i);
1897	}	1982	}
1898		1983
1899	static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,	1984	static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
@@ -1911,9 +1996,9 @@ static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev, · 11 unmodified lines
1911	if (!pi->caps_sclk_ds)	1996	if (!pi->caps_sclk_ds)
1912	return 0;	1997	return 0;
1913		1998
1914	for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i <= 0; i--) {	1999	for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
1915	temp = sclk / sumo_get_sleep_divider_from_id(i);	2000	temp = sclk / sumo_get_sleep_divider_from_id(i);
1916	if ((temp >= min) \|\| (i == 0))	2001	if (temp >= min)
1917	break;	2002	break;
1918	}	2003	}
1919		2004
@@ -2039,12 +2124,12 @@ static void kv_apply_state_adjust_rules(struct radeon_device *rdev, · 119 unmodified lines
2039	ps->dpmx_nb_ps_lo = 0x1;	2124	ps->dpmx_nb_ps_lo = 0x1;
2040	ps->dpmx_nb_ps_hi = 0x0;	2125	ps->dpmx_nb_ps_hi = 0x0;
2041	} else {	2126	} else {
2042	ps->dpm0_pg_nb_ps_lo = 0x1;	2127	ps->dpm0_pg_nb_ps_lo = 0x3;
2043	ps->dpm0_pg_nb_ps_hi = 0x0;	2128	ps->dpm0_pg_nb_ps_hi = 0x0;
2044	ps->dpmx_nb_ps_lo = 0x2;	2129	ps->dpmx_nb_ps_lo = 0x3;
2045	ps->dpmx_nb_ps_hi = 0x1;	2130	ps->dpmx_nb_ps_hi = 0x0;
2046		2131
2047	if (pi->sys_info.nb_dpm_enable && pi->battery_state) {	2132	if (pi->sys_info.nb_dpm_enable) {
2048	force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) \|\|	2133	force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) \|\|
2049	pi->video_start \|\| (rdev->pm.dpm.new_active_crtc_count >= 3) \|\|	2134	pi->video_start \|\| (rdev->pm.dpm.new_active_crtc_count >= 3) \|\|
2050	pi->disable_nb_ps3_in_battery;	2135	pi->disable_nb_ps3_in_battery;
@@ -2210,6 +2295,15 @@ static void kv_enable_new_levels(struct radeon_device *rdev) · 159 unmodified lines
2210	}	2295	}
2211	}	2296	}
2212		2297
		2298	static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
		2299	{
		2300	u32 new_mask = (1 << level);
		2301
		2302	return kv_send_msg_to_smc_with_parameter(rdev,
		2303	PPSMC_MSG_SCLKDPM_SetEnabledMask,
		2304	new_mask);
		2305	}
		2306
2213	static int kv_set_enabled_levels(struct radeon_device *rdev)	2307	static int kv_set_enabled_levels(struct radeon_device *rdev)
2214	{	2308	{
2215	struct kv_power_info *pi = kv_get_pi(rdev);	2309	struct kv_power_info *pi = kv_get_pi(rdev);

drivers/gpu/drm/radeon/kv_dpm.h+1−0

@@ -192,6 +192,7 @@ int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev, · 191 unmodified lines
192	int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,	192	int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
193	u32 *value, u32 limit);	193	u32 *value, u32 limit);
194	int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);	194	int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
		195	int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable);
195	int kv_copy_bytes_to_smc(struct radeon_device *rdev,	196	int kv_copy_bytes_to_smc(struct radeon_device *rdev,
196	u32 smc_start_address,	197	u32 smc_start_address,
197	const u8 *src, u32 byte_count, u32 limit);	198	const u8 *src, u32 byte_count, u32 limit);

drivers/gpu/drm/radeon/kv_smc.c+8−0

@@ -107,6 +107,14 @@ int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable) · 106 unmodified lines
107	return kv_notify_message_to_smu(rdev, PPSMC_MSG_DPM_Disable);	107	return kv_notify_message_to_smu(rdev, PPSMC_MSG_DPM_Disable);
108	}	108	}
109		109
		110	int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable)
		111	{
		112	if (enable)
		113	return kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableBAPM);
		114	else
		115	return kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableBAPM);
		116	}
		117
110	int kv_copy_bytes_to_smc(struct radeon_device *rdev,	118	int kv_copy_bytes_to_smc(struct radeon_device *rdev,
111	u32 smc_start_address,	119	u32 smc_start_address,
112	const u8 *src, u32 byte_count, u32 limit)	120	const u8 *src, u32 byte_count, u32 limit)

drivers/gpu/drm/radeon/ni_dpm.c+24−6

 	bool disable_mclk_switching;
 	u32 mclk, sclk;
 	u16 vddc, vddci;
+	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
 	int i;
 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 		}
 	}
+	/* limit clocks to max supported clocks based on voltage dependency tables */
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
+							&max_sclk_vddc);
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
+							&max_mclk_vddci);
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
+							&max_mclk_vddc);
+	for (i = 0; i < ps->performance_level_count; i++) {
+		if (max_sclk_vddc) {
+			if (ps->performance_levels[i].sclk > max_sclk_vddc)
+				ps->performance_levels[i].sclk = max_sclk_vddc;
+		}
+		if (max_mclk_vddci) {
+			if (ps->performance_levels[i].mclk > max_mclk_vddci)
+				ps->performance_levels[i].mclk = max_mclk_vddci;
+		}
+		if (max_mclk_vddc) {
+			if (ps->performance_levels[i].mclk > max_mclk_vddc)
+				ps->performance_levels[i].mclk = max_mclk_vddc;
+		}
+	}
 	/* XXX validate the min clocks required for display */
 	if (disable_mclk_switching) {
 		return ret;
 	}
-	ret = ni_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
-	if (ret) {
-		DRM_ERROR("ni_dpm_force_performance_level failed\n");
-		return ret;
-	}
 	return 0;
 }

drivers/gpu/drm/radeon/ppsmc.h+2−0

@@ -163,6 +163,8 @@ typedef uint8_t PPSMC_Result; · 162 unmodified lines
163	#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f)	163	#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f)
164	#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)	164	#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)
165	#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)	165	#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)
		166	#define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120)
		167	#define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121)
166	#define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124)	168	#define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124)
167		169
168		170

drivers/gpu/drm/radeon/r100.c+12−3

 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
 {
+	unsigned long flags;
 	uint32_t data;
+	spin_lock_irqsave(&rdev->pll_idx_lock, flags);
 	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
 	r100_pll_errata_after_index(rdev);
 	data = RREG32(RADEON_CLOCK_CNTL_DATA);
 	r100_pll_errata_after_data(rdev);
+	spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
 	return data;
 }
 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->pll_idx_lock, flags);
 	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
 	r100_pll_errata_after_index(rdev);
 	WREG32(RADEON_CLOCK_CNTL_DATA, v);
 	r100_pll_errata_after_data(rdev);
+	spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
 }
 static void r100_set_safe_registers(struct radeon_device *rdev)
 	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
 	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
 	seq_printf(m, "%u dwords in ring\n", count);
-	for (j = 0; j <= count; j++) {
+	if (ring->ready) {
-		i = (rdp + j) & ring->ptr_mask;
+		for (j = 0; j <= count; j++) {
-		seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
+			i = (rdp + j) & ring->ptr_mask;
+			seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
+		}
 	}
 	return 0;
 }

drivers/gpu/drm/radeon/r420.c+7−0

 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 	r = RREG32(R_0001FC_MC_IND_DATA);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 	return r;
 }
 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 		S_0001F8_MC_IND_WR_EN(1));
 	WREG32(R_0001FC_MC_IND_DATA, v);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 }
 static void r420_debugfs(struct radeon_device *rdev)

drivers/gpu/drm/radeon/r600.c+19−0

 	return rdev->clock.spll.reference_freq;
 }
+int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
+{
+	return 0;
+}
 /* get temperature in millidegrees */
 int rv6xx_get_temp(struct radeon_device *rdev)
 {
 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 {
+	unsigned long flags;
 	uint32_t r;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
 	r = RREG32(R_0028FC_MC_DATA);
 	WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 	return r;
 }
 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
 		S_0028F8_MC_IND_WR_EN(1));
 	WREG32(R_0028FC_MC_DATA, v);
 	WREG32(R_0028F8_MC_INDEX, 0x7F);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 }
 static void r600_mc_program(struct radeon_device *rdev)
  */
 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
 	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 	(void)RREG32(PCIE_PORT_INDEX);
 	r = RREG32(PCIE_PORT_DATA);
+	spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
 	return r;
 }
 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
 	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 	(void)RREG32(PCIE_PORT_INDEX);
 	WREG32(PCIE_PORT_DATA, (v));
 	(void)RREG32(PCIE_PORT_DATA);
+	spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
 }
 /*

drivers/gpu/drm/radeon/r600_dpm.c+15−25

@@ -1084,7 +1084,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) · 1083 unmodified lines
1084	rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =	1084	rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
1085	le16_to_cpu(uvd_clk->usDClkLow) \| (uvd_clk->ucDClkHigh << 16);	1085	le16_to_cpu(uvd_clk->usDClkLow) \| (uvd_clk->ucDClkHigh << 16);
1086	rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =	1086	rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
1087	le16_to_cpu(limits->entries[i].usVoltage);	1087	le16_to_cpu(entry->usVoltage);
1088	entry = (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *)	1088	entry = (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *)
1089	((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));	1089	((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));
1090	}	1090	}
@@ -1219,30 +1219,20 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) · 128 unmodified lines
1219		1219
1220	void r600_free_extended_power_table(struct radeon_device *rdev)	1220	void r600_free_extended_power_table(struct radeon_device *rdev)
1221	{	1221	{
1222	if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries)	1222	struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state;
1223	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);	1223
1224	if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries)	1224	kfree(dyn_state->vddc_dependency_on_sclk.entries);
1225	kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);	1225	kfree(dyn_state->vddci_dependency_on_mclk.entries);
1226	if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries)	1226	kfree(dyn_state->vddc_dependency_on_mclk.entries);
1227	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);	1227	kfree(dyn_state->mvdd_dependency_on_mclk.entries);
1228	if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries)	1228	kfree(dyn_state->cac_leakage_table.entries);
1229	kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);	1229	kfree(dyn_state->phase_shedding_limits_table.entries);
1230	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries)	1230	kfree(dyn_state->ppm_table);
1231	kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);	1231	kfree(dyn_state->cac_tdp_table);
1232	if (rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)	1232	kfree(dyn_state->vce_clock_voltage_dependency_table.entries);
1233	kfree(rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries);	1233	kfree(dyn_state->uvd_clock_voltage_dependency_table.entries);
1234	if (rdev->pm.dpm.dyn_state.ppm_table)	1234	kfree(dyn_state->samu_clock_voltage_dependency_table.entries);
1235	kfree(rdev->pm.dpm.dyn_state.ppm_table);	1235	kfree(dyn_state->acp_clock_voltage_dependency_table.entries);
1236	if (rdev->pm.dpm.dyn_state.cac_tdp_table)
1237	kfree(rdev->pm.dpm.dyn_state.cac_tdp_table);
1238	if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries)
1239	kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
1240	if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries)
1241	kfree(rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries);
1242	if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries)
1243	kfree(rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries);
1244	if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries)
1245	kfree(rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries);
1246	}	1236	}
1247		1237
1248	enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,	1238	enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,

drivers/gpu/drm/radeon/r600_hdmi.c+15−5

 	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 	 */
-	if (ASIC_IS_DCE3(rdev)) {
+	if (ASIC_IS_DCE32(rdev)) {
-		/* according to the reg specs, this should DCE3.2 only, but in
-		 * practice it seems to cover DCE3.0 as well.
-		 */
 		if (dig->dig_encoder == 0) {
 			dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 			dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 			WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
 			WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
 		}
+	} else if (ASIC_IS_DCE3(rdev)) {
+		/* according to the reg specs, this should DCE3.2 only, but in
+		 * practice it seems to cover DCE3.0/3.1 as well.
+		 */
+		if (dig->dig_encoder == 0) {
+			WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
+			WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
+			WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
+		} else {
+			WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
+			WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
+			WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
+		}
 	} else {
-		/* according to the reg specs, this should be DCE2.0 and DCE3.0 */
+		/* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */
 		WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
 		       AUDIO_DTO_MODULE(clock / 10));
 	}

drivers/gpu/drm/radeon/r600d.h+1−1

@@ -1040,7 +1040,7 @@ · 1039 unmodified lines
1040	# define HDMI0_AVI_INFO_CONT (1 << 1)	1040	# define HDMI0_AVI_INFO_CONT (1 << 1)
1041	# define HDMI0_AUDIO_INFO_SEND (1 << 4)	1041	# define HDMI0_AUDIO_INFO_SEND (1 << 4)
1042	# define HDMI0_AUDIO_INFO_CONT (1 << 5)	1042	# define HDMI0_AUDIO_INFO_CONT (1 << 5)
1043	# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */	1043	# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
1044	# define HDMI0_AUDIO_INFO_UPDATE (1 << 7)	1044	# define HDMI0_AUDIO_INFO_UPDATE (1 << 7)
1045	# define HDMI0_MPEG_INFO_SEND (1 << 8)	1045	# define HDMI0_MPEG_INFO_SEND (1 << 8)
1046	# define HDMI0_MPEG_INFO_CONT (1 << 9)	1046	# define HDMI0_MPEG_INFO_CONT (1 << 9)

drivers/gpu/drm/radeon/radeon.h+81−1

 #define RADEON_CG_SUPPORT_HDP_MGCG		(1 << 16)
 /* PG flags */
-#define RADEON_PG_SUPPORT_GFX_CG		(1 << 0)
+#define RADEON_PG_SUPPORT_GFX_PG		(1 << 0)
 #define RADEON_PG_SUPPORT_GFX_SMG		(1 << 1)
 #define RADEON_PG_SUPPORT_GFX_DMG		(1 << 2)
 #define RADEON_PG_SUPPORT_UVD			(1 << 3)
 		int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
 		bool (*vblank_too_short)(struct radeon_device *rdev);
 		void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
+		void (*enable_bapm)(struct radeon_device *rdev, bool enable);
 	} dpm;
 	/* pageflipping */
 	struct {
 	resource_size_t			rmmio_size;
 	/* protects concurrent MM_INDEX/DATA based register access */
 	spinlock_t mmio_idx_lock;
+	/* protects concurrent SMC based register access */
+	spinlock_t smc_idx_lock;
+	/* protects concurrent PLL register access */
+	spinlock_t pll_idx_lock;
+	/* protects concurrent MC register access */
+	spinlock_t mc_idx_lock;
+	/* protects concurrent PCIE register access */
+	spinlock_t pcie_idx_lock;
+	/* protects concurrent PCIE_PORT register access */
+	spinlock_t pciep_idx_lock;
+	/* protects concurrent PIF register access */
+	spinlock_t pif_idx_lock;
+	/* protects concurrent CG register access */
+	spinlock_t cg_idx_lock;
+	/* protects concurrent UVD register access */
+	spinlock_t uvd_idx_lock;
+	/* protects concurrent RCU register access */
+	spinlock_t rcu_idx_lock;
+	/* protects concurrent DIDT register access */
+	spinlock_t didt_idx_lock;
+	/* protects concurrent ENDPOINT (audio) register access */
+	spinlock_t end_idx_lock;
 	void __iomem			*rmmio;
 	radeon_rreg_t			mc_rreg;
 	radeon_wreg_t			mc_wreg;
  */
 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 {
+	unsigned long flags;
 	uint32_t r;
+	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
 	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 	r = RREG32(RADEON_PCIE_DATA);
+	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
 	return r;
 }
 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
 	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 	WREG32(RADEON_PCIE_DATA, (v));
+	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
 }
 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
 	WREG32(TN_SMC_IND_INDEX_0, (reg));
 	r = RREG32(TN_SMC_IND_DATA_0);
+	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
 	return r;
 }
 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
 	WREG32(TN_SMC_IND_INDEX_0, (reg));
 	WREG32(TN_SMC_IND_DATA_0, (v));
+	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
 }
 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
 	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
 	r = RREG32(R600_RCU_DATA);
+	spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
 	return r;
 }
 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
 	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
 	WREG32(R600_RCU_DATA, (v));
+	spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
 }
 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->cg_idx_lock, flags);
 	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
 	r = RREG32(EVERGREEN_CG_IND_DATA);
+	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
 	return r;
 }
 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->cg_idx_lock, flags);
 	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
 	WREG32(EVERGREEN_CG_IND_DATA, (v));
+	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
 }
 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
 	r = RREG32(EVERGREEN_PIF_PHY0_DATA);
+	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
 	return r;
 }
 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
 	WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
+	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
 }
 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
 	r = RREG32(EVERGREEN_PIF_PHY1_DATA);
+	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
 	return r;
 }
 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
 	WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
+	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
 }
 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
 	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
 	r = RREG32(R600_UVD_CTX_DATA);
+	spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
 	return r;
 }
 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
 	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
 	WREG32(R600_UVD_CTX_DATA, (v));
+	spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
 }
 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
 {
+	unsigned long flags;
 	u32 r;
+	spin_lock_irqsave(&rdev->didt_idx_lock, flags);
 	WREG32(CIK_DIDT_IND_INDEX, (reg));
 	r = RREG32(CIK_DIDT_IND_DATA);
+	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
 	return r;
 }
 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->didt_idx_lock, flags);
 	WREG32(CIK_DIDT_IND_INDEX, (reg));
 	WREG32(CIK_DIDT_IND_DATA, (v));
+	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
 }
 void r100_pll_errata_after_index(struct radeon_device *rdev);
 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
+#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
 /* Common functions */
 /* AGP */

drivers/gpu/drm/radeon/radeon_asic.c+10−3

 		.wait_for_vblank = &avivo_wait_for_vblank,
 		.set_backlight_level = &atombios_set_backlight_level,
 		.get_backlight_level = &atombios_get_backlight_level,
+		.hdmi_enable = &r600_hdmi_enable,
+		.hdmi_setmode = &r600_hdmi_setmode,
 	},
 	.copy = {
 		.blit = &r600_copy_cpdma,
 		.set_pcie_lanes = &r600_set_pcie_lanes,
 		.set_clock_gating = NULL,
 		.get_temperature = &rv6xx_get_temp,
+		.set_uvd_clocks = &r600_set_uvd_clocks,
 	},
 	.dpm = {
 		.init = &rv6xx_dpm_init,
 		.set_pcie_lanes = NULL,
 		.set_clock_gating = NULL,
 		.get_temperature = &rv6xx_get_temp,
+		.set_uvd_clocks = &r600_set_uvd_clocks,
 	},
 	.dpm = {
 		.init = &rs780_dpm_init,
 		.get_mclk = &rs780_dpm_get_mclk,
 		.print_power_state = &rs780_dpm_print_power_state,
 		.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
+		.force_performance_level = &rs780_dpm_force_performance_level,
 	},
 	.pflip = {
 		.pre_page_flip = &rs600_pre_page_flip,
 		.print_power_state = &trinity_dpm_print_power_state,
 		.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
 		.force_performance_level = &trinity_dpm_force_performance_level,
+		.enable_bapm = &trinity_dpm_enable_bapm,
 	},
 	.pflip = {
 		.pre_page_flip = &evergreen_pre_page_flip,
 		.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
 		.force_performance_level = &kv_dpm_force_performance_level,
 		.powergate_uvd = &kv_dpm_powergate_uvd,
+		.enable_bapm = &kv_dpm_enable_bapm,
 	},
 	.pflip = {
 		.pre_page_flip = &evergreen_pre_page_flip,
 				RADEON_CG_SUPPORT_HDP_LS |
 				RADEON_CG_SUPPORT_HDP_MGCG;
 			rdev->pg_flags = 0 |
-				/*RADEON_PG_SUPPORT_GFX_CG | */
+				/*RADEON_PG_SUPPORT_GFX_PG | */
 				RADEON_PG_SUPPORT_SDMA;
 			break;
 		case CHIP_OLAND:
 				RADEON_CG_SUPPORT_HDP_LS |
 				RADEON_CG_SUPPORT_HDP_MGCG;
 			rdev->pg_flags = 0;
-				/*RADEON_PG_SUPPORT_GFX_CG |
+				/*RADEON_PG_SUPPORT_GFX_PG |
 				RADEON_PG_SUPPORT_GFX_SMG |
 				RADEON_PG_SUPPORT_GFX_DMG |
 				RADEON_PG_SUPPORT_UVD |
 				RADEON_CG_SUPPORT_HDP_LS |
 				RADEON_CG_SUPPORT_HDP_MGCG;
 			rdev->pg_flags = 0;
-				/*RADEON_PG_SUPPORT_GFX_CG |
+				/*RADEON_PG_SUPPORT_GFX_PG |
 				RADEON_PG_SUPPORT_GFX_SMG |
 				RADEON_PG_SUPPORT_UVD |
 				RADEON_PG_SUPPORT_VCE |

drivers/gpu/drm/radeon/radeon_asic.h+5−0

 u32 r600_get_xclk(struct radeon_device *rdev);
 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
 int rv6xx_get_temp(struct radeon_device *rdev);
+int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
 void r600_dpm_post_set_power_state(struct radeon_device *rdev);
 /* r600 dma */
 				 struct radeon_ps *ps);
 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 						       struct seq_file *m);
+int rs780_dpm_force_performance_level(struct radeon_device *rdev,
+				      enum radeon_dpm_forced_level level);
 /*
  * rv770,rv730,rv710,rv740
 							 struct seq_file *m);
 int trinity_dpm_force_performance_level(struct radeon_device *rdev,
 					enum radeon_dpm_forced_level level);
+void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 /* DCE6 - SI */
 void dce6_bandwidth_update(struct radeon_device *rdev);
 int kv_dpm_force_performance_level(struct radeon_device *rdev,
 				   enum radeon_dpm_forced_level level);
 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
+void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 /* uvd v1.0 */
 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,

drivers/gpu/drm/radeon/radeon_atombios.c+43−23

@@ -1367,6 +1367,7 @@ bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, · 1366 unmodified lines
1367	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);	1367	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1368	uint16_t data_offset, size;	1368	uint16_t data_offset, size;
1369	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;	1369	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
		1370	struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1370	uint8_t frev, crev;	1371	uint8_t frev, crev;
1371	int i, num_indices;	1372	int i, num_indices;
1372		1373
@@ -1378,18 +1379,21 @@ bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, · 5 unmodified lines
1378		1379
1379	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /	1380	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1380	sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);	1381	sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1381		1382	ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
		1383	((u8 *)&ss_info->asSS_Info[0]);
1382	for (i = 0; i < num_indices; i++) {	1384	for (i = 0; i < num_indices; i++) {
1383	if (ss_info->asSS_Info[i].ucSS_Id == id) {	1385	if (ss_assign->ucSS_Id == id) {
1384	ss->percentage =	1386	ss->percentage =
1385	le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);	1387	le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1386	ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;	1388	ss->type = ss_assign->ucSpreadSpectrumType;
1387	ss->step = ss_info->asSS_Info[i].ucSS_Step;	1389	ss->step = ss_assign->ucSS_Step;
1388	ss->delay = ss_info->asSS_Info[i].ucSS_Delay;	1390	ss->delay = ss_assign->ucSS_Delay;
1389	ss->range = ss_info->asSS_Info[i].ucSS_Range;	1391	ss->range = ss_assign->ucSS_Range;
1390	ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;	1392	ss->refdiv = ss_assign->ucRecommendedRef_Div;
1391	return true;	1393	return true;
1392	}	1394	}
		1395	ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
		1396	((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1393	}	1397	}
1394	}	1398	}
1395	return false;	1399	return false;
@@ -1477,6 +1481,12 @@ union asic_ss_info { · 81 unmodified lines
1477	struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;	1481	struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1478	};	1482	};
1479		1483
		1484	union asic_ss_assignment {
		1485	struct _ATOM_ASIC_SS_ASSIGNMENT v1;
		1486	struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
		1487	struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
		1488	};
		1489
1480	bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,	1490	bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1481	struct radeon_atom_ss *ss,	1491	struct radeon_atom_ss *ss,
1482	int id, u32 clock)	1492	int id, u32 clock)
@@ -1485,6 +1495,7 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, · 2 unmodified lines
1485	int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);	1495	int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1486	uint16_t data_offset, size;	1496	uint16_t data_offset, size;
1487	union asic_ss_info *ss_info;	1497	union asic_ss_info *ss_info;
		1498	union asic_ss_assignment *ss_assign;
1488	uint8_t frev, crev;	1499	uint8_t frev, crev;
1489	int i, num_indices;	1500	int i, num_indices;
1490		1501
@@ -1509,45 +1520,52 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, · 18 unmodified lines
1509	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /	1520	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1510	sizeof(ATOM_ASIC_SS_ASSIGNMENT);	1521	sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1511		1522
		1523	ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info.asSpreadSpectrum[0]);
1512	for (i = 0; i < num_indices; i++) {	1524	for (i = 0; i < num_indices; i++) {
1513	if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&	1525	if ((ss_assign->v1.ucClockIndication == id) &&
1514	(clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {	1526	(clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1515	ss->percentage =	1527	ss->percentage =
1516	le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);	1528	le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1517	ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;	1529	ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1518	ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);	1530	ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1519	return true;	1531	return true;
1520	}	1532	}
		1533	ss_assign = (union asic_ss_assignment *)
		1534	((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1521	}	1535	}
1522	break;	1536	break;
1523	case 2:	1537	case 2:
1524	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /	1538	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1525	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);	1539	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
		1540	ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info_2.asSpreadSpectrum[0]);
1526	for (i = 0; i < num_indices; i++) {	1541	for (i = 0; i < num_indices; i++) {
1527	if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&	1542	if ((ss_assign->v2.ucClockIndication == id) &&
1528	(clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {	1543	(clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1529	ss->percentage =	1544	ss->percentage =
1530	le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);	1545	le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1531	ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;	1546	ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1532	ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);	1547	ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1533	if ((crev == 2) &&	1548	if ((crev == 2) &&
1534	((id == ASIC_INTERNAL_ENGINE_SS) \|\|	1549	((id == ASIC_INTERNAL_ENGINE_SS) \|\|
1535	(id == ASIC_INTERNAL_MEMORY_SS)))	1550	(id == ASIC_INTERNAL_MEMORY_SS)))
1536	ss->rate /= 100;	1551	ss->rate /= 100;
1537	return true;	1552	return true;
1538	}	1553	}
		1554	ss_assign = (union asic_ss_assignment *)
		1555	((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1539	}	1556	}
1540	break;	1557	break;
1541	case 3:	1558	case 3:
1542	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /	1559	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1543	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);	1560	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
		1561	ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info_3.asSpreadSpectrum[0]);
1544	for (i = 0; i < num_indices; i++) {	1562	for (i = 0; i < num_indices; i++) {
1545	if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&	1563	if ((ss_assign->v3.ucClockIndication == id) &&
1546	(clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {	1564	(clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1547	ss->percentage =	1565	ss->percentage =
1548	le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);	1566	le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1549	ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;	1567	ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1550	ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);	1568	ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1551	if ((id == ASIC_INTERNAL_ENGINE_SS) \|\|	1569	if ((id == ASIC_INTERNAL_ENGINE_SS) \|\|
1552	(id == ASIC_INTERNAL_MEMORY_SS))	1570	(id == ASIC_INTERNAL_MEMORY_SS))
1553	ss->rate /= 100;	1571	ss->rate /= 100;
@@ -1555,6 +1573,8 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, · 1 unmodified line
1555	radeon_atombios_get_igp_ss_overrides(rdev, ss, id);	1573	radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1556	return true;	1574	return true;
1557	}	1575	}
		1576	ss_assign = (union asic_ss_assignment *)
		1577	((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1558	}	1578	}
1559	break;	1579	break;
1560	default:	1580	default:

drivers/gpu/drm/radeon/radeon_connectors.c+65−4

 		}
 	}
+	if (property == rdev->mode_info.audio_property) {
+		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+		/* need to find digital encoder on connector */
+		encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
+		if (!encoder)
+			return 0;
+		radeon_encoder = to_radeon_encoder(encoder);
+		if (radeon_connector->audio != val) {
+			radeon_connector->audio = val;
+			radeon_property_change_mode(&radeon_encoder->base);
+		}
+	}
 	if (property == rdev->mode_info.underscan_property) {
 		/* need to find digital encoder on connector */
 		encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 				if (radeon_dp_getdpcd(radeon_connector))
 					ret = connector_status_connected;
 			} else {
-				/* try non-aux ddc (DP to DVI/HMDI/etc. adapter) */
+				/* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
 				if (radeon_ddc_probe(radeon_connector, false))
 					ret = connector_status_connected;
 			}
 	.force = radeon_dvi_force,
 };
+static const struct drm_connector_funcs radeon_edp_connector_funcs = {
+	.dpms = drm_helper_connector_dpms,
+	.detect = radeon_dp_detect,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.set_property = radeon_lvds_set_property,
+	.destroy = radeon_dp_connector_destroy,
+	.force = radeon_dvi_force,
+};
+static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = {
+	.dpms = drm_helper_connector_dpms,
+	.detect = radeon_dp_detect,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.set_property = radeon_lvds_set_property,
+	.destroy = radeon_dp_connector_destroy,
+	.force = radeon_dvi_force,
+};
 void
 radeon_add_atom_connector(struct drm_device *dev,
 			  uint32_t connector_id,
 			goto failed;
 		radeon_dig_connector->igp_lane_info = igp_lane_info;
 		radeon_connector->con_priv = radeon_dig_connector;
-		drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
-		drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
 		if (i2c_bus->valid) {
 			/* add DP i2c bus */
 			if (connector_type == DRM_MODE_CONNECTOR_eDP)
 		case DRM_MODE_CONNECTOR_VGA:
 		case DRM_MODE_CONNECTOR_DVIA:
 		default:
+			drm_connector_init(dev, &radeon_connector->base,
+					   &radeon_dp_connector_funcs, connector_type);
+			drm_connector_helper_add(&radeon_connector->base,
+						 &radeon_dp_connector_helper_funcs);
 			connector->interlace_allowed = true;
 			connector->doublescan_allowed = true;
 			radeon_connector->dac_load_detect = true;
 		case DRM_MODE_CONNECTOR_HDMIA:
 		case DRM_MODE_CONNECTOR_HDMIB:
 		case DRM_MODE_CONNECTOR_DisplayPort:
+			drm_connector_init(dev, &radeon_connector->base,
+					   &radeon_dp_connector_funcs, connector_type);
+			drm_connector_helper_add(&radeon_connector->base,
+						 &radeon_dp_connector_helper_funcs);
 			drm_object_attach_property(&radeon_connector->base.base,
 						      rdev->mode_info.underscan_property,
 						      UNDERSCAN_OFF);
 			drm_object_attach_property(&radeon_connector->base.base,
 						      rdev->mode_info.underscan_vborder_property,
 						      0);
+			drm_object_attach_property(&radeon_connector->base.base,
+						   rdev->mode_info.audio_property,
+						   RADEON_AUDIO_DISABLE);
 			subpixel_order = SubPixelHorizontalRGB;
 			connector->interlace_allowed = true;
 			if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
 			break;
 		case DRM_MODE_CONNECTOR_LVDS:
 		case DRM_MODE_CONNECTOR_eDP:
+			drm_connector_init(dev, &radeon_connector->base,
+					   &radeon_lvds_bridge_connector_funcs, connector_type);
+			drm_connector_helper_add(&radeon_connector->base,
+						 &radeon_dp_connector_helper_funcs);
 			drm_object_attach_property(&radeon_connector->base.base,
 						      dev->mode_config.scaling_mode_property,
 						      DRM_MODE_SCALE_FULLSCREEN);
 							      rdev->mode_info.underscan_vborder_property,
 							      0);
 			}
+			if (ASIC_IS_DCE2(rdev)) {
+				drm_object_attach_property(&radeon_connector->base.base,
+							      rdev->mode_info.audio_property,
+							      RADEON_AUDIO_DISABLE);
+			}
 			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
 				radeon_connector->dac_load_detect = true;
 				drm_object_attach_property(&radeon_connector->base.base,
 							      rdev->mode_info.underscan_vborder_property,
 							      0);
 			}
+			if (ASIC_IS_DCE2(rdev)) {
+				drm_object_attach_property(&radeon_connector->base.base,
+							      rdev->mode_info.audio_property,
+							      RADEON_AUDIO_DISABLE);
+			}
 			subpixel_order = SubPixelHorizontalRGB;
 			connector->interlace_allowed = true;
 			if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
 							      rdev->mode_info.underscan_vborder_property,
 							      0);
 			}
+			if (ASIC_IS_DCE2(rdev)) {
+				drm_object_attach_property(&radeon_connector->base.base,
+							      rdev->mode_info.audio_property,
+							      RADEON_AUDIO_DISABLE);
+			}
 			connector->interlace_allowed = true;
 			/* in theory with a DP to VGA converter... */
 			connector->doublescan_allowed = false;
 				goto failed;
 			radeon_dig_connector->igp_lane_info = igp_lane_info;
 			radeon_connector->con_priv = radeon_dig_connector;
-			drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
+			drm_connector_init(dev, &radeon_connector->base, &radeon_edp_connector_funcs, connector_type);
 			drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
 			if (i2c_bus->valid) {
 				/* add DP i2c bus */

drivers/gpu/drm/radeon/radeon_cs.c+10−4

 #include <drm/radeon_drm.h>
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "radeon_trace.h"
 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
 {
 		p->relocs[i].lobj.bo = p->relocs[i].robj;
 		p->relocs[i].lobj.written = !!r->write_domain;
-		/* the first reloc of an UVD job is the
+		/* the first reloc of an UVD job is the msg and that must be in
-		   msg and that must be in VRAM */
+		   VRAM, also but everything into VRAM on AGP cards to avoid
-		if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) {
+		   image corruptions */
-			/* TODO: is this still needed for NI+ ? */
+		if (p->ring == R600_RING_TYPE_UVD_INDEX &&
+		    p->rdev->family < CHIP_PALM &&
+		    (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
 			p->relocs[i].lobj.domain =
 				RADEON_GEM_DOMAIN_VRAM;
 		return r;
 	}
+	trace_radeon_cs(&parser);
 	r = radeon_cs_ib_chunk(rdev, &parser);
 	if (r) {
 		goto out;

drivers/gpu/drm/radeon/radeon_device.c+23−3

@@ -1249,6 +1249,17 @@ int radeon_device_init(struct radeon_device *rdev, · 1248 unmodified lines
1249	/* Registers mapping */	1249	/* Registers mapping */
1250	/* TODO: block userspace mapping of io register */	1250	/* TODO: block userspace mapping of io register */
1251	spin_lock_init(&rdev->mmio_idx_lock);	1251	spin_lock_init(&rdev->mmio_idx_lock);
		1252	spin_lock_init(&rdev->smc_idx_lock);
		1253	spin_lock_init(&rdev->pll_idx_lock);
		1254	spin_lock_init(&rdev->mc_idx_lock);
		1255	spin_lock_init(&rdev->pcie_idx_lock);
		1256	spin_lock_init(&rdev->pciep_idx_lock);
		1257	spin_lock_init(&rdev->pif_idx_lock);
		1258	spin_lock_init(&rdev->cg_idx_lock);
		1259	spin_lock_init(&rdev->uvd_idx_lock);
		1260	spin_lock_init(&rdev->rcu_idx_lock);
		1261	spin_lock_init(&rdev->didt_idx_lock);
		1262	spin_lock_init(&rdev->end_idx_lock);
1252	if (rdev->family >= CHIP_BONAIRE) {	1263	if (rdev->family >= CHIP_BONAIRE) {
1253	rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);	1264	rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1254	rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);	1265	rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
@@ -1309,13 +1320,22 @@ int radeon_device_init(struct radeon_device *rdev, · 54 unmodified lines
1309	return r;	1320	return r;
1310	}	1321	}
1311	if ((radeon_testing & 1)) {	1322	if ((radeon_testing & 1)) {
1312	radeon_test_moves(rdev);	1323	if (rdev->accel_working)
		1324	radeon_test_moves(rdev);
		1325	else
		1326	DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1313	}	1327	}
1314	if ((radeon_testing & 2)) {	1328	if ((radeon_testing & 2)) {
1315	radeon_test_syncing(rdev);	1329	if (rdev->accel_working)
		1330	radeon_test_syncing(rdev);
		1331	else
		1332	DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1316	}	1333	}
1317	if (radeon_benchmarking) {	1334	if (radeon_benchmarking) {
1318	radeon_benchmark(rdev, radeon_benchmarking);	1335	if (rdev->accel_working)
		1336	radeon_benchmark(rdev, radeon_benchmarking);
		1337	else
		1338	DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1319	}	1339	}
1320	return 0;	1340	return 0;
1321	}	1341	}

drivers/gpu/drm/radeon/radeon_display.c+12−0

 	{ UNDERSCAN_AUTO, "auto" },
 };
+static struct drm_prop_enum_list radeon_audio_enum_list[] =
+{	{ RADEON_AUDIO_DISABLE, "off" },
+	{ RADEON_AUDIO_ENABLE, "on" },
+	{ RADEON_AUDIO_AUTO, "auto" },
+};
 static int radeon_modeset_create_props(struct radeon_device *rdev)
 {
 	int sz;
 	if (!rdev->mode_info.underscan_vborder_property)
 		return -ENOMEM;
+	sz = ARRAY_SIZE(radeon_audio_enum_list);
+	rdev->mode_info.audio_property =
+		drm_property_create_enum(rdev->ddev, 0,
+					 "audio",
+					 radeon_audio_enum_list, sz);
 	return 0;
 }

drivers/gpu/drm/radeon/radeon_drv.c+1−1

@@ -153,7 +153,7 @@ int radeon_benchmarking = 0; · 152 unmodified lines
153	int radeon_testing = 0;	153	int radeon_testing = 0;
154	int radeon_connector_table = 0;	154	int radeon_connector_table = 0;
155	int radeon_tv = 1;	155	int radeon_tv = 1;
156	int radeon_audio = 0;	156	int radeon_audio = 1;
157	int radeon_disp_priority = 0;	157	int radeon_disp_priority = 0;
158	int radeon_hw_i2c = 0;	158	int radeon_hw_i2c = 0;
159	int radeon_pcie_gen2 = -1;	159	int radeon_pcie_gen2 = -1;

drivers/gpu/drm/radeon/radeon_mode.h+9−0

 	struct drm_property *underscan_property;
 	struct drm_property *underscan_hborder_property;
 	struct drm_property *underscan_vborder_property;
+	/* audio */
+	struct drm_property *audio_property;
 	/* hardcoded DFP edid from BIOS */
 	struct edid *bios_hardcoded_edid;
 	int bios_hardcoded_edid_size;
 	u8 cd_mux_state;
 };
+enum radeon_connector_audio {
+	RADEON_AUDIO_DISABLE = 0,
+	RADEON_AUDIO_ENABLE = 1,
+	RADEON_AUDIO_AUTO = 2
+};
 struct radeon_connector {
 	struct drm_connector base;
 	uint32_t connector_id;
 	struct radeon_hpd hpd;
 	struct radeon_router router;
 	struct radeon_i2c_chan *router_bus;
+	enum radeon_connector_audio audio;
 };
 struct radeon_framebuffer {

drivers/gpu/drm/radeon/radeon_pm.c+70−19

 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
 {
-	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
+	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
+		mutex_lock(&rdev->pm.mutex);
+		if (power_supply_is_system_supplied() > 0)
+			rdev->pm.dpm.ac_power = true;
+		else
+			rdev->pm.dpm.ac_power = false;
+		if (rdev->asic->dpm.enable_bapm)
+			radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
+		mutex_unlock(&rdev->pm.mutex);
+        } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 		if (rdev->pm.profile == PM_PROFILE_AUTO) {
 			mutex_lock(&rdev->pm.mutex);
 			radeon_pm_update_profile(rdev);
 				     struct device_attribute *attr,
 				     char *buf)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	int cp = rdev->pm.profile;
 				     const char *buf,
 				     size_t count)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	mutex_lock(&rdev->pm.mutex);
 				    struct device_attribute *attr,
 				    char *buf)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	int pm = rdev->pm.pm_method;
 				    const char *buf,
 				    size_t count)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	/* we don't support the legacy modes with dpm */
 				    struct device_attribute *attr,
 				    char *buf)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 				    const char *buf,
 				    size_t count)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	mutex_lock(&rdev->pm.mutex);
 						       struct device_attribute *attr,
 						       char *buf)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 						       const char *buf,
 						       size_t count)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	enum radeon_dpm_forced_level level;
 	int ret = 0;
 				      struct device_attribute *attr,
 				      char *buf)
 {
-	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
+	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	int temp;
 	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 }
+static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
+					     struct device_attribute *attr,
+					     char *buf)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct radeon_device *rdev = ddev->dev_private;
+	int hyst = to_sensor_dev_attr(attr)->index;
+	int temp;
+	if (hyst)
+		temp = rdev->pm.dpm.thermal.min_temp;
+	else
+		temp = rdev->pm.dpm.thermal.max_temp;
+	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
+}
 static ssize_t radeon_hwmon_show_name(struct device *dev,
 				      struct device_attribute *attr,
 				      char *buf)
 }
 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
+static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
+static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 static struct attribute *hwmon_attributes[] = {
 	&sensor_dev_attr_temp1_input.dev_attr.attr,
+	&sensor_dev_attr_temp1_crit.dev_attr.attr,
+	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 	&sensor_dev_attr_name.dev_attr.attr,
 	NULL
 };
+static umode_t hwmon_attributes_visible(struct kobject *kobj,
+					struct attribute *attr, int index)
+{
+	struct device *dev = container_of(kobj, struct device, kobj);
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct radeon_device *rdev = ddev->dev_private;
+	/* Skip limit attributes if DPM is not enabled */
+	if (rdev->pm.pm_method != PM_METHOD_DPM &&
+	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
+	     attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
+		return 0;
+	return attr->mode;
+}
 static const struct attribute_group hwmon_attrgroup = {
 	.attrs = hwmon_attributes,
+	.is_visible = hwmon_attributes_visible,
 };
 static int radeon_hwmon_init(struct radeon_device *rdev)
 	radeon_dpm_post_set_power_state(rdev);
-	/* force low perf level for thermal */
+	if (rdev->asic->dpm.force_performance_level) {
-	if (rdev->pm.dpm.thermal_active &&
+		if (rdev->pm.dpm.thermal_active)
-	    rdev->asic->dpm.force_performance_level) {
+			/* force low perf level for thermal */
-		radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
+			radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
+		else
+			/* otherwise, enable auto */
+			radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
 	}
 done:
 {
 	/* set up the default clocks if the MC ucode is loaded */
 	if ((rdev->family >= CHIP_BARTS) &&
-	    (rdev->family <= CHIP_HAINAN) &&
+	    (rdev->family <= CHIP_CAYMAN) &&
 	    rdev->mc_fw) {
 		if (rdev->pm.default_vddc)
 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 	if (ret) {
 		DRM_ERROR("radeon: dpm resume failed\n");
 		if ((rdev->family >= CHIP_BARTS) &&
-		    (rdev->family <= CHIP_HAINAN) &&
+		    (rdev->family <= CHIP_CAYMAN) &&
 		    rdev->mc_fw) {
 			if (rdev->pm.default_vddc)
 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 		radeon_pm_init_profile(rdev);
 		/* set up the default clocks if the MC ucode is loaded */
 		if ((rdev->family >= CHIP_BARTS) &&
-		    (rdev->family <= CHIP_HAINAN) &&
+		    (rdev->family <= CHIP_CAYMAN) &&
 		    rdev->mc_fw) {
 			if (rdev->pm.default_vddc)
 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 {
 	int ret;
-	/* default to performance state */
+	/* default to balanced state */
 	rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
 	rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
+	rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
 	rdev->pm.default_sclk = rdev->clock.default_sclk;
 	rdev->pm.default_mclk = rdev->clock.default_mclk;
 	rdev->pm.current_sclk = rdev->clock.default_sclk;
 	if (ret) {
 		rdev->pm.dpm_enabled = false;
 		if ((rdev->family >= CHIP_BARTS) &&
-		    (rdev->family <= CHIP_HAINAN) &&
+		    (rdev->family <= CHIP_CAYMAN) &&
 		    rdev->mc_fw) {
 			if (rdev->pm.default_vddc)
 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,

drivers/gpu/drm/radeon/radeon_ring.c+5−3

 	 * packet that is the root issue
 	 */
 	i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
-	for (j = 0; j <= (count + 32); j++) {
+	if (ring->ready) {
-		seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
+		for (j = 0; j <= (count + 32); j++) {
-		i = (i + 1) & ring->ptr_mask;
+			seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
+			i = (i + 1) & ring->ptr_mask;
+		}
 	}
 	return 0;
 }

drivers/gpu/drm/radeon/radeon_trace.h+20−7

@@ -27,6 +27,26 @@ TRACE_EVENT(radeon_bo_create, · 26 unmodified lines
27	TP_printk("bo=%p, pages=%u", __entry->bo, __entry->pages)	27	TP_printk("bo=%p, pages=%u", __entry->bo, __entry->pages)
28	);	28	);
29		29
		30	TRACE_EVENT(radeon_cs,
		31	TP_PROTO(struct radeon_cs_parser *p),
		32	TP_ARGS(p),
		33	TP_STRUCT__entry(
		34	__field(u32, ring)
		35	__field(u32, dw)
		36	__field(u32, fences)
		37	),
		38
		39	TP_fast_assign(
		40	__entry->ring = p->ring;
		41	__entry->dw = p->chunks[p->chunk_ib_idx].length_dw;
		42	__entry->fences = radeon_fence_count_emitted(
		43	p->rdev, p->ring);
		44	),
		45	TP_printk("ring=%u, dw=%u, fences=%u",
		46	__entry->ring, __entry->dw,
		47	__entry->fences)
		48	);
		49
30	DECLARE_EVENT_CLASS(radeon_fence_request,	50	DECLARE_EVENT_CLASS(radeon_fence_request,
31		51
32	TP_PROTO(struct drm_device *dev, u32 seqno),	52	TP_PROTO(struct drm_device *dev, u32 seqno),
@@ -53,13 +73,6 @@ DEFINE_EVENT(radeon_fence_request, radeon_fence_emit, · 20 unmodified lines
53	TP_ARGS(dev, seqno)	73	TP_ARGS(dev, seqno)
54	);	74	);
55		75
56	DEFINE_EVENT(radeon_fence_request, radeon_fence_retire,
57
58	TP_PROTO(struct drm_device *dev, u32 seqno),
59
60	TP_ARGS(dev, seqno)
61	);
62
63	DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_begin,	76	DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_begin,
64		77
65	TP_PROTO(struct drm_device *dev, u32 seqno),	78	TP_PROTO(struct drm_device *dev, u32 seqno),

drivers/gpu/drm/radeon/radeon_uvd.c+1−2

@@ -476,8 +476,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, · 475 unmodified lines
476	return -EINVAL;	476	return -EINVAL;
477	}	477	}
478		478
479	/* TODO: is this still necessary on NI+ ? */	479	if (p->rdev->family < CHIP_PALM && (cmd == 0 \|\| cmd == 0x3) &&
480	if ((cmd == 0 \|\| cmd == 0x3) &&
481	(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {	480	(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
482	DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",	481	DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
483	start, end);	482	start, end);

drivers/gpu/drm/radeon/rs400.c+7−0

 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 {
+	unsigned long flags;
 	uint32_t r;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
 	r = RREG32(RS480_NB_MC_DATA);
 	WREG32(RS480_NB_MC_INDEX, 0xff);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 	return r;
 }
 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
 	WREG32(RS480_NB_MC_DATA, (v));
 	WREG32(RS480_NB_MC_INDEX, 0xff);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 }
 #if defined(CONFIG_DEBUG_FS)

drivers/gpu/drm/radeon/rs600.c+11−1

 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 {
+	unsigned long flags;
+	u32 r;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 		S_000070_MC_IND_CITF_ARB0(1));
-	return RREG32(R_000074_MC_IND_DATA);
+	r = RREG32(R_000074_MC_IND_DATA);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
+	return r;
 }
 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 		S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 	WREG32(R_000074_MC_IND_DATA, v);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 }
 static void rs600_debugfs(struct radeon_device *rdev)

drivers/gpu/drm/radeon/rs690.c+7−0

 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 {
+	unsigned long flags;
 	uint32_t r;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 	r = RREG32(R_00007C_MC_DATA);
 	WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 	return r;
 }
 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 		S_000078_MC_IND_WR_EN(1));
 	WREG32(R_00007C_MC_DATA, v);
 	WREG32(R_000078_MC_INDEX, 0x7F);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 }
 static void rs690_mc_program(struct radeon_device *rdev)

drivers/gpu/drm/radeon/rs780_dpm.c+92−20

@@ -62,9 +62,7 @@ static void rs780_get_pm_mode_parameters(struct radeon_device *rdev) · 61 unmodified lines
62	radeon_crtc = to_radeon_crtc(crtc);	62	radeon_crtc = to_radeon_crtc(crtc);
63	pi->crtc_id = radeon_crtc->crtc_id;	63	pi->crtc_id = radeon_crtc->crtc_id;
64	if (crtc->mode.htotal && crtc->mode.vtotal)	64	if (crtc->mode.htotal && crtc->mode.vtotal)
65	pi->refresh_rate =	65	pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
66	(crtc->mode.clock * 1000) /
67	(crtc->mode.htotal * crtc->mode.vtotal);
68	break;	66	break;
69	}	67	}
70	}	68	}
@@ -376,9 +374,8 @@ static void rs780_disable_vbios_powersaving(struct radeon_device *rdev) · 305 unmodified lines
376	WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);	374	WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
377	}	375	}
378		376
379	static void rs780_force_voltage_to_high(struct radeon_device *rdev)	377	static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
380	{	378	{
381	struct igp_power_info *pi = rs780_get_pi(rdev);
382	struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);	379	struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
383		380
384	if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&	381	if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
@@ -390,7 +387,7 @@ static void rs780_force_voltage_to_high(struct radeon_device *rdev) · 5 unmodified lines
390	udelay(1);	387	udelay(1);
391		388
392	WREG32_P(FVTHROT_PWM_CTRL_REG0,	389	WREG32_P(FVTHROT_PWM_CTRL_REG0,
393	STARTING_PWM_HIGHTIME(pi->max_voltage),	390	STARTING_PWM_HIGHTIME(voltage),
394	~STARTING_PWM_HIGHTIME_MASK);	391	~STARTING_PWM_HIGHTIME_MASK);
395		392
396	WREG32_P(FVTHROT_PWM_CTRL_REG0,	393	WREG32_P(FVTHROT_PWM_CTRL_REG0,
@@ -404,6 +401,26 @@ static void rs780_force_voltage_to_high(struct radeon_device *rdev) · 7 unmodified lines
404	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);	401	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
405	}	402	}
406		403
		404	static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
		405	{
		406	struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
		407
		408	if (current_state->sclk_low == current_state->sclk_high)
		409	return;
		410
		411	WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
		412
		413	WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
		414	~FORCED_FEEDBACK_DIV_MASK);
		415	WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
		416	~STARTING_FEEDBACK_DIV_MASK);
		417	WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
		418
		419	udelay(100);
		420
		421	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
		422	}
		423
407	static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,	424	static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
408	struct radeon_ps *new_ps,	425	struct radeon_ps *new_ps,
409	struct radeon_ps *old_ps)	426	struct radeon_ps *old_ps)
@@ -432,17 +449,13 @@ static int rs780_set_engine_clock_scaling(struct radeon_device *rdev, · 22 unmodified lines
432	if (ret)	449	if (ret)
433	return ret;	450	return ret;
434		451
435	WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);	452	if ((min_dividers.ref_div != max_dividers.ref_div) \|\|
436		453	(min_dividers.post_div != max_dividers.post_div) \|\|
437	WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(max_dividers.fb_div),	454	(max_dividers.ref_div != current_max_dividers.ref_div) \|\|
438	~FORCED_FEEDBACK_DIV_MASK);	455	(max_dividers.post_div != current_max_dividers.post_div))
439	WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(max_dividers.fb_div),	456	return -EINVAL;
440	~STARTING_FEEDBACK_DIV_MASK);
441	WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
442
443	udelay(100);
444		457
445	WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);	458	rs780_force_fbdiv(rdev, max_dividers.fb_div);
446		459
447	if (max_dividers.fb_div > min_dividers.fb_div) {	460	if (max_dividers.fb_div > min_dividers.fb_div) {
448	WREG32_P(FVTHROT_FBDIV_REG0,	461	WREG32_P(FVTHROT_FBDIV_REG0,
@@ -486,6 +499,9 @@ static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev, · 37 unmodified lines
486	(new_state->sclk_low == old_state->sclk_low))	499	(new_state->sclk_low == old_state->sclk_low))
487	return;	500	return;
488		501
		502	if (new_state->sclk_high == new_state->sclk_low)
		503	return;
		504
489	rs780_clk_scaling_enable(rdev, true);	505	rs780_clk_scaling_enable(rdev, true);
490	}	506	}
491		507
@@ -649,7 +665,7 @@ int rs780_dpm_set_power_state(struct radeon_device *rdev) · 157 unmodified lines
649	rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);	665	rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
650		666
651	if (pi->voltage_control) {	667	if (pi->voltage_control) {
652	rs780_force_voltage_to_high(rdev);	668	rs780_force_voltage(rdev, pi->max_voltage);
653	mdelay(5);	669	mdelay(5);
654	}	670	}
655		671
@@ -717,14 +733,18 @@ static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev, · 61 unmodified lines
717	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {	733	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
718	rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);	734	rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
719	rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);	735	rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
720	} else if (r600_is_uvd_state(rps->class, rps->class2)) {
721	rps->vclk = RS780_DEFAULT_VCLK_FREQ;
722	rps->dclk = RS780_DEFAULT_DCLK_FREQ;
723	} else {	736	} else {
724	rps->vclk = 0;	737	rps->vclk = 0;
725	rps->dclk = 0;	738	rps->dclk = 0;
726	}	739	}
727		740
		741	if (r600_is_uvd_state(rps->class, rps->class2)) {
		742	if ((rps->vclk == 0) \|\| (rps->dclk == 0)) {
		743	rps->vclk = RS780_DEFAULT_VCLK_FREQ;
		744	rps->dclk = RS780_DEFAULT_DCLK_FREQ;
		745	}
		746	}
		747
728	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)	748	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
729	rdev->pm.dpm.boot_ps = rps;	749	rdev->pm.dpm.boot_ps = rps;
730	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)	750	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
@@ -986,3 +1006,55 @@ void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rde · 255 unmodified lines
986	seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n",	1006	seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n",
987	ps->sclk_high, ps->max_voltage);	1007	ps->sclk_high, ps->max_voltage);
988	}	1008	}
		1009
		1010	int rs780_dpm_force_performance_level(struct radeon_device *rdev,
		1011	enum radeon_dpm_forced_level level)
		1012	{
		1013	struct igp_power_info *pi = rs780_get_pi(rdev);
		1014	struct radeon_ps *rps = rdev->pm.dpm.current_ps;
		1015	struct igp_ps *ps = rs780_get_ps(rps);
		1016	struct atom_clock_dividers dividers;
		1017	int ret;
		1018
		1019	rs780_clk_scaling_enable(rdev, false);
		1020	rs780_voltage_scaling_enable(rdev, false);
		1021
		1022	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
		1023	if (pi->voltage_control)
		1024	rs780_force_voltage(rdev, pi->max_voltage);
		1025
		1026	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		1027	ps->sclk_high, false, &dividers);
		1028	if (ret)
		1029	return ret;
		1030
		1031	rs780_force_fbdiv(rdev, dividers.fb_div);
		1032	} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
		1033	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
		1034	ps->sclk_low, false, &dividers);
		1035	if (ret)
		1036	return ret;
		1037
		1038	rs780_force_fbdiv(rdev, dividers.fb_div);
		1039
		1040	if (pi->voltage_control)
		1041	rs780_force_voltage(rdev, pi->min_voltage);
		1042	} else {
		1043	if (pi->voltage_control)
		1044	rs780_force_voltage(rdev, pi->max_voltage);
		1045
		1046	if (ps->sclk_high != ps->sclk_low) {
		1047	WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
		1048	rs780_clk_scaling_enable(rdev, true);
		1049	}
		1050
		1051	if (pi->voltage_control) {
		1052	rs780_voltage_scaling_enable(rdev, true);
		1053	rs780_enable_voltage_scaling(rdev, rps);
		1054	}
		1055	}
		1056
		1057	rdev->pm.dpm.forced_level = level;
		1058
		1059	return 0;
		1060	}

drivers/gpu/drm/radeon/rv515.c+8−0

 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 {
+	unsigned long flags;
 	uint32_t r;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 	r = RREG32(MC_IND_DATA);
 	WREG32(MC_IND_INDEX, 0);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 	return r;
 }
 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
+	unsigned long flags;
+	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 	WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 	WREG32(MC_IND_DATA, (v));
 	WREG32(MC_IND_INDEX, 0);
+	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 }
 #if defined(CONFIG_DEBUG_FS)

drivers/gpu/drm/radeon/rv6xx_dpm.c+0−2

@@ -1758,8 +1758,6 @@ int rv6xx_dpm_set_power_state(struct radeon_device *rdev) · 1757 unmodified lines
1758		1758
1759	rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);	1759	rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1760		1760
1761	rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1762
1763	return 0;	1761	return 0;
1764	}	1762	}
1765		1763

drivers/gpu/drm/radeon/rv770_dpm.c+7−9

 		rv770_program_dcodt_after_state_switch(rdev, new_ps, old_ps);
 	rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
-	ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
-	if (ret) {
-		DRM_ERROR("rv770_dpm_force_performance_level failed\n");
-		return ret;
-	}
 	return 0;
 }
 	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
-	} else if (r600_is_uvd_state(rps->class, rps->class2)) {
-		rps->vclk = RV770_DEFAULT_VCLK_FREQ;
-		rps->dclk = RV770_DEFAULT_DCLK_FREQ;
 	} else {
 		rps->vclk = 0;
 		rps->dclk = 0;
 	}
+	if (r600_is_uvd_state(rps->class, rps->class2)) {
+		if ((rps->vclk == 0) || (rps->dclk == 0)) {
+			rps->vclk = RV770_DEFAULT_VCLK_FREQ;
+			rps->dclk = RV770_DEFAULT_DCLK_FREQ;
+		}
+	}
 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
 		rdev->pm.dpm.boot_ps = rps;
 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)

drivers/gpu/drm/radeon/rv770_smc.c+27−17

@@ -274,8 +274,8 @@ static const u8 cayman_smc_int_vectors[] = · 273 unmodified lines
274	0x08, 0x72, 0x08, 0x72	274	0x08, 0x72, 0x08, 0x72
275	};	275	};
276		276
277	int rv770_set_smc_sram_address(struct radeon_device *rdev,	277	static int rv770_set_smc_sram_address(struct radeon_device *rdev,
278	u16 smc_address, u16 limit)	278	u16 smc_address, u16 limit)
279	{	279	{
280	u32 addr;	280	u32 addr;
281		281
@@ -296,9 +296,10 @@ int rv770_copy_bytes_to_smc(struct radeon_device *rdev, · 14 unmodified lines
296	u16 smc_start_address, const u8 *src,	296	u16 smc_start_address, const u8 *src,
297	u16 byte_count, u16 limit)	297	u16 byte_count, u16 limit)
298	{	298	{
		299	unsigned long flags;
299	u32 data, original_data, extra_shift;	300	u32 data, original_data, extra_shift;
300	u16 addr;	301	u16 addr;
301	int ret;	302	int ret = 0;
302		303
303	if (smc_start_address & 3)	304	if (smc_start_address & 3)
304	return -EINVAL;	305	return -EINVAL;
@@ -307,13 +308,14 @@ int rv770_copy_bytes_to_smc(struct radeon_device *rdev, · 2 unmodified lines
307		308
308	addr = smc_start_address;	309	addr = smc_start_address;
309		310
		311	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
310	while (byte_count >= 4) {	312	while (byte_count >= 4) {
311	/* SMC address space is BE */	313	/* SMC address space is BE */
312	data = (src[0] << 24) \| (src[1] << 16) \| (src[2] << 8) \| src[3];	314	data = (src[0] << 24) \| (src[1] << 16) \| (src[2] << 8) \| src[3];
313		315
314	ret = rv770_set_smc_sram_address(rdev, addr, limit);	316	ret = rv770_set_smc_sram_address(rdev, addr, limit);
315	if (ret)	317	if (ret)
316	return ret;	318	goto done;
317		319
318	WREG32(SMC_SRAM_DATA, data);	320	WREG32(SMC_SRAM_DATA, data);
319		321
@@ -328,7 +330,7 @@ int rv770_copy_bytes_to_smc(struct radeon_device *rdev, · 8 unmodified lines
328		330
329	ret = rv770_set_smc_sram_address(rdev, addr, limit);	331	ret = rv770_set_smc_sram_address(rdev, addr, limit);
330	if (ret)	332	if (ret)
331	return ret;	333	goto done;
332		334
333	original_data = RREG32(SMC_SRAM_DATA);	335	original_data = RREG32(SMC_SRAM_DATA);
334		336
@@ -346,12 +348,15 @@ int rv770_copy_bytes_to_smc(struct radeon_device *rdev, · 11 unmodified lines
346		348
347	ret = rv770_set_smc_sram_address(rdev, addr, limit);	349	ret = rv770_set_smc_sram_address(rdev, addr, limit);
348	if (ret)	350	if (ret)
349	return ret;	351	goto done;
350		352
351	WREG32(SMC_SRAM_DATA, data);	353	WREG32(SMC_SRAM_DATA, data);
352	}	354	}
353		355
354	return 0;	356	done:
		357	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
		358
		359	return ret;
355	}	360	}
356		361
357	static int rv770_program_interrupt_vectors(struct radeon_device *rdev,	362	static int rv770_program_interrupt_vectors(struct radeon_device *rdev,
@@ -461,12 +466,15 @@ PPSMC_Result rv770_wait_for_smc_inactive(struct radeon_device *rdev) · 103 unmodified lines
461		466
462	static void rv770_clear_smc_sram(struct radeon_device *rdev, u16 limit)	467	static void rv770_clear_smc_sram(struct radeon_device *rdev, u16 limit)
463	{	468	{
		469	unsigned long flags;
464	u16 i;	470	u16 i;
465		471
		472	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
466	for (i = 0; i < limit; i += 4) {	473	for (i = 0; i < limit; i += 4) {
467	rv770_set_smc_sram_address(rdev, i, limit);	474	rv770_set_smc_sram_address(rdev, i, limit);
468	WREG32(SMC_SRAM_DATA, 0);	475	WREG32(SMC_SRAM_DATA, 0);
469	}	476	}
		477	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
470	}	478	}
471		479
472	int rv770_load_smc_ucode(struct radeon_device *rdev,	480	int rv770_load_smc_ucode(struct radeon_device *rdev,
@@ -595,27 +603,29 @@ int rv770_load_smc_ucode(struct radeon_device *rdev, · 122 unmodified lines
595	int rv770_read_smc_sram_dword(struct radeon_device *rdev,	603	int rv770_read_smc_sram_dword(struct radeon_device *rdev,
596	u16 smc_address, u32 *value, u16 limit)	604	u16 smc_address, u32 *value, u16 limit)
597	{	605	{
		606	unsigned long flags;
598	int ret;	607	int ret;
599		608
		609	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
600	ret = rv770_set_smc_sram_address(rdev, smc_address, limit);	610	ret = rv770_set_smc_sram_address(rdev, smc_address, limit);
601	if (ret)	611	if (ret == 0)
602	return ret;	612	*value = RREG32(SMC_SRAM_DATA);
603		613	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
604	*value = RREG32(SMC_SRAM_DATA);
605		614
606	return 0;	615	return ret;
607	}	616	}
608		617
609	int rv770_write_smc_sram_dword(struct radeon_device *rdev,	618	int rv770_write_smc_sram_dword(struct radeon_device *rdev,
610	u16 smc_address, u32 value, u16 limit)	619	u16 smc_address, u32 value, u16 limit)
611	{	620	{
		621	unsigned long flags;
612	int ret;	622	int ret;
613		623
		624	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
614	ret = rv770_set_smc_sram_address(rdev, smc_address, limit);	625	ret = rv770_set_smc_sram_address(rdev, smc_address, limit);
615	if (ret)	626	if (ret == 0)
616	return ret;	627	WREG32(SMC_SRAM_DATA, value);
		628	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
617		629
618	WREG32(SMC_SRAM_DATA, value);	630	return ret;
619
620	return 0;
621	}	631	}

drivers/gpu/drm/radeon/rv770_smc.h+0−2

@@ -187,8 +187,6 @@ typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE; · 186 unmodified lines
187	#define RV770_SMC_SOFT_REGISTER_uvd_enabled 0x9C	187	#define RV770_SMC_SOFT_REGISTER_uvd_enabled 0x9C
188	#define RV770_SMC_SOFT_REGISTER_is_asic_lombok 0xA0	188	#define RV770_SMC_SOFT_REGISTER_is_asic_lombok 0xA0
189		189
190	int rv770_set_smc_sram_address(struct radeon_device *rdev,
191	u16 smc_address, u16 limit);
192	int rv770_copy_bytes_to_smc(struct radeon_device *rdev,	190	int rv770_copy_bytes_to_smc(struct radeon_device *rdev,
193	u16 smc_start_address, const u8 *src,	191	u16 smc_start_address, const u8 *src,
194	u16 byte_count, u16 limit);	192	u16 byte_count, u16 limit);

drivers/gpu/drm/radeon/rv770d.h+1−1

@@ -852,7 +852,7 @@ · 851 unmodified lines
852	#define AFMT_VBI_PACKET_CONTROL 0x7608	852	#define AFMT_VBI_PACKET_CONTROL 0x7608
853	# define AFMT_GENERIC0_UPDATE (1 << 2)	853	# define AFMT_GENERIC0_UPDATE (1 << 2)
854	#define AFMT_INFOFRAME_CONTROL0 0x760c	854	#define AFMT_INFOFRAME_CONTROL0 0x760c
855	# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */	855	# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
856	# define AFMT_AUDIO_INFO_UPDATE (1 << 7)	856	# define AFMT_AUDIO_INFO_UPDATE (1 << 7)
857	# define AFMT_MPEG_INFO_UPDATE (1 << 10)	857	# define AFMT_MPEG_INFO_UPDATE (1 << 10)
858	#define AFMT_GENERIC0_7 0x7610	858	#define AFMT_GENERIC0_7 0x7610

drivers/gpu/drm/radeon/si.c+17−4

 			       uint64_t pe,
 			       uint64_t addr, unsigned count,
 			       uint32_t incr, uint32_t flags);
+static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
+					 bool enable);
 static const u32 verde_rlc_save_restore_register_list[] =
 {
 	u32 rb_bufsz;
 	int r;
+	si_enable_gui_idle_interrupt(rdev, false);
 	WREG32(CP_SEM_WAIT_TIMER, 0x0);
 	WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
 		rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
 	}
+	si_enable_gui_idle_interrupt(rdev, true);
 	return 0;
 }
 {
 	u32 tmp;
-	if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
+	if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
 		tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
 		WREG32(RLC_TTOP_D, tmp);
 		  u32 block, bool enable)
 {
 	if (block & RADEON_CG_BLOCK_GFX) {
+		si_enable_gui_idle_interrupt(rdev, false);
 		/* order matters! */
 		if (enable) {
 			si_enable_mgcg(rdev, true);
 			si_enable_cgcg(rdev, false);
 			si_enable_mgcg(rdev, false);
 		}
+		si_enable_gui_idle_interrupt(rdev, true);
 	}
 	if (block & RADEON_CG_BLOCK_MC) {
 			si_init_dma_pg(rdev);
 		}
 		si_init_ao_cu_mask(rdev);
-		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
+		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
 			si_init_gfx_cgpg(rdev);
 		}
 		si_enable_dma_pg(rdev, true);
 {
 	u32 tmp;
-	WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+	tmp = RREG32(CP_INT_CNTL_RING0) &
+		(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+	WREG32(CP_INT_CNTL_RING0, tmp);
 	WREG32(CP_INT_CNTL_RING1, 0);
 	WREG32(CP_INT_CNTL_RING2, 0);
 	tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
 int si_irq_set(struct radeon_device *rdev)
 {
-	u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
+	u32 cp_int_cntl;
 	u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
 	u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
 	u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
 		return 0;
 	}
+	cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
+		(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
 	if (!ASIC_IS_NODCE(rdev)) {
 		hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
 		hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/si_dpm.c+24−6

 	bool disable_sclk_switching = false;
 	u32 mclk, sclk;
 	u16 vddc, vddci;
+	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
 	int i;
 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 		}
 	}
+	/* limit clocks to max supported clocks based on voltage dependency tables */
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
+							&max_sclk_vddc);
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
+							&max_mclk_vddci);
+	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
+							&max_mclk_vddc);
+	for (i = 0; i < ps->performance_level_count; i++) {
+		if (max_sclk_vddc) {
+			if (ps->performance_levels[i].sclk > max_sclk_vddc)
+				ps->performance_levels[i].sclk = max_sclk_vddc;
+		}
+		if (max_mclk_vddci) {
+			if (ps->performance_levels[i].mclk > max_mclk_vddci)
+				ps->performance_levels[i].mclk = max_mclk_vddci;
+		}
+		if (max_mclk_vddc) {
+			if (ps->performance_levels[i].mclk > max_mclk_vddc)
+				ps->performance_levels[i].mclk = max_mclk_vddc;
+		}
+	}
 	/* XXX validate the min clocks required for display */
 	if (disable_mclk_switching) {
 		return ret;
 	}
-	ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
-	if (ret) {
-		DRM_ERROR("si_dpm_force_performance_level failed\n");
-		return ret;
-	}
 	si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
 			    RADEON_CG_BLOCK_MC |
 			    RADEON_CG_BLOCK_SDMA |

drivers/gpu/drm/radeon/si_smc.c+28−15

@@ -29,8 +29,8 @@ · 28 unmodified lines
29	#include "ppsmc.h"	29	#include "ppsmc.h"
30	#include "radeon_ucode.h"	30	#include "radeon_ucode.h"
31		31
32	int si_set_smc_sram_address(struct radeon_device *rdev,	32	static int si_set_smc_sram_address(struct radeon_device *rdev,
33	u32 smc_address, u32 limit)	33	u32 smc_address, u32 limit)
34	{	34	{
35	if (smc_address & 3)	35	if (smc_address & 3)
36	return -EINVAL;	36	return -EINVAL;
@@ -47,7 +47,8 @@ int si_copy_bytes_to_smc(struct radeon_device *rdev, · 10 unmodified lines
47	u32 smc_start_address,	47	u32 smc_start_address,
48	const u8 *src, u32 byte_count, u32 limit)	48	const u8 *src, u32 byte_count, u32 limit)
49	{	49	{
50	int ret;	50	unsigned long flags;
		51	int ret = 0;
51	u32 data, original_data, addr, extra_shift;	52	u32 data, original_data, addr, extra_shift;
52		53
53	if (smc_start_address & 3)	54	if (smc_start_address & 3)
@@ -57,13 +58,14 @@ int si_copy_bytes_to_smc(struct radeon_device *rdev, · 3 unmodified lines
57		58
58	addr = smc_start_address;	59	addr = smc_start_address;
59		60
		61	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
60	while (byte_count >= 4) {	62	while (byte_count >= 4) {
61	/* SMC address space is BE */	63	/* SMC address space is BE */
62	data = (src[0] << 24) \| (src[1] << 16) \| (src[2] << 8) \| src[3];	64	data = (src[0] << 24) \| (src[1] << 16) \| (src[2] << 8) \| src[3];
63		65
64	ret = si_set_smc_sram_address(rdev, addr, limit);	66	ret = si_set_smc_sram_address(rdev, addr, limit);
65	if (ret)	67	if (ret)
66	return ret;	68	goto done;
67		69
68	WREG32(SMC_IND_DATA_0, data);	70	WREG32(SMC_IND_DATA_0, data);
69		71
@@ -78,7 +80,7 @@ int si_copy_bytes_to_smc(struct radeon_device *rdev, · 8 unmodified lines
78		80
79	ret = si_set_smc_sram_address(rdev, addr, limit);	81	ret = si_set_smc_sram_address(rdev, addr, limit);
80	if (ret)	82	if (ret)
81	return ret;	83	goto done;
82		84
83	original_data = RREG32(SMC_IND_DATA_0);	85	original_data = RREG32(SMC_IND_DATA_0);
84		86
@@ -96,11 +98,15 @@ int si_copy_bytes_to_smc(struct radeon_device *rdev, · 11 unmodified lines
96		98
97	ret = si_set_smc_sram_address(rdev, addr, limit);	99	ret = si_set_smc_sram_address(rdev, addr, limit);
98	if (ret)	100	if (ret)
99	return ret;	101	goto done;
100		102
101	WREG32(SMC_IND_DATA_0, data);	103	WREG32(SMC_IND_DATA_0, data);
102	}	104	}
103	return 0;	105
		106	done:
		107	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
		108
		109	return ret;
104	}	110	}
105		111
106	void si_start_smc(struct radeon_device *rdev)	112	void si_start_smc(struct radeon_device *rdev)
@@ -203,6 +209,7 @@ PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev) · 96 unmodified lines
203		209
204	int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)	210	int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
205	{	211	{
		212	unsigned long flags;
206	u32 ucode_start_address;	213	u32 ucode_start_address;
207	u32 ucode_size;	214	u32 ucode_size;
208	const u8 *src;	215	const u8 *src;
@@ -241,6 +248,7 @@ int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) · 32 unmodified lines
241	return -EINVAL;	248	return -EINVAL;
242		249
243	src = (const u8 *)rdev->smc_fw->data;	250	src = (const u8 *)rdev->smc_fw->data;
		251	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
244	WREG32(SMC_IND_INDEX_0, ucode_start_address);	252	WREG32(SMC_IND_INDEX_0, ucode_start_address);
245	WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);	253	WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
246	while (ucode_size >= 4) {	254	while (ucode_size >= 4) {
@@ -253,6 +261,7 @@ int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) · 6 unmodified lines
253	ucode_size -= 4;	261	ucode_size -= 4;
254	}	262	}
255	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);	263	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
		264	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
256		265
257	return 0;	266	return 0;
258	}	267	}
@@ -260,25 +269,29 @@ int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) · 1 unmodified line
260	int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,	269	int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
261	u32 *value, u32 limit)	270	u32 *value, u32 limit)
262	{	271	{
		272	unsigned long flags;
263	int ret;	273	int ret;
264		274
		275	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
265	ret = si_set_smc_sram_address(rdev, smc_address, limit);	276	ret = si_set_smc_sram_address(rdev, smc_address, limit);
266	if (ret)	277	if (ret == 0)
267	return ret;	278	*value = RREG32(SMC_IND_DATA_0);
		279	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
268		280
269	*value = RREG32(SMC_IND_DATA_0);	281	return ret;
270	return 0;
271	}	282	}
272		283
273	int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,	284	int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
274	u32 value, u32 limit)	285	u32 value, u32 limit)
275	{	286	{
		287	unsigned long flags;
276	int ret;	288	int ret;
277		289
		290	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
278	ret = si_set_smc_sram_address(rdev, smc_address, limit);	291	ret = si_set_smc_sram_address(rdev, smc_address, limit);
279	if (ret)	292	if (ret == 0)
280	return ret;	293	WREG32(SMC_IND_DATA_0, value);
		294	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
281		295
282	WREG32(SMC_IND_DATA_0, value);	296	return ret;
283	return 0;
284	}	297	}

drivers/gpu/drm/radeon/sumo_dpm.c+0−2

@@ -1319,8 +1319,6 @@ int sumo_dpm_set_power_state(struct radeon_device *rdev) · 1318 unmodified lines
1319	if (pi->enable_dpm)	1319	if (pi->enable_dpm)
1320	sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);	1320	sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1321		1321
1322	rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1323
1324	return 0;	1322	return 0;
1325	}	1323	}
1326		1324

drivers/gpu/drm/radeon/trinity_dpm.c+16−1

 	pi->requested_rps.ps_priv = &pi->requested_ps;
 }
+void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
+{
+	struct trinity_power_info *pi = trinity_get_pi(rdev);
+	if (pi->enable_bapm) {
+		trinity_acquire_mutex(rdev);
+		trinity_dpm_bapm_enable(rdev, enable);
+		trinity_release_mutex(rdev);
+	}
+}
 int trinity_dpm_enable(struct radeon_device *rdev)
 {
 	struct trinity_power_info *pi = trinity_get_pi(rdev);
 	trinity_program_sclk_dpm(rdev);
 	trinity_start_dpm(rdev);
 	trinity_wait_for_dpm_enabled(rdev);
+	trinity_dpm_bapm_enable(rdev, false);
 	trinity_release_mutex(rdev);
 	if (rdev->irq.installed &&
 		trinity_release_mutex(rdev);
 		return;
 	}
+	trinity_dpm_bapm_enable(rdev, false);
 	trinity_disable_clock_power_gating(rdev);
 	sumo_clear_vc(rdev);
 	trinity_wait_for_level_0(rdev);
 	trinity_acquire_mutex(rdev);
 	if (pi->enable_dpm) {
+		if (pi->enable_bapm)
+			trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power);
 		trinity_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
 		trinity_enable_power_level_0(rdev);
 		trinity_force_level_0(rdev);
 		trinity_force_level_0(rdev);
 		trinity_unforce_levels(rdev);
 		trinity_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
-		rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
 	}
 	trinity_release_mutex(rdev);
 	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
 		pi->at[i] = TRINITY_AT_DFLT;
+	pi->enable_bapm = true;
 	pi->enable_nbps_policy = true;
 	pi->enable_sclk_ds = true;
 	pi->enable_gfx_power_gating = true;

drivers/gpu/drm/radeon/trinity_dpm.h+2−0

 	bool enable_auto_thermal_throttling;
 	bool enable_dpm;
 	bool enable_sclk_ds;
+	bool enable_bapm;
 	bool uvd_dpm;
 	struct radeon_ps current_rps;
 	struct trinity_ps current_ps;
 #define TRINITY_AT_DFLT            30
 /* trinity_smc.c */
+int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable);
 int trinity_dpm_config(struct radeon_device *rdev, bool enable);
 int trinity_uvd_dpm_config(struct radeon_device *rdev);
 int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);

drivers/gpu/drm/radeon/trinity_smc.c+8−0

@@ -56,6 +56,14 @@ static int trinity_notify_message_to_smu(struct radeon_device *rdev, u32 id) · 55 unmodified lines
56	return 0;	56	return 0;
57	}	57	}
58		58
		59	int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable)
		60	{
		61	if (enable)
		62	return trinity_notify_message_to_smu(rdev, PPSMC_MSG_EnableBAPM);
		63	else
		64	return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DisableBAPM);
		65	}
		66
59	int trinity_dpm_config(struct radeon_device *rdev, bool enable)	67	int trinity_dpm_config(struct radeon_device *rdev, bool enable)
60	{	68	{
61	if (enable)	69	if (enable)

drivers/gpu/drm/radeon/uvd_v1_0.c+2−2

@@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev) · 211 unmodified lines
212	/* enable VCPU clock */	212	/* enable VCPU clock */
213	WREG32(UVD_VCPU_CNTL, 1 << 9);	213	WREG32(UVD_VCPU_CNTL, 1 << 9);
214		214
215	/* enable UMC */	215	/* enable UMC and NC0 */
216	WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));	216	WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) \| (1 << 13)));
217		217
218	/* boot up the VCPU */	218	/* boot up the VCPU */
219	WREG32(UVD_SOFT_RESET, 0);	219	WREG32(UVD_SOFT_RESET, 0);

drivers/gpu/drm/ttm/ttm_object.c+1−1

@@ -218,7 +218,7 @@ struct ttm_base_object ttm_base_object_lookup(struct ttm_object_file tfile, · 217 unmodified lines
218	uint32_t key)	218	uint32_t key)
219	{	219	{
220	struct ttm_object_device *tdev = tfile->tdev;	220	struct ttm_object_device *tdev = tfile->tdev;
221	struct ttm_base_object *base;	221	struct ttm_base_object *uninitialized_var(base);
222	struct drm_hash_item *hash;	222	struct drm_hash_item *hash;
223	int ret;	223	int ret;
224		224

drivers/gpu/drm/ttm/ttm_tt.c+1−1

@@ -170,7 +170,7 @@ void ttm_tt_destroy(struct ttm_tt *ttm) · 169 unmodified lines
170	ttm_tt_unbind(ttm);	170	ttm_tt_unbind(ttm);
171	}	171	}
172		172
173	if (likely(ttm->pages != NULL)) {	173	if (ttm->state == tt_unbound) {
174	ttm->bdev->driver->ttm_tt_unpopulate(ttm);	174	ttm->bdev->driver->ttm_tt_unpopulate(ttm);
175	}	175	}
176		176

drivers/gpu/drm/udl/udl_gem.c+0−1

@@ -97,7 +97,6 @@ int udl_gem_fault(struct vm_area_struct vma, struct vm_fault vmf) · 96 unmodified lines
97	ret = vm_insert_page(vma, (unsigned long)vmf->virtual_address, page);	97	ret = vm_insert_page(vma, (unsigned long)vmf->virtual_address, page);
98	switch (ret) {	98	switch (ret) {
99	case -EAGAIN:	99	case -EAGAIN:
100	set_need_resched();
101	case 0:	100	case 0:
102	case -ERESTARTSYS:	101	case -ERESTARTSYS:
103	return VM_FAULT_NOPAGE;	102	return VM_FAULT_NOPAGE;

drivers/hv/connection.c+1−1

@@ -195,7 +195,7 @@ int vmbus_connect(void) · 194 unmodified lines
195		195
196	do {	196	do {
197	ret = vmbus_negotiate_version(msginfo, version);	197	ret = vmbus_negotiate_version(msginfo, version);
198	if (ret)	198	if (ret == -ETIMEDOUT)
199	goto cleanup;	199	goto cleanup;
200		200
201	if (vmbus_connection.conn_state == CONNECTED)	201	if (vmbus_connection.conn_state == CONNECTED)

drivers/hv/hv_kvp.c+26−12

@@ -32,13 +32,17 @@ · 31 unmodified lines
32	/*	32	/*
33	* Pre win8 version numbers used in ws2008 and ws 2008 r2 (win7)	33	* Pre win8 version numbers used in ws2008 and ws 2008 r2 (win7)
34	*/	34	*/
		35	#define WS2008_SRV_MAJOR 1
		36	#define WS2008_SRV_MINOR 0
		37	#define WS2008_SRV_VERSION (WS2008_SRV_MAJOR << 16 \| WS2008_SRV_MINOR)
		38
35	#define WIN7_SRV_MAJOR 3	39	#define WIN7_SRV_MAJOR 3
36	#define WIN7_SRV_MINOR 0	40	#define WIN7_SRV_MINOR 0
37	#define WIN7_SRV_MAJOR_MINOR (WIN7_SRV_MAJOR << 16 \| WIN7_SRV_MINOR)	41	#define WIN7_SRV_VERSION (WIN7_SRV_MAJOR << 16 \| WIN7_SRV_MINOR)
38		42
39	#define WIN8_SRV_MAJOR 4	43	#define WIN8_SRV_MAJOR 4
40	#define WIN8_SRV_MINOR 0	44	#define WIN8_SRV_MINOR 0
41	#define WIN8_SRV_MAJOR_MINOR (WIN8_SRV_MAJOR << 16 \| WIN8_SRV_MINOR)	45	#define WIN8_SRV_VERSION (WIN8_SRV_MAJOR << 16 \| WIN8_SRV_MINOR)
42		46
43	/*	47	/*
44	* Global state maintained for transaction that is being processed.	48	* Global state maintained for transaction that is being processed.
@@ -587,6 +591,8 @@ void hv_kvp_onchannelcallback(void *context) · 542 unmodified lines
587		591
588	struct icmsg_hdr *icmsghdrp;	592	struct icmsg_hdr *icmsghdrp;
589	struct icmsg_negotiate *negop = NULL;	593	struct icmsg_negotiate *negop = NULL;
		594	int util_fw_version;
		595	int kvp_srv_version;
590		596
591	if (kvp_transaction.active) {	597	if (kvp_transaction.active) {
592	/*	598	/*
@@ -606,17 +612,26 @@ void hv_kvp_onchannelcallback(void *context) · 13 unmodified lines
606		612
607	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {	613	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
608	/*	614	/*
609	* We start with win8 version and if the host cannot	615	* Based on the host, select appropriate
610	* support that we use the previous version.	616	* framework and service versions we will
		617	* negotiate.
611	*/	618	*/
612	if (vmbus_prep_negotiate_resp(icmsghdrp, negop,	619	switch (vmbus_proto_version) {
613	recv_buffer, UTIL_FW_MAJOR_MINOR,	620	case (VERSION_WS2008):
614	WIN8_SRV_MAJOR_MINOR))	621	util_fw_version = UTIL_WS2K8_FW_VERSION;
615	goto done;	622	kvp_srv_version = WS2008_SRV_VERSION;
616		623	break;
		624	case (VERSION_WIN7):
		625	util_fw_version = UTIL_FW_VERSION;
		626	kvp_srv_version = WIN7_SRV_VERSION;
		627	break;
		628	default:
		629	util_fw_version = UTIL_FW_VERSION;
		630	kvp_srv_version = WIN8_SRV_VERSION;
		631	}
617	vmbus_prep_negotiate_resp(icmsghdrp, negop,	632	vmbus_prep_negotiate_resp(icmsghdrp, negop,
618	recv_buffer, UTIL_FW_MAJOR_MINOR,	633	recv_buffer, util_fw_version,
619	WIN7_SRV_MAJOR_MINOR);	634	kvp_srv_version);
620		635
621	} else {	636	} else {
622	kvp_msg = (struct hv_kvp_msg *)&recv_buffer[	637	kvp_msg = (struct hv_kvp_msg *)&recv_buffer[
@@ -649,7 +664,6 @@ void hv_kvp_onchannelcallback(void *context) · 26 unmodified lines
649	return;	664	return;
650		665
651	}	666	}
652	done:
653		667
654	icmsghdrp->icflags = ICMSGHDRFLAG_TRANSACTION	668	icmsghdrp->icflags = ICMSGHDRFLAG_TRANSACTION
655	\| ICMSGHDRFLAG_RESPONSE;	669	\| ICMSGHDRFLAG_RESPONSE;

drivers/hv/hv_snapshot.c+3−3

@@ -26,7 +26,7 @@ · 25 unmodified lines
26		26
27	#define VSS_MAJOR 5	27	#define VSS_MAJOR 5
28	#define VSS_MINOR 0	28	#define VSS_MINOR 0
29	#define VSS_MAJOR_MINOR (VSS_MAJOR << 16 \| VSS_MINOR)	29	#define VSS_VERSION (VSS_MAJOR << 16 \| VSS_MINOR)
30		30
31		31
32		32
@@ -190,8 +190,8 @@ void hv_vss_onchannelcallback(void *context) · 157 unmodified lines
190		190
191	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {	191	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
192	vmbus_prep_negotiate_resp(icmsghdrp, negop,	192	vmbus_prep_negotiate_resp(icmsghdrp, negop,
193	recv_buffer, UTIL_FW_MAJOR_MINOR,	193	recv_buffer, UTIL_FW_VERSION,
194	VSS_MAJOR_MINOR);	194	VSS_VERSION);
195	} else {	195	} else {
196	vss_msg = (struct hv_vss_msg *)&recv_buffer[	196	vss_msg = (struct hv_vss_msg *)&recv_buffer[
197	sizeof(struct vmbuspipe_hdr) +	197	sizeof(struct vmbuspipe_hdr) +

drivers/hv/hv_util.c+54−17

@@ -28,17 +28,32 @@ · 27 unmodified lines
28	#include <linux/reboot.h>	28	#include <linux/reboot.h>
29	#include <linux/hyperv.h>	29	#include <linux/hyperv.h>
30		30
31	#define SHUTDOWN_MAJOR 3
32	#define SHUTDOWN_MINOR 0
33	#define SHUTDOWN_MAJOR_MINOR (SHUTDOWN_MAJOR << 16 \| SHUTDOWN_MINOR)
34		31
35	#define TIMESYNCH_MAJOR 3	32	#define SD_MAJOR 3
36	#define TIMESYNCH_MINOR 0	33	#define SD_MINOR 0
37	#define TIMESYNCH_MAJOR_MINOR (TIMESYNCH_MAJOR << 16 \| TIMESYNCH_MINOR)	34	#define SD_VERSION (SD_MAJOR << 16 \| SD_MINOR)
38		35
39	#define HEARTBEAT_MAJOR 3	36	#define SD_WS2008_MAJOR 1
40	#define HEARTBEAT_MINOR 0	37	#define SD_WS2008_VERSION (SD_WS2008_MAJOR << 16 \| SD_MINOR)
41	#define HEARTBEAT_MAJOR_MINOR (HEARTBEAT_MAJOR << 16 \| HEARTBEAT_MINOR)	38
		39	#define TS_MAJOR 3
		40	#define TS_MINOR 0
		41	#define TS_VERSION (TS_MAJOR << 16 \| TS_MINOR)
		42
		43	#define TS_WS2008_MAJOR 1
		44	#define TS_WS2008_VERSION (TS_WS2008_MAJOR << 16 \| TS_MINOR)
		45
		46	#define HB_MAJOR 3
		47	#define HB_MINOR 0
		48	#define HB_VERSION (HB_MAJOR << 16 \| HB_MINOR)
		49
		50	#define HB_WS2008_MAJOR 1
		51	#define HB_WS2008_VERSION (HB_WS2008_MAJOR << 16 \| HB_MINOR)
		52
		53	static int sd_srv_version;
		54	static int ts_srv_version;
		55	static int hb_srv_version;
		56	static int util_fw_version;
42		57
43	static void shutdown_onchannelcallback(void *context);	58	static void shutdown_onchannelcallback(void *context);
44	static struct hv_util_service util_shutdown = {	59	static struct hv_util_service util_shutdown = {
@@ -99,8 +114,8 @@ static void shutdown_onchannelcallback(void *context) · 54 unmodified lines
99		114
100	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {	115	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
101	vmbus_prep_negotiate_resp(icmsghdrp, negop,	116	vmbus_prep_negotiate_resp(icmsghdrp, negop,
102	shut_txf_buf, UTIL_FW_MAJOR_MINOR,	117	shut_txf_buf, util_fw_version,
103	SHUTDOWN_MAJOR_MINOR);	118	sd_srv_version);
104	} else {	119	} else {
105	shutdown_msg =	120	shutdown_msg =
106	(struct shutdown_msg_data *)&shut_txf_buf[	121	(struct shutdown_msg_data *)&shut_txf_buf[
@@ -216,6 +231,7 @@ static void timesync_onchannelcallback(void *context) · 109 unmodified lines
216	struct icmsg_hdr *icmsghdrp;	231	struct icmsg_hdr *icmsghdrp;
217	struct ictimesync_data *timedatap;	232	struct ictimesync_data *timedatap;
218	u8 *time_txf_buf = util_timesynch.recv_buffer;	233	u8 *time_txf_buf = util_timesynch.recv_buffer;
		234	struct icmsg_negotiate *negop = NULL;
219		235
220	vmbus_recvpacket(channel, time_txf_buf,	236	vmbus_recvpacket(channel, time_txf_buf,
221	PAGE_SIZE, &recvlen, &requestid);	237	PAGE_SIZE, &recvlen, &requestid);
@@ -225,9 +241,10 @@ static void timesync_onchannelcallback(void *context) · 3 unmodified lines
225	sizeof(struct vmbuspipe_hdr)];	241	sizeof(struct vmbuspipe_hdr)];
226		242
227	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {	243	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
228	vmbus_prep_negotiate_resp(icmsghdrp, NULL, time_txf_buf,	244	vmbus_prep_negotiate_resp(icmsghdrp, negop,
229	UTIL_FW_MAJOR_MINOR,	245	time_txf_buf,
230	TIMESYNCH_MAJOR_MINOR);	246	util_fw_version,
		247	ts_srv_version);
231	} else {	248	} else {
232	timedatap = (struct ictimesync_data *)&time_txf_buf[	249	timedatap = (struct ictimesync_data *)&time_txf_buf[
233	sizeof(struct vmbuspipe_hdr) +	250	sizeof(struct vmbuspipe_hdr) +
@@ -257,6 +274,7 @@ static void heartbeat_onchannelcallback(void *context) · 23 unmodified lines
257	struct icmsg_hdr *icmsghdrp;	274	struct icmsg_hdr *icmsghdrp;
258	struct heartbeat_msg_data *heartbeat_msg;	275	struct heartbeat_msg_data *heartbeat_msg;
259	u8 *hbeat_txf_buf = util_heartbeat.recv_buffer;	276	u8 *hbeat_txf_buf = util_heartbeat.recv_buffer;
		277	struct icmsg_negotiate *negop = NULL;
260		278
261	vmbus_recvpacket(channel, hbeat_txf_buf,	279	vmbus_recvpacket(channel, hbeat_txf_buf,
262	PAGE_SIZE, &recvlen, &requestid);	280	PAGE_SIZE, &recvlen, &requestid);
@@ -266,9 +284,9 @@ static void heartbeat_onchannelcallback(void *context) · 3 unmodified lines
266	sizeof(struct vmbuspipe_hdr)];	284	sizeof(struct vmbuspipe_hdr)];
267		285
268	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {	286	if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) {
269	vmbus_prep_negotiate_resp(icmsghdrp, NULL,	287	vmbus_prep_negotiate_resp(icmsghdrp, negop,
270	hbeat_txf_buf, UTIL_FW_MAJOR_MINOR,	288	hbeat_txf_buf, util_fw_version,
271	HEARTBEAT_MAJOR_MINOR);	289	hb_srv_version);
272	} else {	290	} else {
273	heartbeat_msg =	291	heartbeat_msg =
274	(struct heartbeat_msg_data *)&hbeat_txf_buf[	292	(struct heartbeat_msg_data *)&hbeat_txf_buf[
@@ -321,6 +339,25 @@ static int util_probe(struct hv_device *dev, · 46 unmodified lines
321	goto error;	339	goto error;
322		340
323	hv_set_drvdata(dev, srv);	341	hv_set_drvdata(dev, srv);
		342	/*
		343	* Based on the host; initialize the framework and
		344	* service version numbers we will negotiate.
		345	*/
		346	switch (vmbus_proto_version) {
		347	case (VERSION_WS2008):
		348	util_fw_version = UTIL_WS2K8_FW_VERSION;
		349	sd_srv_version = SD_WS2008_VERSION;
		350	ts_srv_version = TS_WS2008_VERSION;
		351	hb_srv_version = HB_WS2008_VERSION;
		352	break;
		353
		354	default:
		355	util_fw_version = UTIL_FW_VERSION;
		356	sd_srv_version = SD_VERSION;
		357	ts_srv_version = TS_VERSION;
		358	hb_srv_version = HB_VERSION;
		359	}
		360
324	return 0;	361	return 0;
325		362
326	error:	363	error:

drivers/hwmon/applesmc.c+10−1

 {
 	struct applesmc_registers *s = &smcreg;
 	bool left_light_sensor, right_light_sensor;
+	unsigned int count;
 	u8 tmp[1];
 	int ret;
 	if (s->init_complete)
 		return 0;
-	ret = read_register_count(&s->key_count);
+	ret = read_register_count(&count);
 	if (ret)
 		return ret;
+	if (s->cache && s->key_count != count) {
+		pr_warn("key count changed from %d to %d\n",
+			s->key_count, count);
+		kfree(s->cache);
+		s->cache = NULL;
+	}
+	s->key_count = count;
 	if (!s->cache)
 		s->cache = kcalloc(s->key_count, sizeof(*s->cache), GFP_KERNEL);
 	if (!s->cache)

drivers/i2c/busses/i2c-designware-core.c+20−6

 #define DW_IC_ERR_TX_ABRT	0x1
+#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
 /*
  * status codes
  */
 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 {
 	struct i2c_msg *msgs = dev->msgs;
-	u32 ic_con;
+	u32 ic_con, ic_tar = 0;
 	/* Disable the adapter */
 	__i2c_dw_enable(dev, false);
-	/* set the slave (target) address */
-	dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
 	/* if the slave address is ten bit address, enable 10BITADDR */
 	ic_con = dw_readl(dev, DW_IC_CON);
-	if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
+	if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 		ic_con |= DW_IC_CON_10BITADDR_MASTER;
-	else
+		/*
+		 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
+		 * mode has to be enabled via bit 12 of IC_TAR register.
+		 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
+		 * detected from registers.
+		 */
+		ic_tar = DW_IC_TAR_10BITADDR_MASTER;
+	} else {
 		ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
+	}
 	dw_writel(dev, ic_con, DW_IC_CON);
+	/*
+	 * Set the slave (target) address and enable 10-bit addressing mode
+	 * if applicable.
+	 */
+	dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 	/* Enable the adapter */
 	__i2c_dw_enable(dev, true);

drivers/i2c/busses/i2c-ismt.c+3−0

@@ -393,6 +393,9 @@ static int ismt_access(struct i2c_adapter *adap, u16 addr, · 392 unmodified lines
393		393
394	desc = &priv->hw[priv->head];	394	desc = &priv->hw[priv->head];
395		395
		396	/* Initialize the DMA buffer */
		397	memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer));
		398
396	/* Initialize the descriptor */	399	/* Initialize the descriptor */
397	memset(desc, 0, sizeof(struct ismt_desc));	400	memset(desc, 0, sizeof(struct ismt_desc));
398	desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);	401	desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);

drivers/i2c/busses/i2c-mv64xxx.c+9−7

 		ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
 		    (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT;
-		writel_relaxed(data_reg_lo,
+		writel(data_reg_lo,
 			drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
-		writel_relaxed(data_reg_hi,
+		writel(data_reg_hi,
 			drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
 	} else {
 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
 #ifdef CONFIG_OF
+#ifdef CONFIG_HAVE_CLK
 static int
 mv64xxx_calc_freq(const int tclk, const int n, const int m)
 {
 		return false;
 	return true;
 }
+#endif /* CONFIG_HAVE_CLK */
 static int
 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
 		  struct device *dev)
 {
-	const struct of_device_id *device;
-	struct device_node *np = dev->of_node;
-	u32 bus_freq, tclk;
-	int rc = 0;
 	/* CLK is mandatory when using DT to describe the i2c bus. We
 	 * need to know tclk in order to calculate bus clock
 	 * factors.
 	/* Have OF but no CLK */
 	return -ENODEV;
 #else
+	const struct of_device_id *device;
+	struct device_node *np = dev->of_node;
+	u32 bus_freq, tclk;
+	int rc = 0;
 	if (IS_ERR(drv_data->clk)) {
 		rc = -ENODEV;
 		goto out;

drivers/i2c/busses/i2c-s3c2410.c+0−2

@@ -1178,8 +1178,6 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev) · 1177 unmodified lines
1178		1178
1179	i2c_del_adapter(&i2c->adap);	1179	i2c_del_adapter(&i2c->adap);
1180		1180
1181	clk_disable_unprepare(i2c->clk);
1182
1183	if (pdev->dev.of_node && IS_ERR(i2c->pctrl))	1181	if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1184	s3c24xx_i2c_dt_gpio_free(i2c);	1182	s3c24xx_i2c_dt_gpio_free(i2c);
1185		1183

drivers/iio/accel/bma180.c+2−2

@@ -620,7 +620,7 @@ static int bma180_remove(struct i2c_client *client) · 619 unmodified lines
620	#ifdef CONFIG_PM_SLEEP	620	#ifdef CONFIG_PM_SLEEP
621	static int bma180_suspend(struct device *dev)	621	static int bma180_suspend(struct device *dev)
622	{	622	{
623	struct iio_dev *indio_dev = dev_to_iio_dev(dev);	623	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
624	struct bma180_data *data = iio_priv(indio_dev);	624	struct bma180_data *data = iio_priv(indio_dev);
625	int ret;	625	int ret;
626		626
@@ -633,7 +633,7 @@ static int bma180_suspend(struct device *dev) · 6 unmodified lines
633		633
634	static int bma180_resume(struct device *dev)	634	static int bma180_resume(struct device *dev)
635	{	635	{
636	struct iio_dev *indio_dev = dev_to_iio_dev(dev);	636	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
637	struct bma180_data *data = iio_priv(indio_dev);	637	struct bma180_data *data = iio_priv(indio_dev);
638	int ret;	638	int ret;
639		639

drivers/iio/adc/at91_adc.c+6−5

 static int at91_adc_probe(struct platform_device *pdev)
 {
-	unsigned int prsc, mstrclk, ticks, adc_clk, shtim;
+	unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
 	int ret;
 	struct iio_dev *idev;
 	struct at91_adc_state *st;
 	 */
 	mstrclk = clk_get_rate(st->clk);
 	adc_clk = clk_get_rate(st->adc_clk);
+	adc_clk_khz = adc_clk / 1000;
 	prsc = (mstrclk / (2 * adc_clk)) - 1;
 	if (!st->startup_time) {
 	 * defined in the electrical characteristics of the board, divided by 8.
 	 * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock
 	 */
-	ticks = round_up((st->startup_time * adc_clk /
+	ticks = round_up((st->startup_time * adc_clk_khz /
-			  1000000) - 1, 8) / 8;
+			  1000) - 1, 8) / 8;
 	/*
 	 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
 	 * the best converted final value between two channels selection
 	 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
 	 */
-	shtim = round_up((st->sample_hold_time * adc_clk /
+	shtim = round_up((st->sample_hold_time * adc_clk_khz /
-			  1000000) - 1, 1);
+			  1000) - 1, 1);
 	reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
 	reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;

drivers/iio/amplifiers/ad8366.c+1−3

@@ -185,10 +185,8 @@ static int ad8366_remove(struct spi_device *spi) · 184 unmodified lines
185		185
186	iio_device_unregister(indio_dev);	186	iio_device_unregister(indio_dev);
187		187
188	if (!IS_ERR(reg)) {	188	if (!IS_ERR(reg))
189	regulator_disable(reg);	189	regulator_disable(reg);
190	regulator_put(reg);
191	}
192		190
193	return 0;	191	return 0;
194	}	192	}

drivers/iio/buffer_cb.c+2−0

@@ -41,6 +41,8 @@ struct iio_cb_buffer iio_channel_get_all_cb(struct device dev, · 40 unmodified lines
41	goto error_ret;	41	goto error_ret;
42	}	42	}
43		43
		44	iio_buffer_init(&cb_buff->buffer);
		45
44	cb_buff->private = private;	46	cb_buff->private = private;
45	cb_buff->cb = cb;	47	cb_buff->cb = cb;
46	cb_buff->buffer.access = &iio_cb_access;	48	cb_buff->buffer.access = &iio_cb_access;

drivers/iio/dac/mcp4725.c+6−6

@@ -37,21 +37,21 @@ struct mcp4725_data { · 36 unmodified lines
37		37
38	static int mcp4725_suspend(struct device *dev)	38	static int mcp4725_suspend(struct device *dev)
39	{	39	{
40	struct iio_dev *indio_dev = dev_to_iio_dev(dev);	40	struct mcp4725_data *data = iio_priv(i2c_get_clientdata(
41	struct mcp4725_data *data = iio_priv(indio_dev);	41	to_i2c_client(dev)));
42	u8 outbuf[2];	42	u8 outbuf[2];
43		43
44	outbuf[0] = (data->powerdown_mode + 1) << 4;	44	outbuf[0] = (data->powerdown_mode + 1) << 4;
45	outbuf[1] = 0;	45	outbuf[1] = 0;
46	data->powerdown = true;	46	data->powerdown = true;
47		47
48	return i2c_master_send(to_i2c_client(dev), outbuf, 2);	48	return i2c_master_send(data->client, outbuf, 2);
49	}	49	}
50		50
51	static int mcp4725_resume(struct device *dev)	51	static int mcp4725_resume(struct device *dev)
52	{	52	{
53	struct iio_dev *indio_dev = dev_to_iio_dev(dev);	53	struct mcp4725_data *data = iio_priv(i2c_get_clientdata(
54	struct mcp4725_data *data = iio_priv(indio_dev);	54	to_i2c_client(dev)));
55	u8 outbuf[2];	55	u8 outbuf[2];
56		56
57	/* restore previous DAC value */	57	/* restore previous DAC value */
@@ -59,7 +59,7 @@ static int mcp4725_resume(struct device *dev) · 1 unmodified line
59	outbuf[1] = data->dac_value & 0xff;	59	outbuf[1] = data->dac_value & 0xff;
60	data->powerdown = false;	60	data->powerdown = false;
61		61
62	return i2c_master_send(to_i2c_client(dev), outbuf, 2);	62	return i2c_master_send(data->client, outbuf, 2);
63	}	63	}
64		64
65	#ifdef CONFIG_PM_SLEEP	65	#ifdef CONFIG_PM_SLEEP

drivers/iio/iio_core.h+4−0

 #define iio_buffer_poll_addr (&iio_buffer_poll)
 #define iio_buffer_read_first_n_outer_addr (&iio_buffer_read_first_n_outer)
+void iio_disable_all_buffers(struct iio_dev *indio_dev);
 #else
 #define iio_buffer_poll_addr NULL
 #define iio_buffer_read_first_n_outer_addr NULL
+static inline void iio_disable_all_buffers(struct iio_dev *indio_dev) {}
 #endif
 int iio_device_register_eventset(struct iio_dev *indio_dev);

drivers/iio/industrialio-buffer.c+28−2

@@ -460,6 +460,25 @@ static int iio_compute_scan_bytes(struct iio_dev indio_dev, const long mask, · 459 unmodified lines
460	return bytes;	460	return bytes;
461	}	461	}
462		462
		463	void iio_disable_all_buffers(struct iio_dev *indio_dev)
		464	{
		465	struct iio_buffer buffer, _buffer;
		466
		467	if (list_empty(&indio_dev->buffer_list))
		468	return;
		469
		470	if (indio_dev->setup_ops->predisable)
		471	indio_dev->setup_ops->predisable(indio_dev);
		472
		473	list_for_each_entry_safe(buffer, _buffer,
		474	&indio_dev->buffer_list, buffer_list)
		475	list_del_init(&buffer->buffer_list);
		476
		477	indio_dev->currentmode = INDIO_DIRECT_MODE;
		478	if (indio_dev->setup_ops->postdisable)
		479	indio_dev->setup_ops->postdisable(indio_dev);
		480	}
		481
463	int iio_update_buffers(struct iio_dev *indio_dev,	482	int iio_update_buffers(struct iio_dev *indio_dev,
464	struct iio_buffer *insert_buffer,	483	struct iio_buffer *insert_buffer,
465	struct iio_buffer *remove_buffer)	484	struct iio_buffer *remove_buffer)
@@ -528,8 +547,15 @@ int iio_update_buffers(struct iio_dev *indio_dev, · 62 unmodified lines
528	* Note can only occur when adding a buffer.	547	* Note can only occur when adding a buffer.
529	*/	548	*/
530	list_del(&insert_buffer->buffer_list);	549	list_del(&insert_buffer->buffer_list);
531	indio_dev->active_scan_mask = old_mask;	550	if (old_mask) {
532	success = -EINVAL;	551	indio_dev->active_scan_mask = old_mask;
		552	success = -EINVAL;
		553	}
		554	else {
		555	kfree(compound_mask);
		556	ret = -EINVAL;
		557	goto error_ret;
		558	}
533	}	559	}
534	} else {	560	} else {
535	indio_dev->active_scan_mask = compound_mask;	561	indio_dev->active_scan_mask = compound_mask;

drivers/iio/industrialio-core.c+22−11

 static void iio_dev_release(struct device *device)
 {
 	struct iio_dev *indio_dev = dev_to_iio_dev(device);
-	if (indio_dev->chrdev.dev)
-		cdev_del(&indio_dev->chrdev);
 	if (indio_dev->modes & INDIO_BUFFER_TRIGGERED)
 		iio_device_unregister_trigger_consumer(indio_dev);
 	iio_device_unregister_eventset(indio_dev);
 	iio_device_unregister_sysfs(indio_dev);
-	iio_device_unregister_debugfs(indio_dev);
 	ida_simple_remove(&iio_ida, indio_dev->id);
 	kfree(indio_dev);
 	if (test_and_set_bit(IIO_BUSY_BIT_POS, &indio_dev->flags))
 		return -EBUSY;
+	iio_device_get(indio_dev);
 	filp->private_data = indio_dev;
 	return 0;
 	struct iio_dev *indio_dev = container_of(inode->i_cdev,
 						struct iio_dev, chrdev);
 	clear_bit(IIO_BUSY_BIT_POS, &indio_dev->flags);
+	iio_device_put(indio_dev);
 	return 0;
 }
 		indio_dev->setup_ops == NULL)
 		indio_dev->setup_ops = &noop_ring_setup_ops;
-	ret = device_add(&indio_dev->dev);
-	if (ret < 0)
-		goto error_unreg_eventset;
 	cdev_init(&indio_dev->chrdev, &iio_buffer_fileops);
 	indio_dev->chrdev.owner = indio_dev->info->driver_module;
+	indio_dev->chrdev.kobj.parent = &indio_dev->dev.kobj;
 	ret = cdev_add(&indio_dev->chrdev, indio_dev->dev.devt, 1);
 	if (ret < 0)
-		goto error_del_device;
+		goto error_unreg_eventset;
-	return 0;
-error_del_device:
+	ret = device_add(&indio_dev->dev);
-	device_del(&indio_dev->dev);
+	if (ret < 0)
+		goto error_cdev_del;
+	return 0;
+error_cdev_del:
+	cdev_del(&indio_dev->chrdev);
 error_unreg_eventset:
 	iio_device_unregister_eventset(indio_dev);
 error_free_sysfs:
 void iio_device_unregister(struct iio_dev *indio_dev)
 {
 	mutex_lock(&indio_dev->info_exist_lock);
+	device_del(&indio_dev->dev);
+	if (indio_dev->chrdev.dev)
+		cdev_del(&indio_dev->chrdev);
+	iio_device_unregister_debugfs(indio_dev);
+	iio_disable_all_buffers(indio_dev);
 	indio_dev->info = NULL;
 	mutex_unlock(&indio_dev->info_exist_lock);
-	device_del(&indio_dev->dev);
 }
 EXPORT_SYMBOL(iio_device_unregister);
 subsys_initcall(iio_init);

drivers/iio/industrialio-event.c+14−6

@@ -72,7 +72,8 @@ EXPORT_SYMBOL(iio_push_event); · 71 unmodified lines
72	static unsigned int iio_event_poll(struct file *filep,	72	static unsigned int iio_event_poll(struct file *filep,
73	struct poll_table_struct *wait)	73	struct poll_table_struct *wait)
74	{	74	{
75	struct iio_event_interface *ev_int = filep->private_data;	75	struct iio_dev *indio_dev = filep->private_data;
		76	struct iio_event_interface *ev_int = indio_dev->event_interface;
76	unsigned int events = 0;	77	unsigned int events = 0;
77		78
78	poll_wait(filep, &ev_int->wait, wait);	79	poll_wait(filep, &ev_int->wait, wait);
@@ -90,7 +91,8 @@ static ssize_t iio_event_chrdev_read(struct file *filep, · 11 unmodified lines
90	size_t count,	91	size_t count,
91	loff_t *f_ps)	92	loff_t *f_ps)
92	{	93	{
93	struct iio_event_interface *ev_int = filep->private_data;	94	struct iio_dev *indio_dev = filep->private_data;
		95	struct iio_event_interface *ev_int = indio_dev->event_interface;
94	unsigned int copied;	96	unsigned int copied;
95	int ret;	97	int ret;
96		98
@@ -121,7 +123,8 @@ error_unlock: · 24 unmodified lines
121		123
122	static int iio_event_chrdev_release(struct inode inode, struct file filep)	124	static int iio_event_chrdev_release(struct inode inode, struct file filep)
123	{	125	{
124	struct iio_event_interface *ev_int = filep->private_data;	126	struct iio_dev *indio_dev = filep->private_data;
		127	struct iio_event_interface *ev_int = indio_dev->event_interface;
125		128
126	spin_lock_irq(&ev_int->wait.lock);	129	spin_lock_irq(&ev_int->wait.lock);
127	__clear_bit(IIO_BUSY_BIT_POS, &ev_int->flags);	130	__clear_bit(IIO_BUSY_BIT_POS, &ev_int->flags);
@@ -133,6 +136,8 @@ static int iio_event_chrdev_release(struct inode inode, struct file filep) · 5 unmodified lines
133	kfifo_reset_out(&ev_int->det_events);	136	kfifo_reset_out(&ev_int->det_events);
134	spin_unlock_irq(&ev_int->wait.lock);	137	spin_unlock_irq(&ev_int->wait.lock);
135		138
		139	iio_device_put(indio_dev);
		140
136	return 0;	141	return 0;
137	}	142	}
138		143
@@ -158,12 +163,15 @@ int iio_event_getfd(struct iio_dev *indio_dev) · 19 unmodified lines
158	return -EBUSY;	163	return -EBUSY;
159	}	164	}
160	spin_unlock_irq(&ev_int->wait.lock);	165	spin_unlock_irq(&ev_int->wait.lock);
161	fd = anon_inode_getfd("iio:event",	166	iio_device_get(indio_dev);
162	&iio_event_chrdev_fileops, ev_int, O_RDONLY);	167
		168	fd = anon_inode_getfd("iio:event", &iio_event_chrdev_fileops,
		169	indio_dev, O_RDONLY);
163	if (fd < 0) {	170	if (fd < 0) {
164	spin_lock_irq(&ev_int->wait.lock);	171	spin_lock_irq(&ev_int->wait.lock);
165	__clear_bit(IIO_BUSY_BIT_POS, &ev_int->flags);	172	__clear_bit(IIO_BUSY_BIT_POS, &ev_int->flags);
166	spin_unlock_irq(&ev_int->wait.lock);	173	spin_unlock_irq(&ev_int->wait.lock);
		174	iio_device_put(indio_dev);
167	}	175	}
168	return fd;	176	return fd;
169	}	177	}
@@ -276,7 +284,7 @@ static int iio_device_add_event_sysfs(struct iio_dev *indio_dev, · 106 unmodified lines
276	goto error_ret;	284	goto error_ret;
277	}	285	}
278	if (chan->modified)	286	if (chan->modified)
279	mask = IIO_MOD_EVENT_CODE(chan->type, 0, chan->channel,	287	mask = IIO_MOD_EVENT_CODE(chan->type, 0, chan->channel2,
280	i/IIO_EV_DIR_MAX,	288	i/IIO_EV_DIR_MAX,
281	i%IIO_EV_DIR_MAX);	289	i%IIO_EV_DIR_MAX);
282	else if (chan->differential)	290	else if (chan->differential)

drivers/iio/magnetometer/st_magn_core.c+9−9

@@ -29,9 +29,9 @@ · 28 unmodified lines
29	#define ST_MAGN_NUMBER_DATA_CHANNELS 3	29	#define ST_MAGN_NUMBER_DATA_CHANNELS 3
30		30
31	/* DEFAULT VALUE FOR SENSORS */	31	/* DEFAULT VALUE FOR SENSORS */
32	#define ST_MAGN_DEFAULT_OUT_X_L_ADDR 0X04	32	#define ST_MAGN_DEFAULT_OUT_X_H_ADDR 0X03
33	#define ST_MAGN_DEFAULT_OUT_Y_L_ADDR 0X08	33	#define ST_MAGN_DEFAULT_OUT_Y_H_ADDR 0X07
34	#define ST_MAGN_DEFAULT_OUT_Z_L_ADDR 0X06	34	#define ST_MAGN_DEFAULT_OUT_Z_H_ADDR 0X05
35		35
36	/* FULLSCALE */	36	/* FULLSCALE */
37	#define ST_MAGN_FS_AVL_1300MG 1300	37	#define ST_MAGN_FS_AVL_1300MG 1300
@@ -117,16 +117,16 @@ · 79 unmodified lines
117	static const struct iio_chan_spec st_magn_16bit_channels[] = {	117	static const struct iio_chan_spec st_magn_16bit_channels[] = {
118	ST_SENSORS_LSM_CHANNELS(IIO_MAGN,	118	ST_SENSORS_LSM_CHANNELS(IIO_MAGN,
119	BIT(IIO_CHAN_INFO_RAW) \| BIT(IIO_CHAN_INFO_SCALE),	119	BIT(IIO_CHAN_INFO_RAW) \| BIT(IIO_CHAN_INFO_SCALE),
120	ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 16, 16,	120	ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_BE, 16, 16,
121	ST_MAGN_DEFAULT_OUT_X_L_ADDR),	121	ST_MAGN_DEFAULT_OUT_X_H_ADDR),
122	ST_SENSORS_LSM_CHANNELS(IIO_MAGN,	122	ST_SENSORS_LSM_CHANNELS(IIO_MAGN,
123	BIT(IIO_CHAN_INFO_RAW) \| BIT(IIO_CHAN_INFO_SCALE),	123	BIT(IIO_CHAN_INFO_RAW) \| BIT(IIO_CHAN_INFO_SCALE),
124	ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 16, 16,	124	ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_BE, 16, 16,
125	ST_MAGN_DEFAULT_OUT_Y_L_ADDR),	125	ST_MAGN_DEFAULT_OUT_Y_H_ADDR),
126	ST_SENSORS_LSM_CHANNELS(IIO_MAGN,	126	ST_SENSORS_LSM_CHANNELS(IIO_MAGN,
127	BIT(IIO_CHAN_INFO_RAW) \| BIT(IIO_CHAN_INFO_SCALE),	127	BIT(IIO_CHAN_INFO_RAW) \| BIT(IIO_CHAN_INFO_SCALE),
128	ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 16, 16,	128	ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_BE, 16, 16,
129	ST_MAGN_DEFAULT_OUT_Z_L_ADDR),	129	ST_MAGN_DEFAULT_OUT_Z_H_ADDR),
130	IIO_CHAN_SOFT_TIMESTAMP(3)	130	IIO_CHAN_SOFT_TIMESTAMP(3)
131	};	131	};
132		132

drivers/iio/temperature/tmp006.c+4−2

 #ifdef CONFIG_PM_SLEEP
 static int tmp006_suspend(struct device *dev)
 {
-	return tmp006_powerdown(iio_priv(dev_to_iio_dev(dev)));
+	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
+	return tmp006_powerdown(iio_priv(indio_dev));
 }
 static int tmp006_resume(struct device *dev)
 {
-	struct tmp006_data *data = iio_priv(dev_to_iio_dev(dev));
+	struct tmp006_data *data = iio_priv(i2c_get_clientdata(
+		to_i2c_client(dev)));
 	return i2c_smbus_write_word_swapped(data->client, TMP006_CONFIG,
 		data->config | TMP006_CONFIG_MOD_MASK);
 }

drivers/infiniband/ulp/srpt/ib_srpt.c+6−8

 	int resp_data_len;
 	int resp_len;
-	resp_data_len = (rsp_code == SRP_TSK_MGMT_SUCCESS) ? 0 : 4;
+	resp_data_len = 4;
 	resp_len = sizeof(*srp_rsp) + resp_data_len;
 	srp_rsp = ioctx->ioctx.buf;
 				    + atomic_xchg(&ch->req_lim_delta, 0));
 	srp_rsp->tag = tag;
-	if (rsp_code != SRP_TSK_MGMT_SUCCESS) {
+	srp_rsp->flags |= SRP_RSP_FLAG_RSPVALID;
-		srp_rsp->flags |= SRP_RSP_FLAG_RSPVALID;
+	srp_rsp->resp_data_len = cpu_to_be32(resp_data_len);
-		srp_rsp->resp_data_len = cpu_to_be32(resp_data_len);
+	srp_rsp->data[3] = rsp_code;
-		srp_rsp->data[3] = rsp_code;
-	}
 	return resp_len;
 }
 	transport_deregister_session(se_sess);
 	ch->sess = NULL;
+	ib_destroy_cm_id(ch->cm_id);
 	srpt_destroy_ch_ib(ch);
 	srpt_free_ioctx_ring((struct srpt_ioctx **)ch->ioctx_ring,
 	list_del(&ch->list);
 	spin_unlock_irq(&sdev->spinlock);
-	ib_destroy_cm_id(ch->cm_id);
 	if (ch->release_done)
 		complete(ch->release_done);

drivers/iommu/arm-smmu.c+7−6

 	u32				cbar;
 	pgd_t				*pgd;
 };
+#define INVALID_IRPTNDX			0xff
 #define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
 #define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
 	if (IS_ERR_VALUE(ret)) {
 		dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 			root_cfg->irptndx, irq);
-		root_cfg->irptndx = -1;
+		root_cfg->irptndx = INVALID_IRPTNDX;
 		goto out_free_context;
 	}
 	writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
 	arm_smmu_tlb_inv_context(root_cfg);
-	if (root_cfg->irptndx != -1) {
+	if (root_cfg->irptndx != INVALID_IRPTNDX) {
 		irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
 		free_irq(irq, domain);
 	}
 		goto out_put_parent;
 	}
-	arm_smmu_device_reset(smmu);
 	for (i = 0; i < smmu->num_global_irqs; ++i) {
 		err = request_irq(smmu->irqs[i],
 				  arm_smmu_global_fault,
 	spin_lock(&arm_smmu_devices_lock);
 	list_add(&smmu->list, &arm_smmu_devices);
 	spin_unlock(&arm_smmu_devices_lock);
+	arm_smmu_device_reset(smmu);
 	return 0;
 out_free_irqs:
 		return ret;
 	/* Oh, for a proper bus abstraction */
-	if (!iommu_present(&platform_bus_type));
+	if (!iommu_present(&platform_bus_type))
 		bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
-	if (!iommu_present(&amba_bustype));
+	if (!iommu_present(&amba_bustype))
 		bus_set_iommu(&amba_bustype, &arm_smmu_ops);
 	return 0;

drivers/isdn/hardware/mISDN/hfcpci.c+2−2

@@ -2295,8 +2295,8 @@ _hfcpci_softirq(struct device dev, void arg) · 2294 unmodified lines
2295	static void	2295	static void
2296	hfcpci_softirq(void *arg)	2296	hfcpci_softirq(void *arg)
2297	{	2297	{
2298	(void) driver_for_each_device(&hfc_driver.driver, NULL, arg,	2298	WARN_ON_ONCE(driver_for_each_device(&hfc_driver.driver, NULL, arg,
2299	_hfcpci_softirq);	2299	_hfcpci_softirq) != 0);
2300		2300
2301	/* if next event would be in the past ... */	2301	/* if next event would be in the past ... */
2302	if ((s32)(hfc_jiffies + tics - jiffies) <= 0)	2302	if ((s32)(hfc_jiffies + tics - jiffies) <= 0)

drivers/isdn/hisax/amd7930_fn.c+2−2

@@ -314,7 +314,7 @@ Amd7930_empty_Dfifo(struct IsdnCardState *cs, int flag) · 313 unmodified lines
314		314
315	t += sprintf(t, "Amd7930: empty_Dfifo cnt: %d \|", cs->rcvidx);	315	t += sprintf(t, "Amd7930: empty_Dfifo cnt: %d \|", cs->rcvidx);
316	QuickHex(t, cs->rcvbuf, cs->rcvidx);	316	QuickHex(t, cs->rcvbuf, cs->rcvidx);
317	debugl1(cs, cs->dlog);	317	debugl1(cs, "%s", cs->dlog);
318	}	318	}
319	/* moves received data in sk-buffer */	319	/* moves received data in sk-buffer */
320	memcpy(skb_put(skb, cs->rcvidx), cs->rcvbuf, cs->rcvidx);	320	memcpy(skb_put(skb, cs->rcvidx), cs->rcvbuf, cs->rcvidx);
@@ -406,7 +406,7 @@ Amd7930_fill_Dfifo(struct IsdnCardState *cs) · 85 unmodified lines
406		406
407	t += sprintf(t, "Amd7930: fill_Dfifo cnt: %d \|", count);	407	t += sprintf(t, "Amd7930: fill_Dfifo cnt: %d \|", count);
408	QuickHex(t, deb_ptr, count);	408	QuickHex(t, deb_ptr, count);
409	debugl1(cs, cs->dlog);	409	debugl1(cs, "%s", cs->dlog);
410	}	410	}
411	/* AMD interrupts on */	411	/* AMD interrupts on */
412	AmdIrqOn(cs);	412	AmdIrqOn(cs);

drivers/isdn/hisax/avm_pci.c+2−2

@@ -285,7 +285,7 @@ hdlc_empty_fifo(struct BCState *bcs, int count) · 284 unmodified lines
285	t += sprintf(t, "hdlc_empty_fifo %c cnt %d",	285	t += sprintf(t, "hdlc_empty_fifo %c cnt %d",
286	bcs->channel ? 'B' : 'A', count);	286	bcs->channel ? 'B' : 'A', count);
287	QuickHex(t, p, count);	287	QuickHex(t, p, count);
288	debugl1(cs, bcs->blog);	288	debugl1(cs, "%s", bcs->blog);
289	}	289	}
290	}	290	}
291		291
@@ -345,7 +345,7 @@ hdlc_fill_fifo(struct BCState *bcs) · 53 unmodified lines
345	t += sprintf(t, "hdlc_fill_fifo %c cnt %d",	345	t += sprintf(t, "hdlc_fill_fifo %c cnt %d",
346	bcs->channel ? 'B' : 'A', count);	346	bcs->channel ? 'B' : 'A', count);
347	QuickHex(t, p, count);	347	QuickHex(t, p, count);
348	debugl1(cs, bcs->blog);	348	debugl1(cs, "%s", bcs->blog);
349	}	349	}
350	}	350	}
351		351

drivers/isdn/hisax/config.c+1−1

@@ -1896,7 +1896,7 @@ static void EChannel_proc_rcv(struct hisax_d_if *d_if) · 1895 unmodified lines
1896	ptr--;	1896	ptr--;
1897	*ptr++ = '\n';	1897	*ptr++ = '\n';
1898	*ptr = 0;	1898	*ptr = 0;
1899	HiSax_putstatus(cs, NULL, cs->dlog);	1899	HiSax_putstatus(cs, NULL, "%s", cs->dlog);
1900	} else	1900	} else
1901	HiSax_putstatus(cs, "LogEcho: ",	1901	HiSax_putstatus(cs, "LogEcho: ",
1902	"warning Frame too big (%d)",	1902	"warning Frame too big (%d)",

drivers/isdn/hisax/diva.c+2−2

@@ -427,7 +427,7 @@ Memhscx_empty_fifo(struct BCState *bcs, int count) · 426 unmodified lines
427	t += sprintf(t, "hscx_empty_fifo %c cnt %d",	427	t += sprintf(t, "hscx_empty_fifo %c cnt %d",
428	bcs->hw.hscx.hscx ? 'B' : 'A', count);	428	bcs->hw.hscx.hscx ? 'B' : 'A', count);
429	QuickHex(t, ptr, count);	429	QuickHex(t, ptr, count);
430	debugl1(cs, bcs->blog);	430	debugl1(cs, "%s", bcs->blog);
431	}	431	}
432	}	432	}
433		433
@@ -469,7 +469,7 @@ Memhscx_fill_fifo(struct BCState *bcs) · 35 unmodified lines
469	t += sprintf(t, "hscx_fill_fifo %c cnt %d",	469	t += sprintf(t, "hscx_fill_fifo %c cnt %d",
470	bcs->hw.hscx.hscx ? 'B' : 'A', count);	470	bcs->hw.hscx.hscx ? 'B' : 'A', count);
471	QuickHex(t, ptr, count);	471	QuickHex(t, ptr, count);
472	debugl1(cs, bcs->blog);	472	debugl1(cs, "%s", bcs->blog);
473	}	473	}
474	}	474	}
475		475

drivers/isdn/hisax/elsa.c+1−1

@@ -535,7 +535,7 @@ check_arcofi(struct IsdnCardState *cs) · 534 unmodified lines
535	t = tmp;	535	t = tmp;
536	t += sprintf(tmp, "Arcofi data");	536	t += sprintf(tmp, "Arcofi data");
537	QuickHex(t, p, cs->dc.isac.mon_rxp);	537	QuickHex(t, p, cs->dc.isac.mon_rxp);
538	debugl1(cs, tmp);	538	debugl1(cs, "%s", tmp);
539	if ((cs->dc.isac.mon_rxp == 2) && (cs->dc.isac.mon_rx[0] == 0xa0)) {	539	if ((cs->dc.isac.mon_rxp == 2) && (cs->dc.isac.mon_rx[0] == 0xa0)) {
540	switch (cs->dc.isac.mon_rx[1]) {	540	switch (cs->dc.isac.mon_rx[1]) {
541	case 0x80:	541	case 0x80:

drivers/isdn/hisax/elsa_ser.c+1−1

@@ -344,7 +344,7 @@ static inline void receive_chars(struct IsdnCardState *cs, · 343 unmodified lines
344		344
345	t += sprintf(t, "modem read cnt %d", cs->hw.elsa.rcvcnt);	345	t += sprintf(t, "modem read cnt %d", cs->hw.elsa.rcvcnt);
346	QuickHex(t, cs->hw.elsa.rcvbuf, cs->hw.elsa.rcvcnt);	346	QuickHex(t, cs->hw.elsa.rcvbuf, cs->hw.elsa.rcvcnt);
347	debugl1(cs, tmp);	347	debugl1(cs, "%s", tmp);
348	}	348	}
349	cs->hw.elsa.rcvcnt = 0;	349	cs->hw.elsa.rcvcnt = 0;
350	}	350	}

drivers/isdn/hisax/hfc_pci.c+1−1

@@ -901,7 +901,7 @@ Begin: · 900 unmodified lines
901	ptr--;	901	ptr--;
902	*ptr++ = '\n';	902	*ptr++ = '\n';
903	*ptr = 0;	903	*ptr = 0;
904	HiSax_putstatus(cs, NULL, cs->dlog);	904	HiSax_putstatus(cs, NULL, "%s", cs->dlog);
905	} else	905	} else
906	HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);	906	HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);
907	}	907	}

drivers/isdn/hisax/hfc_sx.c+1−1

@@ -674,7 +674,7 @@ receive_emsg(struct IsdnCardState *cs) · 673 unmodified lines
674	ptr--;	674	ptr--;
675	*ptr++ = '\n';	675	*ptr++ = '\n';
676	*ptr = 0;	676	*ptr = 0;
677	HiSax_putstatus(cs, NULL, cs->dlog);	677	HiSax_putstatus(cs, NULL, "%s", cs->dlog);
678	} else	678	} else
679	HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);	679	HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);
680	}	680	}

drivers/isdn/hisax/hscx_irq.c+2−2

@@ -75,7 +75,7 @@ hscx_empty_fifo(struct BCState *bcs, int count) · 74 unmodified lines
75	t += sprintf(t, "hscx_empty_fifo %c cnt %d",	75	t += sprintf(t, "hscx_empty_fifo %c cnt %d",
76	bcs->hw.hscx.hscx ? 'B' : 'A', count);	76	bcs->hw.hscx.hscx ? 'B' : 'A', count);
77	QuickHex(t, ptr, count);	77	QuickHex(t, ptr, count);
78	debugl1(cs, bcs->blog);	78	debugl1(cs, "%s", bcs->blog);
79	}	79	}
80	}	80	}
81		81
@@ -115,7 +115,7 @@ hscx_fill_fifo(struct BCState *bcs) · 33 unmodified lines
115	t += sprintf(t, "hscx_fill_fifo %c cnt %d",	115	t += sprintf(t, "hscx_fill_fifo %c cnt %d",
116	bcs->hw.hscx.hscx ? 'B' : 'A', count);	116	bcs->hw.hscx.hscx ? 'B' : 'A', count);
117	QuickHex(t, ptr, count);	117	QuickHex(t, ptr, count);
118	debugl1(cs, bcs->blog);	118	debugl1(cs, "%s", bcs->blog);
119	}	119	}
120	}	120	}
121		121

drivers/isdn/hisax/icc.c+2−2

@@ -134,7 +134,7 @@ icc_empty_fifo(struct IsdnCardState *cs, int count) · 133 unmodified lines
134		134
135	t += sprintf(t, "icc_empty_fifo cnt %d", count);	135	t += sprintf(t, "icc_empty_fifo cnt %d", count);
136	QuickHex(t, ptr, count);	136	QuickHex(t, ptr, count);
137	debugl1(cs, cs->dlog);	137	debugl1(cs, "%s", cs->dlog);
138	}	138	}
139	}	139	}
140		140
@@ -176,7 +176,7 @@ icc_fill_fifo(struct IsdnCardState *cs) · 35 unmodified lines
176		176
177	t += sprintf(t, "icc_fill_fifo cnt %d", count);	177	t += sprintf(t, "icc_fill_fifo cnt %d", count);
178	QuickHex(t, ptr, count);	178	QuickHex(t, ptr, count);
179	debugl1(cs, cs->dlog);	179	debugl1(cs, "%s", cs->dlog);
180	}	180	}
181	}	181	}
182		182

drivers/isdn/hisax/ipacx.c+4−4

@@ -260,7 +260,7 @@ dch_empty_fifo(struct IsdnCardState *cs, int count) · 259 unmodified lines
260		260
261	t += sprintf(t, "dch_empty_fifo() cnt %d", count);	261	t += sprintf(t, "dch_empty_fifo() cnt %d", count);
262	QuickHex(t, ptr, count);	262	QuickHex(t, ptr, count);
263	debugl1(cs, cs->dlog);	263	debugl1(cs, "%s", cs->dlog);
264	}	264	}
265	}	265	}
266		266
@@ -307,7 +307,7 @@ dch_fill_fifo(struct IsdnCardState *cs) · 40 unmodified lines
307		307
308	t += sprintf(t, "dch_fill_fifo() cnt %d", count);	308	t += sprintf(t, "dch_fill_fifo() cnt %d", count);
309	QuickHex(t, ptr, count);	309	QuickHex(t, ptr, count);
310	debugl1(cs, cs->dlog);	310	debugl1(cs, "%s", cs->dlog);
311	}	311	}
312	}	312	}
313		313
@@ -539,7 +539,7 @@ bch_empty_fifo(struct BCState *bcs, int count) · 225 unmodified lines
539		539
540	t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count);	540	t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count);
541	QuickHex(t, ptr, count);	541	QuickHex(t, ptr, count);
542	debugl1(cs, bcs->blog);	542	debugl1(cs, "%s", bcs->blog);
543	}	543	}
544	}	544	}
545		545
@@ -582,7 +582,7 @@ bch_fill_fifo(struct BCState *bcs) · 36 unmodified lines
582		582
583	t += sprintf(t, "chb_fill_fifo() B-%d cnt %d", hscx, count);	583	t += sprintf(t, "chb_fill_fifo() B-%d cnt %d", hscx, count);
584	QuickHex(t, ptr, count);	584	QuickHex(t, ptr, count);
585	debugl1(cs, bcs->blog);	585	debugl1(cs, "%s", bcs->blog);
586	}	586	}
587	}	587	}
588		588

drivers/isdn/hisax/isac.c+2−2

@@ -137,7 +137,7 @@ isac_empty_fifo(struct IsdnCardState *cs, int count) · 136 unmodified lines
137		137
138	t += sprintf(t, "isac_empty_fifo cnt %d", count);	138	t += sprintf(t, "isac_empty_fifo cnt %d", count);
139	QuickHex(t, ptr, count);	139	QuickHex(t, ptr, count);
140	debugl1(cs, cs->dlog);	140	debugl1(cs, "%s", cs->dlog);
141	}	141	}
142	}	142	}
143		143
@@ -179,7 +179,7 @@ isac_fill_fifo(struct IsdnCardState *cs) · 35 unmodified lines
179		179
180	t += sprintf(t, "isac_fill_fifo cnt %d", count);	180	t += sprintf(t, "isac_fill_fifo cnt %d", count);
181	QuickHex(t, ptr, count);	181	QuickHex(t, ptr, count);
182	debugl1(cs, cs->dlog);	182	debugl1(cs, "%s", cs->dlog);
183	}	183	}
184	}	184	}
185		185

drivers/isdn/hisax/isar.c+3−3

@@ -74,7 +74,7 @@ sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len, · 73 unmodified lines
74	t = tmp;	74	t = tmp;
75	t += sprintf(t, "sendmbox cnt %d", len);	75	t += sprintf(t, "sendmbox cnt %d", len);
76	QuickHex(t, &msg[len-i], (i > 64) ? 64 : i);	76	QuickHex(t, &msg[len-i], (i > 64) ? 64 : i);
77	debugl1(cs, tmp);	77	debugl1(cs, "%s", tmp);
78	i -= 64;	78	i -= 64;
79	}	79	}
80	}	80	}
@@ -105,7 +105,7 @@ rcv_mbox(struct IsdnCardState cs, struct isar_reg ireg, u_char *msg) · 24 unmodified lines
105	t = tmp;	105	t = tmp;
106	t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);	106	t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
107	QuickHex(t, &msg[ireg->clsb - i], (i > 64) ? 64 : i);	107	QuickHex(t, &msg[ireg->clsb - i], (i > 64) ? 64 : i);
108	debugl1(cs, tmp);	108	debugl1(cs, "%s", tmp);
109	i -= 64;	109	i -= 64;
110	}	110	}
111	}	111	}
@@ -1248,7 +1248,7 @@ isar_int_main(struct IsdnCardState *cs) · 1136 unmodified lines
1248	tp += sprintf(debbuf, "msg iis(%x) msb(%x)",	1248	tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
1249	ireg->iis, ireg->cmsb);	1249	ireg->iis, ireg->cmsb);
1250	QuickHex(tp, (u_char *)ireg->par, ireg->clsb);	1250	QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
1251	debugl1(cs, debbuf);	1251	debugl1(cs, "%s", debbuf);
1252	}	1252	}
1253	break;	1253	break;
1254	case ISAR_IIS_INVMSG:	1254	case ISAR_IIS_INVMSG:

drivers/isdn/hisax/jade.c+5−13

 	int jade = bcs->hw.hscx.hscx;
 	if (cs->debug & L1_DEB_HSCX) {
-		char tmp[40];
+		debugl1(cs, "jade %c mode %d ichan %d", 'A' + jade, mode, bc);
-		sprintf(tmp, "jade %c mode %d ichan %d",
-			'A' + jade, mode, bc);
-		debugl1(cs, tmp);
 	}
 	bcs->mode = mode;
 	bcs->channel = bc;
 clear_pending_jade_ints(struct IsdnCardState *cs)
 {
 	int val;
-	char tmp[64];
 	cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
 	cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
 	val = cs->BC_Read_Reg(cs, 1, jade_HDLC_ISR);
-	sprintf(tmp, "jade B ISTA %x", val);
+	debugl1(cs, "jade B ISTA %x", val);
-	debugl1(cs, tmp);
 	val = cs->BC_Read_Reg(cs, 0, jade_HDLC_ISR);
-	sprintf(tmp, "jade A ISTA %x", val);
+	debugl1(cs, "jade A ISTA %x", val);
-	debugl1(cs, tmp);
 	val = cs->BC_Read_Reg(cs, 1, jade_HDLC_STAR);
-	sprintf(tmp, "jade B STAR %x", val);
+	debugl1(cs, "jade B STAR %x", val);
-	debugl1(cs, tmp);
 	val = cs->BC_Read_Reg(cs, 0, jade_HDLC_STAR);
-	sprintf(tmp, "jade A STAR %x", val);
+	debugl1(cs, "jade A STAR %x", val);
-	debugl1(cs, tmp);
 	/* Unmask ints */
 	cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8);
 	cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8);

drivers/isdn/hisax/jade_irq.c+2−2

@@ -65,7 +65,7 @@ jade_empty_fifo(struct BCState *bcs, int count) · 64 unmodified lines
65	t += sprintf(t, "jade_empty_fifo %c cnt %d",	65	t += sprintf(t, "jade_empty_fifo %c cnt %d",
66	bcs->hw.hscx.hscx ? 'B' : 'A', count);	66	bcs->hw.hscx.hscx ? 'B' : 'A', count);
67	QuickHex(t, ptr, count);	67	QuickHex(t, ptr, count);
68	debugl1(cs, bcs->blog);	68	debugl1(cs, "%s", bcs->blog);
69	}	69	}
70	}	70	}
71		71
@@ -105,7 +105,7 @@ jade_fill_fifo(struct BCState *bcs) · 33 unmodified lines
105	t += sprintf(t, "jade_fill_fifo %c cnt %d",	105	t += sprintf(t, "jade_fill_fifo %c cnt %d",
106	bcs->hw.hscx.hscx ? 'B' : 'A', count);	106	bcs->hw.hscx.hscx ? 'B' : 'A', count);
107	QuickHex(t, ptr, count);	107	QuickHex(t, ptr, count);
108	debugl1(cs, bcs->blog);	108	debugl1(cs, "%s", bcs->blog);
109	}	109	}
110	}	110	}
111		111

drivers/isdn/hisax/l3_1tr6.c+18−32

 {
 	dev_kfree_skb(skb);
 	if (pc->st->l3.debug & L3_DEB_WARN)
-		l3_debug(pc->st, msg);
+		l3_debug(pc->st, "%s", msg);
 	l3_1tr6_release_req(pc, 0, NULL);
 }
 {
 	u_char *p;
 	int bcfound = 0;
-	char tmp[80];
 	struct sk_buff *skb = arg;
 	/* Channel Identification */
 	/* Signal all services, linklevel takes care of Service-Indicator */
 	if (bcfound) {
 		if ((pc->para.setup.si1 != 7) && (pc->st->l3.debug & L3_DEB_WARN)) {
-			sprintf(tmp, "non-digital call: %s -> %s",
+			l3_debug(pc->st, "non-digital call: %s -> %s",
 				pc->para.setup.phone,
 				pc->para.setup.eazmsn);
-			l3_debug(pc->st, tmp);
 		}
 		newl3state(pc, 6);
 		pc->st->l3.l3l4(pc->st, CC_SETUP | INDICATION, pc);
 {
 	u_char *p;
 	int i, tmpcharge = 0;
-	char a_charge[8], tmp[32];
+	char a_charge[8];
 	struct sk_buff *skb = arg;
 	p = skb->data;
 			pc->st->l3.l3l4(pc->st, CC_CHARGE | INDICATION, pc);
 		}
 		if (pc->st->l3.debug & L3_DEB_CHARGE) {
-			sprintf(tmp, "charging info %d", pc->para.chargeinfo);
+			l3_debug(pc->st, "charging info %d",
-			l3_debug(pc->st, tmp);
+				 pc->para.chargeinfo);
 		}
 	} else if (pc->st->l3.debug & L3_DEB_CHARGE)
 		l3_debug(pc->st, "charging info not found");
 	struct sk_buff *skb = arg;
 	u_char *p;
 	int i, tmpcharge = 0;
-	char a_charge[8], tmp[32];
+	char a_charge[8];
 	StopAllL3Timer(pc);
 	p = skb->data;
 			pc->st->l3.l3l4(pc->st, CC_CHARGE | INDICATION, pc);
 		}
 		if (pc->st->l3.debug & L3_DEB_CHARGE) {
-			sprintf(tmp, "charging info %d", pc->para.chargeinfo);
+			l3_debug(pc->st, "charging info %d",
-			l3_debug(pc->st, tmp);
+				 pc->para.chargeinfo);
 		}
 	} else if (pc->st->l3.debug & L3_DEB_CHARGE)
 		l3_debug(pc->st, "charging info not found");
 	int i, mt, cr;
 	struct l3_process *proc;
 	struct sk_buff *skb = arg;
-	char tmp[80];
 	switch (pr) {
 	case (DL_DATA | INDICATION):
 	}
 	if (skb->len < 4) {
 		if (st->l3.debug & L3_DEB_PROTERR) {
-			sprintf(tmp, "up1tr6 len only %d", skb->len);
+			l3_debug(st, "up1tr6 len only %d", skb->len);
-			l3_debug(st, tmp);
 		}
 		dev_kfree_skb(skb);
 		return;
 	}
 	if ((skb->data[0] & 0xfe) != PROTO_DIS_N0) {
 		if (st->l3.debug & L3_DEB_PROTERR) {
-			sprintf(tmp, "up1tr6%sunexpected discriminator %x message len %d",
+			l3_debug(st, "up1tr6%sunexpected discriminator %x message len %d",
 				(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
 				skb->data[0], skb->len);
-			l3_debug(st, tmp);
 		}
 		dev_kfree_skb(skb);
 		return;
 	}
 	if (skb->data[1] != 1) {
 		if (st->l3.debug & L3_DEB_PROTERR) {
-			sprintf(tmp, "up1tr6 CR len not 1");
+			l3_debug(st, "up1tr6 CR len not 1");
-			l3_debug(st, tmp);
 		}
 		dev_kfree_skb(skb);
 		return;
 	if (skb->data[0] == PROTO_DIS_N0) {
 		dev_kfree_skb(skb);
 		if (st->l3.debug & L3_DEB_STATE) {
-			sprintf(tmp, "up1tr6%s N0 mt %x unhandled",
+			l3_debug(st, "up1tr6%s N0 mt %x unhandled",
 				(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ", mt);
-			l3_debug(st, tmp);
 		}
 	} else if (skb->data[0] == PROTO_DIS_N1) {
 		if (!(proc = getl3proc(st, cr))) {
 				if (cr < 128) {
 					if (!(proc = new_l3_process(st, cr))) {
 						if (st->l3.debug & L3_DEB_PROTERR) {
-							sprintf(tmp, "up1tr6 no roc mem");
+							l3_debug(st, "up1tr6 no roc mem");
-							l3_debug(st, tmp);
 						}
 						dev_kfree_skb(skb);
 						return;
 			} else {
 				if (!(proc = new_l3_process(st, cr))) {
 					if (st->l3.debug & L3_DEB_PROTERR) {
-						sprintf(tmp, "up1tr6 no roc mem");
+						l3_debug(st, "up1tr6 no roc mem");
-						l3_debug(st, tmp);
 					}
 					dev_kfree_skb(skb);
 					return;
 		if (i == ARRAY_SIZE(datastln1)) {
 			dev_kfree_skb(skb);
 			if (st->l3.debug & L3_DEB_STATE) {
-				sprintf(tmp, "up1tr6%sstate %d mt %x unhandled",
+				l3_debug(st, "up1tr6%sstate %d mt %x unhandled",
 					(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
 					proc->state, mt);
-				l3_debug(st, tmp);
 			}
 			return;
 		} else {
 			if (st->l3.debug & L3_DEB_STATE) {
-				sprintf(tmp, "up1tr6%sstate %d mt %x",
+				l3_debug(st, "up1tr6%sstate %d mt %x",
 					(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
 					proc->state, mt);
-				l3_debug(st, tmp);
 			}
 			datastln1[i].rout(proc, pr, skb);
 		}
 	int i, cr;
 	struct l3_process *proc;
 	struct Channel *chan;
-	char tmp[80];
 	if ((DL_ESTABLISH | REQUEST) == pr) {
 		l3_msg(st, pr, NULL);
 			break;
 	if (i == ARRAY_SIZE(downstl)) {
 		if (st->l3.debug & L3_DEB_STATE) {
-			sprintf(tmp, "down1tr6 state %d prim %d unhandled",
+			l3_debug(st, "down1tr6 state %d prim %d unhandled",
 				proc->state, pr);
-			l3_debug(st, tmp);
 		}
 	} else {
 		if (st->l3.debug & L3_DEB_STATE) {
-			sprintf(tmp, "down1tr6 state %d prim %d",
+			l3_debug(st, "down1tr6 state %d prim %d",
 				proc->state, pr);
-			l3_debug(st, tmp);
 		}
 		downstl[i].rout(proc, pr, arg);
 	}

drivers/isdn/hisax/netjet.c+1−1

@@ -176,7 +176,7 @@ static void printframe(struct IsdnCardState cs, u_char buf, int count, char *s · 175 unmodified lines
176	else	176	else
177	j = i;	177	j = i;
178	QuickHex(t, p, j);	178	QuickHex(t, p, j);
179	debugl1(cs, tmp);	179	debugl1(cs, "%s", tmp);
180	p += j;	180	p += j;
181	i -= j;	181	i -= j;
182	t = tmp;	182	t = tmp;

drivers/isdn/hisax/q931.c+3−3

@@ -1179,7 +1179,7 @@ LogFrame(struct IsdnCardState cs, u_char buf, int size) · 1178 unmodified lines
1179	dp--;	1179	dp--;
1180	*dp++ = '\n';	1180	*dp++ = '\n';
1181	*dp = 0;	1181	*dp = 0;
1182	HiSax_putstatus(cs, NULL, cs->dlog);	1182	HiSax_putstatus(cs, NULL, "%s", cs->dlog);
1183	} else	1183	} else
1184	HiSax_putstatus(cs, "LogFrame: ", "warning Frame too big (%d)", size);	1184	HiSax_putstatus(cs, "LogFrame: ", "warning Frame too big (%d)", size);
1185	}	1185	}
@@ -1246,7 +1246,7 @@ dlogframe(struct IsdnCardState cs, struct sk_buff skb, int dir) · 60 unmodified lines
1246	}	1246	}
1247	if (finish) {	1247	if (finish) {
1248	*dp = 0;	1248	*dp = 0;
1249	HiSax_putstatus(cs, NULL, cs->dlog);	1249	HiSax_putstatus(cs, NULL, "%s", cs->dlog);
1250	return;	1250	return;
1251	}	1251	}
1252	if ((0xfe & buf[0]) == PROTO_DIS_N0) { /* 1TR6 */	1252	if ((0xfe & buf[0]) == PROTO_DIS_N0) { /* 1TR6 */
@@ -1509,5 +1509,5 @@ dlogframe(struct IsdnCardState cs, struct sk_buff skb, int dir) · 256 unmodified lines
1509	dp += sprintf(dp, "Unknown protocol %x!", buf[0]);	1509	dp += sprintf(dp, "Unknown protocol %x!", buf[0]);
1510	}	1510	}
1511	*dp = 0;	1511	*dp = 0;
1512	HiSax_putstatus(cs, NULL, cs->dlog);	1512	HiSax_putstatus(cs, NULL, "%s", cs->dlog);
1513	}	1513	}

drivers/isdn/hisax/w6692.c+4−4

@@ -154,7 +154,7 @@ W6692_empty_fifo(struct IsdnCardState *cs, int count) · 153 unmodified lines
154		154
155	t += sprintf(t, "W6692_empty_fifo cnt %d", count);	155	t += sprintf(t, "W6692_empty_fifo cnt %d", count);
156	QuickHex(t, ptr, count);	156	QuickHex(t, ptr, count);
157	debugl1(cs, cs->dlog);	157	debugl1(cs, "%s", cs->dlog);
158	}	158	}
159	}	159	}
160		160
@@ -196,7 +196,7 @@ W6692_fill_fifo(struct IsdnCardState *cs) · 35 unmodified lines
196		196
197	t += sprintf(t, "W6692_fill_fifo cnt %d", count);	197	t += sprintf(t, "W6692_fill_fifo cnt %d", count);
198	QuickHex(t, ptr, count);	198	QuickHex(t, ptr, count);
199	debugl1(cs, cs->dlog);	199	debugl1(cs, "%s", cs->dlog);
200	}	200	}
201	}	201	}
202		202
@@ -226,7 +226,7 @@ W6692B_empty_fifo(struct BCState *bcs, int count) · 23 unmodified lines
226	t += sprintf(t, "W6692B_empty_fifo %c cnt %d",	226	t += sprintf(t, "W6692B_empty_fifo %c cnt %d",
227	bcs->channel + '1', count);	227	bcs->channel + '1', count);
228	QuickHex(t, ptr, count);	228	QuickHex(t, ptr, count);
229	debugl1(cs, bcs->blog);	229	debugl1(cs, "%s", bcs->blog);
230	}	230	}
231	}	231	}
232		232
@@ -264,7 +264,7 @@ W6692B_fill_fifo(struct BCState *bcs) · 31 unmodified lines
264	t += sprintf(t, "W6692B_fill_fifo %c cnt %d",	264	t += sprintf(t, "W6692B_fill_fifo %c cnt %d",
265	bcs->channel + '1', count);	265	bcs->channel + '1', count);
266	QuickHex(t, ptr, count);	266	QuickHex(t, ptr, count);
267	debugl1(cs, bcs->blog);	267	debugl1(cs, "%s", bcs->blog);
268	}	268	}
269	}	269	}
270		270

drivers/mailbox/mailbox-omap2.c+0−1

@@ -325,7 +325,6 @@ static int omap2_mbox_remove(struct platform_device *pdev) · 324 unmodified lines
325	kfree(privblk);	325	kfree(privblk);
326	kfree(mboxblk);	326	kfree(mboxblk);
327	kfree(list);	327	kfree(list);
328	platform_set_drvdata(pdev, NULL);
329		328
330	return 0;	329	return 0;
331	}	330	}

drivers/md/bcache/bcache.h+3−4

 	 */
 	atomic_t		has_dirty;
-	struct ratelimit	writeback_rate;
+	struct bch_ratelimit	writeback_rate;
 	struct delayed_work	writeback_rate_update;
 	/*
 	 */
 	sector_t		last_read;
-	/* Number of writeback bios in flight */
+	/* Limit number of writeback bios in flight */
-	atomic_t		in_flight;
+	struct semaphore	in_flight;
 	struct closure_with_timer writeback;
-	struct closure_waitlist	writeback_wait;
 	struct keybuf		writeback_keys;

drivers/md/bcache/bset.c+28−11

 /* Mergesort */
+static void sort_key_next(struct btree_iter *iter,
+			  struct btree_iter_set *i)
+{
+	i->k = bkey_next(i->k);
+	if (i->k == i->end)
+		*i = iter->data[--iter->used];
+}
 static void btree_sort_fixup(struct btree_iter *iter)
 {
 	while (iter->used > 1) {
 		struct btree_iter_set *top = iter->data, *i = top + 1;
-		struct bkey *k;
 		if (iter->used > 2 &&
 		    btree_iter_cmp(i[0], i[1]))
 			i++;
-		for (k = i->k;
+		if (bkey_cmp(top->k, &START_KEY(i->k)) <= 0)
-		     k != i->end && bkey_cmp(top->k, &START_KEY(k)) > 0;
-		     k = bkey_next(k))
-			if (top->k > i->k)
-				__bch_cut_front(top->k, k);
-			else if (KEY_SIZE(k))
-				bch_cut_back(&START_KEY(k), top->k);
-		if (top->k < i->k || k == i->k)
 			break;
-		heap_sift(iter, i - top, btree_iter_cmp);
+		if (!KEY_SIZE(i->k)) {
+			sort_key_next(iter, i);
+			heap_sift(iter, i - top, btree_iter_cmp);
+			continue;
+		}
+		if (top->k > i->k) {
+			if (bkey_cmp(top->k, i->k) >= 0)
+				sort_key_next(iter, i);
+			else
+				bch_cut_front(top->k, i->k);
+			heap_sift(iter, i - top, btree_iter_cmp);
+		} else {
+			/* can't happen because of comparison func */
+			BUG_ON(!bkey_cmp(&START_KEY(top->k), &START_KEY(i->k)));
+			bch_cut_back(&START_KEY(i->k), top->k);
+		}
 	}
 }

drivers/md/bcache/btree.c+2−2

@@ -255,7 +255,7 @@ void bch_btree_node_read(struct btree *b) · 254 unmodified lines
255		255
256	return;	256	return;
257	err:	257	err:
258	bch_cache_set_error(b->c, "io error reading bucket %lu",	258	bch_cache_set_error(b->c, "io error reading bucket %zu",
259	PTR_BUCKET_NR(b->c, &b->key, 0));	259	PTR_BUCKET_NR(b->c, &b->key, 0));
260	}	260	}
261		261
@@ -612,7 +612,7 @@ static unsigned long bch_mca_scan(struct shrinker *shrink, · 350 unmodified lines
612	return SHRINK_STOP;	612	return SHRINK_STOP;
613		613
614	/* Return -1 if we can't do anything right now */	614	/* Return -1 if we can't do anything right now */
615	if (sc->gfp_mask & __GFP_WAIT)	615	if (sc->gfp_mask & __GFP_IO)
616	mutex_lock(&c->bucket_lock);	616	mutex_lock(&c->bucket_lock);
617	else if (!mutex_trylock(&c->bucket_lock))	617	else if (!mutex_trylock(&c->bucket_lock))
618	return -1;	618	return -1;

drivers/md/bcache/journal.c+20−13

@@ -153,7 +153,8 @@ int bch_journal_read(struct cache_set c, struct list_head list, · 152 unmodified lines
153	bitmap_zero(bitmap, SB_JOURNAL_BUCKETS);	153	bitmap_zero(bitmap, SB_JOURNAL_BUCKETS);
154	pr_debug("%u journal buckets", ca->sb.njournal_buckets);	154	pr_debug("%u journal buckets", ca->sb.njournal_buckets);
155		155
156	/* Read journal buckets ordered by golden ratio hash to quickly	156	/*
		157	* Read journal buckets ordered by golden ratio hash to quickly
157	* find a sequence of buckets with valid journal entries	158	* find a sequence of buckets with valid journal entries
158	*/	159	*/
159	for (i = 0; i < ca->sb.njournal_buckets; i++) {	160	for (i = 0; i < ca->sb.njournal_buckets; i++) {
@@ -166,18 +167,20 @@ int bch_journal_read(struct cache_set c, struct list_head list, · 6 unmodified lines
166	goto bsearch;	167	goto bsearch;
167	}	168	}
168		169
169	/* If that fails, check all the buckets we haven't checked	170	/*
		171	* If that fails, check all the buckets we haven't checked
170	* already	172	* already
171	*/	173	*/
172	pr_debug("falling back to linear search");	174	pr_debug("falling back to linear search");
173		175
174	for (l = 0; l < ca->sb.njournal_buckets; l++) {	176	for (l = find_first_zero_bit(bitmap, ca->sb.njournal_buckets);
175	if (test_bit(l, bitmap))	177	l < ca->sb.njournal_buckets;
176	continue;	178	l = find_next_zero_bit(bitmap, ca->sb.njournal_buckets, l + 1))
177
178	if (read_bucket(l))	179	if (read_bucket(l))
179	goto bsearch;	180	goto bsearch;
180	}	181
		182	if (list_empty(list))
		183	continue;
181	bsearch:	184	bsearch:
182	/* Binary search */	185	/* Binary search */
183	m = r = find_next_bit(bitmap, ca->sb.njournal_buckets, l + 1);	186	m = r = find_next_bit(bitmap, ca->sb.njournal_buckets, l + 1);
@@ -197,10 +200,12 @@ bsearch: · 13 unmodified lines
197	r = m;	200	r = m;
198	}	201	}
199		202
200	/* Read buckets in reverse order until we stop finding more	203	/*
		204	* Read buckets in reverse order until we stop finding more
201	* journal entries	205	* journal entries
202	*/	206	*/
203	pr_debug("finishing up");	207	pr_debug("finishing up: m %u njournal_buckets %u",
		208	m, ca->sb.njournal_buckets);
204	l = m;	209	l = m;
205		210
206	while (1) {	211	while (1) {
@@ -228,9 +233,10 @@ bsearch: · 21 unmodified lines
228	}	233	}
229	}	234	}
230		235
231	c->journal.seq = list_entry(list->prev,	236	if (!list_empty(list))
232	struct journal_replay,	237	c->journal.seq = list_entry(list->prev,
233	list)->j.seq;	238	struct journal_replay,
		239	list)->j.seq;
234		240
235	return 0;	241	return 0;
236	#undef read_bucket	242	#undef read_bucket
@@ -428,7 +434,7 @@ static void do_journal_discard(struct cache *ca) · 191 unmodified lines
428	return;	434	return;
429	}	435	}
430		436
431	switch (atomic_read(&ja->discard_in_flight) == DISCARD_IN_FLIGHT) {	437	switch (atomic_read(&ja->discard_in_flight)) {
432	case DISCARD_IN_FLIGHT:	438	case DISCARD_IN_FLIGHT:
433	return;	439	return;
434		440
@@ -689,6 +695,7 @@ void bch_journal_meta(struct cache_set c, struct closure cl) · 254 unmodified lines
689	if (cl)	695	if (cl)
690	BUG_ON(!closure_wait(&w->wait, cl));	696	BUG_ON(!closure_wait(&w->wait, cl));
691		697
		698	closure_flush(&c->journal.io);
692	__journal_try_write(c, true);	699	__journal_try_write(c, true);
693	}	700	}
694	}	701	}

drivers/md/bcache/request.c+9−6

@@ -997,14 +997,17 @@ static void request_write(struct cached_dev dc, struct search s) · 996 unmodified lines
997	} else {	997	} else {
998	bch_writeback_add(dc);	998	bch_writeback_add(dc);
999		999
1000	if (s->op.flush_journal) {	1000	if (bio->bi_rw & REQ_FLUSH) {
1001	/* Also need to send a flush to the backing device */	1001	/* Also need to send a flush to the backing device */
1002	s->op.cache_bio = bio_clone_bioset(bio, GFP_NOIO,	1002	struct bio *flush = bio_alloc_bioset(0, GFP_NOIO,
1003	dc->disk.bio_split);	1003	dc->disk.bio_split);
1004		1004
1005	bio->bi_size = 0;	1005	flush->bi_rw = WRITE_FLUSH;
1006	bio->bi_vcnt = 0;	1006	flush->bi_bdev = bio->bi_bdev;
1007	closure_bio_submit(bio, cl, s->d);	1007	flush->bi_end_io = request_endio;
		1008	flush->bi_private = cl;
		1009
		1010	closure_bio_submit(flush, cl, s->d);
1008	} else {	1011	} else {
1009	s->op.cache_bio = bio;	1012	s->op.cache_bio = bio;
1010	}	1013	}

drivers/md/bcache/sysfs.c+7−2

 	}
 	if (attr == &sysfs_label) {
-		/* note: endlines are preserved */
+		if (size > SB_LABEL_SIZE)
-		memcpy(dc->sb.label, buf, SB_LABEL_SIZE);
+			return -EINVAL;
+		memcpy(dc->sb.label, buf, size);
+		if (size < SB_LABEL_SIZE)
+			dc->sb.label[size] = '\0';
+		if (size && dc->sb.label[size - 1] == '\n')
+			dc->sb.label[size - 1] = '\0';
 		bch_write_bdev_super(dc, NULL);
 		if (dc->disk.c) {
 			memcpy(dc->disk.c->uuids[dc->disk.id].label,

drivers/md/bcache/util.c+10−1

@@ -190,7 +190,16 @@ void bch_time_stats_update(struct time_stats *stats, uint64_t start_time) · 189 unmodified lines
190	stats->last = now ?: 1;	190	stats->last = now ?: 1;
191	}	191	}
192		192
193	unsigned bch_next_delay(struct ratelimit *d, uint64_t done)	193	/**
		194	* bch_next_delay() - increment @d by the amount of work done, and return how
		195	* long to delay until the next time to do some work.
		196	*
		197	* @d - the struct bch_ratelimit to update
		198	* @done - the amount of work done, in arbitrary units
		199	*
		200	* Returns the amount of time to delay by, in jiffies
		201	*/
		202	uint64_t bch_next_delay(struct bch_ratelimit *d, uint64_t done)
194	{	203	{
195	uint64_t now = local_clock();	204	uint64_t now = local_clock();
196		205

drivers/md/bcache/util.h+9−3

 	(ewma) >> factor;						\
 })
-struct ratelimit {
+struct bch_ratelimit {
+	/* Next time we want to do some work, in nanoseconds */
 	uint64_t		next;
+	/*
+	 * Rate at which we want to do work, in units per nanosecond
+	 * The units here correspond to the units passed to bch_next_delay()
+	 */
 	unsigned		rate;
 };
-static inline void ratelimit_reset(struct ratelimit *d)
+static inline void bch_ratelimit_reset(struct bch_ratelimit *d)
 {
 	d->next = local_clock();
 }
-unsigned bch_next_delay(struct ratelimit *d, uint64_t done);
+uint64_t bch_next_delay(struct bch_ratelimit *d, uint64_t done);
 #define __DIV_SAFE(n, d, zero)						\
 ({									\

drivers/md/bcache/writeback.c+20−22

 static unsigned writeback_delay(struct cached_dev *dc, unsigned sectors)
 {
+	uint64_t ret;
 	if (atomic_read(&dc->disk.detaching) ||
 	    !dc->writeback_percent)
 		return 0;
-	return bch_next_delay(&dc->writeback_rate, sectors * 10000000ULL);
+	ret = bch_next_delay(&dc->writeback_rate, sectors * 10000000ULL);
+	return min_t(uint64_t, ret, HZ);
 }
 /* Background writeback */
 	up_write(&dc->writeback_lock);
-	ratelimit_reset(&dc->writeback_rate);
+	bch_ratelimit_reset(&dc->writeback_rate);
 	/* Punt to workqueue only so we don't recurse and blow the stack */
 	continue_at(cl, read_dirty, dirty_wq);
 	}
 	bch_keybuf_del(&dc->writeback_keys, w);
-	atomic_dec_bug(&dc->in_flight);
+	up(&dc->in_flight);
-	closure_wake_up(&dc->writeback_wait);
 	closure_return_with_destructor(cl, dirty_io_destructor);
 }
 	closure_bio_submit(&io->bio, cl, &io->dc->disk);
-	continue_at(cl, write_dirty_finish, dirty_wq);
+	continue_at(cl, write_dirty_finish, system_wq);
 }
 static void read_dirty_endio(struct bio *bio, int error)
 	closure_bio_submit(&io->bio, cl, &io->dc->disk);
-	continue_at(cl, write_dirty, dirty_wq);
+	continue_at(cl, write_dirty, system_wq);
 }
 static void read_dirty(struct closure *cl)
 		if (delay > 0 &&
 		    (KEY_START(&w->key) != dc->last_read ||
-		     jiffies_to_msecs(delay) > 50)) {
+		     jiffies_to_msecs(delay) > 50))
-			w->private = NULL;
+			delay = schedule_timeout_uninterruptible(delay);
-			closure_delay(&dc->writeback, delay);
-			continue_at(cl, read_dirty, dirty_wq);
-		}
 		dc->last_read	= KEY_OFFSET(&w->key);
 		trace_bcache_writeback(&w->key);
-		closure_call(&io->cl, read_dirty_submit, NULL, &dc->disk.cl);
+		down(&dc->in_flight);
+		closure_call(&io->cl, read_dirty_submit, NULL, cl);
 		delay = writeback_delay(dc, KEY_SIZE(&w->key));
-		atomic_inc(&dc->in_flight);
-		if (!closure_wait_event(&dc->writeback_wait, cl,
-					atomic_read(&dc->in_flight) < 64))
-			continue_at(cl, read_dirty, dirty_wq);
 	}
 	if (0) {
 		bch_keybuf_del(&dc->writeback_keys, w);
 	}
-	refill_dirty(cl);
+	/*
+	 * Wait for outstanding writeback IOs to finish (and keybuf slots to be
+	 * freed) before refilling again
+	 */
+	continue_at(cl, refill_dirty, dirty_wq);
 }
 /* Init */
 void bch_cached_dev_writeback_init(struct cached_dev *dc)
 {
+	sema_init(&dc->in_flight, 64);
 	closure_init_unlocked(&dc->writeback);
 	init_rwsem(&dc->writeback_lock);
 int __init bch_writeback_init(void)
 {
-	dirty_wq = create_singlethread_workqueue("bcache_writeback");
+	dirty_wq = create_workqueue("bcache_writeback");
 	if (!dirty_wq)
 		return -ENOMEM;

drivers/md/dm-io.c+3−4

 #define DM_MSG_PREFIX "io"
 #define DM_IO_MAX_REGIONS	BITS_PER_LONG
-#define MIN_IOS		16
-#define MIN_BIOS	16
 struct dm_io_client {
 	mempool_t *pool;
 struct dm_io_client *dm_io_client_create(void)
 {
 	struct dm_io_client *client;
+	unsigned min_ios = dm_get_reserved_bio_based_ios();
 	client = kmalloc(sizeof(*client), GFP_KERNEL);
 	if (!client)
 		return ERR_PTR(-ENOMEM);
-	client->pool = mempool_create_slab_pool(MIN_IOS, _dm_io_cache);
+	client->pool = mempool_create_slab_pool(min_ios, _dm_io_cache);
 	if (!client->pool)
 		goto bad;
-	client->bios = bioset_create(MIN_BIOS, 0);
+	client->bios = bioset_create(min_ios, 0);
 	if (!client->bios)
 		goto bad;

drivers/md/dm-mpath.c+14−4

 #include <linux/device-mapper.h>
+#include "dm.h"
 #include "dm-path-selector.h"
 #include "dm-uevent.h"
 typedef int (*action_fn) (struct pgpath *pgpath);
-#define MIN_IOS 256	/* Mempool size */
 static struct kmem_cache *_mpio_cache;
 static struct workqueue_struct *kmultipathd, *kmpath_handlerd;
 static struct multipath *alloc_multipath(struct dm_target *ti)
 {
 	struct multipath *m;
+	unsigned min_ios = dm_get_reserved_rq_based_ios();
 	m = kzalloc(sizeof(*m), GFP_KERNEL);
 	if (m) {
 		INIT_WORK(&m->trigger_event, trigger_event);
 		init_waitqueue_head(&m->pg_init_wait);
 		mutex_init(&m->work_mutex);
-		m->mpio_pool = mempool_create_slab_pool(MIN_IOS, _mpio_cache);
+		m->mpio_pool = mempool_create_slab_pool(min_ios, _mpio_cache);
 		if (!m->mpio_pool) {
 			kfree(m);
 			return NULL;
 	case -EREMOTEIO:
 	case -EILSEQ:
 	case -ENODATA:
+	case -ENOSPC:
 		return 1;
 	}
 	if (!error && !clone->errors)
 		return 0;	/* I/O complete */
-	if (noretry_error(error))
+	if (noretry_error(error)) {
+		if ((clone->cmd_flags & REQ_WRITE_SAME) &&
+		    !clone->q->limits.max_write_same_sectors) {
+			struct queue_limits *limits;
+			/* device doesn't really support WRITE SAME, disable it */
+			limits = dm_get_queue_limits(dm_table_get_md(m->ti->table));
+			limits->max_write_same_sectors = 0;
+		}
 		return error;
+	}
 	if (mpio->pgpath)
 		fail_path(mpio->pgpath);

drivers/md/dm-snap-persistent.c+1−1

@@ -256,7 +256,7 @@ static int chunk_io(struct pstore ps, void area, chunk_t chunk, int rw, · 255 unmodified lines
256	*/	256	*/
257	INIT_WORK_ONSTACK(&req.work, do_metadata);	257	INIT_WORK_ONSTACK(&req.work, do_metadata);
258	queue_work(ps->metadata_wq, &req.work);	258	queue_work(ps->metadata_wq, &req.work);
259	flush_work(&req.work);	259	flush_workqueue(ps->metadata_wq);
260		260
261	return req.result;	261	return req.result;
262	}	262	}

drivers/md/dm-snap.c+2−3

  */
 static int init_hash_tables(struct dm_snapshot *s)
 {
-	sector_t hash_size, cow_dev_size, origin_dev_size, max_buckets;
+	sector_t hash_size, cow_dev_size, max_buckets;
 	/*
 	 * Calculate based on the size of the original volume or
 	 * the COW volume...
 	 */
 	cow_dev_size = get_dev_size(s->cow->bdev);
-	origin_dev_size = get_dev_size(s->origin->bdev);
 	max_buckets = calc_max_buckets();
-	hash_size = min(origin_dev_size, cow_dev_size) >> s->store->chunk_shift;
+	hash_size = cow_dev_size >> s->store->chunk_shift;
 	hash_size = min(hash_size, max_buckets);
 	if (hash_size < 64)

drivers/md/dm-stats.c+17−6

 	struct dm_stat_percpu *p;
 	/*
-	 * For strict correctness we should use local_irq_disable/enable
+	 * For strict correctness we should use local_irq_save/restore
 	 * instead of preempt_disable/enable.
 	 *
-	 * This is racy if the driver finishes bios from non-interrupt
+	 * preempt_disable/enable is racy if the driver finishes bios
-	 * context as well as from interrupt context or from more different
+	 * from non-interrupt context as well as from interrupt context
-	 * interrupts.
+	 * or from more different interrupts.
 	 *
-	 * However, the race only results in not counting some events,
+	 * On 64-bit architectures the race only results in not counting some
-	 * so it is acceptable.
+	 * events, so it is acceptable.  On 32-bit architectures the race could
+	 * cause the counter going off by 2^32, so we need to do proper locking
+	 * there.
 	 *
 	 * part_stat_lock()/part_stat_unlock() have this race too.
 	 */
+#if BITS_PER_LONG == 32
+	unsigned long flags;
+	local_irq_save(flags);
+#else
 	preempt_disable();
+#endif
 	p = &s->stat_percpu[smp_processor_id()][entry];
 	if (!end) {
 		p->ticks[idx] += duration;
 	}
+#if BITS_PER_LONG == 32
+	local_irq_restore(flags);
+#else
 	preempt_enable();
+#endif
 }
 static void __dm_stat_bio(struct dm_stat *s, unsigned long bi_rw,

drivers/md/dm-thin.c+11−3

 	 * them down to the data device.  The thin device's discard
 	 * processing will cause mappings to be removed from the btree.
 	 */
+	ti->discard_zeroes_data_unsupported = true;
 	if (pf.discard_enabled && pf.discard_passdown) {
 		ti->num_discard_bios = 1;
 		 * thin devices' discard limits consistent).
 		 */
 		ti->discards_supported = true;
-		ti->discard_zeroes_data_unsupported = true;
 	}
 	ti->private = pt;
 	 * They get transferred to the live pool in bind_control_target()
 	 * called from pool_preresume().
 	 */
-	if (!pt->adjusted_pf.discard_enabled)
+	if (!pt->adjusted_pf.discard_enabled) {
+		/*
+		 * Must explicitly disallow stacking discard limits otherwise the
+		 * block layer will stack them if pool's data device has support.
+		 * QUEUE_FLAG_DISCARD wouldn't be set but there is no way for the
+		 * user to see that, so make sure to set all discard limits to 0.
+		 */
+		limits->discard_granularity = 0;
 		return;
+	}
 	disable_passdown_if_not_supported(pt);
 	ti->per_bio_data_size = sizeof(struct dm_thin_endio_hook);
 	/* In case the pool supports discards, pass them on. */
+	ti->discard_zeroes_data_unsupported = true;
 	if (tc->pool->pf.discard_enabled) {
 		ti->discards_supported = true;
 		ti->num_discard_bios = 1;
-		ti->discard_zeroes_data_unsupported = true;
 		/* Discard bios must be split on a block boundary */
 		ti->split_discard_bios = true;
 	}

drivers/md/dm.c+67−4

@@ -211,10 +211,55 @@ struct dm_md_mempools { · 210 unmodified lines
211	struct bio_set *bs;	211	struct bio_set *bs;
212	};	212	};
213		213
214	#define MIN_IOS 256	214	#define RESERVED_BIO_BASED_IOS 16
		215	#define RESERVED_REQUEST_BASED_IOS 256
		216	#define RESERVED_MAX_IOS 1024
215	static struct kmem_cache *_io_cache;	217	static struct kmem_cache *_io_cache;
216	static struct kmem_cache *_rq_tio_cache;	218	static struct kmem_cache *_rq_tio_cache;
217		219
		220	/*
		221	* Bio-based DM's mempools' reserved IOs set by the user.
		222	*/
		223	static unsigned reserved_bio_based_ios = RESERVED_BIO_BASED_IOS;
		224
		225	/*
		226	* Request-based DM's mempools' reserved IOs set by the user.
		227	*/
		228	static unsigned reserved_rq_based_ios = RESERVED_REQUEST_BASED_IOS;
		229
		230	static unsigned __dm_get_reserved_ios(unsigned *reserved_ios,
		231	unsigned def, unsigned max)
		232	{
		233	unsigned ios = ACCESS_ONCE(*reserved_ios);
		234	unsigned modified_ios = 0;
		235
		236	if (!ios)
		237	modified_ios = def;
		238	else if (ios > max)
		239	modified_ios = max;
		240
		241	if (modified_ios) {
		242	(void)cmpxchg(reserved_ios, ios, modified_ios);
		243	ios = modified_ios;
		244	}
		245
		246	return ios;
		247	}
		248
		249	unsigned dm_get_reserved_bio_based_ios(void)
		250	{
		251	return __dm_get_reserved_ios(&reserved_bio_based_ios,
		252	RESERVED_BIO_BASED_IOS, RESERVED_MAX_IOS);
		253	}
		254	EXPORT_SYMBOL_GPL(dm_get_reserved_bio_based_ios);
		255
		256	unsigned dm_get_reserved_rq_based_ios(void)
		257	{
		258	return __dm_get_reserved_ios(&reserved_rq_based_ios,
		259	RESERVED_REQUEST_BASED_IOS, RESERVED_MAX_IOS);
		260	}
		261	EXPORT_SYMBOL_GPL(dm_get_reserved_rq_based_ios);
		262
218	static int __init local_init(void)	263	static int __init local_init(void)
219	{	264	{
220	int r = -ENOMEM;	265	int r = -ENOMEM;
@@ -2277,6 +2322,17 @@ struct target_type dm_get_immutable_target_type(struct mapped_device md) · 2056 unmodified lines
2277	return md->immutable_target_type;	2322	return md->immutable_target_type;
2278	}	2323	}
2279		2324
		2325	/*
		2326	* The queue_limits are only valid as long as you have a reference
		2327	* count on 'md'.
		2328	*/
		2329	struct queue_limits dm_get_queue_limits(struct mapped_device md)
		2330	{
		2331	BUG_ON(!atomic_read(&md->holders));
		2332	return &md->queue->limits;
		2333	}
		2334	EXPORT_SYMBOL_GPL(dm_get_queue_limits);
		2335
2280	/*	2336	/*
2281	* Fully initialize a request-based queue (->elevator, ->request_fn, etc).	2337	* Fully initialize a request-based queue (->elevator, ->request_fn, etc).
2282	*/	2338	*/
@@ -2862,18 +2918,18 @@ struct dm_md_mempools *dm_alloc_md_mempools(unsigned type, unsigned integrity, u · 579 unmodified lines
2862		2918
2863	if (type == DM_TYPE_BIO_BASED) {	2919	if (type == DM_TYPE_BIO_BASED) {
2864	cachep = _io_cache;	2920	cachep = _io_cache;
2865	pool_size = 16;	2921	pool_size = dm_get_reserved_bio_based_ios();
2866	front_pad = roundup(per_bio_data_size, __alignof__(struct dm_target_io)) + offsetof(struct dm_target_io, clone);	2922	front_pad = roundup(per_bio_data_size, __alignof__(struct dm_target_io)) + offsetof(struct dm_target_io, clone);
2867	} else if (type == DM_TYPE_REQUEST_BASED) {	2923	} else if (type == DM_TYPE_REQUEST_BASED) {
2868	cachep = _rq_tio_cache;	2924	cachep = _rq_tio_cache;
2869	pool_size = MIN_IOS;	2925	pool_size = dm_get_reserved_rq_based_ios();
2870	front_pad = offsetof(struct dm_rq_clone_bio_info, clone);	2926	front_pad = offsetof(struct dm_rq_clone_bio_info, clone);
2871	/* per_bio_data_size is not used. See __bind_mempools(). */	2927	/* per_bio_data_size is not used. See __bind_mempools(). */
2872	WARN_ON(per_bio_data_size != 0);	2928	WARN_ON(per_bio_data_size != 0);
2873	} else	2929	} else
2874	goto out;	2930	goto out;
2875		2931
2876	pools->io_pool = mempool_create_slab_pool(MIN_IOS, cachep);	2932	pools->io_pool = mempool_create_slab_pool(pool_size, cachep);
2877	if (!pools->io_pool)	2933	if (!pools->io_pool)
2878	goto out;	2934	goto out;
2879		2935
@@ -2924,6 +2980,13 @@ module_exit(dm_exit); · 44 unmodified lines
2924		2980
2925	module_param(major, uint, 0);	2981	module_param(major, uint, 0);
2926	MODULE_PARM_DESC(major, "The major number of the device mapper");	2982	MODULE_PARM_DESC(major, "The major number of the device mapper");
		2983
		2984	module_param(reserved_bio_based_ios, uint, S_IRUGO \| S_IWUSR);
		2985	MODULE_PARM_DESC(reserved_bio_based_ios, "Reserved IOs in bio-based mempools");
		2986
		2987	module_param(reserved_rq_based_ios, uint, S_IRUGO \| S_IWUSR);
		2988	MODULE_PARM_DESC(reserved_rq_based_ios, "Reserved IOs in request-based mempools");
		2989
2927	MODULE_DESCRIPTION(DM_NAME " driver");	2990	MODULE_DESCRIPTION(DM_NAME " driver");
2928	MODULE_AUTHOR("Joe Thornber <dm-devel@redhat.com>");	2991	MODULE_AUTHOR("Joe Thornber <dm-devel@redhat.com>");
2929	MODULE_LICENSE("GPL");	2992	MODULE_LICENSE("GPL");

drivers/md/dm.h+3−0

 /*
  * Helpers that are used by DM core
  */
+unsigned dm_get_reserved_bio_based_ios(void);
+unsigned dm_get_reserved_rq_based_ios(void);
 static inline bool dm_message_test_buffer_overflow(char *result, unsigned maxlen)
 {
 	return !maxlen || strlen(result) + 1 >= maxlen;

drivers/misc/mei/amthif.c+1−0

@@ -57,6 +57,7 @@ void mei_amthif_reset_params(struct mei_device *dev) · 56 unmodified lines
57	dev->iamthif_ioctl = false;	57	dev->iamthif_ioctl = false;
58	dev->iamthif_state = MEI_IAMTHIF_IDLE;	58	dev->iamthif_state = MEI_IAMTHIF_IDLE;
59	dev->iamthif_timer = 0;	59	dev->iamthif_timer = 0;
		60	dev->iamthif_stall_timer = 0;
60	}	61	}
61		62
62	/**	63	/**

drivers/misc/mei/bus.c+4−1

 	if (cl->reading_state != MEI_READ_COMPLETE &&
 	    !waitqueue_active(&cl->rx_wait)) {
 		mutex_unlock(&dev->device_lock);
 		if (wait_event_interruptible(cl->rx_wait,
-				(MEI_READ_COMPLETE == cl->reading_state))) {
+				cl->reading_state == MEI_READ_COMPLETE  ||
+				mei_cl_is_transitioning(cl))) {
 			if (signal_pending(current))
 				return -EINTR;
 			return -ERESTARTSYS;

drivers/misc/mei/client.h+6−0

 		cl->dev->dev_state == MEI_DEV_ENABLED &&
 		cl->state == MEI_FILE_CONNECTED);
 }
+static inline bool mei_cl_is_transitioning(struct mei_cl *cl)
+{
+	return (MEI_FILE_INITIALIZING == cl->state ||
+		MEI_FILE_DISCONNECTED == cl->state ||
+		MEI_FILE_DISCONNECTING == cl->state);
+}
 bool mei_cl_is_other_connecting(struct mei_cl *cl);
 int mei_cl_disconnect(struct mei_cl *cl);

drivers/misc/mei/hbm.c+6−4

 	struct mei_me_client *clients;
 	int b;
+	dev->me_clients_num = 0;
+	dev->me_client_presentation_num = 0;
+	dev->me_client_index = 0;
 	/* count how many ME clients we have */
 	for_each_set_bit(b, dev->me_clients_map, MEI_CLIENTS_MAX)
 		dev->me_clients_num++;
-	if (dev->me_clients_num <= 0)
+	if (dev->me_clients_num == 0)
 		return;
 	kfree(dev->me_clients);
 	struct hbm_props_request *prop_req;
 	const size_t len = sizeof(struct hbm_props_request);
 	unsigned long next_client_index;
-	u8 client_num;
+	unsigned long client_num;
 	client_num = dev->me_client_presentation_num;
 		if (dev->dev_state == MEI_DEV_INIT_CLIENTS &&
 		    dev->hbm_state == MEI_HBM_ENUM_CLIENTS) {
 				dev->init_clients_timer = 0;
-				dev->me_client_presentation_num = 0;
-				dev->me_client_index = 0;
 				mei_hbm_me_cl_allocate(dev);
 				dev->hbm_state = MEI_HBM_CLIENT_PROPERTIES;

drivers/misc/mei/init.c+3−0

@@ -175,6 +175,9 @@ void mei_reset(struct mei_device *dev, int interrupts_enabled) · 174 unmodified lines
175	memset(&dev->wr_ext_msg, 0, sizeof(dev->wr_ext_msg));	175	memset(&dev->wr_ext_msg, 0, sizeof(dev->wr_ext_msg));
176	}	176	}
177		177
		178	/* we're already in reset, cancel the init timer */
		179	dev->init_clients_timer = 0;
		180
178	dev->me_clients_num = 0;	181	dev->me_clients_num = 0;
179	dev->rd_msg_hdr = 0;	182	dev->rd_msg_hdr = 0;
180	dev->wd_pending = false;	183	dev->wd_pending = false;

drivers/misc/mei/main.c+4−7

@@ -249,19 +249,16 @@ static ssize_t mei_read(struct file file, char __user ubuf, · 248 unmodified lines
249	mutex_unlock(&dev->device_lock);	249	mutex_unlock(&dev->device_lock);
250		250
251	if (wait_event_interruptible(cl->rx_wait,	251	if (wait_event_interruptible(cl->rx_wait,
252	(MEI_READ_COMPLETE == cl->reading_state \|\|	252	MEI_READ_COMPLETE == cl->reading_state \|\|
253	MEI_FILE_INITIALIZING == cl->state \|\|	253	mei_cl_is_transitioning(cl))) {
254	MEI_FILE_DISCONNECTED == cl->state \|\|	254
255	MEI_FILE_DISCONNECTING == cl->state))) {
256	if (signal_pending(current))	255	if (signal_pending(current))
257	return -EINTR;	256	return -EINTR;
258	return -ERESTARTSYS;	257	return -ERESTARTSYS;
259	}	258	}
260		259
261	mutex_lock(&dev->device_lock);	260	mutex_lock(&dev->device_lock);
262	if (MEI_FILE_INITIALIZING == cl->state \|\|	261	if (mei_cl_is_transitioning(cl)) {
263	MEI_FILE_DISCONNECTED == cl->state \|\|
264	MEI_FILE_DISCONNECTING == cl->state) {
265	rets = -EBUSY;	262	rets = -EBUSY;
266	goto out;	263	goto out;
267	}	264	}

drivers/misc/mei/mei_dev.h+3−3

@@ -396,9 +396,9 @@ struct mei_device { · 395 unmodified lines
396	struct mei_me_client me_clients; / Note: memory has to be allocated */	396	struct mei_me_client me_clients; / Note: memory has to be allocated */
397	DECLARE_BITMAP(me_clients_map, MEI_CLIENTS_MAX);	397	DECLARE_BITMAP(me_clients_map, MEI_CLIENTS_MAX);
398	DECLARE_BITMAP(host_clients_map, MEI_CLIENTS_MAX);	398	DECLARE_BITMAP(host_clients_map, MEI_CLIENTS_MAX);
399	u8 me_clients_num;	399	unsigned long me_clients_num;
400	u8 me_client_presentation_num;	400	unsigned long me_client_presentation_num;
401	u8 me_client_index;	401	unsigned long me_client_index;
402		402
403	struct mei_cl wd_cl;	403	struct mei_cl wd_cl;
404	enum mei_wd_states wd_state;	404	enum mei_wd_states wd_state;

drivers/mmc/host/sh_mobile_sdhi.c+8−8

@@ -113,14 +113,14 @@ static const struct sh_mobile_sdhi_ops sdhi_ops = { · 112 unmodified lines
113	};	113	};
114		114
115	static const struct of_device_id sh_mobile_sdhi_of_match[] = {	115	static const struct of_device_id sh_mobile_sdhi_of_match[] = {
116	{ .compatible = "renesas,shmobile-sdhi" },	116	{ .compatible = "renesas,sdhi-shmobile" },
117	{ .compatible = "renesas,sh7372-sdhi" },	117	{ .compatible = "renesas,sdhi-sh7372" },
118	{ .compatible = "renesas,sh73a0-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },	118	{ .compatible = "renesas,sdhi-sh73a0", .data = &sh_mobile_sdhi_of_cfg[0], },
119	{ .compatible = "renesas,r8a73a4-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },	119	{ .compatible = "renesas,sdhi-r8a73a4", .data = &sh_mobile_sdhi_of_cfg[0], },
120	{ .compatible = "renesas,r8a7740-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },	120	{ .compatible = "renesas,sdhi-r8a7740", .data = &sh_mobile_sdhi_of_cfg[0], },
121	{ .compatible = "renesas,r8a7778-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },	121	{ .compatible = "renesas,sdhi-r8a7778", .data = &sh_mobile_sdhi_of_cfg[0], },
122	{ .compatible = "renesas,r8a7779-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },	122	{ .compatible = "renesas,sdhi-r8a7779", .data = &sh_mobile_sdhi_of_cfg[0], },
123	{ .compatible = "renesas,r8a7790-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },	123	{ .compatible = "renesas,sdhi-r8a7790", .data = &sh_mobile_sdhi_of_cfg[0], },
124	{},	124	{},
125	};	125	};
126	MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);	126	MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);

drivers/mtd/nand/pxa3xx_nand.c+0−7

 	return 0;
 }
-#ifdef CONFIG_OF
 static struct of_device_id pxa3xx_nand_dt_ids[] = {
 	{
 		.compatible = "marvell,pxa3xx-nand",
 	return 0;
 }
-#else
-static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
-{
-	return 0;
-}
-#endif
 static int pxa3xx_nand_probe(struct platform_device *pdev)
 {

drivers/net/bonding/bond_alb.c+1−1

@@ -1472,7 +1472,7 @@ void bond_alb_monitor(struct work_struct *work) · 1471 unmodified lines
1472	bond_info->lp_counter++;	1472	bond_info->lp_counter++;
1473		1473
1474	/* send learning packets */	1474	/* send learning packets */
1475	if (bond_info->lp_counter >= BOND_ALB_LP_TICKS) {	1475	if (bond_info->lp_counter >= BOND_ALB_LP_TICKS(bond)) {
1476	/* change of curr_active_slave involves swapping of mac addresses.	1476	/* change of curr_active_slave involves swapping of mac addresses.
1477	* in order to avoid this swapping from happening while	1477	* in order to avoid this swapping from happening while
1478	* sending the learning packets, the curr_slave_lock must be held for	1478	* sending the learning packets, the curr_slave_lock must be held for

drivers/net/bonding/bond_alb.h+5−4

 					 * Used for division - never set
 					 * to zero !!!
 					 */
-#define BOND_ALB_LP_INTERVAL	    1	/* In seconds, periodic send of
+#define BOND_ALB_DEFAULT_LP_INTERVAL 1
-					 * learning packets to the switch
+#define BOND_ALB_LP_INTERVAL(bond) (bond->params.lp_interval)	/* In seconds, periodic send of
-					 */
+								 * learning packets to the switch
+								 */
 #define BOND_TLB_REBALANCE_TICKS (BOND_TLB_REBALANCE_INTERVAL \
 				  * ALB_TIMER_TICKS_PER_SEC)
-#define BOND_ALB_LP_TICKS (BOND_ALB_LP_INTERVAL \
+#define BOND_ALB_LP_TICKS(bond) (BOND_ALB_LP_INTERVAL(bond) \
 			   * ALB_TIMER_TICKS_PER_SEC)
 #define TLB_HASH_TABLE_SIZE 256	/* The size of the clients hash table.

drivers/net/bonding/bond_main.c+11−3

 	struct bonding *bond = netdev_priv(bond_dev);
 	struct slave *slave, *oldcurrent;
 	struct sockaddr addr;
+	int old_flags = bond_dev->flags;
 	netdev_features_t old_features = bond_dev->features;
 	/* slave is not a slave or master is not master of this slave */
 	 * bond_change_active_slave(..., NULL)
 	 */
 	if (!USES_PRIMARY(bond->params.mode)) {
-		/* unset promiscuity level from slave */
+		/* unset promiscuity level from slave
-		if (bond_dev->flags & IFF_PROMISC)
+		 * NOTE: The NETDEV_CHANGEADDR call above may change the value
+		 * of the IFF_PROMISC flag in the bond_dev, but we need the
+		 * value of that flag before that change, as that was the value
+		 * when this slave was attached, so we cache at the start of the
+		 * function and use it here. Same goes for ALLMULTI below
+		 */
+		if (old_flags & IFF_PROMISC)
 			dev_set_promiscuity(slave_dev, -1);
 		/* unset allmulti level from slave */
-		if (bond_dev->flags & IFF_ALLMULTI)
+		if (old_flags & IFF_ALLMULTI)
 			dev_set_allmulti(slave_dev, -1);
 		bond_hw_addr_flush(bond_dev, slave_dev);
 	params->all_slaves_active = all_slaves_active;
 	params->resend_igmp = resend_igmp;
 	params->min_links = min_links;
+	params->lp_interval = BOND_ALB_DEFAULT_LP_INTERVAL;
 	if (primary) {
 		strncpy(params->primary, primary, IFNAMSIZ);

drivers/net/bonding/bond_sysfs.c+39−0

@@ -1699,6 +1699,44 @@ out: · 1698 unmodified lines
1699	static DEVICE_ATTR(resend_igmp, S_IRUGO \| S_IWUSR,	1699	static DEVICE_ATTR(resend_igmp, S_IRUGO \| S_IWUSR,
1700	bonding_show_resend_igmp, bonding_store_resend_igmp);	1700	bonding_show_resend_igmp, bonding_store_resend_igmp);
1701		1701
		1702
		1703	static ssize_t bonding_show_lp_interval(struct device *d,
		1704	struct device_attribute *attr,
		1705	char *buf)
		1706	{
		1707	struct bonding *bond = to_bond(d);
		1708	return sprintf(buf, "%d\n", bond->params.lp_interval);
		1709	}
		1710
		1711	static ssize_t bonding_store_lp_interval(struct device *d,
		1712	struct device_attribute *attr,
		1713	const char *buf, size_t count)
		1714	{
		1715	struct bonding *bond = to_bond(d);
		1716	int new_value, ret = count;
		1717
		1718	if (sscanf(buf, "%d", &new_value) != 1) {
		1719	pr_err("%s: no lp interval value specified.\n",
		1720	bond->dev->name);
		1721	ret = -EINVAL;
		1722	goto out;
		1723	}
		1724
		1725	if (new_value <= 0) {
		1726	pr_err ("%s: lp_interval must be between 1 and %d\n",
		1727	bond->dev->name, INT_MAX);
		1728	ret = -EINVAL;
		1729	goto out;
		1730	}
		1731
		1732	bond->params.lp_interval = new_value;
		1733	out:
		1734	return ret;
		1735	}
		1736
		1737	static DEVICE_ATTR(lp_interval, S_IRUGO \| S_IWUSR,
		1738	bonding_show_lp_interval, bonding_store_lp_interval);
		1739
1702	static struct attribute *per_bond_attrs[] = {	1740	static struct attribute *per_bond_attrs[] = {
1703	&dev_attr_slaves.attr,	1741	&dev_attr_slaves.attr,
1704	&dev_attr_mode.attr,	1742	&dev_attr_mode.attr,
@@ -1729,6 +1767,7 @@ static struct attribute *per_bond_attrs[] = { · 24 unmodified lines
1729	&dev_attr_all_slaves_active.attr,	1767	&dev_attr_all_slaves_active.attr,
1730	&dev_attr_resend_igmp.attr,	1768	&dev_attr_resend_igmp.attr,
1731	&dev_attr_min_links.attr,	1769	&dev_attr_min_links.attr,
		1770	&dev_attr_lp_interval.attr,
1732	NULL,	1771	NULL,
1733	};	1772	};
1734		1773

drivers/net/bonding/bonding.h+1−0

@@ -176,6 +176,7 @@ struct bond_params { · 175 unmodified lines
176	int tx_queues;	176	int tx_queues;
177	int all_slaves_active;	177	int all_slaves_active;
178	int resend_igmp;	178	int resend_igmp;
		179	int lp_interval;
179	};	180	};
180		181
181	struct bond_parm_tbl {	182	struct bond_parm_tbl {

drivers/net/can/flexcan.c+0−12

 {
 	struct flexcan_priv *priv = netdev_priv(dev);
 	struct flexcan_regs __iomem *regs = priv->base;
-	unsigned int i;
 	int err;
 	u32 reg_mcr, reg_ctrl;
 	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
 	flexcan_write(reg_ctrl, &regs->ctrl);
-	for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
-		flexcan_write(0, &regs->cantxfg[i].can_ctrl);
-		flexcan_write(0, &regs->cantxfg[i].can_id);
-		flexcan_write(0, &regs->cantxfg[i].data[0]);
-		flexcan_write(0, &regs->cantxfg[i].data[1]);
-		/* put MB into rx queue */
-		flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
-			&regs->cantxfg[i].can_ctrl);
-	}
 	/* acceptance mask/acceptance code (accept everything) */
 	flexcan_write(0x0, &regs->rxgmask);
 	flexcan_write(0x0, &regs->rx14mask);

drivers/net/can/slcan.c+90−49

@@ -76,6 +76,10 @@ MODULE_PARM_DESC(maxdev, "Maximum number of slcan interfaces"); · 75 unmodified lines
76	/* maximum rx buffer len: extended CAN frame with timestamp */	76	/* maximum rx buffer len: extended CAN frame with timestamp */
77	#define SLC_MTU (sizeof("T1111222281122334455667788EA5F\r")+1)	77	#define SLC_MTU (sizeof("T1111222281122334455667788EA5F\r")+1)
78		78
		79	#define SLC_CMD_LEN 1
		80	#define SLC_SFF_ID_LEN 3
		81	#define SLC_EFF_ID_LEN 8
		82
79	struct slcan {	83	struct slcan {
80	int magic;	84	int magic;
81		85
@@ -142,47 +146,63 @@ static void slc_bump(struct slcan *sl) · 60 unmodified lines
142	{	146	{
143	struct sk_buff *skb;	147	struct sk_buff *skb;
144	struct can_frame cf;	148	struct can_frame cf;
145	int i, dlc_pos, tmp;	149	int i, tmp;
146	unsigned long ultmp;	150	u32 tmpid;
147	char cmd = sl->rbuff[0];	151	char *cmd = sl->rbuff;
148		152
149	if ((cmd != 't') && (cmd != 'T') && (cmd != 'r') && (cmd != 'R'))	153	cf.can_id = 0;
		154
		155	switch (*cmd) {
		156	case 'r':
		157	cf.can_id = CAN_RTR_FLAG;
		158	/* fallthrough */
		159	case 't':
		160	/* store dlc ASCII value and terminate SFF CAN ID string */
		161	cf.can_dlc = sl->rbuff[SLC_CMD_LEN + SLC_SFF_ID_LEN];
		162	sl->rbuff[SLC_CMD_LEN + SLC_SFF_ID_LEN] = 0;
		163	/* point to payload data behind the dlc */
		164	cmd += SLC_CMD_LEN + SLC_SFF_ID_LEN + 1;
		165	break;
		166	case 'R':
		167	cf.can_id = CAN_RTR_FLAG;
		168	/* fallthrough */
		169	case 'T':
		170	cf.can_id \|= CAN_EFF_FLAG;
		171	/* store dlc ASCII value and terminate EFF CAN ID string */
		172	cf.can_dlc = sl->rbuff[SLC_CMD_LEN + SLC_EFF_ID_LEN];
		173	sl->rbuff[SLC_CMD_LEN + SLC_EFF_ID_LEN] = 0;
		174	/* point to payload data behind the dlc */
		175	cmd += SLC_CMD_LEN + SLC_EFF_ID_LEN + 1;
		176	break;
		177	default:
150	return;	178	return;
		179	}
151		180
152	if (cmd & 0x20) /* tiny chars 'r' 't' => standard frame format */	181	if (kstrtou32(sl->rbuff + SLC_CMD_LEN, 16, &tmpid))
153	dlc_pos = 4; /* dlc position tiiid */
154	else
155	dlc_pos = 9; /* dlc position Tiiiiiiiid */
156
157	if (!((sl->rbuff[dlc_pos] >= '0') && (sl->rbuff[dlc_pos] < '9')))
158	return;	182	return;
159		183
160	cf.can_dlc = sl->rbuff[dlc_pos] - '0'; /* get can_dlc from ASCII val */	184	cf.can_id \|= tmpid;
161		185
162	sl->rbuff[dlc_pos] = 0; /* terminate can_id string */	186	/* get can_dlc from sanitized ASCII value */
163		187	if (cf.can_dlc >= '0' && cf.can_dlc < '9')
164	if (kstrtoul(sl->rbuff+1, 16, &ultmp))	188	cf.can_dlc -= '0';
		189	else
165	return;	190	return;
166		191
167	cf.can_id = ultmp;
168
169	if (!(cmd & 0x20)) /* NO tiny chars => extended frame format */
170	cf.can_id \|= CAN_EFF_FLAG;
171
172	if ((cmd \| 0x20) == 'r') /* RTR frame */
173	cf.can_id \|= CAN_RTR_FLAG;
174
175	(u64 ) (&cf.data) = 0; /* clear payload */	192	(u64 ) (&cf.data) = 0; /* clear payload */
176		193
177	for (i = 0, dlc_pos++; i < cf.can_dlc; i++) {	194	/* RTR frames may have a dlc > 0 but they never have any data bytes */
178	tmp = hex_to_bin(sl->rbuff[dlc_pos++]);	195	if (!(cf.can_id & CAN_RTR_FLAG)) {
179	if (tmp < 0)	196	for (i = 0; i < cf.can_dlc; i++) {
180	return;	197	tmp = hex_to_bin(*cmd++);
181	cf.data[i] = (tmp << 4);	198	if (tmp < 0)
182	tmp = hex_to_bin(sl->rbuff[dlc_pos++]);	199	return;
183	if (tmp < 0)	200	cf.data[i] = (tmp << 4);
184	return;	201	tmp = hex_to_bin(*cmd++);
185	cf.data[i] \|= tmp;	202	if (tmp < 0)
		203	return;
		204	cf.data[i] \|= tmp;
		205	}
186	}	206	}
187		207
188	skb = dev_alloc_skb(sizeof(struct can_frame) +	208	skb = dev_alloc_skb(sizeof(struct can_frame) +
@@ -209,7 +229,6 @@ static void slc_bump(struct slcan *sl) · 20 unmodified lines
209	/* parse tty input stream */	229	/* parse tty input stream */
210	static void slcan_unesc(struct slcan *sl, unsigned char s)	230	static void slcan_unesc(struct slcan *sl, unsigned char s)
211	{	231	{
212
213	if ((s == '\r') \|\| (s == '\a')) { /* CR or BEL ends the pdu */	232	if ((s == '\r') \|\| (s == '\a')) { /* CR or BEL ends the pdu */
214	if (!test_and_clear_bit(SLF_ERROR, &sl->flags) &&	233	if (!test_and_clear_bit(SLF_ERROR, &sl->flags) &&
215	(sl->rcount > 4)) {	234	(sl->rcount > 4)) {
@@ -236,27 +255,46 @@ static void slcan_unesc(struct slcan *sl, unsigned char s) · 20 unmodified lines
236	/* Encapsulate one can_frame and stuff into a TTY queue. */	255	/* Encapsulate one can_frame and stuff into a TTY queue. */
237	static void slc_encaps(struct slcan sl, struct can_frame cf)	256	static void slc_encaps(struct slcan sl, struct can_frame cf)
238	{	257	{
239	int actual, idx, i;	258	int actual, i;
240	char cmd;	259	unsigned char *pos;
		260	unsigned char *endpos;
		261	canid_t id = cf->can_id;
		262
		263	pos = sl->xbuff;
241		264
242	if (cf->can_id & CAN_RTR_FLAG)	265	if (cf->can_id & CAN_RTR_FLAG)
243	cmd = 'R'; /* becomes 'r' in standard frame format */	266	pos = 'R'; / becomes 'r' in standard frame format (SFF) */
244	else	267	else
245	cmd = 'T'; /* becomes 't' in standard frame format */	268	pos = 'T'; / becomes 't' in standard frame format (SSF) */
246		269
247	if (cf->can_id & CAN_EFF_FLAG)	270	/* determine number of chars for the CAN-identifier */
248	sprintf(sl->xbuff, "%c%08X%d", cmd,	271	if (cf->can_id & CAN_EFF_FLAG) {
249	cf->can_id & CAN_EFF_MASK, cf->can_dlc);	272	id &= CAN_EFF_MASK;
250	else	273	endpos = pos + SLC_EFF_ID_LEN;
251	sprintf(sl->xbuff, "%c%03X%d", cmd \| 0x20,	274	} else {
252	cf->can_id & CAN_SFF_MASK, cf->can_dlc);	275	pos \|= 0x20; / convert R/T to lower case for SFF */
		276	id &= CAN_SFF_MASK;
		277	endpos = pos + SLC_SFF_ID_LEN;
		278	}
253		279
254	idx = strlen(sl->xbuff);	280	/* build 3 (SFF) or 8 (EFF) digit CAN identifier */
		281	pos++;
		282	while (endpos >= pos) {
		283	*endpos-- = hex_asc_upper[id & 0xf];
		284	id >>= 4;
		285	}
		286
		287	pos += (cf->can_id & CAN_EFF_FLAG) ? SLC_EFF_ID_LEN : SLC_SFF_ID_LEN;
255		288
256	for (i = 0; i < cf->can_dlc; i++)	289	*pos++ = cf->can_dlc + '0';
257	sprintf(&sl->xbuff[idx + 2*i], "%02X", cf->data[i]);	290
		291	/* RTR frames may have a dlc > 0 but they never have any data bytes */
		292	if (!(cf->can_id & CAN_RTR_FLAG)) {
		293	for (i = 0; i < cf->can_dlc; i++)
		294	pos = hex_byte_pack_upper(pos, cf->data[i]);
		295	}
258		296
259	strcat(sl->xbuff, "\r"); /* add terminating character */	297	*pos++ = '\r';
260		298
261	/* Order of next two lines is very important.	299	/* Order of next two lines is very important.
262	* When we are sending a little amount of data,	300	* When we are sending a little amount of data,
@@ -267,8 +305,8 @@ static void slc_encaps(struct slcan sl, struct can_frame cf) · 4 unmodified lines
267	* 14 Oct 1994 Dmitry Gorodchanin.	305	* 14 Oct 1994 Dmitry Gorodchanin.
268	*/	306	*/
269	set_bit(TTY_DO_WRITE_WAKEUP, &sl->tty->flags);	307	set_bit(TTY_DO_WRITE_WAKEUP, &sl->tty->flags);
270	actual = sl->tty->ops->write(sl->tty, sl->xbuff, strlen(sl->xbuff));	308	actual = sl->tty->ops->write(sl->tty, sl->xbuff, pos - sl->xbuff);
271	sl->xleft = strlen(sl->xbuff) - actual;	309	sl->xleft = (pos - sl->xbuff) - actual;
272	sl->xhead = sl->xbuff + actual;	310	sl->xhead = sl->xbuff + actual;
273	sl->dev->stats.tx_bytes += cf->can_dlc;	311	sl->dev->stats.tx_bytes += cf->can_dlc;
274	}	312	}
@@ -286,11 +324,13 @@ static void slcan_write_wakeup(struct tty_struct *tty) · 11 unmodified lines
286	if (!sl \|\| sl->magic != SLCAN_MAGIC \|\| !netif_running(sl->dev))	324	if (!sl \|\| sl->magic != SLCAN_MAGIC \|\| !netif_running(sl->dev))
287	return;	325	return;
288		326
		327	spin_lock(&sl->lock);
289	if (sl->xleft <= 0) {	328	if (sl->xleft <= 0) {
290	/* Now serial buffer is almost free & we can start	329	/* Now serial buffer is almost free & we can start
291	* transmission of another packet */	330	* transmission of another packet */
292	sl->dev->stats.tx_packets++;	331	sl->dev->stats.tx_packets++;
293	clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);	332	clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
		333	spin_unlock(&sl->lock);
294	netif_wake_queue(sl->dev);	334	netif_wake_queue(sl->dev);
295	return;	335	return;
296	}	336	}
@@ -298,6 +338,7 @@ static void slcan_write_wakeup(struct tty_struct *tty) · 1 unmodified line
298	actual = tty->ops->write(tty, sl->xhead, sl->xleft);	338	actual = tty->ops->write(tty, sl->xhead, sl->xleft);
299	sl->xleft -= actual;	339	sl->xleft -= actual;
300	sl->xhead += actual;	340	sl->xhead += actual;
		341	spin_unlock(&sl->lock);
301	}	342	}
302		343
303	/* Send a can_frame to a TTY queue. */	344	/* Send a can_frame to a TTY queue. */

drivers/net/can/usb/peak_usb/pcan_usb_core.c+11−4

 	if (i < PCAN_USB_MAX_TX_URBS) {
 		if (i == 0) {
 			netdev_err(netdev, "couldn't setup any tx URB\n");
-			return err;
+			goto err_tx;
 		}
 		netdev_warn(netdev, "tx performance may be slow\n");
 	if (dev->adapter->dev_start) {
 		err = dev->adapter->dev_start(dev);
 		if (err)
-			goto failed;
+			goto err_adapter;
 	}
 	dev->state |= PCAN_USB_STATE_STARTED;
 	if (dev->adapter->dev_set_bus) {
 		err = dev->adapter->dev_set_bus(dev, 1);
 		if (err)
-			goto failed;
+			goto err_adapter;
 	}
 	dev->can.state = CAN_STATE_ERROR_ACTIVE;
 	return 0;
-failed:
+err_adapter:
 	if (err == -ENODEV)
 		netif_device_detach(dev->netdev);
 	netdev_warn(netdev, "couldn't submit control: %d\n", err);
+	for (i = 0; i < PCAN_USB_MAX_TX_URBS; i++) {
+		usb_free_urb(dev->tx_contexts[i].urb);
+		dev->tx_contexts[i].urb = NULL;
+	}
+err_tx:
+	usb_kill_anchored_urbs(&dev->rx_submitted);
 	return err;
 }

drivers/net/ethernet/adi/bfin_mac.c+2−2

@@ -530,7 +530,7 @@ static int bfin_mac_ethtool_setwol(struct net_device *dev, · 529 unmodified lines
530	if (lp->wol && !lp->irq_wake_requested) {	530	if (lp->wol && !lp->irq_wake_requested) {
531	/* register wake irq handler */	531	/* register wake irq handler */
532	rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,	532	rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
533	IRQF_DISABLED, "EMAC_WAKE", dev);	533	0, "EMAC_WAKE", dev);
534	if (rc)	534	if (rc)
535	return rc;	535	return rc;
536	lp->irq_wake_requested = true;	536	lp->irq_wake_requested = true;
@@ -1686,7 +1686,7 @@ static int bfin_mac_probe(struct platform_device *pdev) · 1149 unmodified lines
1686	/* now, enable interrupts */	1686	/* now, enable interrupts */
1687	/* register irq handler */	1687	/* register irq handler */
1688	rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,	1688	rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1689	IRQF_DISABLED, "EMAC_RX", ndev);	1689	0, "EMAC_RX", ndev);
1690	if (rc) {	1690	if (rc) {
1691	dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");	1691	dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1692	rc = -EBUSY;	1692	rc = -EBUSY;

drivers/net/ethernet/amd/sun3lance.c+1−1

@@ -358,7 +358,7 @@ static int __init lance_probe( struct net_device *dev) · 357 unmodified lines
358		358
359	REGA(CSR0) = CSR0_STOP;	359	REGA(CSR0) = CSR0_STOP;
360		360
361	if (request_irq(LANCE_IRQ, lance_interrupt, IRQF_DISABLED, "SUN3 Lance", dev) < 0) {	361	if (request_irq(LANCE_IRQ, lance_interrupt, 0, "SUN3 Lance", dev) < 0) {
362	#ifdef CONFIG_SUN3	362	#ifdef CONFIG_SUN3
363	iounmap((void __iomem *)ioaddr);	363	iounmap((void __iomem *)ioaddr);
364	#endif	364	#endif

drivers/net/ethernet/atheros/alx/main.c+2−7

 	struct alx_priv *alx;
 	struct alx_hw *hw;
 	bool phy_configured;
-	int bars, pm_cap, err;
+	int bars, err;
 	err = pci_enable_device_mem(pdev);
 	if (err)
 	pci_enable_pcie_error_reporting(pdev);
 	pci_set_master(pdev);
-	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
+	if (!pdev->pm_cap) {
-	if (pm_cap == 0) {
 		dev_err(&pdev->dev,
 			"Can't find power management capability, aborting\n");
 		err = -EIO;
 		goto out_pci_release;
 	}
-	err = pci_set_power_state(pdev, PCI_D0);
-	if (err)
-		goto out_pci_release;
 	netdev = alloc_etherdev(sizeof(*alx));
 	if (!netdev) {
 		err = -ENOMEM;

drivers/net/ethernet/broadcom/bgmac.c+31−13

 	if (++ring->end >= BGMAC_TX_RING_SLOTS)
 		ring->end = 0;
 	bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
+		    ring->index_base +
 		    ring->end * sizeof(struct bgmac_dma_desc));
 	/* Always keep one slot free to allow detecting bugged calls. */
 	/* The last slot that hardware didn't consume yet */
 	empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
 	empty_slot &= BGMAC_DMA_TX_STATDPTR;
+	empty_slot -= ring->index_base;
+	empty_slot &= BGMAC_DMA_TX_STATDPTR;
 	empty_slot /= sizeof(struct bgmac_dma_desc);
 	while (ring->start != empty_slot) {
 	end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
 	end_slot &= BGMAC_DMA_RX_STATDPTR;
+	end_slot -= ring->index_base;
+	end_slot &= BGMAC_DMA_RX_STATDPTR;
 	end_slot /= sizeof(struct bgmac_dma_desc);
 	ring->end = end_slot;
 		ring = &bgmac->tx_ring[i];
 		ring->num_slots = BGMAC_TX_RING_SLOTS;
 		ring->mmio_base = ring_base[i];
-		if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_TX))
-			bgmac_warn(bgmac, "TX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
-				   ring->mmio_base);
 		/* Alloc ring of descriptors */
 		size = ring->num_slots * sizeof(struct bgmac_dma_desc);
 		if (ring->dma_base & 0xC0000000)
 			bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
+		ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
+						      BGMAC_DMA_RING_TX);
+		if (ring->unaligned)
+			ring->index_base = lower_32_bits(ring->dma_base);
+		else
+			ring->index_base = 0;
 		/* No need to alloc TX slots yet */
 	}
 		ring = &bgmac->rx_ring[i];
 		ring->num_slots = BGMAC_RX_RING_SLOTS;
 		ring->mmio_base = ring_base[i];
-		if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_RX))
-			bgmac_warn(bgmac, "RX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
-				   ring->mmio_base);
 		/* Alloc ring of descriptors */
 		size = ring->num_slots * sizeof(struct bgmac_dma_desc);
 		if (ring->dma_base & 0xC0000000)
 			bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
+		ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
+						      BGMAC_DMA_RING_RX);
+		if (ring->unaligned)
+			ring->index_base = lower_32_bits(ring->dma_base);
+		else
+			ring->index_base = 0;
 		/* Alloc RX slots */
 		for (j = 0; j < ring->num_slots; j++) {
 			err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
 	for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
 		ring = &bgmac->tx_ring[i];
-		/* We don't implement unaligned addressing, so enable first */
+		if (!ring->unaligned)
-		bgmac_dma_tx_enable(bgmac, ring);
+			bgmac_dma_tx_enable(bgmac, ring);
 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
 			    lower_32_bits(ring->dma_base));
 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
 			    upper_32_bits(ring->dma_base));
+		if (ring->unaligned)
+			bgmac_dma_tx_enable(bgmac, ring);
 		ring->start = 0;
 		ring->end = 0;	/* Points the slot that should *not* be read */
 		ring = &bgmac->rx_ring[i];
-		/* We don't implement unaligned addressing, so enable first */
+		if (!ring->unaligned)
-		bgmac_dma_rx_enable(bgmac, ring);
+			bgmac_dma_rx_enable(bgmac, ring);
 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
 			    lower_32_bits(ring->dma_base));
 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
 			    upper_32_bits(ring->dma_base));
+		if (ring->unaligned)
+			bgmac_dma_rx_enable(bgmac, ring);
 		for (j = 0, dma_desc = ring->cpu_base; j < ring->num_slots;
 		     j++, dma_desc++) {
 		}
 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
+			    ring->index_base +
 			    ring->num_slots * sizeof(struct bgmac_dma_desc));
 		ring->start = 0;
 		struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
 		u8 et_swtype = 0;
 		u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
-			     BGMAC_CHIPCTL_1_IF_TYPE_RMII;
+			     BGMAC_CHIPCTL_1_IF_TYPE_MII;
-		char buf[2];
+		char buf[4];
-		if (bcm47xx_nvram_getenv("et_swtype", buf, 1) > 0) {
+		if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
 			if (kstrtou8(buf, 0, &et_swtype))
 				bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
 					  buf);

drivers/net/ethernet/broadcom/bgmac.h+3−1

 #define BGMAC_CHIPCTL_1_IF_TYPE_MASK		0x00000030
 #define BGMAC_CHIPCTL_1_IF_TYPE_RMII		0x00000000
-#define BGMAC_CHIPCTL_1_IF_TYPE_MI		0x00000010
+#define BGMAC_CHIPCTL_1_IF_TYPE_MII		0x00000010
 #define BGMAC_CHIPCTL_1_IF_TYPE_RGMII		0x00000020
 #define BGMAC_CHIPCTL_1_SW_TYPE_MASK		0x000000C0
 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHY		0x00000000
 	u16 mmio_base;
 	struct bgmac_dma_desc *cpu_base;
 	dma_addr_t dma_base;
+	u32 index_base; /* Used for unaligned rings only, otherwise 0 */
+	bool unaligned;
 	struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS];
 };

drivers/net/ethernet/broadcom/bnx2x/bnx2x.h+33−4

@@ -246,8 +246,37 @@ enum { · 245 unmodified lines
246	BNX2X_MAX_CNIC_ETH_CL_ID_IDX,	246	BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
247	};	247	};
248		248
249	#define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\	249	/* use a value high enough to be above all the PFs, which has least significant
		250	* nibble as 8, so when cnic needs to come up with a CID for UIO to use to
		251	* calculate doorbell address according to old doorbell configuration scheme
		252	* (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
		253	* We must avoid coming up with cid 8 for iscsi since according to this method
		254	* the designated UIO cid will come out 0 and it has a special handling for that
		255	* case which doesn't suit us. Therefore will will cieling to closes cid which
		256	* has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
		257	*/
		258
		259	#define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
250	(bp)->max_cos)	260	(bp)->max_cos)
		261	/* amount of cids traversed by UIO's DPM addition to doorbell */
		262	#define UIO_DPM 8
		263	/* roundup to DPM offset */
		264	#define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
		265	UIO_DPM))
		266	/* offset to nearest value which has lsb nibble matching DPM */
		267	#define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \
		268	(UIO_DPM * 2))
		269	/* add offset to rounded-up cid to get a value which could be used with UIO */
		270	#define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
		271	/* but wait - avoid UIO special case for cid 0 */
		272	#define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \
		273	(UIO_DPM_ALIGN(bp) == UIO_DPM))
		274	/* Properly DPM aligned CID dajusted to cid 0 secal case */
		275	#define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \
		276	(UIO_DPM_CID0_OFFSET(bp)))
		277	/* how many cids were wasted - need this value for cid allocation */
		278	#define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \
		279	BNX2X_1st_NON_L2_ETH_CID(bp))
251	/* iSCSI L2 */	280	/* iSCSI L2 */
252	#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))	281	#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
253	/* FCoE L2 */	282	/* FCoE L2 */
@@ -1542,7 +1571,6 @@ struct bnx2x { · 1288 unmodified lines
1542	*/	1571	*/
1543	bool fcoe_init;	1572	bool fcoe_init;
1544		1573
1545	int pm_cap;
1546	int mrrs;	1574	int mrrs;
1547		1575
1548	struct delayed_work sp_task;	1576	struct delayed_work sp_task;
@@ -1681,10 +1709,11 @@ struct bnx2x { · 132 unmodified lines
1681	* Maximum CID count that might be required by the bnx2x:	1709	* Maximum CID count that might be required by the bnx2x:
1682	* Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI	1710	* Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1683	*/	1711	*/
		1712
1684	#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \	1713	#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1685	+ 2 * CNIC_SUPPORT(bp))	1714	+ CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1686	#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \	1715	#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1687	+ 2 * CNIC_SUPPORT(bp))	1716	+ CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1688	#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\	1717	#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1689	ILT_PAGE_CIDS))	1718	ILT_PAGE_CIDS))
1690		1719

drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c+5−6

 load_error_cnic1:
 	bnx2x_napi_disable_cnic(bp);
 	/* Update the number of queues without the cnic queues */
-	rc = bnx2x_set_real_num_queues(bp, 0);
+	if (bnx2x_set_real_num_queues(bp, 0))
-	if (rc)
 		BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
 load_error_cnic0:
 	BNX2X_ERR("CNIC-related load failed\n");
 	u16 pmcsr;
 	/* If there is no power capability, silently succeed */
-	if (!bp->pm_cap) {
+	if (!bp->pdev->pm_cap) {
 		BNX2X_DEV_INFO("No power capability. Breaking.\n");
 		return 0;
 	}
-	pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
+	pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, &pmcsr);
 	switch (state) {
 	case PCI_D0:
-		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
+		pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
 				      ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
 				       PCI_PM_CTRL_PME_STATUS));
 		if (bp->wol)
 			pmcsr |= PCI_PM_CTRL_PME_ENABLE;
-		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
+		pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
 				      pmcsr);
 		/* No more memory access after this point until

drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c+2−2

@@ -1387,9 +1387,9 @@ static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) · 1386 unmodified lines
1387	u16 pm = 0;	1387	u16 pm = 0;
1388	struct net_device *dev = pci_get_drvdata(bp->pdev);	1388	struct net_device *dev = pci_get_drvdata(bp->pdev);
1389		1389
1390	if (bp->pm_cap)	1390	if (bp->pdev->pm_cap)
1391	rc = pci_read_config_word(bp->pdev,	1391	rc = pci_read_config_word(bp->pdev,
1392	bp->pm_cap + PCI_PM_CTRL, &pm);	1392	bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1393		1393
1394	if ((rc && !netif_running(dev)) \|\|	1394	if ((rc && !netif_running(dev)) \|\|
1395	(!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))	1395	(!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c+99−90

@@ -175,6 +175,7 @@ typedef int (read_sfp_module_eeprom_func_p)(struct bnx2x_phy phy, · 174 unmodified lines
175	#define EDC_MODE_LINEAR 0x0022	175	#define EDC_MODE_LINEAR 0x0022
176	#define EDC_MODE_LIMITING 0x0044	176	#define EDC_MODE_LIMITING 0x0044
177	#define EDC_MODE_PASSIVE_DAC 0x0055	177	#define EDC_MODE_PASSIVE_DAC 0x0055
		178	#define EDC_MODE_ACTIVE_DAC 0x0066
178		179
179	/* ETS defines*/	180	/* ETS defines*/
180	#define DCBX_INVALID_COS (0xFF)	181	#define DCBX_INVALID_COS (0xFF)
@@ -3684,6 +3685,41 @@ static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, · 3503 unmodified lines
3684	bnx2x_update_link_attr(params, vars->link_attr_sync);	3685	bnx2x_update_link_attr(params, vars->link_attr_sync);
3685	}	3686	}
3686		3687
		3688	static void bnx2x_disable_kr2(struct link_params *params,
		3689	struct link_vars *vars,
		3690	struct bnx2x_phy *phy)
		3691	{
		3692	struct bnx2x *bp = params->bp;
		3693	int i;
		3694	static struct bnx2x_reg_set reg_set[] = {
		3695	/* Step 1 - Program the TX/RX alignment markers */
		3696	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
		3697	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
		3698	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
		3699	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
		3700	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
		3701	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
		3702	{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
		3703	{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
		3704	{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
		3705	{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
		3706	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
		3707	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
		3708	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
		3709	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
		3710	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
		3711	};
		3712	DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
		3713
		3714	for (i = 0; i < ARRAY_SIZE(reg_set); i++)
		3715	bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
		3716	reg_set[i].val);
		3717	vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
		3718	bnx2x_update_link_attr(params, vars->link_attr_sync);
		3719
		3720	vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
		3721	}
		3722
3687	static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,	3723	static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3688	struct link_params *params)	3724	struct link_params *params)
3689	{	3725	{
@@ -3715,7 +3751,6 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, · 25 unmodified lines
3715	struct link_params *params,	3751	struct link_params *params,
3716	struct link_vars *vars) {	3752	struct link_vars *vars) {
3717	u16 lane, i, cl72_ctrl, an_adv = 0;	3753	u16 lane, i, cl72_ctrl, an_adv = 0;
3718	u16 ucode_ver;
3719	struct bnx2x *bp = params->bp;	3754	struct bnx2x *bp = params->bp;
3720	static struct bnx2x_reg_set reg_set[] = {	3755	static struct bnx2x_reg_set reg_set[] = {
3721	{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},	3756	{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
@@ -3806,15 +3841,7 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, · 84 unmodified lines
3806		3841
3807	/* Advertise pause */	3842	/* Advertise pause */
3808	bnx2x_ext_phy_set_pause(params, phy, vars);	3843	bnx2x_ext_phy_set_pause(params, phy, vars);
3809	/* Set KR Autoneg Work-Around flag for Warpcore version older than D108	3844	vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3810	*/
3811	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3812	MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver);
3813	if (ucode_ver < 0xd108) {
3814	DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n",
3815	ucode_ver);
3816	vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3817	}
3818	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,	3845	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3819	MDIO_WC_REG_DIGITAL5_MISC7, 0x100);	3846	MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3820		3847
@@ -3838,6 +3865,8 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, · 17 unmodified lines
3838	bnx2x_set_aer_mmd(params, phy);	3865	bnx2x_set_aer_mmd(params, phy);
3839		3866
3840	bnx2x_warpcore_enable_AN_KR2(phy, params, vars);	3867	bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
		3868	} else {
		3869	bnx2x_disable_kr2(params, vars, phy);
3841	}	3870	}
3842		3871
3843	/* Enable Autoneg: only on the main lane */	3872	/* Enable Autoneg: only on the main lane */
@@ -4347,20 +4376,14 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, · 503 unmodified lines
4347	struct bnx2x *bp = params->bp;	4376	struct bnx2x *bp = params->bp;
4348	u32 serdes_net_if;	4377	u32 serdes_net_if;
4349	u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;	4378	u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4350	u16 lane = bnx2x_get_warpcore_lane(phy, params);
4351		4379
4352	vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;	4380	vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4353		4381
4354	if (!vars->turn_to_run_wc_rt)	4382	if (!vars->turn_to_run_wc_rt)
4355	return;	4383	return;
4356		4384
4357	/* Return if there is no link partner */
4358	if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4359	DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4360	return;
4361	}
4362
4363	if (vars->rx_tx_asic_rst) {	4385	if (vars->rx_tx_asic_rst) {
		4386	u16 lane = bnx2x_get_warpcore_lane(phy, params);
4364	serdes_net_if = (REG_RD(bp, params->shmem_base +	4387	serdes_net_if = (REG_RD(bp, params->shmem_base +
4365	offsetof(struct shmem_region, dev_info.	4388	offsetof(struct shmem_region, dev_info.
4366	port_hw_config[params->port].default_cfg)) &	4389	port_hw_config[params->port].default_cfg)) &
@@ -4375,14 +4398,8 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, · 8 unmodified lines
4375	/10G KR/	4398	/10G KR/
4376	lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;	4399	lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4377		4400
4378	DP(NETIF_MSG_LINK,
4379	"gp_status1 0x%x\n", gp_status1);
4380
4381	if (lnkup_kr \|\| lnkup) {	4401	if (lnkup_kr \|\| lnkup) {
4382	vars->rx_tx_asic_rst = 0;	4402	vars->rx_tx_asic_rst = 0;
4383	DP(NETIF_MSG_LINK,
4384	"link up, rx_tx_asic_rst 0x%x\n",
4385	vars->rx_tx_asic_rst);
4386	} else {	4403	} else {
4387	/* Reset the lane to see if link comes up.*/	4404	/* Reset the lane to see if link comes up.*/
4388	bnx2x_warpcore_reset_lane(bp, phy, 1);	4405	bnx2x_warpcore_reset_lane(bp, phy, 1);
@@ -4507,10 +4524,14 @@ static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, · 118 unmodified lines
4507	* enabled transmitter to avoid current leakage in case	4524	* enabled transmitter to avoid current leakage in case
4508	* no module is connected	4525	* no module is connected
4509	*/	4526	*/
4510	if (bnx2x_is_sfp_module_plugged(phy, params))	4527	if ((params->loopback_mode == LOOPBACK_NONE) \|\|
4511	bnx2x_sfp_module_detection(phy, params);	4528	(params->loopback_mode == LOOPBACK_EXT)) {
4512	else	4529	if (bnx2x_is_sfp_module_plugged(phy, params))
4513	bnx2x_sfp_e3_set_transmitter(params, phy, 1);	4530	bnx2x_sfp_module_detection(phy, params);
		4531	else
		4532	bnx2x_sfp_e3_set_transmitter(params,
		4533	phy, 1);
		4534	}
4514		4535
4515	bnx2x_warpcore_config_sfi(phy, params);	4536	bnx2x_warpcore_config_sfi(phy, params);
4516	break;	4537	break;
@@ -5757,6 +5778,11 @@ static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, · 1240 unmodified lines
5757	rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,	5778	rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5758	duplex);	5779	duplex);
5759		5780
		5781	/* In case of KR link down, start up the recovering procedure */
		5782	if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
		5783	(!(phy->flags & FLAGS_WC_DUAL_MODE)))
		5784	vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
		5785
5760	DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",	5786	DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5761	vars->duplex, vars->flow_ctrl, vars->link_status);	5787	vars->duplex, vars->flow_ctrl, vars->link_status);
5762	return rc;	5788	return rc;
@@ -6507,6 +6533,11 @@ static int bnx2x_link_initialize(struct link_params *params, · 744 unmodified lines
6507	params->phy[INT_PHY].config_init(phy, params, vars);	6533	params->phy[INT_PHY].config_init(phy, params, vars);
6508	}	6534	}
6509		6535
		6536	/* Re-read this value in case it was changed inside config_init due to
		6537	* limitations of optic module
		6538	*/
		6539	vars->line_speed = params->phy[INT_PHY].req_line_speed;
		6540
6510	/* Init external phy*/	6541	/* Init external phy*/
6511	if (non_ext_phy) {	6542	if (non_ext_phy) {
6512	if (params->phy[INT_PHY].supported &	6543	if (params->phy[INT_PHY].supported &
@@ -8080,7 +8111,10 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, · 1567 unmodified lines
8080	if (copper_module_type &	8111	if (copper_module_type &
8081	SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {	8112	SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8082	DP(NETIF_MSG_LINK, "Active Copper cable detected\n");	8113	DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8083	check_limiting_mode = 1;	8114	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
		8115	*edc_mode = EDC_MODE_ACTIVE_DAC;
		8116	else
		8117	check_limiting_mode = 1;
8084	} else if (copper_module_type &	8118	} else if (copper_module_type &
8085	SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {	8119	SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8086	DP(NETIF_MSG_LINK,	8120	DP(NETIF_MSG_LINK,
@@ -8555,6 +8589,7 @@ static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, · 468 unmodified lines
8555	mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;	8589	mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8556	break;	8590	break;
8557	case EDC_MODE_PASSIVE_DAC:	8591	case EDC_MODE_PASSIVE_DAC:
		8592	case EDC_MODE_ACTIVE_DAC:
8558	mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;	8593	mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8559	break;	8594	break;
8560	default:	8595	default:
@@ -9730,32 +9765,41 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, · 1169 unmodified lines
9730	MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,	9765	MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9731	an_1000_val);	9766	an_1000_val);
9732		9767
9733	/* set 100 speed advertisement */	9768	/* Set 10/100 speed advertisement */
9734	if ((phy->req_line_speed == SPEED_AUTO_NEG) &&	9769	if (phy->req_line_speed == SPEED_AUTO_NEG) {
9735	(phy->speed_cap_mask &	9770	if (phy->speed_cap_mask &
9736	(PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL \|	9771	PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9737	PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {	9772	/* Enable autoneg and restart autoneg for legacy speeds
9738	an_10_100_val \|= (1<<7);	9773	*/
9739	/* Enable autoneg and restart autoneg for legacy speeds */	9774	autoneg_val \|= (1<<9 \| 1<<12);
9740	autoneg_val \|= (1<<9 \| 1<<12);
9741
9742	if (phy->req_duplex == DUPLEX_FULL)
9743	an_10_100_val \|= (1<<8);	9775	an_10_100_val \|= (1<<8);
9744	DP(NETIF_MSG_LINK, "Advertising 100M\n");	9776	DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9745	}	9777	}
9746	/* set 10 speed advertisement */	9778
9747	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&	9779	if (phy->speed_cap_mask &
9748	(phy->speed_cap_mask &	9780	PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9749	(PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL \|	9781	/* Enable autoneg and restart autoneg for legacy speeds
9750	PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&	9782	*/
9751	(phy->supported &	9783	autoneg_val \|= (1<<9 \| 1<<12);
9752	(SUPPORTED_10baseT_Half \|	9784	an_10_100_val \|= (1<<7);
9753	SUPPORTED_10baseT_Full)))) {	9785	DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9754	an_10_100_val \|= (1<<5);	9786	}
9755	autoneg_val \|= (1<<9 \| 1<<12);	9787
9756	if (phy->req_duplex == DUPLEX_FULL)	9788	if ((phy->speed_cap_mask &
		9789	PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
		9790	(phy->supported & SUPPORTED_10baseT_Full)) {
9757	an_10_100_val \|= (1<<6);	9791	an_10_100_val \|= (1<<6);
9758	DP(NETIF_MSG_LINK, "Advertising 10M\n");	9792	autoneg_val \|= (1<<9 \| 1<<12);
		9793	DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
		9794	}
		9795
		9796	if ((phy->speed_cap_mask &
		9797	PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
		9798	(phy->supported & SUPPORTED_10baseT_Half)) {
		9799	an_10_100_val \|= (1<<5);
		9800	autoneg_val \|= (1<<9 \| 1<<12);
		9801	DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
		9802	}
9759	}	9803	}
9760		9804
9761	/* Only 10/100 are allowed to work in FORCE mode */	9805	/* Only 10/100 are allowed to work in FORCE mode */
@@ -13432,43 +13476,6 @@ static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, · 3670 unmodified lines
13432	}	13476	}
13433	}	13477	}
13434	}	13478	}
13435	static void bnx2x_disable_kr2(struct link_params *params,
13436	struct link_vars *vars,
13437	struct bnx2x_phy *phy)
13438	{
13439	struct bnx2x *bp = params->bp;
13440	int i;
13441	static struct bnx2x_reg_set reg_set[] = {
13442	/* Step 1 - Program the TX/RX alignment markers */
13443	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
13444	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
13445	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
13446	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
13447	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
13448	{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
13449	{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
13450	{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
13451	{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
13452	{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
13453	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
13454	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
13455	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
13456	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
13457	{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
13458	};
13459	DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
13460
13461	for (i = 0; i < ARRAY_SIZE(reg_set); i++)
13462	bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
13463	reg_set[i].val);
13464	vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
13465	bnx2x_update_link_attr(params, vars->link_attr_sync);
13466
13467	vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
13468	/* Restart AN on leading lane */
13469	bnx2x_warpcore_restart_AN_KR(phy, params);
13470	}
13471
13472	static void bnx2x_kr2_recovery(struct link_params *params,	13479	static void bnx2x_kr2_recovery(struct link_params *params,
13473	struct link_vars *vars,	13480	struct link_vars *vars,
13474	struct bnx2x_phy *phy)	13481	struct bnx2x_phy *phy)
@@ -13546,6 +13553,8 @@ static void bnx2x_check_kr2_wa(struct link_params *params, · 71 unmodified lines
13546	/* Disable KR2 on both lanes */	13553	/* Disable KR2 on both lanes */
13547	DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);	13554	DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13548	bnx2x_disable_kr2(params, vars, phy);	13555	bnx2x_disable_kr2(params, vars, phy);
		13556	/* Restart AN on leading lane */
		13557	bnx2x_warpcore_restart_AN_KR(phy, params);
13549	return;	13558	return;
13550	}	13559	}
13551	}	13560	}

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c+24−14

 	attn.sig[3] = REG_RD(bp,
 		MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
 			     port*4);
+	/* Since MCP attentions can't be disabled inside the block, we need to
+	 * read AEU registers to see whether they're currently disabled
+	 */
+	attn.sig[3] &= ((REG_RD(bp,
+				!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
+				      : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
+			 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
+			~MISC_AEU_ENABLE_MCP_PRTY_BITS);
 	if (!CHIP_IS_E1x(bp))
 		attn.sig[4] = REG_RD(bp,
 	if (IS_PF(bp) &&
 	    !BP_NOMCP(bp)) {
 		int mb_idx = BP_FW_MB_IDX(bp);
-		u32 drv_pulse;
+		u16 drv_pulse;
-		u32 mcp_pulse;
+		u16 mcp_pulse;
 		++bp->fw_drv_pulse_wr_seq;
 		bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
-		/* TBD - add SYSTEM_TIME */
 		drv_pulse = bp->fw_drv_pulse_wr_seq;
 		bnx2x_drv_pulse(bp);
 		mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
 			     MCP_PULSE_SEQ_MASK);
 		/* The delta between driver pulse and mcp response
-		 * should be 1 (before mcp response) or 0 (after mcp response)
+		 * should not get too big. If the MFW is more than 5 pulses
+		 * behind, we should worry about it enough to generate an error
+		 * log.
 		 */
-		if ((drv_pulse != mcp_pulse) &&
+		if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
-		    (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
+			BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
-			/* someone lost a heartbeat... */
-			BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
 				  drv_pulse, mcp_pulse);
-		}
 	}
 	if (bp->state == BNX2X_STATE_OPEN)
 	else if (bp->wol) {
 		u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 		u8 *mac_addr = bp->dev->dev_addr;
+		struct pci_dev *pdev = bp->pdev;
 		u32 val;
 		u16 pmc;
 		EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
 		/* Enable the PME and clear the status */
-		pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
+		pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
 		pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
-		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
+		pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
 		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
 		break;
 	}
-	pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
+	pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
 	bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
 	BNX2X_DEV_INFO("%sWoL capable\n",
 	}
 	if (IS_PF(bp)) {
-		bp->pm_cap = pdev->pm_cap;
+		if (!pdev->pm_cap) {
-		if (bp->pm_cap == 0) {
 			dev_err(&bp->pdev->dev,
 				"Cannot find power management capability, aborting\n");
 			rc = -EIO;
 	cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
 	cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
+	DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
+	   BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
+	   cp->iscsi_l2_cid);
 	if (NO_ISCSI_OOO(bp))
 		cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
 }

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c+4−1

 		fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
 		if (fid & IGU_FID_ENCODE_IS_PF)
 			current_pf = fid & IGU_FID_PF_NUM_MASK;
-		else if (current_pf == BP_ABS_FUNC(bp))
+		else if (current_pf == BP_FUNC(bp))
 			bnx2x_vf_set_igu_info(bp, sb_id,
 					      (fid & IGU_FID_VF_NUM_MASK));
 		DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
 		/* set local queue arrays */
 		vf->vfqs = &bp->vfdb->vfqs[qcount];
 		qcount += vf_sb_count(vf);
+		bnx2x_iov_static_resc(bp, vf);
 	}
 	/* prepare msix vectors in VF configuration space */
 		bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx));
 		REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
 		       num_vf_queues);
+		DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n",
+		   vf_idx, num_vf_queues);
 	}
 	bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));

drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c+24−26

@@ -1765,28 +1765,28 @@ static void bnx2x_vf_mbx_request(struct bnx2x bp, struct bnx2x_virtf vf, · 1764 unmodified lines
1765	switch (mbx->first_tlv.tl.type) {	1765	switch (mbx->first_tlv.tl.type) {
1766	case CHANNEL_TLV_ACQUIRE:	1766	case CHANNEL_TLV_ACQUIRE:
1767	bnx2x_vf_mbx_acquire(bp, vf, mbx);	1767	bnx2x_vf_mbx_acquire(bp, vf, mbx);
1768	break;	1768	return;
1769	case CHANNEL_TLV_INIT:	1769	case CHANNEL_TLV_INIT:
1770	bnx2x_vf_mbx_init_vf(bp, vf, mbx);	1770	bnx2x_vf_mbx_init_vf(bp, vf, mbx);
1771	break;	1771	return;
1772	case CHANNEL_TLV_SETUP_Q:	1772	case CHANNEL_TLV_SETUP_Q:
1773	bnx2x_vf_mbx_setup_q(bp, vf, mbx);	1773	bnx2x_vf_mbx_setup_q(bp, vf, mbx);
1774	break;	1774	return;
1775	case CHANNEL_TLV_SET_Q_FILTERS:	1775	case CHANNEL_TLV_SET_Q_FILTERS:
1776	bnx2x_vf_mbx_set_q_filters(bp, vf, mbx);	1776	bnx2x_vf_mbx_set_q_filters(bp, vf, mbx);
1777	break;	1777	return;
1778	case CHANNEL_TLV_TEARDOWN_Q:	1778	case CHANNEL_TLV_TEARDOWN_Q:
1779	bnx2x_vf_mbx_teardown_q(bp, vf, mbx);	1779	bnx2x_vf_mbx_teardown_q(bp, vf, mbx);
1780	break;	1780	return;
1781	case CHANNEL_TLV_CLOSE:	1781	case CHANNEL_TLV_CLOSE:
1782	bnx2x_vf_mbx_close_vf(bp, vf, mbx);	1782	bnx2x_vf_mbx_close_vf(bp, vf, mbx);
1783	break;	1783	return;
1784	case CHANNEL_TLV_RELEASE:	1784	case CHANNEL_TLV_RELEASE:
1785	bnx2x_vf_mbx_release_vf(bp, vf, mbx);	1785	bnx2x_vf_mbx_release_vf(bp, vf, mbx);
1786	break;	1786	return;
1787	case CHANNEL_TLV_UPDATE_RSS:	1787	case CHANNEL_TLV_UPDATE_RSS:
1788	bnx2x_vf_mbx_update_rss(bp, vf, mbx);	1788	bnx2x_vf_mbx_update_rss(bp, vf, mbx);
1789	break;	1789	return;
1790	}	1790	}
1791		1791
1792	} else {	1792	} else {
@@ -1802,26 +1802,24 @@ static void bnx2x_vf_mbx_request(struct bnx2x bp, struct bnx2x_virtf vf, · 9 unmodified lines
1802	for (i = 0; i < 20; i++)	1802	for (i = 0; i < 20; i++)
1803	DP_CONT(BNX2X_MSG_IOV, "%x ",	1803	DP_CONT(BNX2X_MSG_IOV, "%x ",
1804	mbx->msg->req.tlv_buf_size.tlv_buffer[i]);	1804	mbx->msg->req.tlv_buf_size.tlv_buffer[i]);
		1805	}
1805		1806
1806	/* test whether we can respond to the VF (do we have an address	1807	/* can we respond to VF (do we have an address for it?) */
1807	* for it?)	1808	if (vf->state == VF_ACQUIRED \|\| vf->state == VF_ENABLED) {
1808	*/	1809	/* mbx_resp uses the op_rc of the VF */
1809	if (vf->state == VF_ACQUIRED \|\| vf->state == VF_ENABLED) {	1810	vf->op_rc = PFVF_STATUS_NOT_SUPPORTED;
1810	/* mbx_resp uses the op_rc of the VF */
1811	vf->op_rc = PFVF_STATUS_NOT_SUPPORTED;
1812		1811
1813	/* notify the VF that we do not support this request */	1812	/* notify the VF that we do not support this request */
1814	bnx2x_vf_mbx_resp(bp, vf);	1813	bnx2x_vf_mbx_resp(bp, vf);
1815	} else {	1814	} else {
1816	/* can't send a response since this VF is unknown to us	1815	/* can't send a response since this VF is unknown to us
1817	* just ack the FW to release the mailbox and unlock	1816	* just ack the FW to release the mailbox and unlock
1818	* the channel.	1817	* the channel.
1819	*/	1818	*/
1820	storm_memset_vf_mbx_ack(bp, vf->abs_vfid);	1819	storm_memset_vf_mbx_ack(bp, vf->abs_vfid);
1821	mmiowb();	1820	/* Firmware ack should be written before unlocking channel */
1822	bnx2x_unlock_vf_pf_channel(bp, vf,	1821	mmiowb();
1823	mbx->first_tlv.tl.type);	1822	bnx2x_unlock_vf_pf_channel(bp, vf, mbx->first_tlv.tl.type);
1824	}
1825	}	1823	}
1826	}	1824	}
1827		1825

drivers/net/ethernet/broadcom/cnic.c+4−2

 {
 	struct cnic_dev *dev = (struct cnic_dev *) data;
 	struct cnic_local *cp = dev->cnic_priv;
+	struct bnx2x *bp = netdev_priv(dev->netdev);
 	u32 status_idx, new_status_idx;
 	if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
 		CNIC_WR16(dev, cp->kcq1.io_addr,
 			  cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
-		if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE) {
+		if (!CNIC_SUPPORTS_FCOE(bp)) {
 			cp->arm_int(dev, status_idx);
 			break;
 		}
 				"iSCSI CLIENT_SETUP did not complete\n");
 		cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
 		cnic_ring_ctl(dev, cid, cli, 1);
-		*cid_ptr = cid;
+		*cid_ptr = cid >> 4;
+		*(cid_ptr + 1) = cid * bp->db_size;
 	}
 }

drivers/net/ethernet/broadcom/tg3.c+3−3

 {
 	switch (tg3_asic_rev(tp)) {
 	case ASIC_REV_5719:
+	case ASIC_REV_5720:
 		if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
 		    !tp->pci_fn)
 			return true;
 			 * So explicitly force the chip into D0 here.
 			 */
 			pci_read_config_dword(tp->pdev,
-					      tp->pm_cap + PCI_PM_CTRL,
+					      tp->pdev->pm_cap + PCI_PM_CTRL,
 					      &pm_reg);
 			pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
 			pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
 			pci_write_config_dword(tp->pdev,
-					       tp->pm_cap + PCI_PM_CTRL,
+					       tp->pdev->pm_cap + PCI_PM_CTRL,
 					       pm_reg);
 			/* Also, force SERR#/PERR# in PCI command. */
 	tp = netdev_priv(dev);
 	tp->pdev = pdev;
 	tp->dev = dev;
-	tp->pm_cap = pdev->pm_cap;
 	tp->rx_mode = TG3_DEF_RX_MODE;
 	tp->tx_mode = TG3_DEF_TX_MODE;
 	tp->irq_sync = 1;

drivers/net/ethernet/broadcom/tg3.h+0−1

@@ -3234,7 +3234,6 @@ struct tg3 { · 3233 unmodified lines
3234	u8 pci_lat_timer;	3234	u8 pci_lat_timer;
3235		3235
3236	int pci_fn;	3236	int pci_fn;
3237	int pm_cap;
3238	int msi_cap;	3237	int msi_cap;
3239	int pcix_cap;	3238	int pcix_cap;
3240	int pcie_readrq;	3239	int pcie_readrq;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c+3−1

@@ -6149,8 +6149,10 @@ static int __init cxgb4_init_module(void) · 6148 unmodified lines
6149	pr_warn("could not create debugfs entry, continuing\n");	6149	pr_warn("could not create debugfs entry, continuing\n");
6150		6150
6151	ret = pci_register_driver(&cxgb4_driver);	6151	ret = pci_register_driver(&cxgb4_driver);
6152	if (ret < 0)	6152	if (ret < 0) {
6153	debugfs_remove(cxgb4_debugfs_root);	6153	debugfs_remove(cxgb4_debugfs_root);
		6154	destroy_workqueue(workq);
		6155	}
6154		6156
6155	register_inet6addr_notifier(&cxgb4_inet6addr_notifier);	6157	register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6156		6158

drivers/net/ethernet/dec/tulip/de4x5.c+1−1

@@ -1321,7 +1321,7 @@ de4x5_open(struct net_device *dev) · 1320 unmodified lines
1321	if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,	1321	if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1322	lp->adapter_name, dev)) {	1322	lp->adapter_name, dev)) {
1323	printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);	1323	printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1324	if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED \| IRQF_SHARED,	1324	if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1325	lp->adapter_name, dev)) {	1325	lp->adapter_name, dev)) {
1326	printk("\n Cannot get IRQ- reconfigure your hardware.\n");	1326	printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1327	disable_ast(dev);	1327	disable_ast(dev);

drivers/net/ethernet/emulex/benet/be.h+2−0

 #define BE_MIN_MTU		256
 #define BE_NUM_VLANS_SUPPORTED	64
+#define BE_UMC_NUM_VLANS_SUPPORTED	15
 #define BE_MAX_EQD		96u
 #define	BE_MAX_TX_FRAG_COUNT	30
 #define BE_FLAGS_LINK_STATUS_INIT		1
 #define BE_FLAGS_WORKER_SCHEDULED		(1 << 3)
+#define BE_FLAGS_VLAN_PROMISC			(1 << 4)
 #define BE_FLAGS_NAPI_ENABLED			(1 << 9)
 #define BE_UC_PMAC_COUNT		30
 #define BE_VF_UC_PMAC_COUNT		2

drivers/net/ethernet/emulex/benet/be_cmds.c+9−0

 			dev_err(&adapter->pdev->dev,
 				"opcode %d-%d failed:status %d-%d\n",
 				opcode, subsystem, compl_status, extd_status);
+			if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
+				return extd_status;
 		}
 	}
 done:
 	} else if (flags & IFF_ALLMULTI) {
 		req->if_flags_mask = req->if_flags =
 				cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
+	} else if (flags & BE_FLAGS_VLAN_PROMISC) {
+		req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
+		if (value == ON)
+			req->if_flags =
+				cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
 	} else {
 		struct netdev_hw_addr *ha;
 		int i = 0;

drivers/net/ethernet/emulex/benet/be_cmds.h+3−1

 	MCC_STATUS_NOT_SUPPORTED = 66
 };
+#define MCC_ADDL_STS_INSUFFICIENT_RESOURCES	0x16
 #define CQE_STATUS_COMPL_MASK		0xFFFF
 #define CQE_STATUS_COMPL_SHIFT		0	/* bits 0 - 15 */
 #define CQE_STATUS_EXTD_MASK		0xFFFF
 	u8 acpi_params;
 	u8 wol_param;
 	u16 rsvd7;
-	u32 rsvd8[3];
+	u32 rsvd8[7];
 } __packed;
 struct be_cmd_req_get_func_config {

drivers/net/ethernet/emulex/benet/be_main.c+47−31

@@ -855,11 +855,11 @@ static struct sk_buff be_xmit_workarounds(struct be_adapter adapter, · 854 unmodified lines
855	unsigned int eth_hdr_len;	855	unsigned int eth_hdr_len;
856	struct iphdr *ip;	856	struct iphdr *ip;
857		857
858	/* Lancer ASIC has a bug wherein packets that are 32 bytes or less	858	/* Lancer, SH-R ASICs have a bug wherein Packets that are 32 bytes or less
859	* may cause a transmit stall on that port. So the work-around is to	859	* may cause a transmit stall on that port. So the work-around is to
860	* pad such packets to a 36-byte length.	860	* pad short packets (<= 32 bytes) to a 36-byte length.
861	*/	861	*/
862	if (unlikely(lancer_chip(adapter) && skb->len <= 32)) {	862	if (unlikely(!BEx_chip(adapter) && skb->len <= 32)) {
863	if (skb_padto(skb, 36))	863	if (skb_padto(skb, 36))
864	goto tx_drop;	864	goto tx_drop;
865	skb->len = 36;	865	skb->len = 36;
@@ -1013,18 +1013,40 @@ static int be_vid_config(struct be_adapter *adapter) · 147 unmodified lines
1013	status = be_cmd_vlan_config(adapter, adapter->if_handle,	1013	status = be_cmd_vlan_config(adapter, adapter->if_handle,
1014	vids, num, 1, 0);	1014	vids, num, 1, 0);
1015		1015
1016	/* Set to VLAN promisc mode as setting VLAN filter failed */
1017	if (status) {	1016	if (status) {
1018	dev_info(&adapter->pdev->dev, "Exhausted VLAN HW filters.\n");	1017	/* Set to VLAN promisc mode as setting VLAN filter failed */
1019	dev_info(&adapter->pdev->dev, "Disabling HW VLAN filtering.\n");	1018	if (status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
1020	goto set_vlan_promisc;	1019	goto set_vlan_promisc;
		1020	dev_err(&adapter->pdev->dev,
		1021	"Setting HW VLAN filtering failed.\n");
		1022	} else {
		1023	if (adapter->flags & BE_FLAGS_VLAN_PROMISC) {
		1024	/* hw VLAN filtering re-enabled. */
		1025	status = be_cmd_rx_filter(adapter,
		1026	BE_FLAGS_VLAN_PROMISC, OFF);
		1027	if (!status) {
		1028	dev_info(&adapter->pdev->dev,
		1029	"Disabling VLAN Promiscuous mode.\n");
		1030	adapter->flags &= ~BE_FLAGS_VLAN_PROMISC;
		1031	dev_info(&adapter->pdev->dev,
		1032	"Re-Enabling HW VLAN filtering\n");
		1033	}
		1034	}
1021	}	1035	}
1022		1036
1023	return status;	1037	return status;
1024		1038
1025	set_vlan_promisc:	1039	set_vlan_promisc:
1026	status = be_cmd_vlan_config(adapter, adapter->if_handle,	1040	dev_warn(&adapter->pdev->dev, "Exhausted VLAN HW filters.\n");
1027	NULL, 0, 1, 1);	1041
		1042	status = be_cmd_rx_filter(adapter, BE_FLAGS_VLAN_PROMISC, ON);
		1043	if (!status) {
		1044	dev_info(&adapter->pdev->dev, "Enable VLAN Promiscuous mode\n");
		1045	dev_info(&adapter->pdev->dev, "Disabling HW VLAN filtering\n");
		1046	adapter->flags \|= BE_FLAGS_VLAN_PROMISC;
		1047	} else
		1048	dev_err(&adapter->pdev->dev,
		1049	"Failed to enable VLAN Promiscuous mode.\n");
1028	return status;	1050	return status;
1029	}	1051	}
1030		1052
@@ -1033,10 +1055,6 @@ static int be_vlan_add_vid(struct net_device *netdev, __be16 proto, u16 vid) · 2 unmodified lines
1033	struct be_adapter *adapter = netdev_priv(netdev);	1055	struct be_adapter *adapter = netdev_priv(netdev);
1034	int status = 0;	1056	int status = 0;
1035		1057
1036	if (!lancer_chip(adapter) && !be_physfn(adapter)) {
1037	status = -EINVAL;
1038	goto ret;
1039	}
1040		1058
1041	/* Packets with VID 0 are always received by Lancer by default */	1059	/* Packets with VID 0 are always received by Lancer by default */
1042	if (lancer_chip(adapter) && vid == 0)	1060	if (lancer_chip(adapter) && vid == 0)
@@ -1059,11 +1077,6 @@ static int be_vlan_rem_vid(struct net_device *netdev, __be16 proto, u16 vid) · 16 unmodified lines
1059	struct be_adapter *adapter = netdev_priv(netdev);	1077	struct be_adapter *adapter = netdev_priv(netdev);
1060	int status = 0;	1078	int status = 0;
1061		1079
1062	if (!lancer_chip(adapter) && !be_physfn(adapter)) {
1063	status = -EINVAL;
1064	goto ret;
1065	}
1066
1067	/* Packets with VID 0 are always received by Lancer by default */	1080	/* Packets with VID 0 are always received by Lancer by default */
1068	if (lancer_chip(adapter) && vid == 0)	1081	if (lancer_chip(adapter) && vid == 0)
1069	goto ret;	1082	goto ret;
@@ -1188,8 +1201,8 @@ static int be_get_vf_config(struct net_device *netdev, int vf, · 118 unmodified lines
1188		1201
1189	vi->vf = vf;	1202	vi->vf = vf;
1190	vi->tx_rate = vf_cfg->tx_rate;	1203	vi->tx_rate = vf_cfg->tx_rate;
1191	vi->vlan = vf_cfg->vlan_tag;	1204	vi->vlan = vf_cfg->vlan_tag & VLAN_VID_MASK;
1192	vi->qos = 0;	1205	vi->qos = vf_cfg->vlan_tag >> VLAN_PRIO_SHIFT;
1193	memcpy(&vi->mac, vf_cfg->mac_addr, ETH_ALEN);	1206	memcpy(&vi->mac, vf_cfg->mac_addr, ETH_ALEN);
1194		1207
1195	return 0;	1208	return 0;
@@ -1199,28 +1212,29 @@ static int be_set_vf_vlan(struct net_device *netdev, · 3 unmodified lines
1199	int vf, u16 vlan, u8 qos)	1212	int vf, u16 vlan, u8 qos)
1200	{	1213	{
1201	struct be_adapter *adapter = netdev_priv(netdev);	1214	struct be_adapter *adapter = netdev_priv(netdev);
		1215	struct be_vf_cfg *vf_cfg = &adapter->vf_cfg[vf];
1202	int status = 0;	1216	int status = 0;
1203		1217
1204	if (!sriov_enabled(adapter))	1218	if (!sriov_enabled(adapter))
1205	return -EPERM;	1219	return -EPERM;
1206		1220
1207	if (vf >= adapter->num_vfs \|\| vlan > 4095)	1221	if (vf >= adapter->num_vfs \|\| vlan > 4095 \|\| qos > 7)
1208	return -EINVAL;	1222	return -EINVAL;
1209		1223
1210	if (vlan) {	1224	if (vlan \|\| qos) {
1211	if (adapter->vf_cfg[vf].vlan_tag != vlan) {	1225	vlan \|= qos << VLAN_PRIO_SHIFT;
		1226	if (vf_cfg->vlan_tag != vlan) {
1212	/* If this is new value, program it. Else skip. */	1227	/* If this is new value, program it. Else skip. */
1213	adapter->vf_cfg[vf].vlan_tag = vlan;	1228	vf_cfg->vlan_tag = vlan;
1214		1229	status = be_cmd_set_hsw_config(adapter, vlan, vf + 1,
1215	status = be_cmd_set_hsw_config(adapter, vlan,	1230	vf_cfg->if_handle, 0);
1216	vf + 1, adapter->vf_cfg[vf].if_handle, 0);
1217	}	1231	}
1218	} else {	1232	} else {
1219	/* Reset Transparent Vlan Tagging. */	1233	/* Reset Transparent Vlan Tagging. */
1220	adapter->vf_cfg[vf].vlan_tag = 0;	1234	vf_cfg->vlan_tag = 0;
1221	vlan = adapter->vf_cfg[vf].def_vid;	1235	vlan = vf_cfg->def_vid;
1222	status = be_cmd_set_hsw_config(adapter, vlan, vf + 1,	1236	status = be_cmd_set_hsw_config(adapter, vlan, vf + 1,
1223	adapter->vf_cfg[vf].if_handle, 0);	1237	vf_cfg->if_handle, 0);
1224	}	1238	}
1225		1239
1226		1240
@@ -2802,7 +2816,7 @@ static int be_vfs_if_create(struct be_adapter *adapter) · 1575 unmodified lines
2802	struct be_resources res = {0};	2816	struct be_resources res = {0};
2803	struct be_vf_cfg *vf_cfg;	2817	struct be_vf_cfg *vf_cfg;
2804	u32 cap_flags, en_flags, vf;	2818	u32 cap_flags, en_flags, vf;
2805	int status;	2819	int status = 0;
2806		2820
2807	cap_flags = BE_IF_FLAGS_UNTAGGED \| BE_IF_FLAGS_BROADCAST \|	2821	cap_flags = BE_IF_FLAGS_UNTAGGED \| BE_IF_FLAGS_BROADCAST \|
2808	BE_IF_FLAGS_MULTICAST;	2822	BE_IF_FLAGS_MULTICAST;
@@ -2963,6 +2977,8 @@ static void BEx_get_resources(struct be_adapter *adapter, · 154 unmodified lines
2963		2977
2964	if (adapter->function_mode & FLEX10_MODE)	2978	if (adapter->function_mode & FLEX10_MODE)
2965	res->max_vlans = BE_NUM_VLANS_SUPPORTED/8;	2979	res->max_vlans = BE_NUM_VLANS_SUPPORTED/8;
		2980	else if (adapter->function_mode & UMC_ENABLED)
		2981	res->max_vlans = BE_UMC_NUM_VLANS_SUPPORTED;
2966	else	2982	else
2967	res->max_vlans = BE_NUM_VLANS_SUPPORTED;	2983	res->max_vlans = BE_NUM_VLANS_SUPPORTED;
2968	res->max_mcast_mac = BE_MAX_MC;	2984	res->max_mcast_mac = BE_MAX_MC;

drivers/net/ethernet/freescale/fec_main.c+1−1

@@ -2199,7 +2199,7 @@ fec_probe(struct platform_device *pdev) · 2198 unmodified lines
2199	goto failed_irq;	2199	goto failed_irq;
2200	}	2200	}
2201	ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,	2201	ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2202	IRQF_DISABLED, pdev->name, ndev);	2202	0, pdev->name, ndev);
2203	if (ret)	2203	if (ret)
2204	goto failed_irq;	2204	goto failed_irq;
2205	}	2205	}

drivers/net/ethernet/freescale/gianfar_ptp.c+3−1

@@ -452,7 +452,9 @@ static int gianfar_ptp_probe(struct platform_device *dev) · 451 unmodified lines
452	err = -ENODEV;	452	err = -ENODEV;
453		453
454	etsects->caps = ptp_gianfar_caps;	454	etsects->caps = ptp_gianfar_caps;
455	etsects->cksel = DEFAULT_CKSEL;	455
		456	if (get_of_u32(node, "fsl,cksel", &etsects->cksel))
		457	etsects->cksel = DEFAULT_CKSEL;
456		458
457	if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) \|\|	459	if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) \|\|
458	get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) \|\|	460	get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) \|\|

drivers/net/ethernet/hp/hp100.c+1−1

@@ -1097,7 +1097,7 @@ static int hp100_open(struct net_device *dev) · 1096 unmodified lines
1097	/* New: if bus is PCI or EISA, interrupts might be shared interrupts */	1097	/* New: if bus is PCI or EISA, interrupts might be shared interrupts */
1098	if (request_irq(dev->irq, hp100_interrupt,	1098	if (request_irq(dev->irq, hp100_interrupt,
1099	lp->bus == HP100_BUS_PCI \|\| lp->bus ==	1099	lp->bus == HP100_BUS_PCI \|\| lp->bus ==
1100	HP100_BUS_EISA ? IRQF_SHARED : IRQF_DISABLED,	1100	HP100_BUS_EISA ? IRQF_SHARED : 0,
1101	"hp100", dev)) {	1101	"hp100", dev)) {
1102	printk("hp100: %s: unable to get IRQ %d\n", dev->name, dev->irq);	1102	printk("hp100: %s: unable to get IRQ %d\n", dev->name, dev->irq);
1103	return -EAGAIN;	1103	return -EAGAIN;

drivers/net/ethernet/ibm/ehea/ehea_main.c+16−5

 static int ehea_remove(struct platform_device *dev);
+static struct of_device_id ehea_module_device_table[] = {
+	{
+		.name = "lhea",
+		.compatible = "IBM,lhea",
+	},
+	{
+		.type = "network",
+		.compatible = "IBM,lhea-ethernet",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, ehea_module_device_table);
 static struct of_device_id ehea_device_table[] = {
 	{
 		.name = "lhea",
 	},
 	{},
 };
-MODULE_DEVICE_TABLE(of, ehea_device_table);
 static struct platform_driver ehea_driver = {
 	.driver = {
 	ret = ibmebus_request_irq(port->qp_eq->attr.ist1,
 				  ehea_qp_aff_irq_handler,
-				  IRQF_DISABLED, port->int_aff_name, port);
+				  0, port->int_aff_name, port);
 	if (ret) {
 		netdev_err(dev, "failed registering irq for qp_aff_irq_handler:ist=%X\n",
 			   port->qp_eq->attr.ist1);
 			 "%s-queue%d", dev->name, i);
 		ret = ibmebus_request_irq(pr->eq->attr.ist1,
 					  ehea_recv_irq_handler,
-					  IRQF_DISABLED, pr->int_send_name,
+					  0, pr->int_send_name, pr);
-					  pr);
 		if (ret) {
 			netdev_err(dev, "failed registering irq for ehea_queue port_res_nr:%d, ist=%X\n",
 				   i, pr->eq->attr.ist1);
 	}
 	ret = ibmebus_request_irq(adapter->neq->attr.ist1,
-				  ehea_interrupt_neq, IRQF_DISABLED,
+				  ehea_interrupt_neq, 0,
 				  "ehea_neq", adapter);
 	if (ret) {
 		dev_err(&dev->dev, "requesting NEQ IRQ failed\n");

drivers/net/ethernet/intel/e1000e/ethtool.c+8−0

@@ -922,6 +922,14 @@ static int e1000_reg_test(struct e1000_adapter adapter, u64 data) · 921 unmodified lines
922	else	922	else
923	mask &= ~(1 << 30);	923	mask &= ~(1 << 30);
924	}	924	}
		925	if (mac->type == e1000_pch2lan) {
		926	/* SHRAH[0,1,2] different than previous */
		927	if (i == 7)
		928	mask &= 0xFFF4FFFF;
		929	/* SHRAH[3] different than SHRAH[0,1,2] */
		930	if (i == 10)
		931	mask \|= (1 << 30);
		932	}
925		933
926	REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1), mask,	934	REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1), mask,
927	0xFFFFFFFF);	935	0xFFFFFFFF);

drivers/net/ethernet/intel/e1000e/ich8lan.c+8−5

 		return;
 	}
-	if (index < hw->mac.rar_entry_count) {
+	/* RAR[1-6] are owned by manageability.  Skip those and program the
+	 * next address into the SHRA register array.
+	 */
+	if (index < (u32)(hw->mac.rar_entry_count - 6)) {
 		s32 ret_val;
 		ret_val = e1000_acquire_swflag_ich8lan(hw);
 	if (ret_val)
 		goto release;
-	/* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
+	/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
-	for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
+	for (i = 0; i < (hw->mac.rar_entry_count); i++) {
 		mac_reg = er32(RAL(i));
 		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
 					   (u16)(mac_reg & 0xFFFF));
 		return ret_val;
 	if (enable) {
-		/* Write Rx addresses (rar_entry_count for RAL/H, +4 for
+		/* Write Rx addresses (rar_entry_count for RAL/H, and
 		 * SHRAL/H) and initial CRC values to the MAC
 		 */
-		for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
+		for (i = 0; i < hw->mac.rar_entry_count; i++) {
 			u8 mac_addr[ETH_ALEN] = { 0 };
 			u32 addr_high, addr_low;

drivers/net/ethernet/intel/e1000e/ich8lan.h+1−1

@@ -98,7 +98,7 @@ · 97 unmodified lines
98	#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL	98	#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
99		99
100	#define E1000_ICH_RAR_ENTRIES 7	100	#define E1000_ICH_RAR_ENTRIES 7
101	#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */	101	#define E1000_PCH2_RAR_ENTRIES 11 /* RAR[0-6], SHRA[0-3] */
102	#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */	102	#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
103		103
104	#define PHY_PAGE_SHIFT 5	104	#define PHY_PAGE_SHIFT 5

drivers/net/ethernet/intel/e1000e/netdev.c+1−1

@@ -4868,7 +4868,7 @@ static void e1000_watchdog_task(struct work_struct *work) · 4867 unmodified lines
4868	*/	4868	*/
4869	if ((hw->phy.type == e1000_phy_igp_3 \|\|	4869	if ((hw->phy.type == e1000_phy_igp_3 \|\|
4870	hw->phy.type == e1000_phy_bm) &&	4870	hw->phy.type == e1000_phy_bm) &&
4871	(hw->mac.autoneg == true) &&	4871	hw->mac.autoneg &&
4872	(adapter->link_speed == SPEED_10 \|\|	4872	(adapter->link_speed == SPEED_10 \|\|
4873	adapter->link_speed == SPEED_100) &&	4873	adapter->link_speed == SPEED_100) &&
4874	(adapter->link_duplex == HALF_DUPLEX)) {	4874	(adapter->link_duplex == HALF_DUPLEX)) {

drivers/net/ethernet/intel/i40e/i40e_adminq.c+3−4

 	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
 	if (cmd_details) {
-		memcpy(details, cmd_details,
+		*details = *cmd_details;
-		       sizeof(struct i40e_asq_cmd_details));
 		/* If the cmd_details are defined copy the cookie.  The
 		 * cpu_to_le32 is not needed here because the data is ignored
 	desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
 	/* if the desc is available copy the temp desc to the right place */
-	memcpy(desc_on_ring, desc, sizeof(struct i40e_aq_desc));
+	*desc_on_ring = *desc;
 	/* if buff is not NULL assume indirect command */
 	if (buff != NULL) {
 	/* if ready, copy the desc back to temp */
 	if (i40e_asq_done(hw)) {
-		memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc));
+		*desc = *desc_on_ring;
 		if (buff != NULL)
 			memcpy(buff, dma_buff->va, buff_size);
 		retval = le16_to_cpu(desc->retval);

drivers/net/ethernet/intel/i40e/i40e_common.c+1−1

@@ -507,7 +507,7 @@ i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, · 506 unmodified lines
507		507
508	/* save link status information */	508	/* save link status information */
509	if (link)	509	if (link)
510	memcpy(link, hw_link_info, sizeof(struct i40e_link_status));	510	link = hw_link_info;
511		511
512	/* flag cleared so helper functions don't call AQ again */	512	/* flag cleared so helper functions don't call AQ again */
513	hw->phy.get_link_info = false;	513	hw->phy.get_link_info = false;

drivers/net/ethernet/intel/i40e/i40e_main.c+82−80

@@ -101,10 +101,10 @@ int i40e_allocate_dma_mem_d(struct i40e_hw hw, struct i40e_dma_mem mem, · 100 unmodified lines
101	mem->size = ALIGN(size, alignment);	101	mem->size = ALIGN(size, alignment);
102	mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,	102	mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
103	&mem->pa, GFP_KERNEL);	103	&mem->pa, GFP_KERNEL);
104	if (mem->va)	104	if (!mem->va)
105	return 0;	105	return -ENOMEM;
106		106
107	return -ENOMEM;	107	return 0;
108	}	108	}
109		109
110	/**	110	/**
@@ -136,10 +136,10 @@ int i40e_allocate_virt_mem_d(struct i40e_hw hw, struct i40e_virt_mem mem, · 25 unmodified lines
136	mem->size = size;	136	mem->size = size;
137	mem->va = kzalloc(size, GFP_KERNEL);	137	mem->va = kzalloc(size, GFP_KERNEL);
138		138
139	if (mem->va)	139	if (!mem->va)
140	return 0;	140	return -ENOMEM;
141		141
142	return -ENOMEM;	142	return 0;
143	}	143	}
144		144
145	/**	145	/**
@@ -174,8 +174,7 @@ static int i40e_get_lump(struct i40e_pf pf, struct i40e_lump_tracking pile, · 28 unmodified lines
174	u16 needed, u16 id)	174	u16 needed, u16 id)
175	{	175	{
176	int ret = -ENOMEM;	176	int ret = -ENOMEM;
177	int i = 0;	177	int i, j;
178	int j = 0;
179		178
180	if (!pile \|\| needed == 0 \|\| id >= I40E_PILE_VALID_BIT) {	179	if (!pile \|\| needed == 0 \|\| id >= I40E_PILE_VALID_BIT) {
181	dev_info(&pf->pdev->dev,	180	dev_info(&pf->pdev->dev,
@@ -186,7 +185,7 @@ static int i40e_get_lump(struct i40e_pf pf, struct i40e_lump_tracking pile, · 4 unmodified lines
186		185
187	/* start the linear search with an imperfect hint */	186	/* start the linear search with an imperfect hint */
188	i = pile->search_hint;	187	i = pile->search_hint;
189	while (i < pile->num_entries && ret < 0) {	188	while (i < pile->num_entries) {
190	/* skip already allocated entries */	189	/* skip already allocated entries */
191	if (pile->list[i] & I40E_PILE_VALID_BIT) {	190	if (pile->list[i] & I40E_PILE_VALID_BIT) {
192	i++;	191	i++;
@@ -205,6 +204,7 @@ static int i40e_get_lump(struct i40e_pf pf, struct i40e_lump_tracking pile, · 12 unmodified lines
205	pile->list[i+j] = id \| I40E_PILE_VALID_BIT;	204	pile->list[i+j] = id \| I40E_PILE_VALID_BIT;
206	ret = i;	205	ret = i;
207	pile->search_hint = i + j;	206	pile->search_hint = i + j;
		207	break;
208	} else {	208	} else {
209	/* not enough, so skip over it and continue looking */	209	/* not enough, so skip over it and continue looking */
210	i += j;	210	i += j;
@@ -1388,7 +1388,7 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi) · 1177 unmodified lines
1388	bool add_happened = false;	1388	bool add_happened = false;
1389	int filter_list_len = 0;	1389	int filter_list_len = 0;
1390	u32 changed_flags = 0;	1390	u32 changed_flags = 0;
1391	i40e_status ret = 0;	1391	i40e_status aq_ret = 0;
1392	struct i40e_pf *pf;	1392	struct i40e_pf *pf;
1393	int num_add = 0;	1393	int num_add = 0;
1394	int num_del = 0;	1394	int num_del = 0;
@@ -1449,28 +1449,28 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi) · 54 unmodified lines
1449		1449
1450	/* flush a full buffer */	1450	/* flush a full buffer */
1451	if (num_del == filter_list_len) {	1451	if (num_del == filter_list_len) {
1452	ret = i40e_aq_remove_macvlan(&pf->hw,	1452	aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1453	vsi->seid, del_list, num_del,	1453	vsi->seid, del_list, num_del,
1454	NULL);	1454	NULL);
1455	num_del = 0;	1455	num_del = 0;
1456	memset(del_list, 0, sizeof(*del_list));	1456	memset(del_list, 0, sizeof(*del_list));
1457		1457
1458	if (ret)	1458	if (aq_ret)
1459	dev_info(&pf->pdev->dev,	1459	dev_info(&pf->pdev->dev,
1460	"ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",	1460	"ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
1461	ret,	1461	aq_ret,
1462	pf->hw.aq.asq_last_status);	1462	pf->hw.aq.asq_last_status);
1463	}	1463	}
1464	}	1464	}
1465	if (num_del) {	1465	if (num_del) {
1466	ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,	1466	aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
1467	del_list, num_del, NULL);	1467	del_list, num_del, NULL);
1468	num_del = 0;	1468	num_del = 0;
1469		1469
1470	if (ret)	1470	if (aq_ret)
1471	dev_info(&pf->pdev->dev,	1471	dev_info(&pf->pdev->dev,
1472	"ignoring delete macvlan error, err %d, aq_err %d\n",	1472	"ignoring delete macvlan error, err %d, aq_err %d\n",
1473	ret, pf->hw.aq.asq_last_status);	1473	aq_ret, pf->hw.aq.asq_last_status);
1474	}	1474	}
1475		1475
1476	kfree(del_list);	1476	kfree(del_list);
@@ -1515,32 +1515,30 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi) · 38 unmodified lines
1515		1515
1516	/* flush a full buffer */	1516	/* flush a full buffer */
1517	if (num_add == filter_list_len) {	1517	if (num_add == filter_list_len) {
1518	ret = i40e_aq_add_macvlan(&pf->hw,	1518	aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1519	vsi->seid,	1519	add_list, num_add,
1520	add_list,	1520	NULL);
1521	num_add,
1522	NULL);
1523	num_add = 0;	1521	num_add = 0;
1524		1522
1525	if (ret)	1523	if (aq_ret)
1526	break;	1524	break;
1527	memset(add_list, 0, sizeof(*add_list));	1525	memset(add_list, 0, sizeof(*add_list));
1528	}	1526	}
1529	}	1527	}
1530	if (num_add) {	1528	if (num_add) {
1531	ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,	1529	aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1532	add_list, num_add, NULL);	1530	add_list, num_add, NULL);
1533	num_add = 0;	1531	num_add = 0;
1534	}	1532	}
1535	kfree(add_list);	1533	kfree(add_list);
1536	add_list = NULL;	1534	add_list = NULL;
1537		1535
1538	if (add_happened && (!ret)) {	1536	if (add_happened && (!aq_ret)) {
1539	/* do nothing */;	1537	/* do nothing */;
1540	} else if (add_happened && (ret)) {	1538	} else if (add_happened && (aq_ret)) {
1541	dev_info(&pf->pdev->dev,	1539	dev_info(&pf->pdev->dev,
1542	"add filter failed, err %d, aq_err %d\n",	1540	"add filter failed, err %d, aq_err %d\n",
1543	ret, pf->hw.aq.asq_last_status);	1541	aq_ret, pf->hw.aq.asq_last_status);
1544	if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&	1542	if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1545	!test_bit(__I40E_FILTER_OVERFLOW_PROMISC,	1543	!test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1546	&vsi->state)) {	1544	&vsi->state)) {
@@ -1556,28 +1554,27 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi) · 9 unmodified lines
1556	if (changed_flags & IFF_ALLMULTI) {	1554	if (changed_flags & IFF_ALLMULTI) {
1557	bool cur_multipromisc;	1555	bool cur_multipromisc;
1558	cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);	1556	cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
1559	ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,	1557	aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1560	vsi->seid,	1558	vsi->seid,
1561	cur_multipromisc,	1559	cur_multipromisc,
1562	NULL);	1560	NULL);
1563	if (ret)	1561	if (aq_ret)
1564	dev_info(&pf->pdev->dev,	1562	dev_info(&pf->pdev->dev,
1565	"set multi promisc failed, err %d, aq_err %d\n",	1563	"set multi promisc failed, err %d, aq_err %d\n",
1566	ret, pf->hw.aq.asq_last_status);	1564	aq_ret, pf->hw.aq.asq_last_status);
1567	}	1565	}
1568	if ((changed_flags & IFF_PROMISC) \|\| promisc_forced_on) {	1566	if ((changed_flags & IFF_PROMISC) \|\| promisc_forced_on) {
1569	bool cur_promisc;	1567	bool cur_promisc;
1570	cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) \|\|	1568	cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) \|\|
1571	test_bit(__I40E_FILTER_OVERFLOW_PROMISC,	1569	test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1572	&vsi->state));	1570	&vsi->state));
1573	ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,	1571	aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1574	vsi->seid,	1572	vsi->seid,
1575	cur_promisc,	1573	cur_promisc, NULL);
1576	NULL);	1574	if (aq_ret)
1577	if (ret)
1578	dev_info(&pf->pdev->dev,	1575	dev_info(&pf->pdev->dev,
1579	"set uni promisc failed, err %d, aq_err %d\n",	1576	"set uni promisc failed, err %d, aq_err %d\n",
1580	ret, pf->hw.aq.asq_last_status);	1577	aq_ret, pf->hw.aq.asq_last_status);
1581	}	1578	}
1582		1579
1583	clear_bit(__I40E_CONFIG_BUSY, &vsi->state);	1580	clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
@@ -1790,6 +1787,8 @@ int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid) · 206 unmodified lines
1790	* i40e_vsi_kill_vlan - Remove vsi membership for given vlan	1787	* i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1791	* @vsi: the vsi being configured	1788	* @vsi: the vsi being configured
1792	* @vid: vlan id to be removed (0 = untagged only , -1 = any)	1789	* @vid: vlan id to be removed (0 = untagged only , -1 = any)
		1790	*
		1791	* Return: 0 on success or negative otherwise
1793	**/	1792	**/
1794	int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)	1793	int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1795	{	1794	{
@@ -1863,37 +1862,39 @@ int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid) · 67 unmodified lines
1863	* i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload	1862	* i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1864	* @netdev: network interface to be adjusted	1863	* @netdev: network interface to be adjusted
1865	* @vid: vlan id to be added	1864	* @vid: vlan id to be added
		1865	*
		1866	* net_device_ops implementation for adding vlan ids
1866	**/	1867	**/
1867	static int i40e_vlan_rx_add_vid(struct net_device *netdev,	1868	static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1868	__always_unused __be16 proto, u16 vid)	1869	__always_unused __be16 proto, u16 vid)
1869	{	1870	{
1870	struct i40e_netdev_priv *np = netdev_priv(netdev);	1871	struct i40e_netdev_priv *np = netdev_priv(netdev);
1871	struct i40e_vsi *vsi = np->vsi;	1872	struct i40e_vsi *vsi = np->vsi;
1872	int ret;	1873	int ret = 0;
1873		1874
1874	if (vid > 4095)	1875	if (vid > 4095)
1875	return 0;	1876	return -EINVAL;
		1877
		1878	netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
1876		1879
1877	netdev_info(vsi->netdev, "adding %pM vid=%d\n",
1878	netdev->dev_addr, vid);
1879	/* If the network stack called us with vid = 0, we should	1880	/* If the network stack called us with vid = 0, we should
1880	* indicate to i40e_vsi_add_vlan() that we want to receive	1881	* indicate to i40e_vsi_add_vlan() that we want to receive
1881	* any traffic (i.e. with any vlan tag, or untagged)	1882	* any traffic (i.e. with any vlan tag, or untagged)
1882	*/	1883	*/
1883	ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);	1884	ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1884		1885
1885	if (!ret) {	1886	if (!ret && (vid < VLAN_N_VID))
1886	if (vid < VLAN_N_VID)	1887	set_bit(vid, vsi->active_vlans);
1887	set_bit(vid, vsi->active_vlans);
1888	}
1889		1888
1890	return 0;	1889	return ret;
1891	}	1890	}
1892		1891
1893	/**	1892	/**
1894	* i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload	1893	* i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1895	* @netdev: network interface to be adjusted	1894	* @netdev: network interface to be adjusted
1896	* @vid: vlan id to be removed	1895	* @vid: vlan id to be removed
		1896	*
		1897	* net_device_ops implementation for adding vlan ids
1897	**/	1898	**/
1898	static int i40e_vlan_rx_kill_vid(struct net_device *netdev,	1899	static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1899	__always_unused __be16 proto, u16 vid)	1900	__always_unused __be16 proto, u16 vid)
@@ -1901,15 +1902,16 @@ static int i40e_vlan_rx_kill_vid(struct net_device *netdev, · 1 unmodified line
1901	struct i40e_netdev_priv *np = netdev_priv(netdev);	1902	struct i40e_netdev_priv *np = netdev_priv(netdev);
1902	struct i40e_vsi *vsi = np->vsi;	1903	struct i40e_vsi *vsi = np->vsi;
1903		1904
1904	netdev_info(vsi->netdev, "removing %pM vid=%d\n",	1905	netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1905	netdev->dev_addr, vid);	1906
1906	/* return code is ignored as there is nothing a user	1907	/* return code is ignored as there is nothing a user
1907	* can do about failure to remove and a log message was	1908	* can do about failure to remove and a log message was
1908	* already printed from another function	1909	* already printed from the other function
1909	*/	1910	*/
1910	i40e_vsi_kill_vlan(vsi, vid);	1911	i40e_vsi_kill_vlan(vsi, vid);
1911		1912
1912	clear_bit(vid, vsi->active_vlans);	1913	clear_bit(vid, vsi->active_vlans);
		1914
1913	return 0;	1915	return 0;
1914	}	1916	}
1915		1917
@@ -1936,10 +1938,10 @@ static void i40e_restore_vlan(struct i40e_vsi *vsi) · 20 unmodified lines
1936	* @vsi: the vsi being adjusted	1938	* @vsi: the vsi being adjusted
1937	* @vid: the vlan id to set as a PVID	1939	* @vid: the vlan id to set as a PVID
1938	**/	1940	**/
1939	i40e_status i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)	1941	int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
1940	{	1942	{
1941	struct i40e_vsi_context ctxt;	1943	struct i40e_vsi_context ctxt;
1942	i40e_status ret;	1944	i40e_status aq_ret;
1943		1945
1944	vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);	1946	vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1945	vsi->info.pvid = cpu_to_le16(vid);	1947	vsi->info.pvid = cpu_to_le16(vid);
@@ -1948,14 +1950,15 @@ i40e_status i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid) · 2 unmodified lines
1948		1950
1949	ctxt.seid = vsi->seid;	1951	ctxt.seid = vsi->seid;
1950	memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));	1952	memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1951	ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);	1953	aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1952	if (ret) {	1954	if (aq_ret) {
1953	dev_info(&vsi->back->pdev->dev,	1955	dev_info(&vsi->back->pdev->dev,
1954	"%s: update vsi failed, aq_err=%d\n",	1956	"%s: update vsi failed, aq_err=%d\n",
1955	__func__, vsi->back->hw.aq.asq_last_status);	1957	__func__, vsi->back->hw.aq.asq_last_status);
		1958	return -ENOENT;
1956	}	1959	}
1957		1960
1958	return ret;	1961	return 0;
1959	}	1962	}
1960		1963
1961	/**	1964	/**
@@ -3326,7 +3329,8 @@ static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf) · 1364 unmodified lines
3326	**/	3329	**/
3327	static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)	3330	static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3328	{	3331	{
3329	int num_tc = 0, i;	3332	u8 num_tc = 0;
		3333	int i;
3330		3334
3331	/* Scan the ETS Config Priority Table to find	3335	/* Scan the ETS Config Priority Table to find
3332	* traffic class enabled for a given priority	3336	* traffic class enabled for a given priority
@@ -3341,9 +3345,7 @@ static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg) · 8 unmodified lines
3341	/* Traffic class index starts from zero so	3345	/* Traffic class index starts from zero so
3342	* increment to return the actual count	3346	* increment to return the actual count
3343	*/	3347	*/
3344	num_tc++;	3348	return num_tc + 1;
3345
3346	return num_tc;
3347	}	3349	}
3348		3350
3349	/**	3351	/**
@@ -3451,28 +3453,27 @@ static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) · 101 unmodified lines
3451	struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};	3453	struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3452	struct i40e_pf *pf = vsi->back;	3454	struct i40e_pf *pf = vsi->back;
3453	struct i40e_hw *hw = &pf->hw;	3455	struct i40e_hw *hw = &pf->hw;
		3456	i40e_status aq_ret;
3454	u32 tc_bw_max;	3457	u32 tc_bw_max;
3455	int ret;
3456	int i;	3458	int i;
3457		3459
3458	/* Get the VSI level BW configuration */	3460	/* Get the VSI level BW configuration */
3459	ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);	3461	aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3460	if (ret) {	3462	if (aq_ret) {
3461	dev_info(&pf->pdev->dev,	3463	dev_info(&pf->pdev->dev,
3462	"couldn't get pf vsi bw config, err %d, aq_err %d\n",	3464	"couldn't get pf vsi bw config, err %d, aq_err %d\n",
3463	ret, pf->hw.aq.asq_last_status);	3465	aq_ret, pf->hw.aq.asq_last_status);
3464	return ret;	3466	return -EINVAL;
3465	}	3467	}
3466		3468
3467	/* Get the VSI level BW configuration per TC */	3469	/* Get the VSI level BW configuration per TC */
3468	ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,	3470	aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3469	&bw_ets_config,	3471	NULL);
3470	NULL);	3472	if (aq_ret) {
3471	if (ret) {
3472	dev_info(&pf->pdev->dev,	3473	dev_info(&pf->pdev->dev,
3473	"couldn't get pf vsi ets bw config, err %d, aq_err %d\n",	3474	"couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
3474	ret, pf->hw.aq.asq_last_status);	3475	aq_ret, pf->hw.aq.asq_last_status);
3475	return ret;	3476	return -EINVAL;
3476	}	3477	}
3477		3478
3478	if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {	3479	if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
@@ -3494,7 +3495,8 @@ static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) · 15 unmodified lines
3494	/* 3 bits out of 4 for each TC */	3495	/* 3 bits out of 4 for each TC */
3495	vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);	3496	vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3496	}	3497	}
3497	return ret;	3498
		3499	return 0;
3498	}	3500	}
3499		3501
3500	/**	3502	/**
@@ -3505,30 +3507,30 @@ static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) · 4 unmodified lines
3505	*	3507	*
3506	* Returns 0 on success, negative value on failure	3508	* Returns 0 on success, negative value on failure
3507	**/	3509	**/
3508	static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi,	3510	static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
3509	u8 enabled_tc,
3510	u8 *bw_share)	3511	u8 *bw_share)
3511	{	3512	{
3512	struct i40e_aqc_configure_vsi_tc_bw_data bw_data;	3513	struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
3513	int i, ret = 0;	3514	i40e_status aq_ret;
		3515	int i;
3514		3516
3515	bw_data.tc_valid_bits = enabled_tc;	3517	bw_data.tc_valid_bits = enabled_tc;
3516	for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)	3518	for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3517	bw_data.tc_bw_credits[i] = bw_share[i];	3519	bw_data.tc_bw_credits[i] = bw_share[i];
3518		3520
3519	ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid,	3521	aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3520	&bw_data, NULL);	3522	NULL);
3521	if (ret) {	3523	if (aq_ret) {
3522	dev_info(&vsi->back->pdev->dev,	3524	dev_info(&vsi->back->pdev->dev,
3523	"%s: AQ command Config VSI BW allocation per TC failed = %d\n",	3525	"%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3524	__func__, vsi->back->hw.aq.asq_last_status);	3526	__func__, vsi->back->hw.aq.asq_last_status);
3525	return ret;	3527	return -EINVAL;
3526	}	3528	}
3527		3529
3528	for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)	3530	for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3529	vsi->info.qs_handle[i] = bw_data.qs_handles[i];	3531	vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3530		3532
3531	return ret;	3533	return 0;
3532	}	3534	}
3533		3535
3534	/**	3536	/**

drivers/net/ethernet/intel/igb/e1000_82575.c+4−0

 	u32 ctrl_ext;
 	u32 mdic;
+	/* Extra read required for some PHY's on i354 */
+	if (hw->mac.type == e1000_i354)
+		igb_get_phy_id(hw);
 	/* For SGMII PHYs, we try the list of possible addresses until
 	 * we find one that works.  For non-SGMII PHYs
 	 * (e.g. integrated copper PHYs), an address of 1 should

drivers/net/ethernet/intel/igb/e1000_mac.c+9−1

 static s32 igb_set_default_fc(struct e1000_hw *hw)
 {
 	s32 ret_val = 0;
+	u16 lan_offset;
 	u16 nvm_data;
 	/* Read and store word 0x0F of the EEPROM. This word contains bits
 	 * control setting, then the variable hw->fc will
 	 * be initialized based on a value in the EEPROM.
 	 */
-	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
+	if (hw->mac.type == e1000_i350) {
+		lan_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
+		ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG
+					   + lan_offset, 1, &nvm_data);
+	 } else {
+		ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG,
+					   1, &nvm_data);
+	 }
 	if (ret_val) {
 		hw_dbg("NVM Read Error\n");

drivers/net/ethernet/intel/igb/igb_ethtool.c+3−0

 			igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
 			igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
 		}
+	} else if (hw->phy.type == e1000_phy_82580) {
+		/* enable MII loopback */
+		igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
 	}
 	/* add small delay to avoid loopback test failure */

drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c+25−0

 	bool autoneg = false;
 	bool link_up;
+	/* SFP type is needed for get_link_capabilities */
+	if (hw->phy.media_type & (ixgbe_media_type_fiber |
+				  ixgbe_media_type_fiber_qsfp)) {
+		if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
+				hw->phy.ops.identify_sfp(hw);
+	}
 	hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
 	/* set the supported link speeds */
 			ecmd->advertising |= ADVERTISED_1000baseT_Full;
 		if (supported_link & IXGBE_LINK_SPEED_100_FULL)
 			ecmd->advertising |= ADVERTISED_100baseT_Full;
+		if (hw->phy.multispeed_fiber && !autoneg) {
+			if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
+				ecmd->advertising = ADVERTISED_10000baseT_Full;
+		}
 	}
 	if (autoneg) {
 		if (ecmd->advertising & ~ecmd->supported)
 			return -EINVAL;
+		/* only allow one speed at a time if no autoneg */
+		if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
+			if (ecmd->advertising ==
+			    (ADVERTISED_10000baseT_Full |
+			     ADVERTISED_1000baseT_Full))
+				return -EINVAL;
+		}
 		old = hw->phy.autoneg_advertised;
 		advertised = 0;
 		if (ecmd->advertising & ADVERTISED_10000baseT_Full)
 	unsigned int size = 1024;
 	netdev_tx_t tx_ret_val;
 	struct sk_buff *skb;
+	u32 flags_orig = adapter->flags;
+	/* DCB can modify the frames on Tx */
+	adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
 	/* allocate test skb */
 	skb = alloc_skb(size, GFP_KERNEL);
 	/* free the original skb */
 	kfree_skb(skb);
+	adapter->flags = flags_orig;
 	return ret_val;
 }

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c+17−2

 {
 	struct ixgbe_hw *hw = &adapter->hw;
 	int i;
-	u32 rxctrl;
+	u32 rxctrl, rfctl;
 	/* disable receives while setting up the descriptors */
 	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 	ixgbe_setup_psrtype(adapter);
 	ixgbe_setup_rdrxctl(adapter);
+	/* RSC Setup */
+	rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
+	rfctl &= ~IXGBE_RFCTL_RSC_DIS;
+	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
+		rfctl |= IXGBE_RFCTL_RSC_DIS;
+	IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
 	/* Program registers for the distribution of queues */
 	ixgbe_setup_mrqc(adapter);
 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
 	speed = hw->phy.autoneg_advertised;
-	if ((!speed) && (hw->mac.ops.get_link_capabilities))
+	if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
 		hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
+		/* setup the highest link when no autoneg */
+		if (!autoneg) {
+			if (speed & IXGBE_LINK_SPEED_10GB_FULL)
+				speed = IXGBE_LINK_SPEED_10GB_FULL;
+		}
+	}
 	if (hw->mac.ops.setup_link)
 		hw->mac.ops.setup_link(hw, speed, true);

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h+1−0

@@ -1861,6 +1861,7 @@ enum { · 1860 unmodified lines
1861	#define IXGBE_RFCTL_ISCSI_DIS 0x00000001	1861	#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1862	#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E	1862	#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1863	#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1	1863	#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
		1864	#define IXGBE_RFCTL_RSC_DIS 0x00000020
1864	#define IXGBE_RFCTL_NFSW_DIS 0x00000040	1865	#define IXGBE_RFCTL_NFSW_DIS 0x00000040
1865	#define IXGBE_RFCTL_NFSR_DIS 0x00000080	1866	#define IXGBE_RFCTL_NFSR_DIS 0x00000080
1866	#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300	1867	#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300

drivers/net/ethernet/lantiq_etop.c+2−4

 		if (IS_TX(i)) {
 			ltq_dma_alloc_tx(&ch->dma);
-			request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
+			request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
-				"etop_tx", priv);
 		} else if (IS_RX(i)) {
 			ltq_dma_alloc_rx(&ch->dma);
 			for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 				if (ltq_etop_alloc_skb(ch))
 					return -ENOMEM;
 			ch->dma.desc = 0;
-			request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
+			request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
-				"etop_rx", priv);
 		}
 		ch->dma.irq = irq;
 	}

drivers/net/ethernet/marvell/pxa168_eth.c+1−2

@@ -1123,8 +1123,7 @@ static int pxa168_eth_open(struct net_device *dev) · 1122 unmodified lines
1123	struct pxa168_eth_private *pep = netdev_priv(dev);	1123	struct pxa168_eth_private *pep = netdev_priv(dev);
1124	int err;	1124	int err;
1125		1125
1126	err = request_irq(dev->irq, pxa168_eth_int_handler,	1126	err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev);
1127	IRQF_DISABLED, dev->name, dev);
1128	if (err) {	1127	if (err) {
1129	dev_err(&dev->dev, "can't assign irq\n");	1128	dev_err(&dev->dev, "can't assign irq\n");
1130	return -EAGAIN;	1129	return -EAGAIN;

drivers/net/ethernet/marvell/skge.c+8−4

 					       PCI_DMA_FROMDEVICE);
 		skge_rx_reuse(e, skge->rx_buf_size);
 	} else {
+		struct skge_element ee;
 		struct sk_buff *nskb;
 		nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
 		if (!nskb)
 			goto resubmit;
+		ee = *e;
+		skb = ee.skb;
+		prefetch(skb->data);
 		if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
 			dev_kfree_skb(nskb);
 			goto resubmit;
 		}
 		pci_unmap_single(skge->hw->pdev,
-				 dma_unmap_addr(e, mapaddr),
+				 dma_unmap_addr(&ee, mapaddr),
-				 dma_unmap_len(e, maplen),
+				 dma_unmap_len(&ee, maplen),
 				 PCI_DMA_FROMDEVICE);
-		skb = e->skb;
-		prefetch(skb->data);
 	}
 	skb_put(skb, len);

drivers/net/ethernet/mellanox/mlx4/en_ethtool.c+10−6

 	for (i = 0; i < priv->tx_ring_num; i++) {
 		priv->tx_cq[i].moder_cnt = priv->tx_frames;
 		priv->tx_cq[i].moder_time = priv->tx_usecs;
-		err = mlx4_en_set_cq_moder(priv, &priv->tx_cq[i]);
+		if (priv->port_up) {
-		if (err)
+			err = mlx4_en_set_cq_moder(priv, &priv->tx_cq[i]);
-			return err;
+			if (err)
+				return err;
+		}
 	}
 	if (priv->adaptive_rx_coal)
 		priv->rx_cq[i].moder_cnt = priv->rx_frames;
 		priv->rx_cq[i].moder_time = priv->rx_usecs;
 		priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
-		err = mlx4_en_set_cq_moder(priv, &priv->rx_cq[i]);
+		if (priv->port_up) {
-		if (err)
+			err = mlx4_en_set_cq_moder(priv, &priv->rx_cq[i]);
-			return err;
+			if (err)
+				return err;
+		}
 	}
 	return err;

drivers/net/ethernet/micrel/ks8851_mll.c+1−1

@@ -915,7 +915,7 @@ static int ks_net_open(struct net_device *netdev) · 914 unmodified lines
915	struct ks_net *ks = netdev_priv(netdev);	915	struct ks_net *ks = netdev_priv(netdev);
916	int err;	916	int err;
917		917
918	#define KS_INT_FLAGS (IRQF_DISABLED\|IRQF_TRIGGER_LOW)	918	#define KS_INT_FLAGS IRQF_TRIGGER_LOW
919	/* lock the card, even if we may not actually do anything	919	/* lock the card, even if we may not actually do anything
920	* else at the moment.	920	* else at the moment.
921	*/	921	*/

drivers/net/ethernet/moxa/moxart_ether.c+1−1

@@ -543,7 +543,7 @@ static const struct of_device_id moxart_mac_match[] = { · 542 unmodified lines
543	{ }	543	{ }
544	};	544	};
545		545
546	struct __initdata platform_driver moxart_mac_driver = {	546	static struct platform_driver moxart_mac_driver = {
547	.probe = moxart_mac_probe,	547	.probe = moxart_mac_probe,
548	.remove = moxart_remove,	548	.remove = moxart_remove,
549	.driver = {	549	.driver = {

drivers/net/ethernet/natsemi/jazzsonic.c+1−2

@@ -83,8 +83,7 @@ static int jazzsonic_open(struct net_device* dev) · 82 unmodified lines
83	{	83	{
84	int retval;	84	int retval;
85		85
86	retval = request_irq(dev->irq, sonic_interrupt, IRQF_DISABLED,	86	retval = request_irq(dev->irq, sonic_interrupt, 0, "sonic", dev);
87	"sonic", dev);
88	if (retval) {	87	if (retval) {
89	printk(KERN_ERR "%s: unable to get IRQ %d.\n",	88	printk(KERN_ERR "%s: unable to get IRQ %d.\n",
90	dev->name, dev->irq);	89	dev->name, dev->irq);

drivers/net/ethernet/natsemi/xtsonic.c+1−2

@@ -95,8 +95,7 @@ static int xtsonic_open(struct net_device *dev) · 94 unmodified lines
95	{	95	{
96	int retval;	96	int retval;
97		97
98	retval = request_irq(dev->irq, sonic_interrupt, IRQF_DISABLED,	98	retval = request_irq(dev->irq, sonic_interrupt, 0, "sonic", dev);
99	"sonic", dev);
100	if (retval) {	99	if (retval) {
101	printk(KERN_ERR "%s: unable to get IRQ %d.\n",	100	printk(KERN_ERR "%s: unable to get IRQ %d.\n",
102	dev->name, dev->irq);	101	dev->name, dev->irq);

drivers/net/ethernet/pasemi/pasemi_mac.c+2−2

@@ -1219,7 +1219,7 @@ static int pasemi_mac_open(struct net_device *dev) · 1218 unmodified lines
1219	snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",	1219	snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
1220	dev->name);	1220	dev->name);
1221		1221
1222	ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, IRQF_DISABLED,	1222	ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, 0,
1223	mac->tx_irq_name, mac->tx);	1223	mac->tx_irq_name, mac->tx);
1224	if (ret) {	1224	if (ret) {
1225	dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",	1225	dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
@@ -1230,7 +1230,7 @@ static int pasemi_mac_open(struct net_device *dev) · 4 unmodified lines
1230	snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",	1230	snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
1231	dev->name);	1231	dev->name);
1232		1232
1233	ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, IRQF_DISABLED,	1233	ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, 0,
1234	mac->rx_irq_name, mac->rx);	1234	mac->rx_irq_name, mac->rx);
1235	if (ret) {	1235	if (ret) {
1236	dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",	1236	dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",

drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c+8−0

@@ -1794,3 +1794,11 @@ const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops = { · 1793 unmodified lines
1794	.set_msglevel = qlcnic_set_msglevel,	1794	.set_msglevel = qlcnic_set_msglevel,
1795	.get_msglevel = qlcnic_get_msglevel,	1795	.get_msglevel = qlcnic_get_msglevel,
1796	};	1796	};
		1797
		1798	const struct ethtool_ops qlcnic_ethtool_failed_ops = {
		1799	.get_settings = qlcnic_get_settings,
		1800	.get_drvinfo = qlcnic_get_drvinfo,
		1801	.set_msglevel = qlcnic_set_msglevel,
		1802	.get_msglevel = qlcnic_get_msglevel,
		1803	.set_dump = qlcnic_set_dump,
		1804	};

drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c+37−2

@@ -431,6 +431,9 @@ static void qlcnic_82xx_cancel_idc_work(struct qlcnic_adapter *adapter) · 430 unmodified lines
431	while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))	431	while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
432	usleep_range(10000, 11000);	432	usleep_range(10000, 11000);
433		433
		434	if (!adapter->fw_work.work.func)
		435	return;
		436
434	cancel_delayed_work_sync(&adapter->fw_work);	437	cancel_delayed_work_sync(&adapter->fw_work);
435	}	438	}
436		439
@@ -2275,8 +2278,9 @@ qlcnic_probe(struct pci_dev pdev, const struct pci_device_id ent) · 1838 unmodified lines
2275	adapter->portnum = adapter->ahw->pci_func;	2278	adapter->portnum = adapter->ahw->pci_func;
2276	err = qlcnic_start_firmware(adapter);	2279	err = qlcnic_start_firmware(adapter);
2277	if (err) {	2280	if (err) {
2278	dev_err(&pdev->dev, "Loading fw failed.Please Reboot\n");	2281	dev_err(&pdev->dev, "Loading fw failed.Please Reboot\n"
2279	goto err_out_free_hw;	2282	"\t\tIf reboot doesn't help, try flashing the card\n");
		2283	goto err_out_maintenance_mode;
2280	}	2284	}
2281		2285
2282	qlcnic_get_multiq_capability(adapter);	2286	qlcnic_get_multiq_capability(adapter);
@@ -2408,6 +2412,22 @@ err_out_disable_pdev: · 125 unmodified lines
2408	pci_set_drvdata(pdev, NULL);	2412	pci_set_drvdata(pdev, NULL);
2409	pci_disable_device(pdev);	2413	pci_disable_device(pdev);
2410	return err;	2414	return err;
		2415
		2416	err_out_maintenance_mode:
		2417	netdev->netdev_ops = &qlcnic_netdev_failed_ops;
		2418	SET_ETHTOOL_OPS(netdev, &qlcnic_ethtool_failed_ops);
		2419	err = register_netdev(netdev);
		2420
		2421	if (err) {
		2422	dev_err(&pdev->dev, "Failed to register net device\n");
		2423	qlcnic_clr_all_drv_state(adapter, 0);
		2424	goto err_out_free_hw;
		2425	}
		2426
		2427	pci_set_drvdata(pdev, adapter);
		2428	qlcnic_add_sysfs(adapter);
		2429
		2430	return 0;
2411	}	2431	}
2412		2432
2413	static void qlcnic_remove(struct pci_dev *pdev)	2433	static void qlcnic_remove(struct pci_dev *pdev)
@@ -2518,8 +2538,16 @@ static int qlcnic_resume(struct pci_dev *pdev) · 104 unmodified lines
2518	static int qlcnic_open(struct net_device *netdev)	2538	static int qlcnic_open(struct net_device *netdev)
2519	{	2539	{
2520	struct qlcnic_adapter *adapter = netdev_priv(netdev);	2540	struct qlcnic_adapter *adapter = netdev_priv(netdev);
		2541	u32 state;
2521	int err;	2542	int err;
2522		2543
		2544	state = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DEV_STATE);
		2545	if (state == QLCNIC_DEV_FAILED \|\| state == QLCNIC_DEV_BADBAD) {
		2546	netdev_err(netdev, "%s: Device is in FAILED state\n", __func__);
		2547
		2548	return -EIO;
		2549	}
		2550
2523	netif_carrier_off(netdev);	2551	netif_carrier_off(netdev);
2524		2552
2525	err = qlcnic_attach(adapter);	2553	err = qlcnic_attach(adapter);
@@ -3228,6 +3256,13 @@ void qlcnic_82xx_dev_request_reset(struct qlcnic_adapter *adapter, u32 key) · 702 unmodified lines
3228	return;	3256	return;
3229		3257
3230	state = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DEV_STATE);	3258	state = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DEV_STATE);
		3259	if (state == QLCNIC_DEV_FAILED \|\| state == QLCNIC_DEV_BADBAD) {
		3260	netdev_err(adapter->netdev, "%s: Device is in FAILED state\n",
		3261	__func__);
		3262	qlcnic_api_unlock(adapter);
		3263
		3264	return;
		3265	}
3231		3266
3232	if (state == QLCNIC_DEV_READY) {	3267	if (state == QLCNIC_DEV_READY) {
3233	QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DEV_STATE,	3268	QLC_SHARED_REG_WR32(adapter, QLCNIC_CRB_DEV_STATE,

drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_common.c+1−0

@@ -1561,6 +1561,7 @@ static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter) · 1560 unmodified lines
1561	{	1561	{
1562	int err;	1562	int err;
1563		1563
		1564	adapter->need_fw_reset = 0;
1564	qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);	1565	qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
1565	qlcnic_83xx_enable_mbx_interrupt(adapter);	1566	qlcnic_83xx_enable_mbx_interrupt(adapter);
1566		1567

drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_pf.c+7−1

 {
 	struct net_device *netdev = adapter->netdev;
+	rtnl_lock();
 	if (netif_running(netdev))
 		__qlcnic_down(adapter, netdev);
 	/* After disabling SRIOV re-init the driver in default mode
 	   configure opmode based on op_mode of function
 	 */
-	if (qlcnic_83xx_configure_opmode(adapter))
+	if (qlcnic_83xx_configure_opmode(adapter)) {
+		rtnl_unlock();
 		return -EIO;
+	}
 	if (netif_running(netdev))
 		__qlcnic_up(adapter, netdev);
+	rtnl_unlock();
 	return 0;
 }
 		return -EIO;
 	}
+	rtnl_lock();
 	if (netif_running(netdev))
 		__qlcnic_down(adapter, netdev);
 		__qlcnic_up(adapter, netdev);
 error:
+	rtnl_unlock();
 	return err;
 }

drivers/net/ethernet/qlogic/qlcnic/qlcnic_sysfs.c+12−0

 void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter)
 {
 	struct device *dev = &adapter->pdev->dev;
+	u32 state;
 	if (device_create_bin_file(dev, &bin_attr_port_stats))
 		dev_info(dev, "failed to create port stats sysfs entry");
 	if (device_create_bin_file(dev, &bin_attr_mem))
 		dev_info(dev, "failed to create mem sysfs entry\n");
+	state = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DEV_STATE);
+	if (state == QLCNIC_DEV_FAILED || state == QLCNIC_DEV_BADBAD)
+		return;
 	if (device_create_bin_file(dev, &bin_attr_pci_config))
 		dev_info(dev, "failed to create pci config sysfs entry");
 	if (device_create_file(dev, &dev_attr_beacon))
 		dev_info(dev, "failed to create beacon sysfs entry");
 void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter)
 {
 	struct device *dev = &adapter->pdev->dev;
+	u32 state;
 	device_remove_bin_file(dev, &bin_attr_port_stats);
 	device_remove_file(dev, &dev_attr_diag_mode);
 	device_remove_bin_file(dev, &bin_attr_crb);
 	device_remove_bin_file(dev, &bin_attr_mem);
+	state = QLC_SHARED_REG_RD32(adapter, QLCNIC_CRB_DEV_STATE);
+	if (state == QLCNIC_DEV_FAILED || state == QLCNIC_DEV_BADBAD)
+		return;
 	device_remove_bin_file(dev, &bin_attr_pci_config);
 	device_remove_file(dev, &dev_attr_beacon);
 	if (!(adapter->flags & QLCNIC_ESWITCH_ENABLED))

drivers/net/ethernet/qlogic/qlge/qlge_dbg.c+2−2

@@ -740,8 +740,8 @@ int ql_core_dump(struct ql_adapter qdev, struct ql_mpi_coredump mpi_coredump) · 739 unmodified lines
740	int i;	740	int i;
741		741
742	if (!mpi_coredump) {	742	if (!mpi_coredump) {
743	netif_err(qdev, drv, qdev->ndev, "No memory available\n");	743	netif_err(qdev, drv, qdev->ndev, "No memory allocated\n");
744	return -ENOMEM;	744	return -EINVAL;
745	}	745	}
746		746
747	/* Try to get the spinlock, but dont worry if	747	/* Try to get the spinlock, but dont worry if

drivers/net/ethernet/qlogic/qlge/qlge_mpi.c+1−1

@@ -1274,7 +1274,7 @@ void ql_mpi_reset_work(struct work_struct *work) · 1273 unmodified lines
1274	return;	1274	return;
1275	}	1275	}
1276		1276
1277	if (!ql_core_dump(qdev, qdev->mpi_coredump)) {	1277	if (qdev->mpi_coredump && !ql_core_dump(qdev, qdev->mpi_coredump)) {
1278	netif_err(qdev, drv, qdev->ndev, "Core is dumped!\n");	1278	netif_err(qdev, drv, qdev->ndev, "Core is dumped!\n");
1279	qdev->core_is_dumped = 1;	1279	qdev->core_is_dumped = 1;
1280	queue_delayed_work(qdev->workqueue,	1280	queue_delayed_work(qdev->workqueue,

drivers/net/ethernet/realtek/r8169.c+1−0

@@ -4231,6 +4231,7 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp) · 4230 unmodified lines
4231	case RTL_GIGA_MAC_VER_23:	4231	case RTL_GIGA_MAC_VER_23:
4232	case RTL_GIGA_MAC_VER_24:	4232	case RTL_GIGA_MAC_VER_24:
4233	case RTL_GIGA_MAC_VER_34:	4233	case RTL_GIGA_MAC_VER_34:
		4234	case RTL_GIGA_MAC_VER_35:
4234	RTL_W32(RxConfig, RX128_INT_EN \| RX_MULTI_EN \| RX_DMA_BURST);	4235	RTL_W32(RxConfig, RX128_INT_EN \| RX_MULTI_EN \| RX_DMA_BURST);
4235	break;	4236	break;
4236	case RTL_GIGA_MAC_VER_40:	4237	case RTL_GIGA_MAC_VER_40:

drivers/net/ethernet/sfc/Kconfig+1−1

@@ -7,7 +7,7 @@ config SFC · 6 unmodified lines
7	select I2C_ALGOBIT	7	select I2C_ALGOBIT
8	select PTP_1588_CLOCK	8	select PTP_1588_CLOCK
9	---help---	9	---help---
10	This driver supports 10-gigabit Ethernet cards based on	10	This driver supports 10/40-gigabit Ethernet cards based on
11	the Solarflare SFC4000, SFC9000-family and SFC9100-family	11	the Solarflare SFC4000, SFC9000-family and SFC9100-family
12	controllers.	12	controllers.
13		13

drivers/net/ethernet/sfc/ef10.c+37−21

@@ -94,7 +94,7 @@ static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) · 93 unmodified lines
94	return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);	94	return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
95	}	95	}
96		96
97	static int efx_ef10_init_capabilities(struct efx_nic *efx)	97	static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
98	{	98	{
99	MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);	99	MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
100	struct efx_ef10_nic_data *nic_data = efx->nic_data;	100	struct efx_ef10_nic_data *nic_data = efx->nic_data;
@@ -107,16 +107,27 @@ static int efx_ef10_init_capabilities(struct efx_nic *efx) · 6 unmodified lines
107	outbuf, sizeof(outbuf), &outlen);	107	outbuf, sizeof(outbuf), &outlen);
108	if (rc)	108	if (rc)
109	return rc;	109	return rc;
		110	if (outlen < sizeof(outbuf)) {
		111	netif_err(efx, drv, efx->net_dev,
		112	"unable to read datapath firmware capabilities\n");
		113	return -EIO;
		114	}
110		115
111	if (outlen >= sizeof(outbuf)) {	116	nic_data->datapath_caps =
112	nic_data->datapath_caps =	117	MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
113	MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);	118
114	if (!(nic_data->datapath_caps &	119	if (!(nic_data->datapath_caps &
115	(1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {	120	(1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
116	netif_err(efx, drv, efx->net_dev,	121	netif_err(efx, drv, efx->net_dev,
117	"Capabilities don't indicate TSO support.\n");	122	"current firmware does not support TSO\n");
118	return -ENODEV;	123	return -ENODEV;
119	}	124	}
		125
		126	if (!(nic_data->datapath_caps &
		127	(1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
		128	netif_err(efx, probe, efx->net_dev,
		129	"current firmware does not support an RX prefix\n");
		130	return -ENODEV;
120	}	131	}
121		132
122	return 0;	133	return 0;
@@ -217,21 +228,13 @@ static int efx_ef10_probe(struct efx_nic *efx) · 94 unmodified lines
217	if (rc)	228	if (rc)
218	goto fail3;	229	goto fail3;
219		230
220	rc = efx_ef10_init_capabilities(efx);	231	rc = efx_ef10_init_datapath_caps(efx);
221	if (rc < 0)	232	if (rc < 0)
222	goto fail3;	233	goto fail3;
223		234
224	efx->rx_packet_len_offset =	235	efx->rx_packet_len_offset =
225	ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;	236	ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
226		237
227	if (!(nic_data->datapath_caps &
228	(1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
229	netif_err(efx, probe, efx->net_dev,
230	"current firmware does not support an RX prefix\n");
231	rc = -ENODEV;
232	goto fail3;
233	}
234
235	rc = efx_mcdi_port_get_number(efx);	238	rc = efx_mcdi_port_get_number(efx);
236	if (rc < 0)	239	if (rc < 0)
237	goto fail3;	240	goto fail3;
@@ -260,8 +263,6 @@ static int efx_ef10_probe(struct efx_nic *efx) · 22 unmodified lines
260	if (rc)	263	if (rc)
261	goto fail3;	264	goto fail3;
262		265
263	efx_ptp_probe(efx);
264
265	return 0;	266	return 0;
266		267
267	fail3:	268	fail3:
@@ -342,6 +343,13 @@ static int efx_ef10_init_nic(struct efx_nic *efx) · 74 unmodified lines
342	struct efx_ef10_nic_data *nic_data = efx->nic_data;	343	struct efx_ef10_nic_data *nic_data = efx->nic_data;
343	int rc;	344	int rc;
344		345
		346	if (nic_data->must_check_datapath_caps) {
		347	rc = efx_ef10_init_datapath_caps(efx);
		348	if (rc)
		349	return rc;
		350	nic_data->must_check_datapath_caps = false;
		351	}
		352
345	if (nic_data->must_realloc_vis) {	353	if (nic_data->must_realloc_vis) {
346	/* We cannot let the number of VIs change now */	354	/* We cannot let the number of VIs change now */
347	rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,	355	rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
@@ -710,6 +718,14 @@ static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) · 362 unmodified lines
710	nic_data->must_restore_filters = true;	718	nic_data->must_restore_filters = true;
711	nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;	719	nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
712		720
		721	/* The datapath firmware might have been changed */
		722	nic_data->must_check_datapath_caps = true;
		723
		724	/* MAC statistics have been cleared on the NIC; clear the local
		725	* statistic that we update with efx_update_diff_stat().
		726	*/
		727	nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
		728
713	return -EIO;	729	return -EIO;
714	}	730	}
715		731

drivers/net/ethernet/sfc/mcdi.c+5−5

 /* A reboot/assertion causes the MCDI status word to be set after the
  * command word is set or a REBOOT event is sent. If we notice a reboot
- * via these mechanisms then wait 20ms for the status word to be set.
+ * via these mechanisms then wait 250ms for the status word to be set.
  */
 #define MCDI_STATUS_DELAY_US		100
-#define MCDI_STATUS_DELAY_COUNT		200
+#define MCDI_STATUS_DELAY_COUNT		2500
 #define MCDI_STATUS_SLEEP_MS						\
 	(MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000)
 	} else {
 		int count;
-		/* Nobody was waiting for an MCDI request, so trigger a reset */
-		efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
 		/* Consume the status word since efx_mcdi_rpc_finish() won't */
 		for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) {
 			if (efx_mcdi_poll_reboot(efx))
 			udelay(MCDI_STATUS_DELAY_US);
 		}
 		mcdi->new_epoch = true;
+		/* Nobody was waiting for an MCDI request, so trigger a reset */
+		efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
 	}
 	spin_unlock(&mcdi->iface_lock);

drivers/net/ethernet/sfc/mcdi_port.c+2−0

 		case 100:   caps = 1 << MC_CMD_PHY_CAP_100FDX_LBN;   break;
 		case 1000:  caps = 1 << MC_CMD_PHY_CAP_1000FDX_LBN;  break;
 		case 10000: caps = 1 << MC_CMD_PHY_CAP_10000FDX_LBN; break;
+		case 40000: caps = 1 << MC_CMD_PHY_CAP_40000FDX_LBN; break;
 		default:    return -EINVAL;
 		}
 	} else {
 	[MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
 	[MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
 	[MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
+	[MCDI_EVENT_LINKCHANGE_SPEED_40G] = 40000,
 };
 void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)

drivers/net/ethernet/sfc/nic.h+3−0

  * @rx_rss_context: Firmware handle for our RSS context
  * @stats: Hardware statistics
  * @workaround_35388: Flag: firmware supports workaround for bug 35388
+ * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
+ *	after MC reboot
  * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
  *	%MC_CMD_GET_CAPABILITIES response)
  */
 	u32 rx_rss_context;
 	u64 stats[EF10_STAT_COUNT];
 	bool workaround_35388;
+	bool must_check_datapath_caps;
 	u32 datapath_caps;
 };

drivers/net/ethernet/smsc/smc91x.h+1−1

@@ -271,7 +271,7 @@ static inline void mcf_outsw(void a, unsigned char p, int l) · 270 unmodified lines
271	#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)	271	#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
272	#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)	272	#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
273		273
274	#define SMC_IRQ_FLAGS (IRQF_DISABLED)	274	#define SMC_IRQ_FLAGS 0
275		275
276	#else	276	#else
277		277

drivers/net/ethernet/smsc/smsc9420.c+1−2

@@ -1356,8 +1356,7 @@ static int smsc9420_open(struct net_device *dev) · 1355 unmodified lines
1356	smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);	1356	smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1357	smsc9420_pci_flush_write(pd);	1357	smsc9420_pci_flush_write(pd);
1358		1358
1359	result = request_irq(irq, smsc9420_isr, IRQF_SHARED \| IRQF_DISABLED,	1359	result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1360	DRV_NAME, pd);
1361	if (result) {	1360	if (result) {
1362	smsc_warn(IFUP, "Unable to use IRQ = %d", irq);	1361	smsc_warn(IFUP, "Unable to use IRQ = %d", irq);
1363	result = -ENODEV;	1362	result = -ENODEV;

drivers/net/ethernet/toshiba/ps3_gelic_net.c+1−1

@@ -1726,7 +1726,7 @@ static int ps3_gelic_driver_probe(struct ps3_system_bus_device *dev) · 1725 unmodified lines
1726	goto fail_alloc_irq;	1726	goto fail_alloc_irq;
1727	}	1727	}
1728	result = request_irq(card->irq, gelic_card_interrupt,	1728	result = request_irq(card->irq, gelic_card_interrupt,
1729	IRQF_DISABLED, netdev->name, card);	1729	0, netdev->name, card);
1730		1730
1731	if (result) {	1731	if (result) {
1732	dev_info(ctodev(card), "%s:request_irq failed (%d)\n",	1732	dev_info(ctodev(card), "%s:request_irq failed (%d)\n",

drivers/net/ethernet/via/via-rhine.c+7−2

 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #define DRV_NAME	"via-rhine"
-#define DRV_VERSION	"1.5.0"
+#define DRV_VERSION	"1.5.1"
 #define DRV_RELDATE	"2010-10-09"
 #include <linux/types.h>
 		cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
 	if (unlikely(vlan_tx_tag_present(skb))) {
-		rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
+		u16 vid_pcp = vlan_tx_tag_get(skb);
+		/* drop CFI/DEI bit, register needs VID and PCP */
+		vid_pcp = (vid_pcp & VLAN_VID_MASK) |
+			  ((vid_pcp & VLAN_PRIO_MASK) >> 1);
+		rp->tx_ring[entry].tx_status = cpu_to_le32((vid_pcp) << 16);
 		/* request tagging */
 		rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
 	}

drivers/net/ethernet/xilinx/ll_temac_main.c+6−0

 		       lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
 	lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
+	/* Init descriptor indexes */
+	lp->tx_bd_ci = 0;
+	lp->tx_bd_next = 0;
+	lp->tx_bd_tail = 0;
+	lp->rx_bd_ci = 0;
 	return 0;
 out:

drivers/net/irda/mcs7780.c+23−17

 		goto error;
 	ret = 0;
-	error:
+error:
-		return ret;
+	return ret;
 }
 /* Setup a communication between mcs7780 and agilent chip. */
 		return 0;
 	mcs->rx_urb = usb_alloc_urb(0, GFP_KERNEL);
-	if (!mcs->rx_urb)
+	if (!mcs->rx_urb) {
+		usb_free_urb(mcs->tx_urb);
+		mcs->tx_urb = NULL;
 		return 0;
+	}
 	return 1;
 }
 	ret = mcs_set_reg(mcs, MCS_MODE_REG, rval);
 	mcs->speed = mcs->new_speed;
-	error:
+error:
-		mcs->new_speed = 0;
+	mcs->new_speed = 0;
-		return ret;
+	return ret;
 }
 /* Ioctl calls not supported at this time.  Can be an area of future work. */
 	ret = mcs_receive_start(mcs);
 	if (ret)
-		goto error3;
+		goto error4;
 	netif_start_queue(netdev);
 	return 0;
-	error3:
+error4:
-		irlap_close(mcs->irlap);
+	usb_free_urb(mcs->rx_urb);
-	error2:
+	usb_free_urb(mcs->tx_urb);
-		kfree_skb(mcs->rx_buff.skb);
+error3:
-	error1:
+	irlap_close(mcs->irlap);
-		return ret;
+error2:
+	kfree_skb(mcs->rx_buff.skb);
+error1:
+	return ret;
 }
 /* Receive callback function.  */
 	usb_set_intfdata(intf, mcs);
 	return 0;
-	error2:
+error2:
-		free_netdev(ndev);
+	free_netdev(ndev);
-	error1:
+error1:
-		return ret;
+	return ret;
 }
 /* The current device is removed, the USB layer tells us to shut down. */

drivers/net/loopback.c+1−0

@@ -146,6 +146,7 @@ static int loopback_dev_init(struct net_device *dev) · 145 unmodified lines
146		146
147	static void loopback_dev_free(struct net_device *dev)	147	static void loopback_dev_free(struct net_device *dev)
148	{	148	{
		149	dev_net(dev)->loopback_dev = NULL;
149	free_percpu(dev->lstats);	150	free_percpu(dev->lstats);
150	free_netdev(dev);	151	free_netdev(dev);
151	}	152	}

drivers/net/netconsole.c+1−4

 			case NETDEV_RELEASE:
 			case NETDEV_JOIN:
 			case NETDEV_UNREGISTER:
-				/*
+				/* rtnl_lock already held
-				 * rtnl_lock already held
 				 * we might sleep in __netpoll_cleanup()
 				 */
 				spin_unlock_irqrestore(&target_list_lock, flags);
-				mutex_lock(&nt->mutex);
 				__netpoll_cleanup(&nt->np);
-				mutex_unlock(&nt->mutex);
 				spin_lock_irqsave(&target_list_lock, flags);
 				dev_put(nt->np.dev);

drivers/net/phy/cicada.c+2−2

@@ -30,9 +30,9 @@ · 29 unmodified lines
30	#include <linux/ethtool.h>	30	#include <linux/ethtool.h>
31	#include <linux/phy.h>	31	#include <linux/phy.h>
32		32
33	#include <asm/io.h>	33	#include <linux/io.h>
34	#include <asm/irq.h>	34	#include <asm/irq.h>
35	#include <asm/uaccess.h>	35	#include <linux/uaccess.h>
36		36
37	/* Cicada Extended Control Register 1 */	37	/* Cicada Extended Control Register 1 */
38	#define MII_CIS8201_EXT_CON1 0x17	38	#define MII_CIS8201_EXT_CON1 0x17

drivers/net/ppp/pptp.c+1−1

@@ -281,7 +281,7 @@ static int pptp_xmit(struct ppp_channel chan, struct sk_buff skb) · 280 unmodified lines
281	nf_reset(skb);	281	nf_reset(skb);
282		282
283	skb->ip_summed = CHECKSUM_NONE;	283	skb->ip_summed = CHECKSUM_NONE;
284	ip_select_ident(iph, &rt->dst, NULL);	284	ip_select_ident(skb, &rt->dst, NULL);
285	ip_send_check(iph);	285	ip_send_check(iph);
286		286
287	ip_local_out(skb);	287	ip_local_out(skb);

drivers/net/slip/slip.c+3−0

 	if (!sl || sl->magic != SLIP_MAGIC || !netif_running(sl->dev))
 		return;
+	spin_lock(&sl->lock);
 	if (sl->xleft <= 0)  {
 		/* Now serial buffer is almost free & we can start
 		 * transmission of another packet */
 		sl->dev->stats.tx_packets++;
 		clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
+		spin_unlock(&sl->lock);
 		sl_unlock(sl);
 		return;
 	}
 	actual = tty->ops->write(tty, sl->xhead, sl->xleft);
 	sl->xleft -= actual;
 	sl->xhead += actual;
+	spin_unlock(&sl->lock);
 }
 static void sl_tx_timeout(struct net_device *dev)

drivers/net/tun.c+8−3

 		INIT_LIST_HEAD(&tun->disabled);
 		err = tun_attach(tun, file, false);
 		if (err < 0)
-			goto err_free_dev;
+			goto err_free_flow;
 		err = register_netdevice(tun->dev);
 		if (err < 0)
-			goto err_free_dev;
+			goto err_detach;
 		if (device_create_file(&tun->dev->dev, &dev_attr_tun_flags) ||
 		    device_create_file(&tun->dev->dev, &dev_attr_owner) ||
 	strcpy(ifr->ifr_name, tun->dev->name);
 	return 0;
- err_free_dev:
+err_detach:
+	tun_detach_all(dev);
+err_free_flow:
+	tun_flow_uninit(tun);
+	security_tun_dev_free_security(tun->security);
+err_free_dev:
 	free_netdev(dev);
 	return err;
 }

drivers/net/usb/cdc_ether.c+42−73

 #include <linux/usb/usbnet.h>
-#if defined(CONFIG_USB_NET_RNDIS_HOST) || defined(CONFIG_USB_NET_RNDIS_HOST_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET_RNDIS_HOST)
 static int is_rndis(struct usb_interface_descriptor *desc)
 {
 	0xa6, 0x07, 0xc0, 0xff, 0xcb, 0x7e, 0x39, 0x2a,
 };
-/*
+/* probes control interface, claims data interface, collects the bulk
- * probes control interface, claims data interface, collects the bulk
  * endpoints, activates data interface (if needed), maybe sets MTU.
  * all pure cdc, except for certain firmware workarounds, and knowing
  * that rndis uses one different rule.
 	struct usb_cdc_mdlm_desc	*desc = NULL;
 	struct usb_cdc_mdlm_detail_desc *detail = NULL;
-	if (sizeof dev->data < sizeof *info)
+	if (sizeof(dev->data) < sizeof(*info))
 		return -EDOM;
 	/* expect strict spec conformance for the descriptors, but
 		 is_activesync(&intf->cur_altsetting->desc) ||
 		 is_wireless_rndis(&intf->cur_altsetting->desc));
-	memset(info, 0, sizeof *info);
+	memset(info, 0, sizeof(*info));
 	info->control = intf;
 	while (len > 3) {
-		if (buf [1] != USB_DT_CS_INTERFACE)
+		if (buf[1] != USB_DT_CS_INTERFACE)
 			goto next_desc;
 		/* use bDescriptorSubType to identify the CDC descriptors.
 		 * in favor of a complicated OID-based RPC scheme doing what
 		 * CDC Ethernet achieves with a simple descriptor.
 		 */
-		switch (buf [2]) {
+		switch (buf[2]) {
 		case USB_CDC_HEADER_TYPE:
 			if (info->header) {
 				dev_dbg(&intf->dev, "extra CDC header\n");
 				goto bad_desc;
 			}
 			info->header = (void *) buf;
-			if (info->header->bLength != sizeof *info->header) {
+			if (info->header->bLength != sizeof(*info->header)) {
 				dev_dbg(&intf->dev, "CDC header len %u\n",
 					info->header->bLength);
 				goto bad_desc;
 				goto bad_desc;
 			}
 			info->u = (void *) buf;
-			if (info->u->bLength != sizeof *info->u) {
+			if (info->u->bLength != sizeof(*info->u)) {
 				dev_dbg(&intf->dev, "CDC union len %u\n",
 					info->u->bLength);
 				goto bad_desc;
 				goto bad_desc;
 			}
 			info->ether = (void *) buf;
-			if (info->ether->bLength != sizeof *info->ether) {
+			if (info->ether->bLength != sizeof(*info->ether)) {
 				dev_dbg(&intf->dev, "CDC ether len %u\n",
 					info->ether->bLength);
 				goto bad_desc;
 			break;
 		}
 next_desc:
-		len -= buf [0];	/* bLength */
+		len -= buf[0];	/* bLength */
-		buf += buf [0];
+		buf += buf[0];
 	}
 	/* Microsoft ActiveSync based and some regular RNDIS devices lack the
 }
 EXPORT_SYMBOL_GPL(usbnet_cdc_unbind);
-/*-------------------------------------------------------------------------
+/* Communications Device Class, Ethernet Control model
- *
- * Communications Device Class, Ethernet Control model
  *
  * Takes two interfaces.  The DATA interface is inactive till an altsetting
  * is selected.  Configuration data includes class descriptors.  There's
  *
  * This should interop with whatever the 2.4 "CDCEther.c" driver
  * (by Brad Hards) talked with, with more functionality.
- *
+ */
- *-------------------------------------------------------------------------*/
 static void dumpspeed(struct usbnet *dev, __le32 *speeds)
 {
 {
 	struct usb_cdc_notification	*event;
-	if (urb->actual_length < sizeof *event)
+	if (urb->actual_length < sizeof(*event))
 		return;
 	/* SPEED_CHANGE can get split into two 8-byte packets */
 	case USB_CDC_NOTIFY_SPEED_CHANGE:	/* tx/rx rates */
 		netif_dbg(dev, timer, dev->net, "CDC: speed change (len %d)\n",
 			  urb->actual_length);
-		if (urb->actual_length != (sizeof *event + 8))
+		if (urb->actual_length != (sizeof(*event) + 8))
 			set_bit(EVENT_STS_SPLIT, &dev->flags);
 		else
 			dumpspeed(dev, (__le32 *) &event[1]);
 static const struct driver_info	cdc_info = {
 	.description =	"CDC Ethernet Device",
 	.flags =	FLAG_ETHER | FLAG_POINTTOPOINT,
-	// .check_connect = cdc_check_connect,
 	.bind =		usbnet_cdc_bind,
 	.unbind =	usbnet_cdc_unbind,
 	.status =	usbnet_cdc_status,
 #define DELL_VENDOR_ID		0x413C
 #define REALTEK_VENDOR_ID	0x0bda
-static const struct usb_device_id	products [] = {
+static const struct usb_device_id	products[] = {
-/*
+/* BLACKLIST !!
- * BLACKLIST !!
  *
  * First blacklist any products that are egregiously nonconformant
  * with the CDC Ethernet specs.  Minor braindamage we cope with; when
 	.driver_info		= 0,
 }, {
 	.match_flags    =   USB_DEVICE_ID_MATCH_INT_INFO
-	          | USB_DEVICE_ID_MATCH_DEVICE,
+			  | USB_DEVICE_ID_MATCH_DEVICE,
 	.idVendor		= 0x04DD,
 	.idProduct		= 0x8007,	/* C-700 */
 	ZAURUS_MASTER_INTERFACE,
 	.driver_info = 0,
 },
-/*
+/* WHITELIST!!!
- * WHITELIST!!!
  *
  * CDC Ether uses two interfaces, not necessarily consecutive.
  * We match the main interface, ignoring the optional device
  */
 {
 	/* ZTE (Vodafone) K3805-Z */
-	.match_flags    =   USB_DEVICE_ID_MATCH_VENDOR
+	USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1003, USB_CLASS_COMM,
-		 | USB_DEVICE_ID_MATCH_PRODUCT
+				      USB_CDC_SUBCLASS_ETHERNET,
-		 | USB_DEVICE_ID_MATCH_INT_INFO,
+				      USB_CDC_PROTO_NONE),
-	.idVendor               = ZTE_VENDOR_ID,
-	.idProduct		= 0x1003,
-	.bInterfaceClass	= USB_CLASS_COMM,
-	.bInterfaceSubClass	= USB_CDC_SUBCLASS_ETHERNET,
-	.bInterfaceProtocol	= USB_CDC_PROTO_NONE,
 	.driver_info = (unsigned long)&wwan_info,
 }, {
 	/* ZTE (Vodafone) K3806-Z */
-	.match_flags    =   USB_DEVICE_ID_MATCH_VENDOR
+	USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1015, USB_CLASS_COMM,
-		 | USB_DEVICE_ID_MATCH_PRODUCT
+				      USB_CDC_SUBCLASS_ETHERNET,
-		 | USB_DEVICE_ID_MATCH_INT_INFO,
+				      USB_CDC_PROTO_NONE),
-	.idVendor               = ZTE_VENDOR_ID,
-	.idProduct		= 0x1015,
-	.bInterfaceClass	= USB_CLASS_COMM,
-	.bInterfaceSubClass	= USB_CDC_SUBCLASS_ETHERNET,
-	.bInterfaceProtocol	= USB_CDC_PROTO_NONE,
 	.driver_info = (unsigned long)&wwan_info,
 }, {
 	/* ZTE (Vodafone) K4510-Z */
-	.match_flags    =   USB_DEVICE_ID_MATCH_VENDOR
+	USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1173, USB_CLASS_COMM,
-		 | USB_DEVICE_ID_MATCH_PRODUCT
+				      USB_CDC_SUBCLASS_ETHERNET,
-		 | USB_DEVICE_ID_MATCH_INT_INFO,
+				      USB_CDC_PROTO_NONE),
-	.idVendor               = ZTE_VENDOR_ID,
-	.idProduct		= 0x1173,
-	.bInterfaceClass	= USB_CLASS_COMM,
-	.bInterfaceSubClass	= USB_CDC_SUBCLASS_ETHERNET,
-	.bInterfaceProtocol	= USB_CDC_PROTO_NONE,
 	.driver_info = (unsigned long)&wwan_info,
 }, {
 	/* ZTE (Vodafone) K3770-Z */
-	.match_flags    =   USB_DEVICE_ID_MATCH_VENDOR
+	USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1177, USB_CLASS_COMM,
-		 | USB_DEVICE_ID_MATCH_PRODUCT
+				      USB_CDC_SUBCLASS_ETHERNET,
-		 | USB_DEVICE_ID_MATCH_INT_INFO,
+				      USB_CDC_PROTO_NONE),
-	.idVendor               = ZTE_VENDOR_ID,
-	.idProduct		= 0x1177,
-	.bInterfaceClass	= USB_CLASS_COMM,
-	.bInterfaceSubClass	= USB_CDC_SUBCLASS_ETHERNET,
-	.bInterfaceProtocol	= USB_CDC_PROTO_NONE,
 	.driver_info = (unsigned long)&wwan_info,
 }, {
 	/* ZTE (Vodafone) K3772-Z */
-	.match_flags    =   USB_DEVICE_ID_MATCH_VENDOR
+	USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1181, USB_CLASS_COMM,
-		 | USB_DEVICE_ID_MATCH_PRODUCT
+				      USB_CDC_SUBCLASS_ETHERNET,
-		 | USB_DEVICE_ID_MATCH_INT_INFO,
+				      USB_CDC_PROTO_NONE),
-	.idVendor               = ZTE_VENDOR_ID,
-	.idProduct		= 0x1181,
-	.bInterfaceClass	= USB_CLASS_COMM,
-	.bInterfaceSubClass	= USB_CDC_SUBCLASS_ETHERNET,
-	.bInterfaceProtocol	= USB_CDC_PROTO_NONE,
 	.driver_info = (unsigned long)&wwan_info,
+}, {
+	/* Telit modules */
+	USB_VENDOR_AND_INTERFACE_INFO(0x1bc7, USB_CLASS_COMM,
+			USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
+	.driver_info = (kernel_ulong_t) &wwan_info,
 }, {
 	USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_ETHERNET,
 			USB_CDC_PROTO_NONE),
 }, {
 	/* Various Huawei modems with a network port like the UMG1831 */
-	.match_flags    =   USB_DEVICE_ID_MATCH_VENDOR
+	USB_VENDOR_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, USB_CLASS_COMM,
-		 | USB_DEVICE_ID_MATCH_INT_INFO,
+				      USB_CDC_SUBCLASS_ETHERNET, 255),
-	.idVendor               = HUAWEI_VENDOR_ID,
-	.bInterfaceClass	= USB_CLASS_COMM,
-	.bInterfaceSubClass	= USB_CDC_SUBCLASS_ETHERNET,
-	.bInterfaceProtocol	= 255,
 	.driver_info = (unsigned long)&wwan_info,
 },
-	{ },		// END
+	{ },		/* END */
 };
 MODULE_DEVICE_TABLE(usb, products);

drivers/net/usb/dm9601.c+1−1

@@ -303,7 +303,7 @@ static void dm9601_set_multicast(struct net_device *net) · 302 unmodified lines
303	rx_ctl \|= 0x02;	303	rx_ctl \|= 0x02;
304	} else if (net->flags & IFF_ALLMULTI \|\|	304	} else if (net->flags & IFF_ALLMULTI \|\|
305	netdev_mc_count(net) > DM_MAX_MCAST) {	305	netdev_mc_count(net) > DM_MAX_MCAST) {
306	rx_ctl \|= 0x04;	306	rx_ctl \|= 0x08;
307	} else if (!netdev_mc_empty(net)) {	307	} else if (!netdev_mc_empty(net)) {
308	struct netdev_hw_addr *ha;	308	struct netdev_hw_addr *ha;
309		309

drivers/net/usb/qmi_wwan.c+1−1

@@ -714,7 +714,7 @@ static const struct usb_device_id products[] = { · 713 unmodified lines
714	{QMI_FIXED_INTF(0x2357, 0x0201, 4)}, /* TP-LINK HSUPA Modem MA180 */	714	{QMI_FIXED_INTF(0x2357, 0x0201, 4)}, /* TP-LINK HSUPA Modem MA180 */
715	{QMI_FIXED_INTF(0x2357, 0x9000, 4)}, /* TP-LINK MA260 */	715	{QMI_FIXED_INTF(0x2357, 0x9000, 4)}, /* TP-LINK MA260 */
716	{QMI_FIXED_INTF(0x1bc7, 0x1200, 5)}, /* Telit LE920 */	716	{QMI_FIXED_INTF(0x1bc7, 0x1200, 5)}, /* Telit LE920 */
717	{QMI_FIXED_INTF(0x1e2d, 0x12d1, 4)}, /* Cinterion PLxx */	717	{QMI_FIXED_INTF(0x1e2d, 0x0060, 4)}, /* Cinterion PLxx */
718		718
719	/* 4. Gobi 1000 devices */	719	/* 4. Gobi 1000 devices */
720	{QMI_GOBI1K_DEVICE(0x05c6, 0x9212)}, /* Acer Gobi Modem Device */	720	{QMI_GOBI1K_DEVICE(0x05c6, 0x9212)}, /* Acer Gobi Modem Device */

drivers/net/usb/usbnet.c+21−6

 	if (num_sgs == 1)
 		return 0;
-	urb->sg = kmalloc(num_sgs * sizeof(struct scatterlist), GFP_ATOMIC);
+	/* reserve one for zero packet */
+	urb->sg = kmalloc((num_sgs + 1) * sizeof(struct scatterlist),
+			  GFP_ATOMIC);
 	if (!urb->sg)
 		return -ENOMEM;
 		if (build_dma_sg(skb, urb) < 0)
 			goto drop;
 	}
-	entry->length = length = urb->transfer_buffer_length;
+	length = urb->transfer_buffer_length;
 	/* don't assume the hardware handles USB_ZERO_PACKET
 	 * NOTE:  strictly conforming cdc-ether devices should expect
 	if (length % dev->maxpacket == 0) {
 		if (!(info->flags & FLAG_SEND_ZLP)) {
 			if (!(info->flags & FLAG_MULTI_PACKET)) {
-				urb->transfer_buffer_length++;
+				length++;
-				if (skb_tailroom(skb)) {
+				if (skb_tailroom(skb) && !urb->num_sgs) {
 					skb->data[skb->len] = 0;
 					__skb_put(skb, 1);
-				}
+				} else if (urb->num_sgs)
+					sg_set_buf(&urb->sg[urb->num_sgs++],
+							dev->padding_pkt, 1);
 			}
 		} else
 			urb->transfer_flags |= URB_ZERO_PACKET;
 	}
+	entry->length = urb->transfer_buffer_length = length;
 	spin_lock_irqsave(&dev->txq.lock, flags);
 	retval = usb_autopm_get_interface_async(dev->intf);
 	usb_kill_urb(dev->interrupt);
 	usb_free_urb(dev->interrupt);
+	kfree(dev->padding_pkt);
 	free_netdev(net);
 }
 	/* initialize max rx_qlen and tx_qlen */
 	usbnet_update_max_qlen(dev);
+	if (dev->can_dma_sg && !(info->flags & FLAG_SEND_ZLP) &&
+		!(info->flags & FLAG_MULTI_PACKET)) {
+		dev->padding_pkt = kzalloc(1, GFP_KERNEL);
+		if (!dev->padding_pkt)
+			goto out4;
+	}
 	status = register_netdev (net);
 	if (status)
-		goto out4;
+		goto out5;
 	netif_info(dev, probe, dev->net,
 		   "register '%s' at usb-%s-%s, %s, %pM\n",
 		   udev->dev.driver->name,
 	return 0;
+out5:
+	kfree(dev->padding_pkt);
 out4:
 	usb_free_urb(dev->interrupt);
 out3:

drivers/net/vxlan.c+24−25

 	struct net_device *dev;
 	struct net *net = sock_net(sk);
 	sa_family_t sa_family = sk->sk_family;
-	u16 port = htons(inet_sk(sk)->inet_sport);
+	__be16 port = inet_sk(sk)->inet_sport;
 	rcu_read_lock();
 	for_each_netdev_rcu(net, dev) {
 	struct net_device *dev;
 	struct net *net = sock_net(sk);
 	sa_family_t sa_family = sk->sk_family;
-	u16 port = htons(inet_sk(sk)->inet_sport);
+	__be16 port = inet_sk(sk)->inet_sport;
 	rcu_read_lock();
 	for_each_netdev_rcu(net, dev) {
 	spin_lock(&vn->sock_lock);
 	hlist_del_rcu(&vs->hlist);
-	smp_wmb();
+	rcu_assign_sk_user_data(vs->sock->sk, NULL);
-	vs->sock->sk->sk_user_data = NULL;
 	vxlan_notify_del_rx_port(sk);
 	spin_unlock(&vn->sock_lock);
 	port = inet_sk(sk)->inet_sport;
-	smp_read_barrier_depends();
+	vs = rcu_dereference_sk_user_data(sk);
-	vs = (struct vxlan_sock *)sk->sk_user_data;
 	if (!vs)
 		goto drop;
 };
 /* Calls the ndo_add_vxlan_port of the caller in order to
- * supply the listening VXLAN udp ports.
+ * supply the listening VXLAN udp ports. Callers are expected
+ * to implement the ndo_add_vxlan_port.
  */
 void vxlan_get_rx_port(struct net_device *dev)
 {
 	struct net *net = dev_net(dev);
 	struct vxlan_net *vn = net_generic(net, vxlan_net_id);
 	sa_family_t sa_family;
-	u16 port;
+	__be16 port;
-	int i;
+	unsigned int i;
-	if (!dev || !dev->netdev_ops || !dev->netdev_ops->ndo_add_vxlan_port)
-		return;
 	spin_lock(&vn->sock_lock);
 	for (i = 0; i < PORT_HASH_SIZE; ++i) {
-		hlist_for_each_entry_rcu(vs, vs_head(net, i), hlist) {
+		hlist_for_each_entry_rcu(vs, &vn->sock_list[i], hlist) {
-			port = htons(inet_sk(vs->sock->sk)->inet_sport);
+			port = inet_sk(vs->sock->sk)->inet_sport;
 			sa_family = vs->sock->sk->sk_family;
 			dev->netdev_ops->ndo_add_vxlan_port(dev, sa_family,
 							    port);
 	atomic_set(&vs->refcnt, 1);
 	vs->rcv = rcv;
 	vs->data = data;
-	smp_wmb();
+	rcu_assign_sk_user_data(vs->sock->sk, vs);
-	vs->sock->sk->sk_user_data = vs;
 	spin_lock(&vn->sock_lock);
 	hlist_add_head_rcu(&vs->hlist, vs_head(net, port));
 	SET_ETHTOOL_OPS(dev, &vxlan_ethtool_ops);
-	/* create an fdb entry for default destination */
+	/* create an fdb entry for a valid default destination */
-	err = vxlan_fdb_create(vxlan, all_zeros_mac,
+	if (!vxlan_addr_any(&vxlan->default_dst.remote_ip)) {
-			       &vxlan->default_dst.remote_ip,
+		err = vxlan_fdb_create(vxlan, all_zeros_mac,
-			       NUD_REACHABLE|NUD_PERMANENT,
+				       &vxlan->default_dst.remote_ip,
-			       NLM_F_EXCL|NLM_F_CREATE,
+				       NUD_REACHABLE|NUD_PERMANENT,
-			       vxlan->dst_port, vxlan->default_dst.remote_vni,
+				       NLM_F_EXCL|NLM_F_CREATE,
-			       vxlan->default_dst.remote_ifindex, NTF_SELF);
+				       vxlan->dst_port,
-	if (err)
+				       vxlan->default_dst.remote_vni,
-		return err;
+				       vxlan->default_dst.remote_ifindex,
+				       NTF_SELF);
+		if (err)
+			return err;
+	}
 	err = register_netdevice(dev);
 	if (err) {

drivers/net/wireless/ath/ath9k/recv.c+0−7

@@ -1269,13 +1269,6 @@ static void ath9k_antenna_check(struct ath_softc *sc, · 1268 unmodified lines
1269	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB))	1269	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB))
1270	return;	1270	return;
1271		1271
1272	/*
1273	* All MPDUs in an aggregate will use the same LNA
1274	* as the first MPDU.
1275	*/
1276	if (rs->rs_isaggr && !rs->rs_firstaggr)
1277	return;
1278
1279	/*	1272	/*
1280	* Change the default rx antenna if rx diversity	1273	* Change the default rx antenna if rx diversity
1281	* chooses the other antenna 3 times in a row.	1274	* chooses the other antenna 3 times in a row.

drivers/net/wireless/ath/ath9k/xmit.c+14−3

 	tbf->bf_buf_addr = bf->bf_buf_addr;
 	memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
 	tbf->bf_state = bf->bf_state;
+	tbf->bf_state.stale = false;
 	return tbf;
 }
 		      u16 tid, u16 *ssn)
 {
 	struct ath_atx_tid *txtid;
+	struct ath_txq *txq;
 	struct ath_node *an;
 	u8 density;
 	an = (struct ath_node *)sta->drv_priv;
 	txtid = ATH_AN_2_TID(an, tid);
+	txq = txtid->ac->txq;
+	ath_txq_lock(sc, txq);
 	/* update ampdu factor/density, they may have changed. This may happen
 	 * in HT IBSS when a beacon with HT-info is received after the station
 	memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
 	txtid->baw_head = txtid->baw_tail = 0;
+	ath_txq_unlock_complete(sc, txq);
 	return 0;
 }
 			__skb_unlink(bf->bf_mpdu, tid_q);
 			list_add_tail(&bf->list, &bf_q);
 			ath_set_rates(tid->an->vif, tid->an->sta, bf);
-			ath_tx_addto_baw(sc, tid, bf);
+			if (bf_isampdu(bf)) {
-			bf->bf_state.bf_type &= ~BUF_AGGR;
+				ath_tx_addto_baw(sc, tid, bf);
+				bf->bf_state.bf_type &= ~BUF_AGGR;
+			}
 			if (bf_tail)
 				bf_tail->bf_next = bf;
 			if (bf_is_ampdu_not_probing(bf))
 				txq->axq_ampdu_depth++;
-			bf = bf->bf_lastbf->bf_next;
+			bf_last = bf->bf_lastbf;
+			bf = bf_last->bf_next;
+			bf_last->bf_next = NULL;
 		}
 	}
 }

drivers/net/wireless/brcm80211/Kconfig+2−2

@@ -28,7 +28,7 @@ config BRCMFMAC · 27 unmodified lines
28		28
29	config BRCMFMAC_SDIO	29	config BRCMFMAC_SDIO
30	bool "SDIO bus interface support for FullMAC driver"	30	bool "SDIO bus interface support for FullMAC driver"
31	depends on MMC	31	depends on (MMC = y \|\| MMC = BRCMFMAC)
32	depends on BRCMFMAC	32	depends on BRCMFMAC
33	select FW_LOADER	33	select FW_LOADER
34	default y	34	default y
@@ -39,7 +39,7 @@ config BRCMFMAC_SDIO · 4 unmodified lines
39		39
40	config BRCMFMAC_USB	40	config BRCMFMAC_USB
41	bool "USB bus interface support for FullMAC driver"	41	bool "USB bus interface support for FullMAC driver"
42	depends on USB	42	depends on (USB = y \|\| USB = BRCMFMAC)
43	depends on BRCMFMAC	43	depends on BRCMFMAC
44	select FW_LOADER	44	select FW_LOADER
45	---help---	45	---help---

drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c+13−15

 static int brcmf_sdio_pd_probe(struct platform_device *pdev)
 {
-	int ret;
 	brcmf_dbg(SDIO, "Enter\n");
 	brcmfmac_sdio_pdata = pdev->dev.platform_data;
 	if (brcmfmac_sdio_pdata->power_on)
 		brcmfmac_sdio_pdata->power_on();
-	ret = sdio_register_driver(&brcmf_sdmmc_driver);
+	return 0;
-	if (ret)
-		brcmf_err("sdio_register_driver failed: %d\n", ret);
-	return ret;
 }
 static int brcmf_sdio_pd_remove(struct platform_device *pdev)
 	}
 };
+void brcmf_sdio_register(void)
+{
+	int ret;
+	ret = sdio_register_driver(&brcmf_sdmmc_driver);
+	if (ret)
+		brcmf_err("sdio_register_driver failed: %d\n", ret);
+}
 void brcmf_sdio_exit(void)
 {
 	brcmf_dbg(SDIO, "Enter\n");
 		sdio_unregister_driver(&brcmf_sdmmc_driver);
 }
-void brcmf_sdio_init(void)
+void __init brcmf_sdio_init(void)
 {
 	int ret;
 	brcmf_dbg(SDIO, "Enter\n");
 	ret = platform_driver_probe(&brcmf_sdio_pd, brcmf_sdio_pd_probe);
-	if (ret == -ENODEV) {
+	if (ret == -ENODEV)
-		brcmf_dbg(SDIO, "No platform data available, registering without.\n");
+		brcmf_dbg(SDIO, "No platform data available.\n");
-		ret = sdio_register_driver(&brcmf_sdmmc_driver);
-	}
-	if (ret)
-		brcmf_err("driver registration failed: %d\n", ret);
 }

drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h+2−1

 #ifdef CONFIG_BRCMFMAC_SDIO
 extern void brcmf_sdio_exit(void);
 extern void brcmf_sdio_init(void);
+extern void brcmf_sdio_register(void);
 #endif
 #ifdef CONFIG_BRCMFMAC_USB
 extern void brcmf_usb_exit(void);
-extern void brcmf_usb_init(void);
+extern void brcmf_usb_register(void);
 #endif
 #endif				/* _BRCMF_BUS_H_ */

drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c+8−6

 	return bus->chip << 4 | bus->chiprev;
 }
-static void brcmf_driver_init(struct work_struct *work)
+static void brcmf_driver_register(struct work_struct *work)
 {
-	brcmf_debugfs_init();
 #ifdef CONFIG_BRCMFMAC_SDIO
-	brcmf_sdio_init();
+	brcmf_sdio_register();
 #endif
 #ifdef CONFIG_BRCMFMAC_USB
-	brcmf_usb_init();
+	brcmf_usb_register();
 #endif
 }
-static DECLARE_WORK(brcmf_driver_work, brcmf_driver_init);
+static DECLARE_WORK(brcmf_driver_work, brcmf_driver_register);
 static int __init brcmfmac_module_init(void)
 {
+	brcmf_debugfs_init();
+#ifdef CONFIG_BRCMFMAC_SDIO
+	brcmf_sdio_init();
+#endif
 	if (!schedule_work(&brcmf_driver_work))
 		return -EBUSY;

drivers/net/wireless/brcm80211/brcmfmac/usb.c+1−1

@@ -1539,7 +1539,7 @@ void brcmf_usb_exit(void) · 1538 unmodified lines
1539	brcmf_release_fw(&fw_image_list);	1539	brcmf_release_fw(&fw_image_list);
1540	}	1540	}
1541		1541
1542	void brcmf_usb_init(void)	1542	void brcmf_usb_register(void)
1543	{	1543	{
1544	brcmf_dbg(USB, "Enter\n");	1544	brcmf_dbg(USB, "Enter\n");
1545	INIT_LIST_HEAD(&fw_image_list);	1545	INIT_LIST_HEAD(&fw_image_list);

drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c+4−0

 	if (err != 0)
 		brcms_err(wl->wlc->hw->d11core, "%s: brcms_up() returned %d\n",
 			  __func__, err);
+	bcma_core_pci_power_save(wl->wlc->hw->d11core->bus, true);
 	return err;
 }
 		return;
 	}
+	bcma_core_pci_power_save(wl->wlc->hw->d11core->bus, false);
 	/* put driver in down state */
 	spin_lock_bh(&wl->lock);
 	brcms_down(wl);

drivers/net/wireless/cw1200/cw1200_spi.c+13−3

 	struct cw1200_common	*core;
 	const struct cw1200_platform_data_spi *pdata;
 	spinlock_t		lock; /* Serialize all bus operations */
+	wait_queue_head_t       wq;
 	int claimed;
 };
 {
 	unsigned long flags;
+	DECLARE_WAITQUEUE(wait, current);
 	might_sleep();
+	add_wait_queue(&self->wq, &wait);
 	spin_lock_irqsave(&self->lock, flags);
 	while (1) {
 		set_current_state(TASK_UNINTERRUPTIBLE);
 	set_current_state(TASK_RUNNING);
 	self->claimed = 1;
 	spin_unlock_irqrestore(&self->lock, flags);
+	remove_wait_queue(&self->wq, &wait);
 	return;
 }
 	spin_lock_irqsave(&self->lock, flags);
 	self->claimed = 0;
 	spin_unlock_irqrestore(&self->lock, flags);
+	wake_up(&self->wq);
 	return;
 }
 	pr_debug("SW IRQ subscribe\n");
-	ret = request_any_context_irq(self->func->irq, cw1200_spi_irq_handler,
+	ret = request_threaded_irq(self->func->irq, NULL,
-				      IRQF_TRIGGER_HIGH,
+				   cw1200_spi_irq_handler,
-				      "cw1200_wlan_irq", self);
+				   IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+				   "cw1200_wlan_irq", self);
 	if (WARN_ON(ret < 0))
 		goto exit;
 	spi_set_drvdata(func, self);
+	init_waitqueue_head(&self->wq);
 	status = cw1200_spi_irq_subscribe(self);
 	status = cw1200_core_probe(&cw1200_spi_hwbus_ops,

drivers/net/wireless/mwifiex/11n_aggr.c+2−1

  */
 int
 mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,
-			  struct mwifiex_ra_list_tbl *pra_list, int headroom,
+			  struct mwifiex_ra_list_tbl *pra_list,
 			  int ptrindex, unsigned long ra_list_flags)
 			  __releases(&priv->wmm.ra_list_spinlock)
 {
 	int pad = 0, ret;
 	struct mwifiex_tx_param tx_param;
 	struct txpd *ptx_pd = NULL;
+	int headroom = adapter->iface_type == MWIFIEX_USB ? 0 : INTF_HEADER_LEN;
 	skb_src = skb_peek(&pra_list->skb_head);
 	if (!skb_src) {

drivers/net/wireless/mwifiex/11n_aggr.h+1−1

@@ -26,7 +26,7 @@ · 25 unmodified lines
26	int mwifiex_11n_deaggregate_pkt(struct mwifiex_private *priv,	26	int mwifiex_11n_deaggregate_pkt(struct mwifiex_private *priv,
27	struct sk_buff *skb);	27	struct sk_buff *skb);
28	int mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,	28	int mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,
29	struct mwifiex_ra_list_tbl *ptr, int headroom,	29	struct mwifiex_ra_list_tbl *ptr,
30	int ptr_index, unsigned long flags)	30	int ptr_index, unsigned long flags)
31	__releases(&priv->wmm.ra_list_spinlock);	31	__releases(&priv->wmm.ra_list_spinlock);
32		32

drivers/net/wireless/mwifiex/cmdevt.c+2−3

 	uint32_t conditions = le32_to_cpu(phs_cfg->params.hs_config.conditions);
 	if (phs_cfg->action == cpu_to_le16(HS_ACTIVATE) &&
-	    adapter->iface_type == MWIFIEX_SDIO) {
+	    adapter->iface_type != MWIFIEX_USB) {
 		mwifiex_hs_activated_event(priv, true);
 		return 0;
 	} else {
 	}
 	if (conditions != HS_CFG_CANCEL) {
 		adapter->is_hs_configured = true;
-		if (adapter->iface_type == MWIFIEX_USB ||
+		if (adapter->iface_type == MWIFIEX_USB)
-		    adapter->iface_type == MWIFIEX_PCIE)
 			mwifiex_hs_activated_event(priv, true);
 	} else {
 		adapter->is_hs_configured = false;

drivers/net/wireless/mwifiex/usb.c+0−7

 	 */
 	adapter->is_suspended = true;
-	for (i = 0; i < adapter->priv_num; i++)
-		netif_carrier_off(adapter->priv[i]->netdev);
 	if (atomic_read(&card->rx_cmd_urb_pending) && card->rx_cmd.urb)
 		usb_kill_urb(card->rx_cmd.urb);
 						  MWIFIEX_RX_CMD_BUF_SIZE);
 	}
-	for (i = 0; i < adapter->priv_num; i++)
-		if (adapter->priv[i]->media_connected)
-			netif_carrier_on(adapter->priv[i]->netdev);
 	/* Disable Host Sleep */
 	if (adapter->hs_activated)
 		mwifiex_cancel_hs(mwifiex_get_priv(adapter,

drivers/net/wireless/mwifiex/wmm.c+1−2

 		if (enable_tx_amsdu && mwifiex_is_amsdu_allowed(priv, tid) &&
 		    mwifiex_is_11n_aggragation_possible(priv, ptr,
 							adapter->tx_buf_size))
-			mwifiex_11n_aggregate_pkt(priv, ptr, INTF_HEADER_LEN,
+			mwifiex_11n_aggregate_pkt(priv, ptr, ptr_index, flags);
-						  ptr_index, flags);
 			/* ra_list_spinlock has been freed in
 			   mwifiex_11n_aggregate_pkt() */
 		else

drivers/net/wireless/p54/p54usb.c+2−0

 	{USB_DEVICE(0x06a9, 0x000e)},	/* Westell 802.11g USB (A90-211WG-01) */
 	{USB_DEVICE(0x06b9, 0x0121)},	/* Thomson SpeedTouch 121g */
 	{USB_DEVICE(0x0707, 0xee13)},   /* SMC 2862W-G version 2 */
+	{USB_DEVICE(0x07aa, 0x0020)},	/* Corega WLUSB2GTST USB */
 	{USB_DEVICE(0x0803, 0x4310)},	/* Zoom 4410a */
 	{USB_DEVICE(0x083a, 0x4521)},   /* Siemens Gigaset USB Adapter 54 version 2 */
 	{USB_DEVICE(0x083a, 0x4531)},	/* T-Com Sinus 154 data II */
 	if (err) {
 		dev_err(&priv->udev->dev, "(p54usb) cannot load firmware %s "
 					  "(%d)!\n", p54u_fwlist[i].fw, err);
+		usb_put_dev(udev);
 	}
 	return err;

drivers/net/wireless/rt2x00/rt2800lib.c+6−5

 		     rt2800_init_registers(rt2x00dev)))
 		return -EIO;
+	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
+		return -EIO;
 	/*
 	 * Send signal to firmware during boot time.
 	 */
 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
-	if (rt2x00_is_usb(rt2x00dev)) {
+	if (rt2x00_is_usb(rt2x00dev))
 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
-		rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
+	rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
-	}
 	msleep(1);
-	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
+	if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
-		     rt2800_wait_bbp_ready(rt2x00dev)))
 		return -EIO;
 	rt2800_init_bbp(rt2x00dev);

drivers/net/wireless/rtl818x/rtl8187/dev.c+10−5

 		skb_queue_tail(&priv->rx_queue, skb);
 		usb_anchor_urb(entry, &priv->anchored);
 		ret = usb_submit_urb(entry, GFP_KERNEL);
+		usb_put_urb(entry);
 		if (ret) {
 			skb_unlink(skb, &priv->rx_queue);
 			usb_unanchor_urb(entry);
 			goto err;
 		}
-		usb_free_urb(entry);
 	}
 	return ret;
 err:
-	usb_free_urb(entry);
 	kfree_skb(skb);
 	usb_kill_anchored_urbs(&priv->anchored);
 	return ret;
 				  (RETRY_COUNT << 8  /* short retry limit */) |
 				  (RETRY_COUNT << 0  /* long retry limit */) |
 				  (7 << 21 /* MAX TX DMA */));
-		rtl8187_init_urbs(dev);
+		ret = rtl8187_init_urbs(dev);
-		rtl8187b_init_status_urb(dev);
+		if (ret)
+			goto rtl8187_start_exit;
+		ret = rtl8187b_init_status_urb(dev);
+		if (ret)
+			usb_kill_anchored_urbs(&priv->anchored);
 		goto rtl8187_start_exit;
 	}
 	rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
 	rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
-	rtl8187_init_urbs(dev);
+	ret = rtl8187_init_urbs(dev);
+	if (ret)
+		goto rtl8187_start_exit;
 	reg = RTL818X_RX_CONF_ONLYERLPKT |
 	      RTL818X_RX_CONF_RX_AUTORESETPHY |

drivers/net/wireless/rtlwifi/wifi.h+1−1

@@ -2057,7 +2057,7 @@ struct rtl_priv { · 2056 unmodified lines
2057	that it points to the data allocated	2057	that it points to the data allocated
2058	beyond this structure like:	2058	beyond this structure like:
2059	rtl_pci_priv or rtl_usb_priv */	2059	rtl_pci_priv or rtl_usb_priv */
2060	u8 priv[0];	2060	u8 priv[0] __aligned(sizeof(void *));
2061	};	2061	};
2062		2062
2063	#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))	2063	#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))

drivers/net/xen-netback/common.h+1−0

@@ -184,6 +184,7 @@ int xenvif_connect(struct xenvif *vif, unsigned long tx_ring_ref, · 183 unmodified lines
184	unsigned long rx_ring_ref, unsigned int tx_evtchn,	184	unsigned long rx_ring_ref, unsigned int tx_evtchn,
185	unsigned int rx_evtchn);	185	unsigned int rx_evtchn);
186	void xenvif_disconnect(struct xenvif *vif);	186	void xenvif_disconnect(struct xenvif *vif);
		187	void xenvif_free(struct xenvif *vif);
187		188
188	int xenvif_xenbus_init(void);	189	int xenvif_xenbus_init(void);
189	void xenvif_xenbus_fini(void);	190	void xenvif_xenbus_fini(void);

drivers/net/xen-netback/interface.c+11−17

 	}
 	netdev_dbg(dev, "Successfully created xenvif\n");
+	__module_get(THIS_MODULE);
 	return vif;
 }
 	if (vif->tx_irq)
 		return 0;
-	__module_get(THIS_MODULE);
 	err = xenvif_map_frontend_rings(vif, tx_ring_ref, rx_ring_ref);
 	if (err < 0)
 		goto err;
 	init_waitqueue_head(&vif->wq);
 	vif->task = kthread_create(xenvif_kthread,
-				   (void *)vif, vif->dev->name);
+				   (void *)vif, "%s", vif->dev->name);
 	if (IS_ERR(vif->task)) {
 		pr_warn("Could not allocate kthread for %s\n", vif->dev->name);
 		err = PTR_ERR(vif->task);
 void xenvif_disconnect(struct xenvif *vif)
 {
-	/* Disconnect funtion might get called by generic framework
-	 * even before vif connects, so we need to check if we really
-	 * need to do a module_put.
-	 */
-	int need_module_put = 0;
 	if (netif_carrier_ok(vif->dev))
 		xenvif_carrier_off(vif);
 			unbind_from_irqhandler(vif->tx_irq, vif);
 			unbind_from_irqhandler(vif->rx_irq, vif);
 		}
-		/* vif->irq is valid, we had a module_get in
+		vif->tx_irq = 0;
-		 * xenvif_connect.
-		 */
-		need_module_put = 1;
 	}
 	if (vif->task)
 		kthread_stop(vif->task);
+	xenvif_unmap_frontend_rings(vif);
+}
+void xenvif_free(struct xenvif *vif)
+{
 	netif_napi_del(&vif->napi);
 	unregister_netdev(vif->dev);
-	xenvif_unmap_frontend_rings(vif);
 	free_netdev(vif->dev);
-	if (need_module_put)
+	module_put(THIS_MODULE);
-		module_put(THIS_MODULE);
 }

drivers/net/xen-netback/netback.c+64−30

 	return false;
 }
+struct xenvif_count_slot_state {
+	unsigned long copy_off;
+	bool head;
+};
+unsigned int xenvif_count_frag_slots(struct xenvif *vif,
+				     unsigned long offset, unsigned long size,
+				     struct xenvif_count_slot_state *state)
+{
+	unsigned count = 0;
+	offset &= ~PAGE_MASK;
+	while (size > 0) {
+		unsigned long bytes;
+		bytes = PAGE_SIZE - offset;
+		if (bytes > size)
+			bytes = size;
+		if (start_new_rx_buffer(state->copy_off, bytes, state->head)) {
+			count++;
+			state->copy_off = 0;
+		}
+		if (state->copy_off + bytes > MAX_BUFFER_OFFSET)
+			bytes = MAX_BUFFER_OFFSET - state->copy_off;
+		state->copy_off += bytes;
+		offset += bytes;
+		size -= bytes;
+		if (offset == PAGE_SIZE)
+			offset = 0;
+		state->head = false;
+	}
+	return count;
+}
 /*
  * Figure out how many ring slots we're going to need to send @skb to
  * the guest. This function is essentially a dry run of
  */
 unsigned int xenvif_count_skb_slots(struct xenvif *vif, struct sk_buff *skb)
 {
+	struct xenvif_count_slot_state state;
 	unsigned int count;
-	int i, copy_off;
+	unsigned char *data;
+	unsigned i;
-	count = DIV_ROUND_UP(skb_headlen(skb), PAGE_SIZE);
+	state.head = true;
+	state.copy_off = 0;
-	copy_off = skb_headlen(skb) % PAGE_SIZE;
+	/* Slot for the first (partial) page of data. */
+	count = 1;
+	/* Need a slot for the GSO prefix for GSO extra data? */
 	if (skb_shinfo(skb)->gso_size)
 		count++;
-	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+	data = skb->data;
-		unsigned long size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
+	while (data < skb_tail_pointer(skb)) {
-		unsigned long offset = skb_shinfo(skb)->frags[i].page_offset;
+		unsigned long offset = offset_in_page(data);
-		unsigned long bytes;
+		unsigned long size = PAGE_SIZE - offset;
-		offset &= ~PAGE_MASK;
-		while (size > 0) {
-			BUG_ON(offset >= PAGE_SIZE);
-			BUG_ON(copy_off > MAX_BUFFER_OFFSET);
-			bytes = PAGE_SIZE - offset;
-			if (bytes > size)
-				bytes = size;
-			if (start_new_rx_buffer(copy_off, bytes, 0)) {
+		if (data + size > skb_tail_pointer(skb))
-				count++;
+			size = skb_tail_pointer(skb) - data;
-				copy_off = 0;
-			}
-			if (copy_off + bytes > MAX_BUFFER_OFFSET)
+		count += xenvif_count_frag_slots(vif, offset, size, &state);
-				bytes = MAX_BUFFER_OFFSET - copy_off;
-			copy_off += bytes;
+		data += size;
+	}
-			offset += bytes;
+	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
-			size -= bytes;
+		unsigned long size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
+		unsigned long offset = skb_shinfo(skb)->frags[i].page_offset;
-			if (offset == PAGE_SIZE)
+		count += xenvif_count_frag_slots(vif, offset, size, &state);
-				offset = 0;
-		}
 	}
 	return count;
 }

drivers/net/xen-netback/xenbus.c+123−28

@@ -24,6 +24,12 @@ · 23 unmodified lines
24	struct backend_info {	24	struct backend_info {
25	struct xenbus_device *dev;	25	struct xenbus_device *dev;
26	struct xenvif *vif;	26	struct xenvif *vif;
		27
		28	/* This is the state that will be reflected in xenstore when any
		29	* active hotplug script completes.
		30	*/
		31	enum xenbus_state state;
		32
27	enum xenbus_state frontend_state;	33	enum xenbus_state frontend_state;
28	struct xenbus_watch hotplug_status_watch;	34	struct xenbus_watch hotplug_status_watch;
29	u8 have_hotplug_status_watch:1;	35	u8 have_hotplug_status_watch:1;
@@ -42,7 +48,7 @@ static int netback_remove(struct xenbus_device *dev) · 12 unmodified lines
42	if (be->vif) {	48	if (be->vif) {
43	kobject_uevent(&dev->dev.kobj, KOBJ_OFFLINE);	49	kobject_uevent(&dev->dev.kobj, KOBJ_OFFLINE);
44	xenbus_rm(XBT_NIL, dev->nodename, "hotplug-status");	50	xenbus_rm(XBT_NIL, dev->nodename, "hotplug-status");
45	xenvif_disconnect(be->vif);	51	xenvif_free(be->vif);
46	be->vif = NULL;	52	be->vif = NULL;
47	}	53	}
48	kfree(be);	54	kfree(be);
@@ -136,6 +142,8 @@ static int netback_probe(struct xenbus_device *dev, · 87 unmodified lines
136	if (err)	142	if (err)
137	goto fail;	143	goto fail;
138		144
		145	be->state = XenbusStateInitWait;
		146
139	/* This kicks hotplug scripts, so do it immediately. */	147	/* This kicks hotplug scripts, so do it immediately. */
140	backend_create_xenvif(be);	148	backend_create_xenvif(be);
141		149
@@ -208,15 +216,113 @@ static void backend_create_xenvif(struct backend_info *be) · 66 unmodified lines
208	kobject_uevent(&dev->dev.kobj, KOBJ_ONLINE);	216	kobject_uevent(&dev->dev.kobj, KOBJ_ONLINE);
209	}	217	}
210		218
		219	static void backend_disconnect(struct backend_info *be)
		220	{
		221	if (be->vif)
		222	xenvif_disconnect(be->vif);
		223	}
211		224
212	static void disconnect_backend(struct xenbus_device *dev)	225	static void backend_connect(struct backend_info *be)
213	{	226	{
214	struct backend_info *be = dev_get_drvdata(&dev->dev);	227	if (be->vif)
		228	connect(be);
		229	}
215		230
216	if (be->vif) {	231	static inline void backend_switch_state(struct backend_info *be,
217	xenbus_rm(XBT_NIL, dev->nodename, "hotplug-status");	232	enum xenbus_state state)
218	xenvif_disconnect(be->vif);	233	{
219	be->vif = NULL;	234	struct xenbus_device *dev = be->dev;
		235
		236	pr_debug("%s -> %s\n", dev->nodename, xenbus_strstate(state));
		237	be->state = state;
		238
		239	/* If we are waiting for a hotplug script then defer the
		240	* actual xenbus state change.
		241	*/
		242	if (!be->have_hotplug_status_watch)
		243	xenbus_switch_state(dev, state);
		244	}
		245
		246	/* Handle backend state transitions:
		247	*
		248	* The backend state starts in InitWait and the following transitions are
		249	* allowed.
		250	*
		251	* InitWait -> Connected
		252	*
		253	* ^ \ \|
		254	* \| \ \|
		255	* \| \ \|
		256	* \| \ \|
		257	* \| \ \|
		258	* \| \ \|
		259	* \| V V
		260	*
		261	* Closed <-> Closing
		262	*
		263	* The state argument specifies the eventual state of the backend and the
		264	* function transitions to that state via the shortest path.
		265	*/
		266	static void set_backend_state(struct backend_info *be,
		267	enum xenbus_state state)
		268	{
		269	while (be->state != state) {
		270	switch (be->state) {
		271	case XenbusStateClosed:
		272	switch (state) {
		273	case XenbusStateInitWait:
		274	case XenbusStateConnected:
		275	pr_info("%s: prepare for reconnect\n",
		276	be->dev->nodename);
		277	backend_switch_state(be, XenbusStateInitWait);
		278	break;
		279	case XenbusStateClosing:
		280	backend_switch_state(be, XenbusStateClosing);
		281	break;
		282	default:
		283	BUG();
		284	}
		285	break;
		286	case XenbusStateInitWait:
		287	switch (state) {
		288	case XenbusStateConnected:
		289	backend_connect(be);
		290	backend_switch_state(be, XenbusStateConnected);
		291	break;
		292	case XenbusStateClosing:
		293	case XenbusStateClosed:
		294	backend_switch_state(be, XenbusStateClosing);
		295	break;
		296	default:
		297	BUG();
		298	}
		299	break;
		300	case XenbusStateConnected:
		301	switch (state) {
		302	case XenbusStateInitWait:
		303	case XenbusStateClosing:
		304	case XenbusStateClosed:
		305	backend_disconnect(be);
		306	backend_switch_state(be, XenbusStateClosing);
		307	break;
		308	default:
		309	BUG();
		310	}
		311	break;
		312	case XenbusStateClosing:
		313	switch (state) {
		314	case XenbusStateInitWait:
		315	case XenbusStateConnected:
		316	case XenbusStateClosed:
		317	backend_switch_state(be, XenbusStateClosed);
		318	break;
		319	default:
		320	BUG();
		321	}
		322	break;
		323	default:
		324	BUG();
		325	}
220	}	326	}
221	}	327	}
222		328
@@ -228,42 +334,33 @@ static void frontend_changed(struct xenbus_device *dev, · 5 unmodified lines
228	{	334	{
229	struct backend_info *be = dev_get_drvdata(&dev->dev);	335	struct backend_info *be = dev_get_drvdata(&dev->dev);
230		336
231	pr_debug("frontend state %s\n", xenbus_strstate(frontend_state));	337	pr_debug("%s -> %s\n", dev->otherend, xenbus_strstate(frontend_state));
232		338
233	be->frontend_state = frontend_state;	339	be->frontend_state = frontend_state;
234		340
235	switch (frontend_state) {	341	switch (frontend_state) {
236	case XenbusStateInitialising:	342	case XenbusStateInitialising:
237	if (dev->state == XenbusStateClosed) {	343	set_backend_state(be, XenbusStateInitWait);
238	pr_info("%s: prepare for reconnect\n", dev->nodename);
239	xenbus_switch_state(dev, XenbusStateInitWait);
240	}
241	break;	344	break;
242		345
243	case XenbusStateInitialised:	346	case XenbusStateInitialised:
244	break;	347	break;
245		348
246	case XenbusStateConnected:	349	case XenbusStateConnected:
247	if (dev->state == XenbusStateConnected)	350	set_backend_state(be, XenbusStateConnected);
248	break;
249	backend_create_xenvif(be);
250	if (be->vif)
251	connect(be);
252	break;	351	break;
253		352
254	case XenbusStateClosing:	353	case XenbusStateClosing:
255	if (be->vif)	354	set_backend_state(be, XenbusStateClosing);
256	kobject_uevent(&dev->dev.kobj, KOBJ_OFFLINE);
257	disconnect_backend(dev);
258	xenbus_switch_state(dev, XenbusStateClosing);
259	break;	355	break;
260		356
261	case XenbusStateClosed:	357	case XenbusStateClosed:
262	xenbus_switch_state(dev, XenbusStateClosed);	358	set_backend_state(be, XenbusStateClosed);
263	if (xenbus_dev_is_online(dev))	359	if (xenbus_dev_is_online(dev))
264	break;	360	break;
265	/* fall through if not online */	361	/* fall through if not online */
266	case XenbusStateUnknown:	362	case XenbusStateUnknown:
		363	set_backend_state(be, XenbusStateClosed);
267	device_unregister(&dev->dev);	364	device_unregister(&dev->dev);
268	break;	365	break;
269		366
@@ -356,7 +453,9 @@ static void hotplug_status_changed(struct xenbus_watch *watch, · 86 unmodified lines
356	if (IS_ERR(str))	453	if (IS_ERR(str))
357	return;	454	return;
358	if (len == sizeof("connected")-1 && !memcmp(str, "connected", len)) {	455	if (len == sizeof("connected")-1 && !memcmp(str, "connected", len)) {
359	xenbus_switch_state(be->dev, XenbusStateConnected);	456	/* Complete any pending state change */
		457	xenbus_switch_state(be->dev, be->state);
		458
360	/* Not interested in this watch anymore. */	459	/* Not interested in this watch anymore. */
361	unregister_hotplug_status_watch(be);	460	unregister_hotplug_status_watch(be);
362	}	461	}
@@ -386,12 +485,8 @@ static void connect(struct backend_info *be) · 23 unmodified lines
386	err = xenbus_watch_pathfmt(dev, &be->hotplug_status_watch,	485	err = xenbus_watch_pathfmt(dev, &be->hotplug_status_watch,
387	hotplug_status_changed,	486	hotplug_status_changed,
388	"%s/%s", dev->nodename, "hotplug-status");	487	"%s/%s", dev->nodename, "hotplug-status");
389	if (err) {	488	if (!err)
390	/* Switch now, since we can't do a watch. */
391	xenbus_switch_state(dev, XenbusStateConnected);
392	} else {
393	be->have_hotplug_status_watch = 1;	489	be->have_hotplug_status_watch = 1;
394	}
395		490
396	netif_wake_queue(be->vif->dev);	491	netif_wake_queue(be->vif->dev);
397	}	492	}

drivers/pci/pci-acpi.c+3−3

 	if (event != ACPI_NOTIFY_DEVICE_WAKE || !pci_dev)
 		return;
+	if (pci_dev->pme_poll)
+		pci_dev->pme_poll = false;
 	if (pci_dev->current_state == PCI_D3cold) {
 		pci_wakeup_event(pci_dev);
 		pm_runtime_resume(&pci_dev->dev);
 	if (pci_dev->pme_support)
 		pci_check_pme_status(pci_dev);
-	if (pci_dev->pme_poll)
-		pci_dev->pme_poll = false;
 	pci_wakeup_event(pci_dev);
 	pm_runtime_resume(&pci_dev->dev);

drivers/pci/pci.c+7−1

 	pci_enable_bridge(dev->bus->self);
-	if (pci_is_enabled(dev))
+	if (pci_is_enabled(dev)) {
+		if (!dev->is_busmaster) {
+			dev_warn(&dev->dev, "driver skip pci_set_master, fix it!\n");
+			pci_set_master(dev);
+		}
 		return;
+	}
 	retval = pci_enable_device(dev);
 	if (retval)
 		dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",

drivers/pinctrl/pinconf.c+2−2

@@ -490,7 +490,7 @@ exit: · 489 unmodified lines
490	* <devicename> <state> <pinname> are values that should match the pinctrl-maps	490	* <devicename> <state> <pinname> are values that should match the pinctrl-maps
491	* <newvalue> reflects the new config and is driver dependant	491	* <newvalue> reflects the new config and is driver dependant
492	*/	492	*/
493	static int pinconf_dbg_config_write(struct file *file,	493	static ssize_t pinconf_dbg_config_write(struct file *file,
494	const char __user user_buf, size_t count, loff_t ppos)	494	const char __user user_buf, size_t count, loff_t ppos)
495	{	495	{
496	struct pinctrl_maps *maps_node;	496	struct pinctrl_maps *maps_node;
@@ -508,7 +508,7 @@ static int pinconf_dbg_config_write(struct file *file, · 11 unmodified lines
508	int i;	508	int i;
509		509
510	/* Get userspace string and assure termination */	510	/* Get userspace string and assure termination */
511	buf_size = min(count, (size_t)(sizeof(buf)-1));	511	buf_size = min(count, sizeof(buf) - 1);
512	if (copy_from_user(buf, user_buf, buf_size))	512	if (copy_from_user(buf, user_buf, buf_size))
513	return -EFAULT;	513	return -EFAULT;
514	buf[buf_size] = 0;	514	buf[buf_size] = 0;

drivers/pinctrl/pinctrl-exynos.c+6−6

drivers/pinctrl/pinctrl-palmas.c+3−2

 		param = pinconf_to_config_param(configs[i]);
 		param_val = pinconf_to_config_argument(configs[i]);
+		if (param == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+			continue;
 		switch (param) {
-		case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
-			return 0;
 		case PIN_CONFIG_BIAS_DISABLE:
 		case PIN_CONFIG_BIAS_PULL_UP:
 		case PIN_CONFIG_BIAS_PULL_DOWN:

drivers/pinctrl/pinctrl-tegra114.c+2−3

  *
  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
  *
- * Arthur:  Pritesh Raithatha <praithatha@nvidia.com>
+ * Author:  Pritesh Raithatha <praithatha@nvidia.com>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
 };
 module_platform_driver(tegra114_pinctrl_driver);
-MODULE_ALIAS("platform:tegra114-pinctrl");
 MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>");
-MODULE_DESCRIPTION("NVIDIA Tegra114 pincontrol driver");
+MODULE_DESCRIPTION("NVIDIA Tegra114 pinctrl driver");
 MODULE_LICENSE("GPL v2");

drivers/regulator/da9063-regulator.c+1−1

@@ -709,7 +709,7 @@ static struct da9063_regulators_pdata *da9063_parse_regulators_dt( · 708 unmodified lines
709	struct of_regulator_match **da9063_reg_matches)	709	struct of_regulator_match **da9063_reg_matches)
710	{	710	{
711	da9063_reg_matches = NULL;	711	da9063_reg_matches = NULL;
712	return PTR_ERR(-ENODEV);	712	return ERR_PTR(-ENODEV);
713	}	713	}
714	#endif	714	#endif
715		715

drivers/regulator/palmas-regulator.c+7−7

 #define SMPS_CTRL_MODE_ECO		0x02
 #define SMPS_CTRL_MODE_PWM		0x03
-/* These values are derived from the data sheet. And are the number of steps
+#define PALMAS_SMPS_NUM_VOLTAGES	122
- * where there is a voltage change, the ranges at beginning and end of register
- * max/min values where there are no change are ommitted.
- *
- * So they are basically (maxV-minV)/stepV
- */
-#define PALMAS_SMPS_NUM_VOLTAGES	117
 #define PALMAS_SMPS10_NUM_VOLTAGES	2
 #define PALMAS_LDO_NUM_VOLTAGES		50
 			pmic->desc[id].min_uV = 900000;
 			pmic->desc[id].uV_step = 50000;
 			pmic->desc[id].linear_min_sel = 1;
+			pmic->desc[id].enable_time = 500;
 			pmic->desc[id].vsel_reg =
 					PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
 						palmas_regs_info[id].vsel_addr);
 				pmic->desc[id].min_uV = 450000;
 				pmic->desc[id].uV_step = 25000;
 			}
+			/* LOD6 in vibrator mode will have enable time 2000us */
+			if (pdata && pdata->ldo6_vibrator &&
+				(id == PALMAS_REG_LDO6))
+				pmic->desc[id].enable_time = 2000;
 		} else {
 			pmic->desc[id].n_voltages = 1;
 			pmic->desc[id].ops = &palmas_ops_extreg;

drivers/regulator/ti-abb-regulator.c+14−2

 	ti_abb_rmw(regs->opp_sel_mask, info->opp_sel, regs->control_reg,
 		   abb->base);
-	/* program LDO VBB vset override if needed */
+	/*
-	if (abb->ldo_base)
+	 * program LDO VBB vset override if needed for !bypass mode
+	 * XXX: Do not switch sequence - for !bypass, LDO override reset *must*
+	 * be performed *before* switch to bias mode else VBB glitches.
+	 */
+	if (abb->ldo_base && info->opp_sel != TI_ABB_NOMINAL_OPP)
 		ti_abb_program_ldovbb(dev, abb, info);
 	/* Initiate ABB ldo change */
 	if (ret)
 		goto out;
+	/*
+	 * Reset LDO VBB vset override bypass mode
+	 * XXX: Do not switch sequence - for bypass, LDO override reset *must*
+	 * be performed *after* switch to bypass else VBB glitches.
+	 */
+	if (abb->ldo_base && info->opp_sel == TI_ABB_NOMINAL_OPP)
+		ti_abb_program_ldovbb(dev, abb, info);
 out:
 	return ret;
 }

drivers/regulator/wm831x-ldo.c+2−2

@@ -63,7 +63,7 @@ static irqreturn_t wm831x_ldo_uv_irq(int irq, void *data) · 62 unmodified lines
63	*/	63	*/
64		64
65	static const struct regulator_linear_range wm831x_gp_ldo_ranges[] = {	65	static const struct regulator_linear_range wm831x_gp_ldo_ranges[] = {
66	{ .min_uV = 900000, .max_uV = 1650000, .min_sel = 0, .max_sel = 14,	66	{ .min_uV = 900000, .max_uV = 1600000, .min_sel = 0, .max_sel = 14,
67	.uV_step = 50000 },	67	.uV_step = 50000 },
68	{ .min_uV = 1700000, .max_uV = 3300000, .min_sel = 15, .max_sel = 31,	68	{ .min_uV = 1700000, .max_uV = 3300000, .min_sel = 15, .max_sel = 31,
69	.uV_step = 100000 },	69	.uV_step = 100000 },
@@ -332,7 +332,7 @@ static struct platform_driver wm831x_gp_ldo_driver = { · 262 unmodified lines
332	*/	332	*/
333		333
334	static const struct regulator_linear_range wm831x_aldo_ranges[] = {	334	static const struct regulator_linear_range wm831x_aldo_ranges[] = {
335	{ .min_uV = 1000000, .max_uV = 1650000, .min_sel = 0, .max_sel = 12,	335	{ .min_uV = 1000000, .max_uV = 1600000, .min_sel = 0, .max_sel = 12,
336	.uV_step = 50000 },	336	.uV_step = 50000 },
337	{ .min_uV = 1700000, .max_uV = 3500000, .min_sel = 13, .max_sel = 31,	337	{ .min_uV = 1700000, .max_uV = 3500000, .min_sel = 13, .max_sel = 31,
338	.uV_step = 100000 },	338	.uV_step = 100000 },

drivers/regulator/wm8350-regulator.c+1−1

@@ -543,7 +543,7 @@ static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev, · 542 unmodified lines
543	}	543	}
544		544
545	static const struct regulator_linear_range wm8350_ldo_ranges[] = {	545	static const struct regulator_linear_range wm8350_ldo_ranges[] = {
546	{ .min_uV = 900000, .max_uV = 1750000, .min_sel = 0, .max_sel = 15,	546	{ .min_uV = 900000, .max_uV = 1650000, .min_sel = 0, .max_sel = 15,
547	.uV_step = 50000 },	547	.uV_step = 50000 },
548	{ .min_uV = 1800000, .max_uV = 3300000, .min_sel = 16, .max_sel = 31,	548	{ .min_uV = 1800000, .max_uV = 3300000, .min_sel = 16, .max_sel = 31,
549	.uV_step = 100000 },	549	.uV_step = 100000 },

drivers/scsi/bnx2fc/bnx2fc.h+1−1

@@ -105,7 +105,7 @@ · 104 unmodified lines
105	#define BNX2FC_RQ_WQE_SIZE (BNX2FC_RQ_BUF_SZ)	105	#define BNX2FC_RQ_WQE_SIZE (BNX2FC_RQ_BUF_SZ)
106	#define BNX2FC_XFERQ_WQE_SIZE (sizeof(struct fcoe_xfrqe))	106	#define BNX2FC_XFERQ_WQE_SIZE (sizeof(struct fcoe_xfrqe))
107	#define BNX2FC_CONFQ_WQE_SIZE (sizeof(struct fcoe_confqe))	107	#define BNX2FC_CONFQ_WQE_SIZE (sizeof(struct fcoe_confqe))
108	#define BNX2FC_5771X_DB_PAGE_SIZE 128	108	#define BNX2X_DB_SHIFT 3
109		109
110	#define BNX2FC_TASK_SIZE 128	110	#define BNX2FC_TASK_SIZE 128
111	#define BNX2FC_TASKS_PER_PAGE (PAGE_SIZE/BNX2FC_TASK_SIZE)	111	#define BNX2FC_TASKS_PER_PAGE (PAGE_SIZE/BNX2FC_TASK_SIZE)

drivers/scsi/bnx2fc/bnx2fc_hwi.c+1−2

@@ -1421,8 +1421,7 @@ int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt) · 1420 unmodified lines
1421		1421
1422	reg_base = pci_resource_start(hba->pcidev,	1422	reg_base = pci_resource_start(hba->pcidev,
1423	BNX2X_DOORBELL_PCI_BAR);	1423	BNX2X_DOORBELL_PCI_BAR);
1424	reg_off = BNX2FC_5771X_DB_PAGE_SIZE *	1424	reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF);
1425	(context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
1426	tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);	1425	tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
1427	if (!tgt->ctx_base)	1426	if (!tgt->ctx_base)
1428	return -ENOMEM;	1427	return -ENOMEM;

drivers/scsi/bnx2i/bnx2i.h+1−1

@@ -64,7 +64,7 @@ · 63 unmodified lines
64	#define MAX_PAGES_PER_CTRL_STRUCT_POOL 8	64	#define MAX_PAGES_PER_CTRL_STRUCT_POOL 8
65	#define BNX2I_RESERVED_SLOW_PATH_CMD_SLOTS 4	65	#define BNX2I_RESERVED_SLOW_PATH_CMD_SLOTS 4
66		66
67	#define BNX2I_5771X_DBELL_PAGE_SIZE 128	67	#define BNX2X_DB_SHIFT 3
68		68
69	/* 5706/08 hardware has limit on maximum buffer size per BD it can handle */	69	/* 5706/08 hardware has limit on maximum buffer size per BD it can handle */
70	#define MAX_BD_LENGTH 65535	70	#define MAX_BD_LENGTH 65535

drivers/scsi/bnx2i/bnx2i_hwi.c+1−2

 	if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) {
 		reg_base = pci_resource_start(ep->hba->pcidev,
 					      BNX2X_DOORBELL_PCI_BAR);
-		reg_off = BNX2I_5771X_DBELL_PAGE_SIZE * (cid_num & 0x1FFFF) +
+		reg_off = (1 << BNX2X_DB_SHIFT) * (cid_num & 0x1FFFF);
-			  DPM_TRIGER_TYPE;
 		ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, 4);
 		goto arm_cq;
 	}

drivers/staging/comedi/Kconfig+17−16

 	  To compile this driver as a module, choose M here: the module will be
 	  called skel.
+config COMEDI_SSV_DNP
+	tristate "SSV Embedded Systems DIL/Net-PC support"
+	depends on X86_32 || COMPILE_TEST
+	---help---
+	  Enable support for SSV Embedded Systems DIL/Net-PC
+	  To compile this driver as a module, choose M here: the module will be
+	  called ssv_dnp.
 endif # COMEDI_MISC_DRIVERS
 menuconfig COMEDI_ISA_DRIVERS
 	  To compile this driver as a module, choose M here: the module will be
 	  called dmm32at.
+config COMEDI_UNIOXX5
+	tristate "Fastwel UNIOxx-5 analog and digital io board support"
+	---help---
+	  Enable support for Fastwel UNIOxx-5 (analog and digital i/o) boards
+	  To compile this driver as a module, choose M here: the module will be
+	  called unioxx5.
 config COMEDI_FL512
 	tristate "FL512 ISA card support"
 	---help---
 	  To compile this driver as a module, choose M here: the module will be
 	  called dyna_pci10xx.
-config COMEDI_UNIOXX5
-	tristate "Fastwel UNIOxx-5 analog and digital io board support"
-	---help---
-	  Enable support for Fastwel UNIOxx-5 (analog and digital i/o) boards
-	  To compile this driver as a module, choose M here: the module will be
-	  called unioxx5.
 config COMEDI_GSC_HPDI
 	tristate "General Standards PCI-HPDI32 / PMC-HPDI32 support"
 	select COMEDI_FC
 	  To compile this driver as a module, choose M here: the module will be
 	  called s626.
-config COMEDI_SSV_DNP
-	tristate "SSV Embedded Systems DIL/Net-PC support"
-	---help---
-	  Enable support for SSV Embedded Systems DIL/Net-PC
-	  To compile this driver as a module, choose M here: the module will be
-	  called ssv_dnp.
 config COMEDI_MITE
 	depends on HAS_DMA
 	tristate

drivers/staging/comedi/drivers/ni_65xx.c+10−15

@@ -369,28 +369,23 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev, · 368 unmodified lines
369	{	369	{
370	const struct ni_65xx_board *board = comedi_board(dev);	370	const struct ni_65xx_board *board = comedi_board(dev);
371	struct ni_65xx_private *devpriv = dev->private;	371	struct ni_65xx_private *devpriv = dev->private;
372	unsigned base_bitfield_channel;	372	int base_bitfield_channel;
373	const unsigned max_ports_per_bitfield = 5;
374	unsigned read_bits = 0;	373	unsigned read_bits = 0;
375	unsigned j;	374	int last_port_offset = ni_65xx_port_by_channel(s->n_chan - 1);
		375	int port_offset;
376		376
377	base_bitfield_channel = CR_CHAN(insn->chanspec);	377	base_bitfield_channel = CR_CHAN(insn->chanspec);
378	for (j = 0; j < max_ports_per_bitfield; ++j) {	378	for (port_offset = ni_65xx_port_by_channel(base_bitfield_channel);
379	const unsigned port_offset =	379	port_offset <= last_port_offset; port_offset++) {
380	ni_65xx_port_by_channel(base_bitfield_channel) + j;	380	unsigned port = sprivate(s)->base_port + port_offset;
381	const unsigned port =	381	int base_port_channel = port_offset * ni_65xx_channels_per_port;
382	sprivate(s)->base_port + port_offset;
383	unsigned base_port_channel;
384	unsigned port_mask, port_data, port_read_bits;	382	unsigned port_mask, port_data, port_read_bits;
385	int bitshift;	383	int bitshift = base_port_channel - base_bitfield_channel;
386	if (port >= ni_65xx_total_num_ports(board))	384
		385	if (bitshift >= 32)
387	break;	386	break;
388	base_port_channel = port_offset * ni_65xx_channels_per_port;
389	port_mask = data[0];	387	port_mask = data[0];
390	port_data = data[1];	388	port_data = data[1];
391	bitshift = base_port_channel - base_bitfield_channel;
392	if (bitshift >= 32 \|\| bitshift <= -32)
393	break;
394	if (bitshift > 0) {	389	if (bitshift > 0) {
395	port_mask >>= bitshift;	390	port_mask >>= bitshift;
396	port_data >>= bitshift;	391	port_data >>= bitshift;

drivers/staging/dgap/dgap_driver.c+10−7

                 DGAP_LOCK(dgap_global_lock, flags);
                 brd->msgbuf = NULL;
-                printk(brd->msgbuf_head);
+                printk("%s", brd->msgbuf_head);
                 kfree(brd->msgbuf_head);
                 brd->msgbuf_head = NULL;
                 DGAP_UNLOCK(dgap_global_lock, flags);
 	DPR_INIT(("dgap_scan(%d) - printing out the msgbuf\n", i));
 	DGAP_LOCK(dgap_global_lock, flags);
 	brd->msgbuf = NULL;
-	printk(brd->msgbuf_head);
+	printk("%s", brd->msgbuf_head);
 	kfree(brd->msgbuf_head);
 	brd->msgbuf_head = NULL;
 	DGAP_UNLOCK(dgap_global_lock, flags);
 	char		buf[1024];
 	int		i;
 	unsigned long	flags;
+	size_t		length;
 	DGAP_LOCK(dgap_global_lock, flags);
 	/* Format buf using fmt and arguments contained in ap. */
 	va_start(ap, fmt);
-	i = vsprintf(buf, fmt,  ap);
+	i = vsnprintf(buf, sizeof(buf), fmt,  ap);
 	va_end(ap);
 	DPR((buf));
 	if (!brd || !brd->msgbuf) {
-		printk(buf);
+		printk("%s", buf);
 		DGAP_UNLOCK(dgap_global_lock, flags);
 		return;
 	}
-	memcpy(brd->msgbuf, buf, strlen(buf));
+	length = strlen(buf) + 1;
-	brd->msgbuf += strlen(buf);
+	if (brd->msgbuf - brd->msgbuf_head < length)
-	*brd->msgbuf = 0;
+		length = brd->msgbuf - brd->msgbuf_head;
+	memcpy(brd->msgbuf, buf, length);
+	brd->msgbuf += length;
 	DGAP_UNLOCK(dgap_global_lock, flags);
 }

drivers/staging/dgnc/dgnc_driver.c+2−2

@@ -454,7 +454,7 @@ static void dgnc_cleanup_board(struct board_t *brd) · 453 unmodified lines
454		454
455	DGNC_LOCK(dgnc_global_lock, flags);	455	DGNC_LOCK(dgnc_global_lock, flags);
456	brd->msgbuf = NULL;	456	brd->msgbuf = NULL;
457	printk(brd->msgbuf_head);	457	printk("%s", brd->msgbuf_head);
458	kfree(brd->msgbuf_head);	458	kfree(brd->msgbuf_head);
459	brd->msgbuf_head = NULL;	459	brd->msgbuf_head = NULL;
460	DGNC_UNLOCK(dgnc_global_lock, flags);	460	DGNC_UNLOCK(dgnc_global_lock, flags);
@@ -710,7 +710,7 @@ static int dgnc_found_board(struct pci_dev *pdev, int id) · 249 unmodified lines
710	DPR_INIT(("dgnc_scan(%d) - printing out the msgbuf\n", i));	710	DPR_INIT(("dgnc_scan(%d) - printing out the msgbuf\n", i));
711	DGNC_LOCK(dgnc_global_lock, flags);	711	DGNC_LOCK(dgnc_global_lock, flags);
712	brd->msgbuf = NULL;	712	brd->msgbuf = NULL;
713	printk(brd->msgbuf_head);	713	printk("%s", brd->msgbuf_head);
714	kfree(brd->msgbuf_head);	714	kfree(brd->msgbuf_head);
715	brd->msgbuf_head = NULL;	715	brd->msgbuf_head = NULL;
716	DGNC_UNLOCK(dgnc_global_lock, flags);	716	DGNC_UNLOCK(dgnc_global_lock, flags);

drivers/staging/iio/Kconfig+1−1

@@ -37,7 +37,7 @@ config IIO_SIMPLE_DUMMY_EVENTS · 36 unmodified lines
37		37
38	config IIO_SIMPLE_DUMMY_BUFFER	38	config IIO_SIMPLE_DUMMY_BUFFER
39	boolean "Buffered capture support"	39	boolean "Buffered capture support"
40	depends on IIO_KFIFO_BUF	40	select IIO_KFIFO_BUF
41	help	41	help
42	Add buffered data capture to the simple dummy driver.	42	Add buffered data capture to the simple dummy driver.
43		43

drivers/staging/iio/light/isl29018.c+1−0

@@ -563,6 +563,7 @@ static int isl29018_probe(struct i2c_client *client, · 562 unmodified lines
563	mutex_init(&chip->lock);	563	mutex_init(&chip->lock);
564		564
565	chip->lux_scale = 1;	565	chip->lux_scale = 1;
		566	chip->lux_uscale = 0;
566	chip->range = 1000;	567	chip->range = 1000;
567	chip->adc_bit = 16;	568	chip->adc_bit = 16;
568	chip->suspended = false;	569	chip->suspended = false;

drivers/staging/iio/magnetometer/hmc5843.c+1−1

@@ -229,7 +229,7 @@ static int hmc5843_read_measurement(struct iio_dev *indio_dev, · 228 unmodified lines
229	if (result < 0)	229	if (result < 0)
230	return -EINVAL;	230	return -EINVAL;
231		231
232	*val = result;	232	*val = sign_extend32(result, 15);
233	return IIO_VAL_INT;	233	return IIO_VAL_INT;
234	}	234	}
235		235

drivers/staging/iio/meter/ade7854-spi.c+1−1

@@ -299,7 +299,7 @@ static int ade7854_spi_probe(struct spi_device *spi) · 298 unmodified lines
299	if (ret)	299	if (ret)
300	iio_device_free(indio_dev);	300	iio_device_free(indio_dev);
301		301
302	return 0;	302	return ret;
303	}	303	}
304		304
305	static int ade7854_spi_remove(struct spi_device *spi)	305	static int ade7854_spi_remove(struct spi_device *spi)

drivers/staging/imx-drm/imx-drm-core.c+3−8

 	struct list_head			encoder_list;
 	struct list_head			connector_list;
 	struct mutex				mutex;
-	int					references;
 	int					pipes;
 	struct drm_fbdev_cma			*fbhelper;
 };
 		}
 	}
-	imxdrm->references++;
 	return imxdrm->drm;
 unwind_crtc:
 	list_for_each_entry(enc, &imxdrm->encoder_list, list)
 		module_put(enc->owner);
-	imxdrm->references--;
 	mutex_unlock(&imxdrm->mutex);
 }
 EXPORT_SYMBOL_GPL(imx_drm_device_put);
 	mutex_lock(&imxdrm->mutex);
-	if (imxdrm->references) {
+	if (imxdrm->drm->open_count) {
 		ret = -EBUSY;
 		goto err_busy;
 	}
 	mutex_lock(&imxdrm->mutex);
-	if (imxdrm->references) {
+	if (imxdrm->drm->open_count) {
 		ret = -EBUSY;
 		goto err_busy;
 	}
 	mutex_lock(&imxdrm->mutex);
-	if (imxdrm->references) {
+	if (imxdrm->drm->open_count) {
 		ret = -EBUSY;
 		goto err_busy;
 	}

drivers/staging/line6/toneport.c+7−3

 	struct snd_line6_pcm *line6pcm = snd_kcontrol_chip(kcontrol);
 	struct usb_line6_toneport *toneport =
 	    (struct usb_line6_toneport *)line6pcm->line6;
+	unsigned int source;
-	if (ucontrol->value.enumerated.item[0] == toneport->source)
+	source = ucontrol->value.enumerated.item[0];
+	if (source >= ARRAY_SIZE(toneport_source_info))
+		return -EINVAL;
+	if (source == toneport->source)
 		return 0;
-	toneport->source = ucontrol->value.enumerated.item[0];
+	toneport->source = source;
 	toneport_send_cmd(toneport->line6.usbdev,
-			  toneport_source_info[toneport->source].code, 0x0000);
+			  toneport_source_info[source].code, 0x0000);
 	return 1;
 }

drivers/staging/lustre/lnet/klnds/o2iblnd/o2iblnd_cb.c+1−1

@@ -1802,7 +1802,7 @@ kiblnd_recv (lnet_ni_t ni, void private, lnet_msg_t *lntmsg, int delayed, · 1801 unmodified lines
1802	int	1802	int
1803	kiblnd_thread_start(int (fn)(void arg), void arg, char name)	1803	kiblnd_thread_start(int (fn)(void arg), void arg, char name)
1804	{	1804	{
1805	struct task_struct *task = kthread_run(fn, arg, name);	1805	struct task_struct *task = kthread_run(fn, arg, "%s", name);
1806		1806
1807	if (IS_ERR(task))	1807	if (IS_ERR(task))
1808	return PTR_ERR(task);	1808	return PTR_ERR(task);

drivers/staging/lustre/lnet/klnds/socklnd/socklnd_cb.c+1−1

@@ -1005,7 +1005,7 @@ ksocknal_send(lnet_ni_t ni, void private, lnet_msg_t *lntmsg) · 1004 unmodified lines
1005	int	1005	int
1006	ksocknal_thread_start(int (fn)(void arg), void arg, char name)	1006	ksocknal_thread_start(int (fn)(void arg), void arg, char name)
1007	{	1007	{
1008	struct task_struct *task = kthread_run(fn, arg, name);	1008	struct task_struct *task = kthread_run(fn, arg, "%s", name);
1009		1009
1010	if (IS_ERR(task))	1010	if (IS_ERR(task))
1011	return PTR_ERR(task);	1011	return PTR_ERR(task);

drivers/staging/lustre/lustre/Kconfig+2−2

@@ -1,6 +1,6 @@
1	config LUSTRE_FS	1	config LUSTRE_FS
2	tristate "Lustre file system client support"	2	tristate "Lustre file system client support"
3	depends on INET && m	3	depends on INET && m && !MIPS && !XTENSA && !SUPERH
4	select LNET	4	select LNET
5	select CRYPTO	5	select CRYPTO
6	select CRYPTO_CRC32	6	select CRYPTO_CRC32
@@ -52,7 +52,7 @@ config LUSTRE_DEBUG_EXPENSIVE_CHECK · 45 unmodified lines
52	config LUSTRE_TRANSLATE_ERRNOS	52	config LUSTRE_TRANSLATE_ERRNOS
53	bool	53	bool
54	depends on LUSTRE_FS && !X86	54	depends on LUSTRE_FS && !X86
55	default true	55	default y
56		56
57	config LUSTRE_LLITE_LLOOP	57	config LUSTRE_LLITE_LLOOP
58	bool "Lustre virtual block device"	58	bool "Lustre virtual block device"

drivers/staging/lustre/lustre/ldlm/ldlm_lockd.c+2−2

@@ -800,9 +800,9 @@ static int ldlm_bl_thread_start(struct ldlm_bl_pool *blp) · 799 unmodified lines
800		800
801	init_completion(&bltd.bltd_comp);	801	init_completion(&bltd.bltd_comp);
802	bltd.bltd_num = atomic_read(&blp->blp_num_threads);	802	bltd.bltd_num = atomic_read(&blp->blp_num_threads);
803	snprintf(bltd.bltd_name, sizeof(bltd.bltd_name) - 1,	803	snprintf(bltd.bltd_name, sizeof(bltd.bltd_name),
804	"ldlm_bl_%02d", bltd.bltd_num);	804	"ldlm_bl_%02d", bltd.bltd_num);
805	task = kthread_run(ldlm_bl_thread_main, &bltd, bltd.bltd_name);	805	task = kthread_run(ldlm_bl_thread_main, &bltd, "%s", bltd.bltd_name);
806	if (IS_ERR(task)) {	806	if (IS_ERR(task)) {
807	CERROR("cannot start LDLM thread ldlm_bl_%02d: rc %ld\n",	807	CERROR("cannot start LDLM thread ldlm_bl_%02d: rc %ld\n",
808	atomic_read(&blp->blp_num_threads), PTR_ERR(task));	808	atomic_read(&blp->blp_num_threads), PTR_ERR(task));

drivers/staging/lustre/lustre/libcfs/workitem.c+1−1

@@ -397,7 +397,7 @@ cfs_wi_sched_create(char name, struct cfs_cpt_table cptab, · 396 unmodified lines
397	sched->ws_name, sched->ws_nthreads);	397	sched->ws_name, sched->ws_nthreads);
398	}	398	}
399		399
400	task = kthread_run(cfs_wi_scheduler, sched, name);	400	task = kthread_run(cfs_wi_scheduler, sched, "%s", name);
401	if (!IS_ERR(task)) {	401	if (!IS_ERR(task)) {
402	nthrs--;	402	nthrs--;
403	continue;	403	continue;

drivers/staging/lustre/lustre/obdecho/echo_client.c+1−1

@@ -1387,7 +1387,7 @@ echo_copyout_lsm (struct lov_stripe_md lsm, void _ulsm, int ulsm_nob) · 1386 unmodified lines
1387	if (nob > ulsm_nob)	1387	if (nob > ulsm_nob)
1388	return (-EINVAL);	1388	return (-EINVAL);
1389		1389
1390	if (copy_to_user (ulsm, lsm, sizeof(ulsm)))	1390	if (copy_to_user (ulsm, lsm, sizeof(*ulsm)))
1391	return (-EFAULT);	1391	return (-EFAULT);
1392		1392
1393	for (i = 0; i < lsm->lsm_stripe_count; i++) {	1393	for (i = 0; i < lsm->lsm_stripe_count; i++) {

drivers/staging/lustre/lustre/ptlrpc/pinger.c+2−2

@@ -383,8 +383,8 @@ int ptlrpc_start_pinger(void) · 382 unmodified lines
383		383
384	/* CLONE_VM and CLONE_FILES just avoid a needless copy, because we	384	/* CLONE_VM and CLONE_FILES just avoid a needless copy, because we
385	* just drop the VM and FILES in cfs_daemonize_ctxt() right away. */	385	* just drop the VM and FILES in cfs_daemonize_ctxt() right away. */
386	rc = PTR_ERR(kthread_run(ptlrpc_pinger_main,	386	rc = PTR_ERR(kthread_run(ptlrpc_pinger_main, &pinger_thread,
387	&pinger_thread, pinger_thread.t_name));	387	"%s", pinger_thread.t_name));
388	if (IS_ERR_VALUE(rc)) {	388	if (IS_ERR_VALUE(rc)) {
389	CERROR("cannot start thread: %d\n", rc);	389	CERROR("cannot start thread: %d\n", rc);
390	return rc;	390	return rc;

drivers/staging/lustre/lustre/ptlrpc/ptlrpcd.c+4−4

@@ -615,7 +615,7 @@ int ptlrpcd_start(int index, int max, const char name, struct ptlrpcd_ctl pc) · 614 unmodified lines
615	init_completion(&pc->pc_starting);	615	init_completion(&pc->pc_starting);
616	init_completion(&pc->pc_finishing);	616	init_completion(&pc->pc_finishing);
617	spin_lock_init(&pc->pc_lock);	617	spin_lock_init(&pc->pc_lock);
618	strncpy(pc->pc_name, name, sizeof(pc->pc_name) - 1);	618	strlcpy(pc->pc_name, name, sizeof(pc->pc_name));
619	pc->pc_set = ptlrpc_prep_set();	619	pc->pc_set = ptlrpc_prep_set();
620	if (pc->pc_set == NULL)	620	if (pc->pc_set == NULL)
621	GOTO(out, rc = -ENOMEM);	621	GOTO(out, rc = -ENOMEM);
@@ -638,7 +638,7 @@ int ptlrpcd_start(int index, int max, const char name, struct ptlrpcd_ctl pc) · 16 unmodified lines
638	GOTO(out, rc);	638	GOTO(out, rc);
639	}	639	}
640		640
641	task = kthread_run(ptlrpcd, pc, pc->pc_name);	641	task = kthread_run(ptlrpcd, pc, "%s", pc->pc_name);
642	if (IS_ERR(task))	642	if (IS_ERR(task))
643	GOTO(out, rc = PTR_ERR(task));	643	GOTO(out, rc = PTR_ERR(task));
644		644
@@ -745,7 +745,7 @@ static int ptlrpcd_init(void) · 100 unmodified lines
745	if (ptlrpcds == NULL)	745	if (ptlrpcds == NULL)
746	GOTO(out, rc = -ENOMEM);	746	GOTO(out, rc = -ENOMEM);
747		747
748	snprintf(name, 15, "ptlrpcd_rcv");	748	snprintf(name, sizeof(name), "ptlrpcd_rcv");
749	set_bit(LIOD_RECOVERY, &ptlrpcds->pd_thread_rcv.pc_flags);	749	set_bit(LIOD_RECOVERY, &ptlrpcds->pd_thread_rcv.pc_flags);
750	rc = ptlrpcd_start(-1, nthreads, name, &ptlrpcds->pd_thread_rcv);	750	rc = ptlrpcd_start(-1, nthreads, name, &ptlrpcds->pd_thread_rcv);
751	if (rc < 0)	751	if (rc < 0)
@@ -764,7 +764,7 @@ static int ptlrpcd_init(void) · 12 unmodified lines
764	* unnecessary dependency. But how to distribute async RPCs load	764	* unnecessary dependency. But how to distribute async RPCs load
765	* among all the ptlrpc daemons becomes another trouble. */	765	* among all the ptlrpc daemons becomes another trouble. */
766	for (i = 0; i < nthreads; i++) {	766	for (i = 0; i < nthreads; i++) {
767	snprintf(name, 15, "ptlrpcd_%d", i);	767	snprintf(name, sizeof(name), "ptlrpcd_%d", i);
768	rc = ptlrpcd_start(i, nthreads, name, &ptlrpcds->pd_threads[i]);	768	rc = ptlrpcd_start(i, nthreads, name, &ptlrpcds->pd_threads[i]);
769	if (rc < 0)	769	if (rc < 0)
770	GOTO(out, rc);	770	GOTO(out, rc);

drivers/staging/lustre/lustre/ptlrpc/sec_bulk.c+2−2

@@ -59,8 +59,8 @@ · 58 unmodified lines
59	****************************************/	59	****************************************/
60		60
61		61
62	#define PTRS_PER_PAGE (PAGE_CACHE_SIZE / sizeof(void *))	62	#define POINTERS_PER_PAGE (PAGE_CACHE_SIZE / sizeof(void *))
63	#define PAGES_PER_POOL (PTRS_PER_PAGE)	63	#define PAGES_PER_POOL (POINTERS_PER_PAGE)
64		64
65	#define IDLE_IDX_MAX (100)	65	#define IDLE_IDX_MAX (100)
66	#define IDLE_IDX_WEIGHT (3)	66	#define IDLE_IDX_WEIGHT (3)

drivers/staging/lustre/lustre/ptlrpc/service.c+3−3

@@ -2718,15 +2718,15 @@ int ptlrpc_start_thread(struct ptlrpc_service_part *svcpt, int wait) · 2717 unmodified lines
2718	spin_unlock(&svcpt->scp_lock);	2718	spin_unlock(&svcpt->scp_lock);
2719		2719
2720	if (svcpt->scp_cpt >= 0) {	2720	if (svcpt->scp_cpt >= 0) {
2721	snprintf(thread->t_name, PTLRPC_THR_NAME_LEN, "%s%02d_%03d",	2721	snprintf(thread->t_name, sizeof(thread->t_name), "%s%02d_%03d",
2722	svc->srv_thread_name, svcpt->scp_cpt, thread->t_id);	2722	svc->srv_thread_name, svcpt->scp_cpt, thread->t_id);
2723	} else {	2723	} else {
2724	snprintf(thread->t_name, PTLRPC_THR_NAME_LEN, "%s_%04d",	2724	snprintf(thread->t_name, sizeof(thread->t_name), "%s_%04d",
2725	svc->srv_thread_name, thread->t_id);	2725	svc->srv_thread_name, thread->t_id);
2726	}	2726	}
2727		2727
2728	CDEBUG(D_RPCTRACE, "starting thread '%s'\n", thread->t_name);	2728	CDEBUG(D_RPCTRACE, "starting thread '%s'\n", thread->t_name);
2729	rc = PTR_ERR(kthread_run(ptlrpc_main, thread, thread->t_name));	2729	rc = PTR_ERR(kthread_run(ptlrpc_main, thread, "%s", thread->t_name));
2730	if (IS_ERR_VALUE(rc)) {	2730	if (IS_ERR_VALUE(rc)) {
2731	CERROR("cannot start thread '%s': rc %d\n",	2731	CERROR("cannot start thread '%s': rc %d\n",
2732	thread->t_name, rc);	2732	thread->t_name, rc);

drivers/staging/octeon-usb/cvmx-usb.c+1−1

@@ -604,7 +604,7 @@ int cvmx_usb_initialize(struct cvmx_usb_state *state, int usb_port_number, · 603 unmodified lines
604	}	604	}
605	}	605	}
606		606
607	memset(usb, 0, sizeof(usb));	607	memset(usb, 0, sizeof(*usb));
608	usb->init_flags = flags;	608	usb->init_flags = flags;
609		609
610	/* Initialize the USB state structure */	610	/* Initialize the USB state structure */

drivers/staging/octeon/ethernet-mem.c+1−6

 	while (freed) {
 		struct sk_buff *skb = dev_alloc_skb(size + 256);
-		if (unlikely(skb == NULL)) {
+		if (unlikely(skb == NULL))
-			pr_warning
-			    ("Failed to allocate skb for hardware pool %d\n",
-			     pool);
 			break;
-		}
 		skb_reserve(skb, 256 - (((unsigned long)skb->data) & 0x7f));
 		*(struct sk_buff **)(skb->data - sizeof(void *)) = skb;
 		cvmx_fpa_free(skb->data, pool, DONT_WRITEBACK(size / 128));

drivers/staging/octeon/ethernet-rgmii.c+1−3

 			 * Enable interrupts on inband status changes
 			 * for this port.
 			 */
-			gmx_rx_int_en.u64 =
+			gmx_rx_int_en.u64 = 0;
-			    cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
-					  (index, interface));
 			gmx_rx_int_en.s.phy_dupx = 1;
 			gmx_rx_int_en.s.phy_link = 1;
 			gmx_rx_int_en.s.phy_spd = 1;

drivers/staging/octeon/ethernet-rx.c+1−4

 			if (backlog > budget * cores_in_use && napi != NULL)
 				cvm_oct_enable_one_cpu();
 		}
+		rx_count++;
 		skb_in_hw = USE_SKBUFFS_IN_HW && work->word2.s.bufs == 1;
 		if (likely(skb_in_hw)) {
 			 */
 			skb = dev_alloc_skb(work->len);
 			if (!skb) {
-				printk_ratelimited("Port %d failed to allocate "
-						   "skbuff, packet dropped\n",
-						   work->ipprt);
 				cvm_oct_free_work(work);
 				continue;
 			}
 #endif
 				}
 				netif_receive_skb(skb);
-				rx_count++;
 			} else {
 				/* Drop any packet received for a device that isn't up */
 				/*

drivers/staging/rtl8188eu/core/rtw_ieee80211.c+1−1

@@ -157,8 +157,8 @@ _func_enter_; · 156 unmodified lines
157		157
158	frlen = frlen + (len + 2);	158	frlen = frlen + (len + 2);
159		159
160	return pbuf + len + 2;
161	_func_exit_;	160	_func_exit_;
		161	return pbuf + len + 2;
162	}	162	}
163		163
164	inline u8 rtw_set_ie_ch_switch (u8 buf, u32 *buf_len, u8 ch_switch_mode,	164	inline u8 rtw_set_ie_ch_switch (u8 buf, u32 *buf_len, u8 ch_switch_mode,

drivers/staging/rtl8188eu/core/rtw_mlme_ext.c+7−7

@@ -1827,13 +1827,13 @@ unsigned int OnAction_back(struct adapter padapter, union recv_frame precv_fra · 1826 unmodified lines
1827		1827
1828	#ifdef CONFIG_88EU_P2P	1828	#ifdef CONFIG_88EU_P2P
1829		1829
1830	static int get_reg_classes_full_count(struct p2p_channels channel_list)	1830	static int get_reg_classes_full_count(struct p2p_channels *channel_list)
1831	{	1831	{
1832	int cnt = 0;	1832	int cnt = 0;
1833	int i;	1833	int i;
1834		1834
1835	for (i = 0; i < channel_list.reg_classes; i++) {	1835	for (i = 0; i < channel_list->reg_classes; i++) {
1836	cnt += channel_list.reg_class[i].channels;	1836	cnt += channel_list->reg_class[i].channels;
1837	}	1837	}
1838		1838
1839	return cnt;	1839	return cnt;
@@ -2065,7 +2065,7 @@ void issue_p2p_GO_request(struct adapter padapter, u8 raddr) · 225 unmodified lines
2065	/* + number of channels in all classes */	2065	/* + number of channels in all classes */
2066	len_channellist_attr = 3	2066	len_channellist_attr = 3
2067	+ (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes)	2067	+ (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes)
2068	+ get_reg_classes_full_count(pmlmeext->channel_list);	2068	+ get_reg_classes_full_count(&pmlmeext->channel_list);
2069		2069
2070	(__le16 )(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);	2070	(__le16 )(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
2071	p2pielen += 2;	2071	p2pielen += 2;
@@ -2437,7 +2437,7 @@ static void issue_p2p_GO_response(struct adapter padapter, u8 raddr, u8 *frame · 365 unmodified lines
2437	/* + number of channels in all classes */	2437	/* + number of channels in all classes */
2438	len_channellist_attr = 3	2438	len_channellist_attr = 3
2439	+ (1 + 1) * (u16)pmlmeext->channel_list.reg_classes	2439	+ (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
2440	+ get_reg_classes_full_count(pmlmeext->channel_list);	2440	+ get_reg_classes_full_count(&pmlmeext->channel_list);
2441		2441
2442	(__le16 )(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);	2442	(__le16 )(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
2443		2443
@@ -2859,7 +2859,7 @@ void issue_p2p_invitation_request(struct adapter padapter, u8 raddr) · 415 unmodified lines
2859	/* + number of channels in all classes */	2859	/* + number of channels in all classes */
2860	len_channellist_attr = 3	2860	len_channellist_attr = 3
2861	+ (1 + 1) * (u16)pmlmeext->channel_list.reg_classes	2861	+ (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
2862	+ get_reg_classes_full_count(pmlmeext->channel_list);	2862	+ get_reg_classes_full_count(&pmlmeext->channel_list);
2863		2863
2864	(__le16 )(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);	2864	(__le16 )(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
2865		2865
@@ -3120,7 +3120,7 @@ void issue_p2p_invitation_response(struct adapter padapter, u8 raddr, u8 dialo · 254 unmodified lines
3120	/* + number of channels in all classes */	3120	/* + number of channels in all classes */
3121	len_channellist_attr = 3	3121	len_channellist_attr = 3
3122	+ (1 + 1) * (u16)pmlmeext->channel_list.reg_classes	3122	+ (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
3123	+ get_reg_classes_full_count(pmlmeext->channel_list);	3123	+ get_reg_classes_full_count(&pmlmeext->channel_list);
3124		3124
3125	(__le16 )(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);	3125	(__le16 )(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
3126	p2pielen += 2;	3126	p2pielen += 2;

drivers/staging/rtl8188eu/core/rtw_mp.c+1−1

@@ -907,7 +907,7 @@ u32 mp_query_psd(struct adapter pAdapter, u8 data) · 906 unmodified lines
907	sscanf(data, "pts =%d, start =%d, stop =%d", &psd_pts, &psd_start, &psd_stop);	907	sscanf(data, "pts =%d, start =%d, stop =%d", &psd_pts, &psd_start, &psd_stop);
908	}	908	}
909		909
910	_rtw_memset(data, '\0', sizeof(data));	910	_rtw_memset(data, '\0', sizeof(*data));
911		911
912	i = psd_start;	912	i = psd_start;
913	while (i < psd_stop) {	913	while (i < psd_stop) {

drivers/staging/rtl8188eu/core/rtw_wlan_util.c+1−1

@@ -631,7 +631,7 @@ void WMMOnAssocRsp(struct adapter *padapter) · 630 unmodified lines
631	inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3;	631	inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3;
632		632
633	if (pregpriv->wifi_spec == 1) {	633	if (pregpriv->wifi_spec == 1) {
634	u32 j, tmp, change_inx;	634	u32 j, tmp, change_inx = false;
635		635
636	/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */	636	/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */
637	for (i = 0; i < 4; i++) {	637	for (i = 0; i < 4; i++) {

drivers/staging/rtl8188eu/hal/rtl8188e_dm.c+1−1

@@ -57,7 +57,7 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter) · 56 unmodified lines
57	u8 cut_ver, fab_ver;	57	u8 cut_ver, fab_ver;
58		58
59	/* Init Value */	59	/* Init Value */
60	_rtw_memset(dm_odm, 0, sizeof(dm_odm));	60	_rtw_memset(dm_odm, 0, sizeof(*dm_odm));
61		61
62	dm_odm->Adapter = Adapter;	62	dm_odm->Adapter = Adapter;
63		63

drivers/staging/rtl8188eu/include/odm.h+1−1

@@ -1010,7 +1010,7 @@ enum dm_dig_op { · 1009 unmodified lines
1010	#define DM_false_ALARM_THRESH_LOW 400	1010	#define DM_false_ALARM_THRESH_LOW 400
1011	#define DM_false_ALARM_THRESH_HIGH 1000	1011	#define DM_false_ALARM_THRESH_HIGH 1000
1012		1012
1013	#define DM_DIG_MAX_NIC 0x3e	1013	#define DM_DIG_MAX_NIC 0x4e
1014	#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */	1014	#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */
1015		1015
1016	#define DM_DIG_MAX_AP 0x32	1016	#define DM_DIG_MAX_AP 0x32

drivers/staging/rtl8188eu/include/rtl8188e_hal.h+1−1

@@ -188,7 +188,7 @@ enum ChannelPlan { · 187 unmodified lines
188		188
189	struct txpowerinfo24g {	189	struct txpowerinfo24g {
190	u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];	190	u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
191	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1];	191	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
192	/* If only one tx, only BW20 and OFDM are used. */	192	/* If only one tx, only BW20 and OFDM are used. */
193	s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];	193	s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
194	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];	194	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];

drivers/staging/rtl8188eu/include/rtw_mlme_ext.h+1−0

@@ -870,6 +870,7 @@ static struct fwevent wlanevents[] = { · 869 unmodified lines
870	{0, NULL},	870	{0, NULL},
871	{0, NULL},	871	{0, NULL},
872	{0, &rtw_cpwm_event_callback},	872	{0, &rtw_cpwm_event_callback},
		873	{0, NULL},
873	};	874	};
874		875
875	#endif/* _RTL_MLME_EXT_C_ */	876	#endif/* _RTL_MLME_EXT_C_ */

drivers/staging/rtl8188eu/os_dep/ioctl_linux.c+1−1

@@ -6973,7 +6973,7 @@ static int rtw_mp_ctx(struct net_device *dev, · 6972 unmodified lines
6973	stop = strncmp(extra, "stop", 4);	6973	stop = strncmp(extra, "stop", 4);
6974	sscanf(extra, "count =%d, pkt", &count);	6974	sscanf(extra, "count =%d, pkt", &count);
6975		6975
6976	_rtw_memset(extra, '\0', sizeof(extra));	6976	_rtw_memset(extra, '\0', sizeof(*extra));
6977		6977
6978	if (stop == 0) {	6978	if (stop == 0) {
6979	bStartTest = 0; /* To set Stop */	6979	bStartTest = 0; /* To set Stop */

drivers/staging/rtl8188eu/os_dep/usb_intf.c+1−0

@@ -54,6 +54,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = { · 53 unmodified lines
54	/=== Customer ID ===/	54	/=== Customer ID ===/
55	/**** 8188EUS ******/	55	/**** 8188EUS ******/
56	{USB_DEVICE(0x8179, 0x07B8)}, /* Abocom - Abocom */	56	{USB_DEVICE(0x8179, 0x07B8)}, /* Abocom - Abocom */
		57	{USB_DEVICE(0x2001, 0x330F)}, /* DLink DWA-125 REV D1 */
57	{} /* Terminating entry */	58	{} /* Terminating entry */
58	};	59	};
59		60

drivers/staging/rtl8192u/r819xU_cmdpkt.c+2−0

 	/* Get TCB and local buffer from common pool.
 	   (It is shared by CmdQ, MgntQ, and USB coalesce DataQ) */
 	skb  = dev_alloc_skb(USB_HWDESC_HEADER_LEN + DataLen + 4);
+	if (!skb)
+		return RT_STATUS_FAILURE;
 	memcpy((unsigned char *)(skb->cb), &dev, sizeof(dev));
 	tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
 	tcb_desc->queue_index = TXCMD_QUEUE;

drivers/staging/vt6656/card.c+2−2

@@ -172,8 +172,8 @@ static u16 swGetOFDMControlRate(struct vnt_private *pDevice, u16 wRateIdx) · 171 unmodified lines
172	if (!CARDbIsOFDMinBasicRate(pDevice)) {	172	if (!CARDbIsOFDMinBasicRate(pDevice)) {
173	DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO	173	DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
174	"swGetOFDMControlRate:(NO OFDM) %d\n", wRateIdx);	174	"swGetOFDMControlRate:(NO OFDM) %d\n", wRateIdx);
175	if (wRateIdx > RATE_24M)	175	if (wRateIdx > RATE_24M)
176	wRateIdx = RATE_24M;	176	wRateIdx = RATE_24M;
177	return wRateIdx;	177	return wRateIdx;
178	}	178	}
179		179

drivers/staging/vt6656/iwctl.c+3−0

@@ -1634,6 +1634,9 @@ int iwctl_siwencodeext(struct net_device dev, struct iw_request_info info, · 1633 unmodified lines
1634	if (pMgmt == NULL)	1634	if (pMgmt == NULL)
1635	return -EFAULT;	1635	return -EFAULT;
1636		1636
		1637	if (!(pDevice->flags & DEVICE_FLAGS_OPENED))
		1638	return -ENODEV;
		1639
1637	buf = kzalloc(sizeof(struct viawget_wpa_param), GFP_KERNEL);	1640	buf = kzalloc(sizeof(struct viawget_wpa_param), GFP_KERNEL);
1638	if (buf == NULL)	1641	if (buf == NULL)
1639	return -ENOMEM;	1642	return -ENOMEM;

drivers/staging/vt6656/main_usb.c+2−1

     memset(pMgmt->abyCurrBSSID, 0, 6);
     pMgmt->eCurrState = WMAC_STATE_IDLE;
+	pDevice->flags &= ~DEVICE_FLAGS_OPENED;
     device_free_tx_bufs(pDevice);
     device_free_rx_bufs(pDevice);
     device_free_int_bufs(pDevice);
     usb_free_urb(pDevice->pInterruptURB);
     BSSvClearNodeDBTable(pDevice, 0);
-    pDevice->flags &=(~DEVICE_FLAGS_OPENED);
     DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "device_close2 \n");

drivers/staging/vt6656/rxtx.c+2−0

@@ -148,6 +148,8 @@ static void s_vGetFreeContext(struct vnt_private pDevice) · 147 unmodified lines
148	DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"GetFreeContext()\n");	148	DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"GetFreeContext()\n");
149		149
150	for (ii = 0; ii < pDevice->cbTD; ii++) {	150	for (ii = 0; ii < pDevice->cbTD; ii++) {
		151	if (!pDevice->apTD[ii])
		152	return NULL;
151	pContext = pDevice->apTD[ii];	153	pContext = pDevice->apTD[ii];
152	if (pContext->bBoolInUse == false) {	154	if (pContext->bBoolInUse == false) {
153	pContext->bBoolInUse = true;	155	pContext->bBoolInUse = true;

drivers/staging/xillybus/xillybus_core.c+1−1

@@ -2054,7 +2054,7 @@ static int xillybus_init_chrdev(struct xilly_endpoint *endpoint, · 2053 unmodified lines
2054	NULL,	2054	NULL,
2055	MKDEV(major, i),	2055	MKDEV(major, i),
2056	NULL,	2056	NULL,
2057	devname);	2057	"%s", devname);
2058		2058
2059	if (IS_ERR(device)) {	2059	if (IS_ERR(device)) {
2060	pr_warn("xillybus: Failed to create %s "	2060	pr_warn("xillybus: Failed to create %s "

drivers/staging/zram/zram_drv.c+0−1

@@ -981,4 +981,3 @@ MODULE_PARM_DESC(num_devices, "Number of zram devices"); · 980 unmodified lines
981	MODULE_LICENSE("Dual BSD/GPL");	981	MODULE_LICENSE("Dual BSD/GPL");
982	MODULE_AUTHOR("Nitin Gupta <ngupta@vflare.org>");	982	MODULE_AUTHOR("Nitin Gupta <ngupta@vflare.org>");
983	MODULE_DESCRIPTION("Compressed RAM Block Device");	983	MODULE_DESCRIPTION("Compressed RAM Block Device");
984	MODULE_ALIAS("devname:zram");

drivers/target/iscsi/iscsi_target.c+9−4

 static void iscsit_ack_from_expstatsn(struct iscsi_conn *conn, u32 exp_statsn)
 {
-	struct iscsi_cmd *cmd;
+	LIST_HEAD(ack_list);
+	struct iscsi_cmd *cmd, *cmd_p;
 	conn->exp_statsn = exp_statsn;
 		return;
 	spin_lock_bh(&conn->cmd_lock);
-	list_for_each_entry(cmd, &conn->conn_cmd_list, i_conn_node) {
+	list_for_each_entry_safe(cmd, cmd_p, &conn->conn_cmd_list, i_conn_node) {
 		spin_lock(&cmd->istate_lock);
 		if ((cmd->i_state == ISTATE_SENT_STATUS) &&
 		    iscsi_sna_lt(cmd->stat_sn, exp_statsn)) {
 			cmd->i_state = ISTATE_REMOVE;
 			spin_unlock(&cmd->istate_lock);
-			iscsit_add_cmd_to_immediate_queue(cmd, conn,
+			list_move_tail(&cmd->i_conn_node, &ack_list);
-						cmd->i_state);
 			continue;
 		}
 		spin_unlock(&cmd->istate_lock);
 	}
 	spin_unlock_bh(&conn->cmd_lock);
+	list_for_each_entry_safe(cmd, cmd_p, &ack_list, i_conn_node) {
+		list_del(&cmd->i_conn_node);
+		iscsit_free_cmd(cmd, false);
+	}
 }
 static int iscsit_allocate_iovecs(struct iscsi_cmd *cmd)

drivers/target/iscsi/iscsi_target_nego.c+1−1

@@ -1192,7 +1192,7 @@ get_target: · 1191 unmodified lines
1192	*/	1192	*/
1193	alloc_tags:	1193	alloc_tags:
1194	tag_num = max_t(u32, ISCSIT_MIN_TAGS, queue_depth);	1194	tag_num = max_t(u32, ISCSIT_MIN_TAGS, queue_depth);
1195	tag_num += ISCSIT_EXTRA_TAGS;	1195	tag_num += (tag_num / 2) + ISCSIT_EXTRA_TAGS;
1196	tag_size = sizeof(struct iscsi_cmd) + conn->conn_transport->priv_size;	1196	tag_size = sizeof(struct iscsi_cmd) + conn->conn_transport->priv_size;
1197		1197
1198	ret = transport_alloc_session_tags(sess->se_sess, tag_num, tag_size);	1198	ret = transport_alloc_session_tags(sess->se_sess, tag_num, tag_size);

drivers/target/iscsi/iscsi_target_util.c+2−2

@@ -736,7 +736,7 @@ void iscsit_free_cmd(struct iscsi_cmd *cmd, bool shutdown) · 735 unmodified lines
736	* Fallthrough	736	* Fallthrough
737	*/	737	*/
738	case ISCSI_OP_SCSI_TMFUNC:	738	case ISCSI_OP_SCSI_TMFUNC:
739	rc = transport_generic_free_cmd(&cmd->se_cmd, 1);	739	rc = transport_generic_free_cmd(&cmd->se_cmd, shutdown);
740	if (!rc && shutdown && se_cmd && se_cmd->se_sess) {	740	if (!rc && shutdown && se_cmd && se_cmd->se_sess) {
741	__iscsit_free_cmd(cmd, true, shutdown);	741	__iscsit_free_cmd(cmd, true, shutdown);
742	target_put_sess_cmd(se_cmd->se_sess, se_cmd);	742	target_put_sess_cmd(se_cmd->se_sess, se_cmd);
@@ -752,7 +752,7 @@ void iscsit_free_cmd(struct iscsi_cmd *cmd, bool shutdown) · 9 unmodified lines
752	se_cmd = &cmd->se_cmd;	752	se_cmd = &cmd->se_cmd;
753	__iscsit_free_cmd(cmd, true, shutdown);	753	__iscsit_free_cmd(cmd, true, shutdown);
754		754
755	rc = transport_generic_free_cmd(&cmd->se_cmd, 1);	755	rc = transport_generic_free_cmd(&cmd->se_cmd, shutdown);
756	if (!rc && shutdown && se_cmd->se_sess) {	756	if (!rc && shutdown && se_cmd->se_sess) {
757	__iscsit_free_cmd(cmd, true, shutdown);	757	__iscsit_free_cmd(cmd, true, shutdown);
758	target_put_sess_cmd(se_cmd->se_sess, se_cmd);	758	target_put_sess_cmd(se_cmd->se_sess, se_cmd);

drivers/target/target_core_sbc.c+26−2

 {
 	struct se_device *dev = cmd->se_dev;
-	cmd->se_cmd_flags |= SCF_COMPARE_AND_WRITE_POST;
+	/*
+	 * Only set SCF_COMPARE_AND_WRITE_POST to force a response fall-through
+	 * within target_complete_ok_work() if the command was successfully
+	 * sent to the backend driver.
+	 */
+	spin_lock_irq(&cmd->t_state_lock);
+	if ((cmd->transport_state & CMD_T_SENT) && !cmd->scsi_status)
+		cmd->se_cmd_flags |= SCF_COMPARE_AND_WRITE_POST;
+	spin_unlock_irq(&cmd->t_state_lock);
 	/*
 	 * Unlock ->caw_sem originally obtained during sbc_compare_and_write()
 	 * before the original READ I/O submission.
 {
 	struct se_device *dev = cmd->se_dev;
 	struct scatterlist *write_sg = NULL, *sg;
-	unsigned char *buf, *addr;
+	unsigned char *buf = NULL, *addr;
 	struct sg_mapping_iter m;
 	unsigned int offset = 0, len;
 	unsigned int nlbas = cmd->t_task_nolb;
 	 */
 	if (!cmd->t_data_sg || !cmd->t_bidi_data_sg)
 		return TCM_NO_SENSE;
+	/*
+	 * Immediately exit + release dev->caw_sem if command has already
+	 * been failed with a non-zero SCSI status.
+	 */
+	if (cmd->scsi_status) {
+		pr_err("compare_and_write_callback: non zero scsi_status:"
+			" 0x%02x\n", cmd->scsi_status);
+		goto out;
+	}
 	buf = kzalloc(cmd->data_length, GFP_KERNEL);
 	if (!buf) {
 		cmd->transport_complete_callback = NULL;
 		return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
 	}
+	/*
+	 * Reset cmd->data_length to individual block_size in order to not
+	 * confuse backend drivers that depend on this value matching the
+	 * size of the I/O being submitted.
+	 */
+	cmd->data_length = cmd->t_task_nolb * dev->dev_attrib.block_size;
 	ret = cmd->execute_rw(cmd, cmd->t_bidi_data_sg, cmd->t_bidi_data_nents,
 			      DMA_FROM_DEVICE);

drivers/target/target_core_transport.c+15−5

 {
 	int rc;
-	se_sess->sess_cmd_map = kzalloc(tag_num * tag_size, GFP_KERNEL);
+	se_sess->sess_cmd_map = kzalloc(tag_num * tag_size,
+					GFP_KERNEL | __GFP_NOWARN | __GFP_REPEAT);
 	if (!se_sess->sess_cmd_map) {
-		pr_err("Unable to allocate se_sess->sess_cmd_map\n");
+		se_sess->sess_cmd_map = vzalloc(tag_num * tag_size);
-		return -ENOMEM;
+		if (!se_sess->sess_cmd_map) {
+			pr_err("Unable to allocate se_sess->sess_cmd_map\n");
+			return -ENOMEM;
+		}
 	}
 	rc = percpu_ida_init(&se_sess->sess_tag_pool, tag_num);
 	if (rc < 0) {
 		pr_err("Unable to init se_sess->sess_tag_pool,"
 			" tag_num: %u\n", tag_num);
-		kfree(se_sess->sess_cmd_map);
+		if (is_vmalloc_addr(se_sess->sess_cmd_map))
+			vfree(se_sess->sess_cmd_map);
+		else
+			kfree(se_sess->sess_cmd_map);
 		se_sess->sess_cmd_map = NULL;
 		return -ENOMEM;
 	}
 {
 	if (se_sess->sess_cmd_map) {
 		percpu_ida_destroy(&se_sess->sess_tag_pool);
-		kfree(se_sess->sess_cmd_map);
+		if (is_vmalloc_addr(se_sess->sess_cmd_map))
+			vfree(se_sess->sess_cmd_map);
+		else
+			kfree(se_sess->sess_cmd_map);
 	}
 	kmem_cache_free(se_sess_cache, se_sess);
 }

drivers/target/target_core_xcopy.c+2−2

@@ -298,8 +298,8 @@ static int target_xcopy_parse_segdesc_02(struct se_cmd *se_cmd, struct xcopy_op · 297 unmodified lines
298	(unsigned long long)xop->dst_lba);	298	(unsigned long long)xop->dst_lba);
299		299
300	if (dc != 0) {	300	if (dc != 0) {
301	xop->dbl = (desc[29] << 16) & 0xff;	301	xop->dbl = (desc[29] & 0xff) << 16;
302	xop->dbl \|= (desc[30] << 8) & 0xff;	302	xop->dbl \|= (desc[30] & 0xff) << 8;
303	xop->dbl \|= desc[31] & 0xff;	303	xop->dbl \|= desc[31] & 0xff;
304		304
305	pr_debug("XCOPY seg desc 0x02: DC=1 w/ dbl: %u\n", xop->dbl);	305	pr_debug("XCOPY seg desc 0x02: DC=1 w/ dbl: %u\n", xop->dbl);

drivers/tty/hvc/hvc_xen.c+1−0

@@ -636,6 +636,7 @@ struct console xenboot_console = { · 635 unmodified lines
636	.name = "xenboot",	636	.name = "xenboot",
637	.write = xenboot_write_console,	637	.write = xenboot_write_console,
638	.flags = CON_PRINTBUFFER \| CON_BOOT \| CON_ANYTIME,	638	.flags = CON_PRINTBUFFER \| CON_BOOT \| CON_ANYTIME,
		639	.index = -1,
639	};	640	};
640	#endif /* CONFIG_EARLY_PRINTK */	641	#endif /* CONFIG_EARLY_PRINTK */
641		642

drivers/tty/n_tty.c+27−22

@@ -1758,8 +1758,7 @@ static void n_tty_set_termios(struct tty_struct tty, struct ktermios old) · 1757 unmodified lines
1758	canon_change = (old->c_lflag ^ tty->termios.c_lflag) & ICANON;	1758	canon_change = (old->c_lflag ^ tty->termios.c_lflag) & ICANON;
1759	if (canon_change) {	1759	if (canon_change) {
1760	bitmap_zero(ldata->read_flags, N_TTY_BUF_SIZE);	1760	bitmap_zero(ldata->read_flags, N_TTY_BUF_SIZE);
1761	ldata->line_start = 0;	1761	ldata->line_start = ldata->canon_head = ldata->read_tail;
1762	ldata->canon_head = ldata->read_tail;
1763	ldata->erasing = 0;	1762	ldata->erasing = 0;
1764	ldata->lnext = 0;	1763	ldata->lnext = 0;
1765	}	1764	}
@@ -2184,28 +2183,34 @@ static ssize_t n_tty_read(struct tty_struct tty, struct file file, · 418 unmodified lines
2184		2183
2185	if (!input_available_p(tty, 0)) {	2184	if (!input_available_p(tty, 0)) {
2186	if (test_bit(TTY_OTHER_CLOSED, &tty->flags)) {	2185	if (test_bit(TTY_OTHER_CLOSED, &tty->flags)) {
2187	retval = -EIO;	2186	up_read(&tty->termios_rwsem);
2188	break;	2187	tty_flush_to_ldisc(tty);
2189	}	2188	down_read(&tty->termios_rwsem);
2190	if (tty_hung_up_p(file))	2189	if (!input_available_p(tty, 0)) {
2191	break;	2190	retval = -EIO;
2192	if (!timeout)	2191	break;
2193	break;	2192	}
2194	if (file->f_flags & O_NONBLOCK) {	2193	} else {
2195	retval = -EAGAIN;	2194	if (tty_hung_up_p(file))
2196	break;	2195	break;
2197	}	2196	if (!timeout)
2198	if (signal_pending(current)) {	2197	break;
2199	retval = -ERESTARTSYS;	2198	if (file->f_flags & O_NONBLOCK) {
2200	break;	2199	retval = -EAGAIN;
2201	}	2200	break;
2202	n_tty_set_room(tty);	2201	}
2203	up_read(&tty->termios_rwsem);	2202	if (signal_pending(current)) {
		2203	retval = -ERESTARTSYS;
		2204	break;
		2205	}
		2206	n_tty_set_room(tty);
		2207	up_read(&tty->termios_rwsem);
2204		2208
2205	timeout = schedule_timeout(timeout);	2209	timeout = schedule_timeout(timeout);
2206		2210
2207	down_read(&tty->termios_rwsem);	2211	down_read(&tty->termios_rwsem);
2208	continue;	2212	continue;
		2213	}
2209	}	2214	}
2210	__set_current_state(TASK_RUNNING);	2215	__set_current_state(TASK_RUNNING);
2211		2216

drivers/tty/serial/pch_uart.c+3−10

 static int dma_push_rx(struct eg20t_port *priv, int size)
 {
-	struct tty_struct *tty;
 	int room;
 	struct uart_port *port = &priv->port;
 	struct tty_port *tport = &port->state->port;
-	port = &priv->port;
-	tty = tty_port_tty_get(tport);
-	if (!tty) {
-		dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
-		return 0;
-	}
 	room = tty_buffer_request_room(tport, size);
 	if (room < size)
 		dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 			 size - room);
 	if (!room)
-		return room;
+		return 0;
 	tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 	port->icount.rx += room;
-	tty_kref_put(tty);
 	return room;
 }
 	if (tty == NULL) {
 		for (i = 0; error_msg[i] != NULL; i++)
 			dev_err(&priv->pdev->dev, error_msg[i]);
+	} else {
+		tty_kref_put(tty);
 	}
 }

drivers/tty/serial/serial-tegra.c+3−1

 static void tegra_uart_stop_rx(struct uart_port *u)
 {
 	struct tegra_uart_port *tup = to_tegra_uport(u);
-	struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
+	struct tty_struct *tty;
 	struct tty_port *port = &u->state->port;
 	struct dma_tx_state state;
 	unsigned long ier;
 	if (!tup->rx_in_progress)
 		return;
+	tty = tty_port_tty_get(&tup->uport.state->port);
 	tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
 	ier = tup->ier_shadow;

drivers/tty/tty_ioctl.c+3−0

 		}
 		return 0;
 	case TCFLSH:
+		retval = tty_check_change(tty);
+		if (retval)
+			return retval;
 		return __tty_perform_flush(tty, arg);
 	default:
 		/* Try the mode commands */

drivers/usb/chipidea/Kconfig+1−1

@@ -1,6 +1,6 @@
1	config USB_CHIPIDEA	1	config USB_CHIPIDEA
2	tristate "ChipIdea Highspeed Dual Role Controller"	2	tristate "ChipIdea Highspeed Dual Role Controller"
3	depends on (USB_EHCI_HCD && USB_GADGET) \|\| (USB_EHCI_HCD && !USB_GADGET) \|\| (!USB_EHCI_HCD && USB_GADGET)	3	depends on ((USB_EHCI_HCD && USB_GADGET) \|\| (USB_EHCI_HCD && !USB_GADGET) \|\| (!USB_EHCI_HCD && USB_GADGET)) && HAS_DMA
4	help	4	help
5	Say Y here if your system has a dual role high speed USB	5	Say Y here if your system has a dual role high speed USB
6	controller based on ChipIdea silicon IP. Currently, only the	6	controller based on ChipIdea silicon IP. Currently, only the

drivers/usb/chipidea/ci_hdrc_imx.c+5−2

 		if (ret) {
 			dev_err(&pdev->dev, "usbmisc init failed, ret=%d\n",
 					ret);
-			goto err_clk;
+			goto err_phy;
 		}
 	}
 		dev_err(&pdev->dev,
 			"Can't register ci_hdrc platform device, err=%d\n",
 			ret);
-		goto err_clk;
+		goto err_phy;
 	}
 	if (data->usbmisc_data) {
 disable_device:
 	ci_hdrc_remove_device(data->ci_pdev);
+err_phy:
+	if (data->phy)
+		usb_phy_shutdown(data->phy);
 err_clk:
 	clk_disable_unprepare(data->clk);
 	return ret;

drivers/usb/chipidea/ci_hdrc_pci.c+6−1

 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829),
 		.driver_data = (kernel_ulong_t)&penwell_pci_platdata,
 	},
-	{ 0, 0, 0, 0, 0, 0, 0 /* end: all zeroes */ }
+	{
+		/* Intel Clovertrail */
+		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006),
+		.driver_data = (kernel_ulong_t)&penwell_pci_platdata,
+	},
+	{ 0 } /* end: all zeroes */
 };
 MODULE_DEVICE_TABLE(pci, ci_hdrc_pci_id_table);

drivers/usb/chipidea/core.c+1−0

@@ -605,6 +605,7 @@ static int ci_hdrc_remove(struct platform_device *pdev) · 604 unmodified lines
605	dbg_remove_files(ci);	605	dbg_remove_files(ci);
606	free_irq(ci->irq, ci);	606	free_irq(ci->irq, ci);
607	ci_role_destroy(ci);	607	ci_role_destroy(ci);
		608	kfree(ci->hw_bank.regmap);
608		609
609	return 0;	610	return 0;
610	}	611	}

drivers/usb/chipidea/udc.c+3−1

 	for (i = 0; i < ci->hw_ep_max; i++) {
 		struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
+		if (hwep->pending_td)
+			free_pending_td(hwep);
 		dma_pool_free(ci->qh_pool, hwep->qh.ptr, hwep->qh.dma);
 	}
 }
 		if (ci->platdata->notify_event)
 			ci->platdata->notify_event(ci,
 			CI_HDRC_CONTROLLER_STOPPED_EVENT);
-		ci->driver = NULL;
 		spin_unlock_irqrestore(&ci->lock, flags);
 		_gadget_stop_activity(&ci->gadget);
 		spin_lock_irqsave(&ci->lock, flags);
 		pm_runtime_put(&ci->gadget.dev);
 	}
+	ci->driver = NULL;
 	spin_unlock_irqrestore(&ci->lock, flags);
 	return 0;

drivers/usb/core/devio.c+16−0

@@ -742,6 +742,22 @@ static int check_ctrlrecip(struct dev_state *ps, unsigned int requesttype, · 741 unmodified lines
742	if ((index & ~USB_DIR_IN) == 0)	742	if ((index & ~USB_DIR_IN) == 0)
743	return 0;	743	return 0;
744	ret = findintfep(ps->dev, index);	744	ret = findintfep(ps->dev, index);
		745	if (ret < 0) {
		746	/*
		747	* Some not fully compliant Win apps seem to get
		748	* index wrong and have the endpoint number here
		749	* rather than the endpoint address (with the
		750	* correct direction). Win does let this through,
		751	* so we'll not reject it here but leave it to
		752	* the device to not break KVM. But we warn.
		753	*/
		754	ret = findintfep(ps->dev, index ^ 0x80);
		755	if (ret >= 0)
		756	dev_info(&ps->dev->dev,
		757	"%s: process %i (%s) requesting ep %02x but needs %02x\n",
		758	__func__, task_pid_nr(current),
		759	current->comm, index, index ^ 0x80);
		760	}
745	if (ret >= 0)	761	if (ret >= 0)
746	ret = checkintf(ps, ret);	762	ret = checkintf(ps, ret);
747	break;	763	break;

drivers/usb/core/hub.c+3−0

@@ -3426,6 +3426,9 @@ static int usb_req_set_sel(struct usb_device *udev, enum usb3_link_state state) · 3425 unmodified lines
3426	unsigned long long u2_pel;	3426	unsigned long long u2_pel;
3427	int ret;	3427	int ret;
3428		3428
		3429	if (udev->state != USB_STATE_CONFIGURED)
		3430	return 0;
		3431
3429	/* Convert SEL and PEL stored in ns to us */	3432	/* Convert SEL and PEL stored in ns to us */
3430	u1_sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);	3433	u1_sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
3431	u1_pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);	3434	u1_pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);

drivers/usb/dwc3/Kconfig+0−1

@@ -1,7 +1,6 @@
1	config USB_DWC3	1	config USB_DWC3
2	tristate "DesignWare USB3 DRD Core Support"	2	tristate "DesignWare USB3 DRD Core Support"
3	depends on (USB \|\| USB_GADGET) && HAS_DMA	3	depends on (USB \|\| USB_GADGET) && HAS_DMA
4	depends on EXTCON
5	select USB_XHCI_PLATFORM if USB_SUPPORT && USB_XHCI_HCD	4	select USB_XHCI_PLATFORM if USB_SUPPORT && USB_XHCI_HCD
6	help	5	help
7	Say Y or M here if your system has a Dual Role SuperSpeed	6	Say Y or M here if your system has a Dual Role SuperSpeed

drivers/usb/dwc3/dwc3-pci.c+4−0

 /* FIXME define these in <linux/pci_ids.h> */
 #define PCI_VENDOR_ID_SYNOPSYS		0x16c3
 #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3	0xabcd
+#define PCI_DEVICE_ID_INTEL_BYT		0x0f37
+#define PCI_DEVICE_ID_INTEL_MRFLD	0x119e
 struct dwc3_pci {
 	struct device		*dev;
 		PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
 				PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
 	},
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
 	{  }	/* Terminating Entry */
 };
 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);

drivers/usb/dwc3/gadget.c+2−4

 	ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
 	if (ret) {
 		dev_err(dwc->dev, "failed to register udc\n");
-		goto err5;
+		goto err4;
 	}
 	return 0;
-err5:
-	dwc3_gadget_free_endpoints(dwc);
 err4:
+	dwc3_gadget_free_endpoints(dwc);
 	dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
 			dwc->ep0_bounce, dwc->ep0_bounce_addr);

drivers/usb/gadget/cdc2.c+1−18

 		c->bmAttributes |= USB_CONFIG_ATT_WAKEUP;
 	}
-	fi_ecm = usb_get_function_instance("ecm");
-	if (IS_ERR(fi_ecm)) {
-		status = PTR_ERR(fi_ecm);
-		goto err_func_ecm;
-	}
 	f_ecm = usb_get_function(fi_ecm);
 	if (IS_ERR(f_ecm)) {
 		status = PTR_ERR(f_ecm);
 	if (status)
 		goto err_add_ecm;
-	fi_serial = usb_get_function_instance("acm");
-	if (IS_ERR(fi_serial)) {
-		status = PTR_ERR(fi_serial);
-		goto err_get_acm;
-	}
 	f_acm = usb_get_function(fi_serial);
 	if (IS_ERR(f_acm)) {
 		status = PTR_ERR(f_acm);
-		goto err_func_acm;
+		goto err_get_acm;
 	}
 	status = usb_add_function(c, f_acm);
 	if (status)
 		goto err_add_acm;
 	return 0;
 err_add_acm:
 	usb_put_function(f_acm);
-err_func_acm:
-	usb_put_function_instance(fi_serial);
 err_get_acm:
 	usb_remove_function(c, f_ecm);
 err_add_ecm:
 	usb_put_function(f_ecm);
 err_get_ecm:
-	usb_put_function_instance(fi_ecm);
-err_func_ecm:
 	return status;
 }

drivers/usb/gadget/dummy_hcd.c+4−3

 	struct dummy_hcd	*dum_hcd = gadget_to_dummy_hcd(g);
 	struct dummy		*dum = dum_hcd->dum;
-	dev_dbg(udc_dev(dum), "unregister gadget driver '%s'\n",
+	if (driver)
-			driver->driver.name);
+		dev_dbg(udc_dev(dum), "unregister gadget driver '%s'\n",
+				driver->driver.name);
 	dum->driver = NULL;
 {
 	struct dummy	*dum = platform_get_drvdata(pdev);
-	usb_del_gadget_udc(&dum->gadget);
 	device_remove_file(&dum->gadget.dev, &dev_attr_function);
+	usb_del_gadget_udc(&dum->gadget);
 	return 0;
 }

drivers/usb/gadget/f_ecm.c+1−1

@@ -995,7 +995,7 @@ static void ecm_unbind(struct usb_configuration c, struct usb_function f) · 994 unmodified lines
995	usb_ep_free_request(ecm->notify, ecm->notify_req);	995	usb_ep_free_request(ecm->notify, ecm->notify_req);
996	}	996	}
997		997
998	struct usb_function ecm_alloc(struct usb_function_instance fi)	998	static struct usb_function ecm_alloc(struct usb_function_instance fi)
999	{	999	{
1000	struct f_ecm *ecm;	1000	struct f_ecm *ecm;
1001	struct f_ecm_opts *opts;	1001	struct f_ecm_opts *opts;

drivers/usb/gadget/f_eem.c+1−1

@@ -624,7 +624,7 @@ static void eem_unbind(struct usb_configuration c, struct usb_function f) · 623 unmodified lines
624	usb_free_all_descriptors(f);	624	usb_free_all_descriptors(f);
625	}	625	}
626		626
627	struct usb_function eem_alloc(struct usb_function_instance fi)	627	static struct usb_function eem_alloc(struct usb_function_instance fi)
628	{	628	{
629	struct f_eem *eem;	629	struct f_eem *eem;
630	struct f_eem_opts *opts;	630	struct f_eem_opts *opts;

drivers/usb/gadget/f_fs.c+28−34

@@ -1034,37 +1034,19 @@ struct ffs_sb_fill_data { · 1033 unmodified lines
1034	struct ffs_file_perms perms;	1034	struct ffs_file_perms perms;
1035	umode_t root_mode;	1035	umode_t root_mode;
1036	const char *dev_name;	1036	const char *dev_name;
1037	union {	1037	struct ffs_data *ffs_data;
1038	/* set by ffs_fs_mount(), read by ffs_sb_fill() */
1039	void *private_data;
1040	/* set by ffs_sb_fill(), read by ffs_fs_mount */
1041	struct ffs_data *ffs_data;
1042	};
1043	};	1038	};
1044		1039
1045	static int ffs_sb_fill(struct super_block sb, void _data, int silent)	1040	static int ffs_sb_fill(struct super_block sb, void _data, int silent)
1046	{	1041	{
1047	struct ffs_sb_fill_data *data = _data;	1042	struct ffs_sb_fill_data *data = _data;
1048	struct inode *inode;	1043	struct inode *inode;
1049	struct ffs_data *ffs;	1044	struct ffs_data *ffs = data->ffs_data;
1050		1045
1051	ENTER();	1046	ENTER();
1052		1047
1053	/* Initialise data */
1054	ffs = ffs_data_new();
1055	if (unlikely(!ffs))
1056	goto Enomem;
1057
1058	ffs->sb = sb;	1048	ffs->sb = sb;
1059	ffs->dev_name = kstrdup(data->dev_name, GFP_KERNEL);	1049	data->ffs_data = NULL;
1060	if (unlikely(!ffs->dev_name))
1061	goto Enomem;
1062	ffs->file_perms = data->perms;
1063	ffs->private_data = data->private_data;
1064
1065	/* used by the caller of this function */
1066	data->ffs_data = ffs;
1067
1068	sb->s_fs_info = ffs;	1050	sb->s_fs_info = ffs;
1069	sb->s_blocksize = PAGE_CACHE_SIZE;	1051	sb->s_blocksize = PAGE_CACHE_SIZE;
1070	sb->s_blocksize_bits = PAGE_CACHE_SHIFT;	1052	sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
@@ -1080,17 +1062,14 @@ static int ffs_sb_fill(struct super_block sb, void _data, int silent) · 9 unmodified lines
1080	&data->perms);	1062	&data->perms);
1081	sb->s_root = d_make_root(inode);	1063	sb->s_root = d_make_root(inode);
1082	if (unlikely(!sb->s_root))	1064	if (unlikely(!sb->s_root))
1083	goto Enomem;	1065	return -ENOMEM;
1084		1066
1085	/* EP0 file */	1067	/* EP0 file */
1086	if (unlikely(!ffs_sb_create_file(sb, "ep0", ffs,	1068	if (unlikely(!ffs_sb_create_file(sb, "ep0", ffs,
1087	&ffs_ep0_operations, NULL)))	1069	&ffs_ep0_operations, NULL)))
1088	goto Enomem;	1070	return -ENOMEM;
1089		1071
1090	return 0;	1072	return 0;
1091
1092	Enomem:
1093	return -ENOMEM;
1094	}	1073	}
1095		1074
1096	static int ffs_fs_parse_opts(struct ffs_sb_fill_data data, char opts)	1075	static int ffs_fs_parse_opts(struct ffs_sb_fill_data data, char opts)
@@ -1193,6 +1172,7 @@ ffs_fs_mount(struct file_system_type *t, int flags, · 96 unmodified lines
1193	struct dentry *rv;	1172	struct dentry *rv;
1194	int ret;	1173	int ret;
1195	void *ffs_dev;	1174	void *ffs_dev;
		1175	struct ffs_data *ffs;
1196		1176
1197	ENTER();	1177	ENTER();
1198		1178
@@ -1200,18 +1180,30 @@ ffs_fs_mount(struct file_system_type *t, int flags, · 1 unmodified line
1200	if (unlikely(ret < 0))	1180	if (unlikely(ret < 0))
1201	return ERR_PTR(ret);	1181	return ERR_PTR(ret);
1202		1182
		1183	ffs = ffs_data_new();
		1184	if (unlikely(!ffs))
		1185	return ERR_PTR(-ENOMEM);
		1186	ffs->file_perms = data.perms;
		1187
		1188	ffs->dev_name = kstrdup(dev_name, GFP_KERNEL);
		1189	if (unlikely(!ffs->dev_name)) {
		1190	ffs_data_put(ffs);
		1191	return ERR_PTR(-ENOMEM);
		1192	}
		1193
1203	ffs_dev = functionfs_acquire_dev_callback(dev_name);	1194	ffs_dev = functionfs_acquire_dev_callback(dev_name);
1204	if (IS_ERR(ffs_dev))	1195	if (IS_ERR(ffs_dev)) {
1205	return ffs_dev;	1196	ffs_data_put(ffs);
		1197	return ERR_CAST(ffs_dev);
		1198	}
		1199	ffs->private_data = ffs_dev;
		1200	data.ffs_data = ffs;
1206		1201
1207	data.dev_name = dev_name;
1208	data.private_data = ffs_dev;
1209	rv = mount_nodev(t, flags, &data, ffs_sb_fill);	1202	rv = mount_nodev(t, flags, &data, ffs_sb_fill);
1210		1203	if (IS_ERR(rv) && data.ffs_data) {
1211	/* data.ffs_data is set by ffs_sb_fill */
1212	if (IS_ERR(rv))
1213	functionfs_release_dev_callback(data.ffs_data);	1204	functionfs_release_dev_callback(data.ffs_data);
1214		1205	ffs_data_put(data.ffs_data);
		1206	}
1215	return rv;	1207	return rv;
1216	}	1208	}
1217		1209
@@ -2264,6 +2256,8 @@ static int ffs_func_bind(struct usb_configuration *c, · 1046 unmodified lines
2264	data->raw_descs + ret,	2256	data->raw_descs + ret,
2265	(sizeof data->raw_descs) - ret,	2257	(sizeof data->raw_descs) - ret,
2266	__ffs_func_bind_do_descs, func);	2258	__ffs_func_bind_do_descs, func);
		2259	if (unlikely(ret < 0))
		2260	goto error;
2267	}	2261	}
2268		2262
2269	/*	2263	/*

drivers/usb/gadget/f_mass_storage.c+2−0

 		/* Disable the endpoints */
 		if (fsg->bulk_in_enabled) {
 			usb_ep_disable(fsg->bulk_in);
+			fsg->bulk_in->driver_data = NULL;
 			fsg->bulk_in_enabled = 0;
 		}
 		if (fsg->bulk_out_enabled) {
 			usb_ep_disable(fsg->bulk_out);
+			fsg->bulk_out->driver_data = NULL;
 			fsg->bulk_out_enabled = 0;
 		}

drivers/usb/gadget/fotg210-udc.c+1−1

@@ -1214,6 +1214,6 @@ static struct platform_driver fotg210_driver = { · 1213 unmodified lines
1214		1214
1215	module_platform_driver(fotg210_driver);	1215	module_platform_driver(fotg210_driver);
1216		1216
1217	MODULE_AUTHOR("Yuan-Hsin Chen <yhchen@faraday-tech.com>");	1217	MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
1218	MODULE_LICENSE("GPL");	1218	MODULE_LICENSE("GPL");
1219	MODULE_DESCRIPTION(DRIVER_DESC);	1219	MODULE_DESCRIPTION(DRIVER_DESC);

drivers/usb/gadget/fusb300_udc.c+1−1

@@ -22,7 +22,7 @@ · 21 unmodified lines
22		22
23	MODULE_DESCRIPTION("FUSB300 USB gadget driver");	23	MODULE_DESCRIPTION("FUSB300 USB gadget driver");
24	MODULE_LICENSE("GPL");	24	MODULE_LICENSE("GPL");
25	MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>");	25	MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
26	MODULE_ALIAS("platform:fusb300_udc");	26	MODULE_ALIAS("platform:fusb300_udc");
27		27
28	#define DRIVER_VERSION "20 October 2010"	28	#define DRIVER_VERSION "20 October 2010"

drivers/usb/gadget/multi.c+4−4

@@ -179,7 +179,7 @@ err_conf: · 178 unmodified lines
179	return ret;	179	return ret;
180	}	180	}
181		181
182	static int rndis_config_register(struct usb_composite_dev *cdev)	182	static __ref int rndis_config_register(struct usb_composite_dev *cdev)
183	{	183	{
184	static struct usb_configuration config = {	184	static struct usb_configuration config = {
185	.bConfigurationValue = MULTI_RNDIS_CONFIG_NUM,	185	.bConfigurationValue = MULTI_RNDIS_CONFIG_NUM,
@@ -194,7 +194,7 @@ static int rndis_config_register(struct usb_composite_dev *cdev) · 8 unmodified lines
194		194
195	#else	195	#else
196		196
197	static int rndis_config_register(struct usb_composite_dev *cdev)	197	static __ref int rndis_config_register(struct usb_composite_dev *cdev)
198	{	198	{
199	return 0;	199	return 0;
200	}	200	}
@@ -241,7 +241,7 @@ err_conf: · 40 unmodified lines
241	return ret;	241	return ret;
242	}	242	}
243		243
244	static int cdc_config_register(struct usb_composite_dev *cdev)	244	static __ref int cdc_config_register(struct usb_composite_dev *cdev)
245	{	245	{
246	static struct usb_configuration config = {	246	static struct usb_configuration config = {
247	.bConfigurationValue = MULTI_CDC_CONFIG_NUM,	247	.bConfigurationValue = MULTI_CDC_CONFIG_NUM,
@@ -256,7 +256,7 @@ static int cdc_config_register(struct usb_composite_dev *cdev) · 8 unmodified lines
256		256
257	#else	257	#else
258		258
259	static int cdc_config_register(struct usb_composite_dev *cdev)	259	static __ref int cdc_config_register(struct usb_composite_dev *cdev)
260	{	260	{
261	return 0;	261	return 0;
262	}	262	}

drivers/usb/gadget/mv_u3d_core.c+3−0

 	struct mv_u3d_ep *ep;
 	struct mv_u3d_ep_context *ep_context;
 	u32 epxcr, direction;
+	unsigned long flags;
 	if (!_ep)
 		return -EINVAL;
 	direction = mv_u3d_ep_dir(ep);
 	/* nuke all pending requests (does flush) */
+	spin_lock_irqsave(&u3d->lock, flags);
 	mv_u3d_nuke(ep, -ESHUTDOWN);
+	spin_unlock_irqrestore(&u3d->lock, flags);
 	/* Disable the endpoint for Rx or Tx and reset the endpoint type */
 	if (direction == MV_U3D_EP_DIR_OUT) {

drivers/usb/gadget/pxa25x_udc.c+5−4

 /*
  *	probe - binds to the platform device
  */
-static int __init pxa25x_udc_probe(struct platform_device *pdev)
+static int pxa25x_udc_probe(struct platform_device *pdev)
 {
 	struct pxa25x_udc *dev = &memory;
 	int retval, irq;
 	pullup_off();
 }
-static int __exit pxa25x_udc_remove(struct platform_device *pdev)
+static int pxa25x_udc_remove(struct platform_device *pdev)
 {
 	struct pxa25x_udc *dev = platform_get_drvdata(pdev);
 static struct platform_driver udc_driver = {
 	.shutdown	= pxa25x_udc_shutdown,
-	.remove		= __exit_p(pxa25x_udc_remove),
+	.probe		= pxa25x_udc_probe,
+	.remove		= pxa25x_udc_remove,
 	.suspend	= pxa25x_udc_suspend,
 	.resume		= pxa25x_udc_resume,
 	.driver		= {
 	},
 };
-module_platform_driver_probe(udc_driver, pxa25x_udc_probe);
+module_platform_driver(udc_driver);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");

drivers/usb/gadget/s3c-hsotg.c+5−10

 	 * FIFO, requests of >512 cause the endpoint to get stuck with a
 	 * fragment of the end of the transfer in it.
 	 */
-	if (can_write > 512)
+	if (can_write > 512 && !periodic)
 		can_write = 512;
 	/*
 	if (gintsts & GINTSTS_ErlySusp) {
 		dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
 		writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
-		s3c_hsotg_disconnect(hsotg);
 	}
 	/*
 	if (!hsotg)
 		return -ENODEV;
-	if (!driver || driver != hsotg->driver || !driver->unbind)
-		return -EINVAL;
 	/* all endpoints should be shutdown */
 	for (ep = 0; ep < hsotg->num_of_eps; ep++)
 		s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
 	spin_lock_irqsave(&hsotg->lock, flags);
 	s3c_hsotg_phy_disable(hsotg);
-	regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
-	hsotg->driver = NULL;
+	if (!driver)
+		hsotg->driver = NULL;
 	hsotg->gadget.speed = USB_SPEED_UNKNOWN;
 	spin_unlock_irqrestore(&hsotg->lock, flags);
-	dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
+	regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
-		 driver->driver.name);
 	return 0;
 }

drivers/usb/host/ehci-fsl.c+7−12

 	}
 	/* Enable USB controller, 83xx or 8536 */
-	if (pdata->have_sysif_regs)
+	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
 		setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
 	/* Don't need to set host mode here. It will be done by tdi_reset() */
 	case FSL_USB2_PHY_ULPI:
 		if (pdata->have_sysif_regs && pdata->controller_ver) {
 			/* controller version 1.6 or above */
+			clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
 			setbits32(non_ehci + FSL_SOC_USB_CTRL,
-					ULPI_PHY_CLK_SEL);
+				ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
-			/*
-			 * Due to controller issue of PHY_CLK_VALID in ULPI
-			 * mode, we set USB_CTRL_USB_EN before checking
-			 * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
-			 */
-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-					UTMI_PHY_EN, USB_CTRL_USB_EN);
 		}
 		portsc |= PORT_PTS_ULPI;
 		break;
 	if (pdata->have_sysif_regs && pdata->controller_ver &&
 	    (phy_mode == FSL_USB2_PHY_ULPI)) {
 		/* check PHY_CLK_VALID to get phy clk valid */
-		if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
+		if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
-				PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
+				PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
+				in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
 			printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
 			return -EINVAL;
 		}
 	 * generic hardware linkage
 	 */
 	.irq = ehci_irq,
-	.flags = HCD_USB2 | HCD_MEMORY | HCD_BH,
+	.flags = HCD_USB2 | HCD_MEMORY,
 	/*
 	 * basic lifecycle operations

drivers/usb/host/ehci-grlib.c+1−1

@@ -43,7 +43,7 @@ static const struct hc_driver ehci_grlib_hc_driver = { · 42 unmodified lines
43	* generic hardware linkage	43	* generic hardware linkage
44	*/	44	*/
45	.irq = ehci_irq,	45	.irq = ehci_irq,
46	.flags = HCD_MEMORY \| HCD_USB2 \| HCD_BH,	46	.flags = HCD_MEMORY \| HCD_USB2,
47		47
48	/*	48	/*
49	* basic lifecycle operations	49	* basic lifecycle operations

drivers/usb/host/ehci-hcd.c+1−1

@@ -1158,7 +1158,7 @@ static const struct hc_driver ehci_hc_driver = { · 1157 unmodified lines
1158	* generic hardware linkage	1158	* generic hardware linkage
1159	*/	1159	*/
1160	.irq = ehci_irq,	1160	.irq = ehci_irq,
1161	.flags = HCD_MEMORY \| HCD_USB2 \| HCD_BH,	1161	.flags = HCD_MEMORY \| HCD_USB2,
1162		1162
1163	/*	1163	/*
1164	* basic lifecycle operations	1164	* basic lifecycle operations

drivers/usb/host/ehci-mv.c+1−1

@@ -96,7 +96,7 @@ static const struct hc_driver mv_ehci_hc_driver = { · 95 unmodified lines
96	* generic hardware linkage	96	* generic hardware linkage
97	*/	97	*/
98	.irq = ehci_irq,	98	.irq = ehci_irq,
99	.flags = HCD_MEMORY \| HCD_USB2 \| HCD_BH,	99	.flags = HCD_MEMORY \| HCD_USB2,
100		100
101	/*	101	/*

1 more lines aren’t shown here.

drivers/usb/host/ehci-octeon.c+1−1

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drivers/usb/host/ehci-pci.c+1−1

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drivers/usb/host/ehci-pmcmsp.c+1−1

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drivers/usb/host/ehci-ppc-of.c+1−1

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drivers/usb/host/ehci-ps3.c+1−1

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drivers/usb/host/ehci-q.c+5−0

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drivers/usb/host/ehci-sead3.c+1−1

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drivers/usb/host/ehci-sh.c+1−1

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drivers/usb/host/ehci-tilegx.c+1−1

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drivers/usb/host/ehci-w90x900.c+1−1

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drivers/usb/host/ehci-xilinx-of.c+1−1

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drivers/usb/host/fsl-mph-dr-of.c+3−3

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drivers/usb/host/imx21-hcd.c+4−4

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drivers/usb/host/ohci-hcd.c+12−10

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drivers/usb/host/ohci-q.c+22−4

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drivers/usb/host/uhci-pci.c+1−1

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drivers/usb/host/uhci-q.c+8−4

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drivers/usb/host/xhci-hub.c+36−11

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drivers/usb/host/xhci-mem.c+2−0

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drivers/usb/host/xhci-pci.c+1−1

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drivers/usb/host/xhci-ring.c+35−2

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drivers/usb/host/xhci.c+5−20

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drivers/usb/host/xhci.h+11−0

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drivers/usb/musb/musb_dsps.c+3−0

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drivers/usb/musb/musb_gadget.c+4−1

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drivers/usb/phy/phy-gpio-vbus-usb.c+5−6

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drivers/usb/phy/phy-omap-usb3.c+1−1

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drivers/usb/serial/Kconfig+1−1

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drivers/usb/serial/option.c+3−0

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drivers/usb/serial/pl2303.c+32−11

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drivers/vhost/scsi.c+34−16

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drivers/vhost/vhost.c+3−1

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drivers/video/mmp/hw/mmp_ctrl.c+2−15

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drivers/video/of_display_timing.c+3−3

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drivers/video/omap2/displays-new/Kconfig+1−0

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drivers/video/omap2/displays-new/connector-analog-tv.c+1−1

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drivers/video/omap2/displays-new/connector-dvi.c+1−1

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drivers/video/omap2/displays-new/connector-hdmi.c+1−1

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drivers/video/omap2/dss/dispc.c+1−0

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drivers/xen/balloon.c+11−12

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fs/9p/v9fs.c+4−3

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fs/9p/vfs_inode_dotl.c+1−7

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fs/afs/dir.c+0−3

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fs/aio.c+37−15

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fs/autofs4/waitq.c+3−10

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fs/bio-integrity.c+1−1

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fs/bio.c+2−2

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fs/btrfs/async-thread.h+2−0

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fs/btrfs/btrfs_inode.h+4−1

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fs/btrfs/ctree.c+5−2

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fs/btrfs/extent-tree.c+30−27

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fs/btrfs/free-space-cache.c+47−20

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fs/btrfs/super.c+20−1

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fs/cachefiles/namei.c+1−1

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@@ -18,17 +18,17 @@ this byte for application use, with the following caveats: · 17 unmodified lines
18	parameters containing user virtual addresses must have	18	parameters containing user virtual addresses must have
19	their top byte cleared before trapping to the kernel.	19	their top byte cleared before trapping to the kernel.
20		20
21	(2) Tags are not guaranteed to be preserved when delivering	21	(2) Non-zero tags are not preserved when delivering signals.
22	signals. This means that signal handlers in applications	22	This means that signal handlers in applications making use
23	making use of tags cannot rely on the tag information for	23	of tags cannot rely on the tag information for user virtual
24	user virtual addresses being maintained for fields inside	24	addresses being maintained for fields inside siginfo_t.
25	siginfo_t. One exception to this rule is for signals raised	25	One exception to this rule is for signals raised in response
26	in response to debug exceptions, where the tag information	26	to watchpoint debug exceptions, where the tag information
27	will be preserved.	27	will be preserved.
28		28
29	(3) Special care should be taken when using tagged pointers,	29	(3) Special care should be taken when using tagged pointers,
30	since it is likely that C compilers will not hazard two	30	since it is likely that C compilers will not hazard two
31	addresses differing only in the upper bits.	31	virtual addresses differing only in the upper byte.
32		32
33	The architecture prevents the use of a tagged PC, so the upper byte will	33	The architecture prevents the use of a tagged PC, so the upper byte will
34	be set to a sign-extension of bit 55 on exception return.	34	be set to a sign-extension of bit 55 on exception return.

@@ -328,7 +328,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, · 327 unmodified lines
328	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");	328	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
329	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");	329	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
330	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");	330	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
331	clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");	331	clk_register_clkdev(clk[cpu_podf], NULL, "cpu0");
332	clk_register_clkdev(clk[iim_gate], "iim", NULL);	332	clk_register_clkdev(clk[iim_gate], "iim", NULL);
333	clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");	333	clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
334	clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");	334	clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
@@ -397,7 +397,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, · 62 unmodified lines
397	mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));	397	mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
398	clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,	398	clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
399	spdif_sel, ARRAY_SIZE(spdif_sel));	399	spdif_sel, ARRAY_SIZE(spdif_sel));
400	clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);	400	clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
401	clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);	401	clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
402	clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,	402	clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
403	mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));	403	mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));

@@ -663,18 +663,18 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) · 662 unmodified lines
663	/* pin banks of s5pv210 pin-controller */	663	/* pin banks of s5pv210 pin-controller */
664	static struct samsung_pin_bank s5pv210_pin_bank[] = {	664	static struct samsung_pin_bank s5pv210_pin_bank[] = {
665	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),	665	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
666	EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),	666	EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
667	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),	667	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
668	EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),	668	EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
669	EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),	669	EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
670	EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),	670	EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
671	EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),	671	EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
672	EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpe0", 0x1c),	672	EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
673	EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),	673	EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
674	EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpf0", 0x24),	674	EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
675	EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),	675	EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
676	EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),	676	EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
677	EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf3", 0x30),	677	EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
678	EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),	678	EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
679	EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),	679	EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
680	EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),	680	EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),