History

Merge tag 'tty-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

Pull tty/serial driver updates from Greg KH: "Here is the big tty/serial driver patchset for 4.11-rc1. Not much here, but a lot of little fixes and individual serial driver updates all over the subsystem. Majority are for the sh-sci driver and platform (the arch-specific changes have acks from the maintainer). The start of the "serial bus" code is here as well, but nothing is converted to use it yet. That work is still ongoing, hopefully will start to show up across different subsystems for 4.12 (bluetooth is one major place that will be used.) All of these have been in linux-next for a while with no reported issues" * tag 'tty-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (109 commits) tty: pl011: Work around QDF2400 E44 stuck BUSY bit atmel_serial: Use the fractional divider when possible tty: Remove extra include in HVC console tty framework serial: exar: Enable MSI support serial: exar: Move register defines from uapi header to consumer site serial: pci: Remove unused pci_boards entries serial: exar: Move Commtech adapters to 8250_exar as well serial: exar: Fix feature control register constants serial: exar: Fix initialization of EXAR registers for ports > 0 serial: exar: Fix mapping of port I/O resources serial: sh-sci: fix hardware RX trigger level setting tty/serial: atmel: ensure state is restored after suspending serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt serdev: ttyport: check whether tty_init_dev() fails serial: 8250_pci: make pciserial_detach_ports() static ARM: dts: STiH410-b2260: Enable HW flow-control ARM: dts: STiH407-family: Use new Pinctrl groups ARM: dts: STiH407-pinctrl: Add Pinctrl group for HW flow-control ARM: dts: STiH410-b2260: Identify the UART RTS line dt-bindings: serial: Update 'uart-has-rtscts' description ...

Linus Torvalds committed 9 years ago

Commit 37c85962 parents caa5942 d8a4995116 files · +3057 −1640Browse files

Unified · Split

116 files
  1. Documentation/admin-guide/kernel-parameters.txt +6 −0
  2. Documentation/devicetree/bindings/serial/8250.txt +1 −0
  3. Documentation/devicetree/bindings/serial/serial.txt +2 −1
  4. Documentation/devicetree/bindings/serial/slave-device.txt +36 −0
  5. MAINTAINERS +8 −0
  6. arch/arm/boot/dts/stih407-family.dtsi +1 −2
  7. arch/arm/boot/dts/stih407-pinctrl.dtsi +10 −2
  8. arch/arm/boot/dts/stih410-b2260.dts +5 −0
  9. arch/sh/kernel/cpu/sh2/setup-sh7619.c +3 −6
  10. arch/sh/kernel/cpu/sh2a/setup-mxg.c +1 −2
  11. arch/sh/kernel/cpu/sh2a/setup-sh7201.c +8 −16
  12. arch/sh/kernel/cpu/sh2a/setup-sh7203.c +4 −12
  13. arch/sh/kernel/cpu/sh2a/setup-sh7206.c +4 −8
  14. arch/sh/kernel/cpu/sh2a/setup-sh7264.c +8 −24
  15. arch/sh/kernel/cpu/sh2a/setup-sh7269.c +8 −24
  16. arch/sh/kernel/cpu/sh3/setup-sh7705.c +1 −5
  17. arch/sh/kernel/cpu/sh3/setup-sh770x.c +0 −10
  18. arch/sh/kernel/cpu/sh3/setup-sh7710.c +2 −6
  19. arch/sh/kernel/cpu/sh3/setup-sh7720.c +0 −4
  20. arch/sh/kernel/cpu/sh4/setup-sh4-202.c +1 −2
  21. arch/sh/kernel/cpu/sh4/setup-sh7750.c +2 −7
  22. arch/sh/kernel/cpu/sh4/setup-sh7760.c +11 −10
  23. arch/sh/kernel/cpu/sh4a/setup-sh7343.c +4 −8
  24. arch/sh/kernel/cpu/sh4a/setup-sh7366.c +1 −3
  25. arch/sh/kernel/cpu/sh4a/setup-sh7722.c +3 −6
  26. arch/sh/kernel/cpu/sh4a/setup-sh7723.c +3 −18
  27. arch/sh/kernel/cpu/sh4a/setup-sh7724.c +3 −18
  28. arch/sh/kernel/cpu/sh4a/setup-sh7734.c +6 −12
  29. arch/sh/kernel/cpu/sh4a/setup-sh7757.c +3 −6
  30. arch/sh/kernel/cpu/sh4a/setup-sh7763.c +3 −6
  31. arch/sh/kernel/cpu/sh4a/setup-sh7770.c +10 −20
  32. arch/sh/kernel/cpu/sh4a/setup-sh7780.c +2 −4
  33. arch/sh/kernel/cpu/sh4a/setup-sh7785.c +6 −12
  34. arch/sh/kernel/cpu/sh4a/setup-sh7786.c +6 −12
  35. arch/sh/kernel/cpu/sh4a/setup-shx3.c +3 −6
  36. arch/sh/kernel/cpu/sh5/setup-sh5.c +2 −2
  37. drivers/acpi/spcr.c +23 −0
  38. drivers/char/Kconfig +1 −0
  39. drivers/dma/hsu/pci.c +15 −2
  40. drivers/tty/Makefile +1 −0
  41. drivers/tty/goldfish.c +1 −1
  42. drivers/tty/hvc/hvc_console.c +0 −1
  43. drivers/tty/serdev/Kconfig +16 −0
  44. drivers/tty/serdev/Makefile +5 −0
  45. drivers/tty/serdev/core.c +421 −0
  46. drivers/tty/serdev/serdev-ttyport.c +226 −0
  47. drivers/tty/serial/8250/8250_dw.c +25 −3
  48. drivers/tty/serial/8250/8250_exar.c +487 −0
  49. drivers/tty/serial/8250/8250_gsc.c +4 −0
  50. drivers/tty/serial/8250/8250_hp300.c +1 −1
  51. drivers/tty/serial/8250/8250_lpss.c +2 −2
  52. drivers/tty/serial/8250/8250_mid.c +42 −3
  53. drivers/tty/serial/8250/8250_moxa.c +1 −0
  54. drivers/tty/serial/8250/8250_of.c +25 −69
  55. drivers/tty/serial/8250/8250_omap.c +17 −16
  56. drivers/tty/serial/8250/8250_pci.c +22 −493
  57. drivers/tty/serial/8250/8250_port.c +28 −4
  58. drivers/tty/serial/8250/Kconfig +8 −3
  59. drivers/tty/serial/8250/Makefile +1 −0
  60. drivers/tty/serial/Kconfig +1 −0
  61. drivers/tty/serial/amba-pl010.c +1 −1
  62. drivers/tty/serial/amba-pl011.c +61 −9
  63. drivers/tty/serial/ar933x_uart.c +1 −1
  64. drivers/tty/serial/atmel_serial.c +48 −3
  65. drivers/tty/serial/bfin_sport_uart.c +1 −1
  66. drivers/tty/serial/cpm_uart/cpm_uart_core.c +10 −8
  67. drivers/tty/serial/dz.c +1 −1
  68. drivers/tty/serial/efm32-uart.c +1 −1
  69. drivers/tty/serial/fsl_lpuart.c +17 −18
  70. drivers/tty/serial/icom.c +1 −1
  71. drivers/tty/serial/imx.c +18 −14
  72. drivers/tty/serial/ioc3_serial.c +1 −1
  73. drivers/tty/serial/ioc4_serial.c +1 −1
  74. drivers/tty/serial/ip22zilog.c +1 −1
  75. drivers/tty/serial/lantiq.c +33 −9
  76. drivers/tty/serial/lpc32xx_hs.c +1 −1
  77. drivers/tty/serial/max310x.c +1 −1
  78. drivers/tty/serial/meson_uart.c +1 −1
  79. drivers/tty/serial/mpsc.c +1 −1
  80. drivers/tty/serial/msm_serial.c +1 −0
  81. drivers/tty/serial/mxs-auart.c +3 −0
  82. drivers/tty/serial/omap-serial.c +56 −1
  83. drivers/tty/serial/pic32_uart.c +3 −3
  84. drivers/tty/serial/pmac_zilog.c +1 −1
  85. drivers/tty/serial/pnx8xxx_uart.c +1 −1
  86. drivers/tty/serial/pxa.c +1 −1
  87. drivers/tty/serial/samsung.c +9 −11
  88. drivers/tty/serial/samsung.h +0 −4
  89. drivers/tty/serial/serial-tegra.c +1 −1
  90. drivers/tty/serial/serial_txx9.c +1 −1
  91. drivers/tty/serial/sh-sci.c +578 −514
  92. drivers/tty/serial/sh-sci.h +9 −3
  93. drivers/tty/serial/sirfsoc_uart.c +1 −1
  94. drivers/tty/serial/sn_console.c +1 −1
  95. drivers/tty/serial/sprd_serial.c +1 −1
  96. drivers/tty/serial/st-asc.c +92 −9
  97. drivers/tty/serial/sunhv.c +1 −1
  98. drivers/tty/serial/sunzilog.c +1 −1
  99. drivers/tty/serial/vr41xx_siu.c +1 −1
  100. drivers/tty/serial/vt8500_serial.c +1 −1
  101. drivers/tty/serial/xilinx_uartps.c +9 −0
  102. drivers/tty/serial/zs.c +1 −1
  103. drivers/tty/tty_buffer.c +4 −15
  104. drivers/tty/tty_io.c +33 −19
  105. drivers/tty/tty_port.c +55 −10
  106. drivers/tty/vt/vt.c +9 −0
  107. drivers/video/console/Kconfig +24 −3
  108. drivers/video/console/vgacon.c +112 −52
  109. include/linux/console.h +4 −0
  110. include/linux/serdev.h +262 −0
  111. include/linux/serial_core.h +1 −1
  112. include/linux/serial_sci.h +0 −15
  113. include/linux/tty.h +10 −2
  114. include/uapi/linux/serial_core.h +2 −1
  115. include/uapi/linux/serial_reg.h +8 −18
  116. lib/Kconfig.debug +10 −0
Documentation/admin-guide/kernel-parameters.txt+6−0
@@ -957,6 +957,12 @@ · 956 unmodified lines
957957 serial port must already be setup and configured.
958958 Options are not yet supported.
959959
960+ lantiq,<addr>
961+ Start an early, polled-mode console on a lantiq serial
962+ (lqasc) port at the specified address. The serial port
963+ must already be setup and configured. Options are not
964+ yet supported.
965+
960966 lpuart,<addr>
961967 lpuart32,<addr>
962968 Use early console provided by Freescale LP UART driver
Documentation/devicetree/bindings/serial/8250.txt+1−0
@@ -19,6 +19,7 @@ Required properties: · 18 unmodified lines
1919 - "altr,16550-FIFO128"
2020 - "fsl,16550-FIFO64"
2121 - "fsl,ns16550"
22+ - "ti,da830-uart"
2223 - "serial" if the port type is unknown.
2324 - reg : offset and length of the register set for the device.
2425 - interrupts : should contain uart interrupt.
Documentation/devicetree/bindings/serial/serial.txt+2−1
@@ -23,7 +23,8 @@ Optional properties: · 22 unmodified lines
2323 they are available for use (wired and enabled by pinmux configuration).
2424 This depends on both the UART hardware and the board wiring.
2525 Note that this property is mutually-exclusive with "cts-gpios" and
26− "rts-gpios" above.
26+ "rts-gpios" above, unless support is provided to switch between modes
27+ dynamically.
2728
2829
2930 Examples:
Documentation/devicetree/bindings/serial/slave-device.txt+36−0
@@ -0,0 +1,36 @@
1+Serial Slave Device DT binding
2+
3+This documents the binding structure and common properties for serial
4+attached devices. Common examples include Bluetooth, WiFi, NFC and GPS
5+devices.
6+
7+Serial attached devices shall be a child node of the host UART device the
8+slave device is attached to. It is expected that the attached device is
9+the only child node of the UART device. The slave device node name shall
10+reflect the generic type of device for the node.
11+
12+Required Properties:
13+
14+- compatible : A string reflecting the vendor and specific device the node
15+ represents.
16+
17+Optional Properties:
18+
19+- max-speed : The maximum baud rate the device operates at. This should
20+ only be present if the maximum is less than the slave device
21+ can support. For example, a particular board has some signal
22+ quality issue or the host processor can't support higher
23+ baud rates.
24+
25+Example:
26+
27+serial@1234 {
28+ compatible = "ns16550a";
29+ interrupts = <1>;
30+
31+ bluetooth {
32+ compatible = "brcm,bcm43341-bt";
33+ interrupt-parent = <&gpio>;
34+ interrupts = <10>;
35+ };
36+};
MAINTAINERS+8−0
@@ -10927,6 +10927,14 @@ S: Maintained · 10926 unmodified lines
1092710927 F: Documentation/devicetree/bindings/serial/
1092810928 F: drivers/tty/serial/
1092910929
10930+SERIAL DEVICE BUS
10931+M: Rob Herring <robh@kernel.org>
10932+L: linux-serial@vger.kernel.org
10933+S: Maintained
10934+F: Documentation/devicetree/bindings/serial/slave-device.txt
10935+F: drivers/tty/serdev/
10936+F: include/linux/serdev.h
10937+
1093010938 SERIAL IR RECEIVER
1093110939 M: Sean Young <sean@mess.org>
1093210940 L: linux-media@vger.kernel.org
arch/arm/boot/dts/stih407-family.dtsi+1−2
@@ -222,9 +222,8 @@ · 221 unmodified lines
222222 compatible = "st,asc";
223223 reg = <0x9830000 0x2c>;
224224 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
225− pinctrl-names = "default";
226− pinctrl-0 = <&pinctrl_serial0>;
227225 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
226+ /* Pinctrl moved out to a per-board configuration */
228227
229228 status = "disabled";
230229 };
arch/arm/boot/dts/stih407-pinctrl.dtsi+10−2
@@ -465,8 +465,16 @@ · 464 unmodified lines
465465 serial0 {
466466 pinctrl_serial0: serial0-0 {
467467 st,pins {
468− tx = <&pio17 0 ALT1 OUT>;
469− rx = <&pio17 1 ALT1 IN>;
468+ tx = <&pio17 0 ALT1 OUT>;
469+ rx = <&pio17 1 ALT1 IN>;
470+ };
471+ };
472+ pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl {
473+ st,pins {
474+ tx = <&pio17 0 ALT1 OUT>;
475+ rx = <&pio17 1 ALT1 IN>;
476+ cts = <&pio17 2 ALT1 IN>;
477+ rts = <&pio17 3 ALT1 OUT>;
470478 };
471479 };
472480 };
arch/arm/boot/dts/stih410-b2260.dts+5−0
@@ -62,6 +62,11 @@ · 61 unmodified lines
6262 /* Low speed expansion connector */
6363 uart0: serial@9830000 {
6464 label = "LS-UART0";
65+ pinctrl-names = "default", "no-hw-flowctrl";
66+ pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>;
67+ pinctrl-1 = <&pinctrl_serial0>;
68+ rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>;
69+ uart-has-rtscts;
6570 status = "okay";
6671 };
6772
arch/sh/kernel/cpu/sh2/setup-sh7619.c+3−6
@@ -61,8 +61,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL, · 60 unmodified lines
6161 NULL, prio_registers, NULL);
6262
6363 static struct plat_sci_port scif0_platform_data = {
64− .flags = UPF_BOOT_AUTOCONF,
65− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
64+ .scscr = SCSCR_REIE,
6665 .type = PORT_SCIF,
6766 };
6867
@@ -82,8 +81,7 @@ static struct platform_device scif0_device = { · 13 unmodified lines
8281 };
8382
8483 static struct plat_sci_port scif1_platform_data = {
85− .flags = UPF_BOOT_AUTOCONF,
86− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
84+ .scscr = SCSCR_REIE,
8785 .type = PORT_SCIF,
8886 };
8987
@@ -103,8 +101,7 @@ static struct platform_device scif1_device = { · 13 unmodified lines
103101 };
104102
105103 static struct plat_sci_port scif2_platform_data = {
106− .flags = UPF_BOOT_AUTOCONF,
107− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
104+ .scscr = SCSCR_REIE,
108105 .type = PORT_SCIF,
109106 };
110107
arch/sh/kernel/cpu/sh2a/setup-mxg.c+1−2
@@ -129,8 +129,7 @@ static struct platform_device mtu2_device = { · 128 unmodified lines
129129 };
130130
131131 static struct plat_sci_port scif0_platform_data = {
132− .flags = UPF_BOOT_AUTOCONF,
133− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
132+ .scscr = SCSCR_REIE,
134133 .type = PORT_SCIF,
135134 };
136135
arch/sh/kernel/cpu/sh2a/setup-sh7201.c+8−16
@@ -178,8 +178,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, · 177 unmodified lines
178178 mask_registers, prio_registers, NULL);
179179
180180 static struct plat_sci_port scif0_platform_data = {
181− .flags = UPF_BOOT_AUTOCONF,
182− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
181+ .scscr = SCSCR_REIE,
183182 .type = PORT_SCIF,
184183 };
185184
@@ -199,8 +198,7 @@ static struct platform_device scif0_device = { · 13 unmodified lines
199198 };
200199
201200 static struct plat_sci_port scif1_platform_data = {
202− .flags = UPF_BOOT_AUTOCONF,
203− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
201+ .scscr = SCSCR_REIE,
204202 .type = PORT_SCIF,
205203 };
206204
@@ -220,8 +218,7 @@ static struct platform_device scif1_device = { · 13 unmodified lines
220218 };
221219
222220 static struct plat_sci_port scif2_platform_data = {
223− .flags = UPF_BOOT_AUTOCONF,
224− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
221+ .scscr = SCSCR_REIE,
225222 .type = PORT_SCIF,
226223 };
227224
@@ -241,8 +238,7 @@ static struct platform_device scif2_device = { · 13 unmodified lines
241238 };
242239
243240 static struct plat_sci_port scif3_platform_data = {
244− .flags = UPF_BOOT_AUTOCONF,
245− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
241+ .scscr = SCSCR_REIE,
246242 .type = PORT_SCIF,
247243 };
248244
@@ -262,8 +258,7 @@ static struct platform_device scif3_device = { · 13 unmodified lines
262258 };
263259
264260 static struct plat_sci_port scif4_platform_data = {
265− .flags = UPF_BOOT_AUTOCONF,
266− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
261+ .scscr = SCSCR_REIE,
267262 .type = PORT_SCIF,
268263 };
269264
@@ -283,8 +278,7 @@ static struct platform_device scif4_device = { · 13 unmodified lines
283278 };
284279
285280 static struct plat_sci_port scif5_platform_data = {
286− .flags = UPF_BOOT_AUTOCONF,
287− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
281+ .scscr = SCSCR_REIE,
288282 .type = PORT_SCIF,
289283 };
290284
@@ -304,8 +298,7 @@ static struct platform_device scif5_device = { · 13 unmodified lines
304298 };
305299
306300 static struct plat_sci_port scif6_platform_data = {
307− .flags = UPF_BOOT_AUTOCONF,
308− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
301+ .scscr = SCSCR_REIE,
309302 .type = PORT_SCIF,
310303 };
311304
@@ -325,8 +318,7 @@ static struct platform_device scif6_device = { · 13 unmodified lines
325318 };
326319
327320 static struct plat_sci_port scif7_platform_data = {
328− .flags = UPF_BOOT_AUTOCONF,
329− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
321+ .scscr = SCSCR_REIE,
330322 .type = PORT_SCIF,
331323 };
332324
arch/sh/kernel/cpu/sh2a/setup-sh7203.c+4−12
@@ -174,9 +174,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, · 173 unmodified lines
174174 mask_registers, prio_registers, NULL);
175175
176176 static struct plat_sci_port scif0_platform_data = {
177− .flags = UPF_BOOT_AUTOCONF,
178− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
179− SCSCR_REIE,
177+ .scscr = SCSCR_REIE,
180178 .type = PORT_SCIF,
181179 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
182180 };
@@ -197,9 +195,7 @@ static struct platform_device scif0_device = { · 14 unmodified lines
197195 };
198196
199197 static struct plat_sci_port scif1_platform_data = {
200− .flags = UPF_BOOT_AUTOCONF,
201− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
202− SCSCR_REIE,
198+ .scscr = SCSCR_REIE,
203199 .type = PORT_SCIF,
204200 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
205201 };
@@ -220,9 +216,7 @@ static struct platform_device scif1_device = { · 14 unmodified lines
220216 };
221217
222218 static struct plat_sci_port scif2_platform_data = {
223− .flags = UPF_BOOT_AUTOCONF,
224− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
225− SCSCR_REIE,
219+ .scscr = SCSCR_REIE,
226220 .type = PORT_SCIF,
227221 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
228222 };
@@ -243,9 +237,7 @@ static struct platform_device scif2_device = { · 14 unmodified lines
243237 };
244238
245239 static struct plat_sci_port scif3_platform_data = {
246− .flags = UPF_BOOT_AUTOCONF,
247− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
248− SCSCR_REIE,
240+ .scscr = SCSCR_REIE,
249241 .type = PORT_SCIF,
250242 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
251243 };
arch/sh/kernel/cpu/sh2a/setup-sh7206.c+4−8
@@ -134,8 +134,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, · 133 unmodified lines
134134 mask_registers, prio_registers, NULL);
135135
136136 static struct plat_sci_port scif0_platform_data = {
137− .flags = UPF_BOOT_AUTOCONF,
138− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
137+ .scscr = SCSCR_REIE,
139138 .type = PORT_SCIF,
140139 };
141140
@@ -155,8 +154,7 @@ static struct platform_device scif0_device = { · 13 unmodified lines
155154 };
156155
157156 static struct plat_sci_port scif1_platform_data = {
158− .flags = UPF_BOOT_AUTOCONF,
159− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157+ .scscr = SCSCR_REIE,
160158 .type = PORT_SCIF,
161159 };
162160
@@ -176,8 +174,7 @@ static struct platform_device scif1_device = { · 13 unmodified lines
176174 };
177175
178176 static struct plat_sci_port scif2_platform_data = {
179− .flags = UPF_BOOT_AUTOCONF,
180− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
177+ .scscr = SCSCR_REIE,
181178 .type = PORT_SCIF,
182179 };
183180
@@ -197,8 +194,7 @@ static struct platform_device scif2_device = { · 13 unmodified lines
197194 };
198195
199196 static struct plat_sci_port scif3_platform_data = {
200− .flags = UPF_BOOT_AUTOCONF,
201− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197+ .scscr = SCSCR_REIE,
202198 .type = PORT_SCIF,
203199 };
204200
arch/sh/kernel/cpu/sh2a/setup-sh7264.c+8−24
@@ -226,9 +226,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups, · 225 unmodified lines
226226 mask_registers, prio_registers, NULL);
227227
228228 static struct plat_sci_port scif0_platform_data = {
229− .flags = UPF_BOOT_AUTOCONF,
230− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
231− SCSCR_REIE | SCSCR_TOIE,
229+ .scscr = SCSCR_REIE,
232230 .type = PORT_SCIF,
233231 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
234232 };
@@ -252,9 +250,7 @@ static struct platform_device scif0_device = { · 17 unmodified lines
252250 };
253251
254252 static struct plat_sci_port scif1_platform_data = {
255− .flags = UPF_BOOT_AUTOCONF,
256− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
257− SCSCR_REIE | SCSCR_TOIE,
253+ .scscr = SCSCR_REIE,
258254 .type = PORT_SCIF,
259255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
260256 };
@@ -278,9 +274,7 @@ static struct platform_device scif1_device = { · 17 unmodified lines
278274 };
279275
280276 static struct plat_sci_port scif2_platform_data = {
281− .flags = UPF_BOOT_AUTOCONF,
282− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
283− SCSCR_REIE | SCSCR_TOIE,
277+ .scscr = SCSCR_REIE,
284278 .type = PORT_SCIF,
285279 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
286280 };
@@ -304,9 +298,7 @@ static struct platform_device scif2_device = { · 17 unmodified lines
304298 };
305299
306300 static struct plat_sci_port scif3_platform_data = {
307− .flags = UPF_BOOT_AUTOCONF,
308− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
309− SCSCR_REIE | SCSCR_TOIE,
301+ .scscr = SCSCR_REIE,
310302 .type = PORT_SCIF,
311303 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
312304 };
@@ -330,9 +322,7 @@ static struct platform_device scif3_device = { · 17 unmodified lines
330322 };
331323
332324 static struct plat_sci_port scif4_platform_data = {
333− .flags = UPF_BOOT_AUTOCONF,
334− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
335− SCSCR_REIE | SCSCR_TOIE,
325+ .scscr = SCSCR_REIE,
336326 .type = PORT_SCIF,
337327 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
338328 };
@@ -356,9 +346,7 @@ static struct platform_device scif4_device = { · 17 unmodified lines
356346 };
357347
358348 static struct plat_sci_port scif5_platform_data = {
359− .flags = UPF_BOOT_AUTOCONF,
360− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
361− SCSCR_REIE | SCSCR_TOIE,
349+ .scscr = SCSCR_REIE,
362350 .type = PORT_SCIF,
363351 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
364352 };
@@ -382,9 +370,7 @@ static struct platform_device scif5_device = { · 17 unmodified lines
382370 };
383371
384372 static struct plat_sci_port scif6_platform_data = {
385− .flags = UPF_BOOT_AUTOCONF,
386− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
387− SCSCR_REIE | SCSCR_TOIE,
373+ .scscr = SCSCR_REIE,
388374 .type = PORT_SCIF,
389375 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
390376 };
@@ -408,9 +394,7 @@ static struct platform_device scif6_device = { · 17 unmodified lines
408394 };
409395
410396 static struct plat_sci_port scif7_platform_data = {
411− .flags = UPF_BOOT_AUTOCONF,
412− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
413− SCSCR_REIE | SCSCR_TOIE,
397+ .scscr = SCSCR_REIE,
414398 .type = PORT_SCIF,
415399 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
416400 };
arch/sh/kernel/cpu/sh2a/setup-sh7269.c+8−24
@@ -248,9 +248,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups, · 247 unmodified lines
248248 mask_registers, prio_registers, NULL);
249249
250250 static struct plat_sci_port scif0_platform_data = {
251− .flags = UPF_BOOT_AUTOCONF,
252− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
253− SCSCR_REIE | SCSCR_TOIE,
251+ .scscr = SCSCR_REIE,
254252 .type = PORT_SCIF,
255253 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
256254 };
@@ -274,9 +272,7 @@ static struct platform_device scif0_device = { · 17 unmodified lines
274272 };
275273
276274 static struct plat_sci_port scif1_platform_data = {
277− .flags = UPF_BOOT_AUTOCONF,
278− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
279− SCSCR_REIE | SCSCR_TOIE,
275+ .scscr = SCSCR_REIE,
280276 .type = PORT_SCIF,
281277 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
282278 };
@@ -300,9 +296,7 @@ static struct platform_device scif1_device = { · 17 unmodified lines
300296 };
301297
302298 static struct plat_sci_port scif2_platform_data = {
303− .flags = UPF_BOOT_AUTOCONF,
304− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
305− SCSCR_REIE | SCSCR_TOIE,
299+ .scscr = SCSCR_REIE,
306300 .type = PORT_SCIF,
307301 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
308302 };
@@ -326,9 +320,7 @@ static struct platform_device scif2_device = { · 17 unmodified lines
326320 };
327321
328322 static struct plat_sci_port scif3_platform_data = {
329− .flags = UPF_BOOT_AUTOCONF,
330− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
331− SCSCR_REIE | SCSCR_TOIE,
323+ .scscr = SCSCR_REIE,
332324 .type = PORT_SCIF,
333325 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
334326 };
@@ -352,9 +344,7 @@ static struct platform_device scif3_device = { · 17 unmodified lines
352344 };
353345
354346 static struct plat_sci_port scif4_platform_data = {
355− .flags = UPF_BOOT_AUTOCONF,
356− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
357− SCSCR_REIE | SCSCR_TOIE,
347+ .scscr = SCSCR_REIE,
358348 .type = PORT_SCIF,
359349 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
360350 };
@@ -378,9 +368,7 @@ static struct platform_device scif4_device = { · 17 unmodified lines
378368 };
379369
380370 static struct plat_sci_port scif5_platform_data = {
381− .flags = UPF_BOOT_AUTOCONF,
382− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
383− SCSCR_REIE | SCSCR_TOIE,
371+ .scscr = SCSCR_REIE,
384372 .type = PORT_SCIF,
385373 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
386374 };
@@ -404,9 +392,7 @@ static struct platform_device scif5_device = { · 17 unmodified lines
404392 };
405393
406394 static struct plat_sci_port scif6_platform_data = {
407− .flags = UPF_BOOT_AUTOCONF,
408− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
409− SCSCR_REIE | SCSCR_TOIE,
395+ .scscr = SCSCR_REIE,
410396 .type = PORT_SCIF,
411397 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
412398 };
@@ -430,9 +416,7 @@ static struct platform_device scif6_device = { · 17 unmodified lines
430416 };
431417
432418 static struct plat_sci_port scif7_platform_data = {
433− .flags = UPF_BOOT_AUTOCONF,
434− .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
435− SCSCR_REIE | SCSCR_TOIE,
419+ .scscr = SCSCR_REIE,
436420 .type = PORT_SCIF,
437421 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
438422 };
arch/sh/kernel/cpu/sh3/setup-sh7705.c+1−5
@@ -70,9 +70,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL, · 69 unmodified lines
7070 NULL, prio_registers, NULL);
7171
7272 static struct plat_sci_port scif0_platform_data = {
73− .flags = UPF_BOOT_AUTOCONF,
74− .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
75− SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
73+ .scscr = SCSCR_CKE1,
7674 .type = PORT_SCIF,
7775 .ops = &sh770x_sci_port_ops,
7876 .regtype = SCIx_SH7705_SCIF_REGTYPE,
@@ -94,8 +92,6 @@ static struct platform_device scif0_device = { · 15 unmodified lines
9492 };
9593
9694 static struct plat_sci_port scif1_platform_data = {
97− .flags = UPF_BOOT_AUTOCONF,
98− .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
9995 .type = PORT_SCIF,
10096 .ops = &sh770x_sci_port_ops,
10197 .regtype = SCIx_SH7705_SCIF_REGTYPE,
arch/sh/kernel/cpu/sh3/setup-sh770x.c+0−10
@@ -109,12 +109,8 @@ static struct platform_device rtc_device = { · 108 unmodified lines
109109 };
110110
111111 static struct plat_sci_port scif0_platform_data = {
112− .port_reg = 0xa4000136,
113− .flags = UPF_BOOT_AUTOCONF,
114− .scscr = SCSCR_TE | SCSCR_RE,
115112 .type = PORT_SCI,
116113 .ops = &sh770x_sci_port_ops,
117− .regshift = 1,
118114 };
119115
120116 static struct resource scif0_resources[] = {
@@ -135,8 +131,6 @@ static struct platform_device scif0_device = { · 14 unmodified lines
135131 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
136132 defined(CONFIG_CPU_SUBTYPE_SH7709)
137133 static struct plat_sci_port scif1_platform_data = {
138− .flags = UPF_BOOT_AUTOCONF,
139− .scscr = SCSCR_TE | SCSCR_RE,
140134 .type = PORT_SCIF,
141135 .ops = &sh770x_sci_port_ops,
142136 .regtype = SCIx_SH3_SCIF_REGTYPE,
@@ -160,12 +154,8 @@ static struct platform_device scif1_device = { · 17 unmodified lines
160154 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
161155 defined(CONFIG_CPU_SUBTYPE_SH7709)
162156 static struct plat_sci_port scif2_platform_data = {
163− .port_reg = SCIx_NOT_SUPPORTED,
164− .flags = UPF_BOOT_AUTOCONF,
165− .scscr = SCSCR_TE | SCSCR_RE,
166157 .type = PORT_IRDA,
167158 .ops = &sh770x_sci_port_ops,
168− .regshift = 1,
169159 };
170160
171161 static struct resource scif2_resources[] = {
arch/sh/kernel/cpu/sh3/setup-sh7710.c+2−6
@@ -98,9 +98,7 @@ static struct platform_device rtc_device = { · 97 unmodified lines
9898 };
9999
100100 static struct plat_sci_port scif0_platform_data = {
101− .flags = UPF_BOOT_AUTOCONF,
102− .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
103− SCSCR_CKE1 | SCSCR_CKE0,
101+ .scscr = SCSCR_REIE | SCSCR_CKE1,
104102 .type = PORT_SCIF,
105103 };
106104
@@ -120,9 +118,7 @@ static struct platform_device scif0_device = { · 13 unmodified lines
120118 };
121119
122120 static struct plat_sci_port scif1_platform_data = {
123− .flags = UPF_BOOT_AUTOCONF,
124− .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
125− SCSCR_CKE1 | SCSCR_CKE0,
121+ .scscr = SCSCR_REIE | SCSCR_CKE1,
126122 .type = PORT_SCIF,
127123 };
128124
arch/sh/kernel/cpu/sh3/setup-sh7720.c+0−4
@@ -52,8 +52,6 @@ static struct platform_device rtc_device = { · 51 unmodified lines
5252 };
5353
5454 static struct plat_sci_port scif0_platform_data = {
55− .flags = UPF_BOOT_AUTOCONF,
56− .scscr = SCSCR_RE | SCSCR_TE,
5755 .type = PORT_SCIF,
5856 .ops = &sh7720_sci_port_ops,
5957 .regtype = SCIx_SH7705_SCIF_REGTYPE,
@@ -75,8 +73,6 @@ static struct platform_device scif0_device = { · 15 unmodified lines
7573 };
7674
7775 static struct plat_sci_port scif1_platform_data = {
78− .flags = UPF_BOOT_AUTOCONF,
79− .scscr = SCSCR_RE | SCSCR_TE,
8076 .type = PORT_SCIF,
8177 .ops = &sh7720_sci_port_ops,
8278 .regtype = SCIx_SH7705_SCIF_REGTYPE,
arch/sh/kernel/cpu/sh4/setup-sh4-202.c+1−2
@@ -17,8 +17,7 @@ · 16 unmodified lines
1717 #include <linux/io.h>
1818
1919 static struct plat_sci_port scif0_platform_data = {
20− .flags = UPF_BOOT_AUTOCONF,
21− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
20+ .scscr = SCSCR_REIE,
2221 .type = PORT_SCIF,
2322 };
2423
arch/sh/kernel/cpu/sh4/setup-sh7750.c+2−7
@@ -38,15 +38,11 @@ static struct platform_device rtc_device = { · 37 unmodified lines
3838 };
3939
4040 static struct plat_sci_port sci_platform_data = {
41− .port_reg = 0xffe0001C,
42− .flags = UPF_BOOT_AUTOCONF,
43− .scscr = SCSCR_TE | SCSCR_RE,
4441 .type = PORT_SCI,
45− .regshift = 2,
4642 };
4743
4844 static struct resource sci_resources[] = {
49− DEFINE_RES_MEM(0xffe00000, 0x100),
45+ DEFINE_RES_MEM(0xffe00000, 0x20),
5046 DEFINE_RES_IRQ(evt2irq(0x4e0)),
5147 };
5248
@@ -61,8 +57,7 @@ static struct platform_device sci_device = { · 8 unmodified lines
6157 };
6258
6359 static struct plat_sci_port scif_platform_data = {
64− .flags = UPF_BOOT_AUTOCONF,
65− .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
60+ .scscr = SCSCR_REIE,
6661 .type = PORT_SCIF,
6762 };
6863
arch/sh/kernel/cpu/sh4/setup-sh7760.c+11−10
@@ -128,8 +128,7 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, · 127 unmodified lines
128128 mask_registers, prio_registers, NULL);
129129
130130 static struct plat_sci_port scif0_platform_data = {
131− .flags = UPF_BOOT_AUTOCONF,
132− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
131+ .scscr = SCSCR_REIE,
133132 .type = PORT_SCIF,
134133 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
135134 };
@@ -153,9 +152,8 @@ static struct platform_device scif0_device = { · 17 unmodified lines
153152 };
154153
155154 static struct plat_sci_port scif1_platform_data = {
156− .flags = UPF_BOOT_AUTOCONF,
157155 .type = PORT_SCIF,
158− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
156+ .scscr = SCSCR_REIE,
159157 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
160158 };
161159
@@ -178,8 +176,7 @@ static struct platform_device scif1_device = { · 16 unmodified lines
178176 };
179177
180178 static struct plat_sci_port scif2_platform_data = {
181− .flags = UPF_BOOT_AUTOCONF,
182− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
179+ .scscr = SCSCR_REIE,
183180 .type = PORT_SCIF,
184181 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
185182 };
@@ -203,14 +200,18 @@ static struct platform_device scif2_device = { · 17 unmodified lines
203200 };
204201
205202 static struct plat_sci_port scif3_platform_data = {
206− .flags = UPF_BOOT_AUTOCONF,
207− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
203+ /*
204+ * This is actually a SIM card module serial port, based on an SCI with
205+ * additional registers. The sh-sci driver doesn't support the SIM port
206+ * type, declare it as a SCI. Don't declare the additional registers in
207+ * the memory resource or the driver will compute an incorrect regshift
208+ * value.
209+ */
208210 .type = PORT_SCI,
209− .regshift = 2,
210211 };
211212
212213 static struct resource scif3_resources[] = {
213− DEFINE_RES_MEM(0xfe480000, 0x100),
214+ DEFINE_RES_MEM(0xfe480000, 0x10),
214215 DEFINE_RES_IRQ(evt2irq(0xc00)),
215216 DEFINE_RES_IRQ(evt2irq(0xc20)),
216217 DEFINE_RES_IRQ(evt2irq(0xc40)),
arch/sh/kernel/cpu/sh4a/setup-sh7343.c+4−8
@@ -18,8 +18,7 @@ · 17 unmodified lines
1818
1919 /* Serial */
2020 static struct plat_sci_port scif0_platform_data = {
21− .flags = UPF_BOOT_AUTOCONF,
22− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
21+ .scscr = SCSCR_CKE1,
2322 .type = PORT_SCIF,
2423 };
2524
@@ -39,8 +38,7 @@ static struct platform_device scif0_device = { · 13 unmodified lines
3938 };
4039
4140 static struct plat_sci_port scif1_platform_data = {
42− .flags = UPF_BOOT_AUTOCONF,
43− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
41+ .scscr = SCSCR_CKE1,
4442 .type = PORT_SCIF,
4543 };
4644
@@ -60,8 +58,7 @@ static struct platform_device scif1_device = { · 13 unmodified lines
6058 };
6159
6260 static struct plat_sci_port scif2_platform_data = {
63− .flags = UPF_BOOT_AUTOCONF,
64− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
61+ .scscr = SCSCR_CKE1,
6562 .type = PORT_SCIF,
6663 };
6764
@@ -81,8 +78,7 @@ static struct platform_device scif2_device = { · 13 unmodified lines
8178 };
8279
8380 static struct plat_sci_port scif3_platform_data = {
84− .flags = UPF_BOOT_AUTOCONF,
85− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
81+ .scscr = SCSCR_CKE1,
8682 .type = PORT_SCIF,
8783 };
8884
arch/sh/kernel/cpu/sh4a/setup-sh7366.c+1−3
@@ -20,9 +20,7 @@ · 19 unmodified lines
2020 #include <asm/clock.h>
2121
2222 static struct plat_sci_port scif0_platform_data = {
23− .port_reg = 0xa405013e,
24− .flags = UPF_BOOT_AUTOCONF,
25− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23+ .scscr = SCSCR_REIE,
2624 .type = PORT_SCIF,
2725 };
2826
arch/sh/kernel/cpu/sh4a/setup-sh7722.c+3−6
@@ -179,8 +179,7 @@ struct platform_device dma_device = { · 178 unmodified lines
179179
180180 /* Serial */
181181 static struct plat_sci_port scif0_platform_data = {
182− .flags = UPF_BOOT_AUTOCONF,
183− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
182+ .scscr = SCSCR_REIE,
184183 .type = PORT_SCIF,
185184 .ops = &sh7722_sci_port_ops,
186185 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
@@ -202,8 +201,7 @@ static struct platform_device scif0_device = { · 15 unmodified lines
202201 };
203202
204203 static struct plat_sci_port scif1_platform_data = {
205− .flags = UPF_BOOT_AUTOCONF,
206− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
204+ .scscr = SCSCR_REIE,
207205 .type = PORT_SCIF,
208206 .ops = &sh7722_sci_port_ops,
209207 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
@@ -225,8 +223,7 @@ static struct platform_device scif1_device = { · 15 unmodified lines
225223 };
226224
227225 static struct plat_sci_port scif2_platform_data = {
228− .flags = UPF_BOOT_AUTOCONF,
229− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
226+ .scscr = SCSCR_REIE,
230227 .type = PORT_SCIF,
231228 .ops = &sh7722_sci_port_ops,
232229 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
arch/sh/kernel/cpu/sh4a/setup-sh7723.c+3−18
@@ -23,9 +23,7 @@ · 22 unmodified lines
2323
2424 /* Serial */
2525 static struct plat_sci_port scif0_platform_data = {
26− .port_reg = 0xa4050160,
27− .flags = UPF_BOOT_AUTOCONF,
28− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
26+ .scscr = SCSCR_REIE,
2927 .type = PORT_SCIF,
3028 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
3129 };
@@ -46,9 +44,7 @@ static struct platform_device scif0_device = { · 14 unmodified lines
4644 };
4745
4846 static struct plat_sci_port scif1_platform_data = {
49− .port_reg = SCIx_NOT_SUPPORTED,
50− .flags = UPF_BOOT_AUTOCONF,
51− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
47+ .scscr = SCSCR_REIE,
5248 .type = PORT_SCIF,
5349 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
5450 };
@@ -69,9 +65,7 @@ static struct platform_device scif1_device = { · 14 unmodified lines
6965 };
7066
7167 static struct plat_sci_port scif2_platform_data = {
72− .port_reg = SCIx_NOT_SUPPORTED,
73− .flags = UPF_BOOT_AUTOCONF,
74− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
68+ .scscr = SCSCR_REIE,
7569 .type = PORT_SCIF,
7670 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
7771 };
@@ -92,9 +86,6 @@ static struct platform_device scif2_device = { · 14 unmodified lines
9286 };
9387
9488 static struct plat_sci_port scif3_platform_data = {
95− .flags = UPF_BOOT_AUTOCONF,
96− .port_reg = SCIx_NOT_SUPPORTED,
97− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
9889 .sampling_rate = 8,
9990 .type = PORT_SCIFA,
10091 };
@@ -115,9 +106,6 @@ static struct platform_device scif3_device = { · 14 unmodified lines
115106 };
116107
117108 static struct plat_sci_port scif4_platform_data = {
118− .port_reg = SCIx_NOT_SUPPORTED,
119− .flags = UPF_BOOT_AUTOCONF,
120− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121109 .sampling_rate = 8,
122110 .type = PORT_SCIFA,
123111 };
@@ -138,9 +126,6 @@ static struct platform_device scif4_device = { · 14 unmodified lines
138126 };
139127
140128 static struct plat_sci_port scif5_platform_data = {
141− .port_reg = SCIx_NOT_SUPPORTED,
142− .flags = UPF_BOOT_AUTOCONF,
143− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
144129 .sampling_rate = 8,
145130 .type = PORT_SCIFA,
146131 };
arch/sh/kernel/cpu/sh4a/setup-sh7724.c+3−18
@@ -290,9 +290,7 @@ static struct platform_device dma1_device = { · 289 unmodified lines
290290
291291 /* Serial */
292292 static struct plat_sci_port scif0_platform_data = {
293− .port_reg = SCIx_NOT_SUPPORTED,
294− .flags = UPF_BOOT_AUTOCONF,
295− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
293+ .scscr = SCSCR_REIE,
296294 .type = PORT_SCIF,
297295 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
298296 };
@@ -313,9 +311,7 @@ static struct platform_device scif0_device = { · 14 unmodified lines
313311 };
314312
315313 static struct plat_sci_port scif1_platform_data = {
316− .port_reg = SCIx_NOT_SUPPORTED,
317− .flags = UPF_BOOT_AUTOCONF,
318− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
314+ .scscr = SCSCR_REIE,
319315 .type = PORT_SCIF,
320316 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
321317 };
@@ -336,9 +332,7 @@ static struct platform_device scif1_device = { · 14 unmodified lines
336332 };
337333
338334 static struct plat_sci_port scif2_platform_data = {
339− .port_reg = SCIx_NOT_SUPPORTED,
340− .flags = UPF_BOOT_AUTOCONF,
341− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335+ .scscr = SCSCR_REIE,
342336 .type = PORT_SCIF,
343337 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
344338 };
@@ -359,9 +353,6 @@ static struct platform_device scif2_device = { · 14 unmodified lines
359353 };
360354
361355 static struct plat_sci_port scif3_platform_data = {
362− .port_reg = SCIx_NOT_SUPPORTED,
363− .flags = UPF_BOOT_AUTOCONF,
364− .scscr = SCSCR_RE | SCSCR_TE,
365356 .sampling_rate = 8,
366357 .type = PORT_SCIFA,
367358 };
@@ -382,9 +373,6 @@ static struct platform_device scif3_device = { · 14 unmodified lines
382373 };
383374
384375 static struct plat_sci_port scif4_platform_data = {
385− .port_reg = SCIx_NOT_SUPPORTED,
386− .flags = UPF_BOOT_AUTOCONF,
387− .scscr = SCSCR_RE | SCSCR_TE,
388376 .sampling_rate = 8,
389377 .type = PORT_SCIFA,
390378 };
@@ -405,9 +393,6 @@ static struct platform_device scif4_device = { · 14 unmodified lines
405393 };
406394
407395 static struct plat_sci_port scif5_platform_data = {
408− .port_reg = SCIx_NOT_SUPPORTED,
409− .flags = UPF_BOOT_AUTOCONF,
410− .scscr = SCSCR_RE | SCSCR_TE,
411396 .sampling_rate = 8,
412397 .type = PORT_SCIFA,
413398 };
arch/sh/kernel/cpu/sh4a/setup-sh7734.c+6−12
@@ -25,8 +25,7 @@ · 24 unmodified lines
2525
2626 /* SCIF */
2727 static struct plat_sci_port scif0_platform_data = {
28− .flags = UPF_BOOT_AUTOCONF,
29− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28+ .scscr = SCSCR_REIE,
3029 .type = PORT_SCIF,
3130 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
3231 };
@@ -47,8 +46,7 @@ static struct platform_device scif0_device = { · 14 unmodified lines
4746 };
4847
4948 static struct plat_sci_port scif1_platform_data = {
50− .flags = UPF_BOOT_AUTOCONF,
51− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49+ .scscr = SCSCR_REIE,
5250 .type = PORT_SCIF,
5351 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
5452 };
@@ -69,8 +67,7 @@ static struct platform_device scif1_device = { · 14 unmodified lines
6967 };
7068
7169 static struct plat_sci_port scif2_platform_data = {
72− .flags = UPF_BOOT_AUTOCONF,
73− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
70+ .scscr = SCSCR_REIE,
7471 .type = PORT_SCIF,
7572 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
7673 };
@@ -91,8 +88,7 @@ static struct platform_device scif2_device = { · 14 unmodified lines
9188 };
9289
9390 static struct plat_sci_port scif3_platform_data = {
94− .flags = UPF_BOOT_AUTOCONF,
95− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
91+ .scscr = SCSCR_REIE | SCSCR_TOIE,
9692 .type = PORT_SCIF,
9793 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
9894 };
@@ -113,8 +109,7 @@ static struct platform_device scif3_device = { · 14 unmodified lines
113109 };
114110
115111 static struct plat_sci_port scif4_platform_data = {
116− .flags = UPF_BOOT_AUTOCONF,
117− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
112+ .scscr = SCSCR_REIE,
118113 .type = PORT_SCIF,
119114 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
120115 };
@@ -135,8 +130,7 @@ static struct platform_device scif4_device = { · 14 unmodified lines
135130 };
136131
137132 static struct plat_sci_port scif5_platform_data = {
138− .flags = UPF_BOOT_AUTOCONF,
139− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
133+ .scscr = SCSCR_REIE,
140134 .type = PORT_SCIF,
141135 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
142136 };
arch/sh/kernel/cpu/sh4a/setup-sh7757.c+3−6
@@ -24,8 +24,7 @@ · 23 unmodified lines
2424 #include <cpu/sh7757.h>
2525
2626 static struct plat_sci_port scif2_platform_data = {
27− .flags = UPF_BOOT_AUTOCONF,
28− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
27+ .scscr = SCSCR_REIE,
2928 .type = PORT_SCIF,
3029 };
3130
@@ -45,8 +44,7 @@ static struct platform_device scif2_device = { · 13 unmodified lines
4544 };
4645
4746 static struct plat_sci_port scif3_platform_data = {
48− .flags = UPF_BOOT_AUTOCONF,
49− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
47+ .scscr = SCSCR_REIE,
5048 .type = PORT_SCIF,
5149 };
5250
@@ -66,8 +64,7 @@ static struct platform_device scif3_device = { · 13 unmodified lines
6664 };
6765
6866 static struct plat_sci_port scif4_platform_data = {
69− .flags = UPF_BOOT_AUTOCONF,
70− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67+ .scscr = SCSCR_REIE,
7168 .type = PORT_SCIF,
7269 };
7370
arch/sh/kernel/cpu/sh4a/setup-sh7763.c+3−6
@@ -19,8 +19,7 @@ · 18 unmodified lines
1919 #include <linux/usb/ohci_pdriver.h>
2020
2121 static struct plat_sci_port scif0_platform_data = {
22− .flags = UPF_BOOT_AUTOCONF,
23− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
22+ .scscr = SCSCR_REIE,
2423 .type = PORT_SCIF,
2524 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
2625 };
@@ -41,8 +40,7 @@ static struct platform_device scif0_device = { · 14 unmodified lines
4140 };
4241
4342 static struct plat_sci_port scif1_platform_data = {
44− .flags = UPF_BOOT_AUTOCONF,
45− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
43+ .scscr = SCSCR_REIE,
4644 .type = PORT_SCIF,
4745 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
4846 };
@@ -63,8 +61,7 @@ static struct platform_device scif1_device = { · 14 unmodified lines
6361 };
6462
6563 static struct plat_sci_port scif2_platform_data = {
66− .flags = UPF_BOOT_AUTOCONF,
67− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
64+ .scscr = SCSCR_REIE,
6865 .type = PORT_SCIF,
6966 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
7067 };
arch/sh/kernel/cpu/sh4a/setup-sh7770.c+10−20
@@ -16,8 +16,7 @@ · 15 unmodified lines
1616 #include <linux/io.h>
1717
1818 static struct plat_sci_port scif0_platform_data = {
19− .flags = UPF_BOOT_AUTOCONF,
20− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
19+ .scscr = SCSCR_REIE | SCSCR_TOIE,
2120 .type = PORT_SCIF,
2221 };
2322
@@ -37,8 +36,7 @@ static struct platform_device scif0_device = { · 13 unmodified lines
3736 };
3837
3938 static struct plat_sci_port scif1_platform_data = {
40− .flags = UPF_BOOT_AUTOCONF,
41− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
39+ .scscr = SCSCR_REIE | SCSCR_TOIE,
4240 .type = PORT_SCIF,
4341 };
4442
@@ -58,8 +56,7 @@ static struct platform_device scif1_device = { · 13 unmodified lines
5856 };
5957
6058 static struct plat_sci_port scif2_platform_data = {
61− .flags = UPF_BOOT_AUTOCONF,
62− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
59+ .scscr = SCSCR_REIE | SCSCR_TOIE,
6360 .type = PORT_SCIF,
6461 };
6562
@@ -79,8 +76,7 @@ static struct platform_device scif2_device = { · 13 unmodified lines
7976 };
8077
8178 static struct plat_sci_port scif3_platform_data = {
82− .flags = UPF_BOOT_AUTOCONF,
83− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
79+ .scscr = SCSCR_REIE | SCSCR_TOIE,
8480 .type = PORT_SCIF,
8581 };
8682
@@ -100,8 +96,7 @@ static struct platform_device scif3_device = { · 13 unmodified lines
10096 };
10197
10298 static struct plat_sci_port scif4_platform_data = {
103− .flags = UPF_BOOT_AUTOCONF,
104− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
99+ .scscr = SCSCR_REIE | SCSCR_TOIE,
105100 .type = PORT_SCIF,
106101 };
107102
@@ -121,8 +116,7 @@ static struct platform_device scif4_device = { · 13 unmodified lines
121116 };
122117
123118 static struct plat_sci_port scif5_platform_data = {
124− .flags = UPF_BOOT_AUTOCONF,
125− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
119+ .scscr = SCSCR_REIE | SCSCR_TOIE,
126120 .type = PORT_SCIF,
127121 };
128122
@@ -142,8 +136,7 @@ static struct platform_device scif5_device = { · 13 unmodified lines
142136 };
143137
144138 static struct plat_sci_port scif6_platform_data = {
145− .flags = UPF_BOOT_AUTOCONF,
146− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
139+ .scscr = SCSCR_REIE | SCSCR_TOIE,
147140 .type = PORT_SCIF,
148141 };
149142
@@ -163,8 +156,7 @@ static struct platform_device scif6_device = { · 13 unmodified lines
163156 };
164157
165158 static struct plat_sci_port scif7_platform_data = {
166− .flags = UPF_BOOT_AUTOCONF,
167− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
159+ .scscr = SCSCR_REIE | SCSCR_TOIE,
168160 .type = PORT_SCIF,
169161 };
170162
@@ -184,8 +176,7 @@ static struct platform_device scif7_device = { · 13 unmodified lines
184176 };
185177
186178 static struct plat_sci_port scif8_platform_data = {
187− .flags = UPF_BOOT_AUTOCONF,
188− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
179+ .scscr = SCSCR_REIE | SCSCR_TOIE,
189180 .type = PORT_SCIF,
190181 };
191182
@@ -205,8 +196,7 @@ static struct platform_device scif8_device = { · 13 unmodified lines
205196 };
206197
207198 static struct plat_sci_port scif9_platform_data = {
208− .flags = UPF_BOOT_AUTOCONF,
209− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
199+ .scscr = SCSCR_REIE | SCSCR_TOIE,
210200 .type = PORT_SCIF,
211201 };
212202
arch/sh/kernel/cpu/sh4a/setup-sh7780.c+2−4
@@ -18,8 +18,7 @@ · 17 unmodified lines
1818 #include <cpu/dma-register.h>
1919
2020 static struct plat_sci_port scif0_platform_data = {
21− .flags = UPF_BOOT_AUTOCONF,
22− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
21+ .scscr = SCSCR_REIE | SCSCR_CKE1,
2322 .type = PORT_SCIF,
2423 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
2524 };
@@ -40,8 +39,7 @@ static struct platform_device scif0_device = { · 14 unmodified lines
4039 };
4140
4241 static struct plat_sci_port scif1_platform_data = {
43− .flags = UPF_BOOT_AUTOCONF,
44− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
42+ .scscr = SCSCR_REIE | SCSCR_CKE1,
4543 .type = PORT_SCIF,
4644 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
4745 };
arch/sh/kernel/cpu/sh4a/setup-sh7785.c+6−12
@@ -20,8 +20,7 @@ · 19 unmodified lines
2020 #include <cpu/dma-register.h>
2121
2222 static struct plat_sci_port scif0_platform_data = {
23− .flags = UPF_BOOT_AUTOCONF,
24− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
23+ .scscr = SCSCR_REIE | SCSCR_CKE1,
2524 .type = PORT_SCIF,
2625 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
2726 };
@@ -42,8 +41,7 @@ static struct platform_device scif0_device = { · 14 unmodified lines
4241 };
4342
4443 static struct plat_sci_port scif1_platform_data = {
45− .flags = UPF_BOOT_AUTOCONF,
46− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44+ .scscr = SCSCR_REIE | SCSCR_CKE1,
4745 .type = PORT_SCIF,
4846 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
4947 };
@@ -64,8 +62,7 @@ static struct platform_device scif1_device = { · 14 unmodified lines
6462 };
6563
6664 static struct plat_sci_port scif2_platform_data = {
67− .flags = UPF_BOOT_AUTOCONF,
68− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
65+ .scscr = SCSCR_REIE | SCSCR_CKE1,
6966 .type = PORT_SCIF,
7067 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
7168 };
@@ -86,8 +83,7 @@ static struct platform_device scif2_device = { · 14 unmodified lines
8683 };
8784
8885 static struct plat_sci_port scif3_platform_data = {
89− .flags = UPF_BOOT_AUTOCONF,
90− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
86+ .scscr = SCSCR_REIE | SCSCR_CKE1,
9187 .type = PORT_SCIF,
9288 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
9389 };
@@ -108,8 +104,7 @@ static struct platform_device scif3_device = { · 14 unmodified lines
108104 };
109105
110106 static struct plat_sci_port scif4_platform_data = {
111− .flags = UPF_BOOT_AUTOCONF,
112− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
107+ .scscr = SCSCR_REIE | SCSCR_CKE1,
113108 .type = PORT_SCIF,
114109 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
115110 };
@@ -130,8 +125,7 @@ static struct platform_device scif4_device = { · 14 unmodified lines
130125 };
131126
132127 static struct plat_sci_port scif5_platform_data = {
133− .flags = UPF_BOOT_AUTOCONF,
134− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
128+ .scscr = SCSCR_REIE | SCSCR_CKE1,
135129 .type = PORT_SCIF,
136130 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
137131 };
arch/sh/kernel/cpu/sh4a/setup-sh7786.c+6−12
@@ -28,8 +28,7 @@ · 27 unmodified lines
2828 #include <asm/mmzone.h>
2929
3030 static struct plat_sci_port scif0_platform_data = {
31− .flags = UPF_BOOT_AUTOCONF,
32− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
31+ .scscr = SCSCR_REIE | SCSCR_CKE1,
3332 .type = PORT_SCIF,
3433 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
3534 };
@@ -56,8 +55,7 @@ static struct platform_device scif0_device = { · 20 unmodified lines
5655 * The rest of these all have multiplexed IRQs
5756 */
5857 static struct plat_sci_port scif1_platform_data = {
59− .flags = UPF_BOOT_AUTOCONF,
60− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
58+ .scscr = SCSCR_REIE | SCSCR_CKE1,
6159 .type = PORT_SCIF,
6260 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
6361 };
@@ -87,8 +85,7 @@ static struct platform_device scif1_device = { · 23 unmodified lines
8785 };
8886
8987 static struct plat_sci_port scif2_platform_data = {
90− .flags = UPF_BOOT_AUTOCONF,
91− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
88+ .scscr = SCSCR_REIE | SCSCR_CKE1,
9289 .type = PORT_SCIF,
9390 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
9491 };
@@ -109,8 +106,7 @@ static struct platform_device scif2_device = { · 14 unmodified lines
109106 };
110107
111108 static struct plat_sci_port scif3_platform_data = {
112− .flags = UPF_BOOT_AUTOCONF,
113− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
109+ .scscr = SCSCR_REIE | SCSCR_CKE1,
114110 .type = PORT_SCIF,
115111 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
116112 };
@@ -131,8 +127,7 @@ static struct platform_device scif3_device = { · 14 unmodified lines
131127 };
132128
133129 static struct plat_sci_port scif4_platform_data = {
134− .flags = UPF_BOOT_AUTOCONF,
135− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
130+ .scscr = SCSCR_REIE | SCSCR_CKE1,
136131 .type = PORT_SCIF,
137132 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
138133 };
@@ -153,8 +148,7 @@ static struct platform_device scif4_device = { · 14 unmodified lines
153148 };
154149
155150 static struct plat_sci_port scif5_platform_data = {
156− .flags = UPF_BOOT_AUTOCONF,
157− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
151+ .scscr = SCSCR_REIE | SCSCR_CKE1,
158152 .type = PORT_SCIF,
159153 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
160154 };
arch/sh/kernel/cpu/sh4a/setup-shx3.c+3−6
@@ -28,8 +28,7 @@ · 27 unmodified lines
2828 * all rather than adding infrastructure to hack around it.
2929 */
3030 static struct plat_sci_port scif0_platform_data = {
31− .flags = UPF_BOOT_AUTOCONF,
32− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31+ .scscr = SCSCR_REIE,
3332 .type = PORT_SCIF,
3433 };
3534
@@ -52,8 +51,7 @@ static struct platform_device scif0_device = { · 16 unmodified lines
5251 };
5352
5453 static struct plat_sci_port scif1_platform_data = {
55− .flags = UPF_BOOT_AUTOCONF,
56− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
54+ .scscr = SCSCR_REIE,
5755 .type = PORT_SCIF,
5856 };
5957
@@ -76,8 +74,7 @@ static struct platform_device scif1_device = { · 16 unmodified lines
7674 };
7775
7876 static struct plat_sci_port scif2_platform_data = {
79− .flags = UPF_BOOT_AUTOCONF,
80− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
77+ .scscr = SCSCR_REIE,
8178 .type = PORT_SCIF,
8279 };
8380
arch/sh/kernel/cpu/sh5/setup-sh5.c+2−2
@@ -17,8 +17,8 @@ · 16 unmodified lines
1717 #include <asm/addrspace.h>
1818
1919 static struct plat_sci_port scif0_platform_data = {
20− .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
21− .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
20+ .flags = UPF_IOREMAP,
21+ .scscr = SCSCR_REIE,
2222 .type = PORT_SCIF,
2323 };
2424
drivers/acpi/spcr.c+23−0
@@ -16,6 +16,26 @@ · 15 unmodified lines
1616 #include <linux/kernel.h>
1717 #include <linux/serial_core.h>
1818
19+/*
20+ * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
21+ * Detect them by examining the OEM fields in the SPCR header, similiar to PCI
22+ * quirk detection in pci_mcfg.c.
23+ */
24+static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
25+{
26+ if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE))
27+ return false;
28+
29+ if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
30+ return true;
31+
32+ if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
33+ h->oem_revision == 0)
34+ return true;
35+
36+ return false;
37+}
38+
1939 /**
2040 * parse_spcr() - parse ACPI SPCR table and add preferred console
2141 *
@@ -93,6 +113,9 @@ int __init parse_spcr(bool earlycon) · 71 unmodified lines
93113 goto done;
94114 }
95115
116+ if (qdf2400_erratum_44_present(&table->header))
117+ uart = "qdf2400_e44";
118+
96119 snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
97120 table->serial_port.address, baud_rate);
98121
drivers/char/Kconfig+1−0
@@ -46,6 +46,7 @@ config SGI_MBCS · 45 unmodified lines
4646 say Y or M here, otherwise say N.
4747
4848 source "drivers/tty/serial/Kconfig"
49+source "drivers/tty/serdev/Kconfig"
4950
5051 config TTY_PRINTK
5152 tristate "TTY driver to output user messages via printk"
drivers/dma/hsu/pci.c+15−2
@@ -23,15 +23,28 @@ · 22 unmodified lines
2323
2424 #define HSU_PCI_CHAN_OFFSET 0x100
2525
26+#define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA 0x081e
27+#define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA 0x1192
28+
2629 static irqreturn_t hsu_pci_irq(int irq, void *dev)
2730 {
2831 struct hsu_dma_chip *chip = dev;
32+ struct pci_dev *pdev = to_pci_dev(chip->dev);
2933 u32 dmaisr;
3034 u32 status;
3135 unsigned short i;
3236 int ret = 0;
3337 int err;
3438
39+ /*
40+ * On Intel Tangier B0 and Anniedale the interrupt line, disregarding
41+ * to have different numbers, is shared between HSU DMA and UART IPs.
42+ * Thus on such SoCs we are expecting that IRQ handler is called in
43+ * UART driver only.
44+ */
45+ if (pdev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA)
46+ return IRQ_HANDLED;
47+
3548 dmaisr = readl(chip->regs + HSU_PCI_DMAISR);
3649 for (i = 0; i < chip->hsu->nr_channels; i++) {
3750 if (dmaisr & 0x1) {
@@ -113,8 +126,8 @@ static void hsu_pci_remove(struct pci_dev *pdev) · 75 unmodified lines
113126 }
114127
115128 static const struct pci_device_id hsu_pci_id_table[] = {
116− { PCI_VDEVICE(INTEL, 0x081e), 0 },
117− { PCI_VDEVICE(INTEL, 0x1192), 0 },
129+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA), 0 },
130+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA), 0 },
118131 { }
119132 };
120133 MODULE_DEVICE_TABLE(pci, hsu_pci_id_table);
drivers/tty/Makefile+1−0
@@ -13,6 +13,7 @@ obj-$(CONFIG_R3964) += n_r3964.o · 12 unmodified lines
1313 obj-y += vt/
1414 obj-$(CONFIG_HVC_DRIVER) += hvc/
1515 obj-y += serial/
16+obj-$(CONFIG_SERIAL_DEV_BUS) += serdev/
1617
1718 # tty drivers
1819 obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
drivers/tty/goldfish.c+1−1
@@ -300,7 +300,7 @@ static int goldfish_tty_probe(struct platform_device *pdev) · 299 unmodified lines
300300 return 0;
301301
302302 err_tty_register_device_failed:
303− free_irq(irq, pdev);
303+ free_irq(irq, qtty);
304304 err_request_irq_failed:
305305 goldfish_tty_current_line_count--;
306306 if (goldfish_tty_current_line_count == 0)
drivers/tty/hvc/hvc_console.c+0−1
@@ -29,7 +29,6 @@ · 28 unmodified lines
2929 #include <linux/kernel.h>
3030 #include <linux/kthread.h>
3131 #include <linux/list.h>
32−#include <linux/init.h>
3332 #include <linux/major.h>
3433 #include <linux/atomic.h>
3534 #include <linux/sysrq.h>
drivers/tty/serdev/Kconfig+16−0
@@ -0,0 +1,16 @@
1+#
2+# Serial bus device driver configuration
3+#
4+menuconfig SERIAL_DEV_BUS
5+ tristate "Serial device bus"
6+ help
7+ Core support for devices connected via a serial port.
8+
9+if SERIAL_DEV_BUS
10+
11+config SERIAL_DEV_CTRL_TTYPORT
12+ bool "Serial device TTY port controller"
13+ depends on TTY
14+ depends on SERIAL_DEV_BUS != m
15+
16+endif
drivers/tty/serdev/Makefile+5−0
@@ -0,0 +1,5 @@
1+serdev-objs := core.o
2+
3+obj-$(CONFIG_SERIAL_DEV_BUS) += serdev.o
4+
5+obj-$(CONFIG_SERIAL_DEV_CTRL_TTYPORT) += serdev-ttyport.o
drivers/tty/serdev/core.c+421−0
@@ -0,0 +1,421 @@
1+/*
2+ * Copyright (C) 2016-2017 Linaro Ltd., Rob Herring <robh@kernel.org>
3+ *
4+ * Based on drivers/spmi/spmi.c:
5+ * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
6+ *
7+ * This program is free software; you can redistribute it and/or modify
8+ * it under the terms of the GNU General Public License version 2 and
9+ * only version 2 as published by the Free Software Foundation.
10+ *
11+ * This program is distributed in the hope that it will be useful,
12+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ * GNU General Public License for more details.
15+ */
16+
17+#include <linux/errno.h>
18+#include <linux/idr.h>
19+#include <linux/kernel.h>
20+#include <linux/module.h>
21+#include <linux/of.h>
22+#include <linux/of_device.h>
23+#include <linux/serdev.h>
24+#include <linux/slab.h>
25+
26+static bool is_registered;
27+static DEFINE_IDA(ctrl_ida);
28+
29+static void serdev_device_release(struct device *dev)
30+{
31+ struct serdev_device *serdev = to_serdev_device(dev);
32+ kfree(serdev);
33+}
34+
35+static const struct device_type serdev_device_type = {
36+ .release = serdev_device_release,
37+};
38+
39+static void serdev_ctrl_release(struct device *dev)
40+{
41+ struct serdev_controller *ctrl = to_serdev_controller(dev);
42+ ida_simple_remove(&ctrl_ida, ctrl->nr);
43+ kfree(ctrl);
44+}
45+
46+static const struct device_type serdev_ctrl_type = {
47+ .release = serdev_ctrl_release,
48+};
49+
50+static int serdev_device_match(struct device *dev, struct device_driver *drv)
51+{
52+ /* TODO: ACPI and platform matching */
53+ return of_driver_match_device(dev, drv);
54+}
55+
56+static int serdev_uevent(struct device *dev, struct kobj_uevent_env *env)
57+{
58+ /* TODO: ACPI and platform modalias */
59+ return of_device_uevent_modalias(dev, env);
60+}
61+
62+/**
63+ * serdev_device_add() - add a device previously constructed via serdev_device_alloc()
64+ * @serdev: serdev_device to be added
65+ */
66+int serdev_device_add(struct serdev_device *serdev)
67+{
68+ struct device *parent = serdev->dev.parent;
69+ int err;
70+
71+ dev_set_name(&serdev->dev, "%s-%d", dev_name(parent), serdev->nr);
72+
73+ err = device_add(&serdev->dev);
74+ if (err < 0) {
75+ dev_err(&serdev->dev, "Can't add %s, status %d\n",
76+ dev_name(&serdev->dev), err);
77+ goto err_device_add;
78+ }
79+
80+ dev_dbg(&serdev->dev, "device %s registered\n", dev_name(&serdev->dev));
81+
82+err_device_add:
83+ return err;
84+}
85+EXPORT_SYMBOL_GPL(serdev_device_add);
86+
87+/**
88+ * serdev_device_remove(): remove an serdev device
89+ * @serdev: serdev_device to be removed
90+ */
91+void serdev_device_remove(struct serdev_device *serdev)
92+{
93+ device_unregister(&serdev->dev);
94+}
95+EXPORT_SYMBOL_GPL(serdev_device_remove);
96+
97+int serdev_device_open(struct serdev_device *serdev)
98+{
99+ struct serdev_controller *ctrl = serdev->ctrl;
100+
101+ if (!ctrl || !ctrl->ops->open)
102+ return -EINVAL;
103+
104+ return ctrl->ops->open(ctrl);
105+}
106+EXPORT_SYMBOL_GPL(serdev_device_open);
107+
108+void serdev_device_close(struct serdev_device *serdev)
109+{
110+ struct serdev_controller *ctrl = serdev->ctrl;
111+
112+ if (!ctrl || !ctrl->ops->close)
113+ return;
114+
115+ ctrl->ops->close(ctrl);
116+}
117+EXPORT_SYMBOL_GPL(serdev_device_close);
118+
119+int serdev_device_write_buf(struct serdev_device *serdev,
120+ const unsigned char *buf, size_t count)
121+{
122+ struct serdev_controller *ctrl = serdev->ctrl;
123+
124+ if (!ctrl || !ctrl->ops->write_buf)
125+ return -EINVAL;
126+
127+ return ctrl->ops->write_buf(ctrl, buf, count);
128+}
129+EXPORT_SYMBOL_GPL(serdev_device_write_buf);
130+
131+void serdev_device_write_flush(struct serdev_device *serdev)
132+{
133+ struct serdev_controller *ctrl = serdev->ctrl;
134+
135+ if (!ctrl || !ctrl->ops->write_flush)
136+ return;
137+
138+ ctrl->ops->write_flush(ctrl);
139+}
140+EXPORT_SYMBOL_GPL(serdev_device_write_flush);
141+
142+int serdev_device_write_room(struct serdev_device *serdev)
143+{
144+ struct serdev_controller *ctrl = serdev->ctrl;
145+
146+ if (!ctrl || !ctrl->ops->write_room)
147+ return 0;
148+
149+ return serdev->ctrl->ops->write_room(ctrl);
150+}
151+EXPORT_SYMBOL_GPL(serdev_device_write_room);
152+
153+unsigned int serdev_device_set_baudrate(struct serdev_device *serdev, unsigned int speed)
154+{
155+ struct serdev_controller *ctrl = serdev->ctrl;
156+
157+ if (!ctrl || !ctrl->ops->set_baudrate)
158+ return 0;
159+
160+ return ctrl->ops->set_baudrate(ctrl, speed);
161+
162+}
163+EXPORT_SYMBOL_GPL(serdev_device_set_baudrate);
164+
165+void serdev_device_set_flow_control(struct serdev_device *serdev, bool enable)
166+{
167+ struct serdev_controller *ctrl = serdev->ctrl;
168+
169+ if (!ctrl || !ctrl->ops->set_flow_control)
170+ return;
171+
172+ ctrl->ops->set_flow_control(ctrl, enable);
173+}
174+EXPORT_SYMBOL_GPL(serdev_device_set_flow_control);
175+
176+static int serdev_drv_probe(struct device *dev)
177+{
178+ const struct serdev_device_driver *sdrv = to_serdev_device_driver(dev->driver);
179+
180+ return sdrv->probe(to_serdev_device(dev));
181+}
182+
183+static int serdev_drv_remove(struct device *dev)
184+{
185+ const struct serdev_device_driver *sdrv = to_serdev_device_driver(dev->driver);
186+
187+ sdrv->remove(to_serdev_device(dev));
188+ return 0;
189+}
190+
191+static ssize_t modalias_show(struct device *dev,
192+ struct device_attribute *attr, char *buf)
193+{
194+ ssize_t len = of_device_get_modalias(dev, buf, PAGE_SIZE - 2);
195+ buf[len] = '\n';
196+ buf[len+1] = 0;
197+ return len+1;
198+}
199+
200+static struct device_attribute serdev_device_attrs[] = {
201+ __ATTR_RO(modalias),
202+ __ATTR_NULL
203+};
204+
205+static struct bus_type serdev_bus_type = {
206+ .name = "serial",
207+ .match = serdev_device_match,
208+ .probe = serdev_drv_probe,
209+ .remove = serdev_drv_remove,
210+ .uevent = serdev_uevent,
211+ .dev_attrs = serdev_device_attrs,
212+};
213+
214+/**
215+ * serdev_controller_alloc() - Allocate a new serdev device
216+ * @ctrl: associated controller
217+ *
218+ * Caller is responsible for either calling serdev_device_add() to add the
219+ * newly allocated controller, or calling serdev_device_put() to discard it.
220+ */
221+struct serdev_device *serdev_device_alloc(struct serdev_controller *ctrl)
222+{
223+ struct serdev_device *serdev;
224+
225+ serdev = kzalloc(sizeof(*serdev), GFP_KERNEL);
226+ if (!serdev)
227+ return NULL;
228+
229+ serdev->ctrl = ctrl;
230+ ctrl->serdev = serdev;
231+ device_initialize(&serdev->dev);
232+ serdev->dev.parent = &ctrl->dev;
233+ serdev->dev.bus = &serdev_bus_type;
234+ serdev->dev.type = &serdev_device_type;
235+ return serdev;
236+}
237+EXPORT_SYMBOL_GPL(serdev_device_alloc);
238+
239+/**
240+ * serdev_controller_alloc() - Allocate a new serdev controller
241+ * @parent: parent device
242+ * @size: size of private data
243+ *
244+ * Caller is responsible for either calling serdev_controller_add() to add the
245+ * newly allocated controller, or calling serdev_controller_put() to discard it.
246+ * The allocated private data region may be accessed via
247+ * serdev_controller_get_drvdata()
248+ */
249+struct serdev_controller *serdev_controller_alloc(struct device *parent,
250+ size_t size)
251+{
252+ struct serdev_controller *ctrl;
253+ int id;
254+
255+ if (WARN_ON(!parent))
256+ return NULL;
257+
258+ ctrl = kzalloc(sizeof(*ctrl) + size, GFP_KERNEL);
259+ if (!ctrl)
260+ return NULL;
261+
262+ device_initialize(&ctrl->dev);
263+ ctrl->dev.type = &serdev_ctrl_type;
264+ ctrl->dev.bus = &serdev_bus_type;
265+ ctrl->dev.parent = parent;
266+ ctrl->dev.of_node = parent->of_node;
267+ serdev_controller_set_drvdata(ctrl, &ctrl[1]);
268+
269+ id = ida_simple_get(&ctrl_ida, 0, 0, GFP_KERNEL);
270+ if (id < 0) {
271+ dev_err(parent,
272+ "unable to allocate serdev controller identifier.\n");
273+ serdev_controller_put(ctrl);
274+ return NULL;
275+ }
276+
277+ ctrl->nr = id;
278+ dev_set_name(&ctrl->dev, "serial%d", id);
279+
280+ dev_dbg(&ctrl->dev, "allocated controller 0x%p id %d\n", ctrl, id);
281+ return ctrl;
282+}
283+EXPORT_SYMBOL_GPL(serdev_controller_alloc);
284+
285+static int of_serdev_register_devices(struct serdev_controller *ctrl)
286+{
287+ struct device_node *node;
288+ struct serdev_device *serdev = NULL;
289+ int err;
290+ bool found = false;
291+
292+ for_each_available_child_of_node(ctrl->dev.of_node, node) {
293+ if (!of_get_property(node, "compatible", NULL))
294+ continue;
295+
296+ dev_dbg(&ctrl->dev, "adding child %s\n", node->full_name);
297+
298+ serdev = serdev_device_alloc(ctrl);
299+ if (!serdev)
300+ continue;
301+
302+ serdev->dev.of_node = node;
303+
304+ err = serdev_device_add(serdev);
305+ if (err) {
306+ dev_err(&serdev->dev,
307+ "failure adding device. status %d\n", err);
308+ serdev_device_put(serdev);
309+ } else
310+ found = true;
311+ }
312+ if (!found)
313+ return -ENODEV;
314+
315+ return 0;
316+}
317+
318+/**
319+ * serdev_controller_add() - Add an serdev controller
320+ * @ctrl: controller to be registered.
321+ *
322+ * Register a controller previously allocated via serdev_controller_alloc() with
323+ * the serdev core.
324+ */
325+int serdev_controller_add(struct serdev_controller *ctrl)
326+{
327+ int ret;
328+
329+ /* Can't register until after driver model init */
330+ if (WARN_ON(!is_registered))
331+ return -EAGAIN;
332+
333+ ret = device_add(&ctrl->dev);
334+ if (ret)
335+ return ret;
336+
337+ ret = of_serdev_register_devices(ctrl);
338+ if (ret)
339+ goto out_dev_del;
340+
341+ dev_dbg(&ctrl->dev, "serdev%d registered: dev:%p\n",
342+ ctrl->nr, &ctrl->dev);
343+ return 0;
344+
345+out_dev_del:
346+ device_del(&ctrl->dev);
347+ return ret;
348+};
349+EXPORT_SYMBOL_GPL(serdev_controller_add);
350+
351+/* Remove a device associated with a controller */
352+static int serdev_remove_device(struct device *dev, void *data)
353+{
354+ struct serdev_device *serdev = to_serdev_device(dev);
355+ if (dev->type == &serdev_device_type)
356+ serdev_device_remove(serdev);
357+ return 0;
358+}
359+
360+/**
361+ * serdev_controller_remove(): remove an serdev controller
362+ * @ctrl: controller to remove
363+ *
364+ * Remove a serdev controller. Caller is responsible for calling
365+ * serdev_controller_put() to discard the allocated controller.
366+ */
367+void serdev_controller_remove(struct serdev_controller *ctrl)
368+{
369+ int dummy;
370+
371+ if (!ctrl)
372+ return;
373+
374+ dummy = device_for_each_child(&ctrl->dev, NULL,
375+ serdev_remove_device);
376+ device_del(&ctrl->dev);
377+}
378+EXPORT_SYMBOL_GPL(serdev_controller_remove);
379+
380+/**
381+ * serdev_driver_register() - Register client driver with serdev core
382+ * @sdrv: client driver to be associated with client-device.
383+ *
384+ * This API will register the client driver with the serdev framework.
385+ * It is typically called from the driver's module-init function.
386+ */
387+int __serdev_device_driver_register(struct serdev_device_driver *sdrv, struct module *owner)
388+{
389+ sdrv->driver.bus = &serdev_bus_type;
390+ sdrv->driver.owner = owner;
391+
392+ /* force drivers to async probe so I/O is possible in probe */
393+ sdrv->driver.probe_type = PROBE_PREFER_ASYNCHRONOUS;
394+
395+ return driver_register(&sdrv->driver);
396+}
397+EXPORT_SYMBOL_GPL(__serdev_device_driver_register);
398+
399+static void __exit serdev_exit(void)
400+{
401+ bus_unregister(&serdev_bus_type);
402+}
403+module_exit(serdev_exit);
404+
405+static int __init serdev_init(void)
406+{
407+ int ret;
408+
409+ ret = bus_register(&serdev_bus_type);
410+ if (ret)
411+ return ret;
412+
413+ is_registered = true;
414+ return 0;
415+}
416+/* Must be before serial drivers register */
417+postcore_initcall(serdev_init);
418+
419+MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
420+MODULE_LICENSE("GPL v2");
421+MODULE_DESCRIPTION("Serial attached device bus");
drivers/tty/serdev/serdev-ttyport.c+226−0
@@ -0,0 +1,226 @@
1+/*
2+ * Copyright (C) 2016-2017 Linaro Ltd., Rob Herring <robh@kernel.org>
3+ *
4+ * This program is free software; you can redistribute it and/or modify
5+ * it under the terms of the GNU General Public License version 2 and
6+ * only version 2 as published by the Free Software Foundation.
7+ *
8+ * This program is distributed in the hope that it will be useful,
9+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
10+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11+ * GNU General Public License for more details.
12+ */
13+#include <linux/kernel.h>
14+#include <linux/serdev.h>
15+#include <linux/tty.h>
16+#include <linux/tty_driver.h>
17+
18+#define SERPORT_ACTIVE 1
19+
20+struct serport {
21+ struct tty_port *port;
22+ struct tty_struct *tty;
23+ struct tty_driver *tty_drv;
24+ int tty_idx;
25+ unsigned long flags;
26+};
27+
28+/*
29+ * Callback functions from the tty port.
30+ */
31+
32+static int ttyport_receive_buf(struct tty_port *port, const unsigned char *cp,
33+ const unsigned char *fp, size_t count)
34+{
35+ struct serdev_controller *ctrl = port->client_data;
36+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
37+
38+ if (!test_bit(SERPORT_ACTIVE, &serport->flags))
39+ return 0;
40+
41+ return serdev_controller_receive_buf(ctrl, cp, count);
42+}
43+
44+static void ttyport_write_wakeup(struct tty_port *port)
45+{
46+ struct serdev_controller *ctrl = port->client_data;
47+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
48+
49+ if (!test_and_clear_bit(TTY_DO_WRITE_WAKEUP, &port->tty->flags))
50+ return;
51+
52+ if (test_bit(SERPORT_ACTIVE, &serport->flags))
53+ serdev_controller_write_wakeup(ctrl);
54+}
55+
56+static const struct tty_port_client_operations client_ops = {
57+ .receive_buf = ttyport_receive_buf,
58+ .write_wakeup = ttyport_write_wakeup,
59+};
60+
61+/*
62+ * Callback functions from the serdev core.
63+ */
64+
65+static int ttyport_write_buf(struct serdev_controller *ctrl, const unsigned char *data, size_t len)
66+{
67+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
68+ struct tty_struct *tty = serport->tty;
69+
70+ if (!test_bit(SERPORT_ACTIVE, &serport->flags))
71+ return 0;
72+
73+ set_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
74+ return tty->ops->write(serport->tty, data, len);
75+}
76+
77+static void ttyport_write_flush(struct serdev_controller *ctrl)
78+{
79+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
80+ struct tty_struct *tty = serport->tty;
81+
82+ tty_driver_flush_buffer(tty);
83+}
84+
85+static int ttyport_write_room(struct serdev_controller *ctrl)
86+{
87+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
88+ struct tty_struct *tty = serport->tty;
89+
90+ return tty_write_room(tty);
91+}
92+
93+static int ttyport_open(struct serdev_controller *ctrl)
94+{
95+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
96+ struct tty_struct *tty;
97+ struct ktermios ktermios;
98+
99+ tty = tty_init_dev(serport->tty_drv, serport->tty_idx);
100+ if (IS_ERR(tty))
101+ return PTR_ERR(tty);
102+ serport->tty = tty;
103+
104+ serport->port->client_ops = &client_ops;
105+ serport->port->client_data = ctrl;
106+
107+ if (tty->ops->open)
108+ tty->ops->open(serport->tty, NULL);
109+ else
110+ tty_port_open(serport->port, tty, NULL);
111+
112+ /* Bring the UART into a known 8 bits no parity hw fc state */
113+ ktermios = tty->termios;
114+ ktermios.c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP |
115+ INLCR | IGNCR | ICRNL | IXON);
116+ ktermios.c_oflag &= ~OPOST;
117+ ktermios.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN);
118+ ktermios.c_cflag &= ~(CSIZE | PARENB);
119+ ktermios.c_cflag |= CS8;
120+ ktermios.c_cflag |= CRTSCTS;
121+ tty_set_termios(tty, &ktermios);
122+
123+ set_bit(SERPORT_ACTIVE, &serport->flags);
124+
125+ tty_unlock(serport->tty);
126+ return 0;
127+}
128+
129+static void ttyport_close(struct serdev_controller *ctrl)
130+{
131+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
132+ struct tty_struct *tty = serport->tty;
133+
134+ clear_bit(SERPORT_ACTIVE, &serport->flags);
135+
136+ if (tty->ops->close)
137+ tty->ops->close(tty, NULL);
138+
139+ tty_release_struct(tty, serport->tty_idx);
140+}
141+
142+static unsigned int ttyport_set_baudrate(struct serdev_controller *ctrl, unsigned int speed)
143+{
144+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
145+ struct tty_struct *tty = serport->tty;
146+ struct ktermios ktermios = tty->termios;
147+
148+ ktermios.c_cflag &= ~CBAUD;
149+ tty_termios_encode_baud_rate(&ktermios, speed, speed);
150+
151+ /* tty_set_termios() return not checked as it is always 0 */
152+ tty_set_termios(tty, &ktermios);
153+ return speed;
154+}
155+
156+static void ttyport_set_flow_control(struct serdev_controller *ctrl, bool enable)
157+{
158+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
159+ struct tty_struct *tty = serport->tty;
160+ struct ktermios ktermios = tty->termios;
161+
162+ if (enable)
163+ ktermios.c_cflag |= CRTSCTS;
164+ else
165+ ktermios.c_cflag &= ~CRTSCTS;
166+
167+ tty_set_termios(tty, &ktermios);
168+}
169+
170+static const struct serdev_controller_ops ctrl_ops = {
171+ .write_buf = ttyport_write_buf,
172+ .write_flush = ttyport_write_flush,
173+ .write_room = ttyport_write_room,
174+ .open = ttyport_open,
175+ .close = ttyport_close,
176+ .set_flow_control = ttyport_set_flow_control,
177+ .set_baudrate = ttyport_set_baudrate,
178+};
179+
180+struct device *serdev_tty_port_register(struct tty_port *port,
181+ struct device *parent,
182+ struct tty_driver *drv, int idx)
183+{
184+ struct serdev_controller *ctrl;
185+ struct serport *serport;
186+ int ret;
187+
188+ if (!port || !drv || !parent)
189+ return ERR_PTR(-ENODEV);
190+
191+ ctrl = serdev_controller_alloc(parent, sizeof(struct serport));
192+ if (!ctrl)
193+ return ERR_PTR(-ENOMEM);
194+ serport = serdev_controller_get_drvdata(ctrl);
195+
196+ serport->port = port;
197+ serport->tty_idx = idx;
198+ serport->tty_drv = drv;
199+
200+ ctrl->ops = &ctrl_ops;
201+
202+ ret = serdev_controller_add(ctrl);
203+ if (ret)
204+ goto err_controller_put;
205+
206+ dev_info(&ctrl->dev, "tty port %s%d registered\n", drv->name, idx);
207+ return &ctrl->dev;
208+
209+err_controller_put:
210+ serdev_controller_put(ctrl);
211+ return ERR_PTR(ret);
212+}
213+
214+void serdev_tty_port_unregister(struct tty_port *port)
215+{
216+ struct serdev_controller *ctrl = port->client_data;
217+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
218+
219+ if (!serport)
220+ return;
221+
222+ serdev_controller_remove(ctrl);
223+ port->client_ops = NULL;
224+ port->client_data = NULL;
225+ serdev_controller_put(ctrl);
226+}
drivers/tty/serial/8250/8250_dw.c+25−3
@@ -201,8 +201,31 @@ static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) · 200 unmodified lines
201201
202202 static int dw8250_handle_irq(struct uart_port *p)
203203 {
204+ struct uart_8250_port *up = up_to_u8250p(p);
204205 struct dw8250_data *d = p->private_data;
205206 unsigned int iir = p->serial_in(p, UART_IIR);
207+ unsigned int status;
208+ unsigned long flags;
209+
210+ /*
211+ * There are ways to get Designware-based UARTs into a state where
212+ * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
213+ * data available. If we see such a case then we'll do a bogus
214+ * read. If we don't do this then the "RX TIMEOUT" interrupt will
215+ * fire forever.
216+ *
217+ * This problem has only been observed so far when not in DMA mode
218+ * so we limit the workaround only to non-DMA mode.
219+ */
220+ if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
221+ spin_lock_irqsave(&p->lock, flags);
222+ status = p->serial_in(p, UART_LSR);
223+
224+ if (!(status & (UART_LSR_DR | UART_LSR_BI)))
225+ (void) p->serial_in(p, UART_RX);
226+
227+ spin_unlock_irqrestore(&p->lock, flags);
228+ }
206229
207230 if (serial8250_handle_irq(p, iir))
208231 return 1;
@@ -248,11 +271,11 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, · 39 unmodified lines
248271 if (!ret)
249272 p->uartclk = rate;
250273
274+out:
251275 p->status &= ~UPSTAT_AUTOCTS;
252276 if (termios->c_cflag & CRTSCTS)
253277 p->status |= UPSTAT_AUTOCTS;
254278
255−out:
256279 serial8250_do_set_termios(p, termios, old);
257280 }
258281
@@ -326,13 +349,11 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) · 67 unmodified lines
326349 p->serial_in = dw8250_serial_in32;
327350 data->uart_16550_compatible = true;
328351 }
329− p->set_termios = dw8250_set_termios;
330352 }
331353
332354 /* Platforms with iDMA */
333355 if (platform_get_resource_byname(to_platform_device(p->dev),
334356 IORESOURCE_MEM, "lpss_priv")) {
335− p->set_termios = dw8250_set_termios;
336357 data->dma.rx_param = p->dev->parent;
337358 data->dma.tx_param = p->dev->parent;
338359 data->dma.fn = dw8250_idma_filter;
@@ -414,6 +435,7 @@ static int dw8250_probe(struct platform_device *pdev) · 75 unmodified lines
414435 p->serial_in = dw8250_serial_in;
415436 p->serial_out = dw8250_serial_out;
416437 p->set_ldisc = dw8250_set_ldisc;
438+ p->set_termios = dw8250_set_termios;
417439
418440 p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
419441 if (!p->membase)
drivers/tty/serial/8250/8250_exar.c+487−0
@@ -0,0 +1,487 @@
1+/*
2+ * Probe module for 8250/16550-type Exar chips PCI serial ports.
3+ *
4+ * Based on drivers/tty/serial/8250/8250_pci.c,
5+ *
6+ * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
7+ *
8+ * This program is free software; you can redistribute it and/or modify
9+ * it under the terms of the GNU General Public License as published by
10+ * the Free Software Foundation; either version 2 of the License.
11+ */
12+#include <linux/io.h>
13+#include <linux/kernel.h>
14+#include <linux/module.h>
15+#include <linux/pci.h>
16+#include <linux/serial_core.h>
17+#include <linux/serial_reg.h>
18+#include <linux/slab.h>
19+#include <linux/string.h>
20+#include <linux/tty.h>
21+#include <linux/8250_pci.h>
22+
23+#include <asm/byteorder.h>
24+
25+#include "8250.h"
26+
27+#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
28+#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
29+#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
30+#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
31+#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
32+#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
33+#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
34+#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
35+#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
36+
37+#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
38+
39+#define UART_EXAR_FCTR 0x08 /* Feature Control Register */
40+#define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
41+#define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
42+#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
43+#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
44+#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
45+#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
46+
47+#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
48+#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
49+
50+#define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
51+#define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
52+#define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
53+#define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
54+#define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
55+#define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
56+#define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
57+#define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
58+#define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
59+#define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
60+#define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
61+#define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
62+
63+struct exar8250;
64+
65+/**
66+ * struct exar8250_board - board information
67+ * @num_ports: number of serial ports
68+ * @reg_shift: describes UART register mapping in PCI memory
69+ */
70+struct exar8250_board {
71+ unsigned int num_ports;
72+ unsigned int reg_shift;
73+ bool has_slave;
74+ int (*setup)(struct exar8250 *, struct pci_dev *,
75+ struct uart_8250_port *, int);
76+ void (*exit)(struct pci_dev *pcidev);
77+};
78+
79+struct exar8250 {
80+ unsigned int nr;
81+ struct exar8250_board *board;
82+ int line[0];
83+};
84+
85+static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
86+ int idx, unsigned int offset,
87+ struct uart_8250_port *port)
88+{
89+ const struct exar8250_board *board = priv->board;
90+ unsigned int bar = 0;
91+
92+ if (!pcim_iomap_table(pcidev)[bar] && !pcim_iomap(pcidev, bar, 0))
93+ return -ENOMEM;
94+
95+ port->port.iotype = UPIO_MEM;
96+ port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
97+ port->port.membase = pcim_iomap_table(pcidev)[bar] + offset;
98+ port->port.regshift = board->reg_shift;
99+
100+ return 0;
101+}
102+
103+static int
104+pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
105+ struct uart_8250_port *port, int idx)
106+{
107+ unsigned int offset = idx * 0x200;
108+ unsigned int baud = 1843200;
109+ u8 __iomem *p;
110+ int err;
111+
112+ port->port.flags |= UPF_EXAR_EFR;
113+ port->port.uartclk = baud * 16;
114+
115+ err = default_setup(priv, pcidev, idx, offset, port);
116+ if (err)
117+ return err;
118+
119+ p = port->port.membase;
120+
121+ writeb(0x00, p + UART_EXAR_8XMODE);
122+ writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
123+ writeb(32, p + UART_EXAR_TXTRG);
124+ writeb(32, p + UART_EXAR_RXTRG);
125+
126+ /*
127+ * Setup Multipurpose Input/Output pins.
128+ */
129+ if (idx == 0) {
130+ switch (pcidev->device) {
131+ case PCI_DEVICE_ID_COMMTECH_4222PCI335:
132+ case PCI_DEVICE_ID_COMMTECH_4224PCI335:
133+ writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
134+ writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
135+ writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
136+ break;
137+ case PCI_DEVICE_ID_COMMTECH_2324PCI335:
138+ case PCI_DEVICE_ID_COMMTECH_2328PCI335:
139+ writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
140+ writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
141+ writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
142+ break;
143+ }
144+ writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
145+ writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
146+ writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
147+ }
148+
149+ return 0;
150+}
151+
152+static int
153+pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
154+ struct uart_8250_port *port, int idx)
155+{
156+ unsigned int offset = idx * 0x200;
157+ unsigned int baud = 1843200;
158+
159+ port->port.uartclk = baud * 16;
160+ return default_setup(priv, pcidev, idx, offset, port);
161+}
162+
163+static int
164+pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
165+ struct uart_8250_port *port, int idx)
166+{
167+ unsigned int offset = idx * 0x200;
168+ unsigned int baud = 921600;
169+
170+ port->port.uartclk = baud * 16;
171+ return default_setup(priv, pcidev, idx, offset, port);
172+}
173+
174+static void setup_gpio(u8 __iomem *p)
175+{
176+ writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
177+ writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
178+ writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
179+ writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
180+ writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
181+ writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
182+ writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
183+ writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
184+ writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
185+ writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
186+ writeb(0x00, p + UART_EXAR_MPIOSEL_15_8);
187+ writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
188+}
189+
190+static void *
191+xr17v35x_register_gpio(struct pci_dev *pcidev)
192+{
193+ struct platform_device *pdev;
194+
195+ pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
196+ if (!pdev)
197+ return NULL;
198+
199+ platform_set_drvdata(pdev, pcidev);
200+ if (platform_device_add(pdev) < 0) {
201+ platform_device_put(pdev);
202+ return NULL;
203+ }
204+
205+ return pdev;
206+}
207+
208+static int
209+pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
210+ struct uart_8250_port *port, int idx)
211+{
212+ const struct exar8250_board *board = priv->board;
213+ unsigned int offset = idx * 0x400;
214+ unsigned int baud = 7812500;
215+ u8 __iomem *p;
216+ int ret;
217+
218+ port->port.uartclk = baud * 16;
219+ /*
220+ * Setup the uart clock for the devices on expansion slot to
221+ * half the clock speed of the main chip (which is 125MHz)
222+ */
223+ if (board->has_slave && idx >= 8)
224+ port->port.uartclk /= 2;
225+
226+ ret = default_setup(priv, pcidev, idx, offset, port);
227+ if (ret)
228+ return ret;
229+
230+ p = port->port.membase;
231+
232+ writeb(0x00, p + UART_EXAR_8XMODE);
233+ writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
234+ writeb(128, p + UART_EXAR_TXTRG);
235+ writeb(128, p + UART_EXAR_RXTRG);
236+
237+ if (idx == 0) {
238+ /* Setup Multipurpose Input/Output pins. */
239+ setup_gpio(p);
240+
241+ port->port.private_data = xr17v35x_register_gpio(pcidev);
242+ }
243+
244+ return 0;
245+}
246+
247+static void pci_xr17v35x_exit(struct pci_dev *pcidev)
248+{
249+ struct exar8250 *priv = pci_get_drvdata(pcidev);
250+ struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
251+ struct platform_device *pdev = port->port.private_data;
252+
253+ platform_device_unregister(pdev);
254+ port->port.private_data = NULL;
255+}
256+
257+static int
258+exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
259+{
260+ unsigned int nr_ports, i, bar = 0, maxnr;
261+ struct exar8250_board *board;
262+ struct uart_8250_port uart;
263+ struct exar8250 *priv;
264+ int rc;
265+
266+ board = (struct exar8250_board *)ent->driver_data;
267+ if (!board)
268+ return -EINVAL;
269+
270+ rc = pcim_enable_device(pcidev);
271+ if (rc)
272+ return rc;
273+
274+ maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
275+
276+ nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
277+
278+ priv = devm_kzalloc(&pcidev->dev, sizeof(*priv) +
279+ sizeof(unsigned int) * nr_ports,
280+ GFP_KERNEL);
281+ if (!priv)
282+ return -ENOMEM;
283+
284+ priv->board = board;
285+
286+ pci_set_master(pcidev);
287+
288+ rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
289+ if (rc < 0)
290+ return rc;
291+
292+ memset(&uart, 0, sizeof(uart));
293+ uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ
294+ | UPF_EXAR_EFR;
295+ uart.port.irq = pci_irq_vector(pcidev, 0);
296+ uart.port.dev = &pcidev->dev;
297+
298+ for (i = 0; i < nr_ports && i < maxnr; i++) {
299+ rc = board->setup(priv, pcidev, &uart, i);
300+ if (rc) {
301+ dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
302+ break;
303+ }
304+
305+ dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
306+ uart.port.iobase, uart.port.irq, uart.port.iotype);
307+
308+ priv->line[i] = serial8250_register_8250_port(&uart);
309+ if (priv->line[i] < 0) {
310+ dev_err(&pcidev->dev,
311+ "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
312+ uart.port.iobase, uart.port.irq,
313+ uart.port.iotype, priv->line[i]);
314+ break;
315+ }
316+ }
317+ priv->nr = i;
318+ pci_set_drvdata(pcidev, priv);
319+ return 0;
320+}
321+
322+static void exar_pci_remove(struct pci_dev *pcidev)
323+{
324+ struct exar8250 *priv = pci_get_drvdata(pcidev);
325+ unsigned int i;
326+
327+ for (i = 0; i < priv->nr; i++)
328+ serial8250_unregister_port(priv->line[i]);
329+
330+ if (priv->board->exit)
331+ priv->board->exit(pcidev);
332+}
333+
334+static int __maybe_unused exar_suspend(struct device *dev)
335+{
336+ struct pci_dev *pcidev = to_pci_dev(dev);
337+ struct exar8250 *priv = pci_get_drvdata(pcidev);
338+ unsigned int i;
339+
340+ for (i = 0; i < priv->nr; i++)
341+ if (priv->line[i] >= 0)
342+ serial8250_suspend_port(priv->line[i]);
343+
344+ /* Ensure that every init quirk is properly torn down */
345+ if (priv->board->exit)
346+ priv->board->exit(pcidev);
347+
348+ return 0;
349+}
350+
351+static int __maybe_unused exar_resume(struct device *dev)
352+{
353+ struct pci_dev *pcidev = to_pci_dev(dev);
354+ struct exar8250 *priv = pci_get_drvdata(pcidev);
355+ unsigned int i;
356+
357+ for (i = 0; i < priv->nr; i++)
358+ if (priv->line[i] >= 0)
359+ serial8250_resume_port(priv->line[i]);
360+
361+ return 0;
362+}
363+
364+static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
365+
366+static const struct exar8250_board pbn_fastcom335_2 = {
367+ .num_ports = 2,
368+ .setup = pci_fastcom335_setup,
369+};
370+
371+static const struct exar8250_board pbn_fastcom335_4 = {
372+ .num_ports = 4,
373+ .setup = pci_fastcom335_setup,
374+};
375+
376+static const struct exar8250_board pbn_fastcom335_8 = {
377+ .num_ports = 8,
378+ .setup = pci_fastcom335_setup,
379+};
380+
381+static const struct exar8250_board pbn_connect = {
382+ .setup = pci_connect_tech_setup,
383+};
384+
385+static const struct exar8250_board pbn_exar_ibm_saturn = {
386+ .num_ports = 1,
387+ .setup = pci_xr17c154_setup,
388+};
389+
390+static const struct exar8250_board pbn_exar_XR17C15x = {
391+ .setup = pci_xr17c154_setup,
392+};
393+
394+static const struct exar8250_board pbn_exar_XR17V35x = {
395+ .setup = pci_xr17v35x_setup,
396+ .exit = pci_xr17v35x_exit,
397+};
398+
399+static const struct exar8250_board pbn_exar_XR17V4358 = {
400+ .num_ports = 12,
401+ .has_slave = true,
402+ .setup = pci_xr17v35x_setup,
403+ .exit = pci_xr17v35x_exit,
404+};
405+
406+static const struct exar8250_board pbn_exar_XR17V8358 = {
407+ .num_ports = 16,
408+ .has_slave = true,
409+ .setup = pci_xr17v35x_setup,
410+ .exit = pci_xr17v35x_exit,
411+};
412+
413+#define CONNECT_DEVICE(devid, sdevid, bd) { \
414+ PCI_DEVICE_SUB( \
415+ PCI_VENDOR_ID_EXAR, \
416+ PCI_DEVICE_ID_EXAR_##devid, \
417+ PCI_SUBVENDOR_ID_CONNECT_TECH, \
418+ PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
419+ (kernel_ulong_t)&bd \
420+ }
421+
422+#define EXAR_DEVICE(vend, devid, bd) { \
423+ PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd \
424+ }
425+
426+#define IBM_DEVICE(devid, sdevid, bd) { \
427+ PCI_DEVICE_SUB( \
428+ PCI_VENDOR_ID_EXAR, \
429+ PCI_DEVICE_ID_EXAR_##devid, \
430+ PCI_VENDOR_ID_IBM, \
431+ PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
432+ (kernel_ulong_t)&bd \
433+ }
434+
435+static struct pci_device_id exar_pci_tbl[] = {
436+ CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
437+ CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
438+ CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
439+ CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
440+ CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
441+ CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
442+ CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
443+ CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
444+ CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
445+ CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
446+ CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
447+ CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
448+
449+ IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
450+
451+ /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
452+ EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
453+ EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
454+ EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
455+
456+ /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
457+ EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
458+ EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
459+ EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
460+ EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
461+ EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
462+ EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x),
463+ EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x),
464+ EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x),
465+
466+ EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
467+ EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
468+ EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
469+ EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
470+ { 0, }
471+};
472+MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
473+
474+static struct pci_driver exar_pci_driver = {
475+ .name = "exar_serial",
476+ .probe = exar_pci_probe,
477+ .remove = exar_pci_remove,
478+ .driver = {
479+ .pm = &exar_pci_pm,
480+ },
481+ .id_table = exar_pci_tbl,
482+};
483+module_pci_driver(exar_pci_driver);
484+
485+MODULE_LICENSE("GPL");
486+MODULE_DESCRIPTION("Exar Serial Dricer");
487+MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
drivers/tty/serial/8250/8250_gsc.c+4−0
@@ -60,6 +60,10 @@ static int __init serial_init_chip(struct parisc_device *dev) · 59 unmodified lines
6060 7272727 : 1843200;
6161 uart.port.mapbase = address;
6262 uart.port.membase = ioremap_nocache(address, 16);
63+ if (!uart.port.membase) {
64+ dev_warn(&dev->dev, "Failed to map memory\n");
65+ return -ENOMEM;
66+ }
6367 uart.port.irq = dev->irq;
6468 uart.port.flags = UPF_BOOT_AUTOCONF;
6569 uart.port.dev = &dev->dev;
drivers/tty/serial/8250/8250_hp300.c+1−1
@@ -19,7 +19,7 @@ · 18 unmodified lines
1919
2020 #include "8250.h"
2121
22−#if !defined(CONFIG_HPDCA) && !defined(CONFIG_HPAPCI)
22+#if !defined(CONFIG_HPDCA) && !defined(CONFIG_HPAPCI) && !defined(CONFIG_COMPILE_TEST)
2323 #warning CONFIG_SERIAL_8250 defined but neither CONFIG_HPDCA nor CONFIG_HPAPCI defined, are you sure?
2424 #endif
2525
drivers/tty/serial/8250/8250_lpss.c+2−2
@@ -332,10 +332,10 @@ static void lpss8250_remove(struct pci_dev *pdev) · 331 unmodified lines
332332 {
333333 struct lpss8250 *lpss = pci_get_drvdata(pdev);
334334
335+ serial8250_unregister_port(lpss->line);
336+
335337 if (lpss->board->exit)
336338 lpss->board->exit(lpss);
337−
338− serial8250_unregister_port(lpss->line);
339339 }
340340
341341 static const struct lpss8250_board byt_board = {
drivers/tty/serial/8250/8250_mid.c+42−3
@@ -75,6 +75,37 @@ static int pnw_setup(struct mid8250 *mid, struct uart_port *p) · 74 unmodified lines
7575 return 0;
7676 }
7777
78+static int tng_handle_irq(struct uart_port *p)
79+{
80+ struct mid8250 *mid = p->private_data;
81+ struct uart_8250_port *up = up_to_u8250p(p);
82+ struct hsu_dma_chip *chip;
83+ u32 status;
84+ int ret = 0;
85+ int err;
86+
87+ chip = pci_get_drvdata(mid->dma_dev);
88+
89+ /* Rx DMA */
90+ err = hsu_dma_get_status(chip, mid->dma_index * 2 + 1, &status);
91+ if (err > 0) {
92+ serial8250_rx_dma_flush(up);
93+ ret |= 1;
94+ } else if (err == 0)
95+ ret |= hsu_dma_do_irq(chip, mid->dma_index * 2 + 1, status);
96+
97+ /* Tx DMA */
98+ err = hsu_dma_get_status(chip, mid->dma_index * 2, &status);
99+ if (err > 0)
100+ ret |= 1;
101+ else if (err == 0)
102+ ret |= hsu_dma_do_irq(chip, mid->dma_index * 2, status);
103+
104+ /* UART */
105+ ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
106+ return IRQ_RETVAL(ret);
107+}
108+
78109 static int tng_setup(struct mid8250 *mid, struct uart_port *p)
79110 {
80111 struct pci_dev *pdev = to_pci_dev(p->dev);
@@ -90,6 +121,8 @@ static int tng_setup(struct mid8250 *mid, struct uart_port *p) · 9 unmodified lines
90121
91122 mid->dma_index = index;
92123 mid->dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
124+
125+ p->handle_irq = tng_handle_irq;
93126 return 0;
94127 }
95128
@@ -131,8 +164,16 @@ static int dnv_setup(struct mid8250 *mid, struct uart_port *p) · 35 unmodified lines
131164 unsigned int bar = FL_GET_BASE(mid->board->flags);
132165 int ret;
133166
167+ pci_set_master(pdev);
168+
169+ ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
170+ if (ret < 0)
171+ return ret;
172+
173+ p->irq = pci_irq_vector(pdev, 0);
174+
134175 chip->dev = &pdev->dev;
135− chip->irq = pdev->irq;
176+ chip->irq = pci_irq_vector(pdev, 0);
136177 chip->regs = p->membase;
137178 chip->length = pci_resource_len(pdev, bar);
138179 chip->offset = DNV_DMA_CHAN_OFFSET;
@@ -250,8 +291,6 @@ static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 111 unmodified lines
250291 if (ret)
251292 return ret;
252293
253− pci_set_master(pdev);
254−
255294 mid = devm_kzalloc(&pdev->dev, sizeof(*mid), GFP_KERNEL);
256295 if (!mid)
257296 return -ENOMEM;
drivers/tty/serial/8250/8250_moxa.c+1−0
@@ -68,6 +68,7 @@ static int moxa8250_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 67 unmodified lines
6868 sizeof(unsigned int) * nr_ports, GFP_KERNEL);
6969 if (!brd)
7070 return -ENOMEM;
71+ brd->num_ports = nr_ports;
7172
7273 memset(&uart, 0, sizeof(struct uart_8250_port));
7374
drivers/tty/serial/8250/8250_of.c+25−69
@@ -172,7 +172,8 @@ static int of_platform_serial_probe(struct platform_device *ofdev) · 171 unmodified lines
172172 {
173173 const struct of_device_id *match;
174174 struct of_serial_info *info;
175− struct uart_port port;
175+ struct uart_8250_port port8250;
176+ u32 tx_threshold;
176177 int port_type;
177178 int ret;
178179
@@ -188,41 +189,24 @@ static int of_platform_serial_probe(struct platform_device *ofdev) · 9 unmodified lines
188189 return -ENOMEM;
189190
190191 port_type = (unsigned long)match->data;
191− ret = of_platform_serial_setup(ofdev, port_type, &port, info);
192+ memset(&port8250, 0, sizeof(port8250));
193+ ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info);
192194 if (ret)
193195 goto out;
194196
195− switch (port_type) {
196− case PORT_8250 ... PORT_MAX_8250:
197− {
198− u32 tx_threshold;
199− struct uart_8250_port port8250;
200− memset(&port8250, 0, sizeof(port8250));
201− port8250.port = port;
197+ if (port8250.port.fifosize)
198+ port8250.capabilities = UART_CAP_FIFO;
202199
203− if (port.fifosize)
204− port8250.capabilities = UART_CAP_FIFO;
200+ /* Check for TX FIFO threshold & set tx_loadsz */
201+ if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
202+ &tx_threshold) == 0) &&
203+ (tx_threshold < port8250.port.fifosize))
204+ port8250.tx_loadsz = port8250.port.fifosize - tx_threshold;
205205
206− /* Check for TX FIFO threshold & set tx_loadsz */
207− if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
208− &tx_threshold) == 0) &&
209− (tx_threshold < port.fifosize))
210− port8250.tx_loadsz = port.fifosize - tx_threshold;
206+ if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control"))
207+ port8250.capabilities |= UART_CAP_AFE;
211208
212− if (of_property_read_bool(ofdev->dev.of_node,
213− "auto-flow-control"))
214− port8250.capabilities |= UART_CAP_AFE;
215−
216− ret = serial8250_register_8250_port(&port8250);
217− break;
218− }
219− default:
220− /* need to add code for these */
221− case PORT_UNKNOWN:
222− dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
223− ret = -ENODEV;
224− break;
225− }
209+ ret = serial8250_register_8250_port(&port8250);
226210 if (ret < 0)
227211 goto out;
228212
@@ -232,7 +216,7 @@ static int of_platform_serial_probe(struct platform_device *ofdev) · 3 unmodified lines
232216 return 0;
233217 out:
234218 kfree(info);
235− irq_dispose_mapping(port.irq);
219+ irq_dispose_mapping(port8250.port.irq);
236220 return ret;
237221 }
238222
@@ -242,14 +226,8 @@ out: · 3 unmodified lines
242226 static int of_platform_serial_remove(struct platform_device *ofdev)
243227 {
244228 struct of_serial_info *info = platform_get_drvdata(ofdev);
245− switch (info->type) {
246− case PORT_8250 ... PORT_MAX_8250:
247− serial8250_unregister_port(info->line);
248− break;
249− default:
250− /* need to add code for these */
251− break;
252− }
229+
230+ serial8250_unregister_port(info->line);
253231
254232 if (info->clk)
255233 clk_disable_unprepare(info->clk);
@@ -258,18 +236,23 @@ static int of_platform_serial_remove(struct platform_device *ofdev) · 2 unmodified lines
258236 }
259237
260238 #ifdef CONFIG_PM_SLEEP
261−static void of_serial_suspend_8250(struct of_serial_info *info)
239+static int of_serial_suspend(struct device *dev)
262240 {
241+ struct of_serial_info *info = dev_get_drvdata(dev);
263242 struct uart_8250_port *port8250 = serial8250_get_port(info->line);
264243 struct uart_port *port = &port8250->port;
265244
266245 serial8250_suspend_port(info->line);
246+
267247 if (info->clk && (!uart_console(port) || console_suspend_enabled))
268248 clk_disable_unprepare(info->clk);
249+
250+ return 0;
269251 }
270252
271−static void of_serial_resume_8250(struct of_serial_info *info)
253+static int of_serial_resume(struct device *dev)
272254 {
255+ struct of_serial_info *info = dev_get_drvdata(dev);
273256 struct uart_8250_port *port8250 = serial8250_get_port(info->line);
274257 struct uart_port *port = &port8250->port;
275258
@@ -277,34 +260,6 @@ static void of_serial_resume_8250(struct of_serial_info *info) · 1 unmodified line
277260 clk_prepare_enable(info->clk);
278261
279262 serial8250_resume_port(info->line);
280−}
281−
282−static int of_serial_suspend(struct device *dev)
283−{
284− struct of_serial_info *info = dev_get_drvdata(dev);
285−
286− switch (info->type) {
287− case PORT_8250 ... PORT_MAX_8250:
288− of_serial_suspend_8250(info);
289− break;
290− default:
291− break;
292− }
293−
294− return 0;
295−}
296−
297−static int of_serial_resume(struct device *dev)
298−{
299− struct of_serial_info *info = dev_get_drvdata(dev);
300−
301− switch (info->type) {
302− case PORT_8250 ... PORT_MAX_8250:
303− of_serial_resume_8250(info);
304− break;
305− default:
306− break;
307− }
308263
309264 return 0;
310265 }
@@ -332,6 +287,7 @@ static const struct of_device_id of_platform_serial_table[] = { · 21 unmodified lines
332287 .data = (void *)PORT_ALTR_16550_F128, },
333288 { .compatible = "mrvl,mmp-uart",
334289 .data = (void *)PORT_XSCALE, },
290+ { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
335291 { /* end of list */ },
336292 };
337293 MODULE_DEVICE_TABLE(of, of_platform_serial_table);
drivers/tty/serial/8250/8250_omap.c+17−16
@@ -790,6 +790,7 @@ static void omap_8250_rx_dma_flush(struct uart_8250_port *p) · 789 unmodified lines
790790 {
791791 struct omap8250_priv *priv = p->port.private_data;
792792 struct uart_8250_dma *dma = p->dma;
793+ struct dma_tx_state state;
793794 unsigned long flags;
794795 int ret;
795796
@@ -800,10 +801,12 @@ static void omap_8250_rx_dma_flush(struct uart_8250_port *p) · 4 unmodified lines
800801 return;
801802 }
802803
803− ret = dmaengine_pause(dma->rxchan);
804− if (WARN_ON_ONCE(ret))
805− priv->rx_dma_broken = true;
806−
804+ ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
805+ if (ret == DMA_IN_PROGRESS) {
806+ ret = dmaengine_pause(dma->rxchan);
807+ if (WARN_ON_ONCE(ret))
808+ priv->rx_dma_broken = true;
809+ }
807810 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
808811
809812 __dma_rx_do_complete(p);
@@ -1075,15 +1078,15 @@ static int omap8250_no_handle_irq(struct uart_port *port) · 265 unmodified lines
10751078 }
10761079
10771080 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1078−static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE;
1081+static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
10791082
10801083 static const struct of_device_id omap8250_dt_ids[] = {
10811084 { .compatible = "ti,omap2-uart" },
10821085 { .compatible = "ti,omap3-uart" },
10831086 { .compatible = "ti,omap4-uart" },
10841087 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1085− { .compatible = "ti,am4372-uart", .data = &am4372_habit, },
1086− { .compatible = "ti,dra742-uart", .data = &am4372_habit, },
1088+ { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1089+ { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
10871090 {},
10881091 };
10891092 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
@@ -1218,14 +1221,6 @@ static int omap8250_probe(struct platform_device *pdev) · 128 unmodified lines
12181221 priv->omap8250_dma.rx_size = RX_TRIGGER;
12191222 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
12201223 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1221−
1222− if (of_machine_is_compatible("ti,am33xx"))
1223− priv->habit |= OMAP_DMA_TX_KICK;
1224− /*
1225− * pause is currently not supported atleast on omap-sdma
1226− * and edma on most earlier kernels.
1227− */
1228− priv->rx_dma_broken = true;
12291224 }
12301225 }
12311226 #endif
@@ -1240,7 +1235,8 @@ static int omap8250_probe(struct platform_device *pdev) · 8 unmodified lines
12401235 pm_runtime_put_autosuspend(&pdev->dev);
12411236 return 0;
12421237 err:
1243− pm_runtime_put(&pdev->dev);
1238+ pm_runtime_dont_use_autosuspend(&pdev->dev);
1239+ pm_runtime_put_sync(&pdev->dev);
12441240 pm_runtime_disable(&pdev->dev);
12451241 return ret;
12461242 }
@@ -1249,6 +1245,7 @@ static int omap8250_remove(struct platform_device *pdev) · 2 unmodified lines
12491245 {
12501246 struct omap8250_priv *priv = platform_get_drvdata(pdev);
12511247
1248+ pm_runtime_dont_use_autosuspend(&pdev->dev);
12521249 pm_runtime_put_sync(&pdev->dev);
12531250 pm_runtime_disable(&pdev->dev);
12541251 serial8250_unregister_port(priv->line);
@@ -1348,6 +1345,10 @@ static int omap8250_runtime_suspend(struct device *dev) · 93 unmodified lines
13481345 struct omap8250_priv *priv = dev_get_drvdata(dev);
13491346 struct uart_8250_port *up;
13501347
1348+ /* In case runtime-pm tries this before we are setup */
1349+ if (!priv)
1350+ return 0;
1351+
13511352 up = serial8250_get_port(priv->line);
13521353 /*
13531354 * When using 'no_console_suspend', the console UART must not be
drivers/tty/serial/8250/8250_pci.c+22−493
@@ -1477,11 +1477,16 @@ static int pci_fintek_init(struct pci_dev *dev) · 1476 unmodified lines
14771477 {
14781478 unsigned long iobase;
14791479 u32 max_port, i;
1480− u32 bar_data[3];
1480+ resource_size_t bar_data[3];
14811481 u8 config_base;
14821482 struct serial_private *priv = pci_get_drvdata(dev);
14831483 struct uart_8250_port *port;
14841484
1485+ if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1486+ !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1487+ !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1488+ return -ENODEV;
1489+
14851490 switch (dev->device) {
14861491 case 0x1104: /* 4 ports */
14871492 case 0x1108: /* 8 ports */
@@ -1495,9 +1500,9 @@ static int pci_fintek_init(struct pci_dev *dev) · 7 unmodified lines
14951500 }
14961501
14971502 /* Get the io address dispatch from the BIOS */
1498− pci_read_config_dword(dev, 0x24, &bar_data[0]);
1499− pci_read_config_dword(dev, 0x20, &bar_data[1]);
1500− pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1503+ bar_data[0] = pci_resource_start(dev, 5);
1504+ bar_data[1] = pci_resource_start(dev, 4);
1505+ bar_data[2] = pci_resource_start(dev, 3);
15011506
15021507 for (i = 0; i < max_port; ++i) {
15031508 /* UART0 configuration offset start from 0x40 */
@@ -1605,135 +1610,6 @@ static int pci_eg20t_init(struct pci_dev *dev) · 101 unmodified lines
16051610 #endif
16061611 }
16071612
1608−#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1609−#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1610−
1611−#define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
1612−#define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
1613−#define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
1614−#define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
1615−#define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
1616−#define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
1617−#define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
1618−#define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
1619−#define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
1620−#define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
1621−#define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
1622−#define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
1623−
1624−static int
1625−pci_xr17c154_setup(struct serial_private *priv,
1626− const struct pciserial_board *board,
1627− struct uart_8250_port *port, int idx)
1628−{
1629− port->port.flags |= UPF_EXAR_EFR;
1630− return pci_default_setup(priv, board, port, idx);
1631−}
1632−
1633−static inline int
1634−xr17v35x_has_slave(struct serial_private *priv)
1635−{
1636− const int dev_id = priv->dev->device;
1637−
1638− return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1639− (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1640−}
1641−
1642−static int
1643−pci_xr17v35x_setup(struct serial_private *priv,
1644− const struct pciserial_board *board,
1645− struct uart_8250_port *port, int idx)
1646−{
1647− u8 __iomem *p;
1648−
1649− p = pci_ioremap_bar(priv->dev, 0);
1650− if (p == NULL)
1651− return -ENOMEM;
1652−
1653− port->port.flags |= UPF_EXAR_EFR;
1654−
1655− /*
1656− * Setup the uart clock for the devices on expansion slot to
1657− * half the clock speed of the main chip (which is 125MHz)
1658− */
1659− if (xr17v35x_has_slave(priv) && idx >= 8)
1660− port->port.uartclk = (7812500 * 16 / 2);
1661−
1662− /*
1663− * Setup Multipurpose Input/Output pins.
1664− */
1665− if (idx == 0) {
1666− writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
1667− writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
1668− writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
1669− writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
1670− writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
1671− writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
1672− writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
1673− writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
1674− writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
1675− writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
1676− writeb(0x00, p + UART_EXAR_MPIOSEL_15_8);
1677− writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
1678− }
1679− writeb(0x00, p + UART_EXAR_8XMODE);
1680− writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1681− writeb(128, p + UART_EXAR_TXTRG);
1682− writeb(128, p + UART_EXAR_RXTRG);
1683− iounmap(p);
1684−
1685− return pci_default_setup(priv, board, port, idx);
1686−}
1687−
1688−#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1689−#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1690−#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1691−#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1692−
1693−static int
1694−pci_fastcom335_setup(struct serial_private *priv,
1695− const struct pciserial_board *board,
1696− struct uart_8250_port *port, int idx)
1697−{
1698− u8 __iomem *p;
1699−
1700− p = pci_ioremap_bar(priv->dev, 0);
1701− if (p == NULL)
1702− return -ENOMEM;
1703−
1704− port->port.flags |= UPF_EXAR_EFR;
1705−
1706− /*
1707− * Setup Multipurpose Input/Output pins.
1708− */
1709− if (idx == 0) {
1710− switch (priv->dev->device) {
1711− case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1712− case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1713− writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
1714− writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
1715− writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
1716− break;
1717− case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1718− case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1719− writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
1720− writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
1721− writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
1722− break;
1723− }
1724− writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
1725− writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
1726− writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
1727− }
1728− writeb(0x00, p + UART_EXAR_8XMODE);
1729− writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1730− writeb(32, p + UART_EXAR_TXTRG);
1731− writeb(32, p + UART_EXAR_RXTRG);
1732− iounmap(p);
1733−
1734− return pci_default_setup(priv, board, port, idx);
1735−}
1736−
17371613 static int
17381614 pci_wch_ch353_setup(struct serial_private *priv,
17391615 const struct pciserial_board *board,
@@ -1809,9 +1685,6 @@ pci_wch_ch38x_setup(struct serial_private *priv, · 69 unmodified lines
18091685 #define PCI_VENDOR_ID_AGESTAR 0x5372
18101686 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
18111687 #define PCI_VENDOR_ID_ASIX 0x9710
1812−#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1813−#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1814−#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
18151688 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
18161689 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
18171690
@@ -2272,65 +2145,6 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { · 454 unmodified lines
22722145 .init = pci_timedia_init,
22732146 .setup = pci_timedia_setup,
22742147 },
2275− /*
2276− * Exar cards
2277− */
2278− {
2279− .vendor = PCI_VENDOR_ID_EXAR,
2280− .device = PCI_DEVICE_ID_EXAR_XR17C152,
2281− .subvendor = PCI_ANY_ID,
2282− .subdevice = PCI_ANY_ID,
2283− .setup = pci_xr17c154_setup,
2284− },
2285− {
2286− .vendor = PCI_VENDOR_ID_EXAR,
2287− .device = PCI_DEVICE_ID_EXAR_XR17C154,
2288− .subvendor = PCI_ANY_ID,
2289− .subdevice = PCI_ANY_ID,
2290− .setup = pci_xr17c154_setup,
2291− },
2292− {
2293− .vendor = PCI_VENDOR_ID_EXAR,
2294− .device = PCI_DEVICE_ID_EXAR_XR17C158,
2295− .subvendor = PCI_ANY_ID,
2296− .subdevice = PCI_ANY_ID,
2297− .setup = pci_xr17c154_setup,
2298− },
2299− {
2300− .vendor = PCI_VENDOR_ID_EXAR,
2301− .device = PCI_DEVICE_ID_EXAR_XR17V352,
2302− .subvendor = PCI_ANY_ID,
2303− .subdevice = PCI_ANY_ID,
2304− .setup = pci_xr17v35x_setup,
2305− },
2306− {
2307− .vendor = PCI_VENDOR_ID_EXAR,
2308− .device = PCI_DEVICE_ID_EXAR_XR17V354,
2309− .subvendor = PCI_ANY_ID,
2310− .subdevice = PCI_ANY_ID,
2311− .setup = pci_xr17v35x_setup,
2312− },
2313− {
2314− .vendor = PCI_VENDOR_ID_EXAR,
2315− .device = PCI_DEVICE_ID_EXAR_XR17V358,
2316− .subvendor = PCI_ANY_ID,
2317− .subdevice = PCI_ANY_ID,
2318− .setup = pci_xr17v35x_setup,
2319− },
2320− {
2321− .vendor = PCI_VENDOR_ID_EXAR,
2322− .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2323− .subvendor = PCI_ANY_ID,
2324− .subdevice = PCI_ANY_ID,
2325− .setup = pci_xr17v35x_setup,
2326− },
2327− {
2328− .vendor = PCI_VENDOR_ID_EXAR,
2329− .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2330− .subvendor = PCI_ANY_ID,
2331− .subdevice = PCI_ANY_ID,
2332− .setup = pci_xr17v35x_setup,
2333− },
23342148 /*
23352149 * Xircom cards
23362150 */
@@ -2555,59 +2369,6 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { · 218 unmodified lines
25552369 .subdevice = PCI_ANY_ID,
25562370 .setup = pci_asix_setup,
25572371 },
2558− /*
2559− * Commtech, Inc. Fastcom adapters
2560− *
2561− */
2562− {
2563− .vendor = PCI_VENDOR_ID_COMMTECH,
2564− .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2565− .subvendor = PCI_ANY_ID,
2566− .subdevice = PCI_ANY_ID,
2567− .setup = pci_fastcom335_setup,
2568− },
2569− {
2570− .vendor = PCI_VENDOR_ID_COMMTECH,
2571− .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2572− .subvendor = PCI_ANY_ID,
2573− .subdevice = PCI_ANY_ID,
2574− .setup = pci_fastcom335_setup,
2575− },
2576− {
2577− .vendor = PCI_VENDOR_ID_COMMTECH,
2578− .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2579− .subvendor = PCI_ANY_ID,
2580− .subdevice = PCI_ANY_ID,
2581− .setup = pci_fastcom335_setup,
2582− },
2583− {
2584− .vendor = PCI_VENDOR_ID_COMMTECH,
2585− .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2586− .subvendor = PCI_ANY_ID,
2587− .subdevice = PCI_ANY_ID,
2588− .setup = pci_fastcom335_setup,
2589− },
2590− {
2591− .vendor = PCI_VENDOR_ID_COMMTECH,
2592− .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2593− .subvendor = PCI_ANY_ID,
2594− .subdevice = PCI_ANY_ID,
2595− .setup = pci_xr17v35x_setup,
2596− },
2597− {
2598− .vendor = PCI_VENDOR_ID_COMMTECH,
2599− .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2600− .subvendor = PCI_ANY_ID,
2601− .subdevice = PCI_ANY_ID,
2602− .setup = pci_xr17v35x_setup,
2603− },
2604− {
2605− .vendor = PCI_VENDOR_ID_COMMTECH,
2606− .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2607− .subvendor = PCI_ANY_ID,
2608− .subdevice = PCI_ANY_ID,
2609− .setup = pci_xr17v35x_setup,
2610− },
26112372 /*
26122373 * Broadcom TruManage (NetXtreme)
26132374 */
@@ -2719,17 +2480,11 @@ enum pci_board_num_t { · 105 unmodified lines
27192480
27202481 pbn_b0_4_1152000,
27212482
2722− pbn_b0_2_1152000_200,
2723− pbn_b0_4_1152000_200,
2724− pbn_b0_8_1152000_200,
2483+ pbn_b0_4_1250000,
27252484
27262485 pbn_b0_2_1843200,
27272486 pbn_b0_4_1843200,
27282487
2729− pbn_b0_2_1843200_200,
2730− pbn_b0_4_1843200_200,
2731− pbn_b0_8_1843200_200,
2732−
27332488 pbn_b0_1_4000000,
27342489
27352490 pbn_b0_bt_1_115200,
@@ -2820,15 +2575,6 @@ enum pci_board_num_t { · 84 unmodified lines
28202575 pbn_computone_6,
28212576 pbn_computone_8,
28222577 pbn_sbsxrsio,
2823− pbn_exar_XR17C152,
2824− pbn_exar_XR17C154,
2825− pbn_exar_XR17C158,
2826− pbn_exar_XR17V352,
2827− pbn_exar_XR17V354,
2828− pbn_exar_XR17V358,
2829− pbn_exar_XR17V4358,
2830− pbn_exar_XR17V8358,
2831− pbn_exar_ibm_saturn,
28322578 pbn_pasemi_1682M,
28332579 pbn_ni8430_2,
28342580 pbn_ni8430_4,
@@ -2933,25 +2679,11 @@ static struct pciserial_board pci_boards[] = { · 98 unmodified lines
29332679 .uart_offset = 8,
29342680 },
29352681
2936− [pbn_b0_2_1152000_200] = {
2937− .flags = FL_BASE0,
2938− .num_ports = 2,
2939− .base_baud = 1152000,
2940− .uart_offset = 0x200,
2941− },
2942−
2943− [pbn_b0_4_1152000_200] = {
2682+ [pbn_b0_4_1250000] = {
29442683 .flags = FL_BASE0,
29452684 .num_ports = 4,
2946− .base_baud = 1152000,
2947− .uart_offset = 0x200,
2948− },
2949−
2950− [pbn_b0_8_1152000_200] = {
2951− .flags = FL_BASE0,
2952− .num_ports = 8,
2953− .base_baud = 1152000,
2954− .uart_offset = 0x200,
2685+ .base_baud = 1250000,
2686+ .uart_offset = 8,
29552687 },
29562688
29572689 [pbn_b0_2_1843200] = {
@@ -2967,24 +2699,6 @@ static struct pciserial_board pci_boards[] = { · 9 unmodified lines
29672699 .uart_offset = 8,
29682700 },
29692701
2970− [pbn_b0_2_1843200_200] = {
2971− .flags = FL_BASE0,
2972− .num_ports = 2,
2973− .base_baud = 1843200,
2974− .uart_offset = 0x200,
2975− },
2976− [pbn_b0_4_1843200_200] = {
2977− .flags = FL_BASE0,
2978− .num_ports = 4,
2979− .base_baud = 1843200,
2980− .uart_offset = 0x200,
2981− },
2982− [pbn_b0_8_1843200_200] = {
2983− .flags = FL_BASE0,
2984− .num_ports = 8,
2985− .base_baud = 1843200,
2986− .uart_offset = 0x200,
2987− },
29882702 [pbn_b0_1_4000000] = {
29892703 .flags = FL_BASE0,
29902704 .num_ports = 1,
@@ -3468,76 +3182,6 @@ static struct pciserial_board pci_boards[] = { · 477 unmodified lines
34683182 .uart_offset = 256,
34693183 .reg_shift = 4,
34703184 },
3471− /*
3472− * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3473− * Only basic 16550A support.
3474− * XR17C15[24] are not tested, but they should work.
3475− */
3476− [pbn_exar_XR17C152] = {
3477− .flags = FL_BASE0,
3478− .num_ports = 2,
3479− .base_baud = 921600,
3480− .uart_offset = 0x200,
3481− },
3482− [pbn_exar_XR17C154] = {
3483− .flags = FL_BASE0,
3484− .num_ports = 4,
3485− .base_baud = 921600,
3486− .uart_offset = 0x200,
3487− },
3488− [pbn_exar_XR17C158] = {
3489− .flags = FL_BASE0,
3490− .num_ports = 8,
3491− .base_baud = 921600,
3492− .uart_offset = 0x200,
3493− },
3494− [pbn_exar_XR17V352] = {
3495− .flags = FL_BASE0,
3496− .num_ports = 2,
3497− .base_baud = 7812500,
3498− .uart_offset = 0x400,
3499− .reg_shift = 0,
3500− .first_offset = 0,
3501− },
3502− [pbn_exar_XR17V354] = {
3503− .flags = FL_BASE0,
3504− .num_ports = 4,
3505− .base_baud = 7812500,
3506− .uart_offset = 0x400,
3507− .reg_shift = 0,
3508− .first_offset = 0,
3509− },
3510− [pbn_exar_XR17V358] = {
3511− .flags = FL_BASE0,
3512− .num_ports = 8,
3513− .base_baud = 7812500,
3514− .uart_offset = 0x400,
3515− .reg_shift = 0,
3516− .first_offset = 0,
3517− },
3518− [pbn_exar_XR17V4358] = {
3519− .flags = FL_BASE0,
3520− .num_ports = 12,
3521− .base_baud = 7812500,
3522− .uart_offset = 0x400,
3523− .reg_shift = 0,
3524− .first_offset = 0,
3525− },
3526− [pbn_exar_XR17V8358] = {
3527− .flags = FL_BASE0,
3528− .num_ports = 16,
3529− .base_baud = 7812500,
3530− .uart_offset = 0x400,
3531− .reg_shift = 0,
3532− .first_offset = 0,
3533− },
3534− [pbn_exar_ibm_saturn] = {
3535− .flags = FL_BASE0,
3536− .num_ports = 1,
3537− .base_baud = 921600,
3538− .uart_offset = 0x200,
3539− },
3540−
35413185 /*
35423186 * PA Semi PWRficient PA6T-1682M on-chip UART
35433187 */
@@ -3734,6 +3378,10 @@ static const struct pci_device_id blacklist[] = { · 190 unmodified lines
37343378 { PCI_VDEVICE(INTEL, 0x228c), },
37353379 { PCI_VDEVICE(INTEL, 0x9ce3), },
37363380 { PCI_VDEVICE(INTEL, 0x9ce4), },
3381+
3382+ /* Exar devices */
3383+ { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3384+ { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
37373385 };
37383386
37393387 /*
@@ -3908,7 +3556,7 @@ err_out: · 168 unmodified lines
39083556 }
39093557 EXPORT_SYMBOL_GPL(pciserial_init_ports);
39103558
3911−void pciserial_detach_ports(struct serial_private *priv)
3559+static void pciserial_detach_ports(struct serial_private *priv)
39123560 {
39133561 struct pci_serial_quirk *quirk;
39143562 int i;
@@ -4159,58 +3807,6 @@ static struct pci_device_id serial_pci_tbl[] = { · 244 unmodified lines
41593807 PCI_VENDOR_ID_AFAVLAB,
41603808 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
41613809 pbn_b0_4_1152000 },
4162− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4163− PCI_SUBVENDOR_ID_CONNECT_TECH,
4164− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4165− pbn_b0_2_1843200_200 },
4166− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4167− PCI_SUBVENDOR_ID_CONNECT_TECH,
4168− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4169− pbn_b0_4_1843200_200 },
4170− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4171− PCI_SUBVENDOR_ID_CONNECT_TECH,
4172− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4173− pbn_b0_8_1843200_200 },
4174− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4175− PCI_SUBVENDOR_ID_CONNECT_TECH,
4176− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4177− pbn_b0_2_1843200_200 },
4178− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4179− PCI_SUBVENDOR_ID_CONNECT_TECH,
4180− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4181− pbn_b0_4_1843200_200 },
4182− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4183− PCI_SUBVENDOR_ID_CONNECT_TECH,
4184− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4185− pbn_b0_8_1843200_200 },
4186− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4187− PCI_SUBVENDOR_ID_CONNECT_TECH,
4188− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4189− pbn_b0_2_1843200_200 },
4190− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4191− PCI_SUBVENDOR_ID_CONNECT_TECH,
4192− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4193− pbn_b0_4_1843200_200 },
4194− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4195− PCI_SUBVENDOR_ID_CONNECT_TECH,
4196− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4197− pbn_b0_8_1843200_200 },
4198− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4199− PCI_SUBVENDOR_ID_CONNECT_TECH,
4200− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4201− pbn_b0_2_1843200_200 },
4202− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4203− PCI_SUBVENDOR_ID_CONNECT_TECH,
4204− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4205− pbn_b0_4_1843200_200 },
4206− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4207− PCI_SUBVENDOR_ID_CONNECT_TECH,
4208− PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4209− pbn_b0_8_1843200_200 },
4210− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4211− PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4212− 0, 0, pbn_exar_ibm_saturn },
4213−
42143810 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
42153811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
42163812 pbn_b2_bt_1_115200 },
@@ -4938,45 +4534,6 @@ static struct pci_device_id serial_pci_tbl[] = { · 721 unmodified lines
49384534 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
49394535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
49404536 pbn_b3_8_115200 },
4941−
4942− /*
4943− * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4944− */
4945− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4946− PCI_ANY_ID, PCI_ANY_ID,
4947− 0,
4948− 0, pbn_exar_XR17C152 },
4949− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4950− PCI_ANY_ID, PCI_ANY_ID,
4951− 0,
4952− 0, pbn_exar_XR17C154 },
4953− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4954− PCI_ANY_ID, PCI_ANY_ID,
4955− 0,
4956− 0, pbn_exar_XR17C158 },
4957− /*
4958− * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
4959− */
4960− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4961− PCI_ANY_ID, PCI_ANY_ID,
4962− 0,
4963− 0, pbn_exar_XR17V352 },
4964− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4965− PCI_ANY_ID, PCI_ANY_ID,
4966− 0,
4967− 0, pbn_exar_XR17V354 },
4968− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4969− PCI_ANY_ID, PCI_ANY_ID,
4970− 0,
4971− 0, pbn_exar_XR17V358 },
4972− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
4973− PCI_ANY_ID, PCI_ANY_ID,
4974− 0,
4975− 0, pbn_exar_XR17V4358 },
4976− { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
4977− PCI_ANY_ID, PCI_ANY_ID,
4978− 0,
4979− 0, pbn_exar_XR17V8358 },
49804537 /*
49814538 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
49824539 */
@@ -5552,43 +5109,15 @@ static struct pci_device_id serial_pci_tbl[] = { · 569 unmodified lines
55525109 PCI_ANY_ID, PCI_ANY_ID,
55535110 0, 0, pbn_wch384_4 },
55545111
5555− /*
5556− * Commtech, Inc. Fastcom adapters
5557− */
5558− { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5559− PCI_ANY_ID, PCI_ANY_ID,
5560− 0,
5561− 0, pbn_b0_2_1152000_200 },
5562− { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5563− PCI_ANY_ID, PCI_ANY_ID,
5564− 0,
5565− 0, pbn_b0_4_1152000_200 },
5566− { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5567− PCI_ANY_ID, PCI_ANY_ID,
5568− 0,
5569− 0, pbn_b0_4_1152000_200 },
5570− { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5571− PCI_ANY_ID, PCI_ANY_ID,
5572− 0,
5573− 0, pbn_b0_8_1152000_200 },
5574− { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5575− PCI_ANY_ID, PCI_ANY_ID,
5576− 0,
5577− 0, pbn_exar_XR17V352 },
5578− { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5579− PCI_ANY_ID, PCI_ANY_ID,
5580− 0,
5581− 0, pbn_exar_XR17V354 },
5582− { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5583− PCI_ANY_ID, PCI_ANY_ID,
5584− 0,
5585− 0, pbn_exar_XR17V358 },
5586−
55875112 /* Fintek PCI serial cards */
55885113 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
55895114 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
55905115 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
55915116
5117+ /* MKS Tenta SCOM-080x serial cards */
5118+ { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5119+ { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5120+
55925121 /*
55935122 * These entries match devices with class COMMUNICATION_SERIAL,
55945123 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
drivers/tty/serial/8250/8250_port.c+28−4
@@ -44,6 +44,12 @@ · 43 unmodified lines
4444
4545 #include "8250.h"
4646
47+/*
48+ * These are definitions for the Exar XR17V35X and XR17(C|D)15X
49+ */
50+#define UART_EXAR_SLEEP 0x8b /* Sleep mode */
51+#define UART_EXAR_DVID 0x8d /* Device identification */
52+
4753 /*
4854 * Debugging.
4955 */
@@ -273,6 +279,15 @@ static const struct serial8250_config uart_config[] = { · 223 unmodified lines
273279 .rxtrig_bytes = {1, 4, 8, 14},
274280 .flags = UART_CAP_FIFO,
275281 },
282+ [PORT_DA830] = {
283+ .name = "TI DA8xx/66AK2x",
284+ .fifo_size = 16,
285+ .tx_loadsz = 16,
286+ .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
287+ UART_FCR_R_TRIG_10,
288+ .rxtrig_bytes = {1, 4, 8, 14},
289+ .flags = UART_CAP_FIFO | UART_CAP_AFE,
290+ },
276291 };
277292
278293 /* Uart divisor latch read */
@@ -1753,8 +1768,6 @@ void serial8250_tx_chars(struct uart_8250_port *up) · 1474 unmodified lines
17531768 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
17541769 uart_write_wakeup(port);
17551770
1756− pr_debug("%s: THRE\n", __func__);
1757−
17581771 /*
17591772 * With RPM enabled, we have to wait until the FIFO is empty before the
17601773 * HW can go idle. So we get here once again with empty FIFO and disable
@@ -1819,8 +1832,6 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir) · 58 unmodified lines
18191832
18201833 status = serial_port_in(port, UART_LSR);
18211834
1822− pr_debug("%s: status = %x\n", __func__, status);
1823−
18241835 if (status & (UART_LSR_DR | UART_LSR_BI)) {
18251836 if (!up->dma || handle_rx_dma(up, iir))
18261837 status = serial8250_rx_chars(up, status);
@@ -2118,6 +2129,19 @@ int serial8250_do_startup(struct uart_port *port) · 291 unmodified lines
21182129 serial_port_out(port, UART_LCR, 0);
21192130 }
21202131
2132+ if (port->type == PORT_DA830) {
2133+ /* Reset the port */
2134+ serial_port_out(port, UART_IER, 0);
2135+ serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2136+ mdelay(10);
2137+
2138+ /* Enable Tx, Rx and free run mode */
2139+ serial_port_out(port, UART_DA830_PWREMU_MGMT,
2140+ UART_DA830_PWREMU_MGMT_UTRST |
2141+ UART_DA830_PWREMU_MGMT_URRST |
2142+ UART_DA830_PWREMU_MGMT_FREE);
2143+ }
2144+
21212145 #ifdef CONFIG_SERIAL_8250_RSA
21222146 /*
21232147 * If this is an RSA port, see if we can kick it up to the
drivers/tty/serial/8250/Kconfig+8−3
@@ -117,7 +117,7 @@ config SERIAL_8250_DMA · 116 unmodified lines
117117 compatible UART controllers that support DMA signaling.
118118
119119 config SERIAL_8250_PCI
120− tristate "8250/16550 PCI device support" if EXPERT
120+ tristate "8250/16550 PCI device support"
121121 depends on SERIAL_8250 && PCI
122122 default SERIAL_8250
123123 help
@@ -127,6 +127,11 @@ config SERIAL_8250_PCI · 3 unmodified lines
127127 Note that serial ports on NetMos 9835 Multi-I/O cards are handled
128128 by the parport_serial driver, enabled with CONFIG_PARPORT_SERIAL.
129129
130+config SERIAL_8250_EXAR
131+ tristate "8250/16550 PCI device support"
132+ depends on SERIAL_8250_PCI
133+ default SERIAL_8250
134+
130135 config SERIAL_8250_HP300
131136 tristate
132137 depends on SERIAL_8250 && HP300
@@ -402,7 +407,7 @@ config SERIAL_8250_INGENIC · 269 unmodified lines
402407 its UARTs, say Y to this option. If unsure, say N.
403408
404409 config SERIAL_8250_LPSS
405− tristate "Support for serial ports on Intel LPSS platforms" if EXPERT
410+ tristate "Support for serial ports on Intel LPSS platforms"
406411 default SERIAL_8250
407412 depends on SERIAL_8250 && PCI
408413 depends on X86 || COMPILE_TEST
@@ -417,7 +422,7 @@ config SERIAL_8250_LPSS · 8 unmodified lines
417422 - Intel Quark X1000 SoC
418423
419424 config SERIAL_8250_MID
420− tristate "Support for serial ports on Intel MID platforms" if EXPERT
425+ tristate "Support for serial ports on Intel MID platforms"
421426 default SERIAL_8250
422427 depends on SERIAL_8250 && PCI
423428 depends on X86 || COMPILE_TEST
drivers/tty/serial/8250/Makefile+1−0
@@ -10,6 +10,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o · 9 unmodified lines
1010 8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o
1111 obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o
1212 obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o
13+obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o
1314 obj-$(CONFIG_SERIAL_8250_HP300) += 8250_hp300.o
1415 obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o
1516 obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o
drivers/tty/serial/Kconfig+1−0
@@ -1161,6 +1161,7 @@ config SERIAL_LANTIQ · 1160 unmodified lines
11611161 depends on LANTIQ
11621162 select SERIAL_CORE
11631163 select SERIAL_CORE_CONSOLE
1164+ select SERIAL_EARLYCON
11641165 help
11651166 Support for console and UART on Lantiq SoCs.
11661167
drivers/tty/serial/amba-pl010.c+1−1
@@ -554,7 +554,7 @@ static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) · 553 unmodified lines
554554 return ret;
555555 }
556556
557−static struct uart_ops amba_pl010_pops = {
557+static const struct uart_ops amba_pl010_pops = {
558558 .tx_empty = pl010_tx_empty,
559559 .set_mctrl = pl010_set_mctrl,
560560 .get_mctrl = pl010_get_mctrl,
drivers/tty/serial/amba-pl011.c+61−9
@@ -97,6 +97,7 @@ struct vendor_data { · 96 unmodified lines
9797 unsigned int fr_dsr;
9898 unsigned int fr_cts;
9999 unsigned int fr_ri;
100+ unsigned int inv_fr;
100101 bool access_32b;
101102 bool oversampling;
102103 bool dma_threshold;
@@ -141,6 +142,30 @@ static struct vendor_data vendor_sbsa = { · 38 unmodified lines
141142 .fixed_options = true,
142143 };
143144
145+/*
146+ * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
147+ * occasionally getting stuck as 1. To avoid the potential for a hang, check
148+ * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
149+ * implementations, so only do so if an affected platform is detected in
150+ * parse_spcr().
151+ */
152+static bool qdf2400_e44_present = false;
153+
154+static struct vendor_data vendor_qdt_qdf2400_e44 = {
155+ .reg_offset = pl011_std_offsets,
156+ .fr_busy = UART011_FR_TXFE,
157+ .fr_dsr = UART01x_FR_DSR,
158+ .fr_cts = UART01x_FR_CTS,
159+ .fr_ri = UART011_FR_RI,
160+ .inv_fr = UART011_FR_TXFE,
161+ .access_32b = true,
162+ .oversampling = false,
163+ .dma_threshold = false,
164+ .cts_event_workaround = false,
165+ .always_enabled = true,
166+ .fixed_options = true,
167+};
168+
144169 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145170 [REG_DR] = UART01x_DR,
146171 [REG_ST_DMAWM] = ST_UART011_DMAWM,
@@ -1518,7 +1543,10 @@ static unsigned int pl011_tx_empty(struct uart_port *port) · 1371 unmodified lines
15181543 {
15191544 struct uart_amba_port *uap =
15201545 container_of(port, struct uart_amba_port, port);
1521− unsigned int status = pl011_read(uap, REG_FR);
1546+
1547+ /* Allow feature register bits to be inverted to work around errata */
1548+ unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1549+
15221550 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
15231551 0 : TIOCSER_TEMT;
15241552 }
@@ -2114,7 +2142,7 @@ static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) · 589 unmodified lines
21142142 return ret;
21152143 }
21162144
2117−static struct uart_ops amba_pl011_pops = {
2145+static const struct uart_ops amba_pl011_pops = {
21182146 .tx_empty = pl011_tx_empty,
21192147 .set_mctrl = pl011_set_mctrl,
21202148 .get_mctrl = pl011_get_mctrl,
@@ -2215,10 +2243,12 @@ pl011_console_write(struct console *co, const char *s, unsigned int count) · 94 unmodified lines
22152243 uart_console_write(&uap->port, s, count, pl011_console_putchar);
22162244
22172245 /*
2218− * Finally, wait for transmitter to become empty
2219− * and restore the TCR
2246+ * Finally, wait for transmitter to become empty and restore the
2247+ * TCR. Allow feature register bits to be inverted to work around
2248+ * errata.
22202249 */
2221− while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2250+ while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2251+ & uap->vendor->fr_busy)
22222252 cpu_relax();
22232253 if (!uap->vendor->always_enabled)
22242254 pl011_write(old_cr, uap, REG_CR);
@@ -2340,8 +2370,12 @@ static int __init pl011_console_match(struct console *co, char *name, int idx, · 115 unmodified lines
23402370 resource_size_t addr;
23412371 int i;
23422372
2343− if (strcmp(name, "pl011") != 0)
2373+ if (strcmp(name, "qdf2400_e44") == 0) {
2374+ pr_info_once("UART: Working around QDF2400 SoC erratum 44");
2375+ qdf2400_e44_present = true;
2376+ } else if (strcmp(name, "pl011") != 0 || strcmp(name, "ttyAMA") != 0) {
23442377 return -ENODEV;
2378+ }
23452379
23462380 if (uart_parse_earlycon(options, &iotype, &addr, &options))
23472381 return -ENODEV;
@@ -2376,13 +2410,29 @@ static struct console amba_console = { · 28 unmodified lines
23762410 .device = uart_console_device,
23772411 .setup = pl011_console_setup,
23782412 .match = pl011_console_match,
2379− .flags = CON_PRINTBUFFER,
2413+ .flags = CON_PRINTBUFFER | CON_ANYTIME,
23802414 .index = -1,
23812415 .data = &amba_reg,
23822416 };
23832417
23842418 #define AMBA_CONSOLE (&amba_console)
23852419
2420+static void qdf2400_e44_putc(struct uart_port *port, int c)
2421+{
2422+ while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2423+ cpu_relax();
2424+ writel(c, port->membase + UART01x_DR);
2425+ while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2426+ cpu_relax();
2427+}
2428+
2429+static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2430+{
2431+ struct earlycon_device *dev = con->data;
2432+
2433+ uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2434+}
2435+
23862436 static void pl011_putc(struct uart_port *port, int c)
23872437 {
23882438 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
@@ -2408,7 +2458,8 @@ static int __init pl011_early_console_setup(struct earlycon_device *device, · 19 unmodified lines
24082458 if (!device->port.membase)
24092459 return -ENODEV;
24102460
2411− device->con->write = pl011_early_write;
2461+ device->con->write = qdf2400_e44_present ?
2462+ qdf2400_e44_early_write : pl011_early_write;
24122463 return 0;
24132464 }
24142465 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
@@ -2645,7 +2696,8 @@ static int sbsa_uart_probe(struct platform_device *pdev) · 230 unmodified lines
26452696 uap->port.irq = ret;
26462697
26472698 uap->reg_offset = vendor_sbsa.reg_offset;
2648− uap->vendor = &vendor_sbsa;
2699+ uap->vendor = qdf2400_e44_present ?
2700+ &vendor_qdt_qdf2400_e44 : &vendor_sbsa;
26492701 uap->fifosize = 32;
26502702 uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM;
26512703 uap->port.ops = &sbsa_uart_pops;
drivers/tty/serial/ar933x_uart.c+1−1
@@ -493,7 +493,7 @@ static int ar933x_uart_verify_port(struct uart_port *port, · 492 unmodified lines
493493 return 0;
494494 }
495495
496−static struct uart_ops ar933x_uart_ops = {
496+static const struct uart_ops ar933x_uart_ops = {
497497 .tx_empty = ar933x_uart_tx_empty,
498498 .set_mctrl = ar933x_uart_set_mctrl,
499499 .get_mctrl = ar933x_uart_get_mctrl,
drivers/tty/serial/atmel_serial.c+48−3
@@ -175,6 +175,17 @@ struct atmel_uart_port { · 174 unmodified lines
175175 unsigned int pending_status;
176176 spinlock_t lock_suspended;
177177
178+ struct {
179+ u32 cr;
180+ u32 mr;
181+ u32 imr;
182+ u32 brgr;
183+ u32 rtor;
184+ u32 ttgr;
185+ u32 fmr;
186+ u32 fimr;
187+ } cache;
188+
178189 int (*prepare_rx)(struct uart_port *port);
179190 int (*prepare_tx)(struct uart_port *port);
180191 void (*schedule_rx)(struct uart_port *port);
@@ -1758,7 +1769,9 @@ static void atmel_get_ip_name(struct uart_port *port) · 1577 unmodified lines
17581769
17591770 /*
17601771 * Only USART devices from at91sam9260 SOC implement fractional
1761− * baudrate.
1772+ * baudrate. It is available for all asynchronous modes, with the
1773+ * following restriction: the sampling clock's duty cycle is not
1774+ * constant.
17621775 */
17631776 atmel_port->has_frac_baudrate = false;
17641777 atmel_port->has_hw_timer = false;
@@ -2202,8 +2215,7 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, · 437 unmodified lines
22022215 * then
22032216 * 8 CD + FP = selected clock / (2 * baudrate)
22042217 */
2205− if (atmel_port->has_frac_baudrate &&
2206− (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) {
2218+ if (atmel_port->has_frac_baudrate) {
22072219 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
22082220 cd = div >> 3;
22092221 fp = div & ATMEL_US_FP_MASK;
@@ -2659,6 +2671,20 @@ static int atmel_serial_suspend(struct platform_device *pdev, · 449 unmodified lines
26592671 cpu_relax();
26602672 }
26612673
2674+ if (atmel_is_console_port(port) && !console_suspend_enabled) {
2675+ /* Cache register values as we won't get a full shutdown/startup
2676+ * cycle
2677+ */
2678+ atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2679+ atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2680+ atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2681+ atmel_port->cache.rtor = atmel_uart_readl(port,
2682+ atmel_port->rtor);
2683+ atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2684+ atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2685+ atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2686+ }
2687+
26622688 /* we can not wake up if we're running on slow clock */
26632689 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
26642690 if (atmel_serial_clk_will_stop()) {
@@ -2681,6 +2707,25 @@ static int atmel_serial_resume(struct platform_device *pdev) · 16 unmodified lines
26812707 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
26822708 unsigned long flags;
26832709
2710+ if (atmel_is_console_port(port) && !console_suspend_enabled) {
2711+ atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2712+ atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2713+ atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2714+ atmel_uart_writel(port, atmel_port->rtor,
2715+ atmel_port->cache.rtor);
2716+ atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2717+
2718+ if (atmel_port->fifo_size) {
2719+ atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2720+ ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2721+ atmel_uart_writel(port, ATMEL_US_FMR,
2722+ atmel_port->cache.fmr);
2723+ atmel_uart_writel(port, ATMEL_US_FIER,
2724+ atmel_port->cache.fimr);
2725+ }
2726+ atmel_start_rx(port);
2727+ }
2728+
26842729 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
26852730 if (atmel_port->pending) {
26862731 atmel_handle_receive(port, atmel_port->pending);
drivers/tty/serial/bfin_sport_uart.c+1−1
@@ -740,7 +740,7 @@ static int sport_uart_resume(struct device *dev) · 739 unmodified lines
740740 return 0;
741741 }
742742
743−static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
743+static const struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
744744 .suspend = sport_uart_suspend,
745745 .resume = sport_uart_resume,
746746 };
drivers/tty/serial/cpm_uart/cpm_uart_core.c+10−8
@@ -1302,7 +1302,7 @@ static int __init cpm_uart_console_setup(struct console *co, char *options) · 1301 unmodified lines
13021302 struct uart_cpm_port *pinfo;
13031303 struct uart_port *port;
13041304
1305− struct device_node *np = NULL;
1305+ struct device_node *np;
13061306 int i = 0;
13071307
13081308 if (co->index >= UART_NR) {
@@ -1311,17 +1311,19 @@ static int __init cpm_uart_console_setup(struct console *co, char *options) · 2 unmodified lines
13111311 return -ENODEV;
13121312 }
13131313
1314− do {
1315− np = of_find_node_by_type(np, "serial");
1316− if (!np)
1317− return -ENODEV;
1318−
1314+ for_each_node_by_type(np, "serial") {
13191315 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
13201316 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
13211317 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
13221318 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1323− i--;
1324− } while (i++ != co->index);
1319+ continue;
1320+
1321+ if (i++ == co->index)
1322+ break;
1323+ }
1324+
1325+ if (!np)
1326+ return -ENODEV;
13251327
13261328 pinfo = &cpm_uart_ports[co->index];
13271329
drivers/tty/serial/dz.c+1−1
@@ -739,7 +739,7 @@ static int dz_verify_port(struct uart_port *uport, struct serial_struct *ser) · 738 unmodified lines
739739 return ret;
740740 }
741741
742−static struct uart_ops dz_ops = {
742+static const struct uart_ops dz_ops = {
743743 .tx_empty = dz_tx_empty,
744744 .get_mctrl = dz_get_mctrl,
745745 .set_mctrl = dz_set_mctrl,
drivers/tty/serial/efm32-uart.c+1−1
@@ -487,7 +487,7 @@ static int efm32_uart_verify_port(struct uart_port *port, · 486 unmodified lines
487487 return ret;
488488 }
489489
490−static struct uart_ops efm32_uart_pops = {
490+static const struct uart_ops efm32_uart_pops = {
491491 .tx_empty = efm32_uart_tx_empty,
492492 .set_mctrl = efm32_uart_set_mctrl,
493493 .get_mctrl = efm32_uart_get_mctrl,
drivers/tty/serial/fsl_lpuart.c+17−18
@@ -1407,6 +1407,18 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios, · 1406 unmodified lines
14071407 /* ask the core to calculate the divisor */
14081408 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
14091409
1410+ /*
1411+ * Need to update the Ring buffer length according to the selected
1412+ * baud rate and restart Rx DMA path.
1413+ *
1414+ * Since timer function acqures sport->port.lock, need to stop before
1415+ * acquring same lock because otherwise del_timer_sync() can deadlock.
1416+ */
1417+ if (old && sport->lpuart_dma_rx_use) {
1418+ del_timer_sync(&sport->lpuart_timer);
1419+ lpuart_dma_rx_free(&sport->port);
1420+ }
1421+
14101422 spin_lock_irqsave(&sport->port.lock, flags);
14111423
14121424 sport->port.read_status_mask = 0;
@@ -1456,22 +1468,11 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios, · 43 unmodified lines
14561468 /* restore control register */
14571469 writeb(old_cr2, sport->port.membase + UARTCR2);
14581470
1459− /*
1460− * If new baud rate is set, we will also need to update the Ring buffer
1461− * length according to the selected baud rate and restart Rx DMA path.
1462− */
1463− if (old) {
1464− if (sport->lpuart_dma_rx_use) {
1465− del_timer_sync(&sport->lpuart_timer);
1466− lpuart_dma_rx_free(&sport->port);
1467− }
1468−
1469− if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1470− sport->lpuart_dma_rx_use = true;
1471+ if (old && sport->lpuart_dma_rx_use) {
1472+ if (!lpuart_start_rx_dma(sport))
14711473 rx_dma_timer_init(sport);
1472− } else {
1474+ else
14731475 sport->lpuart_dma_rx_use = false;
1474− }
14751476 }
14761477
14771478 spin_unlock_irqrestore(&sport->port.lock, flags);
@@ -2131,12 +2132,10 @@ static int lpuart_resume(struct device *dev) · 653 unmodified lines
21312132
21322133 if (sport->lpuart_dma_rx_use) {
21332134 if (sport->port.irq_wake) {
2134− if (!lpuart_start_rx_dma(sport)) {
2135− sport->lpuart_dma_rx_use = true;
2135+ if (!lpuart_start_rx_dma(sport))
21362136 rx_dma_timer_init(sport);
2137− } else {
2137+ else
21382138 sport->lpuart_dma_rx_use = false;
2139− }
21402139 }
21412140 }
21422141
drivers/tty/serial/icom.c+1−1
@@ -1286,7 +1286,7 @@ static void icom_config_port(struct uart_port *port, int flags) · 1285 unmodified lines
12861286 port->type = PORT_ICOM;
12871287 }
12881288
1289−static struct uart_ops icom_ops = {
1289+static const struct uart_ops icom_ops = {
12901290 .tx_empty = icom_tx_empty,
12911291 .set_mctrl = icom_set_mctrl,
12921292 .get_mctrl = icom_get_mctrl,
drivers/tty/serial/imx.c+18−14
@@ -205,6 +205,7 @@ struct imx_port { · 204 unmodified lines
205205 struct timer_list timer;
206206 unsigned int old_status;
207207 unsigned int have_rtscts:1;
208+ unsigned int have_rtsgpio:1;
208209 unsigned int dte_mode:1;
209210 unsigned int irda_inv_rx:1;
210211 unsigned int irda_inv_tx:1;
@@ -335,15 +336,15 @@ static void imx_port_ucrs_restore(struct uart_port *port, · 124 unmodified lines
335336
336337 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
337338 {
338− *ucr2 &= ~UCR2_CTSC;
339− *ucr2 |= UCR2_CTS;
339+ *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
340340
341341 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
342342 }
343343
344344 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
345345 {
346− *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
346+ *ucr2 &= ~UCR2_CTSC;
347+ *ucr2 |= UCR2_CTS;
347348
348349 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
349350 }
@@ -376,9 +377,9 @@ static void imx_stop_tx(struct uart_port *port) · 26 unmodified lines
376377 readl(port->membase + USR2) & USR2_TXDC) {
377378 temp = readl(port->membase + UCR2);
378379 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
379− imx_port_rts_inactive(sport, &temp);
380− else
381380 imx_port_rts_active(sport, &temp);
381+ else
382+ imx_port_rts_inactive(sport, &temp);
382383 temp |= UCR2_RXEN;
383384 writel(temp, port->membase + UCR2);
384385
@@ -584,9 +585,9 @@ static void imx_start_tx(struct uart_port *port) · 199 unmodified lines
584585 if (port->rs485.flags & SER_RS485_ENABLED) {
585586 temp = readl(port->membase + UCR2);
586587 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
587− imx_port_rts_inactive(sport, &temp);
588− else
589588 imx_port_rts_active(sport, &temp);
589+ else
590+ imx_port_rts_inactive(sport, &temp);
590591 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
591592 temp &= ~UCR2_RXEN;
592593 writel(temp, port->membase + UCR2);
@@ -1476,9 +1477,9 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, · 883 unmodified lines
14761477 */
14771478 if (port->rs485.flags &
14781479 SER_RS485_RTS_AFTER_SEND)
1479− imx_port_rts_inactive(sport, &ucr2);
1480− else
14811480 imx_port_rts_active(sport, &ucr2);
1481+ else
1482+ imx_port_rts_inactive(sport, &ucr2);
14821483 } else {
14831484 imx_port_rts_auto(sport, &ucr2);
14841485 }
@@ -1488,9 +1489,9 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, · 3 unmodified lines
14881489 } else if (port->rs485.flags & SER_RS485_ENABLED) {
14891490 /* disable transmitter */
14901491 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1491− imx_port_rts_inactive(sport, &ucr2);
1492− else
14931492 imx_port_rts_active(sport, &ucr2);
1493+ else
1494+ imx_port_rts_inactive(sport, &ucr2);
14941495 }
14951496
14961497
@@ -1725,16 +1726,16 @@ static int imx_rs485_config(struct uart_port *port, · 228 unmodified lines
17251726 rs485conf->delay_rts_after_send = 0;
17261727
17271728 /* RTS is required to control the transmitter */
1728− if (!sport->have_rtscts)
1729+ if (!sport->have_rtscts && !sport->have_rtsgpio)
17291730 rs485conf->flags &= ~SER_RS485_ENABLED;
17301731
17311732 if (rs485conf->flags & SER_RS485_ENABLED) {
17321733 /* disable transmitter */
17331734 temp = readl(sport->port.membase + UCR2);
17341735 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1735− imx_port_rts_inactive(sport, &temp);
1736− else
17371736 imx_port_rts_active(sport, &temp);
1737+ else
1738+ imx_port_rts_inactive(sport, &temp);
17381739 writel(temp, sport->port.membase + UCR2);
17391740 }
17401741
@@ -2048,6 +2049,9 @@ static int serial_imx_probe_dt(struct imx_port *sport, · 307 unmodified lines
20482049 if (of_get_property(np, "fsl,dte-mode", NULL))
20492050 sport->dte_mode = 1;
20502051
2052+ if (of_get_property(np, "rts-gpios", NULL))
2053+ sport->have_rtsgpio = 1;
2054+
20512055 return 0;
20522056 }
20532057 #else
drivers/tty/serial/ioc3_serial.c+1−1
@@ -1873,7 +1873,7 @@ static int ic3_request_port(struct uart_port *port) · 1872 unmodified lines
18731873 }
18741874
18751875 /* Associate the uart functions above - given to serial core */
1876−static struct uart_ops ioc3_ops = {
1876+static const struct uart_ops ioc3_ops = {
18771877 .tx_empty = ic3_tx_empty,
18781878 .set_mctrl = ic3_set_mctrl,
18791879 .get_mctrl = ic3_get_mctrl,
drivers/tty/serial/ioc4_serial.c+1−1
@@ -2596,7 +2596,7 @@ static int ic4_request_port(struct uart_port *port) · 2595 unmodified lines
25962596
25972597 /* Associate the uart functions above - given to serial core */
25982598
2599−static struct uart_ops ioc4_ops = {
2599+static const struct uart_ops ioc4_ops = {
26002600 .tx_empty = ic4_tx_empty,
26012601 .set_mctrl = ic4_set_mctrl,
26022602 .get_mctrl = ic4_get_mctrl,
drivers/tty/serial/ip22zilog.c+1−1
@@ -930,7 +930,7 @@ static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *s · 929 unmodified lines
930930 return -EINVAL;
931931 }
932932
933−static struct uart_ops ip22zilog_pops = {
933+static const struct uart_ops ip22zilog_pops = {
934934 .tx_empty = ip22zilog_tx_empty,
935935 .set_mctrl = ip22zilog_set_mctrl,
936936 .get_mctrl = ip22zilog_get_mctrl,
drivers/tty/serial/lantiq.c+33−9
@@ -16,7 +16,7 @@ · 15 unmodified lines
1616 *
1717 * Copyright (C) 2004 Infineon IFAP DC COM CPE
1818 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
19− * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
19+ * Copyright (C) 2007 John Crispin <john@phrozen.org>
2020 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
2121 */
2222
@@ -557,7 +557,7 @@ lqasc_verify_port(struct uart_port *port, · 534 unmodified lines
557557 return ret;
558558 }
559559
560−static struct uart_ops lqasc_pops = {
560+static const struct uart_ops lqasc_pops = {
561561 .tx_empty = lqasc_tx_empty,
562562 .set_mctrl = lqasc_set_mctrl,
563563 .get_mctrl = lqasc_get_mctrl,
@@ -590,13 +590,20 @@ lqasc_console_putchar(struct uart_port *port, int ch) · 26 unmodified lines
590590 ltq_w8(ch, port->membase + LTQ_ASC_TBUF);
591591 }
592592
593+static void lqasc_serial_port_write(struct uart_port *port, const char *s,
594+ u_int count)
595+{
596+ unsigned long flags;
597+
598+ spin_lock_irqsave(&ltq_asc_lock, flags);
599+ uart_console_write(port, s, count, lqasc_console_putchar);
600+ spin_unlock_irqrestore(&ltq_asc_lock, flags);
601+}
593602
594603 static void
595604 lqasc_console_write(struct console *co, const char *s, u_int count)
596605 {
597606 struct ltq_uart_port *ltq_port;
598− struct uart_port *port;
599− unsigned long flags;
600607
601608 if (co->index >= MAXPORTS)
602609 return;
@@ -605,11 +612,7 @@ lqasc_console_write(struct console *co, const char *s, u_int count) · 2 unmodified lines
605612 if (!ltq_port)
606613 return;
607614
608− port = &ltq_port->port;
609−
610− spin_lock_irqsave(&ltq_asc_lock, flags);
611− uart_console_write(port, s, count, lqasc_console_putchar);
612− spin_unlock_irqrestore(&ltq_asc_lock, flags);
615+ lqasc_serial_port_write(&ltq_port->port, s, count);
613616 }
614617
615618 static int __init
@@ -659,6 +662,27 @@ lqasc_console_init(void) · 43 unmodified lines
659662 }
660663 console_initcall(lqasc_console_init);
661664
665+static void lqasc_serial_early_console_write(struct console *co,
666+ const char *s,
667+ u_int count)
668+{
669+ struct earlycon_device *dev = co->data;
670+
671+ lqasc_serial_port_write(&dev->port, s, count);
672+}
673+
674+static int __init
675+lqasc_serial_early_console_setup(struct earlycon_device *device,
676+ const char *opt)
677+{
678+ if (!device->port.membase)
679+ return -ENODEV;
680+
681+ device->con->write = lqasc_serial_early_console_write;
682+ return 0;
683+}
684+OF_EARLYCON_DECLARE(lantiq, DRVNAME, lqasc_serial_early_console_setup);
685+
662686 static struct uart_driver lqasc_reg = {
663687 .owner = THIS_MODULE,
664688 .driver_name = DRVNAME,
drivers/tty/serial/lpc32xx_hs.c+1−1
@@ -645,7 +645,7 @@ static int serial_lpc32xx_verify_port(struct uart_port *port, · 644 unmodified lines
645645 return ret;
646646 }
647647
648−static struct uart_ops serial_lpc32xx_pops = {
648+static const struct uart_ops serial_lpc32xx_pops = {
649649 .tx_empty = serial_lpc32xx_tx_empty,
650650 .set_mctrl = serial_lpc32xx_set_mctrl,
651651 .get_mctrl = serial_lpc32xx_get_mctrl,
drivers/tty/serial/max310x.c+1−1
@@ -236,7 +236,7 @@ · 235 unmodified lines
236236
237237 /* Misc definitions */
238238 #define MAX310X_FIFO_SIZE (128)
239−#define MAX310x_REV_MASK (0xfc)
239+#define MAX310x_REV_MASK (0xf8)
240240
241241 /* MAX3107 specific */
242242 #define MAX3107_REV_ID (0xa0)
drivers/tty/serial/meson_uart.c+1−1
@@ -364,7 +364,7 @@ static void meson_uart_set_termios(struct uart_port *port, · 363 unmodified lines
364364
365365 writel(val, port->membase + AML_UART_CONTROL);
366366
367− baud = uart_get_baud_rate(port, termios, old, 9600, 115200);
367+ baud = uart_get_baud_rate(port, termios, old, 9600, 4000000);
368368 meson_uart_change_speed(port, baud);
369369
370370 port->read_status_mask = AML_UART_TX_FIFO_WERR;
drivers/tty/serial/mpsc.c+1−1
@@ -1670,7 +1670,7 @@ static void mpsc_put_poll_char(struct uart_port *port, · 1669 unmodified lines
16701670 }
16711671 #endif
16721672
1673−static struct uart_ops mpsc_pops = {
1673+static const struct uart_ops mpsc_pops = {
16741674 .tx_empty = mpsc_tx_empty,
16751675 .set_mctrl = mpsc_set_mctrl,
16761676 .get_mctrl = mpsc_get_mctrl,
drivers/tty/serial/msm_serial.c+1−0
@@ -1809,6 +1809,7 @@ static const struct of_device_id msm_match_table[] = { · 1808 unmodified lines
18091809 { .compatible = "qcom,msm-uartdm" },
18101810 {}
18111811 };
1812+MODULE_DEVICE_TABLE(of, msm_match_table);
18121813
18131814 static struct platform_driver msm_platform_driver = {
18141815 .remove = msm_serial_remove,
drivers/tty/serial/mxs-auart.c+3−0
@@ -95,6 +95,7 @@ · 94 unmodified lines
9595 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
9696 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
9797 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
98+#define AUART_LINECTRL_SPS (1 << 7)
9899 #define AUART_LINECTRL_WLEN_MASK 0x00000060
99100 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
100101 #define AUART_LINECTRL_FEN (1 << 4)
@@ -1014,6 +1015,8 @@ static void mxs_auart_settermios(struct uart_port *u, · 913 unmodified lines
10141015 ctrl |= AUART_LINECTRL_PEN;
10151016 if ((cflag & PARODD) == 0)
10161017 ctrl |= AUART_LINECTRL_EPS;
1018+ if (cflag & CMSPAR)
1019+ ctrl |= AUART_LINECTRL_SPS;
10171020 }
10181021
10191022 u->read_status_mask = AUART_STAT_OERR;
drivers/tty/serial/omap-serial.c+56−1
@@ -1234,6 +1234,61 @@ out: · 1233 unmodified lines
12341234
12351235 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
12361236
1237+#ifdef CONFIG_SERIAL_EARLYCON
1238+static unsigned int __init omap_serial_early_in(struct uart_port *port,
1239+ int offset)
1240+{
1241+ offset <<= port->regshift;
1242+ return readw(port->membase + offset);
1243+}
1244+
1245+static void __init omap_serial_early_out(struct uart_port *port, int offset,
1246+ int value)
1247+{
1248+ offset <<= port->regshift;
1249+ writew(value, port->membase + offset);
1250+}
1251+
1252+static void __init omap_serial_early_putc(struct uart_port *port, int c)
1253+{
1254+ unsigned int status;
1255+
1256+ for (;;) {
1257+ status = omap_serial_early_in(port, UART_LSR);
1258+ if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1259+ break;
1260+ cpu_relax();
1261+ }
1262+ omap_serial_early_out(port, UART_TX, c);
1263+}
1264+
1265+static void __init early_omap_serial_write(struct console *console,
1266+ const char *s, unsigned int count)
1267+{
1268+ struct earlycon_device *device = console->data;
1269+ struct uart_port *port = &device->port;
1270+
1271+ uart_console_write(port, s, count, omap_serial_early_putc);
1272+}
1273+
1274+static int __init early_omap_serial_setup(struct earlycon_device *device,
1275+ const char *options)
1276+{
1277+ struct uart_port *port = &device->port;
1278+
1279+ if (!(device->port.membase || device->port.iobase))
1280+ return -ENODEV;
1281+
1282+ port->regshift = 2;
1283+ device->con->write = early_omap_serial_write;
1284+ return 0;
1285+}
1286+
1287+OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1288+OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1289+OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1290+#endif /* CONFIG_SERIAL_EARLYCON */
1291+
12371292 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
12381293
12391294 static struct uart_driver serial_omap_reg;
@@ -1395,7 +1450,7 @@ serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) · 155 unmodified lines
13951450 return 0;
13961451 }
13971452
1398−static struct uart_ops serial_omap_pops = {
1453+static const struct uart_ops serial_omap_pops = {
13991454 .tx_empty = serial_omap_tx_empty,
14001455 .set_mctrl = serial_omap_set_mctrl,
14011456 .get_mctrl = serial_omap_get_mctrl,
drivers/tty/serial/pic32_uart.c+3−3
@@ -495,13 +495,13 @@ static int pic32_uart_startup(struct uart_port *port) · 494 unmodified lines
495495
496496 out_t:
497497 kfree(sport->irq_tx_name);
498− free_irq(sport->irq_tx, sport);
498+ free_irq(sport->irq_tx, port);
499499 out_r:
500500 kfree(sport->irq_rx_name);
501− free_irq(sport->irq_rx, sport);
501+ free_irq(sport->irq_rx, port);
502502 out_f:
503503 kfree(sport->irq_fault_name);
504− free_irq(sport->irq_fault, sport);
504+ free_irq(sport->irq_fault, port);
505505 out_done:
506506 return ret;
507507 }
drivers/tty/serial/pmac_zilog.c+1−1
@@ -1379,7 +1379,7 @@ static void pmz_poll_put_char(struct uart_port *port, unsigned char c) · 1378 unmodified lines
13791379
13801380 #endif /* CONFIG_CONSOLE_POLL */
13811381
1382−static struct uart_ops pmz_pops = {
1382+static const struct uart_ops pmz_pops = {
13831383 .tx_empty = pmz_tx_empty,
13841384 .set_mctrl = pmz_set_mctrl,
13851385 .get_mctrl = pmz_get_mctrl,
drivers/tty/serial/pnx8xxx_uart.c+1−1
@@ -631,7 +631,7 @@ pnx8xxx_verify_port(struct uart_port *port, struct serial_struct *ser) · 630 unmodified lines
631631 return ret;
632632 }
633633
634−static struct uart_ops pnx8xxx_pops = {
634+static const struct uart_ops pnx8xxx_pops = {
635635 .tx_empty = pnx8xxx_tx_empty,
636636 .set_mctrl = pnx8xxx_set_mctrl,
637637 .get_mctrl = pnx8xxx_get_mctrl,
drivers/tty/serial/pxa.c+1−1
@@ -762,7 +762,7 @@ static struct console serial_pxa_console = { · 761 unmodified lines
762762 #define PXA_CONSOLE NULL
763763 #endif
764764
765−static struct uart_ops serial_pxa_pops = {
765+static const struct uart_ops serial_pxa_pops = {
766766 .tx_empty = serial_pxa_tx_empty,
767767 .set_mctrl = serial_pxa_set_mctrl,
768768 .get_mctrl = serial_pxa_get_mctrl,
drivers/tty/serial/samsung.c+9−11
@@ -859,7 +859,6 @@ static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) · 858 unmodified lines
859859 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
860860 {
861861 struct s3c24xx_uart_dma *dma = p->dma;
862− dma_cap_mask_t mask;
863862 unsigned long flags;
864863
865864 /* Default slave configuration parameters */
@@ -876,21 +875,17 @@ static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) · 10 unmodified lines
876875 else
877876 dma->tx_conf.dst_maxburst = 1;
878877
879− dma_cap_zero(mask);
880− dma_cap_set(DMA_SLAVE, mask);
878+ dma->rx_chan = dma_request_chan(p->port.dev, "rx");
881879
882− dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
883− dma->rx_param, p->port.dev, "rx");
884− if (!dma->rx_chan)
885− return -ENODEV;
880+ if (IS_ERR(dma->rx_chan))
881+ return PTR_ERR(dma->rx_chan);
886882
887883 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
888884
889− dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
890− dma->tx_param, p->port.dev, "tx");
891− if (!dma->tx_chan) {
885+ dma->tx_chan = dma_request_chan(p->port.dev, "tx");
886+ if (IS_ERR(dma->tx_chan)) {
892887 dma_release_channel(dma->rx_chan);
893− return -ENODEV;
888+ return PTR_ERR(dma->tx_chan);
894889 }
895890
896891 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
@@ -1921,6 +1916,7 @@ static int s3c24xx_serial_resume(struct device *dev) · 1024 unmodified lines
19211916 static int s3c24xx_serial_resume_noirq(struct device *dev)
19221917 {
19231918 struct uart_port *port = s3c24xx_dev_to_port(dev);
1919+ struct s3c24xx_uart_port *ourport = to_ourport(port);
19241920
19251921 if (port) {
19261922 /* restore IRQ mask */
@@ -1930,7 +1926,9 @@ static int s3c24xx_serial_resume_noirq(struct device *dev) · 3 unmodified lines
19301926 uintm &= ~S3C64XX_UINTM_TXD_MSK;
19311927 if (rx_enabled(port))
19321928 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1929+ clk_prepare_enable(ourport->clk);
19331930 wr_regl(port, S3C64XX_UINTM, uintm);
1931+ clk_disable_unprepare(ourport->clk);
19341932 }
19351933 }
19361934
drivers/tty/serial/samsung.h+0−4
@@ -44,10 +44,6 @@ struct s3c24xx_serial_drv_data { · 43 unmodified lines
4444 };
4545
4646 struct s3c24xx_uart_dma {
47− dma_filter_fn fn;
48− void *rx_param;
49− void *tx_param;
50−
5147 unsigned int rx_chan_id;
5248 unsigned int tx_chan_id;
5349
drivers/tty/serial/serial-tegra.c+1−1
@@ -1191,7 +1191,7 @@ static const char *tegra_uart_type(struct uart_port *u) · 1190 unmodified lines
11911191 return TEGRA_UART_TYPE;
11921192 }
11931193
1194−static struct uart_ops tegra_uart_ops = {
1194+static const struct uart_ops tegra_uart_ops = {
11951195 .tx_empty = tegra_uart_tx_empty,
11961196 .set_mctrl = tegra_uart_set_mctrl,
11971197 .get_mctrl = tegra_uart_get_mctrl,
drivers/tty/serial/serial_txx9.c+1−1
@@ -845,7 +845,7 @@ serial_txx9_type(struct uart_port *port) · 844 unmodified lines
845845 return "txx9";
846846 }
847847
848−static struct uart_ops serial_txx9_pops = {
848+static const struct uart_ops serial_txx9_pops = {
849849 .tx_empty = serial_txx9_tx_empty,
850850 .set_mctrl = serial_txx9_set_mctrl,
851851 .get_mctrl = serial_txx9_get_mctrl,
drivers/tty/serial/sh-sci.c+578−514
@@ -101,23 +101,30 @@ enum SCI_CLKS { · 100 unmodified lines
101101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103103
104+struct plat_sci_reg {
105+ u8 offset, size;
106+};
107+
108+struct sci_port_params {
109+ const struct plat_sci_reg regs[SCIx_NR_REGS];
110+ unsigned int fifosize;
111+ unsigned int overrun_reg;
112+ unsigned int overrun_mask;
113+ unsigned int sampling_rate_mask;
114+ unsigned int error_mask;
115+ unsigned int error_clear;
116+};
117+
104118 struct sci_port {
105119 struct uart_port port;
106120
107121 /* Platform configuration */
108− struct plat_sci_port *cfg;
109− unsigned int overrun_reg;
110− unsigned int overrun_mask;
111− unsigned int error_mask;
112− unsigned int error_clear;
122+ const struct sci_port_params *params;
123+ const struct plat_sci_port *cfg;
113124 unsigned int sampling_rate_mask;
114125 resource_size_t reg_size;
115126 struct mctrl_gpios *gpios;
116127
117− /* Break timer */
118− struct timer_list break_timer;
119− int break_flag;
120−
121128 /* Clocks */
122129 struct clk *clks[SCI_NUM_CLKS];
123130 unsigned long clk_rates[SCI_NUM_CLKS];
@@ -141,7 +148,12 @@ struct sci_port { · 17 unmodified lines
141148 struct timer_list rx_timer;
142149 unsigned int rx_timeout;
143150 #endif
151+ unsigned int rx_frame;
152+ int rx_trigger;
153+ struct timer_list rx_fifo_timer;
154+ int rx_fifo_timeout;
144155
156+ bool has_rtscts;
145157 bool autorts;
146158 };
147159
@@ -156,110 +168,97 @@ to_sci_port(struct uart_port *uart) · 8 unmodified lines
156168 return container_of(uart, struct sci_port, port);
157169 }
158170
159−struct plat_sci_reg {
160− u8 offset, size;
161−};
162−
163−/* Helper for invalidating specific entries of an inherited map. */
164−#define sci_reg_invalid { .offset = 0, .size = 0 }
165−
166−static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
167− [SCIx_PROBE_REGTYPE] = {
168− [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
169− },
170−
171+static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
171172 /*
172173 * Common SCI definitions, dependent on the port's regshift
173174 * value.
174175 */
175176 [SCIx_SCI_REGTYPE] = {
176− [SCSMR] = { 0x00, 8 },
177− [SCBRR] = { 0x01, 8 },
178− [SCSCR] = { 0x02, 8 },
179− [SCxTDR] = { 0x03, 8 },
180− [SCxSR] = { 0x04, 8 },
181− [SCxRDR] = { 0x05, 8 },
182− [SCFCR] = sci_reg_invalid,
183− [SCFDR] = sci_reg_invalid,
184− [SCTFDR] = sci_reg_invalid,
185− [SCRFDR] = sci_reg_invalid,
186− [SCSPTR] = sci_reg_invalid,
187− [SCLSR] = sci_reg_invalid,
188− [HSSRR] = sci_reg_invalid,
189− [SCPCR] = sci_reg_invalid,
190− [SCPDR] = sci_reg_invalid,
191− [SCDL] = sci_reg_invalid,
192− [SCCKS] = sci_reg_invalid,
177+ .regs = {
178+ [SCSMR] = { 0x00, 8 },
179+ [SCBRR] = { 0x01, 8 },
180+ [SCSCR] = { 0x02, 8 },
181+ [SCxTDR] = { 0x03, 8 },
182+ [SCxSR] = { 0x04, 8 },
183+ [SCxRDR] = { 0x05, 8 },
184+ },
185+ .fifosize = 1,
186+ .overrun_reg = SCxSR,
187+ .overrun_mask = SCI_ORER,
188+ .sampling_rate_mask = SCI_SR(32),
189+ .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
190+ .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
193191 },
194192
195193 /*
196− * Common definitions for legacy IrDA ports, dependent on
197− * regshift value.
194+ * Common definitions for legacy IrDA ports.
198195 */
199196 [SCIx_IRDA_REGTYPE] = {
200− [SCSMR] = { 0x00, 8 },
201− [SCBRR] = { 0x01, 8 },
202− [SCSCR] = { 0x02, 8 },
203− [SCxTDR] = { 0x03, 8 },
204− [SCxSR] = { 0x04, 8 },
205− [SCxRDR] = { 0x05, 8 },
206− [SCFCR] = { 0x06, 8 },
207− [SCFDR] = { 0x07, 16 },
208− [SCTFDR] = sci_reg_invalid,
209− [SCRFDR] = sci_reg_invalid,
210− [SCSPTR] = sci_reg_invalid,
211− [SCLSR] = sci_reg_invalid,
212− [HSSRR] = sci_reg_invalid,
213− [SCPCR] = sci_reg_invalid,
214− [SCPDR] = sci_reg_invalid,
215− [SCDL] = sci_reg_invalid,
216− [SCCKS] = sci_reg_invalid,
197+ .regs = {
198+ [SCSMR] = { 0x00, 8 },
199+ [SCBRR] = { 0x02, 8 },
200+ [SCSCR] = { 0x04, 8 },
201+ [SCxTDR] = { 0x06, 8 },
202+ [SCxSR] = { 0x08, 16 },
203+ [SCxRDR] = { 0x0a, 8 },
204+ [SCFCR] = { 0x0c, 8 },
205+ [SCFDR] = { 0x0e, 16 },
206+ },
207+ .fifosize = 1,
208+ .overrun_reg = SCxSR,
209+ .overrun_mask = SCI_ORER,
210+ .sampling_rate_mask = SCI_SR(32),
211+ .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
212+ .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
217213 },
218214
219215 /*
220216 * Common SCIFA definitions.
221217 */
222218 [SCIx_SCIFA_REGTYPE] = {
223− [SCSMR] = { 0x00, 16 },
224− [SCBRR] = { 0x04, 8 },
225− [SCSCR] = { 0x08, 16 },
226− [SCxTDR] = { 0x20, 8 },
227− [SCxSR] = { 0x14, 16 },
228− [SCxRDR] = { 0x24, 8 },
229− [SCFCR] = { 0x18, 16 },
230− [SCFDR] = { 0x1c, 16 },
231− [SCTFDR] = sci_reg_invalid,
232− [SCRFDR] = sci_reg_invalid,
233− [SCSPTR] = sci_reg_invalid,
234− [SCLSR] = sci_reg_invalid,
235− [HSSRR] = sci_reg_invalid,
236− [SCPCR] = { 0x30, 16 },
237− [SCPDR] = { 0x34, 16 },
238− [SCDL] = sci_reg_invalid,
239− [SCCKS] = sci_reg_invalid,
219+ .regs = {
220+ [SCSMR] = { 0x00, 16 },
221+ [SCBRR] = { 0x04, 8 },
222+ [SCSCR] = { 0x08, 16 },
223+ [SCxTDR] = { 0x20, 8 },
224+ [SCxSR] = { 0x14, 16 },
225+ [SCxRDR] = { 0x24, 8 },
226+ [SCFCR] = { 0x18, 16 },
227+ [SCFDR] = { 0x1c, 16 },
228+ [SCPCR] = { 0x30, 16 },
229+ [SCPDR] = { 0x34, 16 },
230+ },
231+ .fifosize = 64,
232+ .overrun_reg = SCxSR,
233+ .overrun_mask = SCIFA_ORER,
234+ .sampling_rate_mask = SCI_SR_SCIFAB,
235+ .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
236+ .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
240237 },
241238
242239 /*
243240 * Common SCIFB definitions.
244241 */
245242 [SCIx_SCIFB_REGTYPE] = {
246− [SCSMR] = { 0x00, 16 },
247− [SCBRR] = { 0x04, 8 },
248− [SCSCR] = { 0x08, 16 },
249− [SCxTDR] = { 0x40, 8 },
250− [SCxSR] = { 0x14, 16 },
251− [SCxRDR] = { 0x60, 8 },
252− [SCFCR] = { 0x18, 16 },
253− [SCFDR] = sci_reg_invalid,
254− [SCTFDR] = { 0x38, 16 },
255− [SCRFDR] = { 0x3c, 16 },
256− [SCSPTR] = sci_reg_invalid,
257− [SCLSR] = sci_reg_invalid,
258− [HSSRR] = sci_reg_invalid,
259− [SCPCR] = { 0x30, 16 },
260− [SCPDR] = { 0x34, 16 },
261− [SCDL] = sci_reg_invalid,
262− [SCCKS] = sci_reg_invalid,
243+ .regs = {
244+ [SCSMR] = { 0x00, 16 },
245+ [SCBRR] = { 0x04, 8 },
246+ [SCSCR] = { 0x08, 16 },
247+ [SCxTDR] = { 0x40, 8 },
248+ [SCxSR] = { 0x14, 16 },
249+ [SCxRDR] = { 0x60, 8 },
250+ [SCFCR] = { 0x18, 16 },
251+ [SCTFDR] = { 0x38, 16 },
252+ [SCRFDR] = { 0x3c, 16 },
253+ [SCPCR] = { 0x30, 16 },
254+ [SCPDR] = { 0x34, 16 },
255+ },
256+ .fifosize = 256,
257+ .overrun_reg = SCxSR,
258+ .overrun_mask = SCIFA_ORER,
259+ .sampling_rate_mask = SCI_SR_SCIFAB,
260+ .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
261+ .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
263262 },
264263
265264 /*
@@ -267,69 +266,70 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { · 1 unmodified line
267266 * count registers.
268267 */
269268 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
270− [SCSMR] = { 0x00, 16 },
271− [SCBRR] = { 0x04, 8 },
272− [SCSCR] = { 0x08, 16 },
273− [SCxTDR] = { 0x0c, 8 },
274− [SCxSR] = { 0x10, 16 },
275− [SCxRDR] = { 0x14, 8 },
276− [SCFCR] = { 0x18, 16 },
277− [SCFDR] = { 0x1c, 16 },
278− [SCTFDR] = sci_reg_invalid,
279− [SCRFDR] = sci_reg_invalid,
280− [SCSPTR] = { 0x20, 16 },
281− [SCLSR] = { 0x24, 16 },
282− [HSSRR] = sci_reg_invalid,
283− [SCPCR] = sci_reg_invalid,
284− [SCPDR] = sci_reg_invalid,
285− [SCDL] = sci_reg_invalid,
286− [SCCKS] = sci_reg_invalid,
269+ .regs = {
270+ [SCSMR] = { 0x00, 16 },
271+ [SCBRR] = { 0x04, 8 },
272+ [SCSCR] = { 0x08, 16 },
273+ [SCxTDR] = { 0x0c, 8 },
274+ [SCxSR] = { 0x10, 16 },
275+ [SCxRDR] = { 0x14, 8 },
276+ [SCFCR] = { 0x18, 16 },
277+ [SCFDR] = { 0x1c, 16 },
278+ [SCSPTR] = { 0x20, 16 },
279+ [SCLSR] = { 0x24, 16 },
280+ },
281+ .fifosize = 16,
282+ .overrun_reg = SCLSR,
283+ .overrun_mask = SCLSR_ORER,
284+ .sampling_rate_mask = SCI_SR(32),
285+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
286+ .error_clear = SCIF_ERROR_CLEAR,
287287 },
288288
289289 /*
290290 * Common SH-3 SCIF definitions.
291291 */
292292 [SCIx_SH3_SCIF_REGTYPE] = {
293− [SCSMR] = { 0x00, 8 },
294− [SCBRR] = { 0x02, 8 },
295− [SCSCR] = { 0x04, 8 },
296− [SCxTDR] = { 0x06, 8 },
297− [SCxSR] = { 0x08, 16 },
298− [SCxRDR] = { 0x0a, 8 },
299− [SCFCR] = { 0x0c, 8 },
300− [SCFDR] = { 0x0e, 16 },
301− [SCTFDR] = sci_reg_invalid,
302− [SCRFDR] = sci_reg_invalid,
303− [SCSPTR] = sci_reg_invalid,
304− [SCLSR] = sci_reg_invalid,
305− [HSSRR] = sci_reg_invalid,
306− [SCPCR] = sci_reg_invalid,
307− [SCPDR] = sci_reg_invalid,
308− [SCDL] = sci_reg_invalid,
309− [SCCKS] = sci_reg_invalid,
293+ .regs = {
294+ [SCSMR] = { 0x00, 8 },
295+ [SCBRR] = { 0x02, 8 },
296+ [SCSCR] = { 0x04, 8 },
297+ [SCxTDR] = { 0x06, 8 },
298+ [SCxSR] = { 0x08, 16 },
299+ [SCxRDR] = { 0x0a, 8 },
300+ [SCFCR] = { 0x0c, 8 },
301+ [SCFDR] = { 0x0e, 16 },
302+ },
303+ .fifosize = 16,
304+ .overrun_reg = SCLSR,
305+ .overrun_mask = SCLSR_ORER,
306+ .sampling_rate_mask = SCI_SR(32),
307+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
308+ .error_clear = SCIF_ERROR_CLEAR,
310309 },
311310
312311 /*
313312 * Common SH-4(A) SCIF(B) definitions.
314313 */
315314 [SCIx_SH4_SCIF_REGTYPE] = {
316− [SCSMR] = { 0x00, 16 },
317− [SCBRR] = { 0x04, 8 },
318− [SCSCR] = { 0x08, 16 },
319− [SCxTDR] = { 0x0c, 8 },
320− [SCxSR] = { 0x10, 16 },
321− [SCxRDR] = { 0x14, 8 },
322− [SCFCR] = { 0x18, 16 },
323− [SCFDR] = { 0x1c, 16 },
324− [SCTFDR] = sci_reg_invalid,
325− [SCRFDR] = sci_reg_invalid,
326− [SCSPTR] = { 0x20, 16 },
327− [SCLSR] = { 0x24, 16 },
328− [HSSRR] = sci_reg_invalid,
329− [SCPCR] = sci_reg_invalid,
330− [SCPDR] = sci_reg_invalid,
331− [SCDL] = sci_reg_invalid,
332− [SCCKS] = sci_reg_invalid,
315+ .regs = {
316+ [SCSMR] = { 0x00, 16 },
317+ [SCBRR] = { 0x04, 8 },
318+ [SCSCR] = { 0x08, 16 },
319+ [SCxTDR] = { 0x0c, 8 },
320+ [SCxSR] = { 0x10, 16 },
321+ [SCxRDR] = { 0x14, 8 },
322+ [SCFCR] = { 0x18, 16 },
323+ [SCFDR] = { 0x1c, 16 },
324+ [SCSPTR] = { 0x20, 16 },
325+ [SCLSR] = { 0x24, 16 },
326+ },
327+ .fifosize = 16,
328+ .overrun_reg = SCLSR,
329+ .overrun_mask = SCLSR_ORER,
330+ .sampling_rate_mask = SCI_SR(32),
331+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
332+ .error_clear = SCIF_ERROR_CLEAR,
333333 },
334334
335335 /*
@@ -337,46 +337,55 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { · 1 unmodified line
337337 * External Clock (BRG).
338338 */
339339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
340− [SCSMR] = { 0x00, 16 },
341− [SCBRR] = { 0x04, 8 },
342− [SCSCR] = { 0x08, 16 },
343− [SCxTDR] = { 0x0c, 8 },
344− [SCxSR] = { 0x10, 16 },
345− [SCxRDR] = { 0x14, 8 },
346− [SCFCR] = { 0x18, 16 },
347− [SCFDR] = { 0x1c, 16 },
348− [SCTFDR] = sci_reg_invalid,
349− [SCRFDR] = sci_reg_invalid,
350− [SCSPTR] = { 0x20, 16 },
351− [SCLSR] = { 0x24, 16 },
352− [HSSRR] = sci_reg_invalid,
353− [SCPCR] = sci_reg_invalid,
354− [SCPDR] = sci_reg_invalid,
355− [SCDL] = { 0x30, 16 },
356− [SCCKS] = { 0x34, 16 },
340+ .regs = {
341+ [SCSMR] = { 0x00, 16 },
342+ [SCBRR] = { 0x04, 8 },
343+ [SCSCR] = { 0x08, 16 },
344+ [SCxTDR] = { 0x0c, 8 },
345+ [SCxSR] = { 0x10, 16 },
346+ [SCxRDR] = { 0x14, 8 },
347+ [SCFCR] = { 0x18, 16 },
348+ [SCFDR] = { 0x1c, 16 },
349+ [SCSPTR] = { 0x20, 16 },
350+ [SCLSR] = { 0x24, 16 },
351+ [SCDL] = { 0x30, 16 },
352+ [SCCKS] = { 0x34, 16 },
353+ },
354+ .fifosize = 16,
355+ .overrun_reg = SCLSR,
356+ .overrun_mask = SCLSR_ORER,
357+ .sampling_rate_mask = SCI_SR(32),
358+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
359+ .error_clear = SCIF_ERROR_CLEAR,
357360 },
358361
359362 /*
360363 * Common HSCIF definitions.
361364 */
362365 [SCIx_HSCIF_REGTYPE] = {
363− [SCSMR] = { 0x00, 16 },
364− [SCBRR] = { 0x04, 8 },
365− [SCSCR] = { 0x08, 16 },
366− [SCxTDR] = { 0x0c, 8 },
367− [SCxSR] = { 0x10, 16 },
368− [SCxRDR] = { 0x14, 8 },
369− [SCFCR] = { 0x18, 16 },
370− [SCFDR] = { 0x1c, 16 },
371− [SCTFDR] = sci_reg_invalid,
372− [SCRFDR] = sci_reg_invalid,
373− [SCSPTR] = { 0x20, 16 },
374− [SCLSR] = { 0x24, 16 },
375− [HSSRR] = { 0x40, 16 },
376− [SCPCR] = sci_reg_invalid,
377− [SCPDR] = sci_reg_invalid,
378− [SCDL] = { 0x30, 16 },
379− [SCCKS] = { 0x34, 16 },
366+ .regs = {
367+ [SCSMR] = { 0x00, 16 },
368+ [SCBRR] = { 0x04, 8 },
369+ [SCSCR] = { 0x08, 16 },
370+ [SCxTDR] = { 0x0c, 8 },
371+ [SCxSR] = { 0x10, 16 },
372+ [SCxRDR] = { 0x14, 8 },
373+ [SCFCR] = { 0x18, 16 },
374+ [SCFDR] = { 0x1c, 16 },
375+ [SCSPTR] = { 0x20, 16 },
376+ [SCLSR] = { 0x24, 16 },
377+ [HSSRR] = { 0x40, 16 },
378+ [SCDL] = { 0x30, 16 },
379+ [SCCKS] = { 0x34, 16 },
380+ [HSRTRGR] = { 0x54, 16 },
381+ [HSTTRGR] = { 0x58, 16 },
382+ },
383+ .fifosize = 128,
384+ .overrun_reg = SCLSR,
385+ .overrun_mask = SCLSR_ORER,
386+ .sampling_rate_mask = SCI_SR_RANGE(8, 32),
387+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
388+ .error_clear = SCIF_ERROR_CLEAR,
380389 },
381390
382391 /*
@@ -384,23 +393,23 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { · 1 unmodified line
384393 * register.
385394 */
386395 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
387− [SCSMR] = { 0x00, 16 },
388− [SCBRR] = { 0x04, 8 },
389− [SCSCR] = { 0x08, 16 },
390− [SCxTDR] = { 0x0c, 8 },
391− [SCxSR] = { 0x10, 16 },
392− [SCxRDR] = { 0x14, 8 },
393− [SCFCR] = { 0x18, 16 },
394− [SCFDR] = { 0x1c, 16 },
395− [SCTFDR] = sci_reg_invalid,
396− [SCRFDR] = sci_reg_invalid,
397− [SCSPTR] = sci_reg_invalid,
398− [SCLSR] = { 0x24, 16 },
399− [HSSRR] = sci_reg_invalid,
400− [SCPCR] = sci_reg_invalid,
401− [SCPDR] = sci_reg_invalid,
402− [SCDL] = sci_reg_invalid,
403− [SCCKS] = sci_reg_invalid,
396+ .regs = {
397+ [SCSMR] = { 0x00, 16 },
398+ [SCBRR] = { 0x04, 8 },
399+ [SCSCR] = { 0x08, 16 },
400+ [SCxTDR] = { 0x0c, 8 },
401+ [SCxSR] = { 0x10, 16 },
402+ [SCxRDR] = { 0x14, 8 },
403+ [SCFCR] = { 0x18, 16 },
404+ [SCFDR] = { 0x1c, 16 },
405+ [SCLSR] = { 0x24, 16 },
406+ },
407+ .fifosize = 16,
408+ .overrun_reg = SCLSR,
409+ .overrun_mask = SCLSR_ORER,
410+ .sampling_rate_mask = SCI_SR(32),
411+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
412+ .error_clear = SCIF_ERROR_CLEAR,
404413 },
405414
406415 /*
@@ -408,23 +417,26 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { · 1 unmodified line
408417 * count registers.
409418 */
410419 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
411− [SCSMR] = { 0x00, 16 },
412− [SCBRR] = { 0x04, 8 },
413− [SCSCR] = { 0x08, 16 },
414− [SCxTDR] = { 0x0c, 8 },
415− [SCxSR] = { 0x10, 16 },
416− [SCxRDR] = { 0x14, 8 },
417− [SCFCR] = { 0x18, 16 },
418− [SCFDR] = { 0x1c, 16 },
419− [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
420− [SCRFDR] = { 0x20, 16 },
421− [SCSPTR] = { 0x24, 16 },
422− [SCLSR] = { 0x28, 16 },
423− [HSSRR] = sci_reg_invalid,
424− [SCPCR] = sci_reg_invalid,
425− [SCPDR] = sci_reg_invalid,
426− [SCDL] = sci_reg_invalid,
427− [SCCKS] = sci_reg_invalid,
420+ .regs = {
421+ [SCSMR] = { 0x00, 16 },
422+ [SCBRR] = { 0x04, 8 },
423+ [SCSCR] = { 0x08, 16 },
424+ [SCxTDR] = { 0x0c, 8 },
425+ [SCxSR] = { 0x10, 16 },
426+ [SCxRDR] = { 0x14, 8 },
427+ [SCFCR] = { 0x18, 16 },
428+ [SCFDR] = { 0x1c, 16 },
429+ [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
430+ [SCRFDR] = { 0x20, 16 },
431+ [SCSPTR] = { 0x24, 16 },
432+ [SCLSR] = { 0x28, 16 },
433+ },
434+ .fifosize = 16,
435+ .overrun_reg = SCLSR,
436+ .overrun_mask = SCLSR_ORER,
437+ .sampling_rate_mask = SCI_SR(32),
438+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
439+ .error_clear = SCIF_ERROR_CLEAR,
428440 },
429441
430442 /*
@@ -432,27 +444,26 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { · 1 unmodified line
432444 * registers.
433445 */
434446 [SCIx_SH7705_SCIF_REGTYPE] = {
435− [SCSMR] = { 0x00, 16 },
436− [SCBRR] = { 0x04, 8 },
437− [SCSCR] = { 0x08, 16 },
438− [SCxTDR] = { 0x20, 8 },
439− [SCxSR] = { 0x14, 16 },
440− [SCxRDR] = { 0x24, 8 },
441− [SCFCR] = { 0x18, 16 },
442− [SCFDR] = { 0x1c, 16 },
443− [SCTFDR] = sci_reg_invalid,
444− [SCRFDR] = sci_reg_invalid,
445− [SCSPTR] = sci_reg_invalid,
446− [SCLSR] = sci_reg_invalid,
447− [HSSRR] = sci_reg_invalid,
448− [SCPCR] = sci_reg_invalid,
449− [SCPDR] = sci_reg_invalid,
450− [SCDL] = sci_reg_invalid,
451− [SCCKS] = sci_reg_invalid,
447+ .regs = {
448+ [SCSMR] = { 0x00, 16 },
449+ [SCBRR] = { 0x04, 8 },
450+ [SCSCR] = { 0x08, 16 },
451+ [SCxTDR] = { 0x20, 8 },
452+ [SCxSR] = { 0x14, 16 },
453+ [SCxRDR] = { 0x24, 8 },
454+ [SCFCR] = { 0x18, 16 },
455+ [SCFDR] = { 0x1c, 16 },
456+ },
457+ .fifosize = 64,
458+ .overrun_reg = SCxSR,
459+ .overrun_mask = SCIFA_ORER,
460+ .sampling_rate_mask = SCI_SR(16),
461+ .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
462+ .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
452463 },
453464 };
454465
455−#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
466+#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
456467
457468 /*
458469 * The "offset" here is rather misleading, in that it refers to an enum
@@ -486,41 +497,6 @@ static void sci_serial_out(struct uart_port *p, int offset, int value) · 27 unmodified lines
486497 WARN(1, "Invalid register access\n");
487498 }
488499
489−static int sci_probe_regmap(struct plat_sci_port *cfg)
490−{
491− switch (cfg->type) {
492− case PORT_SCI:
493− cfg->regtype = SCIx_SCI_REGTYPE;
494− break;
495− case PORT_IRDA:
496− cfg->regtype = SCIx_IRDA_REGTYPE;
497− break;
498− case PORT_SCIFA:
499− cfg->regtype = SCIx_SCIFA_REGTYPE;
500− break;
501− case PORT_SCIFB:
502− cfg->regtype = SCIx_SCIFB_REGTYPE;
503− break;
504− case PORT_SCIF:
505− /*
506− * The SH-4 is a bit of a misnomer here, although that's
507− * where this particular port layout originated. This
508− * configuration (or some slight variation thereof)
509− * remains the dominant model for all SCIFs.
510− */
511− cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
512− break;
513− case PORT_HSCIF:
514− cfg->regtype = SCIx_HSCIF_REGTYPE;
515− break;
516− default:
517− pr_err("Can't probe register map for given port\n");
518− return -EINVAL;
519− }
520−
521− return 0;
522−}
523−
524500 static void sci_port_enable(struct sci_port *sci_port)
525501 {
526502 unsigned int i;
@@ -544,14 +520,6 @@ static void sci_port_disable(struct sci_port *sci_port) · 17 unmodified lines
544520 if (!sci_port->port.dev)
545521 return;
546522
547− /* Cancel the break timer to ensure that the timer handler will not try
548− * to access the hardware with clocks and power disabled. Reset the
549− * break flag to make the break debouncing state machine ready for the
550− * next break.
551− */
552− del_timer_sync(&sci_port->break_timer);
553− sci_port->break_flag = 0;
554−
555523 for (i = SCI_NUM_CLKS; i-- > 0; )
556524 clk_disable_unprepare(sci_port->clks[i]);
557525
@@ -646,7 +614,7 @@ static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) · 88 unmodified lines
646614 if (port->type == PORT_SCI) {
647615 /* Just store the mask */
648616 serial_port_out(port, SCxSR, mask);
649− } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
617+ } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
650618 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651619 /* Only clear the status bits we want to clear */
652620 serial_port_out(port, SCxSR,
@@ -719,7 +687,7 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag) · 66 unmodified lines
719687
720688 /* Enable RXD and TXD pin functions */
721689 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
722− if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
690+ if (to_sci_port(port)->has_rtscts) {
723691 /* RTS# is output, driven 1 */
724692 ctrl |= SCPCR_RTSC;
725693 serial_port_out(port, SCPDR,
@@ -741,11 +709,13 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag) · 15 unmodified lines
741709
742710 static int sci_txfill(struct uart_port *port)
743711 {
712+ struct sci_port *s = to_sci_port(port);
713+ unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
744714 const struct plat_sci_reg *reg;
745715
746716 reg = sci_getreg(port, SCTFDR);
747717 if (reg->size)
748− return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
718+ return serial_port_in(port, SCTFDR) & fifo_mask;
749719
750720 reg = sci_getreg(port, SCFDR);
751721 if (reg->size)
@@ -761,33 +731,21 @@ static int sci_txroom(struct uart_port *port) · 9 unmodified lines
761731
762732 static int sci_rxfill(struct uart_port *port)
763733 {
734+ struct sci_port *s = to_sci_port(port);
735+ unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
764736 const struct plat_sci_reg *reg;
765737
766738 reg = sci_getreg(port, SCRFDR);
767739 if (reg->size)
768− return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
740+ return serial_port_in(port, SCRFDR) & fifo_mask;
769741
770742 reg = sci_getreg(port, SCFDR);
771743 if (reg->size)
772− return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
744+ return serial_port_in(port, SCFDR) & fifo_mask;
773745
774746 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
775747 }
776748
777−/*
778− * SCI helper for checking the state of the muxed port/RXD pins.
779− */
780−static inline int sci_rxd_in(struct uart_port *port)
781−{
782− struct sci_port *s = to_sci_port(port);
783−
784− if (s->cfg->port_reg <= 0)
785− return 1;
786−
787− /* Cast for ARM damage */
788− return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
789−}
790−
791749 /* ********************************************************************** *
792750 * the interrupt related routines *
793751 * ********************************************************************** */
@@ -855,7 +813,6 @@ static void sci_transmit_chars(struct uart_port *port) · 61 unmodified lines
855813
856814 static void sci_receive_chars(struct uart_port *port)
857815 {
858− struct sci_port *sci_port = to_sci_port(port);
859816 struct tty_port *tport = &port->state->port;
860817 int i, count, copied = 0;
861818 unsigned short status;
@@ -875,8 +832,7 @@ static void sci_receive_chars(struct uart_port *port) · 13 unmodified lines
875832
876833 if (port->type == PORT_SCI) {
877834 char c = serial_port_in(port, SCxRDR);
878− if (uart_handle_sysrq_char(port, c) ||
879− sci_port->break_flag)
835+ if (uart_handle_sysrq_char(port, c))
880836 count = 0;
881837 else
882838 tty_insert_flip_char(tport, c, TTY_NORMAL);
@@ -885,25 +841,6 @@ static void sci_receive_chars(struct uart_port *port) · 2 unmodified lines
885841 char c = serial_port_in(port, SCxRDR);
886842
887843 status = serial_port_in(port, SCxSR);
888−#if defined(CONFIG_CPU_SH3)
889− /* Skip "chars" during break */
890− if (sci_port->break_flag) {
891− if ((c == 0) &&
892− (status & SCxSR_FER(port))) {
893− count--; i--;
894− continue;
895− }
896−
897− /* Nonzero => end-of-break */
898− dev_dbg(port->dev, "debounce<%02x>\n", c);
899− sci_port->break_flag = 0;
900−
901− if (STEPFN(c)) {
902− count--; i--;
903− continue;
904− }
905− }
906−#endif /* CONFIG_CPU_SH3 */
907844 if (uart_handle_sysrq_char(port, c)) {
908845 count--; i--;
909846 continue;
@@ -941,37 +878,6 @@ static void sci_receive_chars(struct uart_port *port) · 31 unmodified lines
941878 }
942879 }
943880
944−#define SCI_BREAK_JIFFIES (HZ/20)
945−
946−/*
947− * The sci generates interrupts during the break,
948− * 1 per millisecond or so during the break period, for 9600 baud.
949− * So dont bother disabling interrupts.
950− * But dont want more than 1 break event.
951− * Use a kernel timer to periodically poll the rx line until
952− * the break is finished.
953− */
954−static inline void sci_schedule_break_timer(struct sci_port *port)
955−{
956− mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
957−}
958−
959−/* Ensure that two consecutive samples find the break over. */
960−static void sci_break_timer(unsigned long data)
961−{
962− struct sci_port *port = (struct sci_port *)data;
963−
964− if (sci_rxd_in(&port->port) == 0) {
965− port->break_flag = 1;
966− sci_schedule_break_timer(port);
967− } else if (port->break_flag == 1) {
968− /* break is over. */
969− port->break_flag = 2;
970− sci_schedule_break_timer(port);
971− } else
972− port->break_flag = 0;
973−}
974−
975881 static int sci_handle_errors(struct uart_port *port)
976882 {
977883 int copied = 0;
@@ -980,7 +886,7 @@ static int sci_handle_errors(struct uart_port *port) · 2 unmodified lines
980886 struct sci_port *s = to_sci_port(port);
981887
982888 /* Handle overruns */
983− if (status & s->overrun_mask) {
889+ if (status & s->params->overrun_mask) {
984890 port->icount.overrun++;
985891
986892 /* overrun error */
@@ -991,35 +897,13 @@ static int sci_handle_errors(struct uart_port *port) · 4 unmodified lines
991897 }
992898
993899 if (status & SCxSR_FER(port)) {
994− if (sci_rxd_in(port) == 0) {
995− /* Notify of BREAK */
996− struct sci_port *sci_port = to_sci_port(port);
997−
998− if (!sci_port->break_flag) {
999− port->icount.brk++;
1000−
1001− sci_port->break_flag = 1;
1002− sci_schedule_break_timer(sci_port);
900+ /* frame error */
901+ port->icount.frame++;
1003902
1004− /* Do sysrq handling. */
1005− if (uart_handle_break(port))
1006− return 0;
1007−
1008− dev_dbg(port->dev, "BREAK detected\n");
1009−
1010− if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1011− copied++;
1012− }
1013−
1014− } else {
1015− /* frame error */
1016− port->icount.frame++;
1017−
1018− if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1019− copied++;
903+ if (tty_insert_flip_char(tport, 0, TTY_FRAME))
904+ copied++;
1020905
1021− dev_notice(port->dev, "frame error\n");
1022− }
906+ dev_notice(port->dev, "frame error\n");
1023907 }
1024908
1025909 if (status & SCxSR_PER(port)) {
@@ -1046,14 +930,14 @@ static int sci_handle_fifo_overrun(struct uart_port *port) · 20 unmodified lines
1046930 int copied = 0;
1047931 u16 status;
1048932
1049− reg = sci_getreg(port, s->overrun_reg);
933+ reg = sci_getreg(port, s->params->overrun_reg);
1050934 if (!reg->size)
1051935 return 0;
1052936
1053− status = serial_port_in(port, s->overrun_reg);
1054− if (status & s->overrun_mask) {
1055− status &= ~s->overrun_mask;
1056− serial_port_out(port, s->overrun_reg, status);
937+ status = serial_port_in(port, s->params->overrun_reg);
938+ if (status & s->params->overrun_mask) {
939+ status &= ~s->params->overrun_mask;
940+ serial_port_out(port, s->params->overrun_reg, status);
1057941
1058942 port->icount.overrun++;
1059943
@@ -1072,17 +956,11 @@ static int sci_handle_breaks(struct uart_port *port) · 12 unmodified lines
1072956 int copied = 0;
1073957 unsigned short status = serial_port_in(port, SCxSR);
1074958 struct tty_port *tport = &port->state->port;
1075− struct sci_port *s = to_sci_port(port);
1076959
1077960 if (uart_handle_break(port))
1078961 return 0;
1079962
1080− if (!s->break_flag && status & SCxSR_BRK(port)) {
1081−#if defined(CONFIG_CPU_SH3)
1082− /* Debounce break */
1083− s->break_flag = 1;
1084−#endif
1085−
963+ if (status & SCxSR_BRK(port)) {
1086964 port->icount.brk++;
1087965
1088966 /* Notify of BREAK */
@@ -1100,6 +978,146 @@ static int sci_handle_breaks(struct uart_port *port) · 11 unmodified lines
1100978 return copied;
1101979 }
1102980
981+static int scif_set_rtrg(struct uart_port *port, int rx_trig)
982+{
983+ unsigned int bits;
984+
985+ if (rx_trig < 1)
986+ rx_trig = 1;
987+ if (rx_trig >= port->fifosize)
988+ rx_trig = port->fifosize;
989+
990+ /* HSCIF can be set to an arbitrary level. */
991+ if (sci_getreg(port, HSRTRGR)->size) {
992+ serial_port_out(port, HSRTRGR, rx_trig);
993+ return rx_trig;
994+ }
995+
996+ switch (port->type) {
997+ case PORT_SCIF:
998+ if (rx_trig < 4) {
999+ bits = 0;
1000+ rx_trig = 1;
1001+ } else if (rx_trig < 8) {
1002+ bits = SCFCR_RTRG0;
1003+ rx_trig = 4;
1004+ } else if (rx_trig < 14) {
1005+ bits = SCFCR_RTRG1;
1006+ rx_trig = 8;
1007+ } else {
1008+ bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1009+ rx_trig = 14;
1010+ }
1011+ break;
1012+ case PORT_SCIFA:
1013+ case PORT_SCIFB:
1014+ if (rx_trig < 16) {
1015+ bits = 0;
1016+ rx_trig = 1;
1017+ } else if (rx_trig < 32) {
1018+ bits = SCFCR_RTRG0;
1019+ rx_trig = 16;
1020+ } else if (rx_trig < 48) {
1021+ bits = SCFCR_RTRG1;
1022+ rx_trig = 32;
1023+ } else {
1024+ bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1025+ rx_trig = 48;
1026+ }
1027+ break;
1028+ default:
1029+ WARN(1, "unknown FIFO configuration");
1030+ return 1;
1031+ }
1032+
1033+ serial_port_out(port, SCFCR,
1034+ (serial_port_in(port, SCFCR) &
1035+ ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1036+
1037+ return rx_trig;
1038+}
1039+
1040+static int scif_rtrg_enabled(struct uart_port *port)
1041+{
1042+ if (sci_getreg(port, HSRTRGR)->size)
1043+ return serial_port_in(port, HSRTRGR) != 0;
1044+ else
1045+ return (serial_port_in(port, SCFCR) &
1046+ (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1047+}
1048+
1049+static void rx_fifo_timer_fn(unsigned long arg)
1050+{
1051+ struct sci_port *s = (struct sci_port *)arg;
1052+ struct uart_port *port = &s->port;
1053+
1054+ dev_dbg(port->dev, "Rx timed out\n");
1055+ scif_set_rtrg(port, 1);
1056+}
1057+
1058+static ssize_t rx_trigger_show(struct device *dev,
1059+ struct device_attribute *attr,
1060+ char *buf)
1061+{
1062+ struct uart_port *port = dev_get_drvdata(dev);
1063+ struct sci_port *sci = to_sci_port(port);
1064+
1065+ return sprintf(buf, "%d\n", sci->rx_trigger);
1066+}
1067+
1068+static ssize_t rx_trigger_store(struct device *dev,
1069+ struct device_attribute *attr,
1070+ const char *buf,
1071+ size_t count)
1072+{
1073+ struct uart_port *port = dev_get_drvdata(dev);
1074+ struct sci_port *sci = to_sci_port(port);
1075+ long r;
1076+
1077+ if (kstrtol(buf, 0, &r) == -EINVAL)
1078+ return -EINVAL;
1079+
1080+ sci->rx_trigger = scif_set_rtrg(port, r);
1081+ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1082+ scif_set_rtrg(port, 1);
1083+
1084+ return count;
1085+}
1086+
1087+static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1088+
1089+static ssize_t rx_fifo_timeout_show(struct device *dev,
1090+ struct device_attribute *attr,
1091+ char *buf)
1092+{
1093+ struct uart_port *port = dev_get_drvdata(dev);
1094+ struct sci_port *sci = to_sci_port(port);
1095+
1096+ return sprintf(buf, "%d\n", sci->rx_fifo_timeout);
1097+}
1098+
1099+static ssize_t rx_fifo_timeout_store(struct device *dev,
1100+ struct device_attribute *attr,
1101+ const char *buf,
1102+ size_t count)
1103+{
1104+ struct uart_port *port = dev_get_drvdata(dev);
1105+ struct sci_port *sci = to_sci_port(port);
1106+ long r;
1107+
1108+ if (kstrtol(buf, 0, &r) == -EINVAL)
1109+ return -EINVAL;
1110+ sci->rx_fifo_timeout = r;
1111+ scif_set_rtrg(port, 1);
1112+ if (r > 0)
1113+ setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
1114+ (unsigned long)sci);
1115+ return count;
1116+}
1117+
1118+static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
1119+
1120+
11031121 #ifdef CONFIG_SERIAL_SH_SCI_DMA
11041122 static void sci_dma_tx_complete(void *arg)
11051123 {
@@ -1410,20 +1428,14 @@ static void rx_timer_fn(unsigned long arg) · 304 unmodified lines
14101428 }
14111429
14121430 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1413− enum dma_transfer_direction dir,
1414− unsigned int id)
1431+ enum dma_transfer_direction dir)
14151432 {
1416− dma_cap_mask_t mask;
14171433 struct dma_chan *chan;
14181434 struct dma_slave_config cfg;
14191435 int ret;
14201436
1421− dma_cap_zero(mask);
1422− dma_cap_set(DMA_SLAVE, mask);
1423−
1424− chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1425− (void *)(unsigned long)id, port->dev,
1426− dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1437+ chan = dma_request_slave_channel(port->dev,
1438+ dir == DMA_MEM_TO_DEV ? "tx" : "rx");
14271439 if (!chan) {
14281440 dev_warn(port->dev,
14291441 "dma_request_slave_channel_compat failed\n");
@@ -1459,12 +1471,11 @@ static void sci_request_dma(struct uart_port *port) · 29 unmodified lines
14591471
14601472 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
14611473
1462− if (!port->dev->of_node &&
1463− (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1474+ if (!port->dev->of_node)
14641475 return;
14651476
14661477 s->cookie_tx = -EINVAL;
1467− chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1478+ chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
14681479 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
14691480 if (chan) {
14701481 s->chan_tx = chan;
@@ -1486,7 +1497,7 @@ static void sci_request_dma(struct uart_port *port) · 15 unmodified lines
14861497 INIT_WORK(&s->work_tx, work_fn_tx);
14871498 }
14881499
1489− chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1500+ chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
14901501 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
14911502 if (chan) {
14921503 unsigned int i;
@@ -1546,10 +1557,10 @@ static inline void sci_free_dma(struct uart_port *port) · 53 unmodified lines
15461557
15471558 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
15481559 {
1549−#ifdef CONFIG_SERIAL_SH_SCI_DMA
15501560 struct uart_port *port = ptr;
15511561 struct sci_port *s = to_sci_port(port);
15521562
1563+#ifdef CONFIG_SERIAL_SH_SCI_DMA
15531564 if (s->chan_rx) {
15541565 u16 scr = serial_port_in(port, SCSCR);
15551566 u16 ssr = serial_port_in(port, SCxSR);
@@ -1574,6 +1585,14 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) · 18 unmodified lines
15741585 }
15751586 #endif
15761587
1588+ if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1589+ if (!scif_rtrg_enabled(port))
1590+ scif_set_rtrg(port, s->rx_trigger);
1591+
1592+ mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1593+ s->rx_frame * s->rx_fifo_timeout, 1000));
1594+ }
1595+
15771596 /* I think sci_receive_chars has to be called irrespective
15781597 * of whether the I_IXOFF is set, otherwise, how is the interrupt
15791598 * to be disabled?
@@ -1642,12 +1661,10 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) · 62 unmodified lines
16421661
16431662 ssr_status = serial_port_in(port, SCxSR);
16441663 scr_status = serial_port_in(port, SCSCR);
1645− if (s->overrun_reg == SCxSR)
1664+ if (s->params->overrun_reg == SCxSR)
16461665 orer_status = ssr_status;
1647− else {
1648− if (sci_getreg(port, s->overrun_reg)->size)
1649− orer_status = serial_port_in(port, s->overrun_reg);
1650− }
1666+ else if (sci_getreg(port, s->params->overrun_reg)->size)
1667+ orer_status = serial_port_in(port, s->params->overrun_reg);
16511668
16521669 err_enabled = scr_status & port_rx_irq_mask(port);
16531670
@@ -1673,7 +1690,7 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) · 19 unmodified lines
16731690 ret = sci_br_interrupt(irq, ptr);
16741691
16751692 /* Overrun Interrupt */
1676− if (orer_status & s->overrun_mask) {
1693+ if (orer_status & s->params->overrun_mask) {
16771694 sci_handle_fifo_overrun(port);
16781695 ret = IRQ_HANDLED;
16791696 }
@@ -1743,8 +1760,10 @@ static int sci_request_irq(struct sci_port *port) · 63 unmodified lines
17431760 desc = sci_irq_desc + i;
17441761 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
17451762 dev_name(up->dev), desc->desc);
1746− if (!port->irqstr[j])
1763+ if (!port->irqstr[j]) {
1764+ ret = -ENOMEM;
17471765 goto out_nomem;
1766+ }
17481767
17491768 ret = request_irq(irq, desc->handler, up->irqflags,
17501769 port->irqstr[j], port);
@@ -1874,7 +1893,7 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) · 123 unmodified lines
18741893
18751894 mctrl_gpio_set(s->gpios, mctrl);
18761895
1877− if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
1896+ if (!s->has_rtscts)
18781897 return;
18791898
18801899 if (!(mctrl & TIOCM_RTS)) {
@@ -2136,6 +2155,7 @@ static void sci_reset(struct uart_port *port) · 255 unmodified lines
21362155 {
21372156 const struct plat_sci_reg *reg;
21382157 unsigned int status;
2158+ struct sci_port *s = to_sci_port(port);
21392159
21402160 do {
21412161 status = serial_port_in(port, SCxSR);
@@ -2155,12 +2175,26 @@ static void sci_reset(struct uart_port *port) · 13 unmodified lines
21552175 status &= ~(SCLSR_TO | SCLSR_ORER);
21562176 serial_port_out(port, SCLSR, status);
21572177 }
2178+
2179+ if (s->rx_trigger > 1) {
2180+ if (s->rx_fifo_timeout) {
2181+ scif_set_rtrg(port, 1);
2182+ setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
2183+ (unsigned long)s);
2184+ } else {
2185+ if (port->type == PORT_SCIFA ||
2186+ port->type == PORT_SCIFB)
2187+ scif_set_rtrg(port, 1);
2188+ else
2189+ scif_set_rtrg(port, s->rx_trigger);
2190+ }
2191+ }
21582192 }
21592193
21602194 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
21612195 struct ktermios *old)
21622196 {
2163− unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2197+ unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
21642198 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
21652199 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
21662200 struct sci_port *s = to_sci_port(port);
@@ -2341,7 +2375,8 @@ done: · 174 unmodified lines
23412375 serial_port_out(port, SCFCR, ctrl);
23422376 }
23432377
2344− scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2378+ scr_val |= SCSCR_RE | SCSCR_TE |
2379+ (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
23452380 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
23462381 serial_port_out(port, SCSCR, scr_val);
23472382 if ((srr + 1 == 5) &&
@@ -2355,7 +2390,6 @@ done: · 7 unmodified lines
23552390 udelay(DIV_ROUND_UP(10 * 1000000, baud));
23562391 }
23572392
2358−#ifdef CONFIG_SERIAL_SH_SCI_DMA
23592393 /*
23602394 * Calculate delay for 2 DMA buffers (4 FIFO).
23612395 * See serial_core.c::uart_update_timeout().
@@ -2366,36 +2400,34 @@ done: · 4 unmodified lines
23662400 * value obtained by this formula is too small. Therefore, if the value
23672401 * is smaller than 20ms, use 20ms as the timeout value for DMA.
23682402 */
2369− if (s->chan_rx) {
2370− unsigned int bits;
2403+ /* byte size and parity */
2404+ switch (termios->c_cflag & CSIZE) {
2405+ case CS5:
2406+ bits = 7;
2407+ break;
2408+ case CS6:
2409+ bits = 8;
2410+ break;
2411+ case CS7:
2412+ bits = 9;
2413+ break;
2414+ default:
2415+ bits = 10;
2416+ break;
2417+ }
23712418
2372− /* byte size and parity */
2373− switch (termios->c_cflag & CSIZE) {
2374− case CS5:
2375− bits = 7;
2376− break;
2377− case CS6:
2378− bits = 8;
2379− break;
2380− case CS7:
2381− bits = 9;
2382− break;
2383− default:
2384− bits = 10;
2385− break;
2386− }
2419+ if (termios->c_cflag & CSTOPB)
2420+ bits++;
2421+ if (termios->c_cflag & PARENB)
2422+ bits++;
23872423
2388− if (termios->c_cflag & CSTOPB)
2389− bits++;
2390− if (termios->c_cflag & PARENB)
2391− bits++;
2392− s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2393− (baud / 10), 10);
2394− dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2395− s->rx_timeout * 1000 / HZ, port->timeout);
2396− if (s->rx_timeout < msecs_to_jiffies(20))
2397− s->rx_timeout = msecs_to_jiffies(20);
2398− }
2424+ s->rx_frame = (100 * bits * HZ) / (baud / 10);
2425+#ifdef CONFIG_SERIAL_SH_SCI_DMA
2426+ s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
2427+ dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2428+ s->rx_timeout * 1000 / HZ, port->timeout);
2429+ if (s->rx_timeout < msecs_to_jiffies(20))
2430+ s->rx_timeout = msecs_to_jiffies(20);
23992431 #endif
24002432
24012433 if ((termios->c_cflag & CREAD) != 0)
@@ -2452,7 +2484,7 @@ static int sci_remap_port(struct uart_port *port) · 50 unmodified lines
24522484 if (port->membase)
24532485 return 0;
24542486
2455− if (port->flags & UPF_IOREMAP) {
2487+ if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
24562488 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
24572489 if (unlikely(!port->membase)) {
24582490 dev_err(port->dev, "can't remap port#%d\n", port->line);
@@ -2474,7 +2506,7 @@ static void sci_release_port(struct uart_port *port) · 15 unmodified lines
24742506 {
24752507 struct sci_port *sport = to_sci_port(port);
24762508
2477− if (port->flags & UPF_IOREMAP) {
2509+ if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
24782510 iounmap(port->membase);
24792511 port->membase = NULL;
24802512 }
@@ -2604,9 +2636,50 @@ found: · 123 unmodified lines
26042636 return 0;
26052637 }
26062638
2639+static const struct sci_port_params *
2640+sci_probe_regmap(const struct plat_sci_port *cfg)
2641+{
2642+ unsigned int regtype;
2643+
2644+ if (cfg->regtype != SCIx_PROBE_REGTYPE)
2645+ return &sci_port_params[cfg->regtype];
2646+
2647+ switch (cfg->type) {
2648+ case PORT_SCI:
2649+ regtype = SCIx_SCI_REGTYPE;
2650+ break;
2651+ case PORT_IRDA:
2652+ regtype = SCIx_IRDA_REGTYPE;
2653+ break;
2654+ case PORT_SCIFA:
2655+ regtype = SCIx_SCIFA_REGTYPE;
2656+ break;
2657+ case PORT_SCIFB:
2658+ regtype = SCIx_SCIFB_REGTYPE;
2659+ break;
2660+ case PORT_SCIF:
2661+ /*
2662+ * The SH-4 is a bit of a misnomer here, although that's
2663+ * where this particular port layout originated. This
2664+ * configuration (or some slight variation thereof)
2665+ * remains the dominant model for all SCIFs.
2666+ */
2667+ regtype = SCIx_SH4_SCIF_REGTYPE;
2668+ break;
2669+ case PORT_HSCIF:
2670+ regtype = SCIx_HSCIF_REGTYPE;
2671+ break;
2672+ default:
2673+ pr_err("Can't probe register map for given port\n");
2674+ return NULL;
2675+ }
2676+
2677+ return &sci_port_params[regtype];
2678+}
2679+
26072680 static int sci_init_single(struct platform_device *dev,
26082681 struct sci_port *sci_port, unsigned int index,
2609− struct plat_sci_port *p, bool early)
2682+ const struct plat_sci_port *p, bool early)
26102683 {
26112684 struct uart_port *port = &sci_port->port;
26122685 const struct resource *res;
@@ -2643,57 +2716,41 @@ static int sci_init_single(struct platform_device *dev, · 30 unmodified lines
26432716 sci_port->irqs[3] = sci_port->irqs[0];
26442717 }
26452718
2646− if (p->regtype == SCIx_PROBE_REGTYPE) {
2647− ret = sci_probe_regmap(p);
2648− if (unlikely(ret))
2649− return ret;
2650− }
2719+ sci_port->params = sci_probe_regmap(p);
2720+ if (unlikely(sci_port->params == NULL))
2721+ return -EINVAL;
26512722
26522723 switch (p->type) {
26532724 case PORT_SCIFB:
2654− port->fifosize = 256;
2655− sci_port->overrun_reg = SCxSR;
2656− sci_port->overrun_mask = SCIFA_ORER;
2657− sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2725+ sci_port->rx_trigger = 48;
26582726 break;
26592727 case PORT_HSCIF:
2660− port->fifosize = 128;
2661− sci_port->overrun_reg = SCLSR;
2662− sci_port->overrun_mask = SCLSR_ORER;
2663− sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2728+ sci_port->rx_trigger = 64;
26642729 break;
26652730 case PORT_SCIFA:
2666− port->fifosize = 64;
2667− sci_port->overrun_reg = SCxSR;
2668− sci_port->overrun_mask = SCIFA_ORER;
2669− sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2731+ sci_port->rx_trigger = 32;
26702732 break;
26712733 case PORT_SCIF:
2672− port->fifosize = 16;
2673− if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2674− sci_port->overrun_reg = SCxSR;
2675− sci_port->overrun_mask = SCIFA_ORER;
2676− sci_port->sampling_rate_mask = SCI_SR(16);
2677− } else {
2678− sci_port->overrun_reg = SCLSR;
2679− sci_port->overrun_mask = SCLSR_ORER;
2680− sci_port->sampling_rate_mask = SCI_SR(32);
2681− }
2734+ if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2735+ /* RX triggering not implemented for this IP */
2736+ sci_port->rx_trigger = 1;
2737+ else
2738+ sci_port->rx_trigger = 8;
26822739 break;
26832740 default:
2684− port->fifosize = 1;
2685− sci_port->overrun_reg = SCxSR;
2686− sci_port->overrun_mask = SCI_ORER;
2687− sci_port->sampling_rate_mask = SCI_SR(32);
2741+ sci_port->rx_trigger = 1;
26882742 break;
26892743 }
26902744
2745+ sci_port->rx_fifo_timeout = 0;
2746+
26912747 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
26922748 * match the SoC datasheet, this should be investigated. Let platform
26932749 * data override the sampling rate for now.
26942750 */
2695− if (p->sampling_rate)
2696− sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2751+ sci_port->sampling_rate_mask = p->sampling_rate
2752+ ? SCI_SR(p->sampling_rate)
2753+ : sci_port->params->sampling_rate_mask;
26972754
26982755 if (!early) {
26992756 ret = sci_init_clocks(sci_port, &dev->dev);
@@ -2705,34 +2762,17 @@ static int sci_init_single(struct platform_device *dev, · 5 unmodified lines
27052762 pm_runtime_enable(&dev->dev);
27062763 }
27072764
2708− sci_port->break_timer.data = (unsigned long)sci_port;
2709− sci_port->break_timer.function = sci_break_timer;
2710− init_timer(&sci_port->break_timer);
2711−
2712− /*
2713− * Establish some sensible defaults for the error detection.
2714− */
2715− if (p->type == PORT_SCI) {
2716− sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2717− sci_port->error_clear = SCI_ERROR_CLEAR;
2718− } else {
2719− sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2720− sci_port->error_clear = SCIF_ERROR_CLEAR;
2721− }
2765+ port->type = p->type;
2766+ port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2767+ port->fifosize = sci_port->params->fifosize;
27222768
2723− /*
2724− * Make the error mask inclusive of overrun detection, if
2725− * supported.
2726− */
2727− if (sci_port->overrun_reg == SCxSR) {
2728− sci_port->error_mask |= sci_port->overrun_mask;
2729− sci_port->error_clear &= ~sci_port->overrun_mask;
2769+ if (port->type == PORT_SCI) {
2770+ if (sci_port->reg_size >= 0x20)
2771+ port->regshift = 2;
2772+ else
2773+ port->regshift = 1;
27302774 }
27312775
2732− port->type = p->type;
2733− port->flags = UPF_FIXED_PORT | p->flags;
2734− port->regshift = p->regshift;
2735−
27362776 /*
27372777 * The UART port needs an IRQ value, so we peg this to the RX IRQ
27382778 * for the multi-IRQ ports, which is where we are primarily
@@ -2746,10 +2786,6 @@ static int sci_init_single(struct platform_device *dev, · 7 unmodified lines
27462786 port->serial_in = sci_serial_in;
27472787 port->serial_out = sci_serial_out;
27482788
2749− if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2750− dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2751− p->dma_slave_tx, p->dma_slave_rx);
2752−
27532789 return 0;
27542790 }
27552791
@@ -2791,7 +2827,8 @@ static void serial_console_write(struct console *co, const char *s, · 35 unmodified lines
27912827
27922828 /* first save SCSCR then disable interrupts, keep clock source */
27932829 ctrl = serial_port_in(port, SCSCR);
2794− ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2830+ ctrl_temp = SCSCR_RE | SCSCR_TE |
2831+ (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
27952832 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
27962833 serial_port_out(port, SCSCR, ctrl_temp);
27972834
@@ -2866,7 +2903,7 @@ static char early_serial_buf[32]; · 68 unmodified lines
28662903
28672904 static int sci_probe_earlyprintk(struct platform_device *pdev)
28682905 {
2869− struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2906+ const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
28702907
28712908 if (early_serial_console.data)
28722909 return -EEXIST;
@@ -2916,6 +2953,15 @@ static int sci_remove(struct platform_device *dev) · 43 unmodified lines
29162953
29172954 sci_cleanup_single(port);
29182955
2956+ if (port->port.fifosize > 1) {
2957+ sysfs_remove_file(&dev->dev.kobj,
2958+ &dev_attr_rx_fifo_trigger.attr);
2959+ }
2960+ if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB) {
2961+ sysfs_remove_file(&dev->dev.kobj,
2962+ &dev_attr_rx_fifo_timeout.attr);
2963+ }
2964+
29192965 return 0;
29202966 }
29212967
@@ -2963,12 +3009,13 @@ static const struct of_device_id of_sci_match[] = { · 41 unmodified lines
29633009 };
29643010 MODULE_DEVICE_TABLE(of, of_sci_match);
29653011
2966−static struct plat_sci_port *
2967−sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
3012+static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3013+ unsigned int *dev_id)
29683014 {
29693015 struct device_node *np = pdev->dev.of_node;
29703016 const struct of_device_id *match;
29713017 struct plat_sci_port *p;
3018+ struct sci_port *sp;
29723019 int id;
29733020
29743021 if (!IS_ENABLED(CONFIG_OF) || !np)
@@ -2989,15 +3036,14 @@ sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id) · 14 unmodified lines
29893036 return NULL;
29903037 }
29913038
3039+ sp = &sci_ports[id];
29923040 *dev_id = id;
29933041
2994− p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
29953042 p->type = SCI_OF_TYPE(match->data);
29963043 p->regtype = SCI_OF_REGTYPE(match->data);
2997− p->scscr = SCSCR_RE | SCSCR_TE;
29983044
29993045 if (of_find_property(np, "uart-has-rtscts", NULL))
3000− p->capabilities |= SCIx_HAVE_RTSCTS;
3046+ sp->has_rtscts = true;
30013047
30023048 return p;
30033049 }
@@ -3025,7 +3071,7 @@ static int sci_probe_single(struct platform_device *dev, · 21 unmodified lines
30253071 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
30263072 return PTR_ERR(sciport->gpios);
30273073
3028− if (p->capabilities & SCIx_HAVE_RTSCTS) {
3074+ if (sciport->has_rtscts) {
30293075 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
30303076 UART_GPIO_CTS)) ||
30313077 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
@@ -3081,6 +3127,24 @@ static int sci_probe(struct platform_device *dev) · 49 unmodified lines
30813127 if (ret)
30823128 return ret;
30833129
3130+ if (sp->port.fifosize > 1) {
3131+ ret = sysfs_create_file(&dev->dev.kobj,
3132+ &dev_attr_rx_fifo_trigger.attr);
3133+ if (ret)
3134+ return ret;
3135+ }
3136+ if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB) {
3137+ ret = sysfs_create_file(&dev->dev.kobj,
3138+ &dev_attr_rx_fifo_timeout.attr);
3139+ if (ret) {
3140+ if (sp->port.fifosize > 1) {
3141+ sysfs_remove_file(&dev->dev.kobj,
3142+ &dev_attr_rx_fifo_trigger.attr);
3143+ }
3144+ return ret;
3145+ }
3146+ }
3147+
30843148 #ifdef CONFIG_SH_STANDARD_BIOS
30853149 sh_bios_gdb_detach();
30863150 #endif
@@ -3159,12 +3223,12 @@ static int __init early_console_setup(struct earlycon_device *device, · 72 unmodified lines
31593223 device->port.serial_out = sci_serial_out;
31603224 device->port.type = type;
31613225 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3226+ port_cfg.type = type;
31623227 sci_ports[0].cfg = &port_cfg;
3163− sci_ports[0].cfg->type = type;
3164− sci_probe_regmap(sci_ports[0].cfg);
3165− port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3166− SCSCR_RE | SCSCR_TE;
3167− sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3228+ sci_ports[0].params = sci_probe_regmap(&port_cfg);
3229+ port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3230+ sci_serial_out(&sci_ports[0].port, SCSCR,
3231+ SCSCR_RE | SCSCR_TE | port_cfg.scscr);
31683232
31693233 device->con->write = serial_console_write;
31703234 return 0;
drivers/tty/serial/sh-sci.h+9−3
@@ -29,6 +29,8 @@ enum { · 28 unmodified lines
2929 SCPDR, /* Serial Port Data Register */
3030 SCDL, /* BRG Frequency Division Register */
3131 SCCKS, /* BRG Clock Select Register */
32+ HSRTRGR, /* Rx FIFO Data Count Trigger Register */
33+ HSTTRGR, /* Tx FIFO Data Count Trigger Register */
3234
3335 SCIx_NR_REGS,
3436 };
@@ -99,6 +101,10 @@ enum { · 64 unmodified lines
99101 #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
100102
101103 /* SCFCR (FIFO Control Register) */
104+#define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */
105+#define SCFCR_RTRG0 BIT(6)
106+#define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */
107+#define SCFCR_TTRG0 BIT(4)
102108 #define SCFCR_MCE BIT(3) /* Modem Control Enable */
103109 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
104110 #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
@@ -145,18 +151,18 @@ enum { · 40 unmodified lines
145151 #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
146152
147153 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
148−#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
154+#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
149155 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
150156 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
151157 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
152158 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
153159
154−#define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask)
160+#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
155161
156162 #define SCxSR_RDxF_CLEAR(port) \
157163 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
158164 #define SCxSR_ERROR_CLEAR(port) \
159− (to_sci_port(port)->error_clear)
165+ (to_sci_port(port)->params->error_clear)
160166 #define SCxSR_TDxE_CLEAR(port) \
161167 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
162168 #define SCxSR_BREAK_CLEAR(port) \
drivers/tty/serial/sirfsoc_uart.c+1−1
@@ -1061,7 +1061,7 @@ static void sirfsoc_uart_config_port(struct uart_port *port, int flags) · 1060 unmodified lines
10611061 }
10621062 }
10631063
1064−static struct uart_ops sirfsoc_uart_ops = {
1064+static const struct uart_ops sirfsoc_uart_ops = {
10651065 .tx_empty = sirfsoc_uart_tx_empty,
10661066 .get_mctrl = sirfsoc_uart_get_mctrl,
10671067 .set_mctrl = sirfsoc_uart_set_mctrl,
drivers/tty/serial/sn_console.c+1−1
@@ -380,7 +380,7 @@ static void snp_config_port(struct uart_port *port, int flags) · 379 unmodified lines
380380
381381 /* Associate the uart functions above - given to serial core */
382382
383−static struct uart_ops sn_console_ops = {
383+static const struct uart_ops sn_console_ops = {
384384 .tx_empty = snp_tx_empty,
385385 .set_mctrl = snp_set_mctrl,
386386 .get_mctrl = snp_get_mctrl,
drivers/tty/serial/sprd_serial.c+1−1
@@ -498,7 +498,7 @@ static int sprd_verify_port(struct uart_port *port, · 497 unmodified lines
498498 return 0;
499499 }
500500
501−static struct uart_ops serial_sprd_ops = {
501+static const struct uart_ops serial_sprd_ops = {
502502 .tx_empty = sprd_tx_empty,
503503 .get_mctrl = sprd_get_mctrl,
504504 .set_mctrl = sprd_set_mctrl,
drivers/tty/serial/st-asc.c+92−9
@@ -18,6 +18,7 @@ · 17 unmodified lines
1818 #include <linux/serial.h>
1919 #include <linux/console.h>
2020 #include <linux/sysrq.h>
21+#include <linux/pinctrl/consumer.h>
2122 #include <linux/platform_device.h>
2223 #include <linux/io.h>
2324 #include <linux/irq.h>
@@ -30,15 +31,23 @@ · 6 unmodified lines
3031 #include <linux/of_platform.h>
3132 #include <linux/serial_core.h>
3233 #include <linux/clk.h>
34+#include <linux/gpio/consumer.h>
3335
3436 #define DRIVER_NAME "st-asc"
3537 #define ASC_SERIAL_NAME "ttyAS"
3638 #define ASC_FIFO_SIZE 16
3739 #define ASC_MAX_PORTS 8
3840
41+/* Pinctrl states */
42+#define DEFAULT 0
43+#define NO_HW_FLOWCTRL 1
44+
3945 struct asc_port {
4046 struct uart_port port;
47+ struct gpio_desc *rts;
4148 struct clk *clk;
49+ struct pinctrl *pinctrl;
50+ struct pinctrl_state *states[2];
4251 unsigned int hw_flow_control:1;
4352 unsigned int force_m1:1;
4453 };
@@ -287,9 +296,19 @@ static void asc_transmit_chars(struct uart_port *port) · 242 unmodified lines
287296 static void asc_receive_chars(struct uart_port *port)
288297 {
289298 struct tty_port *tport = &port->state->port;
290− unsigned long status;
299+ unsigned long status, mode;
291300 unsigned long c = 0;
292301 char flag;
302+ bool ignore_pe = false;
303+
304+ /*
305+ * Datasheet states: If the MODE field selects an 8-bit frame then
306+ * this [parity error] bit is undefined. Software should ignore this
307+ * bit when reading 8-bit frames.
308+ */
309+ mode = asc_in(port, ASC_CTL) & ASC_CTL_MODE_MSK;
310+ if (mode == ASC_CTL_MODE_8BIT || mode == ASC_CTL_MODE_8BIT_PAR)
311+ ignore_pe = true;
293312
294313 if (port->irq_wake)
295314 pm_wakeup_event(tport->tty->dev, 0);
@@ -299,8 +318,8 @@ static void asc_receive_chars(struct uart_port *port) · 3 unmodified lines
299318 flag = TTY_NORMAL;
300319 port->icount.rx++;
301320
302− if ((c & (ASC_RXBUF_FE | ASC_RXBUF_PE)) ||
303− status & ASC_STA_OE) {
321+ if (status & ASC_STA_OE || c & ASC_RXBUF_FE ||
322+ (c & ASC_RXBUF_PE && !ignore_pe)) {
304323
305324 if (c & ASC_RXBUF_FE) {
306325 if (c == (ASC_RXBUF_FE | ASC_RXBUF_DUMMY_RX)) {
@@ -381,12 +400,27 @@ static unsigned int asc_tx_empty(struct uart_port *port) · 74 unmodified lines
381400
382401 static void asc_set_mctrl(struct uart_port *port, unsigned int mctrl)
383402 {
403+ struct asc_port *ascport = to_asc_port(port);
404+
384405 /*
385− * This routine is used for seting signals of: DTR, DCD, CTS/RTS
386− * We use ASC's hardware for CTS/RTS, so don't need any for that.
387− * Some boards have DTR and DCD implemented using PIO pins,
388− * code to do this should be hooked in here.
406+ * This routine is used for seting signals of: DTR, DCD, CTS and RTS.
407+ * We use ASC's hardware for CTS/RTS when hardware flow-control is
408+ * enabled, however if the RTS line is required for another purpose,
409+ * commonly controlled using HUP from userspace, then we need to toggle
410+ * it manually, using GPIO.
411+ *
412+ * Some boards also have DTR and DCD implemented using PIO pins, code to
413+ * do this should be hooked in here.
389414 */
415+
416+ if (!ascport->rts)
417+ return;
418+
419+ /* If HW flow-control is enabled, we can't fiddle with the RTS line */
420+ if (asc_in(port, ASC_CTL) & ASC_CTL_CTSENABLE)
421+ return;
422+
423+ gpiod_set_value(ascport->rts, mctrl & TIOCM_RTS);
390424 }
391425
392426 static unsigned int asc_get_mctrl(struct uart_port *port)
@@ -479,6 +513,8 @@ static void asc_set_termios(struct uart_port *port, struct ktermios *termios, · 86 unmodified lines
479513 struct ktermios *old)
480514 {
481515 struct asc_port *ascport = to_asc_port(port);
516+ struct device_node *np = port->dev->of_node;
517+ struct gpio_desc *gpiod;
482518 unsigned int baud;
483519 u32 ctrl_val;
484520 tcflag_t cflag;
@@ -522,9 +558,32 @@ static void asc_set_termios(struct uart_port *port, struct ktermios *termios, · 37 unmodified lines
522558 ctrl_val |= ASC_CTL_PARITYODD;
523559
524560 /* hardware flow control */
525− if ((cflag & CRTSCTS))
561+ if ((cflag & CRTSCTS)) {
526562 ctrl_val |= ASC_CTL_CTSENABLE;
527563
564+ /* If flow-control selected, stop handling RTS manually */
565+ if (ascport->rts) {
566+ devm_gpiod_put(port->dev, ascport->rts);
567+ ascport->rts = NULL;
568+
569+ pinctrl_select_state(ascport->pinctrl,
570+ ascport->states[DEFAULT]);
571+ }
572+ } else {
573+ /* If flow-control disabled, it's safe to handle RTS manually */
574+ if (!ascport->rts && ascport->states[NO_HW_FLOWCTRL]) {
575+ pinctrl_select_state(ascport->pinctrl,
576+ ascport->states[NO_HW_FLOWCTRL]);
577+
578+ gpiod = devm_get_gpiod_from_child(port->dev, "rts",
579+ &np->fwnode);
580+ if (!IS_ERR(gpiod)) {
581+ gpiod_direction_output(gpiod, 0);
582+ ascport->rts = gpiod;
583+ }
584+ }
585+ }
586+
528587 if ((baud < 19200) && !ascport->force_m1) {
529588 asc_out(port, ASC_BAUDRATE, (port->uartclk / (16 * baud)));
530589 } else {
@@ -667,6 +726,7 @@ static int asc_init_port(struct asc_port *ascport, · 136 unmodified lines
667726 {
668727 struct uart_port *port = &ascport->port;
669728 struct resource *res;
729+ int ret;
670730
671731 port->iotype = UPIO_MEM;
672732 port->flags = UPF_BOOT_AUTOCONF;
@@ -693,6 +753,27 @@ static int asc_init_port(struct asc_port *ascport, · 20 unmodified lines
693753 WARN_ON(ascport->port.uartclk == 0);
694754 clk_disable_unprepare(ascport->clk);
695755
756+ ascport->pinctrl = devm_pinctrl_get(&pdev->dev);
757+ if (IS_ERR(ascport->pinctrl)) {
758+ ret = PTR_ERR(ascport->pinctrl);
759+ dev_err(&pdev->dev, "Failed to get Pinctrl: %d\n", ret);
760+ }
761+
762+ ascport->states[DEFAULT] =
763+ pinctrl_lookup_state(ascport->pinctrl, "default");
764+ if (IS_ERR(ascport->states[DEFAULT])) {
765+ ret = PTR_ERR(ascport->states[DEFAULT]);
766+ dev_err(&pdev->dev,
767+ "Failed to look up Pinctrl state 'default': %d\n", ret);
768+ return ret;
769+ }
770+
771+ /* "no-hw-flowctrl" state is optional */
772+ ascport->states[NO_HW_FLOWCTRL] =
773+ pinctrl_lookup_state(ascport->pinctrl, "no-hw-flowctrl");
774+ if (IS_ERR(ascport->states[NO_HW_FLOWCTRL]))
775+ ascport->states[NO_HW_FLOWCTRL] = NULL;
776+
696777 return 0;
697778 }
698779
@@ -713,9 +794,11 @@ static struct asc_port *asc_of_get_asc_port(struct platform_device *pdev) · 14 unmodified lines
713794 return NULL;
714795
715796 asc_ports[id].hw_flow_control = of_property_read_bool(np,
716− "st,hw-flow-control");
797+ "uart-has-rtscts");
717798 asc_ports[id].force_m1 = of_property_read_bool(np, "st,force_m1");
718799 asc_ports[id].port.line = id;
800+ asc_ports[id].rts = NULL;
801+
719802 return &asc_ports[id];
720803 }
721804
drivers/tty/serial/sunhv.c+1−1
@@ -370,7 +370,7 @@ static int sunhv_verify_port(struct uart_port *port, struct serial_struct *ser) · 369 unmodified lines
370370 return -EINVAL;
371371 }
372372
373−static struct uart_ops sunhv_pops = {
373+static const struct uart_ops sunhv_pops = {
374374 .tx_empty = sunhv_tx_empty,
375375 .set_mctrl = sunhv_set_mctrl,
376376 .get_mctrl = sunhv_get_mctrl,
drivers/tty/serial/sunzilog.c+1−1
@@ -1046,7 +1046,7 @@ static void sunzilog_put_poll_char(struct uart_port *port, · 1045 unmodified lines
10461046 }
10471047 #endif /* CONFIG_CONSOLE_POLL */
10481048
1049−static struct uart_ops sunzilog_pops = {
1049+static const struct uart_ops sunzilog_pops = {
10501050 .tx_empty = sunzilog_tx_empty,
10511051 .set_mctrl = sunzilog_set_mctrl,
10521052 .get_mctrl = sunzilog_get_mctrl,
drivers/tty/serial/vr41xx_siu.c+1−1
@@ -681,7 +681,7 @@ static int siu_verify_port(struct uart_port *port, struct serial_struct *serial) · 680 unmodified lines
681681 return 0;
682682 }
683683
684−static struct uart_ops siu_uart_ops = {
684+static const struct uart_ops siu_uart_ops = {
685685 .tx_empty = siu_tx_empty,
686686 .set_mctrl = siu_set_mctrl,
687687 .get_mctrl = siu_get_mctrl,
drivers/tty/serial/vt8500_serial.c+1−1
@@ -592,7 +592,7 @@ static void vt8500_put_poll_char(struct uart_port *port, unsigned char c) · 591 unmodified lines
592592 }
593593 #endif
594594
595−static struct uart_ops vt8500_uart_pops = {
595+static const struct uart_ops vt8500_uart_pops = {
596596 .tx_empty = vt8500_tx_empty,
597597 .set_mctrl = vt8500_set_mctrl,
598598 .get_mctrl = vt8500_get_mctrl,
drivers/tty/serial/xilinx_uartps.c+9−0
@@ -93,6 +93,7 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); · 92 unmodified lines
9393 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
9494 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
9595 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
96+#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
9697
9798 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
9899 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
@@ -998,17 +999,25 @@ static unsigned int cdns_uart_get_mctrl(struct uart_port *port) · 899 unmodified lines
998999 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
9991000 {
10001001 u32 val;
1002+ u32 mode_reg;
10011003
10021004 val = readl(port->membase + CDNS_UART_MODEMCR);
1005+ mode_reg = readl(port->membase + CDNS_UART_MR);
10031006
10041007 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1008+ mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
10051009
10061010 if (mctrl & TIOCM_RTS)
10071011 val |= CDNS_UART_MODEMCR_RTS;
10081012 if (mctrl & TIOCM_DTR)
10091013 val |= CDNS_UART_MODEMCR_DTR;
1014+ if (mctrl & TIOCM_LOOP)
1015+ mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1016+ else
1017+ mode_reg |= CDNS_UART_MR_CHMODE_NORM;
10101018
10111019 writel(val, port->membase + CDNS_UART_MODEMCR);
1020+ writel(mode_reg, port->membase + CDNS_UART_MR);
10121021 }
10131022
10141023 #ifdef CONFIG_CONSOLE_POLL
drivers/tty/serial/zs.c+1−1
@@ -1045,7 +1045,7 @@ static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser) · 1044 unmodified lines
10451045 }
10461046
10471047
1048−static struct uart_ops zs_ops = {
1048+static const struct uart_ops zs_ops = {
10491049 .tx_empty = zs_tx_empty,
10501050 .set_mctrl = zs_set_mctrl,
10511051 .get_mctrl = zs_get_mctrl,
drivers/tty/tty_buffer.c+4−15
@@ -422,7 +422,7 @@ EXPORT_SYMBOL_GPL(tty_prepare_flip_string); · 421 unmodified lines
422422 *
423423 * Returns the number of bytes not processed
424424 */
425−int tty_ldisc_receive_buf(struct tty_ldisc *ld, unsigned char *p,
425+int tty_ldisc_receive_buf(struct tty_ldisc *ld, const unsigned char *p,
426426 char *f, int count)
427427 {
428428 if (ld->ops->receive_buf2)
@@ -437,7 +437,7 @@ int tty_ldisc_receive_buf(struct tty_ldisc *ld, unsigned char *p, · 8 unmodified lines
437437 EXPORT_SYMBOL_GPL(tty_ldisc_receive_buf);
438438
439439 static int
440−receive_buf(struct tty_ldisc *ld, struct tty_buffer *head, int count)
440+receive_buf(struct tty_port *port, struct tty_buffer *head, int count)
441441 {
442442 unsigned char *p = char_buf_ptr(head, head->read);
443443 char *f = NULL;
@@ -445,7 +445,7 @@ receive_buf(struct tty_ldisc *ld, struct tty_buffer *head, int count) · 1 unmodified line
445445 if (~head->flags & TTYB_NORMAL)
446446 f = flag_buf_ptr(head, head->read);
447447
448− return tty_ldisc_receive_buf(ld, p, f, count);
448+ return port->client_ops->receive_buf(port, p, f, count);
449449 }
450450
451451 /**
@@ -465,16 +465,6 @@ static void flush_to_ldisc(struct work_struct *work) · 13 unmodified lines
465465 {
466466 struct tty_port *port = container_of(work, struct tty_port, buf.work);
467467 struct tty_bufhead *buf = &port->buf;
468− struct tty_struct *tty;
469− struct tty_ldisc *disc;
470−
471− tty = READ_ONCE(port->itty);
472− if (tty == NULL)
473− return;
474−
475− disc = tty_ldisc_ref(tty);
476− if (disc == NULL)
477− return;
478468
479469 mutex_lock(&buf->lock);
480470
@@ -504,7 +494,7 @@ static void flush_to_ldisc(struct work_struct *work) · 23 unmodified lines
504494 continue;
505495 }
506496
507− count = receive_buf(disc, head, count);
497+ count = receive_buf(port, head, count);
508498 if (!count)
509499 break;
510500 head->read += count;
@@ -512,7 +502,6 @@ static void flush_to_ldisc(struct work_struct *work) · 1 unmodified line
512502
513503 mutex_unlock(&buf->lock);
514504
515− tty_ldisc_deref(disc);
516505 }
517506
518507 /**
drivers/tty/tty_io.c+33−19
@@ -855,7 +855,7 @@ static void tty_vhangup_session(struct tty_struct *tty) · 854 unmodified lines
855855
856856 int tty_hung_up_p(struct file *filp)
857857 {
858− return (filp->f_op == &hung_up_tty_fops);
858+ return (filp && filp->f_op == &hung_up_tty_fops);
859859 }
860860
861861 EXPORT_SYMBOL(tty_hung_up_p);
@@ -1744,6 +1744,37 @@ static int tty_release_checks(struct tty_struct *tty, int idx) · 882 unmodified lines
17441744 return 0;
17451745 }
17461746
1747+/**
1748+ * tty_release_struct - release a tty struct
1749+ * @tty: tty device
1750+ * @idx: index of the tty
1751+ *
1752+ * Performs the final steps to release and free a tty device. It is
1753+ * roughly the reverse of tty_init_dev.
1754+ */
1755+void tty_release_struct(struct tty_struct *tty, int idx)
1756+{
1757+ /*
1758+ * Ask the line discipline code to release its structures
1759+ */
1760+ tty_ldisc_release(tty);
1761+
1762+ /* Wait for pending work before tty destruction commmences */
1763+ tty_flush_works(tty);
1764+
1765+ tty_debug_hangup(tty, "freeing structure\n");
1766+ /*
1767+ * The release_tty function takes care of the details of clearing
1768+ * the slots and preserving the termios structure. The tty_unlock_pair
1769+ * should be safe as we keep a kref while the tty is locked (so the
1770+ * unlock never unlocks a freed tty).
1771+ */
1772+ mutex_lock(&tty_mutex);
1773+ release_tty(tty, idx);
1774+ mutex_unlock(&tty_mutex);
1775+}
1776+EXPORT_SYMBOL_GPL(tty_release_struct);
1777+
17471778 /**
17481779 * tty_release - vfs callback for close
17491780 * @inode: inode of tty
@@ -1898,25 +1929,8 @@ int tty_release(struct inode *inode, struct file *filp) · 148 unmodified lines
18981929 return 0;
18991930
19001931 tty_debug_hangup(tty, "final close\n");
1901− /*
1902− * Ask the line discipline code to release its structures
1903− */
1904− tty_ldisc_release(tty);
1905−
1906− /* Wait for pending work before tty destruction commmences */
1907− tty_flush_works(tty);
1908−
1909− tty_debug_hangup(tty, "freeing structure\n");
1910− /*
1911− * The release_tty function takes care of the details of clearing
1912− * the slots and preserving the termios structure. The tty_unlock_pair
1913− * should be safe as we keep a kref while the tty is locked (so the
1914− * unlock never unlocks a freed tty).
1915− */
1916− mutex_lock(&tty_mutex);
1917− release_tty(tty, idx);
1918− mutex_unlock(&tty_mutex);
19191932
1933+ tty_release_struct(tty, idx);
19201934 return 0;
19211935 }
19221936
drivers/tty/tty_port.c+55−10
@@ -16,6 +16,45 @@ · 15 unmodified lines
1616 #include <linux/bitops.h>
1717 #include <linux/delay.h>
1818 #include <linux/module.h>
19+#include <linux/serdev.h>
20+
21+static int tty_port_default_receive_buf(struct tty_port *port,
22+ const unsigned char *p,
23+ const unsigned char *f, size_t count)
24+{
25+ int ret;
26+ struct tty_struct *tty;
27+ struct tty_ldisc *disc;
28+
29+ tty = READ_ONCE(port->itty);
30+ if (!tty)
31+ return 0;
32+
33+ disc = tty_ldisc_ref(tty);
34+ if (!disc)
35+ return 0;
36+
37+ ret = tty_ldisc_receive_buf(disc, p, (char *)f, count);
38+
39+ tty_ldisc_deref(disc);
40+
41+ return ret;
42+}
43+
44+static void tty_port_default_wakeup(struct tty_port *port)
45+{
46+ struct tty_struct *tty = tty_port_tty_get(port);
47+
48+ if (tty) {
49+ tty_wakeup(tty);
50+ tty_kref_put(tty);
51+ }
52+}
53+
54+static const struct tty_port_client_operations default_client_ops = {
55+ .receive_buf = tty_port_default_receive_buf,
56+ .write_wakeup = tty_port_default_wakeup,
57+};
1958
2059 void tty_port_init(struct tty_port *port)
2160 {
@@ -28,6 +67,7 @@ void tty_port_init(struct tty_port *port) · 6 unmodified lines
2867 spin_lock_init(&port->lock);
2968 port->close_delay = (50 * HZ) / 100;
3069 port->closing_wait = (3000 * HZ) / 100;
70+ port->client_ops = &default_client_ops;
3171 kref_init(&port->kref);
3272 }
3373 EXPORT_SYMBOL(tty_port_init);
@@ -67,8 +107,7 @@ struct device *tty_port_register_device(struct tty_port *port, · 33 unmodified lines
67107 struct tty_driver *driver, unsigned index,
68108 struct device *device)
69109 {
70− tty_port_link_device(port, driver, index);
71− return tty_register_device(driver, index, device);
110+ return tty_port_register_device_attr(port, driver, index, device, NULL, NULL);
72111 }
73112 EXPORT_SYMBOL_GPL(tty_port_register_device);
74113
@@ -90,7 +129,15 @@ struct device *tty_port_register_device_attr(struct tty_port *port, · 15 unmodified lines
90129 struct device *device, void *drvdata,
91130 const struct attribute_group **attr_grp)
92131 {
132+ struct device *dev;
133+
93134 tty_port_link_device(port, driver, index);
135+
136+ dev = serdev_tty_port_register(port, device, driver, index);
137+ if (PTR_ERR(dev) != -ENODEV)
138+ /* Skip creating cdev if we registered a serdev device */
139+ return dev;
140+
94141 return tty_register_device_attr(driver, index, device, drvdata,
95142 attr_grp);
96143 }
@@ -142,6 +189,9 @@ static void tty_port_destructor(struct kref *kref) · 45 unmodified lines
142189 /* check if last port ref was dropped before tty release */
143190 if (WARN_ON(port->itty))
144191 return;
192+
193+ serdev_tty_port_unregister(port);
194+
145195 if (port->xmit_buf)
146196 free_page((unsigned long)port->xmit_buf);
147197 tty_port_destroy(port);
@@ -273,12 +323,7 @@ EXPORT_SYMBOL_GPL(tty_port_tty_hangup); · 125 unmodified lines
273323 */
274324 void tty_port_tty_wakeup(struct tty_port *port)
275325 {
276− struct tty_struct *tty = tty_port_tty_get(port);
277−
278− if (tty) {
279− tty_wakeup(tty);
280− tty_kref_put(tty);
281− }
326+ port->client_ops->write_wakeup(port);
282327 }
283328 EXPORT_SYMBOL_GPL(tty_port_tty_wakeup);
284329
@@ -335,7 +380,7 @@ EXPORT_SYMBOL(tty_port_lower_dtr_rts); · 50 unmodified lines
335380 * tty_port_block_til_ready - Waiting logic for tty open
336381 * @port: the tty port being opened
337382 * @tty: the tty device being bound
338− * @filp: the file pointer of the opener
383+ * @filp: the file pointer of the opener or NULL
339384 *
340385 * Implement the core POSIX/SuS tty behaviour when opening a tty device.
341386 * Handles:
@@ -369,7 +414,7 @@ int tty_port_block_til_ready(struct tty_port *port, · 27 unmodified lines
369414 tty_port_set_active(port, 1);
370415 return 0;
371416 }
372− if (filp->f_flags & O_NONBLOCK) {
417+ if (filp == NULL || (filp->f_flags & O_NONBLOCK)) {
373418 /* Indicate we are open */
374419 if (C_BAUD(tty))
375420 tty_port_raise_dtr_rts(port);
drivers/tty/vt/vt.c+9−0
@@ -625,6 +625,14 @@ static void save_screen(struct vc_data *vc) · 624 unmodified lines
625625 vc->vc_sw->con_save_screen(vc);
626626 }
627627
628+static void flush_scrollback(struct vc_data *vc)
629+{
630+ WARN_CONSOLE_UNLOCKED();
631+
632+ if (vc->vc_sw->con_flush_scrollback)
633+ vc->vc_sw->con_flush_scrollback(vc);
634+}
635+
628636 /*
629637 * Redrawing of screen
630638 */
@@ -1171,6 +1179,7 @@ static void csi_J(struct vc_data *vc, int vpar) · 540 unmodified lines
11711179 case 3: /* erase scroll-back buffer (and whole display) */
11721180 scr_memsetw(vc->vc_screenbuf, vc->vc_video_erase_char,
11731181 vc->vc_screenbuf_size);
1182+ flush_scrollback(vc);
11741183 set_origin(vc);
11751184 if (con_is_visible(vc))
11761185 update_screen(vc);
drivers/video/console/Kconfig+24−3
@@ -43,9 +43,30 @@ config VGACON_SOFT_SCROLLBACK_SIZE · 42 unmodified lines
4343 range 1 1024
4444 default "64"
4545 help
46− Enter the amount of System RAM to allocate for the scrollback
47− buffer. Each 64KB will give you approximately 16 80x25
48− screenfuls of scrollback buffer
46+ Enter the amount of System RAM to allocate for scrollback
47+ buffers of VGA consoles. Each 64KB will give you approximately
48+ 16 80x25 screenfuls of scrollback buffer.
49+
50+config VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT
51+ bool "Persistent Scrollback History for each console by default"
52+ depends on VGACON_SOFT_SCROLLBACK
53+ default n
54+ help
55+ Say Y here if the scrollback history should persist by default when
56+ switching between consoles. Otherwise, the scrollback history will be
57+ flushed each time the console is switched. This feature can also be
58+ enabled using the boot command line parameter
59+ 'vgacon.scrollback_persistent=1'.
60+
61+ This feature might break your tool of choice to flush the scrollback
62+ buffer, e.g. clear(1) will work fine but Debian's clear_console(1)
63+ will be broken, which might cause security issues.
64+ You can use the escape sequence \e[3J instead if this feature is
65+ activated.
66+
67+ Note that a buffer of VGACON_SOFT_SCROLLBACK_SIZE is taken for each
68+ created tty device.
69+ So if you use a RAM-constrained system, say N here.
4970
5071 config MDA_CONSOLE
5172 depends on !M68K && !PARISC && ISA
drivers/video/console/vgacon.c+112−52
@@ -162,70 +162,118 @@ static inline void vga_set_mem_top(struct vc_data *c) · 161 unmodified lines
162162
163163 #ifdef CONFIG_VGACON_SOFT_SCROLLBACK
164164 /* software scrollback */
165−static void *vgacon_scrollback;
166−static int vgacon_scrollback_tail;
167−static int vgacon_scrollback_size;
168−static int vgacon_scrollback_rows;
169−static int vgacon_scrollback_cnt;
170−static int vgacon_scrollback_cur;
171−static int vgacon_scrollback_save;
172−static int vgacon_scrollback_restore;
173−
174−static void vgacon_scrollback_init(int pitch)
165+struct vgacon_scrollback_info {
166+ void *data;
167+ int tail;
168+ int size;
169+ int rows;
170+ int cnt;
171+ int cur;
172+ int save;
173+ int restore;
174+};
175+
176+static struct vgacon_scrollback_info *vgacon_scrollback_cur;
177+static struct vgacon_scrollback_info vgacon_scrollbacks[MAX_NR_CONSOLES];
178+static bool scrollback_persistent = \
179+ IS_ENABLED(CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT);
180+module_param_named(scrollback_persistent, scrollback_persistent, bool, 0000);
181+MODULE_PARM_DESC(scrollback_persistent, "Enable persistent scrollback for all vga consoles");
182+
183+static void vgacon_scrollback_reset(int vc_num, size_t reset_size)
184+{
185+ struct vgacon_scrollback_info *scrollback = &vgacon_scrollbacks[vc_num];
186+
187+ if (scrollback->data && reset_size > 0)
188+ memset(scrollback->data, 0, reset_size);
189+
190+ scrollback->cnt = 0;
191+ scrollback->tail = 0;
192+ scrollback->cur = 0;
193+}
194+
195+static void vgacon_scrollback_init(int vc_num)
196+{
197+ int pitch = vga_video_num_columns * 2;
198+ size_t size = CONFIG_VGACON_SOFT_SCROLLBACK_SIZE * 1024;
199+ int rows = size / pitch;
200+ void *data;
201+
202+ data = kmalloc_array(CONFIG_VGACON_SOFT_SCROLLBACK_SIZE, 1024,
203+ GFP_NOWAIT);
204+
205+ vgacon_scrollbacks[vc_num].data = data;
206+ vgacon_scrollback_cur = &vgacon_scrollbacks[vc_num];
207+
208+ vgacon_scrollback_cur->rows = rows - 1;
209+ vgacon_scrollback_cur->size = rows * pitch;
210+
211+ vgacon_scrollback_reset(vc_num, size);
212+}
213+
214+static void vgacon_scrollback_switch(int vc_num)
175215 {
176− int rows = CONFIG_VGACON_SOFT_SCROLLBACK_SIZE * 1024/pitch;
177−
178− if (vgacon_scrollback) {
179− vgacon_scrollback_cnt = 0;
180− vgacon_scrollback_tail = 0;
181− vgacon_scrollback_cur = 0;
182− vgacon_scrollback_rows = rows - 1;
183− vgacon_scrollback_size = rows * pitch;
216+ if (!scrollback_persistent)
217+ vc_num = 0;
218+
219+ if (!vgacon_scrollbacks[vc_num].data) {
220+ vgacon_scrollback_init(vc_num);
221+ } else {
222+ if (scrollback_persistent) {
223+ vgacon_scrollback_cur = &vgacon_scrollbacks[vc_num];
224+ } else {
225+ size_t size = CONFIG_VGACON_SOFT_SCROLLBACK_SIZE * 1024;
226+
227+ vgacon_scrollback_reset(vc_num, size);
228+ }
184229 }
185230 }
186231
187232 static void vgacon_scrollback_startup(void)
188233 {
189− vgacon_scrollback = kcalloc(CONFIG_VGACON_SOFT_SCROLLBACK_SIZE, 1024, GFP_NOWAIT);
190− vgacon_scrollback_init(vga_video_num_columns * 2);
234+ vgacon_scrollback_cur = &vgacon_scrollbacks[0];
235+ vgacon_scrollback_init(0);
191236 }
192237
193238 static void vgacon_scrollback_update(struct vc_data *c, int t, int count)
194239 {
195240 void *p;
196241
197− if (!vgacon_scrollback_size || c->vc_num != fg_console)
242+ if (!vgacon_scrollback_cur->data || !vgacon_scrollback_cur->size ||
243+ c->vc_num != fg_console)
198244 return;
199245
200246 p = (void *) (c->vc_origin + t * c->vc_size_row);
201247
202248 while (count--) {
203− scr_memcpyw(vgacon_scrollback + vgacon_scrollback_tail,
249+ scr_memcpyw(vgacon_scrollback_cur->data +
250+ vgacon_scrollback_cur->tail,
204251 p, c->vc_size_row);
205− vgacon_scrollback_cnt++;
252+
253+ vgacon_scrollback_cur->cnt++;
206254 p += c->vc_size_row;
207− vgacon_scrollback_tail += c->vc_size_row;
255+ vgacon_scrollback_cur->tail += c->vc_size_row;
208256
209− if (vgacon_scrollback_tail >= vgacon_scrollback_size)
210− vgacon_scrollback_tail = 0;
257+ if (vgacon_scrollback_cur->tail >= vgacon_scrollback_cur->size)
258+ vgacon_scrollback_cur->tail = 0;
211259
212− if (vgacon_scrollback_cnt > vgacon_scrollback_rows)
213− vgacon_scrollback_cnt = vgacon_scrollback_rows;
260+ if (vgacon_scrollback_cur->cnt > vgacon_scrollback_cur->rows)
261+ vgacon_scrollback_cur->cnt = vgacon_scrollback_cur->rows;
214262
215− vgacon_scrollback_cur = vgacon_scrollback_cnt;
263+ vgacon_scrollback_cur->cur = vgacon_scrollback_cur->cnt;
216264 }
217265 }
218266
219267 static void vgacon_restore_screen(struct vc_data *c)
220268 {
221− vgacon_scrollback_save = 0;
269+ vgacon_scrollback_cur->save = 0;
222270
223− if (!vga_is_gfx && !vgacon_scrollback_restore) {
271+ if (!vga_is_gfx && !vgacon_scrollback_cur->restore) {
224272 scr_memcpyw((u16 *) c->vc_origin, (u16 *) c->vc_screenbuf,
225273 c->vc_screenbuf_size > vga_vram_size ?
226274 vga_vram_size : c->vc_screenbuf_size);
227− vgacon_scrollback_restore = 1;
228− vgacon_scrollback_cur = vgacon_scrollback_cnt;
275+ vgacon_scrollback_cur->restore = 1;
276+ vgacon_scrollback_cur->cur = vgacon_scrollback_cur->cnt;
229277 }
230278 }
231279
@@ -239,41 +287,41 @@ static void vgacon_scrolldelta(struct vc_data *c, int lines) · 7 unmodified lines
239287 return;
240288 }
241289
242− if (!vgacon_scrollback)
290+ if (!vgacon_scrollback_cur->data)
243291 return;
244292
245− if (!vgacon_scrollback_save) {
293+ if (!vgacon_scrollback_cur->save) {
246294 vgacon_cursor(c, CM_ERASE);
247295 vgacon_save_screen(c);
248− vgacon_scrollback_save = 1;
296+ vgacon_scrollback_cur->save = 1;
249297 }
250298
251− vgacon_scrollback_restore = 0;
252− start = vgacon_scrollback_cur + lines;
299+ vgacon_scrollback_cur->restore = 0;
300+ start = vgacon_scrollback_cur->cur + lines;
253301 end = start + abs(lines);
254302
255303 if (start < 0)
256304 start = 0;
257305
258− if (start > vgacon_scrollback_cnt)
259− start = vgacon_scrollback_cnt;
306+ if (start > vgacon_scrollback_cur->cnt)
307+ start = vgacon_scrollback_cur->cnt;
260308
261309 if (end < 0)
262310 end = 0;
263311
264− if (end > vgacon_scrollback_cnt)
265− end = vgacon_scrollback_cnt;
312+ if (end > vgacon_scrollback_cur->cnt)
313+ end = vgacon_scrollback_cur->cnt;
266314
267− vgacon_scrollback_cur = start;
315+ vgacon_scrollback_cur->cur = start;
268316 count = end - start;
269− soff = vgacon_scrollback_tail - ((vgacon_scrollback_cnt - end) *
270− c->vc_size_row);
317+ soff = vgacon_scrollback_cur->tail -
318+ ((vgacon_scrollback_cur->cnt - end) * c->vc_size_row);
271319 soff -= count * c->vc_size_row;
272320
273321 if (soff < 0)
274− soff += vgacon_scrollback_size;
322+ soff += vgacon_scrollback_cur->size;
275323
276− count = vgacon_scrollback_cnt - start;
324+ count = vgacon_scrollback_cur->cnt - start;
277325
278326 if (count > c->vc_rows)
279327 count = c->vc_rows;
@@ -287,13 +335,13 @@ static void vgacon_scrolldelta(struct vc_data *c, int lines) · 7 unmodified lines
287335
288336 count *= c->vc_size_row;
289337 /* how much memory to end of buffer left? */
290− copysize = min(count, vgacon_scrollback_size - soff);
291− scr_memcpyw(d, vgacon_scrollback + soff, copysize);
338+ copysize = min(count, vgacon_scrollback_cur->size - soff);
339+ scr_memcpyw(d, vgacon_scrollback_cur->data + soff, copysize);
292340 d += copysize;
293341 count -= copysize;
294342
295343 if (count) {
296− scr_memcpyw(d, vgacon_scrollback, count);
344+ scr_memcpyw(d, vgacon_scrollback_cur->data, count);
297345 d += count;
298346 }
299347
@@ -302,10 +350,18 @@ static void vgacon_scrolldelta(struct vc_data *c, int lines) · 2 unmodified lines
302350 } else
303351 vgacon_cursor(c, CM_MOVE);
304352 }
353+
354+static void vgacon_flush_scrollback(struct vc_data *c)
355+{
356+ size_t size = CONFIG_VGACON_SOFT_SCROLLBACK_SIZE * 1024;
357+
358+ vgacon_scrollback_reset(c->vc_num, size);
359+}
305360 #else
306361 #define vgacon_scrollback_startup(...) do { } while (0)
307362 #define vgacon_scrollback_init(...) do { } while (0)
308363 #define vgacon_scrollback_update(...) do { } while (0)
364+#define vgacon_scrollback_switch(...) do { } while (0)
309365
310366 static void vgacon_restore_screen(struct vc_data *c)
311367 {
@@ -319,6 +375,10 @@ static void vgacon_scrolldelta(struct vc_data *c, int lines) · 7 unmodified lines
319375 vga_vram_size);
320376 vga_set_mem_top(c);
321377 }
378+
379+static void vgacon_flush_scrollback(struct vc_data *c)
380+{
381+}
322382 #endif /* CONFIG_VGACON_SOFT_SCROLLBACK */
323383
324384 static const char *vgacon_startup(void)
@@ -780,7 +840,7 @@ static int vgacon_switch(struct vc_data *c) · 455 unmodified lines
780840 vgacon_doresize(c, c->vc_cols, c->vc_rows);
781841 }
782842
783− vgacon_scrollback_init(c->vc_size_row);
843+ vgacon_scrollback_switch(c->vc_num);
784844 return 0; /* Redrawing not needed */
785845 }
786846
@@ -1326,7 +1386,6 @@ static bool vgacon_scroll(struct vc_data *c, unsigned int t, unsigned int b, · 539 unmodified lines
13261386 return true;
13271387 }
13281388
1329−
13301389 /*
13311390 * The console `switch' structure for the VGA based console
13321391 */
@@ -1359,6 +1418,7 @@ const struct consw vga_con = { · 26 unmodified lines
13591418 .con_save_screen = vgacon_save_screen,
13601419 .con_build_attr = vgacon_build_attr,
13611420 .con_invert_region = vgacon_invert_region,
1421+ .con_flush_scrollback = vgacon_flush_scrollback,
13621422 };
13631423 EXPORT_SYMBOL(vga_con);
13641424
include/linux/console.h+4−0
@@ -72,6 +72,10 @@ struct consw { · 71 unmodified lines
7272 void (*con_invert_region)(struct vc_data *, u16 *, int);
7373 u16 *(*con_screen_pos)(struct vc_data *, int);
7474 unsigned long (*con_getxy)(struct vc_data *, unsigned long, int *, int *);
75+ /*
76+ * Flush the video console driver's scrollback buffer
77+ */
78+ void (*con_flush_scrollback)(struct vc_data *);
7579 /*
7680 * Prepare the console for the debugger. This includes, but is not
7781 * limited to, unblanking the console, loading an appropriate
include/linux/serdev.h+262−0
@@ -0,0 +1,262 @@
1+/*
2+ * Copyright (C) 2016-2017 Linaro Ltd., Rob Herring <robh@kernel.org>
3+ *
4+ * This program is free software; you can redistribute it and/or modify
5+ * it under the terms of the GNU General Public License version 2 and
6+ * only version 2 as published by the Free Software Foundation.
7+ *
8+ * This program is distributed in the hope that it will be useful,
9+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
10+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11+ * GNU General Public License for more details.
12+ */
13+#ifndef _LINUX_SERDEV_H
14+#define _LINUX_SERDEV_H
15+
16+#include <linux/types.h>
17+#include <linux/device.h>
18+
19+struct serdev_controller;
20+struct serdev_device;
21+
22+/*
23+ * serdev device structures
24+ */
25+
26+/**
27+ * struct serdev_device_ops - Callback operations for a serdev device
28+ * @receive_buf: Function called with data received from device.
29+ * @write_wakeup: Function called when ready to transmit more data.
30+ */
31+struct serdev_device_ops {
32+ int (*receive_buf)(struct serdev_device *, const unsigned char *, size_t);
33+ void (*write_wakeup)(struct serdev_device *);
34+};
35+
36+/**
37+ * struct serdev_device - Basic representation of an serdev device
38+ * @dev: Driver model representation of the device.
39+ * @nr: Device number on serdev bus.
40+ * @ctrl: serdev controller managing this device.
41+ * @ops: Device operations.
42+ */
43+struct serdev_device {
44+ struct device dev;
45+ int nr;
46+ struct serdev_controller *ctrl;
47+ const struct serdev_device_ops *ops;
48+};
49+
50+static inline struct serdev_device *to_serdev_device(struct device *d)
51+{
52+ return container_of(d, struct serdev_device, dev);
53+}
54+
55+/**
56+ * struct serdev_device_driver - serdev slave device driver
57+ * @driver: serdev device drivers should initialize name field of this
58+ * structure.
59+ * @probe: binds this driver to a serdev device.
60+ * @remove: unbinds this driver from the serdev device.
61+ */
62+struct serdev_device_driver {
63+ struct device_driver driver;
64+ int (*probe)(struct serdev_device *);
65+ void (*remove)(struct serdev_device *);
66+};
67+
68+static inline struct serdev_device_driver *to_serdev_device_driver(struct device_driver *d)
69+{
70+ return container_of(d, struct serdev_device_driver, driver);
71+}
72+
73+/*
74+ * serdev controller structures
75+ */
76+struct serdev_controller_ops {
77+ int (*write_buf)(struct serdev_controller *, const unsigned char *, size_t);
78+ void (*write_flush)(struct serdev_controller *);
79+ int (*write_room)(struct serdev_controller *);
80+ int (*open)(struct serdev_controller *);
81+ void (*close)(struct serdev_controller *);
82+ void (*set_flow_control)(struct serdev_controller *, bool);
83+ unsigned int (*set_baudrate)(struct serdev_controller *, unsigned int);
84+};
85+
86+/**
87+ * struct serdev_controller - interface to the serdev controller
88+ * @dev: Driver model representation of the device.
89+ * @nr: number identifier for this controller/bus.
90+ * @serdev: Pointer to slave device for this controller.
91+ * @ops: Controller operations.
92+ */
93+struct serdev_controller {
94+ struct device dev;
95+ unsigned int nr;
96+ struct serdev_device *serdev;
97+ const struct serdev_controller_ops *ops;
98+};
99+
100+static inline struct serdev_controller *to_serdev_controller(struct device *d)
101+{
102+ return container_of(d, struct serdev_controller, dev);
103+}
104+
105+static inline void *serdev_device_get_drvdata(const struct serdev_device *serdev)
106+{
107+ return dev_get_drvdata(&serdev->dev);
108+}
109+
110+static inline void serdev_device_set_drvdata(struct serdev_device *serdev, void *data)
111+{
112+ dev_set_drvdata(&serdev->dev, data);
113+}
114+
115+/**
116+ * serdev_device_put() - decrement serdev device refcount
117+ * @serdev serdev device.
118+ */
119+static inline void serdev_device_put(struct serdev_device *serdev)
120+{
121+ if (serdev)
122+ put_device(&serdev->dev);
123+}
124+
125+static inline void serdev_device_set_client_ops(struct serdev_device *serdev,
126+ const struct serdev_device_ops *ops)
127+{
128+ serdev->ops = ops;
129+}
130+
131+static inline
132+void *serdev_controller_get_drvdata(const struct serdev_controller *ctrl)
133+{
134+ return ctrl ? dev_get_drvdata(&ctrl->dev) : NULL;
135+}
136+
137+static inline void serdev_controller_set_drvdata(struct serdev_controller *ctrl,
138+ void *data)
139+{
140+ dev_set_drvdata(&ctrl->dev, data);
141+}
142+
143+/**
144+ * serdev_controller_put() - decrement controller refcount
145+ * @ctrl serdev controller.
146+ */
147+static inline void serdev_controller_put(struct serdev_controller *ctrl)
148+{
149+ if (ctrl)
150+ put_device(&ctrl->dev);
151+}
152+
153+struct serdev_device *serdev_device_alloc(struct serdev_controller *);
154+int serdev_device_add(struct serdev_device *);
155+void serdev_device_remove(struct serdev_device *);
156+
157+struct serdev_controller *serdev_controller_alloc(struct device *, size_t);
158+int serdev_controller_add(struct serdev_controller *);
159+void serdev_controller_remove(struct serdev_controller *);
160+
161+static inline void serdev_controller_write_wakeup(struct serdev_controller *ctrl)
162+{
163+ struct serdev_device *serdev = ctrl->serdev;
164+
165+ if (!serdev || !serdev->ops->write_wakeup)
166+ return;
167+
168+ serdev->ops->write_wakeup(ctrl->serdev);
169+}
170+
171+static inline int serdev_controller_receive_buf(struct serdev_controller *ctrl,
172+ const unsigned char *data,
173+ size_t count)
174+{
175+ struct serdev_device *serdev = ctrl->serdev;
176+
177+ if (!serdev || !serdev->ops->receive_buf)
178+ return -EINVAL;
179+
180+ return serdev->ops->receive_buf(ctrl->serdev, data, count);
181+}
182+
183+#if IS_ENABLED(CONFIG_SERIAL_DEV_BUS)
184+
185+int serdev_device_open(struct serdev_device *);
186+void serdev_device_close(struct serdev_device *);
187+unsigned int serdev_device_set_baudrate(struct serdev_device *, unsigned int);
188+void serdev_device_set_flow_control(struct serdev_device *, bool);
189+int serdev_device_write_buf(struct serdev_device *, const unsigned char *, size_t);
190+void serdev_device_write_flush(struct serdev_device *);
191+int serdev_device_write_room(struct serdev_device *);
192+
193+/*
194+ * serdev device driver functions
195+ */
196+int __serdev_device_driver_register(struct serdev_device_driver *, struct module *);
197+#define serdev_device_driver_register(sdrv) \
198+ __serdev_device_driver_register(sdrv, THIS_MODULE)
199+
200+/**
201+ * serdev_device_driver_unregister() - unregister an serdev client driver
202+ * @sdrv: the driver to unregister
203+ */
204+static inline void serdev_device_driver_unregister(struct serdev_device_driver *sdrv)
205+{
206+ if (sdrv)
207+ driver_unregister(&sdrv->driver);
208+}
209+
210+#define module_serdev_device_driver(__serdev_device_driver) \
211+ module_driver(__serdev_device_driver, serdev_device_driver_register, \
212+ serdev_device_driver_unregister)
213+
214+#else
215+
216+static inline int serdev_device_open(struct serdev_device *sdev)
217+{
218+ return -ENODEV;
219+}
220+static inline void serdev_device_close(struct serdev_device *sdev) {}
221+static inline unsigned int serdev_device_set_baudrate(struct serdev_device *sdev, unsigned int baudrate)
222+{
223+ return 0;
224+}
225+static inline void serdev_device_set_flow_control(struct serdev_device *sdev, bool enable) {}
226+static inline int serdev_device_write_buf(struct serdev_device *sdev, const unsigned char *buf, size_t count)
227+{
228+ return -ENODEV;
229+}
230+static inline void serdev_device_write_flush(struct serdev_device *sdev) {}
231+static inline int serdev_device_write_room(struct serdev_device *sdev)
232+{
233+ return 0;
234+}
235+
236+#define serdev_device_driver_register(x)
237+#define serdev_device_driver_unregister(x)
238+
239+#endif /* CONFIG_SERIAL_DEV_BUS */
240+
241+/*
242+ * serdev hooks into TTY core
243+ */
244+struct tty_port;
245+struct tty_driver;
246+
247+#ifdef CONFIG_SERIAL_DEV_CTRL_TTYPORT
248+struct device *serdev_tty_port_register(struct tty_port *port,
249+ struct device *parent,
250+ struct tty_driver *drv, int idx);
251+void serdev_tty_port_unregister(struct tty_port *port);
252+#else
253+static inline struct device *serdev_tty_port_register(struct tty_port *port,
254+ struct device *parent,
255+ struct tty_driver *drv, int idx)
256+{
257+ return ERR_PTR(-ENODEV);
258+}
259+static inline void serdev_tty_port_unregister(struct tty_port *port) {}
260+#endif /* CONFIG_SERIAL_DEV_CTRL_TTYPORT */
261+
262+#endif /*_LINUX_SERDEV_H */
include/linux/serial_core.h+1−1
@@ -450,7 +450,7 @@ extern void uart_handle_cts_change(struct uart_port *uport, · 449 unmodified lines
450450 extern void uart_insert_char(struct uart_port *port, unsigned int status,
451451 unsigned int overrun, unsigned int ch, unsigned int flag);
452452
453−#ifdef SUPPORT_SYSRQ
453+#if defined(SUPPORT_SYSRQ) && defined(CONFIG_MAGIC_SYSRQ_SERIAL)
454454 static inline int
455455 uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
456456 {
include/linux/serial_sci.h+0−15
@@ -9,8 +9,6 @@ · 8 unmodified lines
99 * Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
1010 */
1111
12−#define SCIx_NOT_SUPPORTED (-1)
13−
1412 /* Serial Control Register (@ = not supported by all parts) */
1513 #define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */
1614 #define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */
@@ -41,24 +39,16 @@ enum { · 24 unmodified lines
4139 SCIx_NR_REGTYPES,
4240 };
4341
44−struct device;
45−
4642 struct plat_sci_port_ops {
4743 void (*init_pins)(struct uart_port *, unsigned int cflag);
4844 };
4945
50−/*
51− * Port-specific capabilities
52− */
53−#define SCIx_HAVE_RTSCTS BIT(0)
54−
5546 /*
5647 * Platform device specific platform_data struct
5748 */
5849 struct plat_sci_port {
5950 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
6051 upf_t flags; /* UPF_* flags */
61− unsigned long capabilities; /* Port features/capabilities */
6252
6353 unsigned int sampling_rate;
6454 unsigned int scscr; /* SCSCR initialization */
@@ -66,14 +56,9 @@ struct plat_sci_port { · 1 unmodified line
6656 /*
6757 * Platform overrides if necessary, defaults otherwise.
6858 */
69− int port_reg;
70− unsigned char regshift;
7159 unsigned char regtype;
7260
7361 struct plat_sci_port_ops *ops;
74−
75− unsigned int dma_slave_tx;
76− unsigned int dma_slave_rx;
7762 };
7863
7964 #endif /* __LINUX_SERIAL_SCI_H */
include/linux/tty.h+10−2
@@ -217,12 +217,18 @@ struct tty_port_operations { · 216 unmodified lines
217217 /* Called on the final put of a port */
218218 void (*destruct)(struct tty_port *port);
219219 };
220−
220+
221+struct tty_port_client_operations {
222+ int (*receive_buf)(struct tty_port *port, const unsigned char *, const unsigned char *, size_t);
223+ void (*write_wakeup)(struct tty_port *port);
224+};
225+
221226 struct tty_port {
222227 struct tty_bufhead buf; /* Locked internally */
223228 struct tty_struct *tty; /* Back pointer */
224229 struct tty_struct *itty; /* internal back ptr */
225230 const struct tty_port_operations *ops; /* Port operations */
231+ const struct tty_port_client_operations *client_ops; /* Port client operations */
226232 spinlock_t lock; /* Lock protecting tty field */
227233 int blocked_open; /* Waiting to open */
228234 int count; /* Usage count */
@@ -241,6 +247,7 @@ struct tty_port { · 12 unmodified lines
241247 based drain is needed else
242248 set to size of fifo */
243249 struct kref kref; /* Ref counter */
250+ void *client_data;
244251 };
245252
246253 /* tty_port::iflags bits -- use atomic bit ops */
@@ -528,6 +535,7 @@ extern int tty_alloc_file(struct file *file); · 281 unmodified lines
528535 extern void tty_add_file(struct tty_struct *tty, struct file *file);
529536 extern void tty_free_file(struct file *file);
530537 extern struct tty_struct *tty_init_dev(struct tty_driver *driver, int idx);
538+extern void tty_release_struct(struct tty_struct *tty, int idx);
531539 extern int tty_release(struct inode *inode, struct file *filp);
532540 extern void tty_init_termios(struct tty_struct *tty);
533541 extern int tty_standard_install(struct tty_driver *driver,
@@ -656,7 +664,7 @@ extern int tty_ldisc_setup(struct tty_struct *tty, struct tty_struct *o_tty); · 122 unmodified lines
656664 extern void tty_ldisc_release(struct tty_struct *tty);
657665 extern void tty_ldisc_init(struct tty_struct *tty);
658666 extern void tty_ldisc_deinit(struct tty_struct *tty);
659−extern int tty_ldisc_receive_buf(struct tty_ldisc *ld, unsigned char *p,
667+extern int tty_ldisc_receive_buf(struct tty_ldisc *ld, const unsigned char *p,
660668 char *f, int count);
661669
662670 /* n_tty.c */
include/uapi/linux/serial_core.h+2−1
@@ -56,7 +56,8 @@ · 55 unmodified lines
5656 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
5757 #define PORT_RT2880 29 /* Ralink RT2880 internal UART */
5858 #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
59−#define PORT_MAX_8250 30 /* max port ID */
59+#define PORT_DA830 31 /* TI DA8xx/66AK2x */
60+#define PORT_MAX_8250 31 /* max port ID */
6061
6162 /*
6263 * ARM specific type numbers. These are not currently guaranteed
include/uapi/linux/serial_reg.h+8−18
@@ -327,6 +327,14 @@ · 326 unmodified lines
327327 #define SERIAL_RSA_BAUD_BASE (921600)
328328 #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
329329
330+/* Extra registers for TI DA8xx/66AK2x */
331+#define UART_DA830_PWREMU_MGMT 12
332+
333+/* PWREMU_MGMT register bits */
334+#define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
335+#define UART_DA830_PWREMU_MGMT_URRST (1 << 13) /* Receiver reset/enable */
336+#define UART_DA830_PWREMU_MGMT_UTRST (1 << 14) /* Transmitter reset/enable */
337+
330338 /*
331339 * Extra serial register definitions for the internal UARTs
332340 * in TI OMAP processors.
@@ -358,24 +366,6 @@ · 25 unmodified lines
358366 #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */
359367 #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
360368
361−/*
362− * These are definitions for the Exar XR17V35X and XR17(C|D)15X
363− */
364−#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
365−#define UART_EXAR_SLEEP 0x8b /* Sleep mode */
366−#define UART_EXAR_DVID 0x8d /* Device identification */
367−
368−#define UART_EXAR_FCTR 0x08 /* Feature Control Register */
369−#define UART_FCTR_EXAR_IRDA 0x08 /* IrDa data encode select */
370−#define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */
371−#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
372−#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
373−#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
374−#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
375−
376−#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
377−#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
378−
379369 /*
380370 * These are definitions for the Altera ALTR_16550_F32/F64/F128
381371 * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).
lib/Kconfig.debug+10−0
@@ -416,6 +416,16 @@ config MAGIC_SYSRQ_DEFAULT_ENABLE · 415 unmodified lines
416416 This may be set to 1 or 0 to enable or disable them all, or
417417 to a bitmask as described in Documentation/sysrq.txt.
418418
419+config MAGIC_SYSRQ_SERIAL
420+ bool "Enable magic SysRq key over serial"
421+ depends on MAGIC_SYSRQ
422+ default y
423+ help
424+ Many embedded boards have a disconnected TTL level serial which can
425+ generate some garbage that can lead to spurious false sysrq detects.
426+ This option allows you to decide whether you want to enable the
427+ magic SysRq key.
428+
419429 config DEBUG_KERNEL
420430 bool "Kernel debugging"
421431 help