History

Merge tag 'drm-intel-next-2023-09-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

drm/i915 feature pull for v6.7: Features and functionality: - Early Xe2 LPD / Lunarlake (LNL) display enabling (Lucas, Matt, Gustavo, Stanislav, Luca, Clint, Juha-Pekka, Balasubramani, Ravi) - Plenty of various DSC improvements and fixes (Ankit) - Add DSC PPS state readout and verification (Suraj) - Improve fastsets for VRR, LRR and M/N updates (Ville) - Use connector->ddc to create (non-DP MST) connector sysfs ddc symlinks (Ville) - Various DSB improvements, load LUTs using DSB (Ville) - Improve shared link bandwidth management, starting with FDI (Imre) - Optimize get param ioctl for PXP status (Alan) - Remove DG2 pre-production hardware workarounds (Matt) - Add more RPL P/U PCI IDs (Dnyaneshwar) - Add new DG2-G12 stepping (Swati) - Add PSR sink error status to debugfs (Jouni) - Add DP enhanced framing to crtc state checker (Ville) Refactoring and cleanups: - Simplify TileY/Tile4 tiling selftest enumeration (Matt) - Remove some unused power domain code (Gustavo) - Check stepping of display IP version rather than MTL platform (Matt) - DP audio compute config cleanups (Vinod) - SDVO cleanups and refactoring, more robust failure handling (Ville) - Color register definition and readout cleanups (Jani) - Reduce header interdependencies for frontbuffer tracking (Jani) - Continue replacing struct edid with struct drm_edid (Jani) - Use source physical address instead of EDID for CEC (Jani) - Clean up Type-C port lane count functions (Luca) - Clean up DSC PPS register definitions and readout (Jani) - Stop using GEM_BUG_ON()/GEM_WARN_ON() in display code (Jani) - Move more of the display probe to display code (Jani) - Remove redundant runtime suspended state flag (Jouni) - Move display info printing to display code (Balasubramani) - Frontbuffer tracking improvements (Jouni) - Add trailing newlines to debug logging (Jim Cromie) - Separate display workarounds from clock gating init (Matt) - Reduce dmesg log spamming for combo PHY, PLL state, FEC, DP MST (Ville, Imre) Fixes: - Fix hotplug poll detect loops via suspend/resume (Imre) - Fix hotplug detect for forced connectors (Imre) - Fix DSC first_line_bpg_offset calculation (Suraj) - Fix debug prints for SDP CRC16 (Arun) - Fix PXP runtime resume (Alan) - Fix cx0 PHY lane handling (Gustavo) - Fix frontbuffer tracking locking in debugfs (Juha-Pekka) - Fix SDVO detect on some models (Ville) - Fix SDP split configuration for DP MST (Vinod) - Fix AUX usage and reads for HDCP on DP MST (Suraj) - Fix PSR workaround (Jouni) - Fix redundant AUX power get/put in DP force (Imre) - Fix ICL DSI TCLK POST by letting hardware handle it (William) - Fix IRQ reset for XE LP+ (Gustavo) - Fix h/vsync_end instead of h/vtotal in VBT (Ville) - Fix C20 PHY msgbus timeout issues (Gustavo) - Fix pre-TGL FEC pipe A vs. DDI A mixup (Ville) - Fix FEC state readout for DP MST (Ville) DRM subsystem core changes: - Assume sink supports 8 bpc when DSC is supported (Ankit) - Add drm_edid_is_digital() helper (Jani) - Parse source physical address from EDID (Jani) - Add function to attach CEC without EDID (Jani) - Reorder connector sysfs/debugfs remove (Ville) - Register connector sysfs ddc symlink later (Ville) Media subsystem changes: - Add comments about CEC source physical address usage (Jani) Merges: - Backmerge drm-next to get v6.6-rc1 (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> # Conflicts: # drivers/gpu/drm/i915/i915_drv.h From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87r0mhi7a6.fsf@intel.com

Dave Airlie committed 3 years ago

Commit 389af782 parents caacbdc 3570bd9142 files · +4550 −2464Browse files

Unified · Split

142 files
  1. drivers/gpu/drm/display/drm_dp_cec.c +20 −3
  2. drivers/gpu/drm/display/drm_dp_helper.c +6 −2
  3. drivers/gpu/drm/drm_connector.c +10 −1
  4. drivers/gpu/drm/drm_edid.c +20 −2
  5. drivers/gpu/drm/drm_internal.h +2 −0
  6. drivers/gpu/drm/drm_sysfs.c +15 −7
  7. drivers/gpu/drm/i915/Makefile +2 −0
  8. drivers/gpu/drm/i915/display/g4x_dp.c +8 −2
  9. drivers/gpu/drm/i915/display/g4x_hdmi.c +5 −1
  10. drivers/gpu/drm/i915/display/hsw_ips.c +1 −0
  11. drivers/gpu/drm/i915/display/i9xx_plane.c +1 −0
  12. drivers/gpu/drm/i915/display/icl_dsi.c +1 −12
  13. drivers/gpu/drm/i915/display/intel_atomic.c +2 −0
  14. drivers/gpu/drm/i915/display/intel_atomic_plane.c +11 −3
  15. drivers/gpu/drm/i915/display/intel_audio.c +3 −3
  16. drivers/gpu/drm/i915/display/intel_audio.h +1 −2
  17. drivers/gpu/drm/i915/display/intel_bios.c +17 −9
  18. drivers/gpu/drm/i915/display/intel_cdclk.c +86 −21
  19. drivers/gpu/drm/i915/display/intel_color.c +142 −12
  20. drivers/gpu/drm/i915/display/intel_color.h +2 −0
  21. drivers/gpu/drm/i915/display/intel_color_regs.h +286 −0
  22. drivers/gpu/drm/i915/display/intel_combo_phy.c +8 −9
  23. drivers/gpu/drm/i915/display/intel_connector.c +3 −3
  24. drivers/gpu/drm/i915/display/intel_connector.h +1 −1
  25. drivers/gpu/drm/i915/display/intel_crt.c +33 −31
  26. drivers/gpu/drm/i915/display/intel_crtc.c +76 −42
  27. drivers/gpu/drm/i915/display/intel_crtc.h +4 −2
  28. drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +3 −0
  29. drivers/gpu/drm/i915/display/intel_cx0_phy.c +107 −98
  30. drivers/gpu/drm/i915/display/intel_cx0_phy.h +8 −6
  31. drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +13 −0
  32. drivers/gpu/drm/i915/display/intel_ddi.c +20 −18
  33. drivers/gpu/drm/i915/display/intel_display.c +337 −139
  34. drivers/gpu/drm/i915/display/intel_display.h +4 −4
  35. drivers/gpu/drm/i915/display/intel_display_debugfs.c +4 −0
  36. drivers/gpu/drm/i915/display/intel_display_device.c +82 −16
  37. drivers/gpu/drm/i915/display/intel_display_device.h +28 −3
  38. drivers/gpu/drm/i915/display/intel_display_driver.c +8 −0
  39. drivers/gpu/drm/i915/display/intel_display_irq.c +3 −1
  40. drivers/gpu/drm/i915/display/intel_display_power.c +4 −6
  41. drivers/gpu/drm/i915/display/intel_display_power.h +0 −1
  42. drivers/gpu/drm/i915/display/intel_display_power_map.c +53 −10
  43. drivers/gpu/drm/i915/display/intel_display_power_well.c +49 −3
  44. drivers/gpu/drm/i915/display/intel_display_power_well.h +1 −0
  45. drivers/gpu/drm/i915/display/intel_display_types.h +40 −9
  46. drivers/gpu/drm/i915/display/intel_display_wa.c +48 −0
  47. drivers/gpu/drm/i915/display/intel_display_wa.h +13 −0
  48. drivers/gpu/drm/i915/display/intel_dmc.c +1 −1
  49. drivers/gpu/drm/i915/display/intel_dp.c +676 −201
  50. drivers/gpu/drm/i915/display/intel_dp.h +26 −8
  51. drivers/gpu/drm/i915/display/intel_dp_aux.c +29 −20
  52. drivers/gpu/drm/i915/display/intel_dp_aux_regs.h +44 −36
  53. drivers/gpu/drm/i915/display/intel_dp_hdcp.c +58 −29
  54. drivers/gpu/drm/i915/display/intel_dp_link_training.c +8 −6
  55. drivers/gpu/drm/i915/display/intel_dp_mst.c +97 −59
  56. drivers/gpu/drm/i915/display/intel_dpll.c +35 −19
  57. drivers/gpu/drm/i915/display/intel_dpt.c +1 −1
  58. drivers/gpu/drm/i915/display/intel_drrs.c +1 −0
  59. drivers/gpu/drm/i915/display/intel_dsb.c +188 −29
  60. drivers/gpu/drm/i915/display/intel_dsb.h +8 −1
  61. drivers/gpu/drm/i915/display/intel_dsb_regs.h +31 −0
  62. drivers/gpu/drm/i915/display/intel_dvo.c +5 −6
  63. drivers/gpu/drm/i915/display/intel_fb.c +58 −3
  64. drivers/gpu/drm/i915/display/intel_fb_pin.c +2 −1
  65. drivers/gpu/drm/i915/display/intel_fbc.c +12 −11
  66. drivers/gpu/drm/i915/display/intel_fbc.h +2 −0
  67. drivers/gpu/drm/i915/display/intel_fdi.c +149 −20
  68. drivers/gpu/drm/i915/display/intel_fdi.h +8 −0
  69. drivers/gpu/drm/i915/display/intel_frontbuffer.c +32 −2
  70. drivers/gpu/drm/i915/display/intel_frontbuffer.h +4 −0
  71. drivers/gpu/drm/i915/display/intel_gmbus.c +4 −1
  72. drivers/gpu/drm/i915/display/intel_hdcp.c +14 −19
  73. drivers/gpu/drm/i915/display/intel_hdmi.c +39 −82
  74. drivers/gpu/drm/i915/display/intel_hotplug.c +78 −7
  75. drivers/gpu/drm/i915/display/intel_hotplug_irq.c +22 −2
  76. drivers/gpu/drm/i915/display/intel_link_bw.c +212 −0
  77. drivers/gpu/drm/i915/display/intel_link_bw.h +37 −0
  78. drivers/gpu/drm/i915/display/intel_lspcon.c +7 −7
  79. drivers/gpu/drm/i915/display/intel_lvds.c +18 −15
  80. drivers/gpu/drm/i915/display/intel_overlay.c +2 −0
  81. drivers/gpu/drm/i915/display/intel_panel.c +4 −13
  82. drivers/gpu/drm/i915/display/intel_plane_initial.c +1 −0
  83. drivers/gpu/drm/i915/display/intel_pmdemand.c +1 −1
  84. drivers/gpu/drm/i915/display/intel_psr.c +37 −15
  85. drivers/gpu/drm/i915/display/intel_sdvo.c +196 −185
  86. drivers/gpu/drm/i915/display/intel_sdvo_regs.h +1 −1
  87. drivers/gpu/drm/i915/display/intel_sprite.c +1 −0
  88. drivers/gpu/drm/i915/display/intel_tc.c +50 −16
  89. drivers/gpu/drm/i915/display/intel_tc.h +1 −2
  90. drivers/gpu/drm/i915/display/intel_vblank.c +14 −0
  91. drivers/gpu/drm/i915/display/intel_vblank.h +1 −0
  92. drivers/gpu/drm/i915/display/intel_vdsc.c +287 −343
  93. drivers/gpu/drm/i915/display/intel_vdsc_regs.h +126 −271
  94. drivers/gpu/drm/i915/display/intel_vrr.c +16 −2
  95. drivers/gpu/drm/i915/display/intel_vrr.h +1 −0
  96. drivers/gpu/drm/i915/display/skl_universal_plane.c +2 −5
  97. drivers/gpu/drm/i915/display/skl_watermark.c +24 −8
  98. drivers/gpu/drm/i915/display/skl_watermark.h +2 −0
  99. drivers/gpu/drm/i915/gem/i915_gem_clflush.c +1 −2
  100. drivers/gpu/drm/i915/gem/i915_gem_domain.c +1 −1
  101. drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +2 −2
  102. drivers/gpu/drm/i915/gem/i915_gem_object.c +1 −0
  103. drivers/gpu/drm/i915/gem/i915_gem_object.h +0 −89
  104. drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h +103 −0
  105. drivers/gpu/drm/i915/gem/i915_gem_phys.c +1 −0
  106. drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +15 −24
  107. drivers/gpu/drm/i915/gt/gen8_ppgtt.c +18 −18
  108. drivers/gpu/drm/i915/gt/intel_gtt.h +2 −2
  109. drivers/gpu/drm/i915/i915_driver.c +5 −5
  110. drivers/gpu/drm/i915/i915_driver.h +2 −2
  111. drivers/gpu/drm/i915/i915_drv.h +2 −16
  112. drivers/gpu/drm/i915/i915_gem.c +1 −1
  113. drivers/gpu/drm/i915/i915_getparam.c +1 −1
  114. drivers/gpu/drm/i915/i915_gpu_error.c +2 −2
  115. drivers/gpu/drm/i915/i915_irq.c +2 −0
  116. drivers/gpu/drm/i915/i915_pci.c +0 −1
  117. drivers/gpu/drm/i915/i915_reg.h +4 −277
  118. drivers/gpu/drm/i915/i915_vma.c +1 −0
  119. drivers/gpu/drm/i915/i915_vma_resource.c +1 −1
  120. drivers/gpu/drm/i915/intel_clock_gating.c +2 −50
  121. drivers/gpu/drm/i915/intel_device_info.c +0 −14
  122. drivers/gpu/drm/i915/intel_device_info.h +0 −1
  123. drivers/gpu/drm/i915/intel_gvt_mmio_table.c +1 −0
  124. drivers/gpu/drm/i915/intel_runtime_pm.c +0 −1
  125. drivers/gpu/drm/i915/intel_runtime_pm.h +2 −2
  126. drivers/gpu/drm/i915/intel_step.c +1 −0
  127. drivers/gpu/drm/i915/pxp/intel_pxp.c +33 −7
  128. drivers/gpu/drm/i915/pxp/intel_pxp.h +1 −1
  129. drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c +4 −3
  130. drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +17 −1
  131. drivers/gpu/drm/i915/pxp/intel_pxp_pm.h +3 −2
  132. drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +4 −3
  133. drivers/gpu/drm/i915/pxp/intel_pxp_types.h +9 −0
  134. drivers/gpu/drm/i915/selftests/mock_gem_device.c +2 −0
  135. drivers/gpu/drm/i915/soc/intel_pch.c +9 −3
  136. drivers/gpu/drm/i915/soc/intel_pch.h +2 −0
  137. drivers/media/cec/core/cec-adap.c +5 −0
  138. drivers/media/cec/core/cec-notifier.c +5 −0
  139. include/drm/display/drm_dp_helper.h +6 −0
  140. include/drm/drm_connector.h +8 −0
  141. include/drm/drm_edid.h +1 −0
  142. include/drm/i915_pciids.h +6 −2
drivers/gpu/drm/display/drm_dp_cec.c+20−3
@@ -14,6 +14,7 @@ · 13 unmodified lines
1414 #include <drm/display/drm_dp_helper.h>
1515 #include <drm/drm_connector.h>
1616 #include <drm/drm_device.h>
17+#include <drm/drm_edid.h>
1718
1819 /*
1920 * Unfortunately it turns out that we have a chicken-and-egg situation
@@ -297,7 +298,7 @@ static void drm_dp_cec_unregister_work(struct work_struct *work) · 277 unmodified lines
297298 * were unchanged and just update the CEC physical address. Otherwise
298299 * unregister the old CEC adapter and create a new one.
299300 */
300−void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid)
301+void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address)
301302 {
302303 struct drm_connector *connector = aux->cec.connector;
303304 u32 cec_caps = CEC_CAP_DEFAULTS | CEC_CAP_NEEDS_HPD |
@@ -339,7 +340,7 @@ void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid) · 35 unmodified lines
339340 if (aux->cec.adap->capabilities == cec_caps &&
340341 aux->cec.adap->available_log_addrs == num_las) {
341342 /* Unchanged, so just set the phys addr */
342− cec_s_phys_addr_from_edid(aux->cec.adap, edid);
343+ cec_s_phys_addr(aux->cec.adap, source_physical_address, false);
343344 goto unlock;
344345 }
345346 /*
@@ -370,11 +371,27 @@ void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid) · 24 unmodified lines
370371 * from drm_dp_cec_register_connector() edid == NULL, so in
371372 * that case the phys addr is just invalidated.
372373 */
373− cec_s_phys_addr_from_edid(aux->cec.adap, edid);
374+ cec_s_phys_addr(aux->cec.adap, source_physical_address, false);
374375 }
375376 unlock:
376377 mutex_unlock(&aux->cec.lock);
377378 }
379+EXPORT_SYMBOL(drm_dp_cec_attach);
380+
381+/*
382+ * Note: Prefer calling drm_dp_cec_attach() with
383+ * connector->display_info.source_physical_address if possible.
384+ */
385+void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid)
386+{
387+ u16 pa = CEC_PHYS_ADDR_INVALID;
388+
389+ if (edid && edid->extensions)
390+ pa = cec_get_edid_phys_addr((const u8 *)edid,
391+ EDID_LENGTH * (edid->extensions + 1), NULL);
392+
393+ drm_dp_cec_attach(aux, pa);
394+}
378395 EXPORT_SYMBOL(drm_dp_cec_set_edid);
379396
380397 /*
drivers/gpu/drm/display/drm_dp_helper.c+6−2
@@ -2449,12 +2449,16 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S · 2448 unmodified lines
24492449 int num_bpc = 0;
24502450 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
24512451
2452+ if (!drm_dp_sink_supports_dsc(dsc_dpcd))
2453+ return 0;
2454+
24522455 if (color_depth & DP_DSC_12_BPC)
24532456 dsc_bpc[num_bpc++] = 12;
24542457 if (color_depth & DP_DSC_10_BPC)
24552458 dsc_bpc[num_bpc++] = 10;
2456− if (color_depth & DP_DSC_8_BPC)
2457− dsc_bpc[num_bpc++] = 8;
2459+
2460+ /* A DP DSC Sink device shall support 8 bpc. */
2461+ dsc_bpc[num_bpc++] = 8;
24582462
24592463 return num_bpc;
24602464 }
drivers/gpu/drm/drm_connector.c+10−1
@@ -631,6 +631,10 @@ int drm_connector_register(struct drm_connector *connector) · 630 unmodified lines
631631 goto err_debugfs;
632632 }
633633
634+ ret = drm_sysfs_connector_add_late(connector);
635+ if (ret)
636+ goto err_late_register;
637+
634638 drm_mode_object_register(connector->dev, &connector->base);
635639
636640 connector->registration_state = DRM_CONNECTOR_REGISTERED;
@@ -647,6 +651,9 @@ int drm_connector_register(struct drm_connector *connector) · 10 unmodified lines
647651 mutex_unlock(&connector_list_lock);
648652 goto unlock;
649653
654+err_late_register:
655+ if (connector->funcs->early_unregister)
656+ connector->funcs->early_unregister(connector);
650657 err_debugfs:
651658 drm_debugfs_connector_remove(connector);
652659 drm_sysfs_connector_remove(connector);
@@ -681,11 +688,13 @@ void drm_connector_unregister(struct drm_connector *connector) · 28 unmodified lines
681688 connector->privacy_screen,
682689 &connector->privacy_screen_notifier);
683690
691+ drm_sysfs_connector_remove_early(connector);
692+
684693 if (connector->funcs->early_unregister)
685694 connector->funcs->early_unregister(connector);
686695
687− drm_sysfs_connector_remove(connector);
688696 drm_debugfs_connector_remove(connector);
697+ drm_sysfs_connector_remove(connector);
689698
690699 connector->registration_state = DRM_CONNECTOR_UNREGISTERED;
691700 mutex_unlock(&connector->mutex);
drivers/gpu/drm/drm_edid.c+20−2
@@ -29,6 +29,7 @@ · 28 unmodified lines
2929 */
3030
3131 #include <linux/bitfield.h>
32+#include <linux/cec.h>
3233 #include <linux/hdmi.h>
3334 #include <linux/i2c.h>
3435 #include <linux/kernel.h>
@@ -3110,7 +3111,7 @@ drm_monitor_supports_rb(const struct drm_edid *drm_edid) · 3075 unmodified lines
31103111 return ret;
31113112 }
31123113
3113− return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
3114+ return drm_edid_is_digital(drm_edid);
31143115 }
31153116
31163117 static void
@@ -6200,6 +6201,8 @@ drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) · 3083 unmodified lines
62006201
62016202 info->is_hdmi = true;
62026203
6204+ info->source_physical_address = (db[4] << 8) | db[5];
6205+
62036206 if (len >= 6)
62046207 info->dvi_dual = db[6] & 1;
62056208 if (len >= 7)
@@ -6478,6 +6481,8 @@ static void drm_reset_display_info(struct drm_connector *connector) · 272 unmodified lines
64786481 info->vics_len = 0;
64796482
64806483 info->quirks = 0;
6484+
6485+ info->source_physical_address = CEC_PHYS_ADDR_INVALID;
64816486 }
64826487
64836488 static void update_displayid_info(struct drm_connector *connector,
@@ -6527,7 +6532,7 @@ static void update_display_info(struct drm_connector *connector, · 43 unmodified lines
65276532 if (edid->revision < 3)
65286533 goto out;
65296534
6530− if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6535+ if (!drm_edid_is_digital(drm_edid))
65316536 goto out;
65326537
65336538 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
@@ -7343,3 +7348,16 @@ static void _drm_update_tile_info(struct drm_connector *connector, · 809 unmodified lines
73437348 connector->tile_group = NULL;
73447349 }
73457350 }
7351+
7352+/**
7353+ * drm_edid_is_digital - is digital?
7354+ * @drm_edid: The EDID
7355+ *
7356+ * Return true if input is digital.
7357+ */
7358+bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7359+{
7360+ return drm_edid && drm_edid->edid &&
7361+ drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7362+}
7363+EXPORT_SYMBOL(drm_edid_is_digital);
drivers/gpu/drm/drm_internal.h+2−0
@@ -153,6 +153,8 @@ int drm_sysfs_init(void); · 152 unmodified lines
153153 void drm_sysfs_destroy(void);
154154 struct device *drm_sysfs_minor_alloc(struct drm_minor *minor);
155155 int drm_sysfs_connector_add(struct drm_connector *connector);
156+int drm_sysfs_connector_add_late(struct drm_connector *connector);
157+void drm_sysfs_connector_remove_early(struct drm_connector *connector);
156158 void drm_sysfs_connector_remove(struct drm_connector *connector);
157159
158160 void drm_sysfs_lease_event(struct drm_device *dev);
drivers/gpu/drm/drm_sysfs.c+15−7
@@ -400,10 +400,6 @@ int drm_sysfs_connector_add(struct drm_connector *connector) · 399 unmodified lines
400400 drm_err(dev, "failed to add component to create link to typec connector\n");
401401 }
402402
403− if (connector->ddc)
404− return sysfs_create_link(&connector->kdev->kobj,
405− &connector->ddc->dev.kobj, "ddc");
406−
407403 return 0;
408404
409405 err_free:
@@ -411,13 +407,25 @@ err_free: · 1 unmodified line
411407 return r;
412408 }
413409
414−void drm_sysfs_connector_remove(struct drm_connector *connector)
410+int drm_sysfs_connector_add_late(struct drm_connector *connector)
415411 {
416− if (!connector->kdev)
417− return;
412+ if (connector->ddc)
413+ return sysfs_create_link(&connector->kdev->kobj,
414+ &connector->ddc->dev.kobj, "ddc");
415+
416+ return 0;
417+}
418418
419+void drm_sysfs_connector_remove_early(struct drm_connector *connector)
420+{
419421 if (connector->ddc)
420422 sysfs_remove_link(&connector->kdev->kobj, "ddc");
423+}
424+
425+void drm_sysfs_connector_remove(struct drm_connector *connector)
426+{
427+ if (!connector->kdev)
428+ return;
421429
422430 if (dev_fwnode(connector->kdev))
423431 component_del(connector->kdev, &typec_connector_ops);
drivers/gpu/drm/i915/Makefile+2−0
@@ -248,6 +248,7 @@ i915-y += \ · 247 unmodified lines
248248 display/intel_display_power_well.o \
249249 display/intel_display_reset.o \
250250 display/intel_display_rps.o \
251+ display/intel_display_wa.o \
251252 display/intel_dmc.o \
252253 display/intel_dpio_phy.o \
253254 display/intel_dpll.o \
@@ -267,6 +268,7 @@ i915-y += \ · 13 unmodified lines
267268 display/intel_hotplug.o \
268269 display/intel_hotplug_irq.o \
269270 display/intel_hti.o \
271+ display/intel_link_bw.o \
270272 display/intel_load_detect.o \
271273 display/intel_lpe_audio.o \
272274 display/intel_modeset_lock.o \
drivers/gpu/drm/i915/display/g4x_dp.c+8−2
@@ -141,7 +141,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, · 140 unmodified lines
141141
142142 intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),
143143 TRANS_DP_ENH_FRAMING,
144− drm_dp_enhanced_frame_cap(intel_dp->dpcd) ?
144+ pipe_config->enhanced_framing ?
145145 TRANS_DP_ENH_FRAMING : 0);
146146 } else {
147147 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
@@ -153,7 +153,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, · 5 unmodified lines
153153 intel_dp->DP |= DP_SYNC_VS_HIGH;
154154 intel_dp->DP |= DP_LINK_TRAIN_OFF;
155155
156− if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
156+ if (pipe_config->enhanced_framing)
157157 intel_dp->DP |= DP_ENHANCED_FRAMING;
158158
159159 if (IS_CHERRYVIEW(dev_priv))
@@ -351,6 +351,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder, · 191 unmodified lines
351351 u32 trans_dp = intel_de_read(dev_priv,
352352 TRANS_DP_CTL(crtc->pipe));
353353
354+ if (trans_dp & TRANS_DP_ENH_FRAMING)
355+ pipe_config->enhanced_framing = true;
356+
354357 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
355358 flags |= DRM_MODE_FLAG_PHSYNC;
356359 else
@@ -361,6 +364,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder, · 4 unmodified lines
361364 else
362365 flags |= DRM_MODE_FLAG_NVSYNC;
363366 } else {
367+ if (tmp & DP_ENHANCED_FRAMING)
368+ pipe_config->enhanced_framing = true;
369+
364370 if (tmp & DP_SYNC_HS_HIGH)
365371 flags |= DRM_MODE_FLAG_PHSYNC;
366372 else
drivers/gpu/drm/i915/display/g4x_hdmi.c+5−1
@@ -16,6 +16,7 @@ · 15 unmodified lines
1616 #include "intel_display_types.h"
1717 #include "intel_dp_aux.h"
1818 #include "intel_dpio_phy.h"
19+#include "intel_fdi.h"
1920 #include "intel_fifo_underrun.h"
2021 #include "intel_hdmi.h"
2122 #include "intel_hotplug.h"
@@ -133,8 +134,11 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder, · 111 unmodified lines
133134 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
134135 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
135136
136− if (HAS_PCH_SPLIT(i915))
137+ if (HAS_PCH_SPLIT(i915)) {
137138 crtc_state->has_pch_encoder = true;
139+ if (!intel_fdi_compute_pipe_bpp(crtc_state))
140+ return -EINVAL;
141+ }
138142
139143 if (IS_G4X(i915))
140144 crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
drivers/gpu/drm/i915/display/hsw_ips.c+1−0
@@ -6,6 +6,7 @@ · 5 unmodified lines
66 #include "hsw_ips.h"
77 #include "i915_drv.h"
88 #include "i915_reg.h"
9+#include "intel_color_regs.h"
910 #include "intel_de.h"
1011 #include "intel_display_types.h"
1112 #include "intel_pcode.h"
drivers/gpu/drm/i915/display/i9xx_plane.c+1−0
@@ -17,6 +17,7 @@ · 16 unmodified lines
1717 #include "intel_display_types.h"
1818 #include "intel_fb.h"
1919 #include "intel_fbc.h"
20+#include "intel_frontbuffer.h"
2021 #include "intel_sprite.h"
2122
2223 /* Primary plane formats for gen <= 3 */
drivers/gpu/drm/i915/display/icl_dsi.c+1−12
@@ -1822,7 +1822,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) · 1821 unmodified lines
18221822 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
18231823 u32 ths_prepare_ns, tclk_trail_ns;
18241824 u32 hs_zero_cnt;
1825− u32 tclk_pre_cnt, tclk_post_cnt;
1825+ u32 tclk_pre_cnt;
18261826
18271827 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
18281828
@@ -1869,15 +1869,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) · 40 unmodified lines
18691869 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
18701870 }
18711871
1872− /* tclk post count in escape clocks */
1873− tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1874− if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1875− drm_dbg_kms(&dev_priv->drm,
1876− "tclk_post_cnt out of range (%d)\n",
1877− tclk_post_cnt);
1878− tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1879− }
1880−
18811872 /* hs zero cnt in escape clocks */
18821873 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
18831874 ths_prepare_ns, tlpx_ns);
@@ -1903,8 +1894,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) · 19 unmodified lines
19031894 CLK_ZERO(clk_zero_cnt) |
19041895 CLK_PRE_OVERRIDE |
19051896 CLK_PRE(tclk_pre_cnt) |
1906− CLK_POST_OVERRIDE |
1907− CLK_POST(tclk_post_cnt) |
19081897 CLK_TRAIL_OVERRIDE |
19091898 CLK_TRAIL(trail_cnt));
19101899
drivers/gpu/drm/i915/display/intel_atomic.c+2−0
@@ -259,6 +259,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) · 258 unmodified lines
259259 drm_property_blob_get(crtc_state->post_csc_lut);
260260
261261 crtc_state->update_pipe = false;
262+ crtc_state->update_m_n = false;
263+ crtc_state->update_lrr = false;
262264 crtc_state->disable_lp_wm = false;
263265 crtc_state->disable_cxsr = false;
264266 crtc_state->update_wm_pre = false;
drivers/gpu/drm/i915/display/intel_atomic_plane.c+11−3
@@ -214,9 +214,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, · 213 unmodified lines
214214 int width, height;
215215 unsigned int rel_data_rate;
216216
217− if (plane->id == PLANE_CURSOR)
218− return 0;
219−
220217 if (!plane_state->uapi.visible)
221218 return 0;
222219
@@ -244,6 +241,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, · 21 unmodified lines
244241
245242 rel_data_rate = width * height * fb->format->cpp[color_plane];
246243
244+ if (plane->id == PLANE_CURSOR)
245+ return rel_data_rate;
246+
247247 return intel_adjusted_rate(&plane_state->uapi.src,
248248 &plane_state->uapi.dst,
249249 rel_data_rate);
@@ -981,6 +981,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) · 731 unmodified lines
981981 if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
982982 hsub = 2;
983983 vsub = 2;
984+ } else if (DISPLAY_VER(i915) >= 20 &&
985+ intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
986+ /*
987+ * This allows NV12 and P0xx formats to have odd size and/or odd
988+ * source coordinates on DISPLAY_VER(i915) >= 20
989+ */
990+ hsub = 1;
991+ vsub = 1;
984992 } else {
985993 hsub = fb->format->hsub;
986994 vsub = fb->format->vsub;
drivers/gpu/drm/i915/display/intel_audio.c+3−3
@@ -759,10 +759,10 @@ static void ibx_audio_codec_enable(struct intel_encoder *encoder, · 758 unmodified lines
759759 mutex_unlock(&i915->display.audio.mutex);
760760 }
761761
762−void intel_audio_sdp_split_update(struct intel_encoder *encoder,
763− const struct intel_crtc_state *crtc_state)
762+void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state)
764763 {
765− struct drm_i915_private *i915 = to_i915(encoder->base.dev);
764+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
765+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
766766 enum transcoder trans = crtc_state->cpu_transcoder;
767767
768768 if (HAS_DP20(i915))
drivers/gpu/drm/i915/display/intel_audio.h+1−2
@@ -29,7 +29,6 @@ void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv); · 28 unmodified lines
2929 void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv);
3030 void intel_audio_init(struct drm_i915_private *dev_priv);
3131 void intel_audio_deinit(struct drm_i915_private *dev_priv);
32−void intel_audio_sdp_split_update(struct intel_encoder *encoder,
33− const struct intel_crtc_state *crtc_state);
32+void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state);
3433
3534 #endif /* __INTEL_AUDIO_H__ */
drivers/gpu/drm/i915/display/intel_bios.c+17−9
@@ -521,7 +521,8 @@ static void init_bdb_blocks(struct drm_i915_private *i915, · 520 unmodified lines
521521 }
522522
523523 static void
524−fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
524+fill_detail_timing_data(struct drm_i915_private *i915,
525+ struct drm_display_mode *panel_fixed_mode,
525526 const struct lvds_dvo_timing *dvo_timing)
526527 {
527528 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
@@ -561,11 +562,17 @@ fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, · 33 unmodified lines
561562 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |
562563 dvo_timing->vimage_lo;
563564
564− /* Some VBTs have bogus h/vtotal values */
565− if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
566− panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
567− if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
568− panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
565+ /* Some VBTs have bogus h/vsync_end values */
566+ if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) {
567+ drm_dbg_kms(&i915->drm, "reducing hsync_end %d->%d\n",
568+ panel_fixed_mode->hsync_end, panel_fixed_mode->htotal);
569+ panel_fixed_mode->hsync_end = panel_fixed_mode->htotal;
570+ }
571+ if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) {
572+ drm_dbg_kms(&i915->drm, "reducing vsync_end %d->%d\n",
573+ panel_fixed_mode->vsync_end, panel_fixed_mode->vtotal);
574+ panel_fixed_mode->vsync_end = panel_fixed_mode->vtotal;
575+ }
569576
570577 drm_mode_set_name(panel_fixed_mode);
571578 }
@@ -849,7 +856,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915, · 277 unmodified lines
849856 if (!panel_fixed_mode)
850857 return;
851858
852− fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
859+ fill_detail_timing_data(i915, panel_fixed_mode, panel_dvo_timing);
853860
854861 panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
855862
@@ -1134,7 +1141,7 @@ parse_sdvo_panel_data(struct drm_i915_private *i915, · 278 unmodified lines
11341141 if (!panel_fixed_mode)
11351142 return;
11361143
1137− fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]);
1144+ fill_detail_timing_data(i915, panel_fixed_mode, &dtds->dtds[index]);
11381145
11391146 panel->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
11401147
@@ -2194,7 +2201,8 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) · 1053 unmodified lines
21942201 const u8 *ddc_pin_map;
21952202 int i, n_entries;
21962203
2197− if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
2204+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
2205+ IS_ALDERLAKE_P(i915)) {
21982206 ddc_pin_map = adlp_ddc_pin_map;
21992207 n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
22002208 } else if (IS_ALDERLAKE_S(i915)) {
drivers/gpu/drm/i915/display/intel_cdclk.c+86−21
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include "intel_cdclk.h"
3333 #include "intel_crtc.h"
3434 #include "intel_de.h"
35+#include "intel_dp.h"
3536 #include "intel_display_types.h"
3637 #include "intel_mchbar_regs.h"
3738 #include "intel_pci_config.h"
@@ -1381,6 +1382,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = { · 1343 unmodified lines
13811382 {}
13821383 };
13831384
1385+static const struct intel_cdclk_vals lnl_cdclk_table[] = {
1386+ { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
1387+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1388+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1389+ { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
1390+ { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
1391+ { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
1392+ { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
1393+ { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
1394+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
1395+ { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
1396+ { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
1397+ { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
1398+ { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
1399+ { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
1400+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
1401+ { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
1402+ { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
1403+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
1404+ { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1405+ { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1406+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1407+ {}
1408+};
1409+
13841410 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
13851411 {
13861412 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -1840,9 +1866,10 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 · 453 unmodified lines
18401866
18411867 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
18421868 {
1843− return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
1844− dev_priv->display.cdclk.hw.vco > 0 &&
1845− HAS_CDCLK_SQUASH(dev_priv));
1869+ return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
1870+ DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
1871+ IS_DG2(dev_priv)) &&
1872+ dev_priv->display.cdclk.hw.vco > 0;
18461873 }
18471874
18481875 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
@@ -1879,8 +1906,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, · 30 unmodified lines
18791906 dg2_cdclk_squash_program(dev_priv, waveform);
18801907
18811908 val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
1882− bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
1883− skl_cdclk_decimal(cdclk);
1909+ bxt_cdclk_cd2x_pipe(dev_priv, pipe);
18841910
18851911 /*
18861912 * Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1889,6 +1915,12 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, · 2 unmodified lines
18891915 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
18901916 cdclk >= 500000)
18911917 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1918+
1919+ if (DISPLAY_VER(dev_priv) >= 20)
1920+ val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
1921+ else
1922+ val |= skl_cdclk_decimal(cdclk);
1923+
18921924 intel_de_write(dev_priv, CDCLK_CTL, val);
18931925
18941926 if (pipe != INVALID_PIPE)
@@ -2533,6 +2565,48 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) · 638 unmodified lines
25332565 return min_cdclk;
25342566 }
25352567
2568+static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
2569+{
2570+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2571+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2572+ int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
2573+ int min_cdclk = 0;
2574+
2575+ /*
2576+ * When we decide to use only one VDSC engine, since
2577+ * each VDSC operates with 1 ppc throughput, pixel clock
2578+ * cannot be higher than the VDSC clock (cdclk)
2579+ * If there 2 VDSC engines, then pixel clock can't be higher than
2580+ * VDSC clock(cdclk) * 2 and so on.
2581+ */
2582+ min_cdclk = max_t(int, min_cdclk,
2583+ DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
2584+
2585+ if (crtc_state->bigjoiner_pipes) {
2586+ int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
2587+
2588+ /*
2589+ * According to Bigjoiner bw check:
2590+ * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
2591+ *
2592+ * We have already computed compressed_bpp, so now compute the min CDCLK that
2593+ * is required to support this compressed_bpp.
2594+ *
2595+ * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
2596+ *
2597+ * Since PPC = 2 with bigjoiner
2598+ * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
2599+ */
2600+ int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
2601+ int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
2602+ (2 * bigjoiner_interface_bits);
2603+
2604+ min_cdclk = max(min_cdclk, min_cdclk_bj);
2605+ }
2606+
2607+ return min_cdclk;
2608+}
2609+
25362610 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
25372611 {
25382612 struct drm_i915_private *dev_priv =
@@ -2604,20 +2678,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) · 65 unmodified lines
26042678 /* Account for additional needs from the planes */
26052679 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
26062680
2607− /*
2608− * When we decide to use only one VDSC engine, since
2609− * each VDSC operates with 1 ppc throughput, pixel clock
2610− * cannot be higher than the VDSC clock (cdclk)
2611− * If there 2 VDSC engines, then pixel clock can't be higher than
2612− * VDSC clock(cdclk) * 2 and so on.
2613− */
2614− if (crtc_state->dsc.compression_enable) {
2615− int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
2616−
2617− min_cdclk = max_t(int, min_cdclk,
2618− DIV_ROUND_UP(crtc_state->pixel_rate,
2619− num_vdsc_instances));
2620− }
2681+ if (crtc_state->dsc.compression_enable)
2682+ min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
26212683
26222684 /*
26232685 * HACK. Currently for TGL/DG2 platforms we calculate
@@ -3108,7 +3170,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) · 484 unmodified lines
31083170 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
31093171 &new_cdclk_state->actual)) {
31103172 /* All pipes must be switched off while we change the cdclk. */
3111− ret = intel_modeset_all_pipes(state, "CDCLK change");
3173+ ret = intel_modeset_all_pipes_late(state, "CDCLK change");
31123174 if (ret)
31133175 return ret;
31143176
@@ -3559,7 +3621,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = { · 444 unmodified lines
35593621 */
35603622 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
35613623 {
3562− if (IS_METEORLAKE(dev_priv)) {
3624+ if (DISPLAY_VER(dev_priv) >= 20) {
3625+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3626+ dev_priv->display.cdclk.table = lnl_cdclk_table;
3627+ } else if (DISPLAY_VER(dev_priv) >= 14) {
35633628 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
35643629 dev_priv->display.cdclk.table = mtl_cdclk_table;
35653630 } else if (IS_DG2(dev_priv)) {
drivers/gpu/drm/i915/display/intel_color.c+142−12
@@ -24,6 +24,7 @@ · 23 unmodified lines
2424
2525 #include "i915_reg.h"
2626 #include "intel_color.h"
27+#include "intel_color_regs.h"
2728 #include "intel_de.h"
2829 #include "intel_display_types.h"
2930 #include "intel_dsb.h"
@@ -75,6 +76,10 @@ struct intel_color_funcs { · 45 unmodified lines
7576 * software state. Used by eg. the hardware state checker.
7677 */
7778 void (*read_csc)(struct intel_crtc_state *crtc_state);
79+ /*
80+ * Read config other than LUTs and CSCs, before them. Optional.
81+ */
82+ void (*get_config)(struct intel_crtc_state *crtc_state);
7883 };
7984
8085 #define CTM_COEFF_SIGN (1ULL << 63)
@@ -1013,6 +1018,65 @@ static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state) · 932 unmodified lines
10131018 crtc_state->csc_mode);
10141019 }
10151020
1021+static u32 hsw_read_gamma_mode(struct intel_crtc *crtc)
1022+{
1023+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1024+
1025+ return intel_de_read(i915, GAMMA_MODE(crtc->pipe));
1026+}
1027+
1028+static u32 ilk_read_csc_mode(struct intel_crtc *crtc)
1029+{
1030+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1031+
1032+ return intel_de_read(i915, PIPE_CSC_MODE(crtc->pipe));
1033+}
1034+
1035+static void i9xx_get_config(struct intel_crtc_state *crtc_state)
1036+{
1037+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1038+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1039+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1041+ u32 tmp;
1042+
1043+ tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
1044+
1045+ if (tmp & DISP_PIPE_GAMMA_ENABLE)
1046+ crtc_state->gamma_enable = true;
1047+
1048+ if (!HAS_GMCH(dev_priv) && tmp & DISP_PIPE_CSC_ENABLE)
1049+ crtc_state->csc_enable = true;
1050+}
1051+
1052+static void hsw_get_config(struct intel_crtc_state *crtc_state)
1053+{
1054+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1055+
1056+ crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
1057+ crtc_state->csc_mode = ilk_read_csc_mode(crtc);
1058+
1059+ i9xx_get_config(crtc_state);
1060+}
1061+
1062+static void skl_get_config(struct intel_crtc_state *crtc_state)
1063+{
1064+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1065+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1066+ u32 tmp;
1067+
1068+ crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
1069+ crtc_state->csc_mode = ilk_read_csc_mode(crtc);
1070+
1071+ tmp = intel_de_read(i915, SKL_BOTTOM_COLOR(crtc->pipe));
1072+
1073+ if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
1074+ crtc_state->gamma_enable = true;
1075+
1076+ if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
1077+ crtc_state->csc_enable = true;
1078+}
1079+
10161080 static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
10171081 {
10181082 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1265,9 +1329,20 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, · 246 unmodified lines
12651329
12661330 lut = blob->data;
12671331
1332+ /*
1333+ * DSB fails to correctly load the legacy LUT
1334+ * unless we either write each entry twice,
1335+ * or use non-posted writes
1336+ */
1337+ if (crtc_state->dsb)
1338+ intel_dsb_nonpost_start(crtc_state->dsb);
1339+
12681340 for (i = 0; i < 256; i++)
12691341 ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
12701342 i9xx_lut_8(&lut[i]));
1343+
1344+ if (crtc_state->dsb)
1345+ intel_dsb_nonpost_end(crtc_state->dsb);
12711346 }
12721347
12731348 static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
@@ -1677,12 +1752,6 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) · 403 unmodified lines
16771752 MISSING_CASE(crtc_state->gamma_mode);
16781753 break;
16791754 }
1680−
1681− if (crtc_state->dsb) {
1682− intel_dsb_finish(crtc_state->dsb);
1683− intel_dsb_commit(crtc_state->dsb, false);
1684− intel_dsb_wait(crtc_state->dsb);
1685− }
16861755 }
16871756
16881757 static void vlv_load_luts(const struct intel_crtc_state *crtc_state)
@@ -1789,6 +1858,9 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state) · 100 unmodified lines
17891858 {
17901859 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
17911860
1861+ if (crtc_state->dsb)
1862+ return;
1863+
17921864 i915->display.funcs.color->load_luts(crtc_state);
17931865 }
17941866
@@ -1805,6 +1877,9 @@ void intel_color_commit_arm(const struct intel_crtc_state *crtc_state) · 10 unmodified lines
18051877 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
18061878
18071879 i915->display.funcs.color->color_commit_arm(crtc_state);
1880+
1881+ if (crtc_state->dsb)
1882+ intel_dsb_commit(crtc_state->dsb, true);
18081883 }
18091884
18101885 void intel_color_post_update(const struct intel_crtc_state *crtc_state)
@@ -1818,14 +1893,25 @@ void intel_color_post_update(const struct intel_crtc_state *crtc_state) · 7 unmodified lines
18181893 void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
18191894 {
18201895 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1896+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
18211897
18221898 /* FIXME DSB has issues loading LUTs, disable it for now */
18231899 return;
18241900
1901+ if (!crtc_state->hw.active ||
1902+ intel_crtc_needs_modeset(crtc_state))
1903+ return;
1904+
18251905 if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
18261906 return;
18271907
1828− crtc_state->dsb = intel_dsb_prepare(crtc, 1024);
1908+ crtc_state->dsb = intel_dsb_prepare(crtc_state, 1024);
1909+ if (!crtc_state->dsb)
1910+ return;
1911+
1912+ i915->display.funcs.color->load_luts(crtc_state);
1913+
1914+ intel_dsb_finish(crtc_state->dsb);
18291915 }
18301916
18311917 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
@@ -1837,6 +1923,17 @@ void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) · 5 unmodified lines
18371923 crtc_state->dsb = NULL;
18381924 }
18391925
1926+void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
1927+{
1928+ if (crtc_state->dsb)
1929+ intel_dsb_wait(crtc_state->dsb);
1930+}
1931+
1932+bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
1933+{
1934+ return crtc_state->dsb;
1935+}
1936+
18401937 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
18411938 {
18421939 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
@@ -1891,6 +1988,9 @@ void intel_color_get_config(struct intel_crtc_state *crtc_state) · 48 unmodified lines
18911988 {
18921989 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
18931990
1991+ if (i915->display.funcs.color->get_config)
1992+ i915->display.funcs.color->get_config(crtc_state);
1993+
18941994 i915->display.funcs.color->read_luts(crtc_state);
18951995
18961996 if (i915->display.funcs.color->read_csc)
@@ -2865,16 +2965,16 @@ static int icl_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) · 968 unmodified lines
28652965 return 16;
28662966 }
28672967
2868−static bool err_check(struct drm_color_lut *lut1,
2869− struct drm_color_lut *lut2, u32 err)
2968+static bool err_check(const struct drm_color_lut *lut1,
2969+ const struct drm_color_lut *lut2, u32 err)
28702970 {
28712971 return ((abs((long)lut2->red - lut1->red)) <= err) &&
28722972 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
28732973 ((abs((long)lut2->green - lut1->green)) <= err);
28742974 }
28752975
2876−static bool intel_lut_entries_equal(struct drm_color_lut *lut1,
2877− struct drm_color_lut *lut2,
2976+static bool intel_lut_entries_equal(const struct drm_color_lut *lut1,
2977+ const struct drm_color_lut *lut2,
28782978 int lut_size, u32 err)
28792979 {
28802980 int i;
@@ -2891,7 +2991,7 @@ static bool intel_lut_equal(const struct drm_property_blob *blob1, · 10 unmodified lines
28912991 const struct drm_property_blob *blob2,
28922992 int check_size, int precision)
28932993 {
2894− struct drm_color_lut *lut1, *lut2;
2994+ const struct drm_color_lut *lut1, *lut2;
28952995 int lut_size1, lut_size2;
28962996 u32 err;
28972997
@@ -3204,6 +3304,16 @@ static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) · 306 unmodified lines
32043304 return blob;
32053305 }
32063306
3307+static void chv_get_config(struct intel_crtc_state *crtc_state)
3308+{
3309+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3310+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3311+
3312+ crtc_state->cgm_mode = intel_de_read(i915, CGM_PIPE_MODE(crtc->pipe));
3313+
3314+ i9xx_get_config(crtc_state);
3315+}
3316+
32073317 static void chv_read_luts(struct intel_crtc_state *crtc_state)
32083318 {
32093319 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -3267,6 +3377,15 @@ static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) · 57 unmodified lines
32673377 return blob;
32683378 }
32693379
3380+static void ilk_get_config(struct intel_crtc_state *crtc_state)
3381+{
3382+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3383+
3384+ crtc_state->csc_mode = ilk_read_csc_mode(crtc);
3385+
3386+ i9xx_get_config(crtc_state);
3387+}
3388+
32703389 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
32713390 {
32723391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -3573,6 +3692,7 @@ static const struct intel_color_funcs chv_color_funcs = { · 300 unmodified lines
35733692 .read_luts = chv_read_luts,
35743693 .lut_equal = chv_lut_equal,
35753694 .read_csc = chv_read_csc,
3695+ .get_config = chv_get_config,
35763696 };
35773697
35783698 static const struct intel_color_funcs vlv_color_funcs = {
@@ -3590,6 +3710,7 @@ static const struct intel_color_funcs i965_color_funcs = { · 11 unmodified lines
35903710 .load_luts = i965_load_luts,
35913711 .read_luts = i965_read_luts,
35923712 .lut_equal = i965_lut_equal,
3713+ .get_config = i9xx_get_config,
35933714 };
35943715
35953716 static const struct intel_color_funcs i9xx_color_funcs = {
@@ -3598,6 +3719,7 @@ static const struct intel_color_funcs i9xx_color_funcs = { · 2 unmodified lines
35983719 .load_luts = i9xx_load_luts,
35993720 .read_luts = i9xx_read_luts,
36003721 .lut_equal = i9xx_lut_equal,
3722+ .get_config = i9xx_get_config,
36013723 };
36023724
36033725 static const struct intel_color_funcs tgl_color_funcs = {
@@ -3608,6 +3730,7 @@ static const struct intel_color_funcs tgl_color_funcs = { · 4 unmodified lines
36083730 .read_luts = icl_read_luts,
36093731 .lut_equal = icl_lut_equal,
36103732 .read_csc = icl_read_csc,
3733+ .get_config = skl_get_config,
36113734 };
36123735
36133736 static const struct intel_color_funcs icl_color_funcs = {
@@ -3619,6 +3742,7 @@ static const struct intel_color_funcs icl_color_funcs = { · 5 unmodified lines
36193742 .read_luts = icl_read_luts,
36203743 .lut_equal = icl_lut_equal,
36213744 .read_csc = icl_read_csc,
3745+ .get_config = skl_get_config,
36223746 };
36233747
36243748 static const struct intel_color_funcs glk_color_funcs = {
@@ -3629,6 +3753,7 @@ static const struct intel_color_funcs glk_color_funcs = { · 4 unmodified lines
36293753 .read_luts = glk_read_luts,
36303754 .lut_equal = glk_lut_equal,
36313755 .read_csc = skl_read_csc,
3756+ .get_config = skl_get_config,
36323757 };
36333758
36343759 static const struct intel_color_funcs skl_color_funcs = {
@@ -3639,6 +3764,7 @@ static const struct intel_color_funcs skl_color_funcs = { · 4 unmodified lines
36393764 .read_luts = bdw_read_luts,
36403765 .lut_equal = ivb_lut_equal,
36413766 .read_csc = skl_read_csc,
3767+ .get_config = skl_get_config,
36423768 };
36433769
36443770 static const struct intel_color_funcs bdw_color_funcs = {
@@ -3649,6 +3775,7 @@ static const struct intel_color_funcs bdw_color_funcs = { · 4 unmodified lines
36493775 .read_luts = bdw_read_luts,
36503776 .lut_equal = ivb_lut_equal,
36513777 .read_csc = ilk_read_csc,
3778+ .get_config = hsw_get_config,
36523779 };
36533780
36543781 static const struct intel_color_funcs hsw_color_funcs = {
@@ -3659,6 +3786,7 @@ static const struct intel_color_funcs hsw_color_funcs = { · 4 unmodified lines
36593786 .read_luts = ivb_read_luts,
36603787 .lut_equal = ivb_lut_equal,
36613788 .read_csc = ilk_read_csc,
3789+ .get_config = hsw_get_config,
36623790 };
36633791
36643792 static const struct intel_color_funcs ivb_color_funcs = {
@@ -3669,6 +3797,7 @@ static const struct intel_color_funcs ivb_color_funcs = { · 4 unmodified lines
36693797 .read_luts = ivb_read_luts,
36703798 .lut_equal = ivb_lut_equal,
36713799 .read_csc = ilk_read_csc,
3800+ .get_config = ilk_get_config,
36723801 };
36733802
36743803 static const struct intel_color_funcs ilk_color_funcs = {
@@ -3679,6 +3808,7 @@ static const struct intel_color_funcs ilk_color_funcs = { · 4 unmodified lines
36793808 .read_luts = ilk_read_luts,
36803809 .lut_equal = ilk_lut_equal,
36813810 .read_csc = ilk_read_csc,
3811+ .get_config = ilk_get_config,
36823812 };
36833813
36843814 void intel_color_crtc_init(struct intel_crtc *crtc)
drivers/gpu/drm/i915/display/intel_color.h+2−0
@@ -19,6 +19,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc); · 18 unmodified lines
1919 int intel_color_check(struct intel_crtc_state *crtc_state);
2020 void intel_color_prepare_commit(struct intel_crtc_state *crtc_state);
2121 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state);
22+bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state);
23+void intel_color_wait_commit(const struct intel_crtc_state *crtc_state);
2224 void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state);
2325 void intel_color_commit_arm(const struct intel_crtc_state *crtc_state);
2426 void intel_color_post_update(const struct intel_crtc_state *crtc_state);
drivers/gpu/drm/i915/display/intel_color_regs.h+286−0
@@ -0,0 +1,286 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2023 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_COLOR_REGS_H__
7+#define __INTEL_COLOR_REGS_H__
8+
9+#include "intel_display_reg_defs.h"
10+
11+/* legacy palette */
12+#define _LGC_PALETTE_A 0x4a000
13+#define _LGC_PALETTE_B 0x4a800
14+/* see PALETTE_* for the bits */
15+#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
16+
17+/* ilk/snb precision palette */
18+#define _PREC_PALETTE_A 0x4b000
19+#define _PREC_PALETTE_B 0x4c000
20+/* 10bit mode */
21+#define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20)
22+#define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10)
23+#define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0)
24+/* 12.4 interpolated mode ldw */
25+#define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24)
26+#define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14)
27+#define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4)
28+/* 12.4 interpolated mode udw */
29+#define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20)
30+#define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10)
31+#define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0)
32+#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
33+
34+#define _PREC_PIPEAGCMAX 0x4d000
35+#define _PREC_PIPEBGCMAX 0x4d010
36+#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */
37+
38+#define _GAMMA_MODE_A 0x4a480
39+#define _GAMMA_MODE_B 0x4ac80
40+#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
41+#define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */
42+#define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */
43+#define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */
44+#define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0)
45+#define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0)
46+#define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1)
47+#define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2)
48+#define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */
49+#define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */
50+
51+/* pipe CSC */
52+#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
53+#define _PIPE_A_CSC_COEFF_BY 0x49014
54+#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
55+#define _PIPE_A_CSC_COEFF_BU 0x4901c
56+#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
57+#define _PIPE_A_CSC_COEFF_BV 0x49024
58+
59+#define _PIPE_A_CSC_MODE 0x49028
60+#define ICL_CSC_ENABLE (1 << 31) /* icl+ */
61+#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
62+#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
63+#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
64+#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
65+
66+#define _PIPE_A_CSC_PREOFF_HI 0x49030
67+#define _PIPE_A_CSC_PREOFF_ME 0x49034
68+#define _PIPE_A_CSC_PREOFF_LO 0x49038
69+#define _PIPE_A_CSC_POSTOFF_HI 0x49040
70+#define _PIPE_A_CSC_POSTOFF_ME 0x49044
71+#define _PIPE_A_CSC_POSTOFF_LO 0x49048
72+
73+#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
74+#define _PIPE_B_CSC_COEFF_BY 0x49114
75+#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
76+#define _PIPE_B_CSC_COEFF_BU 0x4911c
77+#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
78+#define _PIPE_B_CSC_COEFF_BV 0x49124
79+#define _PIPE_B_CSC_MODE 0x49128
80+#define _PIPE_B_CSC_PREOFF_HI 0x49130
81+#define _PIPE_B_CSC_PREOFF_ME 0x49134
82+#define _PIPE_B_CSC_PREOFF_LO 0x49138
83+#define _PIPE_B_CSC_POSTOFF_HI 0x49140
84+#define _PIPE_B_CSC_POSTOFF_ME 0x49144
85+#define _PIPE_B_CSC_POSTOFF_LO 0x49148
86+
87+#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
88+#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
89+#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
90+#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
91+#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
92+#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
93+#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
94+#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
95+#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
96+#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
97+#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
98+#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
99+#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
100+
101+/* Pipe Output CSC */
102+#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
103+#define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
104+#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
105+#define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
106+#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
107+#define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
108+#define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
109+#define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
110+#define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
111+#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
112+#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
113+#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
114+
115+#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
116+#define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
117+#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
118+#define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
119+#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
120+#define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
121+#define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
122+#define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
123+#define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
124+#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
125+#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
126+#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
127+
128+#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
129+ _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
130+ _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
131+#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
132+ _PIPE_A_OUTPUT_CSC_COEFF_BY, \
133+ _PIPE_B_OUTPUT_CSC_COEFF_BY)
134+#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
135+ _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
136+ _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
137+#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
138+ _PIPE_A_OUTPUT_CSC_COEFF_BU, \
139+ _PIPE_B_OUTPUT_CSC_COEFF_BU)
140+#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
141+ _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
142+ _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
143+#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
144+ _PIPE_A_OUTPUT_CSC_COEFF_BV, \
145+ _PIPE_B_OUTPUT_CSC_COEFF_BV)
146+#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
147+ _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
148+ _PIPE_B_OUTPUT_CSC_PREOFF_HI)
149+#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
150+ _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
151+ _PIPE_B_OUTPUT_CSC_PREOFF_ME)
152+#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
153+ _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
154+ _PIPE_B_OUTPUT_CSC_PREOFF_LO)
155+#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
156+ _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
157+ _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
158+#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
159+ _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
160+ _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
161+#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
162+ _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
163+ _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
164+
165+/* pipe degamma/gamma LUTs on IVB+ */
166+#define _PAL_PREC_INDEX_A 0x4A400
167+#define _PAL_PREC_INDEX_B 0x4AC00
168+#define _PAL_PREC_INDEX_C 0x4B400
169+#define PAL_PREC_SPLIT_MODE REG_BIT(31)
170+#define PAL_PREC_AUTO_INCREMENT REG_BIT(15)
171+#define PAL_PREC_INDEX_VALUE_MASK REG_GENMASK(9, 0)
172+#define PAL_PREC_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_INDEX_VALUE_MASK, (x))
173+#define _PAL_PREC_DATA_A 0x4A404
174+#define _PAL_PREC_DATA_B 0x4AC04
175+#define _PAL_PREC_DATA_C 0x4B404
176+/* see PREC_PALETTE_* for the bits */
177+#define _PAL_PREC_GC_MAX_A 0x4A410
178+#define _PAL_PREC_GC_MAX_B 0x4AC10
179+#define _PAL_PREC_GC_MAX_C 0x4B410
180+#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
181+#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
182+#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
183+#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
184+#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
185+#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
186+
187+#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
188+#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
189+#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */
190+#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */
191+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */
192+
193+#define _PRE_CSC_GAMC_INDEX_A 0x4A484
194+#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
195+#define _PRE_CSC_GAMC_INDEX_C 0x4B484
196+#define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10)
197+#define PRE_CSC_GAMC_INDEX_VALUE_MASK REG_GENMASK(7, 0)
198+#define PRE_CSC_GAMC_INDEX_VALUE(x) REG_FIELD_PREP(PRE_CSC_GAMC_INDEX_VALUE_MASK, (x))
199+#define _PRE_CSC_GAMC_DATA_A 0x4A488
200+#define _PRE_CSC_GAMC_DATA_B 0x4AC88
201+#define _PRE_CSC_GAMC_DATA_C 0x4B488
202+
203+#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
204+#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
205+
206+/* ICL Multi segmented gamma */
207+#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
208+#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
209+#define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15)
210+#define PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK REG_GENMASK(4, 0)
211+#define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x))
212+
213+#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
214+#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
215+/* see PREC_PALETTE_12P4_* for the bits */
216+
217+#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
218+ _PAL_PREC_MULTI_SEG_INDEX_A, \
219+ _PAL_PREC_MULTI_SEG_INDEX_B)
220+#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
221+ _PAL_PREC_MULTI_SEG_DATA_A, \
222+ _PAL_PREC_MULTI_SEG_DATA_B)
223+
224+#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */
225+#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */
226+#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */
227+#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */
228+#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */
229+#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */
230+
231+#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00)
232+#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)
233+#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10)
234+#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)
235+#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20)
236+#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)
237+
238+/* pipe CSC & degamma/gamma LUTs on CHV */
239+#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
240+#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
241+#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
242+#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
243+#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
244+#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
245+/* cgm degamma ldw */
246+#define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16)
247+#define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0)
248+/* cgm degamma udw */
249+#define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0)
250+#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
251+/* cgm gamma ldw */
252+#define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16)
253+#define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0)
254+/* cgm gamma udw */
255+#define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0)
256+#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
257+#define CGM_PIPE_MODE_GAMMA (1 << 2)
258+#define CGM_PIPE_MODE_CSC (1 << 1)
259+#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
260+
261+#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
262+#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
263+#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
264+#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
265+#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
266+#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
267+#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
268+#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
269+
270+#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
271+#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
272+#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
273+#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
274+#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
275+#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
276+#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
277+#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
278+
279+/* Skylake+ pipe bottom (background) color */
280+#define _SKL_BOTTOM_COLOR_A 0x70034
281+#define _SKL_BOTTOM_COLOR_B 0x71034
282+#define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
283+#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
284+#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
285+
286+#endif /* __INTEL_COLOR_REGS_H__ */
drivers/gpu/drm/i915/display/intel_combo_phy.c+8−9
@@ -114,10 +114,6 @@ static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, · 113 unmodified lines
114114
115115 procmon = icl_get_procmon_ref_values(dev_priv, phy);
116116
117− drm_dbg_kms(&dev_priv->drm,
118− "Combo PHY %c Voltage/Process Info : %s\n",
119− phy_name(phy), procmon->name);
120−
121117 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
122118 (0xff << 16) | 0xff, procmon->dw1);
123119 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
@@ -312,14 +308,17 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) · 188 unmodified lines
312308 enum phy phy;
313309
314310 for_each_combo_phy(dev_priv, phy) {
311+ const struct icl_procmon *procmon;
315312 u32 val;
316313
317− if (icl_combo_phy_verify_state(dev_priv, phy)) {
318− drm_dbg(&dev_priv->drm,
319− "Combo PHY %c already enabled, won't reprogram it.\n",
320− phy_name(phy));
314+ if (icl_combo_phy_verify_state(dev_priv, phy))
321315 continue;
322− }
316+
317+ procmon = icl_get_procmon_ref_values(dev_priv, phy);
318+
319+ drm_dbg(&dev_priv->drm,
320+ "Initializing combo PHY %c (Voltage/Process Info : %s)\n",
321+ phy_name(phy), procmon->name);
323322
324323 if (!has_phy_misc(dev_priv, phy))
325324 goto skip_phy_misc;
drivers/gpu/drm/i915/display/intel_connector.c+3−3
@@ -192,17 +192,17 @@ int intel_connector_update_modes(struct drm_connector *connector, · 191 unmodified lines
192192 /**
193193 * intel_ddc_get_modes - get modelist from monitor
194194 * @connector: DRM connector device to use
195− * @adapter: i2c adapter
195+ * @ddc: DDC bus i2c adapter
196196 *
197197 * Fetch the EDID information from @connector using the DDC bus.
198198 */
199199 int intel_ddc_get_modes(struct drm_connector *connector,
200− struct i2c_adapter *adapter)
200+ struct i2c_adapter *ddc)
201201 {
202202 const struct drm_edid *drm_edid;
203203 int ret;
204204
205− drm_edid = drm_edid_read_ddc(connector, adapter);
205+ drm_edid = drm_edid_read_ddc(connector, ddc);
206206 if (!drm_edid)
207207 return 0;
208208
drivers/gpu/drm/i915/display/intel_connector.h+1−1
@@ -26,7 +26,7 @@ bool intel_connector_get_hw_state(struct intel_connector *connector); · 25 unmodified lines
2626 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
2727 int intel_connector_update_modes(struct drm_connector *connector,
2828 const struct drm_edid *drm_edid);
29−int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
29+int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *ddc);
3030 void intel_attach_force_audio_property(struct drm_connector *connector);
3131 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
3232 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
drivers/gpu/drm/i915/display/intel_crt.c+33−31
@@ -413,6 +413,9 @@ static int pch_crt_compute_config(struct intel_encoder *encoder, · 412 unmodified lines
413413 return -EINVAL;
414414
415415 pipe_config->has_pch_encoder = true;
416+ if (!intel_fdi_compute_pipe_bpp(pipe_config))
417+ return -EINVAL;
418+
416419 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
417420
418421 return 0;
@@ -435,10 +438,14 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, · 16 unmodified lines
435438 return -EINVAL;
436439
437440 pipe_config->has_pch_encoder = true;
441+ if (!intel_fdi_compute_pipe_bpp(pipe_config))
442+ return -EINVAL;
443+
438444 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
439445
440446 /* LPT FDI RX only supports 8bpc. */
441447 if (HAS_PCH_LPT(dev_priv)) {
448+ /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
442449 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
443450 drm_dbg_kms(&dev_priv->drm,
444451 "LPT only supports 24bpp\n");
@@ -451,6 +458,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, · 6 unmodified lines
451458 /* FDI must always be 2.7 GHz */
452459 pipe_config->port_clock = 135000 * 2;
453460
461+ pipe_config->enhanced_framing = true;
462+
454463 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
455464
456465 return 0;
@@ -610,18 +619,18 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) · 153 unmodified lines
610619 }
611620
612621 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector,
613− struct i2c_adapter *i2c)
622+ struct i2c_adapter *ddc)
614623 {
615624 const struct drm_edid *drm_edid;
616625
617− drm_edid = drm_edid_read_ddc(connector, i2c);
626+ drm_edid = drm_edid_read_ddc(connector, ddc);
618627
619− if (!drm_edid && !intel_gmbus_is_forced_bit(i2c)) {
628+ if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
620629 drm_dbg_kms(connector->dev,
621630 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
622− intel_gmbus_force_bit(i2c, true);
623− drm_edid = drm_edid_read_ddc(connector, i2c);
624− intel_gmbus_force_bit(i2c, false);
631+ intel_gmbus_force_bit(ddc, true);
632+ drm_edid = drm_edid_read_ddc(connector, ddc);
633+ intel_gmbus_force_bit(ddc, false);
625634 }
626635
627636 return drm_edid;
@@ -629,12 +638,12 @@ static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector · 1 unmodified line
629638
630639 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
631640 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
632− struct i2c_adapter *adapter)
641+ struct i2c_adapter *ddc)
633642 {
634643 const struct drm_edid *drm_edid;
635644 int ret;
636645
637− drm_edid = intel_crt_get_edid(connector, adapter);
646+ drm_edid = intel_crt_get_edid(connector, ddc);
638647 if (!drm_edid)
639648 return 0;
640649
@@ -650,28 +659,23 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector) · 9 unmodified lines
650659 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
651660 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
652661 const struct drm_edid *drm_edid;
653− struct i2c_adapter *i2c;
654662 bool ret = false;
655663
656− i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
657− drm_edid = intel_crt_get_edid(connector, i2c);
664+ drm_edid = intel_crt_get_edid(connector, connector->ddc);
658665
659666 if (drm_edid) {
660− const struct edid *edid = drm_edid_raw(drm_edid);
661− bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
662−
663667 /*
664668 * This may be a DVI-I connector with a shared DDC
665669 * link between analog and digital outputs, so we
666670 * have to check the EDID input spec of the attached device.
667671 */
668− if (!is_digital) {
672+ if (drm_edid_is_digital(drm_edid)) {
669673 drm_dbg_kms(&dev_priv->drm,
670− "CRT detected via DDC:0x50 [EDID]\n");
671− ret = true;
674+ "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
672675 } else {
673676 drm_dbg_kms(&dev_priv->drm,
674− "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
677+ "CRT detected via DDC:0x50 [EDID]\n");
678+ ret = true;
675679 }
676680 } else {
677681 drm_dbg_kms(&dev_priv->drm,
@@ -907,12 +911,6 @@ load_detect: · 229 unmodified lines
907911 out:
908912 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
909913
910− /*
911− * Make sure the refs for power wells enabled during detect are
912− * dropped to avoid a new detect cycle triggered by HPD polling.
913− */
914− intel_display_power_flush_work(dev_priv);
915−
916914 return status;
917915 }
918916
@@ -923,20 +921,19 @@ static int intel_crt_get_modes(struct drm_connector *connector) · 4 unmodified lines
923921 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
924922 struct intel_encoder *intel_encoder = &crt->base;
925923 intel_wakeref_t wakeref;
926− struct i2c_adapter *i2c;
924+ struct i2c_adapter *ddc;
927925 int ret;
928926
929927 wakeref = intel_display_power_get(dev_priv,
930928 intel_encoder->power_domain);
931929
932− i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
933− ret = intel_crt_ddc_get_modes(connector, i2c);
930+ ret = intel_crt_ddc_get_modes(connector, connector->ddc);
934931 if (ret || !IS_G4X(dev_priv))
935932 goto out;
936933
937934 /* Try to probe digital port for output in DVI-I -> VGA mode. */
938− i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
939− ret = intel_crt_ddc_get_modes(connector, i2c);
935+ ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
936+ ret = intel_crt_ddc_get_modes(connector, ddc);
940937
941938 out:
942939 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
@@ -994,6 +991,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv) · 51 unmodified lines
994991 struct intel_crt *crt;
995992 struct intel_connector *intel_connector;
996993 i915_reg_t adpa_reg;
994+ u8 ddc_pin;
997995 u32 adpa;
998996
999997 if (HAS_PCH_SPLIT(dev_priv))
@@ -1030,10 +1028,14 @@ void intel_crt_init(struct drm_i915_private *dev_priv) · 30 unmodified lines
10301028 return;
10311029 }
10321030
1031+ ddc_pin = dev_priv->display.vbt.crt_ddc_pin;
1032+
10331033 connector = &intel_connector->base;
10341034 crt->connector = intel_connector;
1035− drm_connector_init(&dev_priv->drm, &intel_connector->base,
1036− &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1035+ drm_connector_init_with_ddc(&dev_priv->drm, connector,
1036+ &intel_crt_connector_funcs,
1037+ DRM_MODE_CONNECTOR_VGA,
1038+ intel_gmbus_get_adapter(dev_priv, ddc_pin));
10371039
10381040 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
10391041 DRM_MODE_ENCODER_DAC, "CRT");
drivers/gpu/drm/i915/display/intel_crtc.c+76−42
@@ -24,6 +24,7 @@ · 23 unmodified lines
2424 #include "intel_display_trace.h"
2525 #include "intel_display_types.h"
2626 #include "intel_drrs.h"
27+#include "intel_dsb.h"
2728 #include "intel_dsi.h"
2829 #include "intel_fifo_underrun.h"
2930 #include "intel_pipe_crc.h"
@@ -175,6 +176,7 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state, · 145 unmodified lines
175176 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
176177 crtc_state->scaler_state.scaler_id = -1;
177178 crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
179+ crtc_state->max_link_bpp_x16 = INT_MAX;
178180 }
179181
180182 static struct intel_crtc *intel_crtc_alloc(void)
@@ -394,7 +396,8 @@ static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_sta · 213 unmodified lines
394396 return crtc_state->hw.active &&
395397 !intel_crtc_needs_modeset(crtc_state) &&
396398 !crtc_state->preload_luts &&
397− intel_crtc_needs_color_update(crtc_state);
399+ intel_crtc_needs_color_update(crtc_state) &&
400+ !intel_color_uses_dsb(crtc_state);
398401 }
399402
400403 static void intel_crtc_vblank_work(struct kthread_work *base)
@@ -468,9 +471,64 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode) · 67 unmodified lines
468471 return vblank_start;
469472 }
470473
474+static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
475+ struct intel_crtc *crtc,
476+ int *min, int *max, int *vblank_start)
477+{
478+ const struct intel_crtc_state *old_crtc_state =
479+ intel_atomic_get_old_crtc_state(state, crtc);
480+ const struct intel_crtc_state *new_crtc_state =
481+ intel_atomic_get_new_crtc_state(state, crtc);
482+ const struct intel_crtc_state *crtc_state;
483+ const struct drm_display_mode *adjusted_mode;
484+
485+ /*
486+ * During fastsets/etc. the transcoder is still
487+ * running with the old timings at this point.
488+ *
489+ * TODO: maybe just use the active timings here?
490+ */
491+ if (intel_crtc_needs_modeset(new_crtc_state))
492+ crtc_state = new_crtc_state;
493+ else
494+ crtc_state = old_crtc_state;
495+
496+ adjusted_mode = &crtc_state->hw.adjusted_mode;
497+
498+ if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
499+ /* timing changes should happen with VRR disabled */
500+ drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
501+ new_crtc_state->update_m_n || new_crtc_state->update_lrr);
502+
503+ if (intel_vrr_is_push_sent(crtc_state))
504+ *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
505+ else
506+ *vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
507+ } else {
508+ *vblank_start = intel_mode_vblank_start(adjusted_mode);
509+ }
510+
511+ /* FIXME needs to be calibrated sensibly */
512+ *min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode,
513+ VBLANK_EVASION_TIME_US);
514+ *max = *vblank_start - 1;
515+
516+ /*
517+ * M/N and TRANS_VTOTAL are double buffered on the transcoder's
518+ * undelayed vblank, so with seamless M/N and LRR we must evade
519+ * both vblanks.
520+ *
521+ * DSB execution waits for the transcoder's undelayed vblank,
522+ * hence we must kick off the commit before that.
523+ */
524+ if (new_crtc_state->dsb || new_crtc_state->update_m_n || new_crtc_state->update_lrr)
525+ *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
526+}
527+
471528 /**
472529 * intel_pipe_update_start() - start update of a set of display registers
473− * @new_crtc_state: the new crtc state
530+ * @state: the atomic state
531+ * @crtc: the crtc
474532 *
475533 * Mark the start of an update to pipe registers that should be updated
476534 * atomically regarding vblank. If the next vblank will happens within
@@ -480,11 +538,12 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode) · 3 unmodified lines
480538 * until a subsequent call to intel_pipe_update_end(). That is done to
481539 * avoid random delays.
482540 */
483−void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
541+void intel_pipe_update_start(struct intel_atomic_state *state,
542+ struct intel_crtc *crtc)
484543 {
485− struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
486544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
487− const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
545+ struct intel_crtc_state *new_crtc_state =
546+ intel_atomic_get_new_crtc_state(state, crtc);
488547 long timeout = msecs_to_jiffies_timeout(1);
489548 int scanline, min, max, vblank_start;
490549 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
@@ -500,27 +559,7 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state) · 9 unmodified lines
500559 if (intel_crtc_needs_vblank_work(new_crtc_state))
501560 intel_crtc_vblank_work_init(new_crtc_state);
502561
503− if (new_crtc_state->vrr.enable) {
504− if (intel_vrr_is_push_sent(new_crtc_state))
505− vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
506− else
507− vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
508− } else {
509− vblank_start = intel_mode_vblank_start(adjusted_mode);
510− }
511−
512− /* FIXME needs to be calibrated sensibly */
513− min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
514− VBLANK_EVASION_TIME_US);
515− max = vblank_start - 1;
516−
517− /*
518− * M/N is double buffered on the transcoder's undelayed vblank,
519− * so with seamless M/N we must evade both vblanks.
520− */
521− if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
522− min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
523−
562+ intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max, &vblank_start);
524563 if (min <= 0 || max <= 0)
525564 goto irq_disable;
526565
@@ -631,25 +670,26 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {} · 104 unmodified lines
631670
632671 /**
633672 * intel_pipe_update_end() - end update of a set of display registers
634− * @new_crtc_state: the new crtc state
673+ * @state: the atomic state
674+ * @crtc: the crtc
635675 *
636676 * Mark the end of an update started with intel_pipe_update_start(). This
637677 * re-enables interrupts and verifies the update was actually completed
638678 * before a vblank.
639679 */
640−void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
680+void intel_pipe_update_end(struct intel_atomic_state *state,
681+ struct intel_crtc *crtc)
641682 {
642− struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
683+ struct intel_crtc_state *new_crtc_state =
684+ intel_atomic_get_new_crtc_state(state, crtc);
643685 enum pipe pipe = crtc->pipe;
644686 int scanline_end = intel_get_crtc_scanline(crtc);
645687 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
646688 ktime_t end_vbl_time = ktime_get();
647689 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
648690
649− intel_psr_unlock(new_crtc_state);
650−
651691 if (new_crtc_state->do_async_flip)
652− return;
692+ goto out;
653693
654694 trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
655695
@@ -697,19 +737,10 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) · 41 unmodified lines
697737 */
698738 intel_vrr_send_push(new_crtc_state);
699739
700− /*
701− * Seamless M/N update may need to update frame timings.
702− *
703− * FIXME Should be synchronized with the start of vblank somehow...
704− */
705− if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
706− intel_crtc_update_active_timings(new_crtc_state,
707− new_crtc_state->vrr.enable);
708−
709740 local_irq_enable();
710741
711742 if (intel_vgpu_active(dev_priv))
712− return;
743+ goto out;
713744
714745 if (crtc->debug.start_vbl_count &&
715746 crtc->debug.start_vbl_count != end_vbl_count) {
@@ -724,4 +755,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) · 8 unmodified lines
724755 }
725756
726757 dbg_vblank_evade(crtc, end_vbl_time);
758+
759+out:
760+ intel_psr_unlock(new_crtc_state);
727761 }
drivers/gpu/drm/i915/display/intel_crtc.h+4−2
@@ -36,8 +36,10 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state, · 35 unmodified lines
3636 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
3737 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
3838 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
39−void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
40−void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
39+void intel_pipe_update_start(struct intel_atomic_state *state,
40+ struct intel_crtc *crtc);
41+void intel_pipe_update_end(struct intel_atomic_state *state,
42+ struct intel_crtc *crtc);
4143 void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
4244 struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915);
4345 struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c+3−0
@@ -258,6 +258,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, · 257 unmodified lines
258258 intel_dump_m_n_config(pipe_config, "dp m2_n2",
259259 pipe_config->lane_count,
260260 &pipe_config->dp_m2_n2);
261+ drm_dbg_kms(&i915->drm, "fec: %s, enhanced framing: %s\n",
262+ str_enabled_disabled(pipe_config->fec_enable),
263+ str_enabled_disabled(pipe_config->enhanced_framing));
261264 }
262265
263266 drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",
drivers/gpu/drm/i915/display/intel_cx0_phy.c+107−98
@@ -31,7 +31,7 @@ · 30 unmodified lines
3131
3232 bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
3333 {
34− if (IS_METEORLAKE(i915) && (phy < PHY_C))
34+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C)
3535 return true;
3636
3737 return false;
@@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask) · 8 unmodified lines
4646 return ilog2(lane_mask);
4747 }
4848
49+static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
50+ struct intel_encoder *encoder)
51+{
52+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
53+
54+ if (!intel_tc_port_in_dp_alt_mode(dig_port))
55+ return INTEL_CX0_BOTH_LANES;
56+
57+ /*
58+ * In DP-alt with pin assignment D, only PHY lane 0 is owned
59+ * by display and lane 1 is owned by USB.
60+ */
61+ return intel_tc_port_max_lane_count(dig_port) > 2
62+ ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
63+}
64+
4965 static void
5066 assert_dc_off(struct drm_i915_private *i915)
5167 {
@@ -55,19 +71,38 @@ assert_dc_off(struct drm_i915_private *i915) · 3 unmodified lines
5571 drm_WARN_ON(&i915->drm, !enabled);
5672 }
5773
74+static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)
75+{
76+ int lane;
77+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
78+
79+ for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)
80+ intel_de_rmw(i915,
81+ XELPDP_PORT_MSGBUS_TIMER(encoder->port, lane),
82+ XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
83+ XELPDP_PORT_MSGBUS_TIMER_VAL);
84+}
85+
5886 /*
5987 * Prepare HW for CX0 phy transactions.
6088 *
6189 * It is required that PSR and DC5/6 are disabled before any CX0 message
6290 * bus transaction is executed.
91+ *
92+ * We also do the msgbus timer programming here to ensure that the timer
93+ * is already programmed before any access to the msgbus.
6394 */
6495 static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
6596 {
97+ intel_wakeref_t wakeref;
6698 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6799 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
68100
69101 intel_psr_pause(intel_dp);
70− return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
102+ wakeref = intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
103+ intel_cx0_program_msgbus_timer(encoder);
104+
105+ return wakeref;
71106 }
72107
73108 static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
@@ -116,6 +151,13 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port, · 42 unmodified lines
116151 XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
117152 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
118153 phy_name(phy), *val);
154+
155+ if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(port, lane)) &
156+ XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT))
157+ drm_dbg_kms(&i915->drm,
158+ "PHY %c Hardware did not detect a timeout\n",
159+ phy_name(phy));
160+
119161 intel_cx0_bus_reset(i915, port, lane);
120162 return -ETIMEDOUT;
121163 }
@@ -359,6 +401,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, · 237 unmodified lines
359401 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
360402 const struct intel_ddi_buf_trans *trans;
361403 enum phy phy = intel_port_to_phy(i915, encoder->port);
404+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
362405 intel_wakeref_t wakeref;
363406 int n_entries, ln;
364407
@@ -371,13 +414,13 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, · 6 unmodified lines
371414 }
372415
373416 if (intel_is_c10phy(i915, phy)) {
374− intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
417+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
375418 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
376− intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3),
419+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CMN(3),
377420 C10_CMN3_TXVBOOST_MASK,
378421 C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
379422 MB_WRITE_UNCOMMITTED);
380− intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1),
423+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_TX(1),
381424 C10_TX1_TERMCTL_MASK,
382425 C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
383426 MB_WRITE_COMMITTED);
@@ -385,32 +428,34 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, · 1 unmodified line
385428
386429 for (ln = 0; ln < crtc_state->lane_count; ln++) {
387430 int level = intel_ddi_level(encoder, crtc_state, ln);
388− int lane, tx;
431+ int lane = ln / 2;
432+ int tx = ln % 2;
433+ u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
389434
390− lane = ln / 2;
391− tx = ln % 2;
435+ if (!(lane_mask & owned_lane_mask))
436+ continue;
392437
393− intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0),
438+ intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0),
394439 C10_PHY_OVRD_LEVEL_MASK,
395440 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
396441 MB_WRITE_COMMITTED);
397− intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1),
442+ intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1),
398443 C10_PHY_OVRD_LEVEL_MASK,
399444 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
400445 MB_WRITE_COMMITTED);
401− intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2),
446+ intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2),
402447 C10_PHY_OVRD_LEVEL_MASK,
403448 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
404449 MB_WRITE_COMMITTED);
405450 }
406451
407452 /* Write Override enables in 0xD71 */
408− intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,
453+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD,
409454 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
410455 MB_WRITE_COMMITTED);
411456
412457 if (intel_is_c10phy(i915, phy))
413− intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
458+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
414459 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
415460
416461 intel_cx0_phy_transaction_end(encoder, wakeref);
@@ -2534,17 +2579,15 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, · 2117 unmodified lines
25342579 {
25352580 enum port port = encoder->port;
25362581 enum phy phy = intel_port_to_phy(i915, port);
2537− bool both_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
2538− u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
2539− INTEL_CX0_LANE0;
2540− u32 lane_pipe_reset = both_lanes ?
2541− XELPDP_LANE_PIPE_RESET(0) |
2542− XELPDP_LANE_PIPE_RESET(1) :
2543− XELPDP_LANE_PIPE_RESET(0);
2544− u32 lane_phy_current_status = both_lanes ?
2545− XELPDP_LANE_PHY_CURRENT_STATUS(0) |
2546− XELPDP_LANE_PHY_CURRENT_STATUS(1) :
2547− XELPDP_LANE_PHY_CURRENT_STATUS(0);
2582+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
2583+ u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
2584+ u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
2585+ ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
2586+ : XELPDP_LANE_PIPE_RESET(0);
2587+ u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
2588+ ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
2589+ XELPDP_LANE_PHY_CURRENT_STATUS(1))
2590+ : XELPDP_LANE_PHY_CURRENT_STATUS(0);
25482591
25492592 if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
25502593 XELPDP_PORT_BUF_SOC_PHY_READY,
@@ -2564,15 +2607,11 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, · 13 unmodified lines
25642607 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
25652608
25662609 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
2567− intel_cx0_get_pclk_refclk_request(both_lanes ?
2568− INTEL_CX0_BOTH_LANES :
2569− INTEL_CX0_LANE0),
2610+ intel_cx0_get_pclk_refclk_request(owned_lane_mask),
25702611 intel_cx0_get_pclk_refclk_request(lane_mask));
25712612
25722613 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
2573− intel_cx0_get_pclk_refclk_ack(both_lanes ?
2574− INTEL_CX0_BOTH_LANES :
2575− INTEL_CX0_LANE0),
2614+ intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
25762615 intel_cx0_get_pclk_refclk_ack(lane_mask),
25772616 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
25782617 drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
@@ -2594,79 +2633,43 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, · 15 unmodified lines
25942633 struct intel_encoder *encoder, int lane_count,
25952634 bool lane_reversal)
25962635 {
2597− u8 l0t1, l0t2, l1t1, l1t2;
2636+ int i;
2637+ u8 disables;
25982638 bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
2639+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
25992640 enum port port = encoder->port;
26002641
26012642 if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
2602− intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
2643+ intel_cx0_rmw(i915, port, owned_lane_mask,
26032644 PHY_C10_VDR_CONTROL(1), 0,
26042645 C10_VDR_CTRL_MSGBUS_ACCESS,
26052646 MB_WRITE_COMMITTED);
26062647
2607− /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
2608− l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
2609− l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
2610− l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
2611− l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
2612−
2613− l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
2614− l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
2615− l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
2616− l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
2617−
2618− if (lane_reversal) {
2619− switch (lane_count) {
2620− case 4:
2621− l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
2622− fallthrough;
2623− case 3:
2624− l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
2625− fallthrough;
2626− case 2:
2627− l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
2628− fallthrough;
2629− case 1:
2630− l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
2631− break;
2632− default:
2633− MISSING_CASE(lane_count);
2634− }
2635− } else {
2636− switch (lane_count) {
2637− case 4:
2638− l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
2639− fallthrough;
2640− case 3:
2641− l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
2642− fallthrough;
2643− case 2:
2644− l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
2645− l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
2646− break;
2647− case 1:
2648− if (dp_alt_mode)
2649− l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
2650− else
2651− l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
2652− break;
2653− default:
2654− MISSING_CASE(lane_count);
2655− }
2648+ if (lane_reversal)
2649+ disables = REG_GENMASK8(3, 0) >> lane_count;
2650+ else
2651+ disables = REG_GENMASK8(3, 0) << lane_count;
2652+
2653+ if (dp_alt_mode && lane_count == 1) {
2654+ disables &= ~REG_GENMASK8(1, 0);
2655+ disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
26562656 }
26572657
2658− /* disable MLs */
2659− intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
2660− l0t1, MB_WRITE_COMMITTED);
2661− intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
2662− l0t2, MB_WRITE_COMMITTED);
2663− intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
2664− l1t1, MB_WRITE_COMMITTED);
2665− intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
2666− l1t2, MB_WRITE_COMMITTED);
2658+ for (i = 0; i < 4; i++) {
2659+ int tx = i % 2 + 1;
2660+ u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
2661+
2662+ if (!(owned_lane_mask & lane_mask))
2663+ continue;
2664+
2665+ intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
2666+ CONTROL2_DISABLE_SINGLE_TX,
2667+ disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
2668+ MB_WRITE_COMMITTED);
2669+ }
26672670
26682671 if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
2669− intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
2672+ intel_cx0_rmw(i915, port, owned_lane_mask,
26702673 PHY_C10_VDR_CONTROL(1), 0,
26712674 C10_VDR_CTRL_UPDATE_CFG,
26722675 MB_WRITE_COMMITTED);
@@ -2721,39 +2724,45 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, · 48 unmodified lines
27212724 intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
27222725 CX0_P2_STATE_READY);
27232726
2724− /* 4. Program PHY internal PLL internal registers. */
2727+ /*
2728+ * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000.
2729+ * (This is done inside intel_cx0_phy_transaction_begin(), since we would need
2730+ * the right timer thresholds for readouts too.)
2731+ */
2732+
2733+ /* 5. Program PHY internal PLL internal registers. */
27252734 if (intel_is_c10phy(i915, phy))
27262735 intel_c10_pll_program(i915, crtc_state, encoder);
27272736 else
27282737 intel_c20_pll_program(i915, crtc_state, encoder);
27292738
27302739 /*
2731− * 5. Program the enabled and disabled owned PHY lane
2740+ * 6. Program the enabled and disabled owned PHY lane
27322741 * transmitters over message bus
27332742 */
27342743 intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
27352744
27362745 /*
2737− * 6. Follow the Display Voltage Frequency Switching - Sequence
2746+ * 7. Follow the Display Voltage Frequency Switching - Sequence
27382747 * Before Frequency Change. We handle this step in bxt_set_cdclk().
27392748 */
27402749
27412750 /*
2742− * 7. Program DDI_CLK_VALFREQ to match intended DDI
2751+ * 8. Program DDI_CLK_VALFREQ to match intended DDI
27432752 * clock frequency.
27442753 */
27452754 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
27462755 crtc_state->port_clock);
27472756
27482757 /*
2749− * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
2758+ * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
27502759 * LN<Lane for maxPCLK> to "1" to enable PLL.
27512760 */
27522761 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
27532762 intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
27542763 intel_cx0_get_pclk_pll_request(maxpclk_lane));
27552764
2756− /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
2765+ /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
27572766 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
27582767 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
27592768 intel_cx0_get_pclk_pll_ack(maxpclk_lane),
@@ -2762,7 +2771,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, · 2 unmodified lines
27622771 phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
27632772
27642773 /*
2765− * 10. Follow the Display Voltage Frequency Switching Sequence After
2774+ * 11. Follow the Display Voltage Frequency Switching Sequence After
27662775 * Frequency Change. We handle this step in bxt_set_cdclk().
27672776 */
27682777
drivers/gpu/drm/i915/display/intel_cx0_phy.h+8−6
@@ -10,14 +10,15 @@ · 9 unmodified lines
1010 #include <linux/bitfield.h>
1111 #include <linux/bits.h>
1212
13−#include "i915_drv.h"
14−#include "intel_display_types.h"
15−
16−struct drm_i915_private;
17−struct intel_encoder;
18−struct intel_crtc_state;
1913 enum icl_port_dpll_id;
2014 enum phy;
15+struct drm_i915_private;
16+struct intel_atomic_state;
17+struct intel_c10pll_state;
18+struct intel_c20pll_state;
19+struct intel_crtc_state;
20+struct intel_encoder;
21+struct intel_hdmi;
2122
2223 bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
2324 void intel_mtl_pll_enable(struct intel_encoder *encoder,
@@ -44,4 +45,5 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, · 20 unmodified lines
4445 const struct intel_crtc_state *crtc_state);
4546 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
4647 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
48+
4749 #endif /* __INTEL_CX0_PHY_H__ */
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h+13−0
@@ -110,6 +110,19 @@ · 109 unmodified lines
110110 #define CX0_P4PG_STATE_DISABLE 0xC
111111 #define CX0_P2_STATE_RESET 0x2
112112
113+#define _XELPDP_PORT_MSGBUS_TIMER_LN0_A 0x640d8
114+#define _XELPDP_PORT_MSGBUS_TIMER_LN0_B 0x641d8
115+#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 0x16f258
116+#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 0x16f458
117+#define XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
118+ _XELPDP_PORT_MSGBUS_TIMER_LN0_A, \
119+ _XELPDP_PORT_MSGBUS_TIMER_LN0_B, \
120+ _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \
121+ _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4)
122+#define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT REG_BIT(31)
123+#define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0)
124+#define XELPDP_PORT_MSGBUS_TIMER_VAL REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000)
125+
113126 #define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
114127 #define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
115128 #define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
drivers/gpu/drm/i915/display/intel_ddi.c+20−18
@@ -3248,7 +3248,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state, · 3247 unmodified lines
32483248 intel_ddi_enable_transcoder_func(encoder, crtc_state);
32493249
32503250 /* Enable/Disable DP2.0 SDP split config before transcoder */
3251− intel_audio_sdp_split_update(encoder, crtc_state);
3251+ intel_audio_sdp_split_update(crtc_state);
32523252
32533253 intel_enable_transcoder(crtc_state);
32543254
@@ -3432,7 +3432,7 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, · 177 unmodified lines
34323432 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
34333433 } else {
34343434 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3435− if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3435+ if (crtc_state->enhanced_framing)
34363436 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
34373437 }
34383438 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
@@ -3489,7 +3489,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, · 50 unmodified lines
34893489 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
34903490 } else {
34913491 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3492− if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3492+ if (crtc_state->enhanced_framing)
34933493 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
34943494 }
34953495 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
@@ -3724,17 +3724,14 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, · 228 unmodified lines
37243724 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
37253725 &pipe_config->dp_m2_n2);
37263726
3727− if (DISPLAY_VER(dev_priv) >= 11) {
3728− i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3727+ pipe_config->enhanced_framing =
3728+ intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
3729+ DP_TP_CTL_ENHANCED_FRAME_ENABLE;
37293730
3731+ if (DISPLAY_VER(dev_priv) >= 11)
37303732 pipe_config->fec_enable =
3731− intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3732−
3733− drm_dbg_kms(&dev_priv->drm,
3734− "[ENCODER:%d:%s] Fec status: %u\n",
3735− encoder->base.base.id, encoder->base.name,
3736− pipe_config->fec_enable);
3737− }
3733+ intel_de_read(dev_priv,
3734+ dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
37383735
37393736 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
37403737 pipe_config->infoframes.enable |=
@@ -3747,6 +3744,9 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, · 6 unmodified lines
37473744 if (!HAS_DP20(dev_priv)) {
37483745 /* FDI */
37493746 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3747+ pipe_config->enhanced_framing =
3748+ intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
3749+ DP_TP_CTL_ENHANCED_FRAME_ENABLE;
37503750 break;
37513751 }
37523752 fallthrough; /* 128b/132b */
@@ -3762,6 +3762,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, · 9 unmodified lines
37623762 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
37633763 &pipe_config->dp_m_n);
37643764
3765+ if (DISPLAY_VER(dev_priv) >= 11)
3766+ pipe_config->fec_enable =
3767+ intel_de_read(dev_priv,
3768+ dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
3769+
37653770 pipe_config->infoframes.enable |=
37663771 intel_hdmi_infoframes_enabled(encoder, pipe_config);
37673772 break;
@@ -3857,11 +3862,9 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder, · 89 unmodified lines
38573862 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
38583863 } else if (intel_is_c10phy(i915, phy)) {
38593864 intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
3860− intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
38613865 crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
38623866 } else {
38633867 intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
3864− intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
38653868 crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
38663869 }
38673870
@@ -4173,7 +4176,7 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder, · 305 unmodified lines
41734176 struct drm_connector *connector = conn_state->connector;
41744177 u8 port_sync_transcoders = 0;
41754178
4176− drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4179+ drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
41774180 encoder->base.base.id, encoder->base.name,
41784181 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
41794182
@@ -4323,8 +4326,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, · 143 unmodified lines
43234326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
43244327 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
43254328 struct intel_connector *connector = hdmi->attached_connector;
4326− struct i2c_adapter *adapter =
4327− intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4329+ struct i2c_adapter *ddc = connector->base.ddc;
43284330 struct drm_connector_state *conn_state;
43294331 struct intel_crtc_state *crtc_state;
43304332 struct intel_crtc *crtc;
@@ -4365,7 +4367,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, · 34 unmodified lines
43654367 !try_wait_for_completion(&conn_state->commit->hw_done))
43664368 return 0;
43674369
4368− ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4370+ ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config);
43694371 if (ret < 0) {
43704372 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
43714373 connector->base.base.id, connector->base.name, ret);
drivers/gpu/drm/i915/display/intel_display.c+337−139
@@ -77,6 +77,7 @@ · 76 unmodified lines
7777 #include "intel_dpll_mgr.h"
7878 #include "intel_dpt.h"
7979 #include "intel_drrs.h"
80+#include "intel_dsb.h"
8081 #include "intel_dsi.h"
8182 #include "intel_dvo.h"
8283 #include "intel_fb.h"
@@ -87,6 +88,7 @@ · 4 unmodified lines
8788 #include "intel_frontbuffer.h"
8889 #include "intel_hdmi.h"
8990 #include "intel_hotplug.h"
91+#include "intel_link_bw.h"
9092 #include "intel_lvds.h"
9193 #include "intel_lvds_regs.h"
9294 #include "intel_modeset_setup.h"
@@ -726,7 +728,7 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) · 633 unmodified lines
726728 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
727729
728730 /* Wa_14010547955:dg2 */
729− if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
731+ if (IS_DG2(dev_priv))
730732 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
731733
732734 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
@@ -913,16 +915,32 @@ static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, · 180 unmodified lines
913915 return is_disabling(active_planes, old_crtc_state, new_crtc_state);
914916 }
915917
918+static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
919+ const struct intel_crtc_state *new_crtc_state)
920+{
921+ return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
922+ old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
923+ old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
924+ old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
925+ old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
926+}
927+
916928 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
917929 const struct intel_crtc_state *new_crtc_state)
918930 {
919− return is_enabling(vrr.enable, old_crtc_state, new_crtc_state);
931+ return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
932+ (new_crtc_state->vrr.enable &&
933+ (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
934+ vrr_params_changed(old_crtc_state, new_crtc_state)));
920935 }
921936
922937 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
923938 const struct intel_crtc_state *new_crtc_state)
924939 {
925− return is_disabling(vrr.enable, old_crtc_state, new_crtc_state);
940+ return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
941+ (old_crtc_state->vrr.enable &&
942+ (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
943+ vrr_params_changed(old_crtc_state, new_crtc_state)));
926944 }
927945
928946 #undef is_disabling
@@ -1767,7 +1785,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) · 838 unmodified lines
17671785 if (IS_DG2(dev_priv))
17681786 /* DG2's "TC1" output uses a SNPS PHY */
17691787 return false;
1770− else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
1788+ else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))
17711789 return phy >= PHY_F && phy <= PHY_I;
17721790 else if (IS_TIGERLAKE(dev_priv))
17731791 return phy >= PHY_D && phy <= PHY_I;
@@ -2570,6 +2588,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta · 796 unmodified lines
25702588 VTOTAL(crtc_vtotal - 1));
25712589 }
25722590
2591+static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2592+{
2593+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2594+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2595+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2596+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2597+ u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2598+
2599+ crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2600+ crtc_vtotal = adjusted_mode->crtc_vtotal;
2601+ crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2602+ crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2603+
2604+ drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
2605+
2606+ /*
2607+ * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2608+ * But let's write it anyway to keep the state checker happy.
2609+ */
2610+ intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2611+ VBLANK_START(crtc_vblank_start - 1) |
2612+ VBLANK_END(crtc_vblank_end - 1));
2613+ /*
2614+ * The double buffer latch point for TRANS_VTOTAL
2615+ * is the transcoder's undelayed vblank.
2616+ */
2617+ intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2618+ VACTIVE(crtc_vdisplay - 1) |
2619+ VTOTAL(crtc_vtotal - 1));
2620+}
2621+
25732622 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
25742623 {
25752624 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2869,24 +2918,6 @@ bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) · 293 unmodified lines
28692918 }
28702919 }
28712920
2872−static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
2873−{
2874− struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2875− struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2876− struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2877− enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
2878− u32 tmp;
2879−
2880− tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
2881−
2882− if (tmp & DISP_PIPE_GAMMA_ENABLE)
2883− crtc_state->gamma_enable = true;
2884−
2885− if (!HAS_GMCH(dev_priv) &&
2886− tmp & DISP_PIPE_CSC_ENABLE)
2887− crtc_state->csc_enable = true;
2888−}
2889−
28902921 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
28912922 struct intel_crtc_state *pipe_config)
28922923 {
@@ -2942,11 +2973,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, · 49 unmodified lines
29422973 (tmp & TRANSCONF_WGC_ENABLE))
29432974 pipe_config->wgc_enable = true;
29442975
2945− if (IS_CHERRYVIEW(dev_priv))
2946− pipe_config->cgm_mode = intel_de_read(dev_priv,
2947− CGM_PIPE_MODE(crtc->pipe));
2948−
2949− i9xx_get_pipe_color_config(pipe_config);
29502976 intel_color_get_config(pipe_config);
29512977
29522978 if (DISPLAY_VER(dev_priv) < 4)
@@ -3344,10 +3370,6 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, · 391 unmodified lines
33443370
33453371 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
33463372
3347− pipe_config->csc_mode = intel_de_read(dev_priv,
3348− PIPE_CSC_MODE(crtc->pipe));
3349−
3350− i9xx_get_pipe_color_config(pipe_config);
33513373 intel_color_get_config(pipe_config);
33523374
33533375 pipe_config->pixel_multiplier = 1;
@@ -3738,24 +3760,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, · 384 unmodified lines
37383760
37393761 pipe_config->sink_format = pipe_config->output_format;
37403762
3741− pipe_config->gamma_mode = intel_de_read(dev_priv,
3742− GAMMA_MODE(crtc->pipe));
3743−
3744− pipe_config->csc_mode = intel_de_read(dev_priv,
3745− PIPE_CSC_MODE(crtc->pipe));
3746−
3747− if (DISPLAY_VER(dev_priv) >= 9) {
3748− tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
3749−
3750− if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
3751− pipe_config->gamma_enable = true;
3752−
3753− if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
3754− pipe_config->csc_enable = true;
3755− } else {
3756− i9xx_get_pipe_color_config(pipe_config);
3757− }
3758−
37593763 intel_color_get_config(pipe_config);
37603764
37613765 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
@@ -4641,7 +4645,8 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, · 879 unmodified lines
46414645
46424646 static int
46434647 intel_modeset_pipe_config(struct intel_atomic_state *state,
4644− struct intel_crtc *crtc)
4648+ struct intel_crtc *crtc,
4649+ const struct intel_link_bw_limits *limits)
46454650 {
46464651 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
46474652 struct intel_crtc_state *crtc_state =
@@ -4650,7 +4655,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, · 2 unmodified lines
46504655 struct drm_connector_state *connector_state;
46514656 int pipe_src_w, pipe_src_h;
46524657 int base_bpp, ret, i;
4653− bool retry = true;
46544658
46554659 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
46564660
@@ -4673,6 +4677,16 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, · 16 unmodified lines
46734677 if (ret)
46744678 return ret;
46754679
4680+ crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4681+
4682+ if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
4683+ drm_dbg_kms(&i915->drm,
4684+ "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
4685+ crtc->base.base.id, crtc->base.name,
4686+ BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
4687+ crtc_state->bw_constrained = true;
4688+ }
4689+
46764690 base_bpp = crtc_state->pipe_bpp;
46774691
46784692 /*
@@ -4714,7 +4728,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, · 35 unmodified lines
47144728 crtc_state->output_types |= BIT(encoder->type);
47154729 }
47164730
4717−encoder_retry:
47184731 /* Ensure the port clock defaults are reset when retrying. */
47194732 crtc_state->port_clock = 0;
47204733 crtc_state->pixel_multiplier = 1;
@@ -4754,17 +4767,6 @@ encoder_retry: · 33 unmodified lines
47544767 ret = intel_crtc_compute_config(state, crtc);
47554768 if (ret == -EDEADLK)
47564769 return ret;
4757− if (ret == -EAGAIN) {
4758− if (drm_WARN(&i915->drm, !retry,
4759− "[CRTC:%d:%s] loop in pipe configuration computation\n",
4760− crtc->base.base.id, crtc->base.name))
4761− return -EINVAL;
4762−
4763− drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
4764− crtc->base.base.id, crtc->base.name);
4765− retry = false;
4766− goto encoder_retry;
4767− }
47684770 if (ret < 0) {
47694771 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
47704772 crtc->base.base.id, crtc->base.name, ret);
@@ -5111,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 340 unmodified lines
51115113 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
51125114 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
51135115 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5114− PIPE_CONF_CHECK_I(name.crtc_vtotal); \
51155116 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5116− PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
51175117 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
51185118 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5119+ if (!fastset || !pipe_config->update_lrr) { \
5120+ PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5121+ PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5122+ } \
51195123 } while (0)
51205124
51215125 #define PIPE_CONF_CHECK_RECT(name) do { \
@@ -5215,7 +5219,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 93 unmodified lines
52155219 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
52165220
52175221 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5218− if (!fastset || !pipe_config->seamless_m_n)
5222+ if (!fastset || !pipe_config->update_m_n)
52195223 PIPE_CONF_CHECK_M_N(dp_m_n);
52205224 } else {
52215225 PIPE_CONF_CHECK_M_N(dp_m_n);
@@ -5255,6 +5259,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 33 unmodified lines
52555259 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
52565260 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
52575261 PIPE_CONF_CHECK_BOOL(has_infoframe);
5262+ PIPE_CONF_CHECK_BOOL(enhanced_framing);
52585263 PIPE_CONF_CHECK_BOOL(fec_enable);
52595264
52605265 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
@@ -5352,7 +5357,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 91 unmodified lines
53525357 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
53535358 PIPE_CONF_CHECK_I(pipe_bpp);
53545359
5355− if (!fastset || !pipe_config->seamless_m_n) {
5360+ if (!fastset || !pipe_config->update_m_n) {
53565361 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
53575362 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
53585363 }
@@ -5377,6 +5382,37 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 18 unmodified lines
53775382 PIPE_CONF_CHECK_I(master_transcoder);
53785383 PIPE_CONF_CHECK_X(bigjoiner_pipes);
53795384
5385+ PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5386+ PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5387+ PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5388+ PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5389+ PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5390+ PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5391+ PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5392+ PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5393+ PIPE_CONF_CHECK_I(dsc.config.pic_width);
5394+ PIPE_CONF_CHECK_I(dsc.config.pic_height);
5395+ PIPE_CONF_CHECK_I(dsc.config.slice_width);
5396+ PIPE_CONF_CHECK_I(dsc.config.slice_height);
5397+ PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5398+ PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5399+ PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5400+ PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5401+ PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5402+ PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5403+ PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5404+ PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5405+ PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5406+ PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5407+ PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5408+ PIPE_CONF_CHECK_I(dsc.config.final_offset);
5409+ PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5410+ PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5411+ PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5412+ PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5413+ PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5414+ PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5415+
53805416 PIPE_CONF_CHECK_I(dsc.compression_enable);
53815417 PIPE_CONF_CHECK_I(dsc.dsc_split);
53825418 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
@@ -5385,13 +5421,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, · 2 unmodified lines
53855421 PIPE_CONF_CHECK_I(splitter.link_count);
53865422 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
53875423
5388− if (!fastset)
5424+ if (!fastset) {
53895425 PIPE_CONF_CHECK_BOOL(vrr.enable);
5390− PIPE_CONF_CHECK_I(vrr.vmin);
5391− PIPE_CONF_CHECK_I(vrr.vmax);
5392− PIPE_CONF_CHECK_I(vrr.flipline);
5393− PIPE_CONF_CHECK_I(vrr.pipeline_full);
5394− PIPE_CONF_CHECK_I(vrr.guardband);
5426+ PIPE_CONF_CHECK_I(vrr.vmin);
5427+ PIPE_CONF_CHECK_I(vrr.vmax);
5428+ PIPE_CONF_CHECK_I(vrr.flipline);
5429+ PIPE_CONF_CHECK_I(vrr.pipeline_full);
5430+ PIPE_CONF_CHECK_I(vrr.guardband);
5431+ }
53955432
53965433 #undef PIPE_CONF_CHECK_X
53975434 #undef PIPE_CONF_CHECK_I
@@ -5420,17 +5457,54 @@ intel_verify_planes(struct intel_atomic_state *state) · 22 unmodified lines
54205457 plane_state->uapi.visible);
54215458 }
54225459
5423−int intel_modeset_all_pipes(struct intel_atomic_state *state,
5424− const char *reason)
5460+static int intel_modeset_pipe(struct intel_atomic_state *state,
5461+ struct intel_crtc_state *crtc_state,
5462+ const char *reason)
54255463 {
5426− struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5464+ struct drm_i915_private *i915 = to_i915(state->base.dev);
5465+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5466+ int ret;
5467+
5468+ drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5469+ crtc->base.base.id, crtc->base.name, reason);
5470+
5471+ ret = drm_atomic_add_affected_connectors(&state->base,
5472+ &crtc->base);
5473+ if (ret)
5474+ return ret;
5475+
5476+ ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5477+ if (ret)
5478+ return ret;
5479+
5480+ ret = intel_atomic_add_affected_planes(state, crtc);
5481+ if (ret)
5482+ return ret;
5483+
5484+ crtc_state->uapi.mode_changed = true;
5485+
5486+ return 0;
5487+}
5488+
5489+/**
5490+ * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5491+ * @state: intel atomic state
5492+ * @reason: the reason for the full modeset
5493+ * @mask: mask of pipes to modeset
5494+ *
5495+ * Add pipes in @mask to @state and force a full modeset on the enabled ones
5496+ * due to the description in @reason.
5497+ * This function can be called only before new plane states are computed.
5498+ *
5499+ * Returns 0 in case of success, negative error code otherwise.
5500+ */
5501+int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5502+ const char *reason, u8 mask)
5503+{
5504+ struct drm_i915_private *i915 = to_i915(state->base.dev);
54275505 struct intel_crtc *crtc;
54285506
5429− /*
5430− * Add all pipes to the state, and force
5431− * a modeset on all the active ones.
5432− */
5433− for_each_intel_crtc(&dev_priv->drm, crtc) {
5507+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {
54345508 struct intel_crtc_state *crtc_state;
54355509 int ret;
54365510
@@ -5438,29 +5512,54 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state, · 1 unmodified line
54385512 if (IS_ERR(crtc_state))
54395513 return PTR_ERR(crtc_state);
54405514
5441− if (!crtc_state->hw.active ||
5515+ if (!crtc_state->hw.enable ||
54425516 intel_crtc_needs_modeset(crtc_state))
54435517 continue;
54445518
5445− drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5446− crtc->base.base.id, crtc->base.name, reason);
5447−
5448− crtc_state->uapi.mode_changed = true;
5449− crtc_state->update_pipe = false;
5450−
5451− ret = drm_atomic_add_affected_connectors(&state->base,
5452− &crtc->base);
5519+ ret = intel_modeset_pipe(state, crtc_state, reason);
54535520 if (ret)
54545521 return ret;
5522+ }
54555523
5456− ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5457− if (ret)
5458− return ret;
5524+ return 0;
5525+}
54595526
5460− ret = intel_atomic_add_affected_planes(state, crtc);
5527+/**
5528+ * intel_modeset_all_pipes_late - force a full modeset on all pipes
5529+ * @state: intel atomic state
5530+ * @reason: the reason for the full modeset
5531+ *
5532+ * Add all pipes to @state and force a full modeset on the active ones due to
5533+ * the description in @reason.
5534+ * This function can be called only after new plane states are computed already.
5535+ *
5536+ * Returns 0 in case of success, negative error code otherwise.
5537+ */
5538+int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5539+ const char *reason)
5540+{
5541+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5542+ struct intel_crtc *crtc;
5543+
5544+ for_each_intel_crtc(&dev_priv->drm, crtc) {
5545+ struct intel_crtc_state *crtc_state;
5546+ int ret;
5547+
5548+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5549+ if (IS_ERR(crtc_state))
5550+ return PTR_ERR(crtc_state);
5551+
5552+ if (!crtc_state->hw.active ||
5553+ intel_crtc_needs_modeset(crtc_state))
5554+ continue;
5555+
5556+ ret = intel_modeset_pipe(state, crtc_state, reason);
54615557 if (ret)
54625558 return ret;
54635559
5560+ crtc_state->update_pipe = false;
5561+ crtc_state->update_m_n = false;
5562+ crtc_state->update_lrr = false;
54645563 crtc_state->update_planes |= crtc_state->active_planes;
54655564 crtc_state->async_flip_planes = 0;
54665565 crtc_state->do_async_flip = false;
@@ -5564,13 +5663,25 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta · 97 unmodified lines
55645663 {
55655664 struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
55665665
5567− if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
5666+ /* only allow LRR when the timings stay within the VRR range */
5667+ if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5668+ new_crtc_state->update_lrr = false;
5669+
5670+ if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
55685671 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
5672+ else
5673+ new_crtc_state->uapi.mode_changed = false;
55695674
5570− return;
5571− }
5675+ if (intel_crtc_needs_modeset(new_crtc_state) ||
5676+ intel_compare_link_m_n(&old_crtc_state->dp_m_n,
5677+ &new_crtc_state->dp_m_n))
5678+ new_crtc_state->update_m_n = false;
5679+
5680+ if (intel_crtc_needs_modeset(new_crtc_state) ||
5681+ (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
5682+ old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
5683+ new_crtc_state->update_lrr = false;
55725684
5573− new_crtc_state->uapi.mode_changed = false;
55745685 if (!intel_crtc_needs_modeset(new_crtc_state))
55755686 new_crtc_state->update_pipe = true;
55765687 }
@@ -6171,6 +6282,101 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) · 594 unmodified lines
61716282 return 0;
61726283 }
61736284
6285+static int intel_atomic_check_config(struct intel_atomic_state *state,
6286+ struct intel_link_bw_limits *limits,
6287+ enum pipe *failed_pipe)
6288+{
6289+ struct drm_i915_private *i915 = to_i915(state->base.dev);
6290+ struct intel_crtc_state *new_crtc_state;
6291+ struct intel_crtc *crtc;
6292+ int ret;
6293+ int i;
6294+
6295+ *failed_pipe = INVALID_PIPE;
6296+
6297+ ret = intel_bigjoiner_add_affected_crtcs(state);
6298+ if (ret)
6299+ return ret;
6300+
6301+ ret = intel_fdi_add_affected_crtcs(state);
6302+ if (ret)
6303+ return ret;
6304+
6305+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6306+ if (!intel_crtc_needs_modeset(new_crtc_state)) {
6307+ if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6308+ copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6309+ else
6310+ intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6311+ continue;
6312+ }
6313+
6314+ if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6315+ drm_WARN_ON(&i915->drm, new_crtc_state->uapi.enable);
6316+ continue;
6317+ }
6318+
6319+ ret = intel_crtc_prepare_cleared_state(state, crtc);
6320+ if (ret)
6321+ break;
6322+
6323+ if (!new_crtc_state->hw.enable)
6324+ continue;
6325+
6326+ ret = intel_modeset_pipe_config(state, crtc, limits);
6327+ if (ret)
6328+ break;
6329+
6330+ ret = intel_atomic_check_bigjoiner(state, crtc);
6331+ if (ret)
6332+ break;
6333+ }
6334+
6335+ if (ret)
6336+ *failed_pipe = crtc->pipe;
6337+
6338+ return ret;
6339+}
6340+
6341+static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6342+{
6343+ struct drm_i915_private *i915 = to_i915(state->base.dev);
6344+ struct intel_link_bw_limits new_limits;
6345+ struct intel_link_bw_limits old_limits;
6346+ int ret;
6347+
6348+ intel_link_bw_init_limits(i915, &new_limits);
6349+ old_limits = new_limits;
6350+
6351+ while (true) {
6352+ enum pipe failed_pipe;
6353+
6354+ ret = intel_atomic_check_config(state, &new_limits,
6355+ &failed_pipe);
6356+ if (ret) {
6357+ /*
6358+ * The bpp limit for a pipe is below the minimum it supports, set the
6359+ * limit to the minimum and recalculate the config.
6360+ */
6361+ if (ret == -EINVAL &&
6362+ intel_link_bw_set_bpp_limit_for_pipe(state,
6363+ &old_limits,
6364+ &new_limits,
6365+ failed_pipe))
6366+ continue;
6367+
6368+ break;
6369+ }
6370+
6371+ old_limits = new_limits;
6372+
6373+ ret = intel_link_bw_atomic_check(state, &new_limits);
6374+ if (ret != -EAGAIN)
6375+ break;
6376+ }
6377+
6378+ return ret;
6379+}
61746380 /**
61756381 * intel_atomic_check - validate state object
61766382 * @dev: drm device
@@ -6215,41 +6421,10 @@ int intel_atomic_check(struct drm_device *dev, · 38 unmodified lines
62156421 return ret;
62166422 }
62176423
6218− ret = intel_bigjoiner_add_affected_crtcs(state);
6424+ ret = intel_atomic_check_config_and_link(state);
62196425 if (ret)
62206426 goto fail;
62216427
6222− for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6223− new_crtc_state, i) {
6224− if (!intel_crtc_needs_modeset(new_crtc_state)) {
6225− if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6226− copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6227− else
6228− intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6229− continue;
6230− }
6231−
6232− if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6233− drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6234− continue;
6235− }
6236−
6237− ret = intel_crtc_prepare_cleared_state(state, crtc);
6238− if (ret)
6239− goto fail;
6240−
6241− if (!new_crtc_state->hw.enable)
6242− continue;
6243−
6244− ret = intel_modeset_pipe_config(state, crtc);
6245− if (ret)
6246− goto fail;
6247−
6248− ret = intel_atomic_check_bigjoiner(state, crtc);
6249− if (ret)
6250− goto fail;
6251− }
6252−
62536428 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
62546429 new_crtc_state, i) {
62556430 if (!intel_crtc_needs_modeset(new_crtc_state))
@@ -6285,6 +6460,8 @@ int intel_atomic_check(struct drm_device *dev, · 29 unmodified lines
62856460 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
62866461 new_crtc_state->uapi.mode_changed = true;
62876462 new_crtc_state->update_pipe = false;
6463+ new_crtc_state->update_m_n = false;
6464+ new_crtc_state->update_lrr = false;
62886465 }
62896466 }
62906467
@@ -6297,6 +6474,8 @@ int intel_atomic_check(struct drm_device *dev, · 6 unmodified lines
62976474 if (intel_cpu_transcoders_need_modeset(state, trans)) {
62986475 new_crtc_state->uapi.mode_changed = true;
62996476 new_crtc_state->update_pipe = false;
6477+ new_crtc_state->update_m_n = false;
6478+ new_crtc_state->update_lrr = false;
63006479 }
63016480 }
63026481
@@ -6304,6 +6483,8 @@ int intel_atomic_check(struct drm_device *dev, · 1 unmodified line
63046483 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
63056484 new_crtc_state->uapi.mode_changed = true;
63066485 new_crtc_state->update_pipe = false;
6486+ new_crtc_state->update_m_n = false;
6487+ new_crtc_state->update_lrr = false;
63076488 }
63086489 }
63096490 }
@@ -6482,9 +6663,12 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, · 172 unmodified lines
64826663 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
64836664 hsw_set_linetime_wm(new_crtc_state);
64846665
6485− if (new_crtc_state->seamless_m_n)
6666+ if (new_crtc_state->update_m_n)
64866667 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
64876668 &new_crtc_state->dp_m_n);
6669+
6670+ if (new_crtc_state->update_lrr)
6671+ intel_set_transcoder_timings_lrr(new_crtc_state);
64886672 }
64896673
64906674 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
@@ -6521,6 +6705,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, · 30 unmodified lines
65216705 struct intel_crtc *crtc)
65226706 {
65236707 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6708+ const struct intel_crtc_state *old_crtc_state =
6709+ intel_atomic_get_old_crtc_state(state, crtc);
65246710 const struct intel_crtc_state *new_crtc_state =
65256711 intel_atomic_get_new_crtc_state(state, crtc);
65266712
@@ -6532,6 +6718,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, · 5 unmodified lines
65326718 if (DISPLAY_VER(dev_priv) >= 9 &&
65336719 !intel_crtc_needs_modeset(new_crtc_state))
65346720 skl_detach_scalers(new_crtc_state);
6721+
6722+ if (vrr_enabling(old_crtc_state, new_crtc_state))
6723+ intel_vrr_enable(new_crtc_state);
65356724 }
65366725
65376726 static void intel_enable_crtc(struct intel_atomic_state *state,
@@ -6572,12 +6761,6 @@ static void intel_update_crtc(struct intel_atomic_state *state, · 34 unmodified lines
65726761 intel_dpt_configure(crtc);
65736762 }
65746763
6575− if (vrr_enabling(old_crtc_state, new_crtc_state)) {
6576− intel_vrr_enable(new_crtc_state);
6577− intel_crtc_update_active_timings(new_crtc_state,
6578− new_crtc_state->vrr.enable);
6579− }
6580−
65816764 if (!modeset) {
65826765 if (new_crtc_state->preload_luts &&
65836766 intel_crtc_needs_color_update(new_crtc_state))
@@ -6591,6 +6774,9 @@ static void intel_update_crtc(struct intel_atomic_state *state, · 7 unmodified lines
65916774 if (DISPLAY_VER(i915) >= 11 &&
65926775 intel_crtc_needs_fastset(new_crtc_state))
65936776 icl_set_pipe_chicken(new_crtc_state);
6777+
6778+ if (vrr_params_changed(old_crtc_state, new_crtc_state))
6779+ intel_vrr_set_transcoder_timings(new_crtc_state);
65946780 }
65956781
65966782 intel_fbc_update(state, crtc);
@@ -6604,7 +6790,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, · 7 unmodified lines
66046790 intel_crtc_planes_update_noarm(state, crtc);
66056791
66066792 /* Perform vblank evasion around commit operation */
6607− intel_pipe_update_start(new_crtc_state);
6793+ intel_pipe_update_start(state, crtc);
66086794
66096795 commit_pipe_pre_planes(state, crtc);
66106796
@@ -6612,7 +6798,17 @@ static void intel_update_crtc(struct intel_atomic_state *state, · 1 unmodified line
66126798
66136799 commit_pipe_post_planes(state, crtc);
66146800
6615− intel_pipe_update_end(new_crtc_state);
6801+ intel_pipe_update_end(state, crtc);
6802+
6803+ /*
6804+ * VRR/Seamless M/N update may need to update frame timings.
6805+ *
6806+ * FIXME Should be synchronized with the start of vblank somehow...
6807+ */
6808+ if (vrr_enabling(old_crtc_state, new_crtc_state) ||
6809+ new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6810+ intel_crtc_update_active_timings(new_crtc_state,
6811+ new_crtc_state->vrr.enable);
66166812
66176813 /*
66186814 * We usually enable FIFO underrun interrupts as part of the
@@ -7072,6 +7268,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) · 453 unmodified lines
70727268 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
70737269 if (new_crtc_state->do_async_flip)
70747270 intel_crtc_disable_flip_done(state, crtc);
7271+
7272+ intel_color_wait_commit(new_crtc_state);
70757273 }
70767274
70777275 /*
drivers/gpu/drm/i915/display/intel_display.h+4−4
@@ -190,8 +190,6 @@ enum aux_ch { · 189 unmodified lines
190190 AUX_CH_E_XELPD,
191191 };
192192
193−#define aux_ch_name(a) ((a) + 'A')
194−
195193 enum phy {
196194 PHY_NONE = -1,
197195
@@ -513,8 +511,10 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); · 315 unmodified lines
513511 void intel_update_watermarks(struct drm_i915_private *i915);
514512
515513 /* modesetting */
516−int intel_modeset_all_pipes(struct intel_atomic_state *state,
517− const char *reason);
514+int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
515+ const char *reason, u8 pipe_mask);
516+int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
517+ const char *reason);
518518 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
519519 struct intel_power_domain_mask *old_domains);
520520 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
drivers/gpu/drm/i915/display/intel_display_debugfs.c+4−0
@@ -43,12 +43,16 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) · 42 unmodified lines
4343 {
4444 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4545
46+ spin_lock(&dev_priv->display.fb_tracking.lock);
47+
4648 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
4749 dev_priv->display.fb_tracking.busy_bits);
4850
4951 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
5052 dev_priv->display.fb_tracking.flip_bits);
5153
54+ spin_unlock(&dev_priv->display.fb_tracking.lock);
55+
5256 return 0;
5357 }
5458
drivers/gpu/drm/i915/display/intel_display_device.c+82−16
@@ -710,18 +710,61 @@ static const struct intel_display_device_info xe_hpd_display = { · 709 unmodified lines
710710 BIT(PORT_TC1),
711711 };
712712
713+#define XE_LPDP_FEATURES \
714+ .abox_mask = GENMASK(1, 0), \
715+ .color = { \
716+ .degamma_lut_size = 129, .gamma_lut_size = 1024, \
717+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
718+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
719+ }, \
720+ .dbuf.size = 4096, \
721+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
722+ BIT(DBUF_S4), \
723+ .has_cdclk_crawl = 1, \
724+ .has_cdclk_squash = 1, \
725+ .has_ddi = 1, \
726+ .has_dp_mst = 1, \
727+ .has_dsb = 1, \
728+ .has_fpga_dbg = 1, \
729+ .has_hotplug = 1, \
730+ .has_ipc = 1, \
731+ .has_psr = 1, \
732+ .pipe_offsets = { \
733+ [TRANSCODER_A] = PIPE_A_OFFSET, \
734+ [TRANSCODER_B] = PIPE_B_OFFSET, \
735+ [TRANSCODER_C] = PIPE_C_OFFSET, \
736+ [TRANSCODER_D] = PIPE_D_OFFSET, \
737+ }, \
738+ .trans_offsets = { \
739+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
740+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
741+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
742+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
743+ }, \
744+ TGL_CURSOR_OFFSETS, \
745+ \
746+ .__runtime_defaults.cpu_transcoder_mask = \
747+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
748+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
749+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \
750+ .__runtime_defaults.has_dmc = 1, \
751+ .__runtime_defaults.has_dsc = 1, \
752+ .__runtime_defaults.has_hdcp = 1, \
753+ .__runtime_defaults.pipe_mask = \
754+ BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
755+ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
756+ BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
757+
713758 static const struct intel_display_device_info xe_lpdp_display = {
714− XE_LPD_FEATURES,
715− .has_cdclk_crawl = 1,
716− .has_cdclk_squash = 1,
759+ XE_LPDP_FEATURES,
760+};
717761
718− .__runtime_defaults.ip.ver = 14,
719− .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
720− .__runtime_defaults.cpu_transcoder_mask =
721− BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
722− BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
723− .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
724− BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
762+static const struct intel_display_device_info xe2_lpd_display = {
763+ XE_LPDP_FEATURES,
764+
765+ .__runtime_defaults.fbc_mask =
766+ BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
767+ BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
725768 };
726769
727770 /*
@@ -803,6 +846,7 @@ static const struct { · 75 unmodified lines
803846 const struct intel_display_device_info *display;
804847 } gmdid_display_map[] = {
805848 { 14, 0, &xe_lpdp_display },
849+ { 20, 0, &xe2_lpd_display },
806850 };
807851
808852 static const struct intel_display_device_info *
@@ -850,16 +894,12 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step · 41 unmodified lines
850894 return &no_display;
851895 }
852896
853−const struct intel_display_device_info *
854−intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
855− u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
897+static const struct intel_display_device_info *
898+probe_display(struct drm_i915_private *i915)
856899 {
857900 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
858901 int i;
859902
860− if (has_gmdid)
861− return probe_gmdid_display(i915, gmdid_ver, gmdid_rel, gmdid_step);
862−
863903 if (has_no_display(pdev)) {
864904 drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
865905 return &no_display;
@@ -876,6 +916,29 @@ intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, · 10 unmodified lines
876916 return &no_display;
877917 }
878918
919+void intel_display_device_probe(struct drm_i915_private *i915)
920+{
921+ const struct intel_display_device_info *info;
922+ u16 ver, rel, step;
923+
924+ if (HAS_GMD_ID(i915))
925+ info = probe_gmdid_display(i915, &ver, &rel, &step);
926+ else
927+ info = probe_display(i915);
928+
929+ i915->display.info.__device_info = info;
930+
931+ memcpy(DISPLAY_RUNTIME_INFO(i915),
932+ &DISPLAY_INFO(i915)->__runtime_defaults,
933+ sizeof(*DISPLAY_RUNTIME_INFO(i915)));
934+
935+ if (HAS_GMD_ID(i915)) {
936+ DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
937+ DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
938+ DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
939+ }
940+}
941+
879942 void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
880943 {
881944 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
@@ -970,16 +1033,19 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915) · 88 unmodified lines
9701033 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
9711034 display_runtime->pipe_mask &= ~BIT(PIPE_B);
9721035 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
1036+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
9731037 }
9741038 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
9751039 display_runtime->pipe_mask &= ~BIT(PIPE_C);
9761040 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
1041+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
9771042 }
9781043
9791044 if (DISPLAY_VER(i915) >= 12 &&
9801045 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
9811046 display_runtime->pipe_mask &= ~BIT(PIPE_D);
9821047 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
1048+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
9831049 }
9841050
9851051 if (!display_runtime->pipe_mask)
drivers/gpu/drm/i915/display/intel_display_device.h+28−3
@@ -32,6 +32,7 @@ struct drm_printer; · 31 unmodified lines
3232 func(overlay_needs_physical); \
3333 func(supports_tv);
3434
35+#define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
3536 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
3637 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
3738 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
@@ -55,6 +56,7 @@ struct drm_printer; · 17 unmodified lines
5556 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
5657 #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
5758 #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
59+#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
5860 #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
5961 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
6062 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
@@ -71,6 +73,31 @@ struct drm_printer; · 10 unmodified lines
7173 #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
7274 #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
7375
76+/* Check that device has a display IP version within the specific range. */
77+#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
78+ BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
79+ (DISPLAY_VER_FULL(__i915) >= (from) && \
80+ DISPLAY_VER_FULL(__i915) <= (until)))
81+
82+/*
83+ * Check if a device has a specific IP version as well as a stepping within the
84+ * specified range [from, until). The lower bound is inclusive, the upper
85+ * bound is exclusive. The most common use-case of this macro is for checking
86+ * bounds for workarounds, which usually have a stepping ("from") at which the
87+ * hardware issue is first present and another stepping ("until") at which a
88+ * hardware fix is present and the software workaround is no longer necessary.
89+ * E.g.,
90+ *
91+ * IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
92+ * IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
93+ *
94+ * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
95+ * stepping bound for the specified IP version.
96+ */
97+#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
98+ (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
99+ IS_DISPLAY_STEP((__i915), (from), (until)))
100+
74101 struct intel_display_runtime_info {
75102 struct {
76103 u16 ver;
@@ -123,9 +150,7 @@ struct intel_display_device_info { · 46 unmodified lines
123150 } color;
124151 };
125152
126−const struct intel_display_device_info *
127−intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
128− u16 *ver, u16 *rel, u16 *step);
153+void intel_display_device_probe(struct drm_i915_private *i915);
129154 void intel_display_device_info_runtime_init(struct drm_i915_private *i915);
130155
131156 void intel_display_device_info_print(const struct intel_display_device_info *info,
drivers/gpu/drm/i915/display/intel_display_driver.c+8−0
@@ -31,6 +31,7 @@ · 30 unmodified lines
3131 #include "intel_display_irq.h"
3232 #include "intel_display_power.h"
3333 #include "intel_display_types.h"
34+#include "intel_display_wa.h"
3435 #include "intel_dkl_phy.h"
3536 #include "intel_dmc.h"
3637 #include "intel_dp.h"
@@ -88,6 +89,8 @@ void intel_display_driver_init_hw(struct drm_i915_private *i915) · 51 unmodified lines
8889 intel_update_cdclk(i915);
8990 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
9091 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
92+
93+ intel_display_wa_apply(i915);
9194 }
9295
9396 static const struct drm_mode_config_funcs intel_mode_funcs = {
@@ -377,6 +380,8 @@ int intel_display_driver_probe(struct drm_i915_private *i915) · 283 unmodified lines
377380
378381 void intel_display_driver_register(struct drm_i915_private *i915)
379382 {
383+ struct drm_printer p = drm_debug_printer("i915 display info:");
384+
380385 if (!HAS_DISPLAY(i915))
381386 return;
382387
@@ -404,6 +409,9 @@ void intel_display_driver_register(struct drm_i915_private *i915) · 21 unmodified lines
404409 * fbdev->async_cookie.
405410 */
406411 drm_kms_helper_poll_init(&i915->drm);
412+
413+ intel_display_device_info_print(DISPLAY_INFO(i915),
414+ DISPLAY_RUNTIME_INFO(i915), &p);
407415 }
408416
409417 /* part #1: call before irq uninstall */
drivers/gpu/drm/i915/display/intel_display_irq.c+3−1
@@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) · 791 unmodified lines
792792 {
793793 u32 mask;
794794
795− if (DISPLAY_VER(dev_priv) >= 14)
795+ if (DISPLAY_VER(dev_priv) >= 20)
796+ return 0;
797+ else if (DISPLAY_VER(dev_priv) >= 14)
796798 return TGL_DE_PORT_AUX_DDIA |
797799 TGL_DE_PORT_AUX_DDIB;
798800 else if (DISPLAY_VER(dev_priv) >= 13)
drivers/gpu/drm/i915/display/intel_display_power.c+4−6
@@ -186,8 +186,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) · 185 unmodified lines
186186 return "GMBUS";
187187 case POWER_DOMAIN_INIT:
188188 return "INIT";
189− case POWER_DOMAIN_MODESET:
190− return "MODESET";
191189 case POWER_DOMAIN_GT_IRQ:
192190 return "GT_IRQ";
193191 case POWER_DOMAIN_DC_OFF:
@@ -218,7 +216,7 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, · 24 unmodified lines
218216 struct i915_power_well *power_well;
219217 bool is_enabled;
220218
221− if (dev_priv->runtime_pm.suspended)
219+ if (pm_runtime_suspended(dev_priv->drm.dev))
222220 return false;
223221
224222 is_enabled = true;
@@ -338,8 +336,6 @@ unlock: · 113 unmodified lines
338336 mutex_unlock(&power_domains->lock);
339337 }
340338
341−#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
342−
343339 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
344340 struct intel_power_domain_mask *mask)
345341 {
@@ -947,7 +943,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, · 601 unmodified lines
947943 if (!HAS_DISPLAY(dev_priv))
948944 return 0;
949945
950− if (IS_DG2(dev_priv))
946+ if (DISPLAY_VER(dev_priv) >= 20)
947+ max_dc = 2;
948+ else if (IS_DG2(dev_priv))
951949 max_dc = 1;
952950 else if (IS_DG1(dev_priv))
953951 max_dc = 3;
drivers/gpu/drm/i915/display/intel_display_power.h+0−1
@@ -108,7 +108,6 @@ enum intel_display_power_domain { · 107 unmodified lines
108108 POWER_DOMAIN_AUX_TBT6,
109109
110110 POWER_DOMAIN_GMBUS,
111− POWER_DOMAIN_MODESET,
112111 POWER_DOMAIN_GT_IRQ,
113112 POWER_DOMAIN_DC_OFF,
114113 POWER_DOMAIN_TC_COLD_OFF,
drivers/gpu/drm/i915/display/intel_display_power_map.c+53−10
@@ -332,7 +332,6 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2, · 331 unmodified lines
332332 I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
333333 SKL_PW_2_POWER_DOMAINS,
334334 POWER_DOMAIN_AUX_A,
335− POWER_DOMAIN_MODESET,
336335 POWER_DOMAIN_GT_IRQ,
337336 POWER_DOMAIN_DC_OFF,
338337 POWER_DOMAIN_INIT);
@@ -437,7 +436,6 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off, · 98 unmodified lines
437436 BXT_PW_2_POWER_DOMAINS,
438437 POWER_DOMAIN_AUX_A,
439438 POWER_DOMAIN_GMBUS,
440− POWER_DOMAIN_MODESET,
441439 POWER_DOMAIN_GT_IRQ,
442440 POWER_DOMAIN_DC_OFF,
443441 POWER_DOMAIN_INIT);
@@ -519,7 +517,6 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off, · 75 unmodified lines
519517 GLK_PW_2_POWER_DOMAINS,
520518 POWER_DOMAIN_AUX_A,
521519 POWER_DOMAIN_GMBUS,
522− POWER_DOMAIN_MODESET,
523520 POWER_DOMAIN_GT_IRQ,
524521 POWER_DOMAIN_DC_OFF,
525522 POWER_DOMAIN_INIT);
@@ -685,7 +682,6 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2, · 159 unmodified lines
685682 I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
686683 ICL_PW_2_POWER_DOMAINS,
687684 POWER_DOMAIN_AUX_A,
688− POWER_DOMAIN_MODESET,
689685 POWER_DOMAIN_DC_OFF,
690686 POWER_DOMAIN_INIT);
691687
@@ -861,7 +857,6 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off, · 169 unmodified lines
861857 POWER_DOMAIN_AUX_A,
862858 POWER_DOMAIN_AUX_B,
863859 POWER_DOMAIN_AUX_C,
864− POWER_DOMAIN_MODESET,
865860 POWER_DOMAIN_DC_OFF,
866861 POWER_DOMAIN_INIT);
867862
@@ -1058,7 +1053,6 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off, · 190 unmodified lines
10581053 RKL_PW_3_POWER_DOMAINS,
10591054 POWER_DOMAIN_AUX_A,
10601055 POWER_DOMAIN_AUX_B,
1061− POWER_DOMAIN_MODESET,
10621056 POWER_DOMAIN_DC_OFF,
10631057 POWER_DOMAIN_INIT);
10641058
@@ -1141,7 +1135,6 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off, · 76 unmodified lines
11411135 POWER_DOMAIN_AUDIO_MMIO,
11421136 POWER_DOMAIN_AUX_A,
11431137 POWER_DOMAIN_AUX_B,
1144− POWER_DOMAIN_MODESET,
11451138 POWER_DOMAIN_DC_OFF,
11461139 POWER_DOMAIN_INIT);
11471140
@@ -1311,7 +1304,6 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, · 163 unmodified lines
13111304 POWER_DOMAIN_AUDIO_MMIO,
13121305 POWER_DOMAIN_AUX_A,
13131306 POWER_DOMAIN_AUX_B,
1314− POWER_DOMAIN_MODESET,
13151307 POWER_DOMAIN_DC_OFF,
13161308 POWER_DOMAIN_INIT);
13171309
@@ -1426,7 +1418,6 @@ I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off, · 108 unmodified lines
14261418 POWER_DOMAIN_AUDIO_MMIO,
14271419 POWER_DOMAIN_AUX_A,
14281420 POWER_DOMAIN_AUX_B,
1429− POWER_DOMAIN_MODESET,
14301421 POWER_DOMAIN_DC_OFF,
14311422 POWER_DOMAIN_INIT);
14321423
@@ -1545,6 +1536,56 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = { · 112 unmodified lines
15451536 I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
15461537 };
15471538
1539+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
1540+ POWER_DOMAIN_PORT_DDI_LANES_TC1,
1541+ POWER_DOMAIN_PORT_DDI_LANES_TC2,
1542+ POWER_DOMAIN_PORT_DDI_LANES_TC3,
1543+ POWER_DOMAIN_PORT_DDI_LANES_TC4,
1544+ POWER_DOMAIN_AUX_USBC1,
1545+ POWER_DOMAIN_AUX_USBC2,
1546+ POWER_DOMAIN_AUX_USBC3,
1547+ POWER_DOMAIN_AUX_USBC4,
1548+ POWER_DOMAIN_AUX_TBT1,
1549+ POWER_DOMAIN_AUX_TBT2,
1550+ POWER_DOMAIN_AUX_TBT3,
1551+ POWER_DOMAIN_AUX_TBT4,
1552+ POWER_DOMAIN_INIT);
1553+
1554+static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
1555+ {
1556+ .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
1557+ &xe2lpd_pwdoms_pica_tc,
1558+ .id = DISP_PW_ID_NONE),
1559+ ),
1560+ .ops = &xe2lpd_pica_power_well_ops,
1561+ },
1562+};
1563+
1564+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
1565+ POWER_DOMAIN_DC_OFF,
1566+ XELPD_PW_C_POWER_DOMAINS,
1567+ XELPD_PW_D_POWER_DOMAINS,
1568+ POWER_DOMAIN_AUDIO_MMIO,
1569+ POWER_DOMAIN_INIT);
1570+
1571+static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
1572+ {
1573+ .instances = &I915_PW_INSTANCES(
1574+ I915_PW("DC_off", &xe2lpd_pwdoms_dc_off,
1575+ .id = SKL_DISP_DC_OFF),
1576+ ),
1577+ .ops = &gen9_dc_off_power_well_ops,
1578+ },
1579+};
1580+
1581+static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
1582+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1583+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1584+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
1585+ I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
1586+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
1587+};
1588+
15481589 static void init_power_well_domains(const struct i915_power_well_instance *inst,
15491590 struct i915_power_well *power_well)
15501591 {
@@ -1652,7 +1693,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains) · 101 unmodified lines
16521693 return 0;
16531694 }
16541695
1655− if (DISPLAY_VER(i915) >= 14)
1696+ if (DISPLAY_VER(i915) >= 20)
1697+ return set_power_wells(power_domains, xe2lpd_power_wells);
1698+ else if (DISPLAY_VER(i915) >= 14)
16561699 return set_power_wells(power_domains, xelpdp_power_wells);
16571700 else if (IS_DG2(i915))
16581701 return set_power_wells(power_domains, xehpd_power_wells);
drivers/gpu/drm/i915/display/intel_display_power_well.c+49−3
@@ -1794,8 +1794,13 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv, · 1793 unmodified lines
17941794 struct i915_power_well *power_well)
17951795 {
17961796 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1797+ enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
1798+
1799+ if (intel_phy_is_tc(dev_priv, phy))
1800+ icl_tc_port_assert_ref_held(dev_priv, power_well,
1801+ aux_ch_to_digital_port(dev_priv, aux_ch));
17971802
1798− intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
1803+ intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch),
17991804 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
18001805 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
18011806
@@ -1813,7 +1818,7 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv, · 11 unmodified lines
18131818 {
18141819 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
18151820
1816− intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
1821+ intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch),
18171822 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
18181823 0);
18191824 usleep_range(10, 30);
@@ -1824,10 +1829,44 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv, · 4 unmodified lines
18241829 {
18251830 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
18261831
1827− return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
1832+ return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch)) &
18281833 XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
18291834 }
18301835
1836+static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
1837+ struct i915_power_well *power_well)
1838+{
1839+ intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL,
1840+ XE2LPD_PICA_CTL_POWER_REQUEST);
1841+
1842+ if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
1843+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
1844+ drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
1845+
1846+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
1847+ }
1848+}
1849+
1850+static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
1851+ struct i915_power_well *power_well)
1852+{
1853+ intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 0);
1854+
1855+ if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
1856+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
1857+ drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
1858+
1859+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
1860+ }
1861+}
1862+
1863+static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
1864+ struct i915_power_well *power_well)
1865+{
1866+ return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
1867+ XE2LPD_PICA_CTL_POWER_STATUS;
1868+}
1869+
18311870 const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
18321871 .sync_hw = i9xx_power_well_sync_hw_noop,
18331872 .enable = i9xx_always_on_power_well_noop,
@@ -1947,3 +1986,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = { · 113 unmodified lines
19471986 .disable = xelpdp_aux_power_well_disable,
19481987 .is_enabled = xelpdp_aux_power_well_enabled,
19491988 };
1989+
1990+const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
1991+ .sync_hw = i9xx_power_well_sync_hw_noop,
1992+ .enable = xe2lpd_pica_power_well_enable,
1993+ .disable = xe2lpd_pica_power_well_disable,
1994+ .is_enabled = xe2lpd_pica_power_well_enabled,
1995+};
drivers/gpu/drm/i915/display/intel_display_power_well.h+1−0
@@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops; · 175 unmodified lines
176176 extern const struct i915_power_well_ops icl_ddi_power_well_ops;
177177 extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
178178 extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
179+extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
179180
180181 #endif
drivers/gpu/drm/i915/display/intel_display_types.h+40−9
@@ -500,15 +500,15 @@ struct intel_hdcp_shim { · 499 unmodified lines
500500 enum hdcp_wired_protocol protocol;
501501
502502 /* Detects whether sink is HDCP2.2 capable */
503− int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
503+ int (*hdcp_2_2_capable)(struct intel_connector *connector,
504504 bool *capable);
505505
506506 /* Write HDCP2.2 messages */
507− int (*write_2_2_msg)(struct intel_digital_port *dig_port,
507+ int (*write_2_2_msg)(struct intel_connector *connector,
508508 void *buf, size_t size);
509509
510510 /* Read HDCP2.2 messages */
511− int (*read_2_2_msg)(struct intel_digital_port *dig_port,
511+ int (*read_2_2_msg)(struct intel_connector *connector,
512512 u8 msg_id, void *buf, size_t size);
513513
514514 /*
@@ -516,7 +516,7 @@ struct intel_hdcp_shim { · 1 unmodified line
516516 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
517517 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
518518 */
519− int (*config_stream_type)(struct intel_digital_port *dig_port,
519+ int (*config_stream_type)(struct intel_connector *connector,
520520 bool is_repeater, u8 type);
521521
522522 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
@@ -1083,6 +1083,8 @@ struct intel_crtc_state { · 560 unmodified lines
10831083
10841084 unsigned fb_bits; /* framebuffers to flip */
10851085 bool update_pipe; /* can a fast modeset be performed? */
1086+ bool update_m_n; /* update M/N seamlessly during fastset? */
1087+ bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
10861088 bool disable_cxsr;
10871089 bool update_wm_pre, update_wm_post; /* watermarks are updated */
10881090 bool fifo_changed; /* FIFO split is changed */
@@ -1189,13 +1191,13 @@ struct intel_crtc_state { · 100 unmodified lines
11891191 u32 ctrl, div;
11901192 } dsi_pll;
11911193
1192− int pipe_bpp;
1194+ int max_link_bpp_x16; /* in 1/16 bpp units */
1195+ int pipe_bpp; /* in 1 bpp units */
11931196 struct intel_link_m_n dp_m_n;
11941197
11951198 /* m2_n2 for eDP downclock */
11961199 struct intel_link_m_n dp_m2_n2;
11971200 bool has_drrs;
1198− bool seamless_m_n;
11991201
12001202 /* PSR is supported but might not be enabled due the lack of enabled planes */
12011203 bool has_psr;
@@ -1362,7 +1364,14 @@ struct intel_crtc_state { · 160 unmodified lines
13621364 u16 linetime;
13631365 u16 ips_linetime;
13641366
1365− /* Forward Error correction State */
1367+ bool enhanced_framing;
1368+
1369+ /*
1370+ * Forward Error Correction.
1371+ *
1372+ * Note: This will be false for 128b/132b, which will always have FEC
1373+ * enabled automatically.
1374+ */
13661375 bool fec_enable;
13671376
13681377 bool sdp_split_enable;
@@ -1383,7 +1392,7 @@ struct intel_crtc_state { · 14 unmodified lines
13831392
13841393 /* Variable Refresh Rate state */
13851394 struct {
1386− bool enable;
1395+ bool enable, in_range;
13871396 u8 pipeline_full;
13881397 u16 flipline, vmin, vmax, guardband;
13891398 } vrr;
@@ -1581,7 +1590,6 @@ struct intel_watermark_params { · 191 unmodified lines
15811590
15821591 struct intel_hdmi {
15831592 i915_reg_t hdmi_reg;
1584− int ddc_bus;
15851593 struct {
15861594 enum drm_dp_dual_mode_type type;
15871595 int max_tmds_clock;
@@ -2108,4 +2116,27 @@ to_intel_frontbuffer(struct drm_framebuffer *fb) · 520 unmodified lines
21082116 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
21092117 }
21102118
2119+static inline int to_bpp_int(int bpp_x16)
2120+{
2121+ return bpp_x16 >> 4;
2122+}
2123+
2124+static inline int to_bpp_frac(int bpp_x16)
2125+{
2126+ return bpp_x16 & 0xf;
2127+}
2128+
2129+#define BPP_X16_FMT "%d.%04d"
2130+#define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625)
2131+
2132+static inline int to_bpp_int_roundup(int bpp_x16)
2133+{
2134+ return (bpp_x16 + 0xf) >> 4;
2135+}
2136+
2137+static inline int to_bpp_x16(int bpp)
2138+{
2139+ return bpp << 4;
2140+}
2141+
21112142 #endif /* __INTEL_DISPLAY_TYPES_H__ */
drivers/gpu/drm/i915/display/intel_display_wa.c+48−0
@@ -0,0 +1,48 @@
1+// SPDX-License-Identifier: MIT
2+/*
3+ * Copyright © 2023 Intel Corporation
4+ */
5+
6+#include "i915_drv.h"
7+#include "i915_reg.h"
8+#include "intel_de.h"
9+#include "intel_display_wa.h"
10+
11+static void gen11_display_wa_apply(struct drm_i915_private *i915)
12+{
13+ /* Wa_1409120013 */
14+ intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
15+ DPFC_CHICKEN_COMP_DUMMY_PIXEL);
16+
17+ /* Wa_14010594013 */
18+ intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
19+}
20+
21+static void xe_d_display_wa_apply(struct drm_i915_private *i915)
22+{
23+ /* Wa_1409120013 */
24+ intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
25+ DPFC_CHICKEN_COMP_DUMMY_PIXEL);
26+
27+ /* Wa_14013723622 */
28+ intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
29+}
30+
31+static void adlp_display_wa_apply(struct drm_i915_private *i915)
32+{
33+ /* Wa_22011091694:adlp */
34+ intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
35+
36+ /* Bspec/49189 Initialize Sequence */
37+ intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
38+}
39+
40+void intel_display_wa_apply(struct drm_i915_private *i915)
41+{
42+ if (IS_ALDERLAKE_P(i915))
43+ adlp_display_wa_apply(i915);
44+ else if (DISPLAY_VER(i915) == 12)
45+ xe_d_display_wa_apply(i915);
46+ else if (DISPLAY_VER(i915) == 11)
47+ gen11_display_wa_apply(i915);
48+}
drivers/gpu/drm/i915/display/intel_display_wa.h+13−0
@@ -0,0 +1,13 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2023 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_DISPLAY_WA_H__
7+#define __INTEL_DISPLAY_WA_H__
8+
9+struct drm_i915_private;
10+
11+void intel_display_wa_apply(struct drm_i915_private *i915);
12+
13+#endif
drivers/gpu/drm/i915/display/intel_dmc.c+1−1
@@ -998,7 +998,7 @@ void intel_dmc_init(struct drm_i915_private *i915) · 997 unmodified lines
998998
999999 INIT_WORK(&dmc->work, dmc_load_work_fn);
10001000
1001− if (IS_METEORLAKE(i915)) {
1001+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
10021002 dmc->fw_path = MTL_DMC_PATH;
10031003 dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
10041004 } else if (IS_DG2(i915)) {
drivers/gpu/drm/i915/display/intel_dp.c+676−201
@@ -306,13 +306,13 @@ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) · 305 unmodified lines
306306 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
307307 int source_max = intel_dp_max_source_lane_count(dig_port);
308308 int sink_max = intel_dp->max_sink_lane_count;
309− int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
309+ int lane_max = intel_tc_port_max_lane_count(dig_port);
310310 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
311311
312312 if (lttpr_max)
313313 sink_max = min(sink_max, lttpr_max);
314314
315− return min3(source_max, sink_max, fia_max);
315+ return min3(source_max, sink_max, lane_max);
316316 }
317317
318318 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
@@ -740,14 +740,41 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p · 421 unmodified lines
740740 return bits_per_pixel;
741741 }
742742
743−u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
744− u32 link_clock, u32 lane_count,
745− u32 mode_clock, u32 mode_hdisplay,
746− bool bigjoiner,
747− u32 pipe_bpp,
748− u32 timeslots)
743+static
744+u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
745+ u32 mode_clock, u32 mode_hdisplay,
746+ bool bigjoiner)
747+{
748+ u32 max_bpp_small_joiner_ram;
749+
750+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
751+ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
752+
753+ if (bigjoiner) {
754+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
755+ /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
756+ int ppc = 2;
757+ u32 max_bpp_bigjoiner =
758+ i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
759+ intel_dp_mode_to_fec_clock(mode_clock);
760+
761+ max_bpp_small_joiner_ram *= 2;
762+
763+ return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
764+ }
765+
766+ return max_bpp_small_joiner_ram;
767+}
768+
769+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
770+ u32 link_clock, u32 lane_count,
771+ u32 mode_clock, u32 mode_hdisplay,
772+ bool bigjoiner,
773+ enum intel_output_format output_format,
774+ u32 pipe_bpp,
775+ u32 timeslots)
749776 {
750− u32 bits_per_pixel, max_bpp_small_joiner_ram;
777+ u32 bits_per_pixel, joiner_max_bpp;
751778
752779 /*
753780 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
@@ -768,40 +795,32 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, · 14 unmodified lines
768795 bits_per_pixel = ((link_clock * lane_count) * timeslots) /
769796 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
770797
798+ /* Bandwidth required for 420 is half, that of 444 format */
799+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
800+ bits_per_pixel *= 2;
801+
802+ /*
803+ * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
804+ * supported PPS value can be 63.9375 and with the further
805+ * mention that for 420, 422 formats, bpp should be programmed double
806+ * the target bpp restricting our target bpp to be 31.9375 at max.
807+ */
808+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
809+ bits_per_pixel = min_t(u32, bits_per_pixel, 31);
810+
771811 drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
772812 "total bw %u pixel clock %u\n",
773813 bits_per_pixel, timeslots,
774814 (link_clock * lane_count * 8),
775815 intel_dp_mode_to_fec_clock(mode_clock));
776816
777− /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
778− max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
779− mode_hdisplay;
780−
781− if (bigjoiner)
782− max_bpp_small_joiner_ram *= 2;
783−
784− /*
785− * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
786− * check, output bpp from small joiner RAM check)
787− */
788− bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
789−
790− if (bigjoiner) {
791− u32 max_bpp_bigjoiner =
792− i915->display.cdclk.max_cdclk_freq * 48 /
793− intel_dp_mode_to_fec_clock(mode_clock);
794−
795− bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
796− }
817+ joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
818+ mode_hdisplay, bigjoiner);
819+ bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
797820
798821 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
799822
800− /*
801− * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
802− * fractional part is 0
803− */
804− return bits_per_pixel << 4;
823+ return bits_per_pixel;
805824 }
806825
807826 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@@ -916,16 +935,42 @@ dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, · 108 unmodified lines
916935 return false;
917936 }
918937
938+static bool
939+dfp_can_convert(struct intel_dp *intel_dp,
940+ enum intel_output_format output_format,
941+ enum intel_output_format sink_format)
942+{
943+ switch (output_format) {
944+ case INTEL_OUTPUT_FORMAT_RGB:
945+ return dfp_can_convert_from_rgb(intel_dp, sink_format);
946+ case INTEL_OUTPUT_FORMAT_YCBCR444:
947+ return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
948+ default:
949+ MISSING_CASE(output_format);
950+ return false;
951+ }
952+
953+ return false;
954+}
955+
919956 static enum intel_output_format
920957 intel_dp_output_format(struct intel_connector *connector,
921958 enum intel_output_format sink_format)
922959 {
923960 struct intel_dp *intel_dp = intel_attached_dp(connector);
924961 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
962+ enum intel_output_format force_dsc_output_format =
963+ intel_dp->force_dsc_output_format;
925964 enum intel_output_format output_format;
965+ if (force_dsc_output_format) {
966+ if (source_can_output(intel_dp, force_dsc_output_format) &&
967+ (!drm_dp_is_branch(intel_dp->dpcd) ||
968+ sink_format != force_dsc_output_format ||
969+ dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
970+ return force_dsc_output_format;
926971
927− if (intel_dp->force_dsc_output_format)
928− return intel_dp->force_dsc_output_format;
972+ drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
973+ }
929974
930975 if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
931976 dfp_can_convert_from_rgb(intel_dp, sink_format))
@@ -951,7 +996,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format) · 19 unmodified lines
951996 return 8 * 3;
952997 }
953998
954−static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
999+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
9551000 {
9561001 /*
9571002 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
@@ -1122,7 +1167,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, · 164 unmodified lines
11221167 int target_clock = mode->clock;
11231168 int max_rate, mode_rate, max_lanes, max_link_clock;
11241169 int max_dotclk = dev_priv->max_dotclk_freq;
1125− u16 dsc_max_output_bpp = 0;
1170+ u16 dsc_max_compressed_bpp = 0;
11261171 u8 dsc_slice_count = 0;
11271172 enum drm_mode_status status;
11281173 bool dsc = false, bigjoiner = false;
@@ -1161,31 +1206,37 @@ intel_dp_mode_valid(struct drm_connector *_connector, · 32 unmodified lines
11611206
11621207 if (HAS_DSC(dev_priv) &&
11631208 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1209+ enum intel_output_format sink_format, output_format;
1210+ int pipe_bpp;
1211+
1212+ sink_format = intel_dp_sink_format(connector, mode);
1213+ output_format = intel_dp_output_format(connector, sink_format);
11641214 /*
11651215 * TBD pass the connector BPC,
11661216 * for now U8_MAX so that max BPC on that platform would be picked
11671217 */
1168− int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1218+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
11691219
11701220 /*
11711221 * Output bpp is stored in 6.4 format so right shift by 4 to get the
11721222 * integer value since we support only integer values of bpp.
11731223 */
11741224 if (intel_dp_is_edp(intel_dp)) {
1175− dsc_max_output_bpp =
1225+ dsc_max_compressed_bpp =
11761226 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
11771227 dsc_slice_count =
11781228 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
11791229 true);
11801230 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1181− dsc_max_output_bpp =
1182− intel_dp_dsc_get_output_bpp(dev_priv,
1183− max_link_clock,
1184− max_lanes,
1185− target_clock,
1186− mode->hdisplay,
1187− bigjoiner,
1188− pipe_bpp, 64) >> 4;
1231+ dsc_max_compressed_bpp =
1232+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1233+ max_link_clock,
1234+ max_lanes,
1235+ target_clock,
1236+ mode->hdisplay,
1237+ bigjoiner,
1238+ output_format,
1239+ pipe_bpp, 64);
11891240 dsc_slice_count =
11901241 intel_dp_dsc_get_slice_count(intel_dp,
11911242 target_clock,
@@ -1193,7 +1244,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, · 1 unmodified line
11931244 bigjoiner);
11941245 }
11951246
1196− dsc = dsc_max_output_bpp && dsc_slice_count;
1247+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
11971248 }
11981249
11991250 /*
@@ -1306,13 +1357,13 @@ bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) · 106 unmodified lines
13061357 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
13071358 const struct intel_crtc_state *pipe_config)
13081359 {
1360+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
13091361 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
13101362
1311− /* On TGL, FEC is supported on all Pipes */
13121363 if (DISPLAY_VER(dev_priv) >= 12)
13131364 return true;
13141365
1315− if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1366+ if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
13161367 return true;
13171368
13181369 return false;
@@ -1419,7 +1470,7 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, · 100 unmodified lines
14191470 if (intel_dp->compliance.test_data.bpc != 0) {
14201471 int bpp = 3 * intel_dp->compliance.test_data.bpc;
14211472
1422− limits->min_bpp = limits->max_bpp = bpp;
1473+ limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
14231474 pipe_config->dither_force_disable = bpp == 6 * 3;
14241475
14251476 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
@@ -1481,10 +1532,12 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, · 55 unmodified lines
14811532 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
14821533 int mode_rate, link_rate, link_avail;
14831534
1484− for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1485− int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1535+ for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1536+ bpp >= to_bpp_int(limits->link.min_bpp_x16);
1537+ bpp -= 2 * 3) {
1538+ int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
14861539
1487− mode_rate = intel_dp_link_required(clock, output_bpp);
1540+ mode_rate = intel_dp_link_required(clock, link_bpp);
14881541
14891542 for (i = 0; i < intel_dp->num_common_rates; i++) {
14901543 link_rate = intel_dp_common_rate(intel_dp, i);
@@ -1512,18 +1565,31 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, · 21 unmodified lines
15121565 return -EINVAL;
15131566 }
15141567
1515−int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1568+static
1569+u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1570+{
1571+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1572+ if (DISPLAY_VER(i915) >= 12)
1573+ return 12;
1574+ if (DISPLAY_VER(i915) == 11)
1575+ return 10;
1576+
1577+ return 0;
1578+}
1579+
1580+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
15161581 {
15171582 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
15181583 int i, num_bpc;
15191584 u8 dsc_bpc[3] = {0};
15201585 u8 dsc_max_bpc;
15211586
1522− /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1523− if (DISPLAY_VER(i915) >= 12)
1524− dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1525− else
1526− dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1587+ dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1588+
1589+ if (!dsc_max_bpc)
1590+ return dsc_max_bpc;
1591+
1592+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
15271593
15281594 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
15291595 dsc_bpc);
@@ -1651,6 +1717,387 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, · 121 unmodified lines
16511717 return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
16521718 }
16531719
1720+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
1721+ u32 lane_count, u32 mode_clock,
1722+ enum intel_output_format output_format,
1723+ int timeslots)
1724+{
1725+ u32 available_bw, required_bw;
1726+
1727+ available_bw = (link_clock * lane_count * timeslots) / 8;
1728+ required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
1729+
1730+ return available_bw > required_bw;
1731+}
1732+
1733+static int dsc_compute_link_config(struct intel_dp *intel_dp,
1734+ struct intel_crtc_state *pipe_config,
1735+ struct link_config_limits *limits,
1736+ u16 compressed_bpp,
1737+ int timeslots)
1738+{
1739+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1740+ int link_rate, lane_count;
1741+ int i;
1742+
1743+ for (i = 0; i < intel_dp->num_common_rates; i++) {
1744+ link_rate = intel_dp_common_rate(intel_dp, i);
1745+ if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1746+ continue;
1747+
1748+ for (lane_count = limits->min_lane_count;
1749+ lane_count <= limits->max_lane_count;
1750+ lane_count <<= 1) {
1751+ if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
1752+ adjusted_mode->clock,
1753+ pipe_config->output_format,
1754+ timeslots))
1755+ continue;
1756+
1757+ pipe_config->lane_count = lane_count;
1758+ pipe_config->port_clock = link_rate;
1759+
1760+ return 0;
1761+ }
1762+ }
1763+
1764+ return -EINVAL;
1765+}
1766+
1767+static
1768+u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
1769+ struct intel_crtc_state *pipe_config,
1770+ int bpc)
1771+{
1772+ u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd);
1773+
1774+ if (max_bppx16)
1775+ return max_bppx16;
1776+ /*
1777+ * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1778+ * values as given in spec Table 2-157 DP v2.0
1779+ */
1780+ switch (pipe_config->output_format) {
1781+ case INTEL_OUTPUT_FORMAT_RGB:
1782+ case INTEL_OUTPUT_FORMAT_YCBCR444:
1783+ return (3 * bpc) << 4;
1784+ case INTEL_OUTPUT_FORMAT_YCBCR420:
1785+ return (3 * (bpc / 2)) << 4;
1786+ default:
1787+ MISSING_CASE(pipe_config->output_format);
1788+ break;
1789+ }
1790+
1791+ return 0;
1792+}
1793+
1794+static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1795+{
1796+ /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1797+ switch (pipe_config->output_format) {
1798+ case INTEL_OUTPUT_FORMAT_RGB:
1799+ case INTEL_OUTPUT_FORMAT_YCBCR444:
1800+ return 8;
1801+ case INTEL_OUTPUT_FORMAT_YCBCR420:
1802+ return 6;
1803+ default:
1804+ MISSING_CASE(pipe_config->output_format);
1805+ break;
1806+ }
1807+
1808+ return 0;
1809+}
1810+
1811+static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
1812+ struct intel_crtc_state *pipe_config,
1813+ int bpc)
1814+{
1815+ return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
1816+ pipe_config, bpc) >> 4;
1817+}
1818+
1819+static int dsc_src_min_compressed_bpp(void)
1820+{
1821+ /* Min Compressed bpp supported by source is 8 */
1822+ return 8;
1823+}
1824+
1825+static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1826+{
1827+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1828+
1829+ /*
1830+ * Max Compressed bpp for Gen 13+ is 27bpp.
1831+ * For earlier platform is 23bpp. (Bspec:49259).
1832+ */
1833+ if (DISPLAY_VER(i915) <= 12)
1834+ return 23;
1835+ else
1836+ return 27;
1837+}
1838+
1839+/*
1840+ * From a list of valid compressed bpps try different compressed bpp and find a
1841+ * suitable link configuration that can support it.
1842+ */
1843+static int
1844+icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1845+ struct intel_crtc_state *pipe_config,
1846+ struct link_config_limits *limits,
1847+ int dsc_max_bpp,
1848+ int dsc_min_bpp,
1849+ int pipe_bpp,
1850+ int timeslots)
1851+{
1852+ int i, ret;
1853+
1854+ /* Compressed BPP should be less than the Input DSC bpp */
1855+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1856+
1857+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1858+ if (valid_dsc_bpp[i] < dsc_min_bpp ||
1859+ valid_dsc_bpp[i] > dsc_max_bpp)
1860+ break;
1861+
1862+ ret = dsc_compute_link_config(intel_dp,
1863+ pipe_config,
1864+ limits,
1865+ valid_dsc_bpp[i],
1866+ timeslots);
1867+ if (ret == 0) {
1868+ pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
1869+ return 0;
1870+ }
1871+ }
1872+
1873+ return -EINVAL;
1874+}
1875+
1876+/*
1877+ * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1878+ * uncompressed bpp-1. So we start from max compressed bpp and see if any
1879+ * link configuration is able to support that compressed bpp, if not we
1880+ * step down and check for lower compressed bpp.
1881+ */
1882+static int
1883+xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1884+ struct intel_crtc_state *pipe_config,
1885+ struct link_config_limits *limits,
1886+ int dsc_max_bpp,
1887+ int dsc_min_bpp,
1888+ int pipe_bpp,
1889+ int timeslots)
1890+{
1891+ u16 compressed_bpp;
1892+ int ret;
1893+
1894+ /* Compressed BPP should be less than the Input DSC bpp */
1895+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1896+
1897+ for (compressed_bpp = dsc_max_bpp;
1898+ compressed_bpp >= dsc_min_bpp;
1899+ compressed_bpp--) {
1900+ ret = dsc_compute_link_config(intel_dp,
1901+ pipe_config,
1902+ limits,
1903+ compressed_bpp,
1904+ timeslots);
1905+ if (ret == 0) {
1906+ pipe_config->dsc.compressed_bpp = compressed_bpp;
1907+ return 0;
1908+ }
1909+ }
1910+ return -EINVAL;
1911+}
1912+
1913+static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1914+ struct intel_crtc_state *pipe_config,
1915+ struct link_config_limits *limits,
1916+ int pipe_bpp,
1917+ int timeslots)
1918+{
1919+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1920+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1921+ int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
1922+ int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
1923+ int dsc_joiner_max_bpp;
1924+
1925+ dsc_src_min_bpp = dsc_src_min_compressed_bpp();
1926+ dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
1927+ dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
1928+ dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
1929+
1930+ dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
1931+ dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
1932+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
1933+
1934+ dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
1935+ adjusted_mode->hdisplay,
1936+ pipe_config->bigjoiner_pipes);
1937+ dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
1938+ dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
1939+
1940+ if (DISPLAY_VER(i915) >= 13)
1941+ return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits,
1942+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
1943+ return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
1944+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
1945+}
1946+
1947+static
1948+u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
1949+{
1950+ /* Min DSC Input BPC for ICL+ is 8 */
1951+ return HAS_DSC(i915) ? 8 : 0;
1952+}
1953+
1954+static
1955+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
1956+ struct drm_connector_state *conn_state,
1957+ struct link_config_limits *limits,
1958+ int pipe_bpp)
1959+{
1960+ u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
1961+
1962+ dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
1963+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
1964+
1965+ dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
1966+ dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
1967+
1968+ return pipe_bpp >= dsc_min_pipe_bpp &&
1969+ pipe_bpp <= dsc_max_pipe_bpp;
1970+}
1971+
1972+static
1973+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
1974+ struct drm_connector_state *conn_state,
1975+ struct link_config_limits *limits)
1976+{
1977+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1978+ int forced_bpp;
1979+
1980+ if (!intel_dp->force_dsc_bpc)
1981+ return 0;
1982+
1983+ forced_bpp = intel_dp->force_dsc_bpc * 3;
1984+
1985+ if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
1986+ drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
1987+ return forced_bpp;
1988+ }
1989+
1990+ drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
1991+ intel_dp->force_dsc_bpc);
1992+
1993+ return 0;
1994+}
1995+
1996+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
1997+ struct intel_crtc_state *pipe_config,
1998+ struct drm_connector_state *conn_state,
1999+ struct link_config_limits *limits,
2000+ int timeslots)
2001+{
2002+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2003+ u8 max_req_bpc = conn_state->max_requested_bpc;
2004+ u8 dsc_max_bpc, dsc_max_bpp;
2005+ u8 dsc_min_bpc, dsc_min_bpp;
2006+ u8 dsc_bpc[3] = {0};
2007+ int forced_bpp, pipe_bpp;
2008+ int num_bpc, i, ret;
2009+
2010+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2011+
2012+ if (forced_bpp) {
2013+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
2014+ limits, forced_bpp, timeslots);
2015+ if (ret == 0) {
2016+ pipe_config->pipe_bpp = forced_bpp;
2017+ return 0;
2018+ }
2019+ }
2020+
2021+ dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2022+ if (!dsc_max_bpc)
2023+ return -EINVAL;
2024+
2025+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2026+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2027+
2028+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2029+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2030+
2031+ /*
2032+ * Get the maximum DSC bpc that will be supported by any valid
2033+ * link configuration and compressed bpp.
2034+ */
2035+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc);
2036+ for (i = 0; i < num_bpc; i++) {
2037+ pipe_bpp = dsc_bpc[i] * 3;
2038+ if (pipe_bpp < dsc_min_bpp)
2039+ break;
2040+ if (pipe_bpp > dsc_max_bpp)
2041+ continue;
2042+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
2043+ limits, pipe_bpp, timeslots);
2044+ if (ret == 0) {
2045+ pipe_config->pipe_bpp = pipe_bpp;
2046+ return 0;
2047+ }
2048+ }
2049+
2050+ return -EINVAL;
2051+}
2052+
2053+static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2054+ struct intel_crtc_state *pipe_config,
2055+ struct drm_connector_state *conn_state,
2056+ struct link_config_limits *limits)
2057+{
2058+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2059+ int pipe_bpp, forced_bpp;
2060+ int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2061+ int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2062+
2063+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2064+
2065+ if (forced_bpp) {
2066+ pipe_bpp = forced_bpp;
2067+ } else {
2068+ int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2069+
2070+ /* For eDP use max bpp that can be supported with DSC. */
2071+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bpc);
2072+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2073+ drm_dbg_kms(&i915->drm,
2074+ "Computed BPC is not in DSC BPC limits\n");
2075+ return -EINVAL;
2076+ }
2077+ }
2078+ pipe_config->port_clock = limits->max_rate;
2079+ pipe_config->lane_count = limits->max_lane_count;
2080+
2081+ dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2082+ dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
2083+ dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2084+ dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2085+
2086+ dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2087+ dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
2088+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2089+ dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2090+
2091+ /* Compressed BPP should be less than the Input DSC bpp */
2092+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2093+
2094+ pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
2095+
2096+ pipe_config->pipe_bpp = pipe_bpp;
2097+
2098+ return 0;
2099+}
2100+
16542101 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
16552102 struct intel_crtc_state *pipe_config,
16562103 struct drm_connector_state *conn_state,
@@ -1662,7 +2109,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, · 5 unmodified lines
16622109 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
16632110 const struct drm_display_mode *adjusted_mode =
16642111 &pipe_config->hw.adjusted_mode;
1665− int pipe_bpp;
16662112 int ret;
16672113
16682114 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1674,36 +2120,28 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, · 5 unmodified lines
16742120 if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
16752121 return -EINVAL;
16762122
1677− if (compute_pipe_bpp)
1678− pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1679− else
1680− pipe_bpp = pipe_config->pipe_bpp;
1681−
1682− if (intel_dp->force_dsc_bpc) {
1683− pipe_bpp = intel_dp->force_dsc_bpc * 3;
1684− drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
1685− }
1686−
1687− /* Min Input BPC for ICL+ is 8 */
1688− if (pipe_bpp < 8 * 3) {
1689− drm_dbg_kms(&dev_priv->drm,
1690− "No DSC support for less than 8bpc\n");
1691− return -EINVAL;
1692− }
1693−
16942123 /*
1695− * For now enable DSC for max bpp, max link rate, max lane count.
1696− * Optimize this later for the minimum possible link rate/lane count
1697− * with DSC enabled for the requested mode.
2124+ * compute pipe bpp is set to false for DP MST DSC case
2125+ * and compressed_bpp is calculated same time once
2126+ * vpci timeslots are allocated, because overall bpp
2127+ * calculation procedure is bit different for MST case.
16982128 */
1699− pipe_config->pipe_bpp = pipe_bpp;
1700− pipe_config->port_clock = limits->max_rate;
1701− pipe_config->lane_count = limits->max_lane_count;
2129+ if (compute_pipe_bpp) {
2130+ if (intel_dp_is_edp(intel_dp))
2131+ ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2132+ conn_state, limits);
2133+ else
2134+ ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2135+ conn_state, limits, timeslots);
2136+ if (ret) {
2137+ drm_dbg_kms(&dev_priv->drm,
2138+ "No Valid pipe bpp for given mode ret = %d\n", ret);
2139+ return ret;
2140+ }
2141+ }
17022142
2143+ /* Calculate Slice count */
17032144 if (intel_dp_is_edp(intel_dp)) {
1704− pipe_config->dsc.compressed_bpp =
1705− min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1706− pipe_config->pipe_bpp);
17072145 pipe_config->dsc.slice_count =
17082146 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
17092147 true);
@@ -1713,34 +2151,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, · 3 unmodified lines
17132151 return -EINVAL;
17142152 }
17152153 } else {
1716− u16 dsc_max_output_bpp = 0;
17172154 u8 dsc_dp_slice_count;
17182155
1719− if (compute_pipe_bpp) {
1720− dsc_max_output_bpp =
1721− intel_dp_dsc_get_output_bpp(dev_priv,
1722− pipe_config->port_clock,
1723− pipe_config->lane_count,
1724− adjusted_mode->crtc_clock,
1725− adjusted_mode->crtc_hdisplay,
1726− pipe_config->bigjoiner_pipes,
1727− pipe_bpp,
1728− timeslots);
1729− /*
1730− * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
1731− * supported PPS value can be 63.9375 and with the further
1732− * mention that bpp should be programmed double the target bpp
1733− * restricting our target bpp to be 31.9375 at max
1734− */
1735− if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1736− dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
1737−
1738− if (!dsc_max_output_bpp) {
1739− drm_dbg_kms(&dev_priv->drm,
1740− "Compressed BPP not supported\n");
1741− return -EINVAL;
1742− }
1743− }
17442156 dsc_dp_slice_count =
17452157 intel_dp_dsc_get_slice_count(intel_dp,
17462158 adjusted_mode->crtc_clock,
@@ -1752,21 +2164,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, · 5 unmodified lines
17522164 return -EINVAL;
17532165 }
17542166
1755− /*
1756− * compute pipe bpp is set to false for DP MST DSC case
1757− * and compressed_bpp is calculated same time once
1758− * vpci timeslots are allocated, because overall bpp
1759− * calculation procedure is bit different for MST case.
1760− */
1761− if (compute_pipe_bpp) {
1762− pipe_config->dsc.compressed_bpp = min_t(u16,
1763− dsc_max_output_bpp >> 4,
1764− pipe_config->pipe_bpp);
1765− }
17662167 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1767− drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
1768− pipe_config->dsc.compressed_bpp,
1769− pipe_config->dsc.slice_count);
17702168 }
17712169 /*
17722170 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
@@ -1796,29 +2194,82 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, · 23 unmodified lines
17962194 return 0;
17972195 }
17982196
1799−static int
1800−intel_dp_compute_link_config(struct intel_encoder *encoder,
1801− struct intel_crtc_state *pipe_config,
1802− struct drm_connector_state *conn_state,
1803− bool respect_downstream_limits)
2197+/**
2198+ * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2199+ * @intel_dp: intel DP
2200+ * @crtc_state: crtc state
2201+ * @dsc: DSC compression mode
2202+ * @limits: link configuration limits
2203+ *
2204+ * Calculates the output link min, max bpp values in @limits based on the
2205+ * pipe bpp range, @crtc_state and @dsc mode.
2206+ *
2207+ * Returns %true in case of success.
2208+ */
2209+bool
2210+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2211+ const struct intel_crtc_state *crtc_state,
2212+ bool dsc,
2213+ struct link_config_limits *limits)
18042214 {
1805− struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1806− struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2215+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
18072216 const struct drm_display_mode *adjusted_mode =
1808− &pipe_config->hw.adjusted_mode;
1809− struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1810− struct link_config_limits limits;
1811− bool joiner_needs_dsc = false;
1812− int ret;
2217+ &crtc_state->hw.adjusted_mode;
2218+ const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2219+ const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2220+ int max_link_bpp_x16;
2221+
2222+ max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2223+ to_bpp_x16(limits->pipe.max_bpp));
2224+
2225+ if (!dsc) {
2226+ max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2227+
2228+ if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2229+ return false;
2230+
2231+ limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2232+ } else {
2233+ /*
2234+ * TODO: set the DSC link limits already here, atm these are
2235+ * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2236+ * intel_dp_dsc_compute_pipe_bpp()
2237+ */
2238+ limits->link.min_bpp_x16 = 0;
2239+ }
2240+
2241+ limits->link.max_bpp_x16 = max_link_bpp_x16;
2242+
2243+ drm_dbg_kms(&i915->drm,
2244+ "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2245+ encoder->base.base.id, encoder->base.name,
2246+ crtc->base.base.id, crtc->base.name,
2247+ adjusted_mode->crtc_clock,
2248+ dsc ? "on" : "off",
2249+ limits->max_lane_count,
2250+ limits->max_rate,
2251+ limits->pipe.max_bpp,
2252+ BPP_X16_ARGS(limits->link.max_bpp_x16));
18132253
1814− limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1815− limits.max_rate = intel_dp_max_link_rate(intel_dp);
2254+ return true;
2255+}
2256+
2257+static bool
2258+intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2259+ struct intel_crtc_state *crtc_state,
2260+ bool respect_downstream_limits,
2261+ bool dsc,
2262+ struct link_config_limits *limits)
2263+{
2264+ limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2265+ limits->max_rate = intel_dp_max_link_rate(intel_dp);
18162266
1817− limits.min_lane_count = 1;
1818− limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2267+ limits->min_lane_count = 1;
2268+ limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
18192269
1820− limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1821− limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
2270+ limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2271+ limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2272+ respect_downstream_limits);
18222273
18232274 if (intel_dp->use_max_params) {
18242275 /*
@@ -1829,16 +2280,33 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, · 4 unmodified lines
18292280 * configuration, and typically on older panels these
18302281 * values correspond to the native resolution of the panel.
18312282 */
1832− limits.min_lane_count = limits.max_lane_count;
1833− limits.min_rate = limits.max_rate;
2283+ limits->min_lane_count = limits->max_lane_count;
2284+ limits->min_rate = limits->max_rate;
18342285 }
18352286
1836− intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2287+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
18372288
1838− drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1839− "max rate %d max bpp %d pixel clock %iKHz\n",
1840− limits.max_lane_count, limits.max_rate,
1841− limits.max_bpp, adjusted_mode->crtc_clock);
2289+ return intel_dp_compute_config_link_bpp_limits(intel_dp,
2290+ crtc_state,
2291+ dsc,
2292+ limits);
2293+}
2294+
2295+static int
2296+intel_dp_compute_link_config(struct intel_encoder *encoder,
2297+ struct intel_crtc_state *pipe_config,
2298+ struct drm_connector_state *conn_state,
2299+ bool respect_downstream_limits)
2300+{
2301+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2302+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2303+ const struct drm_display_mode *adjusted_mode =
2304+ &pipe_config->hw.adjusted_mode;
2305+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2306+ struct link_config_limits limits;
2307+ bool joiner_needs_dsc = false;
2308+ bool dsc_needed;
2309+ int ret = 0;
18422310
18432311 if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
18442312 adjusted_mode->crtc_clock))
@@ -1851,16 +2319,34 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, · 6 unmodified lines
18512319 */
18522320 joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
18532321
1854− /*
1855− * Optimize for slow and wide for everything, because there are some
1856− * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1857− */
1858− ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
2322+ dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2323+ !intel_dp_compute_config_limits(intel_dp, pipe_config,
2324+ respect_downstream_limits,
2325+ false,
2326+ &limits);
2327+
2328+ if (!dsc_needed) {
2329+ /*
2330+ * Optimize for slow and wide for everything, because there are some
2331+ * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2332+ */
2333+ ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2334+ conn_state, &limits);
2335+ if (ret)
2336+ dsc_needed = true;
2337+ }
18592338
1860− if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
2339+ if (dsc_needed) {
18612340 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
18622341 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
18632342 str_yes_no(intel_dp->force_dsc_en));
2343+
2344+ if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2345+ respect_downstream_limits,
2346+ true,
2347+ &limits))
2348+ return -EINVAL;
2349+
18642350 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
18652351 conn_state, &limits, 64, true);
18662352 if (ret < 0)
@@ -2136,7 +2622,7 @@ static bool can_enable_drrs(struct intel_connector *connector, · 269 unmodified lines
21362622 static void
21372623 intel_dp_drrs_compute_config(struct intel_connector *connector,
21382624 struct intel_crtc_state *pipe_config,
2139− int output_bpp)
2625+ int link_bpp)
21402626 {
21412627 struct drm_i915_private *i915 = to_i915(connector->base.dev);
21422628 const struct drm_display_mode *downclock_mode =
@@ -2144,7 +2630,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, · 1 unmodified line
21442630 int pixel_clock;
21452631
21462632 if (has_seamless_m_n(connector))
2147− pipe_config->seamless_m_n = true;
2633+ pipe_config->update_m_n = true;
21482634
21492635 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
21502636 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
@@ -2161,7 +2647,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, · 10 unmodified lines
21612647 if (pipe_config->splitter.enable)
21622648 pixel_clock /= pipe_config->splitter.link_count;
21632649
2164− intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
2650+ intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
21652651 pipe_config->port_clock, &pipe_config->dp_m2_n2,
21662652 pipe_config->fec_enable);
21672653
@@ -2171,15 +2657,17 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, · 3 unmodified lines
21712657 }
21722658
21732659 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2660+ struct intel_crtc_state *crtc_state,
21742661 const struct drm_connector_state *conn_state)
21752662 {
21762663 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2177− struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2178− struct intel_connector *connector = intel_dp->attached_connector;
21792664 const struct intel_digital_connector_state *intel_conn_state =
21802665 to_intel_digital_connector_state(conn_state);
2666+ struct intel_connector *connector =
2667+ to_intel_connector(conn_state->connector);
21812668
2182− if (!intel_dp_port_has_audio(i915, encoder->port))
2669+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2670+ !intel_dp_port_has_audio(i915, encoder->port))
21832671 return false;
21842672
21852673 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
@@ -2232,7 +2720,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, · 46 unmodified lines
22322720 return ret;
22332721 }
22342722
2235−static void
2723+void
22362724 intel_dp_audio_compute_config(struct intel_encoder *encoder,
22372725 struct intel_crtc_state *pipe_config,
22382726 struct drm_connector_state *conn_state)
@@ -2240,9 +2728,12 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder, · 1 unmodified line
22402728 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
22412729 struct drm_connector *connector = conn_state->connector;
22422730
2243− pipe_config->sdp_split_enable =
2244− intel_dp_has_audio(encoder, conn_state) &&
2245− intel_dp_is_uhbr(pipe_config);
2731+ pipe_config->has_audio =
2732+ intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2733+ intel_audio_compute_config(encoder, pipe_config, conn_state);
2734+
2735+ pipe_config->sdp_split_enable = pipe_config->has_audio &&
2736+ intel_dp_is_uhbr(pipe_config);
22462737
22472738 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
22482739 connector->base.id, connector->name,
@@ -2259,15 +2750,11 @@ intel_dp_compute_config(struct intel_encoder *encoder, · 10 unmodified lines
22592750 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
22602751 const struct drm_display_mode *fixed_mode;
22612752 struct intel_connector *connector = intel_dp->attached_connector;
2262− int ret = 0, output_bpp;
2753+ int ret = 0, link_bpp;
22632754
22642755 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
22652756 pipe_config->has_pch_encoder = true;
22662757
2267− pipe_config->has_audio =
2268− intel_dp_has_audio(encoder, conn_state) &&
2269− intel_audio_compute_config(encoder, pipe_config, conn_state);
2270−
22712758 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
22722759 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
22732760 ret = intel_panel_compute_config(connector, adjusted_mode);
@@ -2308,11 +2795,14 @@ intel_dp_compute_config(struct intel_encoder *encoder, · 34 unmodified lines
23082795 pipe_config->limited_color_range =
23092796 intel_dp_limited_color_range(pipe_config, conn_state);
23102797
2798+ pipe_config->enhanced_framing =
2799+ drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2800+
23112801 if (pipe_config->dsc.compression_enable)
2312− output_bpp = pipe_config->dsc.compressed_bpp;
2802+ link_bpp = pipe_config->dsc.compressed_bpp;
23132803 else
2314− output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2315− pipe_config->pipe_bpp);
2804+ link_bpp = intel_dp_output_bpp(pipe_config->output_format,
2805+ pipe_config->pipe_bpp);
23162806
23172807 if (intel_dp->mso_link_count) {
23182808 int n = intel_dp->mso_link_count;
@@ -2336,7 +2826,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, · 17 unmodified lines
23362826
23372827 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
23382828
2339− intel_link_compute_m_n(output_bpp,
2829+ intel_link_compute_m_n(link_bpp,
23402830 pipe_config->lane_count,
23412831 adjusted_mode->crtc_clock,
23422832 pipe_config->port_clock,
@@ -2352,7 +2842,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, · 9 unmodified lines
23522842
23532843 intel_vrr_compute_config(pipe_config, conn_state);
23542844 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2355− intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2845+ intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
23562846 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
23572847 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
23582848
@@ -4808,7 +5298,6 @@ intel_dp_set_edid(struct intel_dp *intel_dp) · 2449 unmodified lines
48085298 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
48095299 struct intel_connector *connector = intel_dp->attached_connector;
48105300 const struct drm_edid *drm_edid;
4811− const struct edid *edid;
48125301 bool vrr_capable;
48135302
48145303 intel_dp_unset_edid(intel_dp);
@@ -4826,10 +5315,8 @@ intel_dp_set_edid(struct intel_dp *intel_dp) · 11 unmodified lines
48265315 intel_dp_update_dfp(intel_dp, drm_edid);
48275316 intel_dp_update_420(intel_dp);
48285317
4829− /* FIXME: Get rid of drm_edid_raw() */
4830− edid = drm_edid_raw(drm_edid);
4831−
4832− drm_dp_cec_set_edid(&intel_dp->aux, edid);
5318+ drm_dp_cec_attach(&intel_dp->aux,
5319+ connector->base.display_info.source_physical_address);
48335320 }
48345321
48355322 static void
@@ -4957,12 +5444,6 @@ out: · 121 unmodified lines
49575444 if (status != connector_status_connected && !intel_dp->is_mst)
49585445 intel_dp_unset_edid(intel_dp);
49595446
4960− /*
4961− * Make sure the refs for power wells enabled during detect are
4962− * dropped to avoid a new detect cycle triggered by HPD polling.
4963− */
4964− intel_display_power_flush_work(dev_priv);
4965−
49665447 if (!intel_dp_is_edp(intel_dp))
49675448 drm_dp_set_subconnector_property(connector,
49685449 status,
@@ -4978,9 +5459,6 @@ intel_dp_force(struct drm_connector *connector) · 9 unmodified lines
49785459 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
49795460 struct intel_encoder *intel_encoder = &dig_port->base;
49805461 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4981− enum intel_display_power_domain aux_domain =
4982− intel_aux_power_domain(dig_port);
4983− intel_wakeref_t wakeref;
49845462
49855463 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
49865464 connector->base.id, connector->name);
@@ -4989,11 +5467,7 @@ intel_dp_force(struct drm_connector *connector) · 2 unmodified lines
49895467 if (connector->status != connector_status_connected)
49905468 return;
49915469
4992− wakeref = intel_display_power_get(dev_priv, aux_domain);
4993−
49945470 intel_dp_set_edid(intel_dp);
4995−
4996− intel_display_power_put(dev_priv, aux_domain, wakeref);
49975471 }
49985472
49995473 static int intel_dp_get_modes(struct drm_connector *connector)
@@ -5533,7 +6007,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, · 533 unmodified lines
55336007 }
55346008
55356009 mutex_lock(&dev_priv->drm.mode_config.mutex);
5536− drm_edid = drm_edid_read_ddc(connector, &intel_dp->aux.ddc);
6010+ drm_edid = drm_edid_read_ddc(connector, connector->ddc);
55376011 if (!drm_edid) {
55386012 /* Fallback to EDID from ACPI OpRegion, if any */
55396013 drm_edid = intel_opregion_get_edid(intel_connector);
@@ -5672,12 +6146,15 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, · 132 unmodified lines
56726146 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
56736147 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
56746148
6149+ intel_dp_aux_init(intel_dp);
6150+
56756151 drm_dbg_kms(&dev_priv->drm,
56766152 "Adding %s connector on [ENCODER:%d:%s]\n",
56776153 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
56786154 intel_encoder->base.base.id, intel_encoder->base.name);
56796155
5680− drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6156+ drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6157+ type, &intel_dp->aux.ddc);
56816158 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
56826159
56836160 if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
@@ -5685,8 +6162,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, · 1 unmodified line
56856162
56866163 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
56876164
5688− intel_dp_aux_init(intel_dp);
5689−
56906165 intel_connector_attach_encoder(intel_connector, intel_encoder);
56916166
56926167 if (HAS_DDI(dev_priv))
drivers/gpu/drm/i915/display/intel_dp.h+26−8
@@ -26,7 +26,14 @@ struct intel_encoder; · 25 unmodified lines
2626 struct link_config_limits {
2727 int min_rate, max_rate;
2828 int min_lane_count, max_lane_count;
29− int min_bpp, max_bpp;
29+ struct {
30+ /* Uncompressed DSC input or link output bpp in 1 bpp units */
31+ int min_bpp, max_bpp;
32+ } pipe;
33+ struct {
34+ /* Compressed or uncompressed link output bpp in 1/16 bpp units */
35+ int min_bpp_x16, max_bpp_x16;
36+ } link;
3037 };
3138
3239 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
@@ -65,6 +72,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, · 32 unmodified lines
6572 struct link_config_limits *limits,
6673 int timeslots,
6774 bool recompute_pipe_bpp);
75+void intel_dp_audio_compute_config(struct intel_encoder *encoder,
76+ struct intel_crtc_state *pipe_config,
77+ struct drm_connector_state *conn_state);
6878 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
6979 bool intel_dp_is_edp(struct intel_dp *intel_dp);
7080 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
@@ -106,13 +116,14 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, · 35 unmodified lines
106116 struct intel_crtc_state *crtc_state,
107117 unsigned int type);
108118 bool intel_digital_port_connected(struct intel_encoder *encoder);
109−int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
110−u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
111− u32 link_clock, u32 lane_count,
112− u32 mode_clock, u32 mode_hdisplay,
113− bool bigjoiner,
114− u32 pipe_bpp,
115− u32 timeslots);
119+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
120+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
121+ u32 link_clock, u32 lane_count,
122+ u32 mode_clock, u32 mode_hdisplay,
123+ bool bigjoiner,
124+ enum intel_output_format output_format,
125+ u32 pipe_bpp,
126+ u32 timeslots);
116127 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
117128 int mode_clock, int mode_hdisplay,
118129 bool bigjoiner);
@@ -143,5 +154,12 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, · 24 unmodified lines
143154 void intel_dp_phy_test(struct intel_encoder *encoder);
144155
145156 void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
157+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
158+
159+bool
160+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
161+ const struct intel_crtc_state *crtc_state,
162+ bool dsc,
163+ struct link_config_limits *limits);
146164
147165 #endif /* __INTEL_DP_H__ */
drivers/gpu/drm/i915/display/intel_dp_aux.c+29−20
@@ -14,6 +14,21 @@ · 13 unmodified lines
1414 #include "intel_pps.h"
1515 #include "intel_tc.h"
1616
17+#define AUX_CH_NAME_BUFSIZE 6
18+
19+static const char *aux_ch_name(struct drm_i915_private *i915,
20+ char *buf, int size, enum aux_ch aux_ch)
21+{
22+ if (DISPLAY_VER(i915) >= 13 && aux_ch >= AUX_CH_D_XELPD)
23+ snprintf(buf, size, "%c", 'A' + aux_ch - AUX_CH_D_XELPD + AUX_CH_D);
24+ else if (DISPLAY_VER(i915) >= 12 && aux_ch >= AUX_CH_USBC1)
25+ snprintf(buf, size, "USBC%c", '1' + aux_ch - AUX_CH_USBC1);
26+ else
27+ snprintf(buf, size, "%c", 'A' + aux_ch);
28+
29+ return buf;
30+}
31+
1732 u32 intel_dp_aux_pack(const u8 *src, int src_bytes)
1833 {
1934 int i;
@@ -687,10 +702,10 @@ static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) · 667 unmodified lines
687702 case AUX_CH_USBC2:
688703 case AUX_CH_USBC3:
689704 case AUX_CH_USBC4:
690− return XELPDP_DP_AUX_CH_CTL(aux_ch);
705+ return XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch);
691706 default:
692707 MISSING_CASE(aux_ch);
693− return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
708+ return XELPDP_DP_AUX_CH_CTL(dev_priv, AUX_CH_A);
694709 }
695710 }
696711
@@ -707,10 +722,10 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) · 10 unmodified lines
707722 case AUX_CH_USBC2:
708723 case AUX_CH_USBC3:
709724 case AUX_CH_USBC4:
710− return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
725+ return XELPDP_DP_AUX_CH_DATA(dev_priv, aux_ch, index);
711726 default:
712727 MISSING_CASE(aux_ch);
713− return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
728+ return XELPDP_DP_AUX_CH_DATA(dev_priv, AUX_CH_A, index);
714729 }
715730 }
716731
@@ -728,6 +743,7 @@ void intel_dp_aux_init(struct intel_dp *intel_dp) · 11 unmodified lines
728743 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
729744 struct intel_encoder *encoder = &dig_port->base;
730745 enum aux_ch aux_ch = dig_port->aux_ch;
746+ char buf[AUX_CH_NAME_BUFSIZE];
731747
732748 if (DISPLAY_VER(dev_priv) >= 14) {
733749 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
@@ -764,18 +780,9 @@ void intel_dp_aux_init(struct intel_dp *intel_dp) · 30 unmodified lines
764780 drm_dp_aux_init(&intel_dp->aux);
765781
766782 /* Failure to allocate our preferred name is not critical */
767− if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD)
768− intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
769− aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D),
770− encoder->base.name);
771− else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
772− intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
773− aux_ch - AUX_CH_USBC1 + '1',
774− encoder->base.name);
775− else
776− intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
777− aux_ch_name(aux_ch),
778− encoder->base.name);
783+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %s/%s",
784+ aux_ch_name(dev_priv, buf, sizeof(buf), aux_ch),
785+ encoder->base.name);
779786
780787 intel_dp->aux.transfer = intel_dp_aux_transfer;
781788 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
@@ -819,6 +826,7 @@ enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) · 37 unmodified lines
819826 struct intel_encoder *other;
820827 const char *source;
821828 enum aux_ch aux_ch;
829+ char buf[AUX_CH_NAME_BUFSIZE];
822830
823831 aux_ch = intel_bios_dp_aux_ch(encoder->devdata);
824832 source = "VBT";
@@ -836,16 +844,17 @@ enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) · 11 unmodified lines
836844 other = get_encoder_by_aux_ch(encoder, aux_ch);
837845 if (other) {
838846 drm_dbg_kms(&i915->drm,
839− "[ENCODER:%d:%s] AUX CH %c already claimed by [ENCODER:%d:%s]\n",
840− encoder->base.base.id, encoder->base.name, aux_ch_name(aux_ch),
847+ "[ENCODER:%d:%s] AUX CH %s already claimed by [ENCODER:%d:%s]\n",
848+ encoder->base.base.id, encoder->base.name,
849+ aux_ch_name(i915, buf, sizeof(buf), aux_ch),
841850 other->base.base.id, other->base.name);
842851 return AUX_CH_NONE;
843852 }
844853
845854 drm_dbg_kms(&i915->drm,
846− "[ENCODER:%d:%s] Using AUX CH %c (%s)\n",
855+ "[ENCODER:%d:%s] Using AUX CH %s (%s)\n",
847856 encoder->base.base.id, encoder->base.name,
848− aux_ch_name(aux_ch), source);
857+ aux_ch_name(i915, buf, sizeof(buf), aux_ch), source);
849858
850859 return aux_ch;
851860 }
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h+44−36
@@ -13,48 +13,34 @@ · 12 unmodified lines
1313 * packet size supported is 20 bytes in each direction, hence the 5 fixed data
1414 * registers
1515 */
16−#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
17−#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
1816
19−#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
20−#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
21−
22−#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
23−#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
24−
25−#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
26−#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
27−#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
28−#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
29−
30−#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
31− _DPA_AUX_CH_CTL, \
32− _DPB_AUX_CH_CTL, \
33− 0, /* port/aux_ch C is non-existent */ \
34− _XELPDP_USBC1_AUX_CH_CTL, \
35− _XELPDP_USBC2_AUX_CH_CTL, \
36− _XELPDP_USBC3_AUX_CH_CTL, \
37− _XELPDP_USBC4_AUX_CH_CTL))
38−
39−#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
40−#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
41−#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
42−#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
43−
44−#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
45− _DPA_AUX_CH_DATA1, \
46− _DPB_AUX_CH_DATA1, \
47− 0, /* port/aux_ch C is non-existent */ \
48− _XELPDP_USBC1_AUX_CH_DATA1, \
49− _XELPDP_USBC2_AUX_CH_DATA1, \
50− _XELPDP_USBC3_AUX_CH_DATA1, \
51− _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
17+/*
18+ * Wrapper macro to convert from aux_ch to the index used in some of the
19+ * registers.
20+ */
21+#define __xe2lpd_aux_ch_idx(aux_ch) \
22+ (aux_ch >= AUX_CH_USBC1 ? aux_ch : AUX_CH_USBC4 + 1 + (aux_ch) - AUX_CH_A)
5223
24+/* TODO: Remove implicit dev_priv */
25+#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
26+#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
27+#define _XELPDP_USBC1_AUX_CH_CTL 0x16f210
28+#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410
29+#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \
30+ _DPB_AUX_CH_CTL)
31+#define _XELPDP_DP_AUX_CH_CTL(aux_ch) \
32+ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
33+ _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL, \
34+ _XELPDP_USBC1_AUX_CH_CTL, \
35+ _XELPDP_USBC2_AUX_CH_CTL))
36+#define XELPDP_DP_AUX_CH_CTL(i915__, aux_ch) \
37+ (DISPLAY_VER(i915__) >= 20 ? \
38+ _XELPDP_DP_AUX_CH_CTL(__xe2lpd_aux_ch_idx(aux_ch)) : \
39+ _XELPDP_DP_AUX_CH_CTL(aux_ch))
5340 #define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
5441 #define DP_AUX_CH_CTL_DONE REG_BIT(30)
5542 #define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
5643 #define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
57−
5844 #define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26)
5945 #define DP_AUX_CH_CTL_TIME_OUT_400us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 0)
6046 #define DP_AUX_CH_CTL_TIME_OUT_600us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 1)
@@ -83,4 +69,26 @@ · 22 unmodified lines
8369 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
8470 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
8571
72+/* TODO: Remove implicit dev_priv */
73+#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
74+#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
75+#define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214
76+#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414
77+#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \
78+ _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
79+#define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) \
80+ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
81+ _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \
82+ _XELPDP_USBC1_AUX_CH_DATA1, \
83+ _XELPDP_USBC2_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
84+#define XELPDP_DP_AUX_CH_DATA(i915__, aux_ch, i) \
85+ (DISPLAY_VER(i915__) >= 20 ? \
86+ _XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \
87+ _XELPDP_DP_AUX_CH_DATA(aux_ch, i))
88+
89+/* PICA Power Well Control */
90+#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
91+#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
92+#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
93+
8694 #endif /* __INTEL_DP_AUX_REGS_H__ */
drivers/gpu/drm/i915/display/intel_dp_hdcp.c+58−29
@@ -330,14 +330,26 @@ static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { · 329 unmodified lines
330330 0, 0 },
331331 };
332332
333+static struct drm_dp_aux *
334+intel_dp_hdcp_get_aux(struct intel_connector *connector)
335+{
336+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
337+
338+ if (intel_encoder_is_mst(connector->encoder))
339+ return &connector->port->aux;
340+ else
341+ return &dig_port->dp.aux;
342+}
343+
333344 static int
334−intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
345+intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
335346 u8 *rx_status)
336347 {
337− struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
348+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
349+ struct drm_dp_aux *aux = intel_dp_hdcp_get_aux(connector);
338350 ssize_t ret;
339351
340− ret = drm_dp_dpcd_read(&dig_port->dp.aux,
352+ ret = drm_dp_dpcd_read(aux,
341353 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
342354 HDCP_2_2_DP_RXSTATUS_LEN);
343355 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
@@ -350,14 +362,14 @@ intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port, · 6 unmodified lines
350362 }
351363
352364 static
353−int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
365+int hdcp2_detect_msg_availability(struct intel_connector *connector,
354366 u8 msg_id, bool *msg_ready)
355367 {
356368 u8 rx_status;
357369 int ret;
358370
359371 *msg_ready = false;
360− ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
372+ ret = intel_dp_hdcp2_read_rx_status(connector, &rx_status);
361373 if (ret < 0)
362374 return ret;
363375
@@ -383,12 +395,11 @@ int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, · 19 unmodified lines
383395 }
384396
385397 static ssize_t
386−intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
398+intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
387399 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
388400 {
389− struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
390− struct intel_dp *dp = &dig_port->dp;
391− struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
401+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
402+ struct intel_hdcp *hdcp = &connector->hdcp;
392403 u8 msg_id = hdcp2_msg_data->msg_id;
393404 int ret, timeout;
394405 bool msg_ready = false;
@@ -411,8 +422,8 @@ intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, · 16 unmodified lines
411422 * the timeout at wait for CP_IRQ.
412423 */
413424 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
414− ret = hdcp2_detect_msg_availability(dig_port,
415− msg_id, &msg_ready);
425+ ret = hdcp2_detect_msg_availability(connector, msg_id,
426+ &msg_ready);
416427 if (!msg_ready)
417428 ret = -ETIMEDOUT;
418429 }
@@ -437,13 +448,14 @@ static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) · 18 unmodified lines
437448 }
438449
439450 static
440−int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
451+int intel_dp_hdcp2_write_msg(struct intel_connector *connector,
441452 void *buf, size_t size)
442453 {
443454 unsigned int offset;
444455 u8 *byte = buf;
445456 ssize_t ret, bytes_to_write, len;
446457 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
458+ struct drm_dp_aux *aux;
447459
448460 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
449461 if (!hdcp2_msg_data)
@@ -451,6 +463,8 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, · 1 unmodified line
451463
452464 offset = hdcp2_msg_data->offset;
453465
466+ aux = intel_dp_hdcp_get_aux(connector);
467+
454468 /* No msg_id in DP HDCP2.2 msgs */
455469 bytes_to_write = size - 1;
456470 byte++;
@@ -459,7 +473,7 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, · 2 unmodified lines
459473 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
460474 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
461475
462− ret = drm_dp_dpcd_write(&dig_port->dp.aux,
476+ ret = drm_dp_dpcd_write(aux,
463477 offset, (void *)byte, len);
464478 if (ret < 0)
465479 return ret;
@@ -473,12 +487,14 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, · 7 unmodified lines
473487 }
474488
475489 static
476−ssize_t get_receiver_id_list_rx_info(struct intel_digital_port *dig_port, u32 *dev_cnt, u8 *byte)
490+ssize_t get_receiver_id_list_rx_info(struct intel_connector *connector,
491+ u32 *dev_cnt, u8 *byte)
477492 {
493+ struct drm_dp_aux *aux = intel_dp_hdcp_get_aux(connector);
478494 ssize_t ret;
479495 u8 *rx_info = byte;
480496
481− ret = drm_dp_dpcd_read(&dig_port->dp.aux,
497+ ret = drm_dp_dpcd_read(aux,
482498 DP_HDCP_2_2_REG_RXINFO_OFFSET,
483499 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
484500 if (ret != HDCP_2_2_RXINFO_LEN)
@@ -494,12 +510,13 @@ ssize_t get_receiver_id_list_rx_info(struct intel_digital_port *dig_port, u32 *d · 9 unmodified lines
494510 }
495511
496512 static
497−int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
513+int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
498514 u8 msg_id, void *buf, size_t size)
499515 {
516+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
500517 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
501− struct intel_dp *dp = &dig_port->dp;
502− struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
518+ struct intel_hdcp *hdcp = &connector->hdcp;
519+ struct drm_dp_aux *aux;
503520 unsigned int offset;
504521 u8 *byte = buf;
505522 ssize_t ret, bytes_to_recv, len;
@@ -513,7 +530,9 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, · 7 unmodified lines
513530 return -EINVAL;
514531 offset = hdcp2_msg_data->offset;
515532
516− ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
533+ aux = intel_dp_hdcp_get_aux(connector);
534+
535+ ret = intel_dp_hdcp2_wait_for_msg(connector, hdcp2_msg_data);
517536 if (ret < 0)
518537 return ret;
519538
@@ -523,7 +542,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, · 3 unmodified lines
523542 byte++;
524543
525544 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
526− ret = get_receiver_id_list_rx_info(dig_port, &dev_cnt, byte);
545+ ret = get_receiver_id_list_rx_info(connector, &dev_cnt, byte);
527546 if (ret < 0)
528547 return ret;
529548
@@ -541,11 +560,17 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, · 11 unmodified lines
541560 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
542561
543562 /* Entire msg read timeout since initiate of msg read */
544− if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0)
545− msg_end = ktime_add_ms(ktime_get_raw(),
546− hdcp2_msg_data->msg_read_timeout);
563+ if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0) {
564+ if (intel_encoder_is_mst(connector->encoder))
565+ msg_end = ktime_add_ms(ktime_get_raw(),
566+ hdcp2_msg_data->msg_read_timeout *
567+ connector->port->parent->num_ports);
568+ else
569+ msg_end = ktime_add_ms(ktime_get_raw(),
570+ hdcp2_msg_data->msg_read_timeout);
571+ }
547572
548− ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
573+ ret = drm_dp_dpcd_read(aux, offset,
549574 (void *)byte, len);
550575 if (ret < 0) {
551576 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
@@ -574,7 +599,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, · 22 unmodified lines
574599 }
575600
576601 static
577−int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
602+int intel_dp_hdcp2_config_stream_type(struct intel_connector *connector,
578603 bool is_repeater, u8 content_type)
579604 {
580605 int ret;
@@ -593,7 +618,7 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port, · 12 unmodified lines
593618 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
594619 stream_type_msg.stream_type = content_type;
595620
596− ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
621+ ret = intel_dp_hdcp2_write_msg(connector, &stream_type_msg,
597622 sizeof(stream_type_msg));
598623
599624 return ret < 0 ? ret : 0;
@@ -607,7 +632,8 @@ int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, · 7 unmodified lines
607632 u8 rx_status;
608633 int ret;
609634
610− ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
635+ ret = intel_dp_hdcp2_read_rx_status(connector,
636+ &rx_status);
611637 if (ret)
612638 return ret;
613639
@@ -622,14 +648,17 @@ int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, · 8 unmodified lines
622648 }
623649
624650 static
625−int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
651+int intel_dp_hdcp2_capable(struct intel_connector *connector,
626652 bool *capable)
627653 {
654+ struct drm_dp_aux *aux;
628655 u8 rx_caps[3];
629656 int ret;
630657
658+ aux = intel_dp_hdcp_get_aux(connector);
659+
631660 *capable = false;
632− ret = drm_dp_dpcd_read(&dig_port->dp.aux,
661+ ret = drm_dp_dpcd_read(aux,
633662 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
634663 rx_caps, HDCP_2_2_RXCAPS_LEN);
635664 if (ret != HDCP_2_2_RXCAPS_LEN)
drivers/gpu/drm/i915/display/intel_dp_link_training.c+8−6
@@ -655,7 +655,7 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp, · 654 unmodified lines
655655 /* Write the link configuration data */
656656 link_config[0] = link_bw;
657657 link_config[1] = crtc_state->lane_count;
658− if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
658+ if (crtc_state->enhanced_framing)
659659 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
660660 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
661661
@@ -1390,11 +1390,13 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, · 728 unmodified lines
13901390 * Default value of bit 31 is '0' hence discarding the write
13911391 * TODO: Corrective actions on SDP corruption yet to be defined
13921392 */
1393− if (intel_dp_is_uhbr(crtc_state))
1394− /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
1395− drm_dp_dpcd_writeb(&intel_dp->aux,
1396− DP_SDP_ERROR_DETECTION_CONFIGURATION,
1397− DP_SDP_CRC16_128B132B_EN);
1393+ if (!intel_dp_is_uhbr(crtc_state))
1394+ return;
1395+
1396+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
1397+ drm_dp_dpcd_writeb(&intel_dp->aux,
1398+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
1399+ DP_SDP_CRC16_128B132B_EN);
13981400
13991401 lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
14001402 }
drivers/gpu/drm/i915/display/intel_dp_mst.c+97−59
@@ -155,15 +155,24 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, · 154 unmodified lines
155155 const struct drm_display_mode *adjusted_mode =
156156 &crtc_state->hw.adjusted_mode;
157157 int slots = -EINVAL;
158+ int link_bpp;
158159
159− slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
160− limits->min_bpp, limits,
160+ /*
161+ * FIXME: allocate the BW according to link_bpp, which in the case of
162+ * YUV420 is only half of the pipe bpp value.
163+ */
164+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
165+ to_bpp_int(limits->link.max_bpp_x16),
166+ to_bpp_int(limits->link.min_bpp_x16),
167+ limits,
161168 conn_state, 2 * 3, false);
162169
163170 if (slots < 0)
164171 return slots;
165172
166− intel_link_compute_m_n(crtc_state->pipe_bpp,
173+ link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
174+
175+ intel_link_compute_m_n(link_bpp,
167176 crtc_state->lane_count,
168177 adjusted_mode->crtc_clock,
169178 crtc_state->port_clock,
@@ -200,8 +209,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, · 30 unmodified lines
200209 else
201210 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
202211
203− max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
204− min_bpp = limits->min_bpp;
212+ max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
213+ min_bpp = limits->pipe.min_bpp;
205214
206215 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
207216 dsc_bpc);
@@ -228,6 +237,9 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, · 20 unmodified lines
228237 if (max_bpp > sink_max_bpp)
229238 max_bpp = sink_max_bpp;
230239
240+ min_bpp = max(min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
241+ max_bpp = min(max_bpp, to_bpp_int(limits->link.max_bpp_x16));
242+
231243 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
232244 min_bpp, limits,
233245 conn_state, 2 * 3, true);
@@ -290,17 +302,39 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder, · 56 unmodified lines
290302 return 0;
291303 }
292304
293−static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
305+static bool
306+intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
307+ struct intel_crtc_state *crtc_state,
308+ bool dsc,
309+ struct link_config_limits *limits)
294310 {
295− const struct intel_digital_connector_state *intel_conn_state =
296− to_intel_digital_connector_state(conn_state);
297− struct intel_connector *connector =
298− to_intel_connector(conn_state->connector);
311+ /*
312+ * for MST we always configure max link bw - the spec doesn't
313+ * seem to suggest we should do otherwise.
314+ */
315+ limits->min_rate = limits->max_rate =
316+ intel_dp_max_link_rate(intel_dp);
299317
300− if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
301− return connector->base.display_info.has_audio;
302− else
303− return intel_conn_state->force_audio == HDMI_AUDIO_ON;
318+ limits->min_lane_count = limits->max_lane_count =
319+ intel_dp_max_lane_count(intel_dp);
320+
321+ limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
322+ /*
323+ * FIXME: If all the streams can't fit into the link with
324+ * their current pipe_bpp we should reduce pipe_bpp across
325+ * the board until things start to fit. Until then we
326+ * limit to <= 8bpc since that's what was hardcoded for all
327+ * MST streams previously. This hack should be removed once
328+ * we have the proper retry logic in place.
329+ */
330+ limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
331+
332+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
333+
334+ return intel_dp_compute_config_link_bpp_limits(intel_dp,
335+ crtc_state,
336+ dsc,
337+ limits);
304338 }
305339
306340 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
@@ -313,7 +347,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, · 6 unmodified lines
313347 const struct drm_display_mode *adjusted_mode =
314348 &pipe_config->hw.adjusted_mode;
315349 struct link_config_limits limits;
316− int ret;
350+ bool dsc_needed;
351+ int ret = 0;
317352
318353 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
319354 return -EINVAL;
@@ -322,42 +357,40 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, · 2 unmodified lines
322357 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
323358 pipe_config->has_pch_encoder = false;
324359
325− pipe_config->has_audio =
326− intel_dp_mst_has_audio(conn_state) &&
327− intel_audio_compute_config(encoder, pipe_config, conn_state);
360+ dsc_needed = intel_dp->force_dsc_en ||
361+ !intel_dp_mst_compute_config_limits(intel_dp,
362+ pipe_config,
363+ false,
364+ &limits);
328365
329− /*
330− * for MST we always configure max link bw - the spec doesn't
331− * seem to suggest we should do otherwise.
332− */
333− limits.min_rate =
334− limits.max_rate = intel_dp_max_link_rate(intel_dp);
366+ if (!dsc_needed) {
367+ ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
368+ conn_state, &limits);
335369
336− limits.min_lane_count =
337− limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
338−
339− limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
340− /*
341− * FIXME: If all the streams can't fit into the link with
342− * their current pipe_bpp we should reduce pipe_bpp across
343− * the board until things start to fit. Until then we
344− * limit to <= 8bpc since that's what was hardcoded for all
345− * MST streams previously. This hack should be removed once
346− * we have the proper retry logic in place.
347− */
348− limits.max_bpp = min(pipe_config->pipe_bpp, 24);
349−
350− intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
351−
352− ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
353− conn_state, &limits);
370+ if (ret == -EDEADLK)
371+ return ret;
354372
355− if (ret == -EDEADLK)
356− return ret;
373+ if (ret)
374+ dsc_needed = true;
375+ }
357376
358377 /* enable compression if the mode doesn't fit available BW */
359− drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
360− if (ret || intel_dp->force_dsc_en) {
378+ if (dsc_needed) {
379+ drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, force=%s)\n",
380+ str_yes_no(ret),
381+ str_yes_no(intel_dp->force_dsc_en));
382+
383+ if (!intel_dp_mst_compute_config_limits(intel_dp,
384+ pipe_config,
385+ true,
386+ &limits))
387+ return -EINVAL;
388+
389+ /*
390+ * FIXME: As bpc is hardcoded to 8, as mentioned above,
391+ * WARN and ignore the debug flag force_dsc_bpc for now.
392+ */
393+ drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
361394 /*
362395 * Try to get at least some timeslots and then see, if
363396 * we can fit there with DSC.
@@ -388,6 +421,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, · 24 unmodified lines
388421 pipe_config->lane_lat_optim_mask =
389422 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
390423
424+ intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
425+
391426 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
392427
393428 return 0;
@@ -733,8 +768,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, · 339 unmodified lines
733768 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
734769 drm_atomic_get_mst_payload_state(mst_state, connector->port));
735770 if (ret < 0)
736− drm_err(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
737− connector->base.name, ret);
771+ drm_dbg_kms(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
772+ connector->base.name, ret);
738773
739774 /*
740775 * Before Gen 12 this is not done as part of
@@ -798,6 +833,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, · 57 unmodified lines
798833 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
799834 FECSTALL_DIS_DPTSTREAM_DPTTG);
800835
836+ intel_audio_sdp_split_update(pipe_config);
837+
801838 intel_enable_transcoder(pipe_config);
802839
803840 intel_crtc_vblank_on(pipe_config);
@@ -918,7 +955,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, · 114 unmodified lines
918955 int max_rate, mode_rate, max_lanes, max_link_clock;
919956 int ret;
920957 bool dsc = false, bigjoiner = false;
921− u16 dsc_max_output_bpp = 0;
958+ u16 dsc_max_compressed_bpp = 0;
922959 u8 dsc_slice_count = 0;
923960 int target_clock = mode->clock;
924961
@@ -969,17 +1006,18 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, · 44 unmodified lines
9691006 * TBD pass the connector BPC,
9701007 * for now U8_MAX so that max BPC on that platform would be picked
9711008 */
972− int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1009+ int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
9731010
9741011 if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
975− dsc_max_output_bpp =
976− intel_dp_dsc_get_output_bpp(dev_priv,
977− max_link_clock,
978− max_lanes,
979− target_clock,
980− mode->hdisplay,
981− bigjoiner,
982− pipe_bpp, 64) >> 4;
1012+ dsc_max_compressed_bpp =
1013+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1014+ max_link_clock,
1015+ max_lanes,
1016+ target_clock,
1017+ mode->hdisplay,
1018+ bigjoiner,
1019+ INTEL_OUTPUT_FORMAT_RGB,
1020+ pipe_bpp, 64);
9831021 dsc_slice_count =
9841022 intel_dp_dsc_get_slice_count(intel_dp,
9851023 target_clock,
@@ -987,7 +1025,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, · 1 unmodified line
9871025 bigjoiner);
9881026 }
9891027
990− dsc = dsc_max_output_bpp && dsc_slice_count;
1028+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
9911029 }
9921030
9931031 /*
drivers/gpu/drm/i915/display/intel_dpll.c+35−19
@@ -314,10 +314,11 @@ int pnv_calc_dpll_params(int refclk, struct dpll *clock) · 313 unmodified lines
314314 {
315315 clock->m = clock->m2 + 2;
316316 clock->p = clock->p1 * clock->p2;
317− if (WARN_ON(clock->n == 0 || clock->p == 0))
318− return 0;
319− clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
320− clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
317+
318+ clock->vco = clock->n == 0 ? 0 :
319+ DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
320+ clock->dot = clock->p == 0 ? 0 :
321+ DIV_ROUND_CLOSEST(clock->vco, clock->p);
321322
322323 return clock->dot;
323324 }
@@ -331,10 +332,11 @@ int i9xx_calc_dpll_params(int refclk, struct dpll *clock) · 7 unmodified lines
331332 {
332333 clock->m = i9xx_dpll_compute_m(clock);
333334 clock->p = clock->p1 * clock->p2;
334− if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
335− return 0;
336− clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
337− clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
335+
336+ clock->vco = clock->n + 2 == 0 ? 0 :
337+ DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
338+ clock->dot = clock->p == 0 ? 0 :
339+ DIV_ROUND_CLOSEST(clock->vco, clock->p);
338340
339341 return clock->dot;
340342 }
@@ -343,10 +345,11 @@ int vlv_calc_dpll_params(int refclk, struct dpll *clock) · 2 unmodified lines
343345 {
344346 clock->m = clock->m1 * clock->m2;
345347 clock->p = clock->p1 * clock->p2 * 5;
346− if (WARN_ON(clock->n == 0 || clock->p == 0))
347− return 0;
348− clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
349− clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
348+
349+ clock->vco = clock->n == 0 ? 0 :
350+ DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
351+ clock->dot = clock->p == 0 ? 0 :
352+ DIV_ROUND_CLOSEST(clock->vco, clock->p);
350353
351354 return clock->dot;
352355 }
@@ -355,11 +358,11 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock) · 2 unmodified lines
355358 {
356359 clock->m = clock->m1 * clock->m2;
357360 clock->p = clock->p1 * clock->p2 * 5;
358− if (WARN_ON(clock->n == 0 || clock->p == 0))
359− return 0;
360− clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
361− clock->n << 22);
362− clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
361+
362+ clock->vco = clock->n == 0 ? 0 :
363+ DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
364+ clock->dot = clock->p == 0 ? 0 :
365+ DIV_ROUND_CLOSEST(clock->vco, clock->p);
363366
364367 return clock->dot;
365368 }
@@ -1179,6 +1182,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, · 813 unmodified lines
11791182 refclk, NULL, &crtc_state->dpll))
11801183 return -EINVAL;
11811184
1185+ i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1186+
11821187 ilk_compute_dpll(crtc_state, &crtc_state->dpll,
11831188 &crtc_state->dpll);
11841189
@@ -1253,6 +1258,8 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state, · 68 unmodified lines
12531258 refclk, NULL, &crtc_state->dpll))
12541259 return -EINVAL;
12551260
1261+ chv_calc_dpll_params(refclk, &crtc_state->dpll);
1262+
12561263 chv_compute_dpll(crtc_state);
12571264
12581265 /* FIXME this is a mess */
@@ -1275,9 +1282,10 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state, · 16 unmodified lines
12751282
12761283 if (!crtc_state->clock_set &&
12771284 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1278− refclk, NULL, &crtc_state->dpll)) {
1285+ refclk, NULL, &crtc_state->dpll))
12791286 return -EINVAL;
1280− }
1287+
1288+ vlv_calc_dpll_params(refclk, &crtc_state->dpll);
12811289
12821290 vlv_compute_dpll(crtc_state);
12831291
@@ -1327,6 +1335,8 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state, · 43 unmodified lines
13271335 refclk, NULL, &crtc_state->dpll))
13281336 return -EINVAL;
13291337
1338+ i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1339+
13301340 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
13311341 &crtc_state->dpll);
13321342
@@ -1365,6 +1375,8 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state, · 32 unmodified lines
13651375 refclk, NULL, &crtc_state->dpll))
13661376 return -EINVAL;
13671377
1378+ pnv_calc_dpll_params(refclk, &crtc_state->dpll);
1379+
13681380 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
13691381 &crtc_state->dpll);
13701382
@@ -1401,6 +1413,8 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, · 30 unmodified lines
14011413 refclk, NULL, &crtc_state->dpll))
14021414 return -EINVAL;
14031415
1416+ i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1417+
14041418 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
14051419 &crtc_state->dpll);
14061420
@@ -1441,6 +1455,8 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, · 34 unmodified lines
14411455 refclk, NULL, &crtc_state->dpll))
14421456 return -EINVAL;
14431457
1458+ i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1459+
14441460 i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
14451461 &crtc_state->dpll);
14461462
drivers/gpu/drm/i915/display/intel_dpt.c+1−1
@@ -29,7 +29,7 @@ static inline struct i915_dpt * · 28 unmodified lines
2929 i915_vm_to_dpt(struct i915_address_space *vm)
3030 {
3131 BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
32− GEM_BUG_ON(!i915_is_dpt(vm));
32+ drm_WARN_ON(&vm->i915->drm, !i915_is_dpt(vm));
3333 return container_of(vm, struct i915_dpt, vm);
3434 }
3535
drivers/gpu/drm/i915/display/intel_drrs.c+1−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include "intel_de.h"
1010 #include "intel_display_types.h"
1111 #include "intel_drrs.h"
12+#include "intel_frontbuffer.h"
1213 #include "intel_panel.h"
1314
1415 /**
drivers/gpu/drm/i915/display/intel_dsb.c+188−29
@@ -7,11 +7,16 @@ · 6 unmodified lines
77 #include "gem/i915_gem_internal.h"
88
99 #include "i915_drv.h"
10+#include "i915_irq.h"
1011 #include "i915_reg.h"
12+#include "intel_crtc.h"
1113 #include "intel_de.h"
1214 #include "intel_display_types.h"
1315 #include "intel_dsb.h"
1416 #include "intel_dsb_regs.h"
17+#include "intel_vblank.h"
18+#include "intel_vrr.h"
19+#include "skl_watermark.h"
1520
1621 struct i915_vma;
1722
@@ -47,6 +52,8 @@ struct intel_dsb { · 29 unmodified lines
4752 * register.
4853 */
4954 unsigned int ins_start_offset;
55+
56+ int dewake_scanline;
5057 };
5158
5259 /**
@@ -70,17 +77,21 @@ struct intel_dsb { · 17 unmodified lines
7077 #define DSB_OPCODE_SHIFT 24
7178 #define DSB_OPCODE_NOOP 0x0
7279 #define DSB_OPCODE_MMIO_WRITE 0x1
80+#define DSB_BYTE_EN 0xf
81+#define DSB_BYTE_EN_SHIFT 20
82+#define DSB_REG_VALUE_MASK 0xfffff
7383 #define DSB_OPCODE_WAIT_USEC 0x2
74−#define DSB_OPCODE_WAIT_LINES 0x3
84+#define DSB_OPCODE_WAIT_SCANLINE 0x3
7585 #define DSB_OPCODE_WAIT_VBLANKS 0x4
7686 #define DSB_OPCODE_WAIT_DSL_IN 0x5
7787 #define DSB_OPCODE_WAIT_DSL_OUT 0x6
88+#define DSB_SCANLINE_UPPER_SHIFT 20
89+#define DSB_SCANLINE_LOWER_SHIFT 0
7890 #define DSB_OPCODE_INTERRUPT 0x7
7991 #define DSB_OPCODE_INDEXED_WRITE 0x9
92+/* see DSB_REG_VALUE_MASK */
8093 #define DSB_OPCODE_POLL 0xA
81−#define DSB_BYTE_EN 0xF
82−#define DSB_BYTE_EN_SHIFT 20
83−#define DSB_REG_VALUE_MASK 0xfffff
94+/* see DSB_REG_VALUE_MASK */
8495
8596 static bool assert_dsb_has_room(struct intel_dsb *dsb)
8697 {
@@ -93,10 +104,26 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb) · 6 unmodified lines
93104 crtc->base.base.id, crtc->base.name, dsb->id);
94105 }
95106
107+static void intel_dsb_dump(struct intel_dsb *dsb)
108+{
109+ struct intel_crtc *crtc = dsb->crtc;
110+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
111+ const u32 *buf = dsb->cmd_buf;
112+ int i;
113+
114+ drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n",
115+ crtc->base.base.id, crtc->base.name, dsb->id);
116+ for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
117+ drm_dbg_kms(&i915->drm,
118+ " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
119+ i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
120+ drm_dbg_kms(&i915->drm, "}\n");
121+}
122+
96123 static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
97124 enum dsb_id id)
98125 {
99− return intel_de_read(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
126+ return intel_de_read_fw(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
100127 }
101128
102129 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
@@ -121,7 +148,15 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, · 18 unmodified lines
121148 const u32 *buf = dsb->cmd_buf;
122149 u32 prev_opcode, prev_reg;
123150
124− prev_opcode = buf[dsb->ins_start_offset + 1] >> DSB_OPCODE_SHIFT;
151+ /*
152+ * Nothing emitted yet? Must check before looking
153+ * at the actual data since i915_gem_object_create_internal()
154+ * does *not* give you zeroed memory!
155+ */
156+ if (dsb->free_pos == 0)
157+ return false;
158+
159+ prev_opcode = buf[dsb->ins_start_offset + 1] & ~DSB_REG_VALUE_MASK;
125160 prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
126161
127162 return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
@@ -129,12 +164,18 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, · 1 unmodified line
129164
130165 static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg)
131166 {
132− return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_MMIO_WRITE, reg);
167+ /* only full byte-enables can be converted to indexed writes */
168+ return intel_dsb_prev_ins_is_write(dsb,
169+ DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT |
170+ DSB_BYTE_EN << DSB_BYTE_EN_SHIFT,
171+ reg);
133172 }
134173
135174 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)
136175 {
137− return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE, reg);
176+ return intel_dsb_prev_ins_is_write(dsb,
177+ DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT,
178+ reg);
138179 }
139180
140181 /**
@@ -200,6 +241,53 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, · 59 unmodified lines
200241 }
201242 }
202243
244+static u32 intel_dsb_mask_to_byte_en(u32 mask)
245+{
246+ return (!!(mask & 0xff000000) << 3 |
247+ !!(mask & 0x00ff0000) << 2 |
248+ !!(mask & 0x0000ff00) << 1 |
249+ !!(mask & 0x000000ff) << 0);
250+}
251+
252+/* Note: mask implemented via byte enables! */
253+void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
254+ i915_reg_t reg, u32 mask, u32 val)
255+{
256+ intel_dsb_emit(dsb, val,
257+ (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
258+ (intel_dsb_mask_to_byte_en(mask) << DSB_BYTE_EN_SHIFT) |
259+ i915_mmio_reg_offset(reg));
260+}
261+
262+void intel_dsb_noop(struct intel_dsb *dsb, int count)
263+{
264+ int i;
265+
266+ for (i = 0; i < count; i++)
267+ intel_dsb_emit(dsb, 0,
268+ DSB_OPCODE_NOOP << DSB_OPCODE_SHIFT);
269+}
270+
271+void intel_dsb_nonpost_start(struct intel_dsb *dsb)
272+{
273+ struct intel_crtc *crtc = dsb->crtc;
274+ enum pipe pipe = crtc->pipe;
275+
276+ intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id),
277+ DSB_NON_POSTED, DSB_NON_POSTED);
278+ intel_dsb_noop(dsb, 4);
279+}
280+
281+void intel_dsb_nonpost_end(struct intel_dsb *dsb)
282+{
283+ struct intel_crtc *crtc = dsb->crtc;
284+ enum pipe pipe = crtc->pipe;
285+
286+ intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id),
287+ DSB_NON_POSTED, 0);
288+ intel_dsb_noop(dsb, 4);
289+}
290+
203291 static void intel_dsb_align_tail(struct intel_dsb *dsb)
204292 {
205293 u32 aligned_tail, tail;
@@ -216,17 +304,40 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb) · 10 unmodified lines
216304
217305 void intel_dsb_finish(struct intel_dsb *dsb)
218306 {
307+ struct intel_crtc *crtc = dsb->crtc;
308+
309+ /*
310+ * DSB_FORCE_DEWAKE remains active even after DSB is
311+ * disabled, so make sure to clear it (if set during
312+ * intel_dsb_commit()).
313+ */
314+ intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id),
315+ DSB_FORCE_DEWAKE, 0);
316+
219317 intel_dsb_align_tail(dsb);
220318 }
221319
222−/**
223− * intel_dsb_commit() - Trigger workload execution of DSB.
224− * @dsb: DSB context
225− * @wait_for_vblank: wait for vblank before executing
226− *
227− * This function is used to do actual write to hardware using DSB.
228− */
229−void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)
320+static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)
321+{
322+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
323+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
324+ unsigned int latency = skl_watermark_max_latency(i915);
325+ int vblank_start;
326+
327+ if (crtc_state->vrr.enable) {
328+ vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
329+ } else {
330+ vblank_start = adjusted_mode->crtc_vblank_start;
331+
332+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
333+ vblank_start = DIV_ROUND_UP(vblank_start, 2);
334+ }
335+
336+ return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, latency));
337+}
338+
339+static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
340+ unsigned int dewake_scanline)
230341 {
231342 struct intel_crtc *crtc = dsb->crtc;
232343 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -243,13 +354,48 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank) · 10 unmodified lines
243354 return;
244355 }
245356
246− intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
247− (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
248− DSB_ENABLE);
249− intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
250− i915_ggtt_offset(dsb->vma));
251− intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
252− i915_ggtt_offset(dsb->vma) + tail);
357+ intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
358+ ctrl | DSB_ENABLE);
359+
360+ intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id),
361+ i915_ggtt_offset(dsb->vma));
362+
363+ if (dewake_scanline >= 0) {
364+ int diff, hw_dewake_scanline;
365+
366+ hw_dewake_scanline = intel_crtc_scanline_to_hw(crtc, dewake_scanline);
367+
368+ intel_de_write_fw(dev_priv, DSB_PMCTRL(pipe, dsb->id),
369+ DSB_ENABLE_DEWAKE |
370+ DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline));
371+
372+ /*
373+ * Force DEwake immediately if we're already past
374+ * or close to racing past the target scanline.
375+ */
376+ diff = dewake_scanline - intel_get_crtc_scanline(crtc);
377+ intel_de_write_fw(dev_priv, DSB_PMCTRL_2(pipe, dsb->id),
378+ (diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE : 0) |
379+ DSB_BLOCK_DEWAKE_EXTENSION);
380+ }
381+
382+ intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id),
383+ i915_ggtt_offset(dsb->vma) + tail);
384+}
385+
386+/**
387+ * intel_dsb_commit() - Trigger workload execution of DSB.
388+ * @dsb: DSB context
389+ * @wait_for_vblank: wait for vblank before executing
390+ *
391+ * This function is used to do actual write to hardware using DSB.
392+ */
393+void intel_dsb_commit(struct intel_dsb *dsb,
394+ bool wait_for_vblank)
395+{
396+ _intel_dsb_commit(dsb,
397+ wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0,
398+ wait_for_vblank ? dsb->dewake_scanline : -1);
253399 }
254400
255401 void intel_dsb_wait(struct intel_dsb *dsb)
@@ -258,20 +404,31 @@ void intel_dsb_wait(struct intel_dsb *dsb) · 2 unmodified lines
258404 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
259405 enum pipe pipe = crtc->pipe;
260406
261− if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
407+ if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
408+ u32 offset = i915_ggtt_offset(dsb->vma);
409+
410+ intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
411+ DSB_ENABLE | DSB_HALT);
412+
262413 drm_err(&dev_priv->drm,
263− "[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
264− crtc->base.base.id, crtc->base.name, dsb->id);
414+ "[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n",
415+ crtc->base.base.id, crtc->base.name, dsb->id,
416+ intel_de_read_fw(dev_priv, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,
417+ intel_de_read_fw(dev_priv, DSB_HEAD(pipe, dsb->id)) - offset,
418+ intel_de_read_fw(dev_priv, DSB_TAIL(pipe, dsb->id)) - offset);
419+
420+ intel_dsb_dump(dsb);
421+ }
265422
266423 /* Attempt to reset it */
267424 dsb->free_pos = 0;
268425 dsb->ins_start_offset = 0;
269− intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
426+ intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
270427 }
271428
272429 /**
273430 * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
274− * @crtc: the CRTC
431+ * @crtc_state: the CRTC state
275432 * @max_cmds: number of commands we need to fit into command buffer
276433 *
277434 * This function prepare the command buffer which is used to store dsb
@@ -280,9 +437,10 @@ void intel_dsb_wait(struct intel_dsb *dsb) · 2 unmodified lines
280437 * Returns:
281438 * DSB context, NULL on failure
282439 */
283−struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc,
440+struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state,
284441 unsigned int max_cmds)
285442 {
443+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
286444 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
287445 struct drm_i915_gem_object *obj;
288446 intel_wakeref_t wakeref;
@@ -328,6 +486,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc, · 39 unmodified lines
328486 dsb->size = size / 4; /* in dwords */
329487 dsb->free_pos = 0;
330488 dsb->ins_start_offset = 0;
489+ dsb->dewake_scanline = intel_dsb_dewake_scanline(crtc_state);
331490
332491 return dsb;
333492
drivers/gpu/drm/i915/display/intel_dsb.h+8−1
@@ -11,14 +11,21 @@ · 10 unmodified lines
1111 #include "i915_reg_defs.h"
1212
1313 struct intel_crtc;
14+struct intel_crtc_state;
1415 struct intel_dsb;
1516
16−struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc,
17+struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state,
1718 unsigned int max_cmds);
1819 void intel_dsb_finish(struct intel_dsb *dsb);
1920 void intel_dsb_cleanup(struct intel_dsb *dsb);
2021 void intel_dsb_reg_write(struct intel_dsb *dsb,
2122 i915_reg_t reg, u32 val);
23+void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
24+ i915_reg_t reg, u32 mask, u32 val);
25+void intel_dsb_noop(struct intel_dsb *dsb, int count);
26+void intel_dsb_nonpost_start(struct intel_dsb *dsb);
27+void intel_dsb_nonpost_end(struct intel_dsb *dsb);
28+
2229 void intel_dsb_commit(struct intel_dsb *dsb,
2330 bool wait_for_vblank);
2431 void intel_dsb_wait(struct intel_dsb *dsb);
drivers/gpu/drm/i915/display/intel_dsb_regs.h+31−0
@@ -37,6 +37,19 @@ · 36 unmodified lines
3737 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
3838 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
3939 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
40+#define DSB_HP_IDLE_STATUS REG_BIT(31)
41+#define DSB_DEWAKE_STATUS REG_BIT(30)
42+#define DSB_REQARB_SM_STATE_MASK REG_GENMASK(29, 27)
43+#define DSB_SAFE_WINDOW_LIVE REG_BIT(26)
44+#define DSB_VTDFAULT_ARB_SM_STATE_MASK REG_GENMASK(25, 23)
45+#define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20)
46+#define DSB_SAFE_WINDOW REG_BIT(19)
47+#define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17)
48+#define DSB_BUSY_ON_DELAYED_VBLANK REG_BIT(16)
49+#define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13)
50+#define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7)
51+#define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4)
52+#define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0)
4053 #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
4154 #define DSB_ATS_FAULT_INT_EN REG_BIT(20)
4255 #define DSB_GTT_FAULT_INT_EN REG_BIT(19)
@@ -58,10 +71,28 @@ · 15 unmodified lines
5871 #define DSB_RM_READY_TIMEOUT_VALUE(x) REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */
5972 #define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)
6073 #define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
74+#define DSB_ENABLE_DEWAKE REG_BIT(31)
75+#define DSB_SCANLINE_FOR_DEWAKE_MASK REG_GENMASK(30, 0)
76+#define DSB_SCANLINE_FOR_DEWAKE(x) REG_FIELD_PREP(DSB_SCANLINE_FOR_DEWAKE_MASK, (x))
6177 #define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)
78+#define DSB_MMIOGEN_DEWAKE_DIS REG_BIT(31)
79+#define DSB_FORCE_DEWAKE REG_BIT(23)
80+#define DSB_BLOCK_DEWAKE_EXTENSION REG_BIT(15)
81+#define DSB_OVERRIDE_DC5_DC6_OK REG_BIT(7)
6282 #define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)
6383 #define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)
6484 #define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)
6585 #define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)
86+#define DSB_FORCE_DMA_SYNC_RESET REG_BIT(31)
87+#define DSB_FORCE_VTD_ENGIE_RESET REG_BIT(30)
88+#define DSB_DISABLE_IPC_DEMOTE REG_BIT(29)
89+#define DSB_SKIP_WAITS_EN REG_BIT(23)
90+#define DSB_EXTEND_HP_IDLE REG_BIT(16)
91+#define DSB_CTRL_WAIT_SAFE_WINDOW REG_BIT(15)
92+#define DSB_CTRL_NO_WAIT_VBLANK REG_BIT(14)
93+#define DSB_INST_WAIT_SAFE_WINDOW REG_BIT(7)
94+#define DSB_INST_NO_WAIT_VBLANK REG_BIT(6)
95+#define DSB_MMIOGEN_DEWAKE_DIS_CHICKEN REG_BIT(2)
96+#define DSB_DISABLE_MMIO_COUNT_FOR_INDEXED REG_BIT(0)
6697
6798 #endif /* __INTEL_DSB_REGS_H__ */
drivers/gpu/drm/i915/display/intel_dvo.c+5−6
@@ -328,7 +328,6 @@ intel_dvo_detect(struct drm_connector *_connector, bool force) · 327 unmodified lines
328328 static int intel_dvo_get_modes(struct drm_connector *_connector)
329329 {
330330 struct intel_connector *connector = to_intel_connector(_connector);
331− struct drm_i915_private *i915 = to_i915(connector->base.dev);
332331 int num_modes;
333332
334333 /*
@@ -337,8 +336,7 @@ static int intel_dvo_get_modes(struct drm_connector *_connector) · 2 unmodified lines
337336 * (TV-out, for example), but for now with just TMDS and LVDS,
338337 * that's not the case.
339338 */
340− num_modes = intel_ddc_get_modes(&connector->base,
341− intel_gmbus_get_adapter(i915, GMBUS_PIN_DPC));
339+ num_modes = intel_ddc_get_modes(&connector->base, connector->base.ddc);
342340 if (num_modes)
343341 return num_modes;
344342
@@ -533,9 +531,10 @@ void intel_dvo_init(struct drm_i915_private *i915) · 188 unmodified lines
533531 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
534532 DRM_CONNECTOR_POLL_DISCONNECT;
535533
536− drm_connector_init(&i915->drm, &connector->base,
537− &intel_dvo_connector_funcs,
538− intel_dvo_connector_type(&intel_dvo->dev));
534+ drm_connector_init_with_ddc(&i915->drm, &connector->base,
535+ &intel_dvo_connector_funcs,
536+ intel_dvo_connector_type(&intel_dvo->dev),
537+ intel_gmbus_get_adapter(i915, GMBUS_PIN_DPC));
539538
540539 drm_connector_helper_add(&connector->base,
541540 &intel_dvo_connector_helper_funcs);
drivers/gpu/drm/i915/display/intel_fb.c+58−3
@@ -7,11 +7,15 @@ · 6 unmodified lines
77 #include <drm/drm_framebuffer.h>
88 #include <drm/drm_modeset_helper.h>
99
10+#include <linux/dma-fence.h>
11+#include <linux/dma-resv.h>
12+
1013 #include "i915_drv.h"
1114 #include "intel_display.h"
1215 #include "intel_display_types.h"
1316 #include "intel_dpt.h"
1417 #include "intel_fb.h"
18+#include "intel_frontbuffer.h"
1519
1620 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
1721
@@ -1896,6 +1900,21 @@ static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, · 1878 unmodified lines
18961900 return drm_gem_handle_create(file, &obj->base, handle);
18971901 }
18981902
1903+struct frontbuffer_fence_cb {
1904+ struct dma_fence_cb base;
1905+ struct intel_frontbuffer *front;
1906+};
1907+
1908+static void intel_user_framebuffer_fence_wake(struct dma_fence *dma,
1909+ struct dma_fence_cb *data)
1910+{
1911+ struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base);
1912+
1913+ intel_frontbuffer_queue_flush(cb->front);
1914+ kfree(cb);
1915+ dma_fence_put(dma);
1916+}
1917+
18991918 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
19001919 struct drm_file *file,
19011920 unsigned int flags, unsigned int color,
@@ -1903,11 +1922,47 @@ static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, · 1 unmodified line
19031922 unsigned int num_clips)
19041923 {
19051924 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1925+ struct intel_frontbuffer *front = to_intel_frontbuffer(fb);
1926+ struct dma_fence *fence;
1927+ struct frontbuffer_fence_cb *cb;
1928+ int ret = 0;
19061929
1907− i915_gem_object_flush_if_display(obj);
1908− intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
1930+ if (!atomic_read(&front->bits))
1931+ return 0;
19091932
1910− return 0;
1933+ if (dma_resv_test_signaled(obj->base.resv, dma_resv_usage_rw(false)))
1934+ goto flush;
1935+
1936+ ret = dma_resv_get_singleton(obj->base.resv, dma_resv_usage_rw(false),
1937+ &fence);
1938+ if (ret || !fence)
1939+ goto flush;
1940+
1941+ cb = kmalloc(sizeof(*cb), GFP_KERNEL);
1942+ if (!cb) {
1943+ dma_fence_put(fence);
1944+ ret = -ENOMEM;
1945+ goto flush;
1946+ }
1947+
1948+ cb->front = front;
1949+
1950+ intel_frontbuffer_invalidate(front, ORIGIN_DIRTYFB);
1951+
1952+ ret = dma_fence_add_callback(fence, &cb->base,
1953+ intel_user_framebuffer_fence_wake);
1954+ if (ret) {
1955+ intel_user_framebuffer_fence_wake(fence, &cb->base);
1956+ if (ret == -ENOENT)
1957+ ret = 0;
1958+ }
1959+
1960+ return ret;
1961+
1962+flush:
1963+ i915_gem_object_flush_if_display(obj);
1964+ intel_frontbuffer_flush(front, ORIGIN_DIRTYFB);
1965+ return ret;
19111966 }
19121967
19131968 static const struct drm_framebuffer_funcs intel_fb_funcs = {
drivers/gpu/drm/i915/display/intel_fb_pin.c+2−1
@@ -35,7 +35,8 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, · 34 unmodified lines
3535 * We are not syncing against the binding (and potential migrations)
3636 * below, so this vm must never be async.
3737 */
38− GEM_WARN_ON(vm->bind_async_flags);
38+ if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags))
39+ return ERR_PTR(-EINVAL);
3940
4041 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
4142 return ERR_PTR(-EINVAL);
drivers/gpu/drm/i915/display/intel_fbc.c+12−11
@@ -50,6 +50,7 @@ · 49 unmodified lines
5050 #include "i915_vma.h"
5151 #include "intel_cdclk.h"
5252 #include "intel_de.h"
53+#include "intel_display_device.h"
5354 #include "intel_display_trace.h"
5455 #include "intel_display_types.h"
5556 #include "intel_fbc.h"
@@ -332,12 +333,14 @@ static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) · 276 unmodified lines
332333 {
333334 struct drm_i915_private *i915 = fbc->i915;
334335
335− GEM_BUG_ON(range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
336− i915_gem_stolen_node_offset(&fbc->compressed_fb),
337− U32_MAX));
338− GEM_BUG_ON(range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
339− i915_gem_stolen_node_offset(&fbc->compressed_llb),
340− U32_MAX));
336+ drm_WARN_ON(&i915->drm,
337+ range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
338+ i915_gem_stolen_node_offset(&fbc->compressed_fb),
339+ U32_MAX));
340+ drm_WARN_ON(&i915->drm,
341+ range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
342+ i915_gem_stolen_node_offset(&fbc->compressed_llb),
343+ U32_MAX));
341344 intel_de_write(i915, FBC_CFB_BASE,
342345 i915_gem_stolen_node_address(i915, &fbc->compressed_fb));
343346 intel_de_write(i915, FBC_LL_BASE,
@@ -1100,7 +1103,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, · 756 unmodified lines
11001103
11011104 /* Wa_14016291713 */
11021105 if ((IS_DISPLAY_VER(i915, 12, 13) ||
1103− IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
1106+ IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
11041107 crtc_state->has_psr) {
11051108 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
11061109 return 0;
@@ -1306,11 +1309,9 @@ static void __intel_fbc_post_update(struct intel_fbc *fbc) · 199 unmodified lines
13061309 lockdep_assert_held(&fbc->lock);
13071310
13081311 fbc->flip_pending = false;
1312+ fbc->busy_bits = 0;
13091313
1310− if (!fbc->busy_bits)
1311− intel_fbc_activate(fbc);
1312− else
1313− intel_fbc_deactivate(fbc, "frontbuffer write");
1314+ intel_fbc_activate(fbc);
13141315 }
13151316
13161317 void intel_fbc_post_update(struct intel_atomic_state *state,
drivers/gpu/drm/i915/display/intel_fbc.h+2−0
@@ -20,6 +20,8 @@ struct intel_plane_state; · 19 unmodified lines
2020 enum intel_fbc_id {
2121 INTEL_FBC_A,
2222 INTEL_FBC_B,
23+ INTEL_FBC_C,
24+ INTEL_FBC_D,
2325
2426 I915_MAX_FBCS,
2527 };
drivers/gpu/drm/i915/display/intel_fdi.c+149−20
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include "intel_display_types.h"
1414 #include "intel_fdi.h"
1515 #include "intel_fdi_regs.h"
16+#include "intel_link_bw.h"
1617
1718 struct intel_fdi_funcs {
1819 void (*fdi_link_train)(struct intel_crtc *crtc,
@@ -119,6 +120,53 @@ void intel_fdi_link_train(struct intel_crtc *crtc, · 100 unmodified lines
119120 dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
120121 }
121122
123+/**
124+ * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs
125+ * @state: intel atomic state
126+ *
127+ * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is
128+ * known to affect the available FDI BW for the former CRTC. In practice this
129+ * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by
130+ * CRTC C) and CRTC C is getting disabled.
131+ *
132+ * Returns 0 in case of success, or a negative error code otherwise.
133+ */
134+int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state)
135+{
136+ struct drm_i915_private *i915 = to_i915(state->base.dev);
137+ const struct intel_crtc_state *old_crtc_state;
138+ const struct intel_crtc_state *new_crtc_state;
139+ struct intel_crtc *crtc;
140+
141+ if (!IS_IVYBRIDGE(i915) || INTEL_NUM_PIPES(i915) != 3)
142+ return 0;
143+
144+ crtc = intel_crtc_for_pipe(i915, PIPE_C);
145+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
146+ if (!new_crtc_state)
147+ return 0;
148+
149+ if (!intel_crtc_needs_modeset(new_crtc_state))
150+ return 0;
151+
152+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
153+ if (!old_crtc_state->fdi_lanes)
154+ return 0;
155+
156+ crtc = intel_crtc_for_pipe(i915, PIPE_B);
157+ new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
158+ if (IS_ERR(new_crtc_state))
159+ return PTR_ERR(new_crtc_state);
160+
161+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
162+ if (!old_crtc_state->fdi_lanes)
163+ return 0;
164+
165+ return intel_modeset_pipes_in_mask_early(state,
166+ "FDI link BW decrease on pipe C",
167+ BIT(PIPE_B));
168+}
169+
122170 /* units of 100MHz */
123171 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
124172 {
@@ -129,13 +177,16 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) · 4 unmodified lines
129177 }
130178
131179 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
132− struct intel_crtc_state *pipe_config)
180+ struct intel_crtc_state *pipe_config,
181+ enum pipe *pipe_to_reduce)
133182 {
134183 struct drm_i915_private *dev_priv = to_i915(dev);
135184 struct drm_atomic_state *state = pipe_config->uapi.state;
136185 struct intel_crtc *other_crtc;
137186 struct intel_crtc_state *other_crtc_state;
138187
188+ *pipe_to_reduce = pipe;
189+
139190 drm_dbg_kms(&dev_priv->drm,
140191 "checking fdi config on pipe %c, lanes %i\n",
141192 pipe_name(pipe), pipe_config->fdi_lanes);
@@ -198,6 +249,9 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, · 56 unmodified lines
198249 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
199250 drm_dbg_kms(&dev_priv->drm,
200251 "fdi link B uses too many lanes to enable link C\n");
252+
253+ *pipe_to_reduce = PIPE_B;
254+
201255 return -EINVAL;
202256 }
203257 return 0;
@@ -232,16 +286,42 @@ int intel_fdi_link_freq(struct drm_i915_private *i915, · 28 unmodified lines
232286 return i915->display.fdi.pll_freq;
233287 }
234288
289+/**
290+ * intel_fdi_compute_pipe_bpp - compute pipe bpp limited by max link bpp
291+ * @crtc_state: the crtc state
292+ *
293+ * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
294+ * call this function during state computation in the simple case where the
295+ * link bpp will always match the pipe bpp. This is the case for all non-DP
296+ * encoders, while DP encoders will use a link bpp lower than pipe bpp in case
297+ * of DSC compression.
298+ *
299+ * Returns %true in case of success, %false if pipe bpp would need to be
300+ * reduced below its valid range.
301+ */
302+bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
303+{
304+ int pipe_bpp = min(crtc_state->pipe_bpp,
305+ to_bpp_int(crtc_state->max_link_bpp_x16));
306+
307+ pipe_bpp = rounddown(pipe_bpp, 2 * 3);
308+
309+ if (pipe_bpp < 6 * 3)
310+ return false;
311+
312+ crtc_state->pipe_bpp = pipe_bpp;
313+
314+ return true;
315+}
316+
235317 int ilk_fdi_compute_config(struct intel_crtc *crtc,
236318 struct intel_crtc_state *pipe_config)
237319 {
238320 struct drm_device *dev = crtc->base.dev;
239321 struct drm_i915_private *i915 = to_i915(dev);
240322 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
241− int lane, link_bw, fdi_dotclock, ret;
242− bool needs_recompute = false;
323+ int lane, link_bw, fdi_dotclock;
243324
244−retry:
245325 /* FDI is a binary signal running at ~2.7GHz, encoding
246326 * each output octet as 10 bits. The actual frequency
247327 * is stored as a divider into a 100MHz clock, and the
@@ -261,25 +341,69 @@ retry: · 13 unmodified lines
261341 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
262342 link_bw, &pipe_config->fdi_m_n, false);
263343
264− ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
265− if (ret == -EDEADLK)
344+ return 0;
345+}
346+
347+static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state,
348+ struct intel_crtc *crtc,
349+ struct intel_crtc_state *pipe_config,
350+ struct intel_link_bw_limits *limits)
351+{
352+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
353+ enum pipe pipe_to_reduce;
354+ int ret;
355+
356+ ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config,
357+ &pipe_to_reduce);
358+ if (ret != -EINVAL)
266359 return ret;
267360
268− if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
269− pipe_config->pipe_bpp -= 2*3;
270− drm_dbg_kms(&i915->drm,
271− "fdi link bw constraint, reducing pipe bpp to %i\n",
272− pipe_config->pipe_bpp);
273− needs_recompute = true;
274− pipe_config->bw_constrained = true;
361+ ret = intel_link_bw_reduce_bpp(state, limits,
362+ BIT(pipe_to_reduce),
363+ "FDI link BW");
275364
276− goto retry;
277− }
365+ return ret ? : -EAGAIN;
366+}
367+
368+/**
369+ * intel_fdi_atomic_check_link - check all modeset FDI link configuration
370+ * @state: intel atomic state
371+ * @limits: link BW limits
372+ *
373+ * Check the link configuration for all modeset FDI outputs. If the
374+ * configuration is invalid @limits will be updated if possible to
375+ * reduce the total BW, after which the configuration for all CRTCs in
376+ * @state must be recomputed with the updated @limits.
377+ *
378+ * Returns:
379+ * - 0 if the confugration is valid
380+ * - %-EAGAIN, if the configuration is invalid and @limits got updated
381+ * with fallback values with which the configuration of all CRTCs
382+ * in @state must be recomputed
383+ * - Other negative error, if the configuration is invalid without a
384+ * fallback possibility, or the check failed for another reason
385+ */
386+int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
387+ struct intel_link_bw_limits *limits)
388+{
389+ struct intel_crtc *crtc;
390+ struct intel_crtc_state *crtc_state;
391+ int i;
392+
393+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
394+ int ret;
395+
396+ if (!crtc_state->has_pch_encoder ||
397+ !intel_crtc_needs_modeset(crtc_state) ||
398+ !crtc_state->hw.enable)
399+ continue;
278400
279− if (needs_recompute)
280− return -EAGAIN;
401+ ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);
402+ if (ret)
403+ return ret;
404+ }
281405
282− return ret;
406+ return 0;
283407 }
284408
285409 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
@@ -766,7 +890,10 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, · 480 unmodified lines
766890 * WaFDIAutoLinkSetTimingOverrride:hsw
767891 */
768892 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
769− FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
893+ FDI_RX_PWRDN_LANE1_VAL(2) |
894+ FDI_RX_PWRDN_LANE0_VAL(2) |
895+ FDI_RX_TP1_TO_TP2_48 |
896+ FDI_RX_FDI_DELAY_90);
770897
771898 /* Enable the PCH Receiver FDI PLL */
772899 rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
@@ -799,7 +926,9 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, · 26 unmodified lines
799926 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
800927 * port reversal bit */
801928 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
802− DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
929+ DDI_BUF_CTL_ENABLE |
930+ ((crtc_state->fdi_lanes - 1) << 1) |
931+ DDI_BUF_TRANS_SELECT(i / 2));
803932 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
804933
805934 udelay(600);
drivers/gpu/drm/i915/display/intel_fdi.h+8−0
@@ -6,16 +6,24 @@ · 5 unmodified lines
66 #ifndef _INTEL_FDI_H_
77 #define _INTEL_FDI_H_
88
9+#include <linux/types.h>
10+
911 enum pipe;
1012 struct drm_i915_private;
13+struct intel_atomic_state;
1114 struct intel_crtc;
1215 struct intel_crtc_state;
1316 struct intel_encoder;
17+struct intel_link_bw_limits;
1418
19+int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state);
1520 int intel_fdi_link_freq(struct drm_i915_private *i915,
1621 const struct intel_crtc_state *pipe_config);
22+bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
1723 int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
1824 struct intel_crtc_state *pipe_config);
25+int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
26+ struct intel_link_bw_limits *limits);
1927 void intel_fdi_normal_train(struct intel_crtc *crtc);
2028 void ilk_fdi_disable(struct intel_crtc *crtc);
2129 void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc);
drivers/gpu/drm/i915/display/intel_frontbuffer.c+32−2
@@ -55,6 +55,7 @@ · 54 unmodified lines
5555 * cancelled as soon as busyness is detected.
5656 */
5757
58+#include "gem/i915_gem_object_frontbuffer.h"
5859 #include "i915_drv.h"
5960 #include "intel_display_trace.h"
6061 #include "intel_display_types.h"
@@ -202,6 +203,33 @@ void __intel_fb_flush(struct intel_frontbuffer *front, · 141 unmodified lines
202203 frontbuffer_flush(i915, frontbuffer_bits, origin);
203204 }
204205
206+static void intel_frontbuffer_flush_work(struct work_struct *work)
207+{
208+ struct intel_frontbuffer *front =
209+ container_of(work, struct intel_frontbuffer, flush_work);
210+
211+ i915_gem_object_flush_if_display(front->obj);
212+ intel_frontbuffer_flush(front, ORIGIN_DIRTYFB);
213+ intel_frontbuffer_put(front);
214+}
215+
216+/**
217+ * intel_frontbuffer_queue_flush - queue flushing frontbuffer object
218+ * @front: GEM object to flush
219+ *
220+ * This function is targeted for our dirty callback for queueing flush when
221+ * dma fence is signales
222+ */
223+void intel_frontbuffer_queue_flush(struct intel_frontbuffer *front)
224+{
225+ if (!front)
226+ return;
227+
228+ kref_get(&front->ref);
229+ if (!schedule_work(&front->flush_work))
230+ intel_frontbuffer_put(front);
231+}
232+
205233 static int frontbuffer_active(struct i915_active *ref)
206234 {
207235 struct intel_frontbuffer *front =
@@ -223,7 +251,7 @@ static void frontbuffer_retire(struct i915_active *ref) · 15 unmodified lines
223251 static void frontbuffer_release(struct kref *ref)
224252 __releases(&intel_bo_to_i915(front->obj)->display.fb_tracking.lock)
225253 {
226− struct intel_frontbuffer *front =
254+ struct intel_frontbuffer *ret, *front =
227255 container_of(ref, typeof(*front), ref);
228256 struct drm_i915_gem_object *obj = front->obj;
229257
@@ -231,7 +259,8 @@ static void frontbuffer_release(struct kref *ref) · 1 unmodified line
231259
232260 i915_ggtt_clear_scanout(obj);
233261
234− i915_gem_object_set_frontbuffer(obj, NULL);
262+ ret = i915_gem_object_set_frontbuffer(obj, NULL);
263+ drm_WARN_ON(&intel_bo_to_i915(obj)->drm, ret);
235264 spin_unlock(&intel_bo_to_i915(obj)->display.fb_tracking.lock);
236265
237266 i915_active_fini(&front->write);
@@ -261,6 +290,7 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj) · 23 unmodified lines
261290 frontbuffer_active,
262291 frontbuffer_retire,
263292 I915_ACTIVE_RETIRE_SLEEPS);
293+ INIT_WORK(&front->flush_work, intel_frontbuffer_flush_work);
264294
265295 spin_lock(&i915->display.fb_tracking.lock);
266296 cur = i915_gem_object_set_frontbuffer(obj, front);
drivers/gpu/drm/i915/display/intel_frontbuffer.h+4−0
@@ -46,6 +46,8 @@ struct intel_frontbuffer { · 45 unmodified lines
4646 struct i915_active write;
4747 struct drm_i915_gem_object *obj;
4848 struct rcu_head rcu;
49+
50+ struct work_struct flush_work;
4951 };
5052
5153 /*
@@ -135,6 +137,8 @@ static inline void intel_frontbuffer_flush(struct intel_frontbuffer *front, · 83 unmodified lines
135137 __intel_fb_flush(front, origin, frontbuffer_bits);
136138 }
137139
140+void intel_frontbuffer_queue_flush(struct intel_frontbuffer *front);
141+
138142 void intel_frontbuffer_track(struct intel_frontbuffer *old,
139143 struct intel_frontbuffer *new,
140144 unsigned int frontbuffer_bits);
drivers/gpu/drm/i915/display/intel_gmbus.c+4−1
@@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, · 154 unmodified lines
155155 const struct gmbus_pin *pins;
156156 size_t size;
157157
158− if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
158+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
159+ pins = gmbus_pins_mtp;
160+ size = ARRAY_SIZE(gmbus_pins_mtp);
161+ } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
159162 pins = gmbus_pins_dg2;
160163 size = ARRAY_SIZE(gmbus_pins_dg2);
161164 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
drivers/gpu/drm/i915/display/intel_hdcp.c+14−19
@@ -163,7 +163,6 @@ bool intel_hdcp_capable(struct intel_connector *connector) · 162 unmodified lines
163163 /* Is HDCP2.2 capable on Platform and Sink */
164164 bool intel_hdcp2_capable(struct intel_connector *connector)
165165 {
166− struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
167166 struct drm_i915_private *i915 = to_i915(connector->base.dev);
168167 struct intel_hdcp *hdcp = &connector->hdcp;
169168 bool capable = false;
@@ -193,7 +192,7 @@ bool intel_hdcp2_capable(struct intel_connector *connector) · 23 unmodified lines
193192 mutex_unlock(&i915->display.hdcp.hdcp_mutex);
194193
195194 /* Sink's capability for HDCP2.2 */
196− hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
195+ hdcp->shim->hdcp_2_2_capable(connector, &capable);
197196
198197 return capable;
199198 }
@@ -1415,7 +1414,6 @@ static int hdcp2_deauthenticate_port(struct intel_connector *connector) · 1215 unmodified lines
14151414 /* Authentication flow starts from here */
14161415 static int hdcp2_authentication_key_exchange(struct intel_connector *connector)
14171416 {
1418− struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
14191417 struct drm_i915_private *i915 = to_i915(connector->base.dev);
14201418 struct intel_hdcp *hdcp = &connector->hdcp;
14211419 union {
@@ -1437,12 +1435,12 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) · 15 unmodified lines
14371435 if (ret < 0)
14381436 return ret;
14391437
1440− ret = shim->write_2_2_msg(dig_port, &msgs.ake_init,
1438+ ret = shim->write_2_2_msg(connector, &msgs.ake_init,
14411439 sizeof(msgs.ake_init));
14421440 if (ret < 0)
14431441 return ret;
14441442
1445− ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_CERT,
1443+ ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT,
14461444 &msgs.send_cert, sizeof(msgs.send_cert));
14471445 if (ret < 0)
14481446 return ret;
@@ -1471,11 +1469,11 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) · 22 unmodified lines
14711469 if (ret < 0)
14721470 return ret;
14731471
1474− ret = shim->write_2_2_msg(dig_port, &msgs.no_stored_km, size);
1472+ ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size);
14751473 if (ret < 0)
14761474 return ret;
14771475
1478− ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_HPRIME,
1476+ ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME,
14791477 &msgs.send_hprime, sizeof(msgs.send_hprime));
14801478 if (ret < 0)
14811479 return ret;
@@ -1486,7 +1484,7 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) · 4 unmodified lines
14861484
14871485 if (!hdcp->is_paired) {
14881486 /* Pairing is required */
1489− ret = shim->read_2_2_msg(dig_port,
1487+ ret = shim->read_2_2_msg(connector,
14901488 HDCP_2_2_AKE_SEND_PAIRING_INFO,
14911489 &msgs.pairing_info,
14921490 sizeof(msgs.pairing_info));
@@ -1504,7 +1502,6 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) · 11 unmodified lines
15041502
15051503 static int hdcp2_locality_check(struct intel_connector *connector)
15061504 {
1507− struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
15081505 struct intel_hdcp *hdcp = &connector->hdcp;
15091506 union {
15101507 struct hdcp2_lc_init lc_init;
@@ -1518,12 +1515,12 @@ static int hdcp2_locality_check(struct intel_connector *connector) · 7 unmodified lines
15181515 if (ret < 0)
15191516 continue;
15201517
1521− ret = shim->write_2_2_msg(dig_port, &msgs.lc_init,
1518+ ret = shim->write_2_2_msg(connector, &msgs.lc_init,
15221519 sizeof(msgs.lc_init));
15231520 if (ret < 0)
15241521 continue;
15251522
1526− ret = shim->read_2_2_msg(dig_port,
1523+ ret = shim->read_2_2_msg(connector,
15271524 HDCP_2_2_LC_SEND_LPRIME,
15281525 &msgs.send_lprime,
15291526 sizeof(msgs.send_lprime));
@@ -1540,7 +1537,6 @@ static int hdcp2_locality_check(struct intel_connector *connector) · 10 unmodified lines
15401537
15411538 static int hdcp2_session_key_exchange(struct intel_connector *connector)
15421539 {
1543− struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
15441540 struct intel_hdcp *hdcp = &connector->hdcp;
15451541 struct hdcp2_ske_send_eks send_eks;
15461542 int ret;
@@ -1549,7 +1545,7 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector) · 2 unmodified lines
15491545 if (ret < 0)
15501546 return ret;
15511547
1552− ret = hdcp->shim->write_2_2_msg(dig_port, &send_eks,
1548+ ret = hdcp->shim->write_2_2_msg(connector, &send_eks,
15531549 sizeof(send_eks));
15541550 if (ret < 0)
15551551 return ret;
@@ -1587,12 +1583,12 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) · 31 unmodified lines
15871583 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
15881584 sizeof(struct hdcp2_streamid_type);
15891585 /* Send it to Repeater */
1590− ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
1586+ ret = shim->write_2_2_msg(connector, &msgs.stream_manage,
15911587 sizeof(msgs.stream_manage) - streams_size_delta);
15921588 if (ret < 0)
15931589 goto out;
15941590
1595− ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_STREAM_READY,
1591+ ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY,
15961592 &msgs.stream_ready, sizeof(msgs.stream_ready));
15971593 if (ret < 0)
15981594 goto out;
@@ -1622,7 +1618,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) · 23 unmodified lines
16221618 u8 *rx_info;
16231619 int ret;
16241620
1625− ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_SEND_RECVID_LIST,
1621+ ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST,
16261622 &msgs.recvid_list, sizeof(msgs.recvid_list));
16271623 if (ret < 0)
16281624 return ret;
@@ -1675,7 +1671,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) · 46 unmodified lines
16751671 return ret;
16761672
16771673 hdcp->seq_num_v = seq_num_v;
1678− ret = shim->write_2_2_msg(dig_port, &msgs.rep_ack,
1674+ ret = shim->write_2_2_msg(connector, &msgs.rep_ack,
16791675 sizeof(msgs.rep_ack));
16801676 if (ret < 0)
16811677 return ret;
@@ -1685,7 +1681,6 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) · 3 unmodified lines
16851681
16861682 static int hdcp2_authenticate_sink(struct intel_connector *connector)
16871683 {
1688− struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
16891684 struct drm_i915_private *i915 = to_i915(connector->base.dev);
16901685 struct intel_hdcp *hdcp = &connector->hdcp;
16911686 const struct intel_hdcp_shim *shim = hdcp->shim;
@@ -1711,7 +1706,7 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) · 19 unmodified lines
17111706 }
17121707
17131708 if (shim->config_stream_type) {
1714− ret = shim->config_stream_type(dig_port,
1709+ ret = shim->config_stream_type(connector,
17151710 hdcp->is_repeater,
17161711 hdcp->content_type);
17171712 if (ret < 0)
drivers/gpu/drm/i915/display/intel_hdmi.c+39−82
@@ -1240,26 +1240,23 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, · 1239 unmodified lines
12401240 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
12411241 {
12421242 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1243− struct i2c_adapter *adapter;
1243+ struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
12441244
12451245 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
12461246 return;
12471247
1248− adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1249−
12501248 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
12511249 enable ? "Enabling" : "Disabling");
12521250
1253− drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1251+ drm_dp_dual_mode_set_tmds_output(&dev_priv->drm,
1252+ hdmi->dp_dual_mode.type, ddc, enable);
12541253 }
12551254
12561255 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
12571256 unsigned int offset, void *buffer, size_t size)
12581257 {
1259− struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
12601258 struct intel_hdmi *hdmi = &dig_port->hdmi;
1261− struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1262− hdmi->ddc_bus);
1259+ struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
12631260 int ret;
12641261 u8 start = offset & 0xff;
12651262 struct i2c_msg msgs[] = {
@@ -1276,7 +1273,7 @@ static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, · 10 unmodified lines
12761273 .buf = buffer
12771274 }
12781275 };
1279− ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1276+ ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs));
12801277 if (ret == ARRAY_SIZE(msgs))
12811278 return 0;
12821279 return ret >= 0 ? -EIO : ret;
@@ -1285,10 +1282,8 @@ static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, · 2 unmodified lines
12851282 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
12861283 unsigned int offset, void *buffer, size_t size)
12871284 {
1288− struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
12891285 struct intel_hdmi *hdmi = &dig_port->hdmi;
1290− struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1291− hdmi->ddc_bus);
1286+ struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
12921287 int ret;
12931288 u8 *write_buf;
12941289 struct i2c_msg msg;
@@ -1305,7 +1300,7 @@ static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, · 10 unmodified lines
13051300 msg.len = size + 1,
13061301 msg.buf = write_buf;
13071302
1308− ret = i2c_transfer(adapter, &msg, 1);
1303+ ret = i2c_transfer(ddc, &msg, 1);
13091304 if (ret == 1)
13101305 ret = 0;
13111306 else if (ret >= 0)
@@ -1321,8 +1316,7 @@ int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, · 9 unmodified lines
13211316 {
13221317 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
13231318 struct intel_hdmi *hdmi = &dig_port->hdmi;
1324− struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1325− hdmi->ddc_bus);
1319+ struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
13261320 int ret;
13271321
13281322 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
@@ -1333,7 +1327,7 @@ int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, · 4 unmodified lines
13331327 return ret;
13341328 }
13351329
1336− ret = intel_gmbus_output_aksv(adapter);
1330+ ret = intel_gmbus_output_aksv(ddc);
13371331 if (ret < 0) {
13381332 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
13391333 return ret;
@@ -1665,9 +1659,10 @@ intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, · 325 unmodified lines
16651659 }
16661660
16671661 static
1668−int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1662+int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector,
16691663 void *buf, size_t size)
16701664 {
1665+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
16711666 unsigned int offset;
16721667
16731668 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
@@ -1675,9 +1670,10 @@ int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, · 1 unmodified line
16751670 }
16761671
16771672 static
1678−int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1673+int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector,
16791674 u8 msg_id, void *buf, size_t size)
16801675 {
1676+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
16811677 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
16821678 struct intel_hdmi *hdmi = &dig_port->hdmi;
16831679 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
@@ -1733,9 +1729,10 @@ int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, · 49 unmodified lines
17331729 }
17341730
17351731 static
1736−int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1732+int intel_hdmi_hdcp2_capable(struct intel_connector *connector,
17371733 bool *capable)
17381734 {
1735+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
17391736 u8 hdcp2_version;
17401737 int ret;
17411738
@@ -2400,9 +2397,10 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) · 658 unmodified lines
24002397 struct drm_i915_private *dev_priv = to_i915(connector->dev);
24012398 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
24022399 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2403− struct i2c_adapter *adapter =
2404− intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2405− enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2400+ struct i2c_adapter *ddc = connector->ddc;
2401+ enum drm_dp_dual_mode_type type;
2402+
2403+ type = drm_dp_dual_mode_detect(&dev_priv->drm, ddc);
24062404
24072405 /*
24082406 * Type 1 DVI adaptors are not required to implement any
@@ -2429,7 +2427,7 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) · 20 unmodified lines
24292427
24302428 hdmi->dp_dual_mode.type = type;
24312429 hdmi->dp_dual_mode.max_tmds_clock =
2432− drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2430+ drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, ddc);
24332431
24342432 drm_dbg_kms(&dev_priv->drm,
24352433 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
@@ -2450,24 +2448,21 @@ intel_hdmi_set_edid(struct drm_connector *connector) · 14 unmodified lines
24502448 {
24512449 struct drm_i915_private *dev_priv = to_i915(connector->dev);
24522450 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2451+ struct i2c_adapter *ddc = connector->ddc;
24532452 intel_wakeref_t wakeref;
24542453 const struct drm_edid *drm_edid;
2455− const struct edid *edid;
24562454 bool connected = false;
2457− struct i2c_adapter *i2c;
24582455
24592456 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
24602457
2461− i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2458+ drm_edid = drm_edid_read_ddc(connector, ddc);
24622459
2463− drm_edid = drm_edid_read_ddc(connector, i2c);
2464−
2465− if (!drm_edid && !intel_gmbus_is_forced_bit(i2c)) {
2460+ if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
24662461 drm_dbg_kms(&dev_priv->drm,
24672462 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2468− intel_gmbus_force_bit(i2c, true);
2469− drm_edid = drm_edid_read_ddc(connector, i2c);
2470− intel_gmbus_force_bit(i2c, false);
2463+ intel_gmbus_force_bit(ddc, true);
2464+ drm_edid = drm_edid_read_ddc(connector, ddc);
2465+ intel_gmbus_force_bit(ddc, false);
24712466 }
24722467
24732468 /* Below we depend on display info having been updated */
@@ -2475,9 +2470,7 @@ intel_hdmi_set_edid(struct drm_connector *connector) · 1 unmodified line
24752470
24762471 to_intel_connector(connector)->detect_edid = drm_edid;
24772472
2478− /* FIXME: Get rid of drm_edid_raw() */
2479− edid = drm_edid_raw(drm_edid);
2480− if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2473+ if (drm_edid_is_digital(drm_edid)) {
24812474 intel_hdmi_dp_dual_mode_detect(connector);
24822475
24832476 connected = true;
@@ -2485,7 +2478,8 @@ intel_hdmi_set_edid(struct drm_connector *connector) · 1 unmodified line
24852478
24862479 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
24872480
2488− cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2481+ cec_notifier_set_phys_addr(intel_hdmi->cec_notifier,
2482+ connector->display_info.source_physical_address);
24892483
24902484 return connected;
24912485 }
@@ -2522,12 +2516,6 @@ out: · 30 unmodified lines
25222516 if (status != connector_status_connected)
25232517 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
25242518
2525− /*
2526− * Make sure the refs for power wells enabled during detect are
2527− * dropped to avoid a new detect cycle triggered by HPD polling.
2528− */
2529− intel_display_power_flush_work(dev_priv);
2530−
25312519 return status;
25322520 }
25332521
@@ -2553,37 +2541,6 @@ static int intel_hdmi_get_modes(struct drm_connector *connector) · 19 unmodified lines
25532541 return drm_edid_connector_add_modes(connector);
25542542 }
25552543
2556−static struct i2c_adapter *
2557−intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2558−{
2559− struct drm_i915_private *dev_priv = to_i915(connector->dev);
2560− struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2561−
2562− return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2563−}
2564−
2565−static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2566−{
2567− struct drm_i915_private *i915 = to_i915(connector->dev);
2568− struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2569− struct kobject *i2c_kobj = &adapter->dev.kobj;
2570− struct kobject *connector_kobj = &connector->kdev->kobj;
2571− int ret;
2572−
2573− ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2574− if (ret)
2575− drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2576−}
2577−
2578−static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2579−{
2580− struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2581− struct kobject *i2c_kobj = &adapter->dev.kobj;
2582− struct kobject *connector_kobj = &connector->kdev->kobj;
2583−
2584− sysfs_remove_link(connector_kobj, i2c_kobj->name);
2585−}
2586−
25872544 static int
25882545 intel_hdmi_connector_register(struct drm_connector *connector)
25892546 {
@@ -2593,8 +2550,6 @@ intel_hdmi_connector_register(struct drm_connector *connector) · 3 unmodified lines
25932550 if (ret)
25942551 return ret;
25952552
2596− intel_hdmi_create_i2c_symlink(connector);
2597−
25982553 return ret;
25992554 }
26002555
@@ -2604,7 +2559,6 @@ static void intel_hdmi_connector_unregister(struct drm_connector *connector) · 3 unmodified lines
26042559
26052560 cec_notifier_conn_unregister(n);
26062561
2607− intel_hdmi_remove_i2c_symlink(connector);
26082562 intel_connector_unregister(connector);
26092563 }
26102564
@@ -2918,13 +2872,17 @@ get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) · 307 unmodified lines
29182872 struct intel_encoder *other;
29192873
29202874 for_each_intel_encoder(&i915->drm, other) {
2875+ struct intel_connector *connector;
2876+
29212877 if (other == encoder)
29222878 continue;
29232879
29242880 if (!intel_encoder_is_dig_port(other))
29252881 continue;
29262882
2927− if (enc_to_dig_port(other)->hdmi.ddc_bus == ddc_pin)
2883+ connector = enc_to_dig_port(other)->hdmi.attached_connector;
2884+
2885+ if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin))
29282886 return other;
29292887 }
29302888
@@ -3016,9 +2974,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port, · 85 unmodified lines
30162974 struct intel_encoder *intel_encoder = &dig_port->base;
30172975 struct drm_device *dev = intel_encoder->base.dev;
30182976 struct drm_i915_private *dev_priv = to_i915(dev);
3019− struct i2c_adapter *ddc;
30202977 enum port port = intel_encoder->port;
30212978 struct cec_connector_info conn_info;
2979+ u8 ddc_pin;
30222980
30232981 drm_dbg_kms(&dev_priv->drm,
30242982 "Adding HDMI connector on [ENCODER:%d:%s]\n",
@@ -3033,16 +2991,15 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port, · 8 unmodified lines
30332991 intel_encoder->base.name))
30342992 return;
30352993
3036− intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
3037− if (!intel_hdmi->ddc_bus)
2994+ ddc_pin = intel_hdmi_ddc_pin(intel_encoder);
2995+ if (!ddc_pin)
30382996 return;
30392997
3040− ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
3041−
30422998 drm_connector_init_with_ddc(dev, connector,
30432999 &intel_hdmi_connector_funcs,
30443000 DRM_MODE_CONNECTOR_HDMIA,
3045− ddc);
3001+ intel_gmbus_get_adapter(dev_priv, ddc_pin));
3002+
30463003 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
30473004
30483005 if (DISPLAY_VER(dev_priv) < 12)
drivers/gpu/drm/i915/display/intel_hotplug.c+78−7
@@ -25,6 +25,7 @@ · 24 unmodified lines
2525
2626 #include "i915_drv.h"
2727 #include "i915_irq.h"
28+#include "intel_display_power.h"
2829 #include "intel_display_types.h"
2930 #include "intel_hotplug.h"
3031 #include "intel_hotplug_irq.h"
@@ -259,21 +260,22 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work) · 228 unmodified lines
259260 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
260261 }
261262
262−enum intel_hotplug_state
263−intel_encoder_hotplug(struct intel_encoder *encoder,
264− struct intel_connector *connector)
263+static enum intel_hotplug_state
264+intel_hotplug_detect_connector(struct intel_connector *connector)
265265 {
266266 struct drm_device *dev = connector->base.dev;
267267 enum drm_connector_status old_status;
268268 u64 old_epoch_counter;
269+ int status;
269270 bool ret = false;
270271
271272 drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex));
272273 old_status = connector->base.status;
273274 old_epoch_counter = connector->base.epoch_counter;
274275
275− connector->base.status =
276− drm_helper_probe_detect(&connector->base, NULL, false);
276+ status = drm_helper_probe_detect(&connector->base, NULL, false);
277+ if (!connector->base.force)
278+ connector->base.status = status;
277279
278280 if (old_epoch_counter != connector->base.epoch_counter)
279281 ret = true;
@@ -291,6 +293,13 @@ intel_encoder_hotplug(struct intel_encoder *encoder, · 11 unmodified lines
291293 return INTEL_HOTPLUG_UNCHANGED;
292294 }
293295
296+enum intel_hotplug_state
297+intel_encoder_hotplug(struct intel_encoder *encoder,
298+ struct intel_connector *connector)
299+{
300+ return intel_hotplug_detect_connector(connector);
301+}
302+
294303 static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
295304 {
296305 return intel_encoder_is_dig_port(encoder) &&
@@ -631,6 +640,49 @@ void intel_hpd_init(struct drm_i915_private *dev_priv) · 334 unmodified lines
631640 spin_unlock_irq(&dev_priv->irq_lock);
632641 }
633642
643+static void i915_hpd_poll_detect_connectors(struct drm_i915_private *i915)
644+{
645+ struct drm_connector_list_iter conn_iter;
646+ struct intel_connector *connector;
647+ struct intel_connector *first_changed_connector = NULL;
648+ int changed = 0;
649+
650+ mutex_lock(&i915->drm.mode_config.mutex);
651+
652+ if (!i915->drm.mode_config.poll_enabled)
653+ goto out;
654+
655+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
656+ for_each_intel_connector_iter(connector, &conn_iter) {
657+ if (!(connector->base.polled & DRM_CONNECTOR_POLL_HPD))
658+ continue;
659+
660+ if (intel_hotplug_detect_connector(connector) != INTEL_HOTPLUG_CHANGED)
661+ continue;
662+
663+ changed++;
664+
665+ if (changed == 1) {
666+ drm_connector_get(&connector->base);
667+ first_changed_connector = connector;
668+ }
669+ }
670+ drm_connector_list_iter_end(&conn_iter);
671+
672+out:
673+ mutex_unlock(&i915->drm.mode_config.mutex);
674+
675+ if (!changed)
676+ return;
677+
678+ if (changed == 1)
679+ drm_kms_helper_connector_hotplug_event(&first_changed_connector->base);
680+ else
681+ drm_kms_helper_hotplug_event(&i915->drm);
682+
683+ drm_connector_put(&first_changed_connector->base);
684+}
685+
634686 static void i915_hpd_poll_init_work(struct work_struct *work)
635687 {
636688 struct drm_i915_private *dev_priv =
@@ -638,11 +690,25 @@ static void i915_hpd_poll_init_work(struct work_struct *work) · 1 unmodified line
638690 display.hotplug.poll_init_work);
639691 struct drm_connector_list_iter conn_iter;
640692 struct intel_connector *connector;
693+ intel_wakeref_t wakeref;
641694 bool enabled;
642695
643696 mutex_lock(&dev_priv->drm.mode_config.mutex);
644697
645698 enabled = READ_ONCE(dev_priv->display.hotplug.poll_enabled);
699+ /*
700+ * Prevent taking a power reference from this sequence of
701+ * i915_hpd_poll_init_work() -> drm_helper_hpd_irq_event() ->
702+ * connector detect which would requeue i915_hpd_poll_init_work()
703+ * and so risk an endless loop of this same sequence.
704+ */
705+ if (!enabled) {
706+ wakeref = intel_display_power_get(dev_priv,
707+ POWER_DOMAIN_DISPLAY_CORE);
708+ drm_WARN_ON(&dev_priv->drm,
709+ READ_ONCE(dev_priv->display.hotplug.poll_enabled));
710+ cancel_work(&dev_priv->display.hotplug.poll_init_work);
711+ }
646712
647713 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
648714 for_each_intel_connector_iter(connector, &conn_iter) {
@@ -669,8 +735,13 @@ static void i915_hpd_poll_init_work(struct work_struct *work) · 20 unmodified lines
669735 * We might have missed any hotplugs that happened while we were
670736 * in the middle of disabling polling
671737 */
672− if (!enabled)
673− drm_helper_hpd_irq_event(&dev_priv->drm);
738+ if (!enabled) {
739+ i915_hpd_poll_detect_connectors(dev_priv);
740+
741+ intel_display_power_put(dev_priv,
742+ POWER_DOMAIN_DISPLAY_CORE,
743+ wakeref);
744+ }
674745 }
675746
676747 /**
drivers/gpu/drm/i915/display/intel_hotplug_irq.c+22−2
@@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) · 162 unmodified lines
163163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
164164 return;
165165
166− if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
166+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
167+ hpd->pch_hpd = hpd_mtp;
168+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
167169 hpd->pch_hpd = hpd_sde_dg1;
168170 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
169171 hpd->pch_hpd = hpd_mtp;
@@ -514,6 +516,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir) · 344 unmodified lines
514516 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
515517 u32 pin_mask = 0, long_mask = 0;
516518
519+ if (DISPLAY_VER(i915) >= 20)
520+ trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
521+
517522 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
518523 u32 val;
519524
@@ -1060,6 +1065,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private *i915) · 540 unmodified lines
10601065 mtp_tc_hpd_detection_setup(i915);
10611066 }
10621067
1068+static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
1069+{
1070+ u32 hotplug_irqs, enabled_irqs;
1071+
1072+ enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
1073+ hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
1074+
1075+ ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
1076+
1077+ mtp_ddi_hpd_detection_setup(i915);
1078+ mtp_tc_hpd_detection_setup(i915);
1079+}
1080+
10631081 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
10641082 {
10651083 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
@@ -1119,7 +1137,9 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915) · 53 unmodified lines
11191137
11201138 xelpdp_pica_hpd_detection_setup(i915);
11211139
1122− if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
1140+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
1141+ xe2lpd_sde_hpd_irq_setup(i915);
1142+ else if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
11231143 mtp_hpd_irq_setup(i915);
11241144 }
11251145
drivers/gpu/drm/i915/display/intel_link_bw.c+212−0
@@ -0,0 +1,212 @@
1+// SPDX-License-Identifier: MIT
2+/*
3+ * Copyright © 2023 Intel Corporation
4+ */
5+
6+#include "i915_drv.h"
7+
8+#include "intel_atomic.h"
9+#include "intel_display_types.h"
10+#include "intel_fdi.h"
11+#include "intel_link_bw.h"
12+
13+/**
14+ * intel_link_bw_init_limits - initialize BW limits
15+ * @i915: device instance
16+ * @limits: link BW limits
17+ *
18+ * Initialize @limits.
19+ */
20+void intel_link_bw_init_limits(struct drm_i915_private *i915, struct intel_link_bw_limits *limits)
21+{
22+ enum pipe pipe;
23+
24+ limits->bpp_limit_reached_pipes = 0;
25+ for_each_pipe(i915, pipe)
26+ limits->max_bpp_x16[pipe] = INT_MAX;
27+}
28+
29+/**
30+ * intel_link_bw_reduce_bpp - reduce maximum link bpp for a selected pipe
31+ * @state: atomic state
32+ * @limits: link BW limits
33+ * @pipe_mask: mask of pipes to select from
34+ * @reason: explanation of why bpp reduction is needed
35+ *
36+ * Select the pipe from @pipe_mask with the biggest link bpp value and set the
37+ * maximum of link bpp in @limits below this value. Modeset the selected pipe,
38+ * so that its state will get recomputed.
39+ *
40+ * This function can be called to resolve a link's BW overallocation by reducing
41+ * the link bpp of one pipe on the link and hence reducing the total link BW.
42+ *
43+ * Returns
44+ * - 0 in case of success
45+ * - %-ENOSPC if no pipe can further reduce its link bpp
46+ * - Other negative error, if modesetting the selected pipe failed
47+ */
48+int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
49+ struct intel_link_bw_limits *limits,
50+ u8 pipe_mask,
51+ const char *reason)
52+{
53+ struct drm_i915_private *i915 = to_i915(state->base.dev);
54+ enum pipe max_bpp_pipe = INVALID_PIPE;
55+ struct intel_crtc *crtc;
56+ int max_bpp = 0;
57+
58+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
59+ struct intel_crtc_state *crtc_state;
60+ int link_bpp;
61+
62+ if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe))
63+ continue;
64+
65+ crtc_state = intel_atomic_get_crtc_state(&state->base,
66+ crtc);
67+ if (IS_ERR(crtc_state))
68+ return PTR_ERR(crtc_state);
69+
70+ if (crtc_state->dsc.compression_enable)
71+ link_bpp = crtc_state->dsc.compressed_bpp;
72+ else
73+ /*
74+ * TODO: for YUV420 the actual link bpp is only half
75+ * of the pipe bpp value. The MST encoder's BW allocation
76+ * is based on the pipe bpp value, set the actual link bpp
77+ * limit here once the MST BW allocation is fixed.
78+ */
79+ link_bpp = crtc_state->pipe_bpp;
80+
81+ if (link_bpp > max_bpp) {
82+ max_bpp = link_bpp;
83+ max_bpp_pipe = crtc->pipe;
84+ }
85+ }
86+
87+ if (max_bpp_pipe == INVALID_PIPE)
88+ return -ENOSPC;
89+
90+ limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1;
91+
92+ return intel_modeset_pipes_in_mask_early(state, reason,
93+ BIT(max_bpp_pipe));
94+}
95+
96+/**
97+ * intel_link_bw_set_bpp_limit_for_pipe - set link bpp limit for a pipe to its minimum
98+ * @state: atomic state
99+ * @old_limits: link BW limits
100+ * @new_limits: link BW limits
101+ * @pipe: pipe
102+ *
103+ * Set the link bpp limit for @pipe in @new_limits to its value in
104+ * @old_limits and mark this limit as the minimum. This function must be
105+ * called after a pipe's compute config function failed, @old_limits
106+ * containing the bpp limit with which compute config previously passed.
107+ *
108+ * The function will fail if setting a minimum is not possible, either
109+ * because the old and new limits match (and so would lead to a pipe compute
110+ * config failure) or the limit is already at the minimum.
111+ *
112+ * Returns %true in case of success.
113+ */
114+bool
115+intel_link_bw_set_bpp_limit_for_pipe(struct intel_atomic_state *state,
116+ const struct intel_link_bw_limits *old_limits,
117+ struct intel_link_bw_limits *new_limits,
118+ enum pipe pipe)
119+{
120+ struct drm_i915_private *i915 = to_i915(state->base.dev);
121+
122+ if (pipe == INVALID_PIPE)
123+ return false;
124+
125+ if (new_limits->max_bpp_x16[pipe] ==
126+ old_limits->max_bpp_x16[pipe])
127+ return false;
128+
129+ if (drm_WARN_ON(&i915->drm,
130+ new_limits->bpp_limit_reached_pipes & BIT(pipe)))
131+ return false;
132+
133+ new_limits->max_bpp_x16[pipe] =
134+ old_limits->max_bpp_x16[pipe];
135+ new_limits->bpp_limit_reached_pipes |= BIT(pipe);
136+
137+ return true;
138+}
139+
140+static int check_all_link_config(struct intel_atomic_state *state,
141+ struct intel_link_bw_limits *limits)
142+{
143+ /* TODO: Check additional shared display link configurations like MST */
144+ int ret;
145+
146+ ret = intel_fdi_atomic_check_link(state, limits);
147+ if (ret)
148+ return ret;
149+
150+ return 0;
151+}
152+
153+static bool
154+assert_link_limit_change_valid(struct drm_i915_private *i915,
155+ const struct intel_link_bw_limits *old_limits,
156+ const struct intel_link_bw_limits *new_limits)
157+{
158+ bool bpps_changed = false;
159+ enum pipe pipe;
160+
161+ for_each_pipe(i915, pipe) {
162+ /* The bpp limit can only decrease. */
163+ if (drm_WARN_ON(&i915->drm,
164+ new_limits->max_bpp_x16[pipe] >
165+ old_limits->max_bpp_x16[pipe]))
166+ return false;
167+
168+ if (new_limits->max_bpp_x16[pipe] <
169+ old_limits->max_bpp_x16[pipe])
170+ bpps_changed = true;
171+ }
172+
173+ /* At least one limit must change. */
174+ if (drm_WARN_ON(&i915->drm,
175+ !bpps_changed))
176+ return false;
177+
178+ return true;
179+}
180+
181+/**
182+ * intel_link_bw_atomic_check - check display link states and set a fallback config if needed
183+ * @state: atomic state
184+ * @new_limits: link BW limits
185+ *
186+ * Check the configuration of all shared display links in @state and set new BW
187+ * limits in @new_limits if there is a BW limitation.
188+ *
189+ * Returns:
190+ * - 0 if the confugration is valid
191+ * - %-EAGAIN, if the configuration is invalid and @new_limits got updated
192+ * with fallback values with which the configuration of all CRTCs
193+ * in @state must be recomputed
194+ * - Other negative error, if the configuration is invalid without a
195+ * fallback possibility, or the check failed for another reason
196+ */
197+int intel_link_bw_atomic_check(struct intel_atomic_state *state,
198+ struct intel_link_bw_limits *new_limits)
199+{
200+ struct drm_i915_private *i915 = to_i915(state->base.dev);
201+ struct intel_link_bw_limits old_limits = *new_limits;
202+ int ret;
203+
204+ ret = check_all_link_config(state, new_limits);
205+ if (ret != -EAGAIN)
206+ return ret;
207+
208+ if (!assert_link_limit_change_valid(i915, &old_limits, new_limits))
209+ return -EINVAL;
210+
211+ return -EAGAIN;
212+}
drivers/gpu/drm/i915/display/intel_link_bw.h+37−0
@@ -0,0 +1,37 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2023 Intel Corporation
4+ */
5+
6+#ifndef __INTEL_LINK_BW_H__
7+#define __INTEL_LINK_BW_H__
8+
9+#include <linux/types.h>
10+
11+#include "intel_display_limits.h"
12+
13+struct drm_i915_private;
14+
15+struct intel_atomic_state;
16+struct intel_crtc_state;
17+
18+struct intel_link_bw_limits {
19+ u8 bpp_limit_reached_pipes;
20+ /* in 1/16 bpp units */
21+ int max_bpp_x16[I915_MAX_PIPES];
22+};
23+
24+void intel_link_bw_init_limits(struct drm_i915_private *i915,
25+ struct intel_link_bw_limits *limits);
26+int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
27+ struct intel_link_bw_limits *limits,
28+ u8 pipe_mask,
29+ const char *reason);
30+bool intel_link_bw_set_bpp_limit_for_pipe(struct intel_atomic_state *state,
31+ const struct intel_link_bw_limits *old_limits,
32+ struct intel_link_bw_limits *new_limits,
33+ enum pipe pipe);
34+int intel_link_bw_atomic_check(struct intel_atomic_state *state,
35+ struct intel_link_bw_limits *new_limits);
36+
37+#endif
drivers/gpu/drm/i915/display/intel_lspcon.c+7−7
@@ -144,9 +144,9 @@ static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) · 143 unmodified lines
144144 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
145145 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
146146 enum drm_lspcon_mode current_mode;
147− struct i2c_adapter *adapter = &intel_dp->aux.ddc;
147+ struct i2c_adapter *ddc = &intel_dp->aux.ddc;
148148
149− if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, &current_mode)) {
149+ if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode)) {
150150 drm_dbg_kms(&i915->drm, "Error reading LSPCON mode\n");
151151 return DRM_LSPCON_MODE_INVALID;
152152 }
@@ -185,9 +185,9 @@ static int lspcon_change_mode(struct intel_lspcon *lspcon, · 32 unmodified lines
185185 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
186186 int err;
187187 enum drm_lspcon_mode current_mode;
188− struct i2c_adapter *adapter = &intel_dp->aux.ddc;
188+ struct i2c_adapter *ddc = &intel_dp->aux.ddc;
189189
190− err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, &current_mode);
190+ err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode);
191191 if (err) {
192192 drm_err(&i915->drm, "Error reading LSPCON mode\n");
193193 return err;
@@ -198,7 +198,7 @@ static int lspcon_change_mode(struct intel_lspcon *lspcon, · 4 unmodified lines
198198 return 0;
199199 }
200200
201− err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, adapter, mode);
201+ err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode);
202202 if (err < 0) {
203203 drm_err(&i915->drm, "LSPCON mode change failed\n");
204204 return err;
@@ -233,7 +233,7 @@ static bool lspcon_probe(struct intel_lspcon *lspcon) · 28 unmodified lines
233233 enum drm_dp_dual_mode_type adaptor_type;
234234 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
235235 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
236− struct i2c_adapter *adapter = &intel_dp->aux.ddc;
236+ struct i2c_adapter *ddc = &intel_dp->aux.ddc;
237237 enum drm_lspcon_mode expected_mode;
238238
239239 expected_mode = lspcon_wake_native_aux_ch(lspcon) ?
@@ -244,7 +244,7 @@ static bool lspcon_probe(struct intel_lspcon *lspcon) · 4 unmodified lines
244244 if (retry)
245245 usleep_range(500, 1000);
246246
247− adaptor_type = drm_dp_dual_mode_detect(intel_dp->aux.drm_dev, adapter);
247+ adaptor_type = drm_dp_dual_mode_detect(intel_dp->aux.drm_dev, ddc);
248248 if (adaptor_type == DRM_DP_DUAL_MODE_LSPCON)
249249 break;
250250 }
drivers/gpu/drm/i915/display/intel_lvds.c+18−15
@@ -425,11 +425,18 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder, · 424 unmodified lines
425425 return -EINVAL;
426426 }
427427
428+ if (HAS_PCH_SPLIT(i915)) {
429+ crtc_state->has_pch_encoder = true;
430+ if (!intel_fdi_compute_pipe_bpp(crtc_state))
431+ return -EINVAL;
432+ }
433+
428434 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
429435 lvds_bpp = 8*3;
430436 else
431437 lvds_bpp = 6*3;
432438
439+ /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
433440 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
434441 drm_dbg_kms(&i915->drm,
435442 "forcing display bpp (was %d) to LVDS (%d)\n",
@@ -453,9 +460,6 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder, · 17 unmodified lines
453460 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
454461 return -EINVAL;
455462
456− if (HAS_PCH_SPLIT(i915))
457− crtc_state->has_pch_encoder = true;
458−
459463 ret = intel_panel_fitting(crtc_state, conn_state);
460464 if (ret)
461465 return ret;
@@ -837,7 +841,7 @@ void intel_lvds_init(struct drm_i915_private *i915) · 375 unmodified lines
837841 struct intel_encoder *encoder;
838842 i915_reg_t lvds_reg;
839843 u32 lvds;
840− u8 pin;
844+ u8 ddc_pin;
841845
842846 /* Skip init on machines we know falsely report LVDS */
843847 if (dmi_check_system(intel_no_lvds)) {
@@ -864,8 +868,8 @@ void intel_lvds_init(struct drm_i915_private *i915) · 20 unmodified lines
864868 return;
865869 }
866870
867− pin = GMBUS_PIN_PANEL;
868− if (!intel_bios_is_lvds_present(i915, &pin)) {
871+ ddc_pin = GMBUS_PIN_PANEL;
872+ if (!intel_bios_is_lvds_present(i915, &ddc_pin)) {
869873 if ((lvds & LVDS_PORT_EN) == 0) {
870874 drm_dbg_kms(&i915->drm,
871875 "LVDS is not present in VBT\n");
@@ -888,8 +892,10 @@ void intel_lvds_init(struct drm_i915_private *i915) · 16 unmodified lines
888892 lvds_encoder->attached_connector = connector;
889893 encoder = &lvds_encoder->base;
890894
891− drm_connector_init(&i915->drm, &connector->base, &intel_lvds_connector_funcs,
892− DRM_MODE_CONNECTOR_LVDS);
895+ drm_connector_init_with_ddc(&i915->drm, &connector->base,
896+ &intel_lvds_connector_funcs,
897+ DRM_MODE_CONNECTOR_LVDS,
898+ intel_gmbus_get_adapter(i915, ddc_pin));
893899
894900 drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
895901 DRM_MODE_ENCODER_LVDS, "LVDS");
@@ -943,13 +949,10 @@ void intel_lvds_init(struct drm_i915_private *i915) · 47 unmodified lines
943949 * preferred mode is the right one.
944950 */
945951 mutex_lock(&i915->drm.mode_config.mutex);
946− if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) {
947− drm_edid = drm_edid_read_switcheroo(&connector->base,
948− intel_gmbus_get_adapter(i915, pin));
949− } else {
950− drm_edid = drm_edid_read_ddc(&connector->base,
951− intel_gmbus_get_adapter(i915, pin));
952− }
952+ if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
953+ drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc);
954+ else
955+ drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
953956 if (drm_edid) {
954957 if (drm_edid_connector_update(&connector->base, drm_edid) ||
955958 !drm_edid_connector_add_modes(&connector->base)) {
drivers/gpu/drm/i915/display/intel_overlay.c+2−0
@@ -29,12 +29,14 @@ · 28 unmodified lines
2929 #include <drm/drm_fourcc.h>
3030
3131 #include "gem/i915_gem_internal.h"
32+#include "gem/i915_gem_object_frontbuffer.h"
3233 #include "gem/i915_gem_pm.h"
3334 #include "gt/intel_gpu_commands.h"
3435 #include "gt/intel_ring.h"
3536
3637 #include "i915_drv.h"
3738 #include "i915_reg.h"
39+#include "intel_color_regs.h"
3840 #include "intel_de.h"
3941 #include "intel_display_types.h"
4042 #include "intel_frontbuffer.h"
drivers/gpu/drm/i915/display/intel_panel.c+4−13
@@ -59,15 +59,6 @@ intel_panel_preferred_fixed_mode(struct intel_connector *connector) · 58 unmodified lines
5959 struct drm_display_mode, head);
6060 }
6161
62−static bool is_in_vrr_range(struct intel_connector *connector, int vrefresh)
63−{
64− const struct drm_display_info *info = &connector->base.display_info;
65−
66− return intel_vrr_is_capable(connector) &&
67− vrefresh >= info->monitor_range.min_vfreq &&
68− vrefresh <= info->monitor_range.max_vfreq;
69−}
70−
7162 static bool is_best_fixed_mode(struct intel_connector *connector,
7263 int vrefresh, int fixed_mode_vrefresh,
7364 const struct drm_display_mode *best_mode)
@@ -81,8 +72,8 @@ static bool is_best_fixed_mode(struct intel_connector *connector, · 7 unmodified lines
8172 * vrefresh, which we can then reduce to match the requested
8273 * vrefresh by extending the vblank length.
8374 */
84− if (is_in_vrr_range(connector, vrefresh) &&
85− is_in_vrr_range(connector, fixed_mode_vrefresh) &&
75+ if (intel_vrr_is_in_range(connector, vrefresh) &&
76+ intel_vrr_is_in_range(connector, fixed_mode_vrefresh) &&
8677 fixed_mode_vrefresh < vrefresh)
8778 return false;
8879
@@ -224,8 +215,8 @@ int intel_panel_compute_config(struct intel_connector *connector, · 135 unmodified lines
224215 * Assume that we shouldn't muck about with the
225216 * timings if they don't land in the VRR range.
226217 */
227− is_vrr = is_in_vrr_range(connector, vrefresh) &&
228− is_in_vrr_range(connector, fixed_mode_vrefresh);
218+ is_vrr = intel_vrr_is_in_range(connector, vrefresh) &&
219+ intel_vrr_is_in_range(connector, fixed_mode_vrefresh);
229220
230221 if (!is_vrr) {
231222 /*
drivers/gpu/drm/i915/display/intel_plane_initial.c+1−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include "intel_display.h"
1010 #include "intel_display_types.h"
1111 #include "intel_fb.h"
12+#include "intel_frontbuffer.h"
1213 #include "intel_plane_initial.h"
1314
1415 static bool
drivers/gpu/drm/i915/display/intel_pmdemand.c+1−1
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915) · 91 unmodified lines
9292 &pmdemand_state->base,
9393 &intel_pmdemand_funcs);
9494
95− if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
95+ if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
9696 /* Wa_14016740474 */
9797 intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
9898
drivers/gpu/drm/i915/display/intel_psr.c+37−15
@@ -23,6 +23,7 @@ · 22 unmodified lines
2323
2424 #include <drm/drm_atomic_helper.h>
2525 #include <drm/drm_damage_helper.h>
26+#include <drm/drm_debugfs.h>
2627
2728 #include "i915_drv.h"
2829 #include "i915_reg.h"
@@ -32,6 +33,7 @@ · 3 unmodified lines
3233 #include "intel_display_types.h"
3334 #include "intel_dp.h"
3435 #include "intel_dp_aux.h"
36+#include "intel_frontbuffer.h"
3537 #include "intel_hdmi.h"
3638 #include "intel_psr.h"
3739 #include "intel_psr_regs.h"
@@ -1360,8 +1362,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp, · 1322 unmodified lines
13601362 bool set_wa_bit = false;
13611363
13621364 /* Wa_14015648006 */
1363− if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
1364− IS_DISPLAY_VER(dev_priv, 11, 13))
1365+ if (IS_DISPLAY_VER(dev_priv, 11, 14))
13651366 set_wa_bit |= crtc_state->wm_level_disabled;
13661367
13671368 /* Wa_16013835468 */
@@ -1447,7 +1448,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, · 79 unmodified lines
14471448 * All supported adlp panels have 1-based X granularity, this may
14481449 * cause issues if non-supported panels are used.
14491450 */
1450− if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1451+ if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
14511452 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
14521453 ADLP_1_BASED_X_GRANULARITY);
14531454 else if (IS_ALDERLAKE_P(dev_priv))
@@ -1455,7 +1456,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, · 1 unmodified line
14551456 ADLP_1_BASED_X_GRANULARITY);
14561457
14571458 /* Wa_16012604467:adlp,mtl[a0,b0] */
1458− if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1459+ if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
14591460 intel_de_rmw(dev_priv,
14601461 MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
14611462 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1613,7 +1614,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) · 151 unmodified lines
16131614
16141615 if (intel_dp->psr.psr2_enabled) {
16151616 /* Wa_16012604467:adlp,mtl[a0,b0] */
1616− if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1617+ if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
16171618 intel_de_rmw(dev_priv,
16181619 MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
16191620 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2087,7 +2088,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, · 467 unmodified lines
20872088 goto skip_sel_fetch_set_loop;
20882089
20892090 /* Wa_14014971492 */
2090− if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
2091+ if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
20912092 IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
20922093 crtc_state->splitter.enable)
20932094 pipe_clip.y1 = 0;
@@ -2230,6 +2231,12 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, · 136 unmodified lines
22302231 if (crtc_state->crc_enabled && psr->enabled)
22312232 psr_force_hw_tracking_exit(intel_dp);
22322233
2234+ /*
2235+ * Clear possible busy bits in case we have
2236+ * invalidate -> flip -> flush sequence.
2237+ */
2238+ intel_dp->psr.busy_frontbuffer_bits = 0;
2239+
22332240 mutex_unlock(&psr->lock);
22342241 }
22352242 }
@@ -3153,7 +3160,7 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data) · 917 unmodified lines
31533160 };
31543161 const char *str;
31553162 int ret;
3156− u8 val;
3163+ u8 status, error_status;
31573164
31583165 if (!CAN_PSR(intel_dp)) {
31593166 seq_puts(m, "PSR Unsupported\n");
@@ -3163,19 +3170,34 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data) · 3 unmodified lines
31633170 if (connector->base.status != connector_status_connected)
31643171 return -ENODEV;
31653172
3166− ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
3167− if (ret != 1)
3168− return ret < 0 ? ret : -EIO;
3173+ ret = psr_get_status_and_error_status(intel_dp, &status, &error_status);
3174+ if (ret)
3175+ return ret;
31693176
3170− val &= DP_PSR_SINK_STATE_MASK;
3171− if (val < ARRAY_SIZE(sink_status))
3172− str = sink_status[val];
3177+ status &= DP_PSR_SINK_STATE_MASK;
3178+ if (status < ARRAY_SIZE(sink_status))
3179+ str = sink_status[status];
31733180 else
31743181 str = "unknown";
31753182
3176− seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
3183+ seq_printf(m, "Sink PSR status: 0x%x [%s]\n", status, str);
31773184
3178− return 0;
3185+ seq_printf(m, "Sink PSR error status: 0x%x", error_status);
3186+
3187+ if (error_status & (DP_PSR_RFB_STORAGE_ERROR |
3188+ DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
3189+ DP_PSR_LINK_CRC_ERROR))
3190+ seq_puts(m, ":\n");
3191+ else
3192+ seq_puts(m, "\n");
3193+ if (error_status & DP_PSR_RFB_STORAGE_ERROR)
3194+ seq_puts(m, "\tPSR RFB storage error\n");
3195+ if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
3196+ seq_puts(m, "\tPSR VSC SDP uncorrectable error\n");
3197+ if (error_status & DP_PSR_LINK_CRC_ERROR)
3198+ seq_puts(m, "\tPSR Link CRC error\n");
3199+
3200+ return ret;
31793201 }
31803202 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
31813203
drivers/gpu/drm/i915/display/intel_sdvo.c+196−185
@@ -44,6 +44,7 @@ · 43 unmodified lines
4444 #include "intel_crtc.h"
4545 #include "intel_de.h"
4646 #include "intel_display_types.h"
47+#include "intel_fdi.h"
4748 #include "intel_fifo_underrun.h"
4849 #include "intel_gmbus.h"
4950 #include "intel_hdmi.h"
@@ -57,15 +58,16 @@ · 7 unmodified lines
5758 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
5859 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
5960
60−#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
61− SDVO_TV_MASK)
61+#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK | SDVO_TV_MASK)
6262
63−#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
64−#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
65−#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
66−#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
67−#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
63+#define IS_TV(c) ((c)->output_flag & SDVO_TV_MASK)
64+#define IS_TMDS(c) ((c)->output_flag & SDVO_TMDS_MASK)
65+#define IS_LVDS(c) ((c)->output_flag & SDVO_LVDS_MASK)
66+#define IS_TV_OR_LVDS(c) ((c)->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
67+#define IS_DIGITAL(c) ((c)->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
6868
69+#define HAS_DDC(c) ((c)->output_flag & (SDVO_RGB_MASK | SDVO_TMDS_MASK | \
70+ SDVO_LVDS_MASK))
6971
7072 static const char * const tv_format_names[] = {
7173 "NTSC_M" , "NTSC_J" , "NTSC_443",
@@ -79,20 +81,25 @@ static const char * const tv_format_names[] = { · 7 unmodified lines
7981
8082 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
8183
84+struct intel_sdvo;
85+
86+struct intel_sdvo_ddc {
87+ struct i2c_adapter ddc;
88+ struct intel_sdvo *sdvo;
89+ u8 ddc_bus;
90+};
91+
8292 struct intel_sdvo {
8393 struct intel_encoder base;
8494
8595 struct i2c_adapter *i2c;
8696 u8 slave_addr;
8797
88− struct i2c_adapter ddc;
98+ struct intel_sdvo_ddc ddc[3];
8999
90100 /* Register for the SDVO device: SDVOB or SDVOC */
91101 i915_reg_t sdvo_reg;
92102
93− /* Active outputs controlled by this SDVO output */
94− u16 controlled_output;
95−
96103 /*
97104 * Capabilities of the SDVO device returned by
98105 * intel_sdvo_get_capabilities()
@@ -104,22 +111,11 @@ struct intel_sdvo { · 5 unmodified lines
104111 /* Pixel clock limitations reported by the SDVO device, in kHz */
105112 int pixel_clock_min, pixel_clock_max;
106113
107− /*
108− * For multiple function SDVO device,
109− * this is for current attached outputs.
110− */
111− u16 attached_output;
112−
113114 /*
114115 * Hotplug activation bits for this device
115116 */
116117 u16 hotplug_active;
117118
118− enum port port;
119−
120− /* DDC bus used by this SDVO encoder */
121− u8 ddc_bus;
122−
123119 /*
124120 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
125121 */
@@ -233,7 +229,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) · 107 unmodified lines
233229 return;
234230 }
235231
236− if (intel_sdvo->port == PORT_B)
232+ if (intel_sdvo->base.port == PORT_B)
237233 cval = intel_de_read(dev_priv, GEN3_SDVOC);
238234 else
239235 bval = intel_de_read(dev_priv, GEN3_SDVOB);
@@ -410,7 +406,7 @@ static const char *sdvo_cmd_name(u8 cmd) · 170 unmodified lines
410406 return NULL;
411407 }
412408
413−#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
409+#define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")
414410
415411 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
416412 const void *args, int args_len)
@@ -1224,12 +1220,13 @@ static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, · 807 unmodified lines
12241220
12251221 static bool
12261222 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1223+ struct intel_sdvo_connector *intel_sdvo_connector,
12271224 const struct drm_display_mode *mode)
12281225 {
12291226 struct intel_sdvo_dtd output_dtd;
12301227
12311228 if (!intel_sdvo_set_target_output(intel_sdvo,
1232− intel_sdvo->attached_output))
1229+ intel_sdvo_connector->output_flag))
12331230 return false;
12341231
12351232 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
@@ -1270,10 +1267,10 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, · 34 unmodified lines
12701267 return true;
12711268 }
12721269
1273−static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1270+static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
12741271 {
12751272 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
1276− unsigned dotclock = pipe_config->port_clock;
1273+ unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
12771274 struct dpll *clock = &pipe_config->dpll;
12781275
12791276 /*
@@ -1293,11 +1290,14 @@ static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) · 13 unmodified lines
12931290 clock->m1 = 12;
12941291 clock->m2 = 8;
12951292 } else {
1296− drm_WARN(&dev_priv->drm, 1,
1297− "SDVO TV clock out of range: %i\n", dotclock);
1293+ drm_dbg_kms(&dev_priv->drm,
1294+ "SDVO TV clock out of range: %i\n", dotclock);
1295+ return -EINVAL;
12981296 }
12991297
13001298 pipe_config->clock_set = true;
1299+
1300+ return 0;
13011301 }
13021302
13031303 static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector,
@@ -1352,14 +1352,18 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, · 48 unmodified lines
13521352 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
13531353 struct drm_display_mode *mode = &pipe_config->hw.mode;
13541354
1355+ if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
1356+ pipe_config->has_pch_encoder = true;
1357+ if (!intel_fdi_compute_pipe_bpp(pipe_config))
1358+ return -EINVAL;
1359+ }
1360+
13551361 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1362+ /* FIXME: Don't increase pipe_bpp */
13561363 pipe_config->pipe_bpp = 8*3;
13571364 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
13581365 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
13591366
1360− if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
1361− pipe_config->has_pch_encoder = true;
1362−
13631367 /*
13641368 * We need to construct preferred input timings based on our
13651369 * output timings. To do that, we have to set the output
@@ -1367,7 +1371,9 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, · 1 unmodified line
13671371 * the sequence to do it. Oh well.
13681372 */
13691373 if (IS_TV(intel_sdvo_connector)) {
1370− if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1374+ if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1375+ intel_sdvo_connector,
1376+ mode))
13711377 return -EINVAL;
13721378
13731379 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
@@ -1385,7 +1391,9 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, · 11 unmodified lines
13851391 if (ret)
13861392 return ret;
13871393
1388− if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, fixed_mode))
1394+ if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1395+ intel_sdvo_connector,
1396+ fixed_mode))
13891397 return -EINVAL;
13901398
13911399 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
@@ -1415,8 +1423,13 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, · 23 unmodified lines
14151423 conn_state);
14161424
14171425 /* Clock computation needs to happen after pixel multiplier. */
1418− if (IS_TV(intel_sdvo_connector))
1419− i9xx_adjust_sdvo_tv_clock(pipe_config);
1426+ if (IS_TV(intel_sdvo_connector)) {
1427+ int ret;
1428+
1429+ ret = i9xx_adjust_sdvo_tv_clock(pipe_config);
1430+ if (ret)
1431+ return ret;
1432+ }
14201433
14211434 if (conn_state->picture_aspect_ratio)
14221435 adjusted_mode->picture_aspect_ratio =
@@ -1521,7 +1534,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, · 98 unmodified lines
15211534 * channel on the motherboard. In a two-input device, the first input
15221535 * will be SDVOB and the second SDVOC.
15231536 */
1524− in_out.in0 = intel_sdvo->attached_output;
1537+ in_out.in0 = intel_sdvo_connector->output_flag;
15251538 in_out.in1 = 0;
15261539
15271540 intel_sdvo_set_value(intel_sdvo,
@@ -1530,7 +1543,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, · 2 unmodified lines
15301543
15311544 /* Set the output timings to the screen */
15321545 if (!intel_sdvo_set_target_output(intel_sdvo,
1533− intel_sdvo->attached_output))
1546+ intel_sdvo_connector->output_flag))
15341547 return;
15351548
15361549 /* lvds has a special fixed output timing. */
@@ -1598,7 +1611,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, · 61 unmodified lines
15981611 sdvox |= SDVO_BORDER_ENABLE;
15991612 } else {
16001613 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1601− if (intel_sdvo->port == PORT_B)
1614+ if (intel_sdvo->base.port == PORT_B)
16021615 sdvox &= SDVOB_PRESERVE_MASK;
16031616 else
16041617 sdvox &= SDVOC_PRESERVE_MASK;
@@ -1867,6 +1880,8 @@ static void intel_enable_sdvo(struct intel_atomic_state *state, · 262 unmodified lines
18671880 struct drm_device *dev = encoder->base.dev;
18681881 struct drm_i915_private *dev_priv = to_i915(dev);
18691882 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1883+ struct intel_sdvo_connector *intel_sdvo_connector =
1884+ to_intel_sdvo_connector(conn_state->connector);
18701885 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
18711886 u32 temp;
18721887 bool input1, input2;
@@ -1896,7 +1911,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state, · 23 unmodified lines
18961911 if (0)
18971912 intel_sdvo_set_encoder_power_state(intel_sdvo,
18981913 DRM_MODE_DPMS_ON);
1899− intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1914+ intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag);
19001915
19011916 if (pipe_config->has_audio)
19021917 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
@@ -1956,7 +1971,7 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in · 53 unmodified lines
19561971 " device_rev_id: %d\n"
19571972 " sdvo_version_major: %d\n"
19581973 " sdvo_version_minor: %d\n"
1959− " sdvo_inputs_mask: %d\n"
1974+ " sdvo_num_inputs: %d\n"
19601975 " smooth_scaling: %d\n"
19611976 " sharp_scaling: %d\n"
19621977 " up_scaling: %d\n"
@@ -1968,7 +1983,7 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in · 5 unmodified lines
19681983 caps->device_rev_id,
19691984 caps->sdvo_version_major,
19701985 caps->sdvo_version_minor,
1971− caps->sdvo_inputs_mask,
1986+ caps->sdvo_num_inputs,
19721987 caps->smooth_scaling,
19731988 caps->sharp_scaling,
19741989 caps->up_scaling,
@@ -2029,18 +2044,15 @@ intel_sdvo_hotplug(struct intel_encoder *encoder, · 54 unmodified lines
20292044 return intel_encoder_hotplug(encoder, connector);
20302045 }
20312046
2032−static bool
2033−intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
2034−{
2035− /* Is there more than one type of output? */
2036− return hweight16(intel_sdvo->caps.output_flags) > 1;
2037−}
2038−
20392047 static const struct drm_edid *
20402048 intel_sdvo_get_edid(struct drm_connector *connector)
20412049 {
2042− struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2043− return drm_edid_read_ddc(connector, &sdvo->ddc);
2050+ struct i2c_adapter *ddc = connector->ddc;
2051+
2052+ if (!ddc)
2053+ return NULL;
2054+
2055+ return drm_edid_read_ddc(connector, ddc);
20442056 }
20452057
20462058 /* Mac mini hack -- use the same DDC as the analog connector */
@@ -2048,43 +2060,23 @@ static const struct drm_edid * · 1 unmodified line
20482060 intel_sdvo_get_analog_edid(struct drm_connector *connector)
20492061 {
20502062 struct drm_i915_private *i915 = to_i915(connector->dev);
2051− struct i2c_adapter *i2c;
2063+ struct i2c_adapter *ddc;
20522064
2053− i2c = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
2065+ ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
2066+ if (!ddc)
2067+ return NULL;
20542068
2055− return drm_edid_read_ddc(connector, i2c);
2069+ return drm_edid_read_ddc(connector, ddc);
20562070 }
20572071
20582072 static enum drm_connector_status
20592073 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
20602074 {
2061− struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
20622075 enum drm_connector_status status;
20632076 const struct drm_edid *drm_edid;
20642077
20652078 drm_edid = intel_sdvo_get_edid(connector);
20662079
2067− if (!drm_edid && intel_sdvo_multifunc_encoder(intel_sdvo)) {
2068− u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
2069−
2070− /*
2071− * Don't use the 1 as the argument of DDC bus switch to get
2072− * the EDID. It is used for SDVO SPD ROM.
2073− */
2074− for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
2075− intel_sdvo->ddc_bus = ddc;
2076− drm_edid = intel_sdvo_get_edid(connector);
2077− if (drm_edid)
2078− break;
2079− }
2080− /*
2081− * If we found the EDID on the other bus,
2082− * assume that is the correct DDC bus.
2083− */
2084− if (!drm_edid)
2085− intel_sdvo->ddc_bus = saved_ddc;
2086− }
2087−
20882080 /*
20892081 * When there is no edid and no monitor is connected with VGA
20902082 * port, try to use the CRT ddc to read the EDID for DVI-connector.
@@ -2094,10 +2086,8 @@ intel_sdvo_tmds_sink_detect(struct drm_connector *connector) · 3 unmodified lines
20942086
20952087 status = connector_status_unknown;
20962088 if (drm_edid) {
2097− const struct edid *edid = drm_edid_raw(drm_edid);
2098−
20992089 /* DDC bus is shared, match EDID to connector type */
2100− if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
2090+ if (drm_edid_is_digital(drm_edid))
21012091 status = connector_status_connected;
21022092 else
21032093 status = connector_status_disconnected;
@@ -2111,8 +2101,7 @@ static bool · 7 unmodified lines
21112101 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
21122102 const struct drm_edid *drm_edid)
21132103 {
2114− const struct edid *edid = drm_edid_raw(drm_edid);
2115− bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
2104+ bool monitor_is_digital = drm_edid_is_digital(drm_edid);
21162105 bool connector_is_digital = !!IS_DIGITAL(sdvo);
21172106
21182107 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
@@ -2135,6 +2124,10 @@ intel_sdvo_detect(struct drm_connector *connector, bool force) · 16 unmodified lines
21352124 if (!INTEL_DISPLAY_ENABLED(i915))
21362125 return connector_status_disconnected;
21372126
2127+ if (!intel_sdvo_set_target_output(intel_sdvo,
2128+ intel_sdvo_connector->output_flag))
2129+ return connector_status_unknown;
2130+
21382131 if (!intel_sdvo_get_value(intel_sdvo,
21392132 SDVO_CMD_GET_ATTACHED_DISPLAYS,
21402133 &response, 2))
@@ -2147,8 +2140,6 @@ intel_sdvo_detect(struct drm_connector *connector, bool force) · 6 unmodified lines
21472140 if (response == 0)
21482141 return connector_status_disconnected;
21492142
2150− intel_sdvo->attached_output = response;
2151−
21522143 if ((intel_sdvo_connector->output_flag & response) == 0)
21532144 ret = connector_status_disconnected;
21542145 else if (IS_TMDS(intel_sdvo_connector))
@@ -2276,6 +2267,8 @@ static const struct drm_display_mode sdvo_tv_modes[] = { · 121 unmodified lines
22762267 static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
22772268 {
22782269 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2270+ struct intel_sdvo_connector *intel_sdvo_connector =
2271+ to_intel_sdvo_connector(connector);
22792272 const struct drm_connector_state *conn_state = connector->state;
22802273 struct intel_sdvo_sdtv_resolution_request tv_res;
22812274 u32 reply = 0, format_map = 0;
@@ -2293,7 +2286,7 @@ static int intel_sdvo_get_tv_modes(struct drm_connector *connector) · 11 unmodified lines
22932286 memcpy(&tv_res, &format_map,
22942287 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
22952288
2296− if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2289+ if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo_connector->output_flag))
22972290 return 0;
22982291
22992292 BUILD_BUG_ON(sizeof(tv_res) != 3);
@@ -2458,31 +2451,6 @@ intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, · 158 unmodified lines
24582451 return 0;
24592452 }
24602453
2461−static int
2462−intel_sdvo_connector_register(struct drm_connector *connector)
2463−{
2464− struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2465− int ret;
2466−
2467− ret = intel_connector_register(connector);
2468− if (ret)
2469− return ret;
2470−
2471− return sysfs_create_link(&connector->kdev->kobj,
2472− &sdvo->ddc.dev.kobj,
2473− sdvo->ddc.dev.kobj.name);
2474−}
2475−
2476−static void
2477−intel_sdvo_connector_unregister(struct drm_connector *connector)
2478−{
2479− struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2480−
2481− sysfs_remove_link(&connector->kdev->kobj,
2482− sdvo->ddc.dev.kobj.name);
2483− intel_connector_unregister(connector);
2484−}
2485−
24862454 static struct drm_connector_state *
24872455 intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
24882456 {
@@ -2501,8 +2469,8 @@ static const struct drm_connector_funcs intel_sdvo_connector_funcs = { · 12 unmodified lines
25012469 .fill_modes = drm_helper_probe_single_connector_modes,
25022470 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
25032471 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
2504− .late_register = intel_sdvo_connector_register,
2505− .early_unregister = intel_sdvo_connector_unregister,
2472+ .late_register = intel_connector_register,
2473+ .early_unregister = intel_connector_unregister,
25062474 .destroy = intel_connector_destroy,
25072475 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
25082476 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
@@ -2539,29 +2507,37 @@ static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs · 30 unmodified lines
25392507 .atomic_check = intel_sdvo_atomic_check,
25402508 };
25412509
2542−static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2510+static void intel_sdvo_encoder_destroy(struct drm_encoder *_encoder)
25432511 {
2544− struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2512+ struct intel_encoder *encoder = to_intel_encoder(_encoder);
2513+ struct intel_sdvo *sdvo = to_sdvo(encoder);
2514+ int i;
25452515
2546− i2c_del_adapter(&intel_sdvo->ddc);
2547− intel_encoder_destroy(encoder);
2548−}
2516+ for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) {
2517+ if (sdvo->ddc[i].ddc_bus)
2518+ i2c_del_adapter(&sdvo->ddc[i].ddc);
2519+ }
2520+
2521+ drm_encoder_cleanup(&encoder->base);
2522+ kfree(sdvo);
2523+};
25492524
25502525 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2551− .destroy = intel_sdvo_enc_destroy,
2526+ .destroy = intel_sdvo_encoder_destroy,
25522527 };
25532528
2554−static void
2555−intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2529+static int
2530+intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo,
2531+ struct intel_sdvo_connector *connector)
25562532 {
25572533 u16 mask = 0;
2558− unsigned int num_bits;
2534+ int num_bits;
25592535
25602536 /*
25612537 * Make a mask of outputs less than or equal to our own priority in the
25622538 * list.
25632539 */
2564− switch (sdvo->controlled_output) {
2540+ switch (connector->output_flag) {
25652541 case SDVO_OUTPUT_LVDS1:
25662542 mask |= SDVO_OUTPUT_LVDS1;
25672543 fallthrough;
@@ -2590,7 +2566,7 @@ intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) · 22 unmodified lines
25902566 num_bits = 3;
25912567
25922568 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2593− sdvo->ddc_bus = 1 << num_bits;
2569+ return num_bits;
25942570 }
25952571
25962572 /*
@@ -2600,31 +2576,38 @@ intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) · 3 unmodified lines
26002576 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
26012577 * outputs, then LVDS outputs.
26022578 */
2603−static void
2604−intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2605− struct intel_sdvo *sdvo)
2579+static struct intel_sdvo_ddc *
2580+intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
2581+ struct intel_sdvo_connector *connector)
26062582 {
2607− struct sdvo_device_mapping *mapping;
2583+ struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2584+ const struct sdvo_device_mapping *mapping;
2585+ int ddc_bus;
26082586
2609− if (sdvo->port == PORT_B)
2587+ if (sdvo->base.port == PORT_B)
26102588 mapping = &dev_priv->display.vbt.sdvo_mappings[0];
26112589 else
26122590 mapping = &dev_priv->display.vbt.sdvo_mappings[1];
26132591
26142592 if (mapping->initialized)
2615− sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2593+ ddc_bus = (mapping->ddc_pin & 0xf0) >> 4;
26162594 else
2617− intel_sdvo_guess_ddc_bus(sdvo);
2595+ ddc_bus = intel_sdvo_guess_ddc_bus(sdvo, connector);
2596+
2597+ if (ddc_bus < 1 || ddc_bus > 3)
2598+ return NULL;
2599+
2600+ return &sdvo->ddc[ddc_bus - 1];
26182601 }
26192602
26202603 static void
2621−intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2622− struct intel_sdvo *sdvo)
2604+intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
26232605 {
2624− struct sdvo_device_mapping *mapping;
2606+ struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2607+ const struct sdvo_device_mapping *mapping;
26252608 u8 pin;
26262609
2627− if (sdvo->port == PORT_B)
2610+ if (sdvo->base.port == PORT_B)
26282611 mapping = &dev_priv->display.vbt.sdvo_mappings[0];
26292612 else
26302613 mapping = &dev_priv->display.vbt.sdvo_mappings[1];
@@ -2635,6 +2618,10 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, · 4 unmodified lines
26352618 else
26362619 pin = GMBUS_PIN_DPB;
26372620
2621+ drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, slave addr 0x%x\n",
2622+ sdvo->base.base.base.id, sdvo->base.base.name,
2623+ pin, sdvo->slave_addr);
2624+
26382625 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
26392626
26402627 /*
@@ -2659,12 +2646,12 @@ intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) · 18 unmodified lines
26592646 }
26602647
26612648 static u8
2662−intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2663− struct intel_sdvo *sdvo)
2649+intel_sdvo_get_slave_addr(struct intel_sdvo *sdvo)
26642650 {
2665− struct sdvo_device_mapping *my_mapping, *other_mapping;
2651+ struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2652+ const struct sdvo_device_mapping *my_mapping, *other_mapping;
26662653
2667− if (sdvo->port == PORT_B) {
2654+ if (sdvo->base.port == PORT_B) {
26682655 my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
26692656 other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
26702657 } else {
@@ -2691,28 +2678,36 @@ intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv, · 20 unmodified lines
26912678 * No SDVO device info is found for another DVO port,
26922679 * so use mapping assumption we had before BIOS parsing.
26932680 */
2694− if (sdvo->port == PORT_B)
2681+ if (sdvo->base.port == PORT_B)
26952682 return 0x70;
26962683 else
26972684 return 0x72;
26982685 }
26992686
2687+static int
2688+intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
2689+ struct intel_sdvo *sdvo, int bit);
2690+
27002691 static int
27012692 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
27022693 struct intel_sdvo *encoder)
27032694 {
2704− struct drm_connector *drm_connector;
2695+ struct drm_i915_private *i915 = to_i915(encoder->base.base.dev);
2696+ struct intel_sdvo_ddc *ddc = NULL;
27052697 int ret;
27062698
2707− drm_connector = &connector->base.base;
2708− ret = drm_connector_init(encoder->base.base.dev,
2709− drm_connector,
2710− &intel_sdvo_connector_funcs,
2711− connector->base.base.connector_type);
2699+ if (HAS_DDC(connector))
2700+ ddc = intel_sdvo_select_ddc_bus(encoder, connector);
2701+
2702+ ret = drm_connector_init_with_ddc(encoder->base.base.dev,
2703+ &connector->base.base,
2704+ &intel_sdvo_connector_funcs,
2705+ connector->base.base.connector_type,
2706+ ddc ? &ddc->ddc : NULL);
27122707 if (ret < 0)
27132708 return ret;
27142709
2715− drm_connector_helper_add(drm_connector,
2710+ drm_connector_helper_add(&connector->base.base,
27162711 &intel_sdvo_connector_helper_funcs);
27172712
27182713 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
@@ -2721,6 +2716,11 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector, · 2 unmodified lines
27212716
27222717 intel_connector_attach_encoder(&connector->base, &encoder->base);
27232718
2719+ if (ddc)
2720+ drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using %s\n",
2721+ connector->base.base.base.id, connector->base.base.name,
2722+ ddc->ddc.name);
2723+
27242724 return 0;
27252725 }
27262726
@@ -2918,7 +2918,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) · 191 unmodified lines
29182918 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
29192919 mutex_lock(&i915->drm.mode_config.mutex);
29202920
2921− intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2921+ intel_ddc_get_modes(connector, connector->ddc);
29222922 intel_panel_add_edid_fixed_modes(intel_connector, false);
29232923
29242924 mutex_unlock(&i915->drm.mode_config.mutex);
@@ -2982,7 +2982,6 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) · 57 unmodified lines
29822982 SDVO_OUTPUT_LVDS0,
29832983 SDVO_OUTPUT_LVDS1,
29842984 };
2985− struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
29862985 u16 flags;
29872986 int i;
29882987
@@ -2994,10 +2993,6 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) · 5 unmodified lines
29942993 return false;
29952994 }
29962995
2997− intel_sdvo->controlled_output = flags;
2998−
2999− intel_sdvo_select_ddc_bus(i915, intel_sdvo);
3000−
30012996 for (i = 0; i < ARRAY_SIZE(probe_order); i++) {
30022997 u16 type = flags & probe_order[i];
30032998
@@ -3250,9 +3245,10 @@ static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, · 246 unmodified lines
32503245 struct i2c_msg *msgs,
32513246 int num)
32523247 {
3253− struct intel_sdvo *sdvo = adapter->algo_data;
3248+ struct intel_sdvo_ddc *ddc = adapter->algo_data;
3249+ struct intel_sdvo *sdvo = ddc->sdvo;
32543250
3255− if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
3251+ if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus))
32563252 return -EIO;
32573253
32583254 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
@@ -3260,7 +3256,9 @@ static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, · 1 unmodified line
32603256
32613257 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
32623258 {
3263− struct intel_sdvo *sdvo = adapter->algo_data;
3259+ struct intel_sdvo_ddc *ddc = adapter->algo_data;
3260+ struct intel_sdvo *sdvo = ddc->sdvo;
3261+
32643262 return sdvo->i2c->algo->functionality(sdvo->i2c);
32653263 }
32663264
@@ -3272,21 +3270,27 @@ static const struct i2c_algorithm intel_sdvo_ddc_proxy = { · 5 unmodified lines
32723270 static void proxy_lock_bus(struct i2c_adapter *adapter,
32733271 unsigned int flags)
32743272 {
3275− struct intel_sdvo *sdvo = adapter->algo_data;
3273+ struct intel_sdvo_ddc *ddc = adapter->algo_data;
3274+ struct intel_sdvo *sdvo = ddc->sdvo;
3275+
32763276 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
32773277 }
32783278
32793279 static int proxy_trylock_bus(struct i2c_adapter *adapter,
32803280 unsigned int flags)
32813281 {
3282− struct intel_sdvo *sdvo = adapter->algo_data;
3282+ struct intel_sdvo_ddc *ddc = adapter->algo_data;
3283+ struct intel_sdvo *sdvo = ddc->sdvo;
3284+
32833285 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
32843286 }
32853287
32863288 static void proxy_unlock_bus(struct i2c_adapter *adapter,
32873289 unsigned int flags)
32883290 {
3289− struct intel_sdvo *sdvo = adapter->algo_data;
3291+ struct intel_sdvo_ddc *ddc = adapter->algo_data;
3292+ struct intel_sdvo *sdvo = ddc->sdvo;
3293+
32903294 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
32913295 }
32923296
@@ -3296,21 +3300,26 @@ static const struct i2c_lock_operations proxy_lock_ops = { · 3 unmodified lines
32963300 .unlock_bus = proxy_unlock_bus,
32973301 };
32983302
3299−static bool
3300−intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
3301− struct drm_i915_private *dev_priv)
3303+static int
3304+intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
3305+ struct intel_sdvo *sdvo, int ddc_bus)
33023306 {
3307+ struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
33033308 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
33043309
3305− sdvo->ddc.owner = THIS_MODULE;
3306− sdvo->ddc.class = I2C_CLASS_DDC;
3307− snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
3308− sdvo->ddc.dev.parent = &pdev->dev;
3309− sdvo->ddc.algo_data = sdvo;
3310− sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
3311− sdvo->ddc.lock_ops = &proxy_lock_ops;
3310+ ddc->sdvo = sdvo;
3311+ ddc->ddc_bus = ddc_bus;
33123312
3313− return i2c_add_adapter(&sdvo->ddc) == 0;
3313+ ddc->ddc.owner = THIS_MODULE;
3314+ ddc->ddc.class = I2C_CLASS_DDC;
3315+ snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d",
3316+ port_name(sdvo->base.port), ddc_bus);
3317+ ddc->ddc.dev.parent = &pdev->dev;
3318+ ddc->ddc.algo_data = ddc;
3319+ ddc->ddc.algo = &intel_sdvo_ddc_proxy;
3320+ ddc->ddc.lock_ops = &proxy_lock_ops;
3321+
3322+ return i2c_add_adapter(&ddc->ddc);
33143323 }
33153324
33163325 static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port)
@@ -3345,23 +3354,21 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, · 28 unmodified lines
33453354 if (!intel_sdvo)
33463355 return false;
33473356
3348− intel_sdvo->sdvo_reg = sdvo_reg;
3349− intel_sdvo->port = port;
3350− intel_sdvo->slave_addr =
3351− intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
3352− intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3353− if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
3354− goto err_i2c_bus;
3355−
33563357 /* encoder type will be decided later */
33573358 intel_encoder = &intel_sdvo->base;
33583359 intel_encoder->type = INTEL_OUTPUT_SDVO;
33593360 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
33603361 intel_encoder->port = port;
3362+
33613363 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
33623364 &intel_sdvo_enc_funcs, 0,
33633365 "SDVO %c", port_name(port));
33643366
3367+ intel_sdvo->sdvo_reg = sdvo_reg;
3368+ intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(intel_sdvo) >> 1;
3369+
3370+ intel_sdvo_select_i2c_bus(intel_sdvo);
3371+
33653372 /* Read the regs to test if we can talk to the device */
33663373 for (i = 0; i < 0x40; i++) {
33673374 u8 byte;
@@ -3393,6 +3400,15 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, · 25 unmodified lines
33933400 intel_sdvo->colorimetry_cap =
33943401 intel_sdvo_get_colorimetry_cap(intel_sdvo);
33953402
3403+ for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) {
3404+ int ret;
3405+
3406+ ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i],
3407+ intel_sdvo, i + 1);
3408+ if (ret)
3409+ goto err;
3410+ }
3411+
33963412 if (!intel_sdvo_output_setup(intel_sdvo)) {
33973413 drm_dbg_kms(&dev_priv->drm,
33983414 "SDVO output failed to setup on %s\n",
@@ -3406,7 +3422,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, · 7 unmodified lines
34063422 * hotplug lines.
34073423 */
34083424 if (intel_sdvo->hotplug_active) {
3409− if (intel_sdvo->port == PORT_B)
3425+ if (intel_sdvo->base.port == PORT_B)
34103426 intel_encoder->hpd_pin = HPD_SDVO_B;
34113427 else
34123428 intel_encoder->hpd_pin = HPD_SDVO_C;
@@ -3433,15 +3449,14 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, · 20 unmodified lines
34333449
34343450 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
34353451 "clock range %dMHz - %dMHz, "
3436− "input 1: %c, input 2: %c, "
3452+ "num inputs: %d, "
34373453 "output 1: %c, output 2: %c\n",
34383454 SDVO_NAME(intel_sdvo),
34393455 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
34403456 intel_sdvo->caps.device_rev_id,
34413457 intel_sdvo->pixel_clock_min / 1000,
34423458 intel_sdvo->pixel_clock_max / 1000,
3443− (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3444− (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3459+ intel_sdvo->caps.sdvo_num_inputs,
34453460 /* check currently supported outputs */
34463461 intel_sdvo->caps.output_flags &
34473462 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 |
@@ -3454,13 +3469,9 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, · 6 unmodified lines
34543469
34553470 err_output:
34563471 intel_sdvo_output_cleanup(intel_sdvo);
3457−
34583472 err:
3459− drm_encoder_cleanup(&intel_encoder->base);
3460− i2c_del_adapter(&intel_sdvo->ddc);
3461−err_i2c_bus:
34623473 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3463− kfree(intel_sdvo);
3474+ intel_sdvo_encoder_destroy(&intel_encoder->base);
34643475
34653476 return false;
34663477 }
drivers/gpu/drm/i915/display/intel_sdvo_regs.h+1−1
@@ -57,7 +57,7 @@ struct intel_sdvo_caps { · 56 unmodified lines
5757 u8 device_rev_id;
5858 u8 sdvo_version_major;
5959 u8 sdvo_version_minor;
60− unsigned int sdvo_inputs_mask:2;
60+ unsigned int sdvo_num_inputs:2;
6161 unsigned int smooth_scaling:1;
6262 unsigned int sharp_scaling:1;
6363 unsigned int up_scaling:1;
drivers/gpu/drm/i915/display/intel_sprite.c+1−0
@@ -45,6 +45,7 @@ · 44 unmodified lines
4545 #include "intel_de.h"
4646 #include "intel_display_types.h"
4747 #include "intel_fb.h"
48+#include "intel_frontbuffer.h"
4849 #include "intel_sprite.h"
4950
5051 static void i9xx_plane_linear_gamma(u16 gamma[8])
drivers/gpu/drm/i915/display/intel_tc.c+50−16
@@ -260,7 +260,7 @@ assert_tc_port_power_enabled(struct intel_tc_port *tc) · 259 unmodified lines
260260 !intel_display_power_is_enabled(i915, tc_port_power_domain(tc)));
261261 }
262262
263−u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
263+static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
264264 {
265265 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
266266 struct intel_tc_port *tc = to_tc_port(dig_port);
@@ -290,7 +290,32 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) · 23 unmodified lines
290290 DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
291291 }
292292
293−static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
293+static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
294+{
295+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
296+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
297+ intel_wakeref_t wakeref;
298+ u32 val, pin_assignment;
299+
300+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
301+ val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
302+
303+ pin_assignment =
304+ REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
305+
306+ switch (pin_assignment) {
307+ default:
308+ MISSING_CASE(pin_assignment);
309+ fallthrough;
310+ case DP_PIN_ASSIGNMENT_D:
311+ return 2;
312+ case DP_PIN_ASSIGNMENT_C:
313+ case DP_PIN_ASSIGNMENT_E:
314+ return 4;
315+ }
316+}
317+
318+static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
294319 {
295320 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
296321 intel_wakeref_t wakeref;
@@ -311,23 +336,12 @@ static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_po · 14 unmodified lines
311336 }
312337 }
313338
314−int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
339+static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
315340 {
316341 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
317− struct intel_tc_port *tc = to_tc_port(dig_port);
318− enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
319342 intel_wakeref_t wakeref;
320− u32 lane_mask;
321−
322− if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
323− return 4;
324−
325− assert_tc_cold_blocked(tc);
326−
327− if (DISPLAY_VER(i915) >= 14)
328− return mtl_tc_port_get_pin_assignment_mask(dig_port);
343+ u32 lane_mask = 0;
329344
330− lane_mask = 0;
331345 with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
332346 lane_mask = intel_tc_port_get_lane_mask(dig_port);
333347
@@ -348,6 +362,26 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) · 14 unmodified lines
348362 }
349363 }
350364
365+int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
366+{
367+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
368+ struct intel_tc_port *tc = to_tc_port(dig_port);
369+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
370+
371+ if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
372+ return 4;
373+
374+ assert_tc_cold_blocked(tc);
375+
376+ if (DISPLAY_VER(i915) >= 20)
377+ return lnl_tc_port_get_max_lane_count(dig_port);
378+
379+ if (DISPLAY_VER(i915) >= 14)
380+ return mtl_tc_port_get_max_lane_count(dig_port);
381+
382+ return intel_tc_port_get_max_lane_count(dig_port);
383+}
384+
351385 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
352386 int required_lanes)
353387 {
@@ -583,7 +617,7 @@ static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port *tc, · 229 unmodified lines
583617 struct intel_digital_port *dig_port = tc->dig_port;
584618 int max_lanes;
585619
586− max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
620+ max_lanes = intel_tc_port_max_lane_count(dig_port);
587621 if (tc->mode == TC_PORT_LEGACY) {
588622 drm_WARN_ON(&i915->drm, max_lanes != 4);
589623 return true;
drivers/gpu/drm/i915/display/intel_tc.h+1−2
@@ -19,9 +19,8 @@ bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port); · 18 unmodified lines
1919 bool intel_tc_port_connected(struct intel_encoder *encoder);
2020 bool intel_tc_port_connected_locked(struct intel_encoder *encoder);
2121
22−u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
2322 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
24−int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
23+int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
2524 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
2625 int required_lanes);
2726
drivers/gpu/drm/i915/display/intel_vblank.c+14−0
@@ -251,6 +251,20 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) · 250 unmodified lines
251251 return (position + crtc->scanline_offset) % vtotal;
252252 }
253253
254+int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
255+{
256+ const struct drm_vblank_crtc *vblank =
257+ &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
258+ const struct drm_display_mode *mode = &vblank->hwmode;
259+ int vtotal;
260+
261+ vtotal = mode->crtc_vtotal;
262+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
263+ vtotal /= 2;
264+
265+ return (scanline + vtotal - crtc->scanline_offset) % vtotal;
266+}
267+
254268 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
255269 bool in_vblank_irq,
256270 int *vpos, int *hpos,
drivers/gpu/drm/i915/display/intel_vblank.h+1−0
@@ -22,5 +22,6 @@ void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc); · 21 unmodified lines
2222 void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc);
2323 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
2424 bool vrr_enable);
25+int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline);
2526
2627 #endif /* __INTEL_VBLANK_H__ */
drivers/gpu/drm/i915/display/intel_vdsc.c+287−343
@@ -80,13 +80,19 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) · 79 unmodified lines
8080 int bpc = vdsc_cfg->bits_per_component;
8181 int bpp = vdsc_cfg->bits_per_pixel >> 4;
8282 int qp_bpc_modifier = (bpc - 8) * 2;
83+ int uncompressed_bpg_rate;
84+ int first_line_bpg_offset;
8385 u32 res, buf_i, bpp_i;
8486
8587 if (vdsc_cfg->slice_height >= 8)
86− vdsc_cfg->first_line_bpg_offset =
87− 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
88+ first_line_bpg_offset =
89+ 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100;
8890 else
89− vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
91+ first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
92+
93+ uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3;
94+ vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0,
95+ uncompressed_bpg_rate - 3 * bpp);
9096
9197 /*
9298 * According to DSC 1.2 spec in Section 4.1 if native_420 is set:
@@ -350,9 +356,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) · 257 unmodified lines
350356 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
351357 }
352358
359+static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
360+{
361+ return crtc_state->dsc.dsc_split ? 2 : 1;
362+}
363+
353364 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
354365 {
355− int num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
366+ int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state);
356367
357368 if (crtc_state->bigjoiner_pipes)
358369 num_vdsc_instances *= 2;
@@ -360,6 +371,43 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) · 1 unmodified line
360371 return num_vdsc_instances;
361372 }
362373
374+static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
375+ i915_reg_t *dsc_reg, int dsc_reg_num)
376+{
377+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
378+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
379+ enum pipe pipe = crtc->pipe;
380+ bool pipe_dsc;
381+
382+ pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
383+
384+ if (dsc_reg_num >= 3)
385+ MISSING_CASE(dsc_reg_num);
386+ if (dsc_reg_num >= 2)
387+ dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);
388+ if (dsc_reg_num >= 1)
389+ dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);
390+}
391+
392+static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
393+ int pps, u32 pps_val)
394+{
395+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
396+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
397+ i915_reg_t dsc_reg[2];
398+ int i, vdsc_per_pipe, dsc_reg_num;
399+
400+ vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
401+ dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
402+
403+ drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
404+
405+ intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
406+
407+ for (i = 0; i < dsc_reg_num; i++)
408+ intel_de_write(i915, dsc_reg[i], pps_val);
409+}
410+
363411 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
364412 {
365413 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -367,359 +415,119 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) · 1 unmodified line
367415 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
368416 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
369417 enum pipe pipe = crtc->pipe;
370− u32 pps_val = 0;
418+ u32 pps_val;
371419 u32 rc_buf_thresh_dword[4];
372420 u32 rc_range_params_dword[8];
373421 int i = 0;
374422 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
423+ int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
375424
376− /* Populate PICTURE_PARAMETER_SET_0 registers */
377− pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
378− DSC_VER_MIN_SHIFT |
379− vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
380− vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
425+ /* PPS 0 */
426+ pps_val = DSC_PPS0_VER_MAJOR(1) |
427+ DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) |
428+ DSC_PPS0_BPC(vdsc_cfg->bits_per_component) |
429+ DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth);
381430 if (vdsc_cfg->dsc_version_minor == 2) {
382− pps_val |= DSC_ALT_ICH_SEL;
431+ pps_val |= DSC_PPS0_ALT_ICH_SEL;
383432 if (vdsc_cfg->native_420)
384− pps_val |= DSC_NATIVE_420_ENABLE;
433+ pps_val |= DSC_PPS0_NATIVE_420_ENABLE;
385434 if (vdsc_cfg->native_422)
386− pps_val |= DSC_NATIVE_422_ENABLE;
435+ pps_val |= DSC_PPS0_NATIVE_422_ENABLE;
387436 }
388437 if (vdsc_cfg->block_pred_enable)
389− pps_val |= DSC_BLOCK_PREDICTION;
438+ pps_val |= DSC_PPS0_BLOCK_PREDICTION;
390439 if (vdsc_cfg->convert_rgb)
391− pps_val |= DSC_COLOR_SPACE_CONVERSION;
440+ pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;
392441 if (vdsc_cfg->simple_422)
393− pps_val |= DSC_422_ENABLE;
442+ pps_val |= DSC_PPS0_422_ENABLE;
394443 if (vdsc_cfg->vbr_enable)
395− pps_val |= DSC_VBR_ENABLE;
444+ pps_val |= DSC_PPS0_VBR_ENABLE;
396445 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
397− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
398− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
399− pps_val);
400− /*
401− * If 2 VDSC instances are needed, configure PPS for second
402− * VDSC
403− */
404− if (crtc_state->dsc.dsc_split)
405− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
406− pps_val);
407− } else {
408− intel_de_write(dev_priv,
409− ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
410− pps_val);
411− if (crtc_state->dsc.dsc_split)
412− intel_de_write(dev_priv,
413− ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
414− pps_val);
415− }
446+ intel_dsc_pps_write(crtc_state, 0, pps_val);
416447
417− /* Populate PICTURE_PARAMETER_SET_1 registers */
418− pps_val = 0;
419− pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
448+ /* PPS 1 */
449+ pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
420450 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
421− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
422− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
423− pps_val);
424− /*
425− * If 2 VDSC instances are needed, configure PPS for second
426− * VDSC
427− */
428− if (crtc_state->dsc.dsc_split)
429− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
430− pps_val);
431− } else {
432− intel_de_write(dev_priv,
433− ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
434− pps_val);
435− if (crtc_state->dsc.dsc_split)
436− intel_de_write(dev_priv,
437− ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
438− pps_val);
439− }
451+ intel_dsc_pps_write(crtc_state, 1, pps_val);
440452
441− /* Populate PICTURE_PARAMETER_SET_2 registers */
442− pps_val = 0;
443− pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
444− DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
453+ /* PPS 2 */
454+ pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
455+ DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
445456 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
446− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
447− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
448− pps_val);
449− /*
450− * If 2 VDSC instances are needed, configure PPS for second
451− * VDSC
452− */
453− if (crtc_state->dsc.dsc_split)
454− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
455− pps_val);
456− } else {
457− intel_de_write(dev_priv,
458− ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
459− pps_val);
460− if (crtc_state->dsc.dsc_split)
461− intel_de_write(dev_priv,
462− ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
463− pps_val);
464− }
457+ intel_dsc_pps_write(crtc_state, 2, pps_val);
465458
466− /* Populate PICTURE_PARAMETER_SET_3 registers */
467− pps_val = 0;
468− pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
469− DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
459+ /* PPS 3 */
460+ pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
461+ DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
470462 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
471− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
472− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
473− pps_val);
474− /*
475− * If 2 VDSC instances are needed, configure PPS for second
476− * VDSC
477− */
478− if (crtc_state->dsc.dsc_split)
479− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
480− pps_val);
481− } else {
482− intel_de_write(dev_priv,
483− ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
484− pps_val);
485− if (crtc_state->dsc.dsc_split)
486− intel_de_write(dev_priv,
487− ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
488− pps_val);
489− }
463+ intel_dsc_pps_write(crtc_state, 3, pps_val);
490464
491− /* Populate PICTURE_PARAMETER_SET_4 registers */
492− pps_val = 0;
493− pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
494− DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
465+ /* PPS 4 */
466+ pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
467+ DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
495468 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
496− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
497− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
498− pps_val);
499− /*
500− * If 2 VDSC instances are needed, configure PPS for second
501− * VDSC
502− */
503− if (crtc_state->dsc.dsc_split)
504− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
505− pps_val);
506− } else {
507− intel_de_write(dev_priv,
508− ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
509− pps_val);
510− if (crtc_state->dsc.dsc_split)
511− intel_de_write(dev_priv,
512− ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
513− pps_val);
514− }
469+ intel_dsc_pps_write(crtc_state, 4, pps_val);
515470
516− /* Populate PICTURE_PARAMETER_SET_5 registers */
517− pps_val = 0;
518− pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
519− DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
471+ /* PPS 5 */
472+ pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
473+ DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
520474 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
521− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
522− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
523− pps_val);
524− /*
525− * If 2 VDSC instances are needed, configure PPS for second
526− * VDSC
527− */
528− if (crtc_state->dsc.dsc_split)
529− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
530− pps_val);
531− } else {
532− intel_de_write(dev_priv,
533− ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
534− pps_val);
535− if (crtc_state->dsc.dsc_split)
536− intel_de_write(dev_priv,
537− ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
538− pps_val);
539− }
475+ intel_dsc_pps_write(crtc_state, 5, pps_val);
540476
541− /* Populate PICTURE_PARAMETER_SET_6 registers */
542− pps_val = 0;
543− pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
544− DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
545− DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
546− DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
477+ /* PPS 6 */
478+ pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
479+ DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
480+ DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
481+ DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
547482 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
548− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
549− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
550− pps_val);
551− /*
552− * If 2 VDSC instances are needed, configure PPS for second
553− * VDSC
554− */
555− if (crtc_state->dsc.dsc_split)
556− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
557− pps_val);
558− } else {
559− intel_de_write(dev_priv,
560− ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
561− pps_val);
562− if (crtc_state->dsc.dsc_split)
563− intel_de_write(dev_priv,
564− ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
565− pps_val);
566− }
483+ intel_dsc_pps_write(crtc_state, 6, pps_val);
567484
568− /* Populate PICTURE_PARAMETER_SET_7 registers */
569− pps_val = 0;
570− pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
571− DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
485+ /* PPS 7 */
486+ pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
487+ DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
572488 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
573− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
574− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
575− pps_val);
576− /*
577− * If 2 VDSC instances are needed, configure PPS for second
578− * VDSC
579− */
580− if (crtc_state->dsc.dsc_split)
581− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
582− pps_val);
583− } else {
584− intel_de_write(dev_priv,
585− ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
586− pps_val);
587− if (crtc_state->dsc.dsc_split)
588− intel_de_write(dev_priv,
589− ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
590− pps_val);
591− }
489+ intel_dsc_pps_write(crtc_state, 7, pps_val);
592490
593− /* Populate PICTURE_PARAMETER_SET_8 registers */
594− pps_val = 0;
595− pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
596− DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
491+ /* PPS 8 */
492+ pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
493+ DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
597494 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
598− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
599− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
600− pps_val);
601− /*
602− * If 2 VDSC instances are needed, configure PPS for second
603− * VDSC
604− */
605− if (crtc_state->dsc.dsc_split)
606− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
607− pps_val);
608− } else {
609− intel_de_write(dev_priv,
610− ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
611− pps_val);
612− if (crtc_state->dsc.dsc_split)
613− intel_de_write(dev_priv,
614− ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
615− pps_val);
616− }
495+ intel_dsc_pps_write(crtc_state, 8, pps_val);
617496
618− /* Populate PICTURE_PARAMETER_SET_9 registers */
619− pps_val = 0;
620− pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
621− DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
497+ /* PPS 9 */
498+ pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
499+ DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
622500 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
623− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
624− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
625− pps_val);
626− /*
627− * If 2 VDSC instances are needed, configure PPS for second
628− * VDSC
629− */
630− if (crtc_state->dsc.dsc_split)
631− intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
632− pps_val);
633− } else {
634− intel_de_write(dev_priv,
635− ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
636− pps_val);
637− if (crtc_state->dsc.dsc_split)
638− intel_de_write(dev_priv,
639− ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
640− pps_val);
641− }
501+ intel_dsc_pps_write(crtc_state, 9, pps_val);
642502
643− /* Populate PICTURE_PARAMETER_SET_10 registers */
644− pps_val = 0;
645− pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
646− DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
647− DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
648− DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
503+ /* PPS 10 */
504+ pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
505+ DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
506+ DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
507+ DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
649508 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
650− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
651− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
652− pps_val);
653− /*
654− * If 2 VDSC instances are needed, configure PPS for second
655− * VDSC
656− */
657− if (crtc_state->dsc.dsc_split)
658− intel_de_write(dev_priv,
659− DSCC_PICTURE_PARAMETER_SET_10, pps_val);
660− } else {
661− intel_de_write(dev_priv,
662− ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
663− pps_val);
664− if (crtc_state->dsc.dsc_split)
665− intel_de_write(dev_priv,
666− ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
667− pps_val);
668− }
669−
670− /* Populate Picture parameter set 16 */
671− pps_val = 0;
672− pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
673− DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
674− vdsc_cfg->slice_width) |
675− DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
676− vdsc_cfg->slice_height);
509+ intel_dsc_pps_write(crtc_state, 10, pps_val);
510+
511+ /* PPS 16 */
512+ pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
513+ DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
514+ vdsc_cfg->slice_width) |
515+ DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
516+ vdsc_cfg->slice_height);
677517 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
678− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
679− intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
680− pps_val);
681− /*
682− * If 2 VDSC instances are needed, configure PPS for second
683− * VDSC
684− */
685− if (crtc_state->dsc.dsc_split)
686− intel_de_write(dev_priv,
687− DSCC_PICTURE_PARAMETER_SET_16, pps_val);
688− } else {
689− intel_de_write(dev_priv,
690− ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
691− pps_val);
692− if (crtc_state->dsc.dsc_split)
693− intel_de_write(dev_priv,
694− ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
695− pps_val);
696− }
518+ intel_dsc_pps_write(crtc_state, 16, pps_val);
697519
698520 if (DISPLAY_VER(dev_priv) >= 14) {
699− /* Populate PICTURE_PARAMETER_SET_17 registers */
700− pps_val = 0;
701− pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
521+ /* PPS 17 */
522+ pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
702523 drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
703− intel_de_write(dev_priv,
704− MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
705− pps_val);
706− if (crtc_state->dsc.dsc_split)
707− intel_de_write(dev_priv,
708− MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
709− pps_val);
524+ intel_dsc_pps_write(crtc_state, 17, pps_val);
710525
711− /* Populate PICTURE_PARAMETER_SET_18 registers */
712− pps_val = 0;
713− pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
714− DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
526+ /* PPS 18 */
527+ pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
528+ DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
715529 drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
716− intel_de_write(dev_priv,
717− MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
718− pps_val);
719− if (crtc_state->dsc.dsc_split)
720− intel_de_write(dev_priv,
721− MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
722− pps_val);
530+ intel_dsc_pps_write(crtc_state, 18, pps_val);
723531 }
724532
725533 /* Populate the RC_BUF_THRESH registers */
@@ -740,7 +548,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) · 14 unmodified lines
740548 rc_buf_thresh_dword[2]);
741549 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
742550 rc_buf_thresh_dword[3]);
743− if (crtc_state->dsc.dsc_split) {
551+ if (vdsc_instances_per_pipe > 1) {
744552 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
745553 rc_buf_thresh_dword[0]);
746554 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
@@ -759,7 +567,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) · 12 unmodified lines
759567 rc_buf_thresh_dword[2]);
760568 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
761569 rc_buf_thresh_dword[3]);
762− if (crtc_state->dsc.dsc_split) {
570+ if (vdsc_instances_per_pipe > 1) {
763571 intel_de_write(dev_priv,
764572 ICL_DSC1_RC_BUF_THRESH_0(pipe),
765573 rc_buf_thresh_dword[0]);
@@ -805,7 +613,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) · 39 unmodified lines
805613 rc_range_params_dword[6]);
806614 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
807615 rc_range_params_dword[7]);
808− if (crtc_state->dsc.dsc_split) {
616+ if (vdsc_instances_per_pipe > 1) {
809617 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
810618 rc_range_params_dword[0]);
811619 intel_de_write(dev_priv,
@@ -848,7 +656,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) · 36 unmodified lines
848656 intel_de_write(dev_priv,
849657 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
850658 rc_range_params_dword[7]);
851− if (crtc_state->dsc.dsc_split) {
659+ if (vdsc_instances_per_pipe > 1) {
852660 intel_de_write(dev_priv,
853661 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
854662 rc_range_params_dword[0]);
@@ -954,6 +762,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) · 99 unmodified lines
954762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
955763 u32 dss_ctl1_val = 0;
956764 u32 dss_ctl2_val = 0;
765+ int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
957766
958767 if (!crtc_state->dsc.compression_enable)
959768 return;
@@ -961,7 +770,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) · 1 unmodified line
961770 intel_dsc_pps_configure(crtc_state);
962771
963772 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
964− if (crtc_state->dsc.dsc_split) {
773+ if (vdsc_instances_per_pipe > 1) {
965774 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
966775 dss_ctl1_val |= JOINER_ENABLE;
967776 }
@@ -987,16 +796,168 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) · 19 unmodified lines
987796 }
988797 }
989798
799+static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
800+ bool *check_equal)
801+{
802+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
803+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
804+ i915_reg_t dsc_reg[2];
805+ int i, vdsc_per_pipe, dsc_reg_num;
806+ u32 val = 0;
807+
808+ vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
809+ dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
810+
811+ drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
812+
813+ intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
814+
815+ if (check_equal)
816+ *check_equal = true;
817+
818+ for (i = 0; i < dsc_reg_num; i++) {
819+ u32 tmp;
820+
821+ tmp = intel_de_read(i915, dsc_reg[i]);
822+
823+ if (i == 0) {
824+ val = tmp;
825+ } else if (check_equal && tmp != val) {
826+ *check_equal = false;
827+ break;
828+ } else if (!check_equal) {
829+ break;
830+ }
831+ }
832+
833+ return val;
834+}
835+
836+static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
837+{
838+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
839+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
840+ u32 val;
841+ bool all_equal;
842+
843+ val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
844+ drm_WARN_ON(&i915->drm, !all_equal);
845+
846+ return val;
847+}
848+
849+static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
850+{
851+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
852+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
853+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
854+ int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
855+ u32 pps_temp;
856+
857+ /* PPS 0 */
858+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
859+
860+ vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);
861+ vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp);
862+ vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION;
863+ vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION;
864+ vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
865+ vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE;
866+ vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE;
867+ vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE;
868+
869+ /* PPS 1 */
870+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
871+
872+ vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);
873+
874+ if (vdsc_cfg->native_420)
875+ vdsc_cfg->bits_per_pixel >>= 1;
876+
877+ crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
878+
879+ /* PPS 2 */
880+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
881+
882+ vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances;
883+ vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp);
884+
885+ /* PPS 3 */
886+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
887+
888+ vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);
889+ vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp);
890+
891+ /* PPS 4 */
892+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
893+
894+ vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);
895+ vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);
896+
897+ /* PPS 5 */
898+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
899+
900+ vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);
901+ vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);
902+
903+ /* PPS 6 */
904+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
905+
906+ vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);
907+ vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
908+ vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);
909+ vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);
910+
911+ /* PPS 7 */
912+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
913+
914+ vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);
915+ vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);
916+
917+ /* PPS 8 */
918+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
919+
920+ vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);
921+ vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp);
922+
923+ /* PPS 9 */
924+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
925+
926+ vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp);
927+
928+ /* PPS 10 */
929+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
930+
931+ vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
932+ vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
933+
934+ /* PPS 16 */
935+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
936+
937+ vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
938+
939+ if (DISPLAY_VER(i915) >= 14) {
940+ /* PPS 17 */
941+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
942+
943+ vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);
944+
945+ /* PPS 18 */
946+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
947+
948+ vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);
949+ vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);
950+ }
951+}
952+
990953 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
991954 {
992955 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
993956 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
994− struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
995957 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
996− enum pipe pipe = crtc->pipe;
997958 enum intel_display_power_domain power_domain;
998959 intel_wakeref_t wakeref;
999− u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
960+ u32 dss_ctl1, dss_ctl2;
1000961
1001962 if (!intel_dsc_source_support(crtc_state))
1002963 return;
@@ -1017,24 +978,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) · 14 unmodified lines
1017978 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1018979 (dss_ctl1 & JOINER_ENABLE);
1019980
1020− /* FIXME: add more state readout as needed */
1021−
1022− /* PPS0 & PPS1 */
1023− if (!is_pipe_dsc(crtc, cpu_transcoder)) {
1024− pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1025− } else {
1026− pps0 = intel_de_read(dev_priv,
1027− ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
1028− pps1 = intel_de_read(dev_priv,
1029− ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1030− }
1031−
1032− vdsc_cfg->bits_per_pixel = pps1;
1033−
1034− if (pps0 & DSC_NATIVE_420_ENABLE)
1035− vdsc_cfg->bits_per_pixel >>= 1;
1036−
1037− crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
981+ intel_dsc_get_pps_config(crtc_state);
1038982 out:
1039983 intel_display_power_put(dev_priv, power_domain, wakeref);
1040984 }
drivers/gpu/drm/i915/display/intel_vdsc_regs.h+126−271
@@ -46,35 +46,13 @@ · 45 unmodified lines
4646 _ICL_PIPE_DSS_CTL2_PB, \
4747 _ICL_PIPE_DSS_CTL2_PC)
4848
49−/* MTL Display Stream Compression registers */
50−#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4
51−#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4
52−#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4
53−#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4
54−#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
55− _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
56− _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
57−#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
58− _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
59− _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
60−#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27)
61−
62−#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8
63−#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8
64−#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8
65−#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8
66−#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
67− _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
68− _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
69−#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
70− _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
71− _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
72−#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16)
73−#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0)
74−
7549 /* Icelake Display Stream Compression Registers */
7650 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
7751 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
52+#define _DSCA_PPS_0 0x6B200
53+#define _DSCC_PPS_0 0x6BA00
54+#define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + (pps) * 4)
55+#define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + (pps) * 4)
7856 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
7957 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
8058 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
@@ -85,251 +63,128 @@ · 4 unmodified lines
8563 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8664 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
8765 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
88−#define DSC_NATIVE_422_ENABLE BIT(23)
89−#define DSC_NATIVE_420_ENABLE BIT(22)
90−#define DSC_ALT_ICH_SEL (1 << 20)
91−#define DSC_VBR_ENABLE (1 << 19)
92−#define DSC_422_ENABLE (1 << 18)
93−#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
94−#define DSC_BLOCK_PREDICTION (1 << 16)
95−#define DSC_LINE_BUF_DEPTH_SHIFT 12
96−#define DSC_BPC_SHIFT 8
97−#define DSC_VER_MIN_SHIFT 4
98−#define DSC_VER_MAJ (0x1 << 0)
99−
100−#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
101−#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
102−#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
103−#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
104−#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
105−#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
106−#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
107− _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
108− _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
109−#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
110− _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
111− _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
112−#define DSC_BPP(bpp) ((bpp) << 0)
113−
114−#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
115−#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
116−#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
117−#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
118−#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
119−#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
120−#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
121− _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
122− _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
123−#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
124− _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
125− _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
126−#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
127−#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
128−
129−#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
130−#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
131−#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
132−#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
133−#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
134−#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
135−#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
136− _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
137− _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
138−#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
139− _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
140− _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
141−#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
142−#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
143−
144−#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
145−#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
146−#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
147−#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
148−#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
149−#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
150−#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
151− _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
152− _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
153−#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
154− _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
155− _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
156−#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
157−#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
158−
159−#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
160−#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
161−#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
162−#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
163−#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
164−#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
165−#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
166− _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
167− _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
168−#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
169− _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
170− _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
171−#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
172−#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
173−
174−#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
175−#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
176−#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
177−#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
178−#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
179−#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
180−#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
181− _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
182− _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
183−#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
184− _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
185− _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
186−#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
187−#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
188−#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
189−#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
190−
191−#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
192−#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
193−#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
194−#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
195−#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
196−#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
197−#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
198− _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
199− _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
200−#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
201− _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
202− _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
203−#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
204−#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
205−
206−#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
207−#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
208−#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
209−#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
210−#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
211−#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
212−#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
213− _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
214− _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
215−#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
216− _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
217− _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
218−#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
219−#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
220−
221−#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
222−#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
223−#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
224−#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
225−#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
226−#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
227−#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
228− _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
229− _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
230−#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
231− _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
232− _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
233−#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
234−#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
235−
236−#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
237−#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
238−#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
239−#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
240−#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
241−#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
242−#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
243− _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
244− _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
245−#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
246− _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
247− _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
248−#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
249−#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
250−#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
251−#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
252−
253−#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
254−#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
255−#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
256−#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
257−#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
258−#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
259−#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
260− _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
261− _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
262−#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
263− _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
264− _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
265−
266−#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
267−#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
268−#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
269−#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
270−#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
271−#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
272−#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
273− _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
274− _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
275−#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
276− _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
277− _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
278−
279−#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
280−#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
281−#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
282−#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
283−#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
284−#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
285−#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
286− _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
287− _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
288−#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
289− _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
290− _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
291−
292−#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
293−#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
294−#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
295−#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
296−#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
297−#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
298−#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
299− _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
300− _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
301−#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
302− _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
303− _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
304−
305−#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
306−#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
307−#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
308−#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
309−#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
310−#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
311−#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
312− _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
313− _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
314−#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
315− _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
316− _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
317−
318−#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
319−#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
320−#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
321−#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
322−#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
323−#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
324−#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
325− _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
326− _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
327−#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
328− _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
329− _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
330−#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
331−#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
332−#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
66+#define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
67+ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
68+ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
69+#define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
70+ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
71+ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
72+#define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
73+#define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
74+
75+/* PPS 0 */
76+#define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23)
77+#define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22)
78+#define DSC_PPS0_ALT_ICH_SEL REG_BIT(20)
79+#define DSC_PPS0_VBR_ENABLE REG_BIT(19)
80+#define DSC_PPS0_422_ENABLE REG_BIT(18)
81+#define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17)
82+#define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16)
83+#define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12)
84+#define DSC_PPS0_LINE_BUF_DEPTH(depth) REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth)
85+#define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8)
86+#define DSC_PPS0_BPC(bpc) REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc)
87+#define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4)
88+#define DSC_PPS0_VER_MINOR(minor) REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor)
89+#define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0)
90+#define DSC_PPS0_VER_MAJOR(major) REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major)
91+
92+/* PPS 1 */
93+#define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0)
94+#define DSC_PPS1_BPP(bpp) REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp)
95+
96+/* PPS 2 */
97+#define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16)
98+#define DSC_PPS2_PIC_HEIGHT_MASK REG_GENMASK(15, 0)
99+#define DSC_PPS2_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width)
100+#define DSC_PPS2_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height)
101+
102+/* PPS 3 */
103+#define DSC_PPS3_SLICE_WIDTH_MASK REG_GENMASK(31, 16)
104+#define DSC_PPS3_SLICE_HEIGHT_MASK REG_GENMASK(15, 0)
105+#define DSC_PPS3_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)
106+#define DSC_PPS3_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)
107+
108+/* PPS 4 */
109+#define DSC_PPS4_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16)
110+#define DSC_PPS4_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0)
111+#define DSC_PPS4_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \
112+ dec_delay)
113+#define DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \
114+ xmit_delay)
115+
116+/* PPS 5 */
117+#define DSC_PPS5_SCALE_DEC_INT_MASK REG_GENMASK(27, 16)
118+#define DSC_PPS5_SCALE_INC_INT_MASK REG_GENMASK(15, 0)
119+#define DSC_PPS5_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)
120+#define DSC_PPS5_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)
121+
122+/* PPS 6 */
123+#define DSC_PPS6_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24)
124+#define DSC_PPS6_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16)
125+#define DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8)
126+#define DSC_PPS6_INITIAL_SCALE_VALUE_MASK REG_GENMASK(5, 0)
127+#define DSC_PPS6_FLATNESS_MAX_QP(max_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)
128+#define DSC_PPS6_FLATNESS_MIN_QP(min_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)
129+#define DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \
130+ offset)
131+#define DSC_PPS6_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \
132+ value)
133+
134+/* PPS 7 */
135+#define DSC_PPS7_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16)
136+#define DSC_PPS7_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0)
137+#define DSC_PPS7_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)
138+#define DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \
139+ bpg_offset)
140+/* PPS 8 */
141+#define DSC_PPS8_INITIAL_OFFSET_MASK REG_GENMASK(31, 16)
142+#define DSC_PPS8_FINAL_OFFSET_MASK REG_GENMASK(15, 0)
143+#define DSC_PPS8_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \
144+ initial_offset)
145+#define DSC_PPS8_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \
146+ final_offset)
147+
148+/* PPS 9 */
149+#define DSC_PPS9_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16)
150+#define DSC_PPS9_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0)
151+#define DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \
152+ rc_edge_fact)
153+#define DSC_PPS9_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \
154+ rc_model_size)
155+
156+/* PPS 10 */
157+#define DSC_PPS10_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20)
158+#define DSC_PPS10_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16)
159+#define DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8)
160+#define DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK REG_GENMASK(4, 0)
161+#define DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \
162+ rc_tgt_off_low)
163+#define DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \
164+ rc_tgt_off_high)
165+#define DSC_PPS10_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)
166+#define DSC_PPS10_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)
167+
168+/* PPS 16 */
169+#define DSC_PPS16_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20)
170+#define DSC_PPS16_SLICE_PER_LINE_MASK REG_GENMASK(18, 16)
171+#define DSC_PPS16_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0)
172+#define DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \
173+ slice_row_per_frame)
174+#define DSC_PPS16_SLICE_PER_LINE(slice_per_line) REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \
175+ slice_per_line)
176+#define DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \
177+ slice_chunk_size)
178+
179+/* PPS 17 (MTL+) */
180+#define DSC_PPS17_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27)
181+#define DSC_PPS17_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset)
182+
183+/* PPS 18 (MTL+) */
184+#define DSC_PPS18_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16)
185+#define DSC_PPS18_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0)
186+#define DSC_PPS18_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)
187+#define DSC_PPS18_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)
333188
334189 /* Icelake Rate Control Buffer Threshold Registers */
335190 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
drivers/gpu/drm/i915/display/intel_vrr.c+16−2
@@ -42,6 +42,15 @@ bool intel_vrr_is_capable(struct intel_connector *connector) · 41 unmodified lines
4242 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
4343 }
4444
45+bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh)
46+{
47+ const struct drm_display_info *info = &connector->base.display_info;
48+
49+ return intel_vrr_is_capable(connector) &&
50+ vrefresh >= info->monitor_range.min_vfreq &&
51+ vrefresh <= info->monitor_range.max_vfreq;
52+}
53+
4554 void
4655 intel_vrr_check_modeset(struct intel_atomic_state *state)
4756 {
@@ -108,12 +117,17 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, · 60 unmodified lines
108117 const struct drm_display_info *info = &connector->base.display_info;
109118 int vmin, vmax;
110119
111− if (!intel_vrr_is_capable(connector))
120+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
112121 return;
113122
114− if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
123+ crtc_state->vrr.in_range =
124+ intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
125+ if (!crtc_state->vrr.in_range)
115126 return;
116127
128+ if (HAS_LRR(i915))
129+ crtc_state->update_lrr = true;
130+
117131 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
118132 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
119133 vmax = adjusted_mode->crtc_clock * 1000 /
drivers/gpu/drm/i915/display/intel_vrr.h+1−0
@@ -14,6 +14,7 @@ struct intel_connector; · 13 unmodified lines
1414 struct intel_crtc_state;
1515
1616 bool intel_vrr_is_capable(struct intel_connector *connector);
17+bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh);
1718 void intel_vrr_check_modeset(struct intel_atomic_state *state);
1819 void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
1920 struct drm_connector_state *conn_state);
drivers/gpu/drm/i915/display/skl_universal_plane.c+2−5
@@ -16,6 +16,7 @@ · 15 unmodified lines
1616 #include "intel_display_types.h"
1717 #include "intel_fb.h"
1818 #include "intel_fbc.h"
19+#include "intel_frontbuffer.h"
1920 #include "intel_psr.h"
2021 #include "skl_scaler.h"
2122 #include "skl_universal_plane.h"
@@ -1246,7 +1247,7 @@ icl_plane_update_noarm(struct intel_plane *plane, · 1224 unmodified lines
12461247 }
12471248
12481249 /* FLAT CCS doesn't need to program AUX_DIST */
1249− if (!HAS_FLAT_CCS(dev_priv))
1250+ if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
12501251 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
12511252 skl_plane_aux_dist(plane_state, color_plane));
12521253
@@ -2199,10 +2200,6 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, · 946 unmodified lines
21992200 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
22002201 return false;
22012202
2202− /* Wa_14013215631 */
2203− if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
2204− return false;
2205−
22062203 return plane_id < PLANE_SPRITE4;
22072204 }
22082205
drivers/gpu/drm/i915/display/skl_watermark.c+24−8
@@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state) · 1366 unmodified lines
13671367 u64 data_rate = 0;
13681368
13691369 for_each_plane_id_on_crtc(crtc, plane_id) {
1370− if (plane_id == PLANE_CURSOR)
1370+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
13711371 continue;
13721372
13731373 data_rate += crtc_state->rel_data_rate[plane_id];
@@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, · 140 unmodified lines
15141514 return 0;
15151515
15161516 /* Allocate fixed number of blocks for cursor. */
1517− cursor_size = skl_cursor_allocation(crtc_state, num_active);
1518− iter.size -= cursor_size;
1519− skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
1520− alloc->end - cursor_size, alloc->end);
1517+ if (DISPLAY_VER(i915) < 20) {
1518+ cursor_size = skl_cursor_allocation(crtc_state, num_active);
1519+ iter.size -= cursor_size;
1520+ skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
1521+ alloc->end - cursor_size, alloc->end);
1522+ }
15211523
15221524 iter.data_rate = skl_total_relative_data_rate(crtc_state);
15231525
@@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, · 7 unmodified lines
15311533 const struct skl_plane_wm *wm =
15321534 &crtc_state->wm.skl.optimal.planes[plane_id];
15331535
1534− if (plane_id == PLANE_CURSOR) {
1536+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
15351537 const struct skl_ddb_entry *ddb =
15361538 &crtc_state->wm.skl.plane_ddb[plane_id];
15371539
@@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, · 41 unmodified lines
15791581 const struct skl_plane_wm *wm =
15801582 &crtc_state->wm.skl.optimal.planes[plane_id];
15811583
1582− if (plane_id == PLANE_CURSOR)
1584+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
15831585 continue;
15841586
15851587 if (DISPLAY_VER(i915) < 11 &&
@@ -2616,7 +2618,7 @@ skl_compute_ddb(struct intel_atomic_state *state) · 1030 unmodified lines
26162618
26172619 if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
26182620 /* TODO: Implement vblank synchronized MBUS joining changes */
2619− ret = intel_modeset_all_pipes(state, "MBUS joining change");
2621+ ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
26202622 if (ret)
26212623 return ret;
26222624 }
@@ -3719,3 +3721,17 @@ void skl_watermark_debugfs_register(struct drm_i915_private *i915) · 1096 unmodified lines
37193721 debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, i915,
37203722 &intel_sagv_status_fops);
37213723 }
3724+
3725+unsigned int skl_watermark_max_latency(struct drm_i915_private *i915)
3726+{
3727+ int level;
3728+
3729+ for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
3730+ unsigned int latency = skl_wm_latency(i915, level, NULL);
3731+
3732+ if (latency)
3733+ return latency;
3734+ }
3735+
3736+ return 0;
3737+}
drivers/gpu/drm/i915/display/skl_watermark.h+2−0
@@ -46,6 +46,8 @@ void skl_watermark_ipc_update(struct drm_i915_private *i915); · 45 unmodified lines
4646 bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
4747 void skl_watermark_debugfs_register(struct drm_i915_private *i915);
4848
49+unsigned int skl_watermark_max_latency(struct drm_i915_private *i915);
50+
4951 void skl_wm_init(struct drm_i915_private *i915);
5052
5153 struct intel_dbuf_state {
drivers/gpu/drm/i915/gem/i915_gem_clflush.c+1−2
@@ -6,11 +6,10 @@ · 5 unmodified lines
66
77 #include <drm/drm_cache.h>
88
9−#include "display/intel_frontbuffer.h"
10−
119 #include "i915_config.h"
1210 #include "i915_drv.h"
1311 #include "i915_gem_clflush.h"
12+#include "i915_gem_object_frontbuffer.h"
1413 #include "i915_sw_fence_work.h"
1514 #include "i915_trace.h"
1615
drivers/gpu/drm/i915/gem/i915_gem_domain.c+1−1
@@ -5,7 +5,6 @@ · 4 unmodified lines
55 */
66
77 #include "display/intel_display.h"
8−#include "display/intel_frontbuffer.h"
98 #include "gt/intel_gt.h"
109
1110 #include "i915_drv.h"
@@ -16,6 +15,7 @@ · 4 unmodified lines
1615 #include "i915_gem_lmem.h"
1716 #include "i915_gem_mman.h"
1817 #include "i915_gem_object.h"
18+#include "i915_gem_object_frontbuffer.h"
1919 #include "i915_vma.h"
2020
2121 #define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+2−2
@@ -1436,7 +1436,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, · 1435 unmodified lines
14361436 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
14371437 drm_dbg(&i915->drm, "reloc with multiple write domains: "
14381438 "target %d offset %d "
1439− "read %08x write %08x",
1439+ "read %08x write %08x\n",
14401440 reloc->target_handle,
14411441 (int) reloc->offset,
14421442 reloc->read_domains,
@@ -1447,7 +1447,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, · 4 unmodified lines
14471447 & ~I915_GEM_GPU_DOMAINS)) {
14481448 drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: "
14491449 "target %d offset %d "
1450− "read %08x write %08x",
1450+ "read %08x write %08x\n",
14511451 reloc->target_handle,
14521452 (int) reloc->offset,
14531453 reloc->read_domains,
drivers/gpu/drm/i915/gem/i915_gem_object.c+1−0
@@ -37,6 +37,7 @@ · 36 unmodified lines
3737 #include "i915_gem_dmabuf.h"
3838 #include "i915_gem_mman.h"
3939 #include "i915_gem_object.h"
40+#include "i915_gem_object_frontbuffer.h"
4041 #include "i915_gem_ttm.h"
4142 #include "i915_memcpy.h"
4243 #include "i915_trace.h"
drivers/gpu/drm/i915/gem/i915_gem_object.h+0−89
@@ -11,7 +11,6 @@ · 10 unmodified lines
1111 #include <drm/drm_file.h>
1212 #include <drm/drm_device.h>
1313
14−#include "display/intel_frontbuffer.h"
1514 #include "intel_memory_region.h"
1615 #include "i915_gem_object_types.h"
1716 #include "i915_gem_gtt.h"
@@ -806,27 +805,6 @@ int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, · 788 unmodified lines
806805 unsigned int flags,
807806 const struct i915_sched_attr *attr);
808807
809−void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
810− enum fb_op_origin origin);
811−void __i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object *obj,
812− enum fb_op_origin origin);
813−
814−static inline void
815−i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
816− enum fb_op_origin origin)
817−{
818− if (unlikely(rcu_access_pointer(obj->frontbuffer)))
819− __i915_gem_object_flush_frontbuffer(obj, origin);
820−}
821−
822−static inline void
823−i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object *obj,
824− enum fb_op_origin origin)
825−{
826− if (unlikely(rcu_access_pointer(obj->frontbuffer)))
827− __i915_gem_object_invalidate_frontbuffer(obj, origin);
828−}
829−
830808 int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size);
831809
832810 bool i915_gem_object_is_shmem(const struct drm_i915_gem_object *obj);
@@ -887,71 +865,4 @@ static inline int i915_gem_object_userptr_validate(struct drm_i915_gem_object *o · 54 unmodified lines
887865
888866 #endif
889867
890−/**
891− * i915_gem_object_get_frontbuffer - Get the object's frontbuffer
892− * @obj: The object whose frontbuffer to get.
893− *
894− * Get pointer to object's frontbuffer if such exists. Please note that RCU
895− * mechanism is used to handle e.g. ongoing removal of frontbuffer pointer.
896− *
897− * Return: pointer to object's frontbuffer is such exists or NULL
898− */
899−static inline struct intel_frontbuffer *
900−i915_gem_object_get_frontbuffer(const struct drm_i915_gem_object *obj)
901−{
902− struct intel_frontbuffer *front;
903−
904− if (likely(!rcu_access_pointer(obj->frontbuffer)))
905− return NULL;
906−
907− rcu_read_lock();
908− do {
909− front = rcu_dereference(obj->frontbuffer);
910− if (!front)
911− break;
912−
913− if (unlikely(!kref_get_unless_zero(&front->ref)))
914− continue;
915−
916− if (likely(front == rcu_access_pointer(obj->frontbuffer)))
917− break;
918−
919− intel_frontbuffer_put(front);
920− } while (1);
921− rcu_read_unlock();
922−
923− return front;
924−}
925−
926−/**
927− * i915_gem_object_set_frontbuffer - Set the object's frontbuffer
928− * @obj: The object whose frontbuffer to set.
929− * @front: The frontbuffer to set
930− *
931− * Set object's frontbuffer pointer. If frontbuffer is already set for the
932− * object keep it and return it's pointer to the caller. Please note that RCU
933− * mechanism is used to handle e.g. ongoing removal of frontbuffer pointer. This
934− * function is protected by i915->display.fb_tracking.lock
935− *
936− * Return: pointer to frontbuffer which was set.
937− */
938−static inline struct intel_frontbuffer *
939−i915_gem_object_set_frontbuffer(struct drm_i915_gem_object *obj,
940− struct intel_frontbuffer *front)
941−{
942− struct intel_frontbuffer *cur = front;
943−
944− if (!front) {
945− RCU_INIT_POINTER(obj->frontbuffer, NULL);
946− } else if (rcu_access_pointer(obj->frontbuffer)) {
947− cur = rcu_dereference_protected(obj->frontbuffer, true);
948− kref_get(&cur->ref);
949− } else {
950− drm_gem_object_get(intel_bo_to_drm_bo(obj));
951− rcu_assign_pointer(obj->frontbuffer, front);
952− }
953−
954− return cur;
955−}
956−
957868 #endif
drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h+103−0
@@ -0,0 +1,103 @@
1+/* SPDX-License-Identifier: MIT */
2+/*
3+ * Copyright © 2023 Intel Corporation
4+ */
5+
6+#ifndef __I915_GEM_OBJECT_FRONTBUFFER_H__
7+#define __I915_GEM_OBJECT_FRONTBUFFER_H__
8+
9+#include <linux/kref.h>
10+#include <linux/rcupdate.h>
11+
12+#include "display/intel_frontbuffer.h"
13+#include "i915_gem_object_types.h"
14+
15+void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
16+ enum fb_op_origin origin);
17+void __i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object *obj,
18+ enum fb_op_origin origin);
19+
20+static inline void
21+i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
22+ enum fb_op_origin origin)
23+{
24+ if (unlikely(rcu_access_pointer(obj->frontbuffer)))
25+ __i915_gem_object_flush_frontbuffer(obj, origin);
26+}
27+
28+static inline void
29+i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object *obj,
30+ enum fb_op_origin origin)
31+{
32+ if (unlikely(rcu_access_pointer(obj->frontbuffer)))
33+ __i915_gem_object_invalidate_frontbuffer(obj, origin);
34+}
35+
36+/**
37+ * i915_gem_object_get_frontbuffer - Get the object's frontbuffer
38+ * @obj: The object whose frontbuffer to get.
39+ *
40+ * Get pointer to object's frontbuffer if such exists. Please note that RCU
41+ * mechanism is used to handle e.g. ongoing removal of frontbuffer pointer.
42+ *
43+ * Return: pointer to object's frontbuffer is such exists or NULL
44+ */
45+static inline struct intel_frontbuffer *
46+i915_gem_object_get_frontbuffer(const struct drm_i915_gem_object *obj)
47+{
48+ struct intel_frontbuffer *front;
49+
50+ if (likely(!rcu_access_pointer(obj->frontbuffer)))
51+ return NULL;
52+
53+ rcu_read_lock();
54+ do {
55+ front = rcu_dereference(obj->frontbuffer);
56+ if (!front)
57+ break;
58+
59+ if (unlikely(!kref_get_unless_zero(&front->ref)))
60+ continue;
61+
62+ if (likely(front == rcu_access_pointer(obj->frontbuffer)))
63+ break;
64+
65+ intel_frontbuffer_put(front);
66+ } while (1);
67+ rcu_read_unlock();
68+
69+ return front;
70+}
71+
72+/**
73+ * i915_gem_object_set_frontbuffer - Set the object's frontbuffer
74+ * @obj: The object whose frontbuffer to set.
75+ * @front: The frontbuffer to set
76+ *
77+ * Set object's frontbuffer pointer. If frontbuffer is already set for the
78+ * object keep it and return it's pointer to the caller. Please note that RCU
79+ * mechanism is used to handle e.g. ongoing removal of frontbuffer pointer. This
80+ * function is protected by i915->display.fb_tracking.lock
81+ *
82+ * Return: pointer to frontbuffer which was set.
83+ */
84+static inline struct intel_frontbuffer *
85+i915_gem_object_set_frontbuffer(struct drm_i915_gem_object *obj,
86+ struct intel_frontbuffer *front)
87+{
88+ struct intel_frontbuffer *cur = front;
89+
90+ if (!front) {
91+ RCU_INIT_POINTER(obj->frontbuffer, NULL);
92+ } else if (rcu_access_pointer(obj->frontbuffer)) {
93+ cur = rcu_dereference_protected(obj->frontbuffer, true);
94+ kref_get(&cur->ref);
95+ } else {
96+ drm_gem_object_get(intel_bo_to_drm_bo(obj));
97+ rcu_assign_pointer(obj->frontbuffer, front);
98+ }
99+
100+ return cur;
101+}
102+
103+#endif
drivers/gpu/drm/i915/gem/i915_gem_phys.c+1−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include "gt/intel_gt.h"
1414 #include "i915_drv.h"
1515 #include "i915_gem_object.h"
16+#include "i915_gem_object_frontbuffer.h"
1617 #include "i915_gem_region.h"
1718 #include "i915_gem_tiling.h"
1819 #include "i915_scatterlist.h"
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c+15−24
@@ -83,8 +83,7 @@ static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) · 82 unmodified lines
8383 enum client_tiling {
8484 CLIENT_TILING_LINEAR,
8585 CLIENT_TILING_X,
86− CLIENT_TILING_Y,
87− CLIENT_TILING_4,
86+ CLIENT_TILING_Y, /* Y-major, either Tile4 (Xe_HP and beyond) or legacy TileY */
8887 CLIENT_NUM_TILING_TYPES
8988 };
9089
@@ -165,11 +164,10 @@ static int prepare_blit(const struct tiled_blits *t, · 74 unmodified lines
165164 BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
166165
167166 src_pitch = t->width; /* in dwords */
168− if (src->tiling == CLIENT_TILING_4) {
169− src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
170− src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
171− } else if (src->tiling == CLIENT_TILING_Y) {
167+ if (src->tiling == CLIENT_TILING_Y) {
172168 src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
169+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
170+ src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
173171 } else if (src->tiling == CLIENT_TILING_X) {
174172 src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
175173 } else {
@@ -177,11 +175,10 @@ static int prepare_blit(const struct tiled_blits *t, · 1 unmodified line
177175 }
178176
179177 dst_pitch = t->width; /* in dwords */
180− if (dst->tiling == CLIENT_TILING_4) {
181− dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
182− dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
183− } else if (dst->tiling == CLIENT_TILING_Y) {
178+ if (dst->tiling == CLIENT_TILING_Y) {
184179 dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
180+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
181+ dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
185182 } else if (dst->tiling == CLIENT_TILING_X) {
186183 dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
187184 } else {
@@ -326,12 +323,6 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, · 138 unmodified lines
326323 t->buffers[i].vma = vma;
327324 t->buffers[i].tiling =
328325 i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
329−
330− /* Platforms support either TileY or Tile4, not both */
331− if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
332− t->buffers[i].tiling = CLIENT_TILING_4;
333− else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
334− t->buffers[i].tiling = CLIENT_TILING_Y;
335326 }
336327
337328 return 0;
@@ -367,18 +358,19 @@ static u64 tiled_offset(const struct intel_gt *gt, · 29 unmodified lines
367358
368359 y = div64_u64_rem(v, stride, &x);
369360
370− if (tiling == CLIENT_TILING_4) {
371− v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
372−
373− /* no swizzling for f-tiling */
374− swizzle = I915_BIT_6_SWIZZLE_NONE;
375− } else if (tiling == CLIENT_TILING_X) {
361+ if (tiling == CLIENT_TILING_X) {
376362 v = div64_u64_rem(y, 8, &y) * stride * 8;
377363 v += y * 512;
378364 v += div64_u64_rem(x, 512, &x) << 12;
379365 v += x;
380366
381367 swizzle = gt->ggtt->bit_6_swizzle_x;
368+ } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
369+ /* Y-major tiling layout is Tile4 for Xe_HP and beyond */
370+ v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
371+
372+ /* no swizzling for f-tiling */
373+ swizzle = I915_BIT_6_SWIZZLE_NONE;
382374 } else {
383375 const unsigned int ytile_span = 16;
384376 const unsigned int ytile_height = 512;
@@ -414,8 +406,7 @@ static const char *repr_tiling(enum client_tiling tiling) · 29 unmodified lines
414406 switch (tiling) {
415407 case CLIENT_TILING_LINEAR: return "linear";
416408 case CLIENT_TILING_X: return "X";
417− case CLIENT_TILING_Y: return "Y";
418− case CLIENT_TILING_4: return "F";
409+ case CLIENT_TILING_Y: return "Y / 4";
419410 default: return "unknown";
420411 }
421412 }
drivers/gpu/drm/i915/gt/gen8_ppgtt.c+18−18
@@ -242,9 +242,9 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm, · 241 unmodified lines
242242 GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT);
243243
244244 len = gen8_pd_range(start, end, lvl--, &idx);
245− DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
246− __func__, vm, lvl + 1, start, end,
247− idx, len, atomic_read(px_used(pd)));
245+ GTT_TRACE("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
246+ __func__, vm, lvl + 1, start, end,
247+ idx, len, atomic_read(px_used(pd)));
248248 GEM_BUG_ON(!len || len >= atomic_read(px_used(pd)));
249249
250250 do {
@@ -252,8 +252,8 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm, · 1 unmodified line
252252
253253 if (atomic_fetch_inc(&pt->used) >> gen8_pd_shift(1) &&
254254 gen8_pd_contains(start, end, lvl)) {
255− DBG("%s(%p):{ lvl:%d, idx:%d, start:%llx, end:%llx } removing pd\n",
256− __func__, vm, lvl + 1, idx, start, end);
255+ GTT_TRACE("%s(%p):{ lvl:%d, idx:%d, start:%llx, end:%llx } removing pd\n",
256+ __func__, vm, lvl + 1, idx, start, end);
257257 clear_pd_entry(pd, idx, scratch);
258258 __gen8_ppgtt_cleanup(vm, as_pd(pt), I915_PDES, lvl);
259259 start += (u64)I915_PDES << gen8_pd_shift(lvl);
@@ -270,10 +270,10 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm, · 10 unmodified lines
270270 u64 *vaddr;
271271
272272 count = gen8_pt_count(start, end);
273− DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d } removing pte\n",
274− __func__, vm, lvl, start, end,
275− gen8_pd_index(start, 0), count,
276− atomic_read(&pt->used));
273+ GTT_TRACE("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d } removing pte\n",
274+ __func__, vm, lvl, start, end,
275+ gen8_pd_index(start, 0), count,
276+ atomic_read(&pt->used));
277277 GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
278278
279279 num_ptes = count;
@@ -325,9 +325,9 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, · 45 unmodified lines
325325 GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT);
326326
327327 len = gen8_pd_range(*start, end, lvl--, &idx);
328− DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
329− __func__, vm, lvl + 1, *start, end,
330− idx, len, atomic_read(px_used(pd)));
328+ GTT_TRACE("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
329+ __func__, vm, lvl + 1, *start, end,
330+ idx, len, atomic_read(px_used(pd)));
331331 GEM_BUG_ON(!len || (idx + len - 1) >> gen8_pd_shift(1));
332332
333333 spin_lock(&pd->lock);
@@ -338,8 +338,8 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, · 4 unmodified lines
338338 if (!pt) {
339339 spin_unlock(&pd->lock);
340340
341− DBG("%s(%p):{ lvl:%d, idx:%d } allocating new tree\n",
342− __func__, vm, lvl + 1, idx);
341+ GTT_TRACE("%s(%p):{ lvl:%d, idx:%d } allocating new tree\n",
342+ __func__, vm, lvl + 1, idx);
343343
344344 pt = stash->pt[!!lvl];
345345 __i915_gem_object_pin_pages(pt->base);
@@ -369,10 +369,10 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, · 23 unmodified lines
369369 } else {
370370 unsigned int count = gen8_pt_count(*start, end);
371371
372− DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d } inserting pte\n",
373− __func__, vm, lvl, *start, end,
374− gen8_pd_index(*start, 0), count,
375− atomic_read(&pt->used));
372+ GTT_TRACE("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d } inserting pte\n",
373+ __func__, vm, lvl, *start, end,
374+ gen8_pd_index(*start, 0), count,
375+ atomic_read(&pt->used));
376376
377377 atomic_add(count, &pt->used);
378378 /* All other pdes may be simultaneously removed */
drivers/gpu/drm/i915/gt/intel_gtt.h+2−2
@@ -35,9 +35,9 @@ · 34 unmodified lines
3535 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
3636
3737 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT)
38−#define DBG(...) trace_printk(__VA_ARGS__)
38+#define GTT_TRACE(...) trace_printk(__VA_ARGS__)
3939 #else
40−#define DBG(...)
40+#define GTT_TRACE(...)
4141 #endif
4242
4343 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
drivers/gpu/drm/i915/i915_driver.c+5−5
@@ -183,6 +183,9 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) · 182 unmodified lines
183183 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
184184 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
185185 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
186+ pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
187+ pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
188+ pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
186189
187190 if (pre) {
188191 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
@@ -696,8 +699,6 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) · 507 unmodified lines
696699
697700 intel_device_info_print(INTEL_INFO(dev_priv),
698701 RUNTIME_INFO(dev_priv), &p);
699− intel_display_device_info_print(DISPLAY_INFO(dev_priv),
700− DISPLAY_RUNTIME_INFO(dev_priv), &p);
701702 i915_print_iommu_status(dev_priv, &p);
702703 for_each_gt(gt, dev_priv, i)
703704 intel_gt_info_print(&gt->info, &p);
@@ -732,6 +733,8 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) · 28 unmodified lines
732733 /* Set up device info and initial runtime info. */
733734 intel_device_info_driver_create(i915, pdev->device, match_info);
734735
736+ intel_display_device_probe(i915);
737+
735738 return i915;
736739 }
737740
@@ -1566,8 +1569,6 @@ static int intel_runtime_suspend(struct device *kdev) · 828 unmodified lines
15661569 if (root_pdev)
15671570 pci_d3cold_disable(root_pdev);
15681571
1569− rpm->suspended = true;
1570−
15711572 /*
15721573 * FIXME: We really should find a document that references the arguments
15731574 * used below!
@@ -1618,7 +1619,6 @@ static int intel_runtime_resume(struct device *kdev) · 44 unmodified lines
16181619 disable_rpm_wakeref_asserts(rpm);
16191620
16201621 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1621− rpm->suspended = false;
16221622
16231623 root_pdev = pcie_find_root_port(pdev);
16241624 if (root_pdev)
drivers/gpu/drm/i915/i915_driver.h+2−2
@@ -15,8 +15,8 @@ struct drm_printer; · 14 unmodified lines
1515
1616 #define DRIVER_NAME "i915"
1717 #define DRIVER_DESC "Intel Graphics"
18−#define DRIVER_DATE "20201103"
19−#define DRIVER_TIMESTAMP 1604406085
18+#define DRIVER_DATE "20230929"
19+#define DRIVER_TIMESTAMP 1695980603
2020
2121 extern const struct dev_pm_ops i915_pm_ops;
2222
drivers/gpu/drm/i915/i915_drv.h+2−16
@@ -437,6 +437,8 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) · 436 unmodified lines
437437 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
438438
439439 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
440+#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
441+ DISPLAY_RUNTIME_INFO(i915)->ip.rel)
440442 #define IS_DISPLAY_VER(i915, from, until) \
441443 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
442444
@@ -644,24 +646,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 201 unmodified lines
644646 #define IS_TIGERLAKE_UY(i915) \
645647 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
646648
647−
648−
649−
650−
651−
652−
653−
654649 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
655650 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
656651
657−#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
658− (IS_METEORLAKE(__i915) && \
659− IS_DISPLAY_STEP(__i915, since, until))
660−
661−#define IS_DG2_DISPLAY_STEP(__i915, since, until) \
662− (IS_DG2(__i915) && \
663− IS_DISPLAY_STEP(__i915, since, until))
664−
665652 #define IS_PVC_BD_STEP(__i915, since, until) \
666653 (IS_PONTEVECCHIO(__i915) && \
667654 IS_BASEDIE_STEP(__i915, since, until))
@@ -706,7 +693,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 38 unmodified lines
706693 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
707694
708695 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
709−#define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile)
710696 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
711697 #define HAS_EDRAM(i915) ((i915)->edram_size_mb)
712698 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
drivers/gpu/drm/i915/i915_gem.c+1−1
@@ -40,12 +40,12 @@ · 39 unmodified lines
4040 #include <drm/drm_vma_manager.h>
4141
4242 #include "display/intel_display.h"
43−#include "display/intel_frontbuffer.h"
4443
4544 #include "gem/i915_gem_clflush.h"
4645 #include "gem/i915_gem_context.h"
4746 #include "gem/i915_gem_ioctls.h"
4847 #include "gem/i915_gem_mman.h"
48+#include "gem/i915_gem_object_frontbuffer.h"
4949 #include "gem/i915_gem_pm.h"
5050 #include "gem/i915_gem_region.h"
5151 #include "gem/i915_gem_userptr.h"
drivers/gpu/drm/i915/i915_getparam.c+1−1
@@ -109,7 +109,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, · 108 unmodified lines
109109 return value;
110110 break;
111111 case I915_PARAM_PXP_STATUS:
112− value = intel_pxp_get_readiness_status(i915->pxp);
112+ value = intel_pxp_get_readiness_status(i915->pxp, 0);
113113 if (value < 0)
114114 return value;
115115 break;
drivers/gpu/drm/i915/i915_gpu_error.c+2−2
@@ -1757,7 +1757,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt) · 1756 unmodified lines
17571757 struct intel_uncore *uncore = gt->_gt->uncore;
17581758 struct drm_i915_private *i915 = uncore->i915;
17591759
1760− if (GRAPHICS_VER(i915) >= 6)
1760+ if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
17611761 gt->derrmr = intel_uncore_read(uncore, DERRMR);
17621762
17631763 if (GRAPHICS_VER(i915) >= 8)
@@ -1972,7 +1972,7 @@ static void capture_gen(struct i915_gpu_coredump *error) · 208 unmodified lines
19721972 struct drm_i915_private *i915 = error->i915;
19731973
19741974 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1975− error->suspended = i915->runtime_pm.suspended;
1975+ error->suspended = pm_runtime_suspended(i915->drm.dev);
19761976
19771977 error->iommu = i915_vtd_active(i915);
19781978 error->reset_count = i915_reset_count(&i915->gpu_error);
drivers/gpu/drm/i915/i915_irq.c+2−0
@@ -751,6 +751,8 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv) · 750 unmodified lines
751751
752752 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
753753 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
754+
755+ intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0);
754756 }
755757
756758 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
drivers/gpu/drm/i915/i915_pci.c+0−1
@@ -713,7 +713,6 @@ static const struct intel_device_info adl_p_info = { · 712 unmodified lines
713713 .has_3d_pipeline = 1, \
714714 .has_64bit_reloc = 1, \
715715 .has_flat_ccs = 1, \
716− .has_4tile = 1, \
717716 .has_global_mocs = 1, \
718717 .has_gt_uc = 1, \
719718 .has_llc = 1, \
drivers/gpu/drm/i915/i915_reg.h+4−277
@@ -2693,13 +2693,6 @@ · 2692 unmodified lines
26932693 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
26942694 #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
26952695
2696−/* Skylake+ pipe bottom (background) color */
2697−#define _SKL_BOTTOM_COLOR_A 0x70034
2698−#define _SKL_BOTTOM_COLOR_B 0x71034
2699−#define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
2700−#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
2701−#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
2702−
27032696 #define _ICL_PIPE_A_STATUS 0x70058
27042697 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
27052698 #define PIPE_STATUS_UNDERRUN REG_BIT(31)
@@ -4213,45 +4206,6 @@ · 1507 unmodified lines
42134206 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
42144207 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
42154208 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
4216−/* legacy palette */
4217−#define _LGC_PALETTE_A 0x4a000
4218−#define _LGC_PALETTE_B 0x4a800
4219−/* see PALETTE_* for the bits */
4220−#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
4221−
4222−/* ilk/snb precision palette */
4223−#define _PREC_PALETTE_A 0x4b000
4224−#define _PREC_PALETTE_B 0x4c000
4225−/* 10bit mode */
4226−#define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20)
4227−#define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10)
4228−#define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0)
4229−/* 12.4 interpolated mode ldw */
4230−#define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24)
4231−#define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14)
4232−#define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4)
4233−/* 12.4 interpolated mode udw */
4234−#define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20)
4235−#define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10)
4236−#define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0)
4237−#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
4238−
4239−#define _PREC_PIPEAGCMAX 0x4d000
4240−#define _PREC_PIPEBGCMAX 0x4d010
4241−#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */
4242−
4243−#define _GAMMA_MODE_A 0x4a480
4244−#define _GAMMA_MODE_B 0x4ac80
4245−#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4246−#define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */
4247−#define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */
4248−#define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */
4249−#define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0)
4250−#define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0)
4251−#define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1)
4252−#define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2)
4253−#define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */
4254−#define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */
42554209
42564210 /* Display Internal Timeout Register */
42574211 #define RM_TIMEOUT _MMIO(0x42060)
@@ -4513,13 +4467,12 @@ · 255 unmodified lines
45134467 #define PICAINTERRUPT_IMR _MMIO(0x16FE54)
45144468 #define PICAINTERRUPT_IIR _MMIO(0x16FE58)
45154469 #define PICAINTERRUPT_IER _MMIO(0x16FE5C)
4516−
45174470 #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
45184471 #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
4519−
45204472 #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
45214473 #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
4522−
4474+#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
4475+#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
45234476 #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
45244477 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
45254478
@@ -5929,6 +5882,7 @@ enum skl_power_gate { · 1403 unmodified lines
59295882 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
59305883 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
59315884 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
5885+#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_BIT(25)
59325886 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
59335887 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
59345888 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
@@ -6269,179 +6223,6 @@ enum skl_power_gate { · 334 unmodified lines
62696223 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
62706224 #define WM_DBG_DISALLOW_SPRITE (1 << 2)
62716225
6272−/* pipe CSC */
6273−#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
6274−#define _PIPE_A_CSC_COEFF_BY 0x49014
6275−#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
6276−#define _PIPE_A_CSC_COEFF_BU 0x4901c
6277−#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
6278−#define _PIPE_A_CSC_COEFF_BV 0x49024
6279−
6280−#define _PIPE_A_CSC_MODE 0x49028
6281−#define ICL_CSC_ENABLE (1 << 31) /* icl+ */
6282−#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
6283−#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
6284−#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
6285−#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
6286−
6287−#define _PIPE_A_CSC_PREOFF_HI 0x49030
6288−#define _PIPE_A_CSC_PREOFF_ME 0x49034
6289−#define _PIPE_A_CSC_PREOFF_LO 0x49038
6290−#define _PIPE_A_CSC_POSTOFF_HI 0x49040
6291−#define _PIPE_A_CSC_POSTOFF_ME 0x49044
6292−#define _PIPE_A_CSC_POSTOFF_LO 0x49048
6293−
6294−#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
6295−#define _PIPE_B_CSC_COEFF_BY 0x49114
6296−#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
6297−#define _PIPE_B_CSC_COEFF_BU 0x4911c
6298−#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
6299−#define _PIPE_B_CSC_COEFF_BV 0x49124
6300−#define _PIPE_B_CSC_MODE 0x49128
6301−#define _PIPE_B_CSC_PREOFF_HI 0x49130
6302−#define _PIPE_B_CSC_PREOFF_ME 0x49134
6303−#define _PIPE_B_CSC_PREOFF_LO 0x49138
6304−#define _PIPE_B_CSC_POSTOFF_HI 0x49140
6305−#define _PIPE_B_CSC_POSTOFF_ME 0x49144
6306−#define _PIPE_B_CSC_POSTOFF_LO 0x49148
6307−
6308−#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
6309−#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
6310−#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
6311−#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
6312−#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
6313−#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
6314−#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
6315−#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
6316−#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
6317−#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
6318−#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
6319−#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
6320−#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
6321−
6322−/* Pipe Output CSC */
6323−#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
6324−#define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
6325−#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
6326−#define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
6327−#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
6328−#define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
6329−#define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
6330−#define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
6331−#define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
6332−#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
6333−#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
6334−#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
6335−
6336−#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
6337−#define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
6338−#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
6339−#define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
6340−#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
6341−#define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
6342−#define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
6343−#define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
6344−#define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
6345−#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
6346−#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
6347−#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
6348−
6349−#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
6350− _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
6351− _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
6352−#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
6353− _PIPE_A_OUTPUT_CSC_COEFF_BY, \
6354− _PIPE_B_OUTPUT_CSC_COEFF_BY)
6355−#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
6356− _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
6357− _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
6358−#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
6359− _PIPE_A_OUTPUT_CSC_COEFF_BU, \
6360− _PIPE_B_OUTPUT_CSC_COEFF_BU)
6361−#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
6362− _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
6363− _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
6364−#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
6365− _PIPE_A_OUTPUT_CSC_COEFF_BV, \
6366− _PIPE_B_OUTPUT_CSC_COEFF_BV)
6367−#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
6368− _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
6369− _PIPE_B_OUTPUT_CSC_PREOFF_HI)
6370−#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
6371− _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
6372− _PIPE_B_OUTPUT_CSC_PREOFF_ME)
6373−#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
6374− _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
6375− _PIPE_B_OUTPUT_CSC_PREOFF_LO)
6376−#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
6377− _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
6378− _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
6379−#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
6380− _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
6381− _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
6382−#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
6383− _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
6384− _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
6385−
6386−/* pipe degamma/gamma LUTs on IVB+ */
6387−#define _PAL_PREC_INDEX_A 0x4A400
6388−#define _PAL_PREC_INDEX_B 0x4AC00
6389−#define _PAL_PREC_INDEX_C 0x4B400
6390−#define PAL_PREC_SPLIT_MODE REG_BIT(31)
6391−#define PAL_PREC_AUTO_INCREMENT REG_BIT(15)
6392−#define PAL_PREC_INDEX_VALUE_MASK REG_GENMASK(9, 0)
6393−#define PAL_PREC_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_INDEX_VALUE_MASK, (x))
6394−#define _PAL_PREC_DATA_A 0x4A404
6395−#define _PAL_PREC_DATA_B 0x4AC04
6396−#define _PAL_PREC_DATA_C 0x4B404
6397−/* see PREC_PALETTE_* for the bits */
6398−#define _PAL_PREC_GC_MAX_A 0x4A410
6399−#define _PAL_PREC_GC_MAX_B 0x4AC10
6400−#define _PAL_PREC_GC_MAX_C 0x4B410
6401−#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
6402−#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
6403−#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
6404−#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
6405−#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
6406−#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
6407−
6408−#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
6409−#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
6410−#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */
6411−#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */
6412−#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */
6413−
6414−#define _PRE_CSC_GAMC_INDEX_A 0x4A484
6415−#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
6416−#define _PRE_CSC_GAMC_INDEX_C 0x4B484
6417−#define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10)
6418−#define PRE_CSC_GAMC_INDEX_VALUE_MASK REG_GENMASK(7, 0)
6419−#define PRE_CSC_GAMC_INDEX_VALUE(x) REG_FIELD_PREP(PRE_CSC_GAMC_INDEX_VALUE_MASK, (x))
6420−#define _PRE_CSC_GAMC_DATA_A 0x4A488
6421−#define _PRE_CSC_GAMC_DATA_B 0x4AC88
6422−#define _PRE_CSC_GAMC_DATA_C 0x4B488
6423−
6424−#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
6425−#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
6426−
6427−/* ICL Multi segmented gamma */
6428−#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
6429−#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
6430−#define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15)
6431−#define PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK REG_GENMASK(4, 0)
6432−#define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x))
6433−
6434−#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
6435−#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
6436−/* see PREC_PALETTE_12P4_* for the bits */
6437−
6438−#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
6439− _PAL_PREC_MULTI_SEG_INDEX_A, \
6440− _PAL_PREC_MULTI_SEG_INDEX_B)
6441−#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
6442− _PAL_PREC_MULTI_SEG_DATA_A, \
6443− _PAL_PREC_MULTI_SEG_DATA_B)
6444−
64456226 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
64466227
64476228 /* Plane CSC Registers */
@@ -6487,61 +6268,6 @@ enum skl_power_gate { · 39 unmodified lines
64876268 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
64886269 (index) * 4)
64896270
6490−#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */
6491−#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */
6492−#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */
6493−#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */
6494−#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */
6495−#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */
6496−
6497−#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00)
6498−#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)
6499−#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10)
6500−#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)
6501−#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20)
6502−#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)
6503−
6504−/* pipe CSC & degamma/gamma LUTs on CHV */
6505−#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
6506−#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
6507−#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
6508−#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
6509−#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
6510−#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
6511−/* cgm degamma ldw */
6512−#define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16)
6513−#define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0)
6514−/* cgm degamma udw */
6515−#define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0)
6516−#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
6517−/* cgm gamma ldw */
6518−#define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16)
6519−#define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0)
6520−/* cgm gamma udw */
6521−#define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0)
6522−#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
6523−#define CGM_PIPE_MODE_GAMMA (1 << 2)
6524−#define CGM_PIPE_MODE_CSC (1 << 1)
6525−#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
6526−
6527−#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
6528−#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
6529−#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
6530−#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
6531−#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
6532−#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
6533−#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
6534−#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
6535−
6536−#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
6537−#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
6538−#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
6539−#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
6540−#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
6541−#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
6542−#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
6543−#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
6544−
65456271 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
65466272 #define GEN4_TIMESTAMP _MMIO(0x2358)
65476273 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
@@ -6624,6 +6350,7 @@ enum skl_power_gate { · 76 unmodified lines
66246350 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
66256351 _TCSS_DDI_STATUS_1, \
66266352 _TCSS_DDI_STATUS_2))
6353+#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
66276354 #define TCSS_DDI_STATUS_READY REG_BIT(2)
66286355 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
66296356 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
drivers/gpu/drm/i915/i915_vma.c+1−0
@@ -29,6 +29,7 @@ · 28 unmodified lines
2929 #include "display/intel_display.h"
3030 #include "display/intel_frontbuffer.h"
3131 #include "gem/i915_gem_lmem.h"
32+#include "gem/i915_gem_object_frontbuffer.h"
3233 #include "gem/i915_gem_tiling.h"
3334 #include "gt/intel_engine.h"
3435 #include "gt/intel_engine_heartbeat.h"
drivers/gpu/drm/i915/i915_vma_resource.c+1−1
@@ -94,7 +94,7 @@ static void unbind_fence_release(struct dma_fence *fence) · 93 unmodified lines
9494 call_rcu(&fence->rcu, unbind_fence_free_rcu);
9595 }
9696
97−static struct dma_fence_ops unbind_fence_ops = {
97+static const struct dma_fence_ops unbind_fence_ops = {
9898 .get_driver_name = get_driver_name,
9999 .get_timeline_name = get_timeline_name,
100100 .release = unbind_fence_release,
drivers/gpu/drm/i915/intel_clock_gating.c+2−50
@@ -349,41 +349,6 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, · 348 unmodified lines
349349 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
350350 }
351351
352−static void icl_init_clock_gating(struct drm_i915_private *i915)
353−{
354− /* Wa_1409120013:icl,ehl */
355− intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
356− DPFC_CHICKEN_COMP_DUMMY_PIXEL);
357−
358− /*Wa_14010594013:icl, ehl */
359− intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1,
360− 0, ICL_DELAY_PMRSP);
361−}
362−
363−static void gen12lp_init_clock_gating(struct drm_i915_private *i915)
364−{
365− /* Wa_1409120013 */
366− if (DISPLAY_VER(i915) == 12)
367− intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
368− DPFC_CHICKEN_COMP_DUMMY_PIXEL);
369−
370− /* Wa_14013723622:tgl,rkl,dg1,adl-s */
371− if (DISPLAY_VER(i915) == 12)
372− intel_uncore_rmw(&i915->uncore, CLKREQ_POLICY,
373− CLKREQ_POLICY_MEM_UP_OVRD, 0);
374−}
375−
376−static void adlp_init_clock_gating(struct drm_i915_private *i915)
377−{
378− gen12lp_init_clock_gating(i915);
379−
380− /* Wa_22011091694:adlp */
381− intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
382−
383− /* Bspec/49189 Initialize Sequence */
384− intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
385−}
386−
387352 static void xehpsdv_init_clock_gating(struct drm_i915_private *i915)
388353 {
389354 /* Wa_22010146351:xehpsdv */
@@ -800,9 +765,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = · 410 unmodified lines
800765 CG_FUNCS(pvc);
801766 CG_FUNCS(dg2);
802767 CG_FUNCS(xehpsdv);
803−CG_FUNCS(adlp);
804−CG_FUNCS(gen12lp);
805−CG_FUNCS(icl);
806768 CG_FUNCS(cfl);
807769 CG_FUNCS(skl);
808770 CG_FUNCS(kbl);
@@ -835,20 +797,12 @@ CG_FUNCS(nop); · 26 unmodified lines
835797 */
836798 void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
837799 {
838− if (IS_METEORLAKE(i915))
839− i915->clock_gating_funcs = &nop_clock_gating_funcs;
840− else if (IS_PONTEVECCHIO(i915))
800+ if (IS_PONTEVECCHIO(i915))
841801 i915->clock_gating_funcs = &pvc_clock_gating_funcs;
842802 else if (IS_DG2(i915))
843803 i915->clock_gating_funcs = &dg2_clock_gating_funcs;
844804 else if (IS_XEHPSDV(i915))
845805 i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
846− else if (IS_ALDERLAKE_P(i915))
847− i915->clock_gating_funcs = &adlp_clock_gating_funcs;
848− else if (GRAPHICS_VER(i915) == 12)
849− i915->clock_gating_funcs = &gen12lp_clock_gating_funcs;
850− else if (GRAPHICS_VER(i915) == 11)
851− i915->clock_gating_funcs = &icl_clock_gating_funcs;
852806 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
853807 i915->clock_gating_funcs = &cfl_clock_gating_funcs;
854808 else if (IS_SKYLAKE(i915))
@@ -885,8 +839,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915) · 30 unmodified lines
885839 i915->clock_gating_funcs = &i85x_clock_gating_funcs;
886840 else if (GRAPHICS_VER(i915) == 2)
887841 i915->clock_gating_funcs = &i830_clock_gating_funcs;
888− else {
889− MISSING_CASE(INTEL_DEVID(i915));
842+ else
890843 i915->clock_gating_funcs = &nop_clock_gating_funcs;
891− }
892844 }
drivers/gpu/drm/i915/intel_device_info.c+0−14
@@ -410,7 +410,6 @@ void intel_device_info_driver_create(struct drm_i915_private *i915, · 409 unmodified lines
410410 const struct intel_device_info *match_info)
411411 {
412412 struct intel_runtime_info *runtime;
413− u16 ver, rel, step;
414413
415414 /* Setup INTEL_INFO() */
416415 i915->__info = match_info;
@@ -419,19 +418,6 @@ void intel_device_info_driver_create(struct drm_i915_private *i915, · 2 unmodified lines
419418 runtime = RUNTIME_INFO(i915);
420419 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
421420
422− /* Probe display support */
423− i915->display.info.__device_info = intel_display_device_probe(i915, HAS_GMD_ID(i915),
424− &ver, &rel, &step);
425− memcpy(DISPLAY_RUNTIME_INFO(i915),
426− &DISPLAY_INFO(i915)->__runtime_defaults,
427− sizeof(*DISPLAY_RUNTIME_INFO(i915)));
428−
429− if (HAS_GMD_ID(i915)) {
430− DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
431− DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
432− DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
433− }
434−
435421 runtime->device_id = device_id;
436422 }
437423
drivers/gpu/drm/i915/intel_device_info.h+0−1
@@ -146,7 +146,6 @@ enum intel_ppgtt_type { · 145 unmodified lines
146146 func(gpu_reset_clobbers_display); \
147147 func(has_reset_engine); \
148148 func(has_3d_pipeline); \
149− func(has_4tile); \
150149 func(has_flat_ccs); \
151150 func(has_global_mocs); \
152151 func(has_gmd_id); \
drivers/gpu/drm/i915/intel_gvt_mmio_table.c+1−0
@@ -5,6 +5,7 @@ · 4 unmodified lines
55
66 #include "display/intel_audio_regs.h"
77 #include "display/intel_backlight_regs.h"
8+#include "display/intel_color_regs.h"
89 #include "display/intel_display_types.h"
910 #include "display/intel_dmc_regs.h"
1011 #include "display/intel_dp_aux_regs.h"
drivers/gpu/drm/i915/intel_runtime_pm.c+0−1
@@ -652,7 +652,6 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm *rpm) · 651 unmodified lines
652652
653653 rpm->kdev = kdev;
654654 rpm->available = HAS_RUNTIME_PM(i915);
655− rpm->suspended = false;
656655 atomic_set(&rpm->wakeref_count, 0);
657656
658657 init_intel_runtime_pm_wakeref(rpm);
drivers/gpu/drm/i915/intel_runtime_pm.h+2−2
@@ -6,6 +6,7 @@ · 5 unmodified lines
66 #ifndef __INTEL_RUNTIME_PM_H__
77 #define __INTEL_RUNTIME_PM_H__
88
9+#include <linux/pm_runtime.h>
910 #include <linux/types.h>
1011
1112 #include "intel_wakeref.h"
@@ -43,7 +44,6 @@ struct intel_runtime_pm { · 31 unmodified lines
4344 atomic_t wakeref_count;
4445 struct device *kdev; /* points to i915->drm.dev */
4546 bool available;
46− bool suspended;
4747 bool irqs_enabled;
4848 bool no_wakeref_tracking;
4949
@@ -110,7 +110,7 @@ intel_rpm_wakelock_count(int wakeref_count) · 60 unmodified lines
110110 static inline void
111111 assert_rpm_device_not_suspended(struct intel_runtime_pm *rpm)
112112 {
113− WARN_ONCE(rpm->suspended,
113+ WARN_ONCE(pm_runtime_suspended(rpm->kdev),
114114 "Device suspended during HW access\n");
115115 }
116116
drivers/gpu/drm/i915/intel_step.c+1−0
@@ -124,6 +124,7 @@ static const struct intel_step_info dg2_g11_revid_step_tbl[] = { · 123 unmodified lines
124124
125125 static const struct intel_step_info dg2_g12_revid_step_tbl[] = {
126126 [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 },
127+ [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_C0 },
127128 };
128129
129130 static const struct intel_step_info adls_rpls_revids[] = {
drivers/gpu/drm/i915/pxp/intel_pxp.c+33−7
@@ -359,22 +359,46 @@ void intel_pxp_end(struct intel_pxp *pxp) · 358 unmodified lines
359359 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
360360 }
361361
362+static bool pxp_required_fw_failed(struct intel_pxp *pxp)
363+{
364+ if (__intel_uc_fw_status(&pxp->ctrl_gt->uc.huc.fw) == INTEL_UC_FIRMWARE_LOAD_FAIL)
365+ return true;
366+ if (HAS_ENGINE(pxp->ctrl_gt, GSC0) &&
367+ __intel_uc_fw_status(&pxp->ctrl_gt->uc.gsc.fw) == INTEL_UC_FIRMWARE_LOAD_FAIL)
368+ return true;
369+
370+ return false;
371+}
372+
373+static bool pxp_fw_dependencies_completed(struct intel_pxp *pxp)
374+{
375+ if (HAS_ENGINE(pxp->ctrl_gt, GSC0))
376+ return intel_pxp_gsccs_is_ready_for_sessions(pxp);
377+
378+ return pxp_component_bound(pxp);
379+}
380+
362381 /*
363382 * this helper is used by both intel_pxp_start and by
364383 * the GET_PARAM IOCTL that user space calls. Thus, the
365384 * return values here should match the UAPI spec.
366385 */
367−int intel_pxp_get_readiness_status(struct intel_pxp *pxp)
386+int intel_pxp_get_readiness_status(struct intel_pxp *pxp, int timeout_ms)
368387 {
369388 if (!intel_pxp_is_enabled(pxp))
370389 return -ENODEV;
371390
372− if (HAS_ENGINE(pxp->ctrl_gt, GSC0)) {
373− if (wait_for(intel_pxp_gsccs_is_ready_for_sessions(pxp), 250))
374− return 2;
375− } else {
376− if (wait_for(pxp_component_bound(pxp), 250))
391+ if (pxp_required_fw_failed(pxp))
392+ return -ENODEV;
393+
394+ if (pxp->platform_cfg_is_bad)
395+ return -ENODEV;
396+
397+ if (timeout_ms) {
398+ if (wait_for(pxp_fw_dependencies_completed(pxp), timeout_ms))
377399 return 2;
400+ } else if (!pxp_fw_dependencies_completed(pxp)) {
401+ return 2;
378402 }
379403 return 1;
380404 }
@@ -383,11 +407,13 @@ int intel_pxp_get_readiness_status(struct intel_pxp *pxp) · 2 unmodified lines
383407 * the arb session is restarted from the irq work when we receive the
384408 * termination completion interrupt
385409 */
410+#define PXP_READINESS_TIMEOUT 250
411+
386412 int intel_pxp_start(struct intel_pxp *pxp)
387413 {
388414 int ret = 0;
389415
390− ret = intel_pxp_get_readiness_status(pxp);
416+ ret = intel_pxp_get_readiness_status(pxp, PXP_READINESS_TIMEOUT);
391417 if (ret < 0)
392418 return ret;
393419 else if (ret > 1)
drivers/gpu/drm/i915/pxp/intel_pxp.h+1−1
@@ -26,7 +26,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp); · 25 unmodified lines
2626 void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
2727 void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id);
2828
29−int intel_pxp_get_readiness_status(struct intel_pxp *pxp);
29+int intel_pxp_get_readiness_status(struct intel_pxp *pxp, int timeout_ms);
3030 int intel_pxp_get_backend_timeout_ms(struct intel_pxp *pxp);
3131 int intel_pxp_start(struct intel_pxp *pxp);
3232 void intel_pxp_end(struct intel_pxp *pxp);
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c+4−3
@@ -18,12 +18,13 @@ · 17 unmodified lines
1818 #include "intel_pxp_types.h"
1919
2020 static bool
21−is_fw_err_platform_config(u32 type)
21+is_fw_err_platform_config(struct intel_pxp *pxp, u32 type)
2222 {
2323 switch (type) {
2424 case PXP_STATUS_ERROR_API_VERSION:
2525 case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF:
2626 case PXP_STATUS_PLATFCONFIG_KF1_BAD:
27+ pxp->platform_cfg_is_bad = true;
2728 return true;
2829 default:
2930 break;
@@ -226,7 +227,7 @@ int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, · 196 unmodified lines
226227 if (ret) {
227228 drm_err(&i915->drm, "Failed to init session %d, ret=[%d]\n", arb_session_id, ret);
228229 } else if (msg_out.header.status != 0) {
229− if (is_fw_err_platform_config(msg_out.header.status)) {
230+ if (is_fw_err_platform_config(pxp, msg_out.header.status)) {
230231 drm_info_once(&i915->drm,
231232 "PXP init-session-%d failed due to BIOS/SOC:0x%08x:%s\n",
232233 arb_session_id, msg_out.header.status,
@@ -269,7 +270,7 @@ void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 session_id) · 36 unmodified lines
269270 drm_err(&i915->drm, "Failed to inv-stream-key-%u, ret=[%d]\n",
270271 session_id, ret);
271272 } else if (msg_out.header.status != 0) {
272− if (is_fw_err_platform_config(msg_out.header.status)) {
273+ if (is_fw_err_platform_config(pxp, msg_out.header.status)) {
273274 drm_info_once(&i915->drm,
274275 "PXP inv-stream-key-%u failed due to BIOS/SOC :0x%08x:%s\n",
275276 session_id, msg_out.header.status,
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c+17−1
@@ -34,8 +34,10 @@ void intel_pxp_suspend(struct intel_pxp *pxp) · 33 unmodified lines
3434 }
3535 }
3636
37−void intel_pxp_resume_complete(struct intel_pxp *pxp)
37+static void _pxp_resume(struct intel_pxp *pxp, bool take_wakeref)
3838 {
39+ intel_wakeref_t wakeref;
40+
3941 if (!intel_pxp_is_enabled(pxp))
4042 return;
4143
@@ -48,7 +50,21 @@ void intel_pxp_resume_complete(struct intel_pxp *pxp) · 6 unmodified lines
4850 if (!HAS_ENGINE(pxp->ctrl_gt, GSC0) && !pxp->pxp_component)
4951 return;
5052
53+ if (take_wakeref)
54+ wakeref = intel_runtime_pm_get(&pxp->ctrl_gt->i915->runtime_pm);
5155 intel_pxp_init_hw(pxp);
56+ if (take_wakeref)
57+ intel_runtime_pm_put(&pxp->ctrl_gt->i915->runtime_pm, wakeref);
58+}
59+
60+void intel_pxp_resume_complete(struct intel_pxp *pxp)
61+{
62+ _pxp_resume(pxp, true);
63+}
64+
65+void intel_pxp_runtime_resume(struct intel_pxp *pxp)
66+{
67+ _pxp_resume(pxp, false);
5268 }
5369
5470 void intel_pxp_runtime_suspend(struct intel_pxp *pxp)
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h+3−2
@@ -13,6 +13,7 @@ void intel_pxp_suspend_prepare(struct intel_pxp *pxp); · 12 unmodified lines
1313 void intel_pxp_suspend(struct intel_pxp *pxp);
1414 void intel_pxp_resume_complete(struct intel_pxp *pxp);
1515 void intel_pxp_runtime_suspend(struct intel_pxp *pxp);
16+void intel_pxp_runtime_resume(struct intel_pxp *pxp);
1617 #else
1718 static inline void intel_pxp_suspend_prepare(struct intel_pxp *pxp)
1819 {
@@ -29,9 +30,9 @@ static inline void intel_pxp_resume_complete(struct intel_pxp *pxp) · 10 unmodified lines
2930 static inline void intel_pxp_runtime_suspend(struct intel_pxp *pxp)
3031 {
3132 }
32−#endif
33+
3334 static inline void intel_pxp_runtime_resume(struct intel_pxp *pxp)
3435 {
35− intel_pxp_resume_complete(pxp);
3636 }
37+#endif
3738 #endif /* __INTEL_PXP_PM_H__ */
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c+4−3
@@ -22,12 +22,13 @@ · 21 unmodified lines
2222 #include "intel_pxp_types.h"
2323
2424 static bool
25−is_fw_err_platform_config(u32 type)
25+is_fw_err_platform_config(struct intel_pxp *pxp, u32 type)
2626 {
2727 switch (type) {
2828 case PXP_STATUS_ERROR_API_VERSION:
2929 case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF:
3030 case PXP_STATUS_PLATFCONFIG_KF1_BAD:
31+ pxp->platform_cfg_is_bad = true;
3132 return true;
3233 default:
3334 break;
@@ -344,7 +345,7 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, · 310 unmodified lines
344345 if (ret) {
345346 drm_err(&i915->drm, "Failed to send tee msg init arb session, ret=[%d]\n", ret);
346347 } else if (msg_out.header.status != 0) {
347− if (is_fw_err_platform_config(msg_out.header.status)) {
348+ if (is_fw_err_platform_config(pxp, msg_out.header.status)) {
348349 drm_info_once(&i915->drm,
349350 "PXP init-arb-session-%d failed due to BIOS/SOC:0x%08x:%s\n",
350351 arb_session_id, msg_out.header.status,
@@ -392,7 +393,7 @@ try_again: · 41 unmodified lines
392393 drm_err(&i915->drm, "Failed to send tee msg for inv-stream-key-%u, ret=[%d]\n",
393394 session_id, ret);
394395 } else if (msg_out.header.status != 0) {
395− if (is_fw_err_platform_config(msg_out.header.status)) {
396+ if (is_fw_err_platform_config(pxp, msg_out.header.status)) {
396397 drm_info_once(&i915->drm,
397398 "PXP inv-stream-key-%u failed due to BIOS/SOC :0x%08x:%s\n",
398399 session_id, msg_out.header.status,
drivers/gpu/drm/i915/pxp/intel_pxp_types.h+9−0
@@ -26,6 +26,15 @@ struct intel_pxp { · 25 unmodified lines
2626 */
2727 struct intel_gt *ctrl_gt;
2828
29+ /**
30+ * @platform_cfg_is_bad: used to track if any prior arb session creation resulted
31+ * in a failure that was caused by a platform configuration issue, meaning that
32+ * failure will not get resolved without a change to the platform (not kernel)
33+ * such as BIOS configuration, firwmware update, etc. This bool gets reflected when
34+ * GET_PARAM:I915_PARAM_PXP_STATUS is called.
35+ */
36+ bool platform_cfg_is_bad;
37+
2938 /**
3039 * @kcr_base: base mmio offset for the KCR engine which is different on legacy platforms
3140 * vs newer platforms where the KCR is inside the media-tile.
drivers/gpu/drm/i915/selftests/mock_gem_device.c+2−0
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void) · 180 unmodified lines
181181 /* Set up device info and initial runtime info. */
182182 intel_device_info_driver_create(i915, pdev->device, &mock_info);
183183
184+ intel_display_device_probe(i915);
185+
184186 dev_pm_domain_set(&pdev->dev, &pm_domain);
185187 pm_runtime_enable(&pdev->dev);
186188 pm_runtime_dont_use_autosuspend(&pdev->dev);
drivers/gpu/drm/i915/soc/intel_pch.c+9−3
@@ -218,13 +218,19 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) · 217 unmodified lines
218218 unsigned short id;
219219 enum intel_pch pch_type;
220220
221− /* DG1 has south engine display on the same PCI device */
222− if (IS_DG1(dev_priv)) {
223− dev_priv->pch_type = PCH_DG1;
221+ /*
222+ * South display engine on the same PCI device: just assign the fake
223+ * PCH.
224+ */
225+ if (DISPLAY_VER(dev_priv) >= 20) {
226+ dev_priv->pch_type = PCH_LNL;
224227 return;
225228 } else if (IS_DG2(dev_priv)) {
226229 dev_priv->pch_type = PCH_DG2;
227230 return;
231+ } else if (IS_DG1(dev_priv)) {
232+ dev_priv->pch_type = PCH_DG1;
233+ return;
228234 }
229235
230236 /*
drivers/gpu/drm/i915/soc/intel_pch.h+2−0
@@ -30,6 +30,7 @@ enum intel_pch { · 29 unmodified lines
3030 /* Fake PCHs, functionality handled on the same PCI dev */
3131 PCH_DG1 = 1024,
3232 PCH_DG2,
33+ PCH_LNL,
3334 };
3435
3536 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -66,6 +67,7 @@ enum intel_pch { · 30 unmodified lines
6667
6768 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
6869 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
70+#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
6971 #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
7072 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
7173 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
drivers/media/cec/core/cec-adap.c+5−0
@@ -1688,6 +1688,11 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) · 1687 unmodified lines
16881688 }
16891689 EXPORT_SYMBOL_GPL(cec_s_phys_addr);
16901690
1691+/*
1692+ * Note: In the drm subsystem, prefer calling (if possible):
1693+ *
1694+ * cec_s_phys_addr(adap, connector->display_info.source_physical_address, false);
1695+ */
16911696 void cec_s_phys_addr_from_edid(struct cec_adapter *adap,
16921697 const struct edid *edid)
16931698 {
drivers/media/cec/core/cec-notifier.c+5−0
@@ -196,6 +196,11 @@ void cec_notifier_set_phys_addr(struct cec_notifier *n, u16 pa) · 195 unmodified lines
196196 }
197197 EXPORT_SYMBOL_GPL(cec_notifier_set_phys_addr);
198198
199+/*
200+ * Note: In the drm subsystem, prefer calling (if possible):
201+ *
202+ * cec_notifier_set_phys_addr(n, connector->display_info.source_physical_address);
203+ */
199204 void cec_notifier_set_phys_addr_from_edid(struct cec_notifier *n,
200205 const struct edid *edid)
201206 {
include/drm/display/drm_dp_helper.h+6−0
@@ -699,6 +699,7 @@ void drm_dp_cec_irq(struct drm_dp_aux *aux); · 698 unmodified lines
699699 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
700700 struct drm_connector *connector);
701701 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
702+void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address);
702703 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
703704 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
704705 #else
@@ -716,6 +717,11 @@ static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) · 11 unmodified lines
716717 {
717718 }
718719
720+static inline void drm_dp_cec_attach(struct drm_dp_aux *aux,
721+ u16 source_physical_address)
722+{
723+}
724+
719725 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
720726 const struct edid *edid)
721727 {
include/drm/drm_connector.h+8−0
@@ -817,6 +817,14 @@ struct drm_display_info { · 816 unmodified lines
817817 * @quirks: EDID based quirks. Internal to EDID parsing.
818818 */
819819 u32 quirks;
820+
821+ /**
822+ * @source_physical_address: Source Physical Address from HDMI
823+ * Vendor-Specific Data Block, for CEC usage.
824+ *
825+ * Defaults to CEC_PHYS_ADDR_INVALID (0xffff).
826+ */
827+ u16 source_physical_address;
820828 };
821829
822830 int drm_display_info_set_bus_formats(struct drm_display_info *info,
include/drm/drm_edid.h+1−0
@@ -612,6 +612,7 @@ const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, · 611 unmodified lines
612612 int drm_edid_connector_update(struct drm_connector *connector,
613613 const struct drm_edid *edid);
614614 int drm_edid_connector_add_modes(struct drm_connector *connector);
615+bool drm_edid_is_digital(const struct drm_edid *drm_edid);
615616
616617 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
617618 int ext_id, int *ext_index);
include/drm/i915_pciids.h+6−2
@@ -689,14 +689,18 @@ · 688 unmodified lines
689689 #define INTEL_RPLU_IDS(info) \
690690 INTEL_VGA_DEVICE(0xA721, info), \
691691 INTEL_VGA_DEVICE(0xA7A1, info), \
692− INTEL_VGA_DEVICE(0xA7A9, info)
692+ INTEL_VGA_DEVICE(0xA7A9, info), \
693+ INTEL_VGA_DEVICE(0xA7AC, info), \
694+ INTEL_VGA_DEVICE(0xA7AD, info)
693695
694696 /* RPL-P */
695697 #define INTEL_RPLP_IDS(info) \
696698 INTEL_RPLU_IDS(info), \
697699 INTEL_VGA_DEVICE(0xA720, info), \
698700 INTEL_VGA_DEVICE(0xA7A0, info), \
699− INTEL_VGA_DEVICE(0xA7A8, info)
701+ INTEL_VGA_DEVICE(0xA7A8, info), \
702+ INTEL_VGA_DEVICE(0xA7AA, info), \
703+ INTEL_VGA_DEVICE(0xA7AB, info)
700704
701705 /* DG2 */
702706 #define INTEL_DG2_G10_IDS(info) \

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